dp_tx.c 144 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include "qdf_module.h"
  30. #include <wlan_cfg.h>
  31. #include "dp_ipa.h"
  32. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  33. #include "if_meta_hdr.h"
  34. #endif
  35. #include "enet.h"
  36. #include "dp_internal.h"
  37. #ifdef ATH_SUPPORT_IQUE
  38. #include "dp_txrx_me.h"
  39. #endif
  40. #include "dp_hist.h"
  41. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  42. #include <dp_swlm.h>
  43. #endif
  44. #ifdef WIFI_MONITOR_SUPPORT
  45. #include <dp_mon.h>
  46. #endif
  47. #ifdef FEATURE_WDS
  48. #include "dp_txrx_wds.h"
  49. #endif
  50. /* Flag to skip CCE classify when mesh or tid override enabled */
  51. #define DP_TX_SKIP_CCE_CLASSIFY \
  52. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  53. /* TODO Add support in TSO */
  54. #define DP_DESC_NUM_FRAG(x) 0
  55. /* disable TQM_BYPASS */
  56. #define TQM_BYPASS_WAR 0
  57. /* invalid peer id for reinject*/
  58. #define DP_INVALID_PEER 0XFFFE
  59. #define DP_RETRY_COUNT 7
  60. /*mapping between hal encrypt type and cdp_sec_type*/
  61. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  62. HAL_TX_ENCRYPT_TYPE_WEP_128,
  63. HAL_TX_ENCRYPT_TYPE_WEP_104,
  64. HAL_TX_ENCRYPT_TYPE_WEP_40,
  65. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  66. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  67. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  68. HAL_TX_ENCRYPT_TYPE_WAPI,
  69. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  70. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  71. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  72. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  73. qdf_export_symbol(sec_type_map);
  74. #ifdef CONFIG_WLAN_SYSFS_MEM_STATS
  75. /**
  76. * dp_update_tx_desc_stats - Update the increase or decrease in
  77. * outstanding tx desc count
  78. * values on pdev and soc
  79. * @vdev: DP pdev handle
  80. *
  81. * Return: void
  82. */
  83. static inline void
  84. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  85. {
  86. int32_t tx_descs_cnt =
  87. qdf_atomic_read(&pdev->num_tx_outstanding);
  88. if (pdev->tx_descs_max < tx_descs_cnt)
  89. pdev->tx_descs_max = tx_descs_cnt;
  90. qdf_mem_tx_desc_cnt_update(pdev->num_tx_outstanding,
  91. pdev->tx_descs_max);
  92. }
  93. #else /* CONFIG_WLAN_SYSFS_MEM_STATS */
  94. static inline void
  95. dp_update_tx_desc_stats(struct dp_pdev *pdev)
  96. {
  97. }
  98. #endif /* CONFIG_WLAN_SYSFS_MEM_STATS */
  99. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  100. static inline
  101. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  102. {
  103. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  104. QDF_DMA_TO_DEVICE,
  105. desc->nbuf->len);
  106. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  107. }
  108. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  109. {
  110. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  111. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  112. QDF_DMA_TO_DEVICE,
  113. desc->nbuf->len);
  114. }
  115. #else
  116. static inline
  117. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  118. {
  119. }
  120. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  121. {
  122. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  123. QDF_DMA_TO_DEVICE, desc->nbuf->len);
  124. }
  125. #endif
  126. #ifdef QCA_TX_LIMIT_CHECK
  127. /**
  128. * dp_tx_limit_check - Check if allocated tx descriptors reached
  129. * soc max limit and pdev max limit
  130. * @vdev: DP vdev handle
  131. *
  132. * Return: true if allocated tx descriptors reached max configured value, else
  133. * false
  134. */
  135. static inline bool
  136. dp_tx_limit_check(struct dp_vdev *vdev)
  137. {
  138. struct dp_pdev *pdev = vdev->pdev;
  139. struct dp_soc *soc = pdev->soc;
  140. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  141. soc->num_tx_allowed) {
  142. dp_tx_info("queued packets are more than max tx, drop the frame");
  143. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  144. return true;
  145. }
  146. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  147. pdev->num_tx_allowed) {
  148. dp_tx_info("queued packets are more than max tx, drop the frame");
  149. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  150. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_outstand.num, 1);
  151. return true;
  152. }
  153. return false;
  154. }
  155. /**
  156. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  157. * reached soc max limit
  158. * @vdev: DP vdev handle
  159. *
  160. * Return: true if allocated tx descriptors reached max configured value, else
  161. * false
  162. */
  163. static inline bool
  164. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  165. {
  166. struct dp_pdev *pdev = vdev->pdev;
  167. struct dp_soc *soc = pdev->soc;
  168. if (qdf_atomic_read(&soc->num_tx_exception) >=
  169. soc->num_msdu_exception_desc) {
  170. dp_info("exc packets are more than max drop the exc pkt");
  171. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  172. return true;
  173. }
  174. return false;
  175. }
  176. /**
  177. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  178. * @vdev: DP pdev handle
  179. *
  180. * Return: void
  181. */
  182. static inline void
  183. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  184. {
  185. struct dp_soc *soc = pdev->soc;
  186. qdf_atomic_inc(&pdev->num_tx_outstanding);
  187. qdf_atomic_inc(&soc->num_tx_outstanding);
  188. dp_update_tx_desc_stats(pdev);
  189. }
  190. /**
  191. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  192. * @vdev: DP pdev handle
  193. *
  194. * Return: void
  195. */
  196. static inline void
  197. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  198. {
  199. struct dp_soc *soc = pdev->soc;
  200. qdf_atomic_dec(&pdev->num_tx_outstanding);
  201. qdf_atomic_dec(&soc->num_tx_outstanding);
  202. dp_update_tx_desc_stats(pdev);
  203. }
  204. #else //QCA_TX_LIMIT_CHECK
  205. static inline bool
  206. dp_tx_limit_check(struct dp_vdev *vdev)
  207. {
  208. return false;
  209. }
  210. static inline bool
  211. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  212. {
  213. return false;
  214. }
  215. static inline void
  216. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  217. {
  218. qdf_atomic_inc(&pdev->num_tx_outstanding);
  219. dp_update_tx_desc_stats(pdev);
  220. }
  221. static inline void
  222. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  223. {
  224. qdf_atomic_dec(&pdev->num_tx_outstanding);
  225. dp_update_tx_desc_stats(pdev);
  226. }
  227. #endif //QCA_TX_LIMIT_CHECK
  228. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  229. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  230. {
  231. enum dp_tx_event_type type;
  232. if (flags & DP_TX_DESC_FLAG_FLUSH)
  233. type = DP_TX_DESC_FLUSH;
  234. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  235. type = DP_TX_COMP_UNMAP_ERR;
  236. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  237. type = DP_TX_COMP_UNMAP;
  238. else
  239. type = DP_TX_DESC_UNMAP;
  240. return type;
  241. }
  242. static inline void
  243. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  244. qdf_nbuf_t skb, uint32_t sw_cookie,
  245. enum dp_tx_event_type type)
  246. {
  247. struct dp_tx_desc_event *entry;
  248. uint32_t idx;
  249. if (qdf_unlikely(!soc->tx_tcl_history || !soc->tx_comp_history))
  250. return;
  251. switch (type) {
  252. case DP_TX_COMP_UNMAP:
  253. case DP_TX_COMP_UNMAP_ERR:
  254. case DP_TX_COMP_MSDU_EXT:
  255. idx = dp_history_get_next_index(&soc->tx_comp_history->index,
  256. DP_TX_COMP_HISTORY_SIZE);
  257. entry = &soc->tx_comp_history->entry[idx];
  258. break;
  259. case DP_TX_DESC_MAP:
  260. case DP_TX_DESC_UNMAP:
  261. case DP_TX_DESC_COOKIE:
  262. case DP_TX_DESC_FLUSH:
  263. idx = dp_history_get_next_index(&soc->tx_tcl_history->index,
  264. DP_TX_TCL_HISTORY_SIZE);
  265. entry = &soc->tx_tcl_history->entry[idx];
  266. break;
  267. default:
  268. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  269. return;
  270. }
  271. entry->skb = skb;
  272. entry->paddr = paddr;
  273. entry->sw_cookie = sw_cookie;
  274. entry->type = type;
  275. entry->ts = qdf_get_log_timestamp();
  276. }
  277. static inline void
  278. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  279. struct qdf_tso_seg_elem_t *tso_seg,
  280. qdf_nbuf_t skb, uint32_t sw_cookie,
  281. enum dp_tx_event_type type)
  282. {
  283. int i;
  284. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  285. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  286. skb, sw_cookie, type);
  287. }
  288. if (!tso_seg->next)
  289. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  290. skb, 0xFFFFFFFF, type);
  291. }
  292. static inline void
  293. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  294. qdf_nbuf_t skb, uint32_t sw_cookie,
  295. enum dp_tx_event_type type)
  296. {
  297. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  298. uint32_t num_segs = tso_info.num_segs;
  299. while (num_segs) {
  300. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  301. curr_seg = curr_seg->next;
  302. num_segs--;
  303. }
  304. }
  305. #else
  306. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  307. {
  308. return DP_TX_DESC_INVAL_EVT;
  309. }
  310. static inline void
  311. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  312. qdf_nbuf_t skb, uint32_t sw_cookie,
  313. enum dp_tx_event_type type)
  314. {
  315. }
  316. static inline void
  317. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  318. struct qdf_tso_seg_elem_t *tso_seg,
  319. qdf_nbuf_t skb, uint32_t sw_cookie,
  320. enum dp_tx_event_type type)
  321. {
  322. }
  323. static inline void
  324. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  325. qdf_nbuf_t skb, uint32_t sw_cookie,
  326. enum dp_tx_event_type type)
  327. {
  328. }
  329. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  330. #if defined(FEATURE_TSO)
  331. /**
  332. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  333. *
  334. * @soc - core txrx main context
  335. * @seg_desc - tso segment descriptor
  336. * @num_seg_desc - tso number segment descriptor
  337. */
  338. static void dp_tx_tso_unmap_segment(
  339. struct dp_soc *soc,
  340. struct qdf_tso_seg_elem_t *seg_desc,
  341. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  342. {
  343. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  344. if (qdf_unlikely(!seg_desc)) {
  345. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  346. __func__, __LINE__);
  347. qdf_assert(0);
  348. } else if (qdf_unlikely(!num_seg_desc)) {
  349. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  350. __func__, __LINE__);
  351. qdf_assert(0);
  352. } else {
  353. bool is_last_seg;
  354. /* no tso segment left to do dma unmap */
  355. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  356. return;
  357. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  358. true : false;
  359. qdf_nbuf_unmap_tso_segment(soc->osdev,
  360. seg_desc, is_last_seg);
  361. num_seg_desc->num_seg.tso_cmn_num_seg--;
  362. }
  363. }
  364. /**
  365. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  366. * back to the freelist
  367. *
  368. * @soc - soc device handle
  369. * @tx_desc - Tx software descriptor
  370. */
  371. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  372. struct dp_tx_desc_s *tx_desc)
  373. {
  374. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  375. if (qdf_unlikely(!tx_desc->tso_desc)) {
  376. dp_tx_err("SO desc is NULL!");
  377. qdf_assert(0);
  378. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  379. dp_tx_err("TSO num desc is NULL!");
  380. qdf_assert(0);
  381. } else {
  382. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  383. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  384. /* Add the tso num segment into the free list */
  385. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  386. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  387. tx_desc->tso_num_desc);
  388. tx_desc->tso_num_desc = NULL;
  389. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  390. }
  391. /* Add the tso segment into the free list*/
  392. dp_tx_tso_desc_free(soc,
  393. tx_desc->pool_id, tx_desc->tso_desc);
  394. tx_desc->tso_desc = NULL;
  395. }
  396. }
  397. #else
  398. static void dp_tx_tso_unmap_segment(
  399. struct dp_soc *soc,
  400. struct qdf_tso_seg_elem_t *seg_desc,
  401. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  402. {
  403. }
  404. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  405. struct dp_tx_desc_s *tx_desc)
  406. {
  407. }
  408. #endif
  409. /**
  410. * dp_tx_desc_release() - Release Tx Descriptor
  411. * @tx_desc : Tx Descriptor
  412. * @desc_pool_id: Descriptor Pool ID
  413. *
  414. * Deallocate all resources attached to Tx descriptor and free the Tx
  415. * descriptor.
  416. *
  417. * Return:
  418. */
  419. static void
  420. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  421. {
  422. struct dp_pdev *pdev = tx_desc->pdev;
  423. struct dp_soc *soc;
  424. uint8_t comp_status = 0;
  425. qdf_assert(pdev);
  426. soc = pdev->soc;
  427. dp_tx_outstanding_dec(pdev);
  428. if (tx_desc->frm_type == dp_tx_frm_tso)
  429. dp_tx_tso_desc_release(soc, tx_desc);
  430. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  431. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  432. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  433. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  434. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  435. qdf_atomic_dec(&soc->num_tx_exception);
  436. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  437. tx_desc->buffer_src)
  438. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  439. soc->hal_soc);
  440. else
  441. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  442. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  443. tx_desc->id, comp_status,
  444. qdf_atomic_read(&pdev->num_tx_outstanding));
  445. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  446. return;
  447. }
  448. /**
  449. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  450. * @vdev: DP vdev Handle
  451. * @nbuf: skb
  452. * @msdu_info: msdu_info required to create HTT metadata
  453. *
  454. * Prepares and fills HTT metadata in the frame pre-header for special frames
  455. * that should be transmitted using varying transmit parameters.
  456. * There are 2 VDEV modes that currently needs this special metadata -
  457. * 1) Mesh Mode
  458. * 2) DSRC Mode
  459. *
  460. * Return: HTT metadata size
  461. *
  462. */
  463. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  464. struct dp_tx_msdu_info_s *msdu_info)
  465. {
  466. uint32_t *meta_data = msdu_info->meta_data;
  467. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  468. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  469. uint8_t htt_desc_size;
  470. /* Size rounded of multiple of 8 bytes */
  471. uint8_t htt_desc_size_aligned;
  472. uint8_t *hdr = NULL;
  473. /*
  474. * Metadata - HTT MSDU Extension header
  475. */
  476. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  477. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  478. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  479. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  480. meta_data[0])) {
  481. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  482. htt_desc_size_aligned)) {
  483. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  484. htt_desc_size_aligned);
  485. if (!nbuf) {
  486. /*
  487. * qdf_nbuf_realloc_headroom won't do skb_clone
  488. * as skb_realloc_headroom does. so, no free is
  489. * needed here.
  490. */
  491. DP_STATS_INC(vdev,
  492. tx_i.dropped.headroom_insufficient,
  493. 1);
  494. qdf_print(" %s[%d] skb_realloc_headroom failed",
  495. __func__, __LINE__);
  496. return 0;
  497. }
  498. }
  499. /* Fill and add HTT metaheader */
  500. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  501. if (!hdr) {
  502. dp_tx_err("Error in filling HTT metadata");
  503. return 0;
  504. }
  505. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  506. } else if (vdev->opmode == wlan_op_mode_ocb) {
  507. /* Todo - Add support for DSRC */
  508. }
  509. return htt_desc_size_aligned;
  510. }
  511. /**
  512. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  513. * @tso_seg: TSO segment to process
  514. * @ext_desc: Pointer to MSDU extension descriptor
  515. *
  516. * Return: void
  517. */
  518. #if defined(FEATURE_TSO)
  519. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  520. void *ext_desc)
  521. {
  522. uint8_t num_frag;
  523. uint32_t tso_flags;
  524. /*
  525. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  526. * tcp_flag_mask
  527. *
  528. * Checksum enable flags are set in TCL descriptor and not in Extension
  529. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  530. */
  531. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  532. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  533. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  534. tso_seg->tso_flags.ip_len);
  535. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  536. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  537. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  538. uint32_t lo = 0;
  539. uint32_t hi = 0;
  540. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  541. (tso_seg->tso_frags[num_frag].length));
  542. qdf_dmaaddr_to_32s(
  543. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  544. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  545. tso_seg->tso_frags[num_frag].length);
  546. }
  547. return;
  548. }
  549. #else
  550. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  551. void *ext_desc)
  552. {
  553. return;
  554. }
  555. #endif
  556. #if defined(FEATURE_TSO)
  557. /**
  558. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  559. * allocated and free them
  560. *
  561. * @soc: soc handle
  562. * @free_seg: list of tso segments
  563. * @msdu_info: msdu descriptor
  564. *
  565. * Return - void
  566. */
  567. static void dp_tx_free_tso_seg_list(
  568. struct dp_soc *soc,
  569. struct qdf_tso_seg_elem_t *free_seg,
  570. struct dp_tx_msdu_info_s *msdu_info)
  571. {
  572. struct qdf_tso_seg_elem_t *next_seg;
  573. while (free_seg) {
  574. next_seg = free_seg->next;
  575. dp_tx_tso_desc_free(soc,
  576. msdu_info->tx_queue.desc_pool_id,
  577. free_seg);
  578. free_seg = next_seg;
  579. }
  580. }
  581. /**
  582. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  583. * allocated and free them
  584. *
  585. * @soc: soc handle
  586. * @free_num_seg: list of tso number segments
  587. * @msdu_info: msdu descriptor
  588. * Return - void
  589. */
  590. static void dp_tx_free_tso_num_seg_list(
  591. struct dp_soc *soc,
  592. struct qdf_tso_num_seg_elem_t *free_num_seg,
  593. struct dp_tx_msdu_info_s *msdu_info)
  594. {
  595. struct qdf_tso_num_seg_elem_t *next_num_seg;
  596. while (free_num_seg) {
  597. next_num_seg = free_num_seg->next;
  598. dp_tso_num_seg_free(soc,
  599. msdu_info->tx_queue.desc_pool_id,
  600. free_num_seg);
  601. free_num_seg = next_num_seg;
  602. }
  603. }
  604. /**
  605. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  606. * do dma unmap for each segment
  607. *
  608. * @soc: soc handle
  609. * @free_seg: list of tso segments
  610. * @num_seg_desc: tso number segment descriptor
  611. *
  612. * Return - void
  613. */
  614. static void dp_tx_unmap_tso_seg_list(
  615. struct dp_soc *soc,
  616. struct qdf_tso_seg_elem_t *free_seg,
  617. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  618. {
  619. struct qdf_tso_seg_elem_t *next_seg;
  620. if (qdf_unlikely(!num_seg_desc)) {
  621. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  622. return;
  623. }
  624. while (free_seg) {
  625. next_seg = free_seg->next;
  626. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  627. free_seg = next_seg;
  628. }
  629. }
  630. #ifdef FEATURE_TSO_STATS
  631. /**
  632. * dp_tso_get_stats_idx: Retrieve the tso packet id
  633. * @pdev - pdev handle
  634. *
  635. * Return: id
  636. */
  637. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  638. {
  639. uint32_t stats_idx;
  640. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  641. % CDP_MAX_TSO_PACKETS);
  642. return stats_idx;
  643. }
  644. #else
  645. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  646. {
  647. return 0;
  648. }
  649. #endif /* FEATURE_TSO_STATS */
  650. /**
  651. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  652. * free the tso segments descriptor and
  653. * tso num segments descriptor
  654. *
  655. * @soc: soc handle
  656. * @msdu_info: msdu descriptor
  657. * @tso_seg_unmap: flag to show if dma unmap is necessary
  658. *
  659. * Return - void
  660. */
  661. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  662. struct dp_tx_msdu_info_s *msdu_info,
  663. bool tso_seg_unmap)
  664. {
  665. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  666. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  667. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  668. tso_info->tso_num_seg_list;
  669. /* do dma unmap for each segment */
  670. if (tso_seg_unmap)
  671. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  672. /* free all tso number segment descriptor though looks only have 1 */
  673. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  674. /* free all tso segment descriptor */
  675. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  676. }
  677. /**
  678. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  679. * @vdev: virtual device handle
  680. * @msdu: network buffer
  681. * @msdu_info: meta data associated with the msdu
  682. *
  683. * Return: QDF_STATUS_SUCCESS success
  684. */
  685. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  686. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  687. {
  688. struct qdf_tso_seg_elem_t *tso_seg;
  689. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  690. struct dp_soc *soc = vdev->pdev->soc;
  691. struct dp_pdev *pdev = vdev->pdev;
  692. struct qdf_tso_info_t *tso_info;
  693. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  694. tso_info = &msdu_info->u.tso_info;
  695. tso_info->curr_seg = NULL;
  696. tso_info->tso_seg_list = NULL;
  697. tso_info->num_segs = num_seg;
  698. msdu_info->frm_type = dp_tx_frm_tso;
  699. tso_info->tso_num_seg_list = NULL;
  700. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  701. while (num_seg) {
  702. tso_seg = dp_tx_tso_desc_alloc(
  703. soc, msdu_info->tx_queue.desc_pool_id);
  704. if (tso_seg) {
  705. tso_seg->next = tso_info->tso_seg_list;
  706. tso_info->tso_seg_list = tso_seg;
  707. num_seg--;
  708. } else {
  709. dp_err_rl("Failed to alloc tso seg desc");
  710. DP_STATS_INC_PKT(vdev->pdev,
  711. tso_stats.tso_no_mem_dropped, 1,
  712. qdf_nbuf_len(msdu));
  713. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  714. return QDF_STATUS_E_NOMEM;
  715. }
  716. }
  717. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  718. tso_num_seg = dp_tso_num_seg_alloc(soc,
  719. msdu_info->tx_queue.desc_pool_id);
  720. if (tso_num_seg) {
  721. tso_num_seg->next = tso_info->tso_num_seg_list;
  722. tso_info->tso_num_seg_list = tso_num_seg;
  723. } else {
  724. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  725. __func__);
  726. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  727. return QDF_STATUS_E_NOMEM;
  728. }
  729. msdu_info->num_seg =
  730. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  731. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  732. msdu_info->num_seg);
  733. if (!(msdu_info->num_seg)) {
  734. /*
  735. * Free allocated TSO seg desc and number seg desc,
  736. * do unmap for segments if dma map has done.
  737. */
  738. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  739. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  740. return QDF_STATUS_E_INVAL;
  741. }
  742. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  743. msdu, 0, DP_TX_DESC_MAP);
  744. tso_info->curr_seg = tso_info->tso_seg_list;
  745. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  746. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  747. msdu, msdu_info->num_seg);
  748. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  749. tso_info->msdu_stats_idx);
  750. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  751. return QDF_STATUS_SUCCESS;
  752. }
  753. #else
  754. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  755. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  756. {
  757. return QDF_STATUS_E_NOMEM;
  758. }
  759. #endif
  760. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  761. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  762. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  763. /**
  764. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  765. * @vdev: DP Vdev handle
  766. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  767. * @desc_pool_id: Descriptor Pool ID
  768. *
  769. * Return:
  770. */
  771. static
  772. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  773. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  774. {
  775. uint8_t i;
  776. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  777. struct dp_tx_seg_info_s *seg_info;
  778. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  779. struct dp_soc *soc = vdev->pdev->soc;
  780. /* Allocate an extension descriptor */
  781. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  782. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  783. if (!msdu_ext_desc) {
  784. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  785. return NULL;
  786. }
  787. if (msdu_info->exception_fw &&
  788. qdf_unlikely(vdev->mesh_vdev)) {
  789. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  790. &msdu_info->meta_data[0],
  791. sizeof(struct htt_tx_msdu_desc_ext2_t));
  792. qdf_atomic_inc(&soc->num_tx_exception);
  793. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  794. }
  795. switch (msdu_info->frm_type) {
  796. case dp_tx_frm_sg:
  797. case dp_tx_frm_me:
  798. case dp_tx_frm_raw:
  799. seg_info = msdu_info->u.sg_info.curr_seg;
  800. /* Update the buffer pointers in MSDU Extension Descriptor */
  801. for (i = 0; i < seg_info->frag_cnt; i++) {
  802. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  803. seg_info->frags[i].paddr_lo,
  804. seg_info->frags[i].paddr_hi,
  805. seg_info->frags[i].len);
  806. }
  807. break;
  808. case dp_tx_frm_tso:
  809. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  810. &cached_ext_desc[0]);
  811. break;
  812. default:
  813. break;
  814. }
  815. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  816. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  817. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  818. msdu_ext_desc->vaddr);
  819. return msdu_ext_desc;
  820. }
  821. /**
  822. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  823. *
  824. * @skb: skb to be traced
  825. * @msdu_id: msdu_id of the packet
  826. * @vdev_id: vdev_id of the packet
  827. *
  828. * Return: None
  829. */
  830. #ifdef DP_DISABLE_TX_PKT_TRACE
  831. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  832. uint8_t vdev_id)
  833. {
  834. }
  835. #else
  836. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  837. uint8_t vdev_id)
  838. {
  839. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  840. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  841. DPTRACE(qdf_dp_trace_ptr(skb,
  842. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  843. QDF_TRACE_DEFAULT_PDEV_ID,
  844. qdf_nbuf_data_addr(skb),
  845. sizeof(qdf_nbuf_data(skb)),
  846. msdu_id, vdev_id, 0));
  847. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  848. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  849. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  850. msdu_id, QDF_TX));
  851. }
  852. #endif
  853. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  854. /**
  855. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  856. * exception by the upper layer (OS_IF)
  857. * @soc: DP soc handle
  858. * @nbuf: packet to be transmitted
  859. *
  860. * Returns: 1 if the packet is marked as exception,
  861. * 0, if the packet is not marked as exception.
  862. */
  863. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  864. qdf_nbuf_t nbuf)
  865. {
  866. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  867. }
  868. #else
  869. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  870. qdf_nbuf_t nbuf)
  871. {
  872. return 0;
  873. }
  874. #endif
  875. /**
  876. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  877. * @vdev: DP vdev handle
  878. * @nbuf: skb
  879. * @desc_pool_id: Descriptor pool ID
  880. * @meta_data: Metadata to the fw
  881. * @tx_exc_metadata: Handle that holds exception path metadata
  882. * Allocate and prepare Tx descriptor with msdu information.
  883. *
  884. * Return: Pointer to Tx Descriptor on success,
  885. * NULL on failure
  886. */
  887. static
  888. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  889. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  890. struct dp_tx_msdu_info_s *msdu_info,
  891. struct cdp_tx_exception_metadata *tx_exc_metadata)
  892. {
  893. uint8_t align_pad;
  894. uint8_t is_exception = 0;
  895. uint8_t htt_hdr_size;
  896. struct dp_tx_desc_s *tx_desc;
  897. struct dp_pdev *pdev = vdev->pdev;
  898. struct dp_soc *soc = pdev->soc;
  899. if (dp_tx_limit_check(vdev))
  900. return NULL;
  901. /* Allocate software Tx descriptor */
  902. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  903. if (qdf_unlikely(!tx_desc)) {
  904. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  905. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  906. return NULL;
  907. }
  908. dp_tx_outstanding_inc(pdev);
  909. /* Initialize the SW tx descriptor */
  910. tx_desc->nbuf = nbuf;
  911. tx_desc->frm_type = dp_tx_frm_std;
  912. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  913. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  914. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  915. tx_desc->vdev_id = vdev->vdev_id;
  916. tx_desc->pdev = pdev;
  917. tx_desc->msdu_ext_desc = NULL;
  918. tx_desc->pkt_offset = 0;
  919. tx_desc->length = qdf_nbuf_headlen(nbuf);
  920. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  921. if (qdf_unlikely(vdev->multipass_en)) {
  922. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  923. goto failure;
  924. }
  925. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  926. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  927. is_exception = 1;
  928. /*
  929. * For special modes (vdev_type == ocb or mesh), data frames should be
  930. * transmitted using varying transmit parameters (tx spec) which include
  931. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  932. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  933. * These frames are sent as exception packets to firmware.
  934. *
  935. * HW requirement is that metadata should always point to a
  936. * 8-byte aligned address. So we add alignment pad to start of buffer.
  937. * HTT Metadata should be ensured to be multiple of 8-bytes,
  938. * to get 8-byte aligned start address along with align_pad added
  939. *
  940. * |-----------------------------|
  941. * | |
  942. * |-----------------------------| <-----Buffer Pointer Address given
  943. * | | ^ in HW descriptor (aligned)
  944. * | HTT Metadata | |
  945. * | | |
  946. * | | | Packet Offset given in descriptor
  947. * | | |
  948. * |-----------------------------| |
  949. * | Alignment Pad | v
  950. * |-----------------------------| <----- Actual buffer start address
  951. * | SKB Data | (Unaligned)
  952. * | |
  953. * | |
  954. * | |
  955. * | |
  956. * | |
  957. * |-----------------------------|
  958. */
  959. if (qdf_unlikely((msdu_info->exception_fw)) ||
  960. (vdev->opmode == wlan_op_mode_ocb) ||
  961. (tx_exc_metadata &&
  962. tx_exc_metadata->is_tx_sniffer)) {
  963. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  964. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  965. DP_STATS_INC(vdev,
  966. tx_i.dropped.headroom_insufficient, 1);
  967. goto failure;
  968. }
  969. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  970. dp_tx_err("qdf_nbuf_push_head failed");
  971. goto failure;
  972. }
  973. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  974. msdu_info);
  975. if (htt_hdr_size == 0)
  976. goto failure;
  977. tx_desc->length = qdf_nbuf_headlen(nbuf);
  978. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  979. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  980. is_exception = 1;
  981. tx_desc->length -= tx_desc->pkt_offset;
  982. }
  983. #if !TQM_BYPASS_WAR
  984. if (is_exception || tx_exc_metadata)
  985. #endif
  986. {
  987. /* Temporary WAR due to TQM VP issues */
  988. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  989. qdf_atomic_inc(&soc->num_tx_exception);
  990. }
  991. return tx_desc;
  992. failure:
  993. dp_tx_desc_release(tx_desc, desc_pool_id);
  994. return NULL;
  995. }
  996. /**
  997. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  998. * @vdev: DP vdev handle
  999. * @nbuf: skb
  1000. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1001. * @desc_pool_id : Descriptor Pool ID
  1002. *
  1003. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1004. * information. For frames wth fragments, allocate and prepare
  1005. * an MSDU extension descriptor
  1006. *
  1007. * Return: Pointer to Tx Descriptor on success,
  1008. * NULL on failure
  1009. */
  1010. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1011. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1012. uint8_t desc_pool_id)
  1013. {
  1014. struct dp_tx_desc_s *tx_desc;
  1015. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1016. struct dp_pdev *pdev = vdev->pdev;
  1017. struct dp_soc *soc = pdev->soc;
  1018. if (dp_tx_limit_check(vdev))
  1019. return NULL;
  1020. /* Allocate software Tx descriptor */
  1021. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1022. if (!tx_desc) {
  1023. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1024. return NULL;
  1025. }
  1026. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1027. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1028. dp_tx_outstanding_inc(pdev);
  1029. /* Initialize the SW tx descriptor */
  1030. tx_desc->nbuf = nbuf;
  1031. tx_desc->frm_type = msdu_info->frm_type;
  1032. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1033. tx_desc->vdev_id = vdev->vdev_id;
  1034. tx_desc->pdev = pdev;
  1035. tx_desc->pkt_offset = 0;
  1036. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1037. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1038. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  1039. /* Handle scattered frames - TSO/SG/ME */
  1040. /* Allocate and prepare an extension descriptor for scattered frames */
  1041. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1042. if (!msdu_ext_desc) {
  1043. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1044. goto failure;
  1045. }
  1046. #if TQM_BYPASS_WAR
  1047. /* Temporary WAR due to TQM VP issues */
  1048. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1049. qdf_atomic_inc(&soc->num_tx_exception);
  1050. #endif
  1051. if (qdf_unlikely(msdu_info->exception_fw))
  1052. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1053. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1054. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1055. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1056. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1057. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1058. else
  1059. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1060. return tx_desc;
  1061. failure:
  1062. dp_tx_desc_release(tx_desc, desc_pool_id);
  1063. return NULL;
  1064. }
  1065. /**
  1066. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1067. * @vdev: DP vdev handle
  1068. * @nbuf: buffer pointer
  1069. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1070. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1071. * descriptor
  1072. *
  1073. * Return:
  1074. */
  1075. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1076. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1077. {
  1078. qdf_nbuf_t curr_nbuf = NULL;
  1079. uint16_t total_len = 0;
  1080. qdf_dma_addr_t paddr;
  1081. int32_t i;
  1082. int32_t mapped_buf_num = 0;
  1083. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1084. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1085. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1086. /* Continue only if frames are of DATA type */
  1087. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1088. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1089. dp_tx_debug("Pkt. recd is of not data type");
  1090. goto error;
  1091. }
  1092. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1093. if (vdev->raw_mode_war &&
  1094. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1095. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1096. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1097. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1098. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1099. /*
  1100. * Number of nbuf's must not exceed the size of the frags
  1101. * array in seg_info.
  1102. */
  1103. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1104. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1105. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1106. goto error;
  1107. }
  1108. if (QDF_STATUS_SUCCESS !=
  1109. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1110. curr_nbuf,
  1111. QDF_DMA_TO_DEVICE,
  1112. curr_nbuf->len)) {
  1113. dp_tx_err("%s dma map error ", __func__);
  1114. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1115. goto error;
  1116. }
  1117. /* Update the count of mapped nbuf's */
  1118. mapped_buf_num++;
  1119. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1120. seg_info->frags[i].paddr_lo = paddr;
  1121. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1122. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1123. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1124. total_len += qdf_nbuf_len(curr_nbuf);
  1125. }
  1126. seg_info->frag_cnt = i;
  1127. seg_info->total_len = total_len;
  1128. seg_info->next = NULL;
  1129. sg_info->curr_seg = seg_info;
  1130. msdu_info->frm_type = dp_tx_frm_raw;
  1131. msdu_info->num_seg = 1;
  1132. return nbuf;
  1133. error:
  1134. i = 0;
  1135. while (nbuf) {
  1136. curr_nbuf = nbuf;
  1137. if (i < mapped_buf_num) {
  1138. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1139. QDF_DMA_TO_DEVICE,
  1140. curr_nbuf->len);
  1141. i++;
  1142. }
  1143. nbuf = qdf_nbuf_next(nbuf);
  1144. qdf_nbuf_free(curr_nbuf);
  1145. }
  1146. return NULL;
  1147. }
  1148. /**
  1149. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1150. * @soc: DP soc handle
  1151. * @nbuf: Buffer pointer
  1152. *
  1153. * unmap the chain of nbufs that belong to this RAW frame.
  1154. *
  1155. * Return: None
  1156. */
  1157. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1158. qdf_nbuf_t nbuf)
  1159. {
  1160. qdf_nbuf_t cur_nbuf = nbuf;
  1161. do {
  1162. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1163. QDF_DMA_TO_DEVICE,
  1164. cur_nbuf->len);
  1165. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1166. } while (cur_nbuf);
  1167. }
  1168. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1169. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1170. qdf_nbuf_t nbuf)
  1171. {
  1172. qdf_nbuf_t nbuf_local;
  1173. struct dp_vdev *vdev_local = vdev_hdl;
  1174. do {
  1175. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1176. break;
  1177. nbuf_local = nbuf;
  1178. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1179. htt_cmn_pkt_type_raw))
  1180. break;
  1181. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1182. break;
  1183. else if (qdf_nbuf_is_tso((nbuf_local)))
  1184. break;
  1185. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1186. (nbuf_local),
  1187. NULL, 1, 0);
  1188. } while (0);
  1189. }
  1190. #endif
  1191. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1192. /**
  1193. * dp_tx_update_stats() - Update soc level tx stats
  1194. * @soc: DP soc handle
  1195. * @nbuf: packet being transmitted
  1196. *
  1197. * Returns: none
  1198. */
  1199. void dp_tx_update_stats(struct dp_soc *soc,
  1200. qdf_nbuf_t nbuf)
  1201. {
  1202. DP_STATS_INC_PKT(soc, tx.egress, 1, qdf_nbuf_len(nbuf));
  1203. }
  1204. int
  1205. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1206. struct dp_tx_desc_s *tx_desc,
  1207. uint8_t tid)
  1208. {
  1209. struct dp_swlm *swlm = &soc->swlm;
  1210. union swlm_data swlm_query_data;
  1211. struct dp_swlm_tcl_data tcl_data;
  1212. QDF_STATUS status;
  1213. int ret;
  1214. if (qdf_unlikely(!swlm->is_enabled))
  1215. return 0;
  1216. tcl_data.nbuf = tx_desc->nbuf;
  1217. tcl_data.tid = tid;
  1218. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1219. swlm_query_data.tcl_data = &tcl_data;
  1220. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1221. if (QDF_IS_STATUS_ERROR(status)) {
  1222. dp_swlm_tcl_reset_session_data(soc);
  1223. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1224. return 0;
  1225. }
  1226. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1227. if (ret) {
  1228. DP_STATS_INC(swlm, tcl.coalesce_success, 1);
  1229. } else {
  1230. DP_STATS_INC(swlm, tcl.coalesce_fail, 1);
  1231. }
  1232. return ret;
  1233. }
  1234. void
  1235. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1236. int coalesce)
  1237. {
  1238. if (coalesce)
  1239. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1240. else
  1241. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1242. }
  1243. #endif
  1244. #ifdef FEATURE_RUNTIME_PM
  1245. /**
  1246. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1247. * @soc: Datapath soc handle
  1248. * @hal_ring_hdl: HAL ring handle
  1249. * @coalesce: Coalesce the current write or not
  1250. *
  1251. * Wrapper for HAL ring access end for data transmission for
  1252. * FEATURE_RUNTIME_PM
  1253. *
  1254. * Returns: none
  1255. */
  1256. void
  1257. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1258. hal_ring_handle_t hal_ring_hdl,
  1259. int coalesce)
  1260. {
  1261. int ret;
  1262. ret = hif_pm_runtime_get(soc->hif_handle,
  1263. RTPM_ID_DW_TX_HW_ENQUEUE, true);
  1264. switch (ret) {
  1265. case 0:
  1266. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1267. hif_pm_runtime_put(soc->hif_handle,
  1268. RTPM_ID_DW_TX_HW_ENQUEUE);
  1269. break;
  1270. /*
  1271. * If hif_pm_runtime_get returns -EBUSY or -EINPROGRESS,
  1272. * take the dp runtime refcount using dp_runtime_get,
  1273. * check link state,if up, write TX ring HP, else just set flush event.
  1274. * In dp_runtime_resume, wait until dp runtime refcount becomes
  1275. * zero or time out, then flush pending tx.
  1276. */
  1277. case -EBUSY:
  1278. case -EINPROGRESS:
  1279. dp_runtime_get(soc);
  1280. if (hif_pm_get_link_state(soc->hif_handle) ==
  1281. HIF_PM_LINK_STATE_UP) {
  1282. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1283. } else {
  1284. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1285. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1286. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1287. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1288. }
  1289. dp_runtime_put(soc);
  1290. break;
  1291. default:
  1292. dp_runtime_get(soc);
  1293. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1294. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1295. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1296. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1297. dp_runtime_put(soc);
  1298. }
  1299. }
  1300. #endif
  1301. /**
  1302. * dp_cce_classify() - Classify the frame based on CCE rules
  1303. * @vdev: DP vdev handle
  1304. * @nbuf: skb
  1305. *
  1306. * Classify frames based on CCE rules
  1307. * Return: bool( true if classified,
  1308. * else false)
  1309. */
  1310. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1311. {
  1312. qdf_ether_header_t *eh = NULL;
  1313. uint16_t ether_type;
  1314. qdf_llc_t *llcHdr;
  1315. qdf_nbuf_t nbuf_clone = NULL;
  1316. qdf_dot3_qosframe_t *qos_wh = NULL;
  1317. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1318. /*
  1319. * In case of mesh packets or hlos tid override enabled,
  1320. * don't do any classification
  1321. */
  1322. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1323. & DP_TX_SKIP_CCE_CLASSIFY))
  1324. return false;
  1325. }
  1326. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1327. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1328. ether_type = eh->ether_type;
  1329. llcHdr = (qdf_llc_t *)(nbuf->data +
  1330. sizeof(qdf_ether_header_t));
  1331. } else {
  1332. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1333. /* For encrypted packets don't do any classification */
  1334. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1335. return false;
  1336. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1337. if (qdf_unlikely(
  1338. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1339. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1340. ether_type = *(uint16_t *)(nbuf->data
  1341. + QDF_IEEE80211_4ADDR_HDR_LEN
  1342. + sizeof(qdf_llc_t)
  1343. - sizeof(ether_type));
  1344. llcHdr = (qdf_llc_t *)(nbuf->data +
  1345. QDF_IEEE80211_4ADDR_HDR_LEN);
  1346. } else {
  1347. ether_type = *(uint16_t *)(nbuf->data
  1348. + QDF_IEEE80211_3ADDR_HDR_LEN
  1349. + sizeof(qdf_llc_t)
  1350. - sizeof(ether_type));
  1351. llcHdr = (qdf_llc_t *)(nbuf->data +
  1352. QDF_IEEE80211_3ADDR_HDR_LEN);
  1353. }
  1354. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1355. && (ether_type ==
  1356. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1357. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1358. return true;
  1359. }
  1360. }
  1361. return false;
  1362. }
  1363. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1364. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1365. sizeof(*llcHdr));
  1366. nbuf_clone = qdf_nbuf_clone(nbuf);
  1367. if (qdf_unlikely(nbuf_clone)) {
  1368. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1369. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1370. qdf_nbuf_pull_head(nbuf_clone,
  1371. sizeof(qdf_net_vlanhdr_t));
  1372. }
  1373. }
  1374. } else {
  1375. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1376. nbuf_clone = qdf_nbuf_clone(nbuf);
  1377. if (qdf_unlikely(nbuf_clone)) {
  1378. qdf_nbuf_pull_head(nbuf_clone,
  1379. sizeof(qdf_net_vlanhdr_t));
  1380. }
  1381. }
  1382. }
  1383. if (qdf_unlikely(nbuf_clone))
  1384. nbuf = nbuf_clone;
  1385. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1386. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1387. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1388. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1389. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1390. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1391. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1392. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1393. if (qdf_unlikely(nbuf_clone))
  1394. qdf_nbuf_free(nbuf_clone);
  1395. return true;
  1396. }
  1397. if (qdf_unlikely(nbuf_clone))
  1398. qdf_nbuf_free(nbuf_clone);
  1399. return false;
  1400. }
  1401. /**
  1402. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1403. * @vdev: DP vdev handle
  1404. * @nbuf: skb
  1405. *
  1406. * Extract the DSCP or PCP information from frame and map into TID value.
  1407. *
  1408. * Return: void
  1409. */
  1410. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1411. struct dp_tx_msdu_info_s *msdu_info)
  1412. {
  1413. uint8_t tos = 0, dscp_tid_override = 0;
  1414. uint8_t *hdr_ptr, *L3datap;
  1415. uint8_t is_mcast = 0;
  1416. qdf_ether_header_t *eh = NULL;
  1417. qdf_ethervlan_header_t *evh = NULL;
  1418. uint16_t ether_type;
  1419. qdf_llc_t *llcHdr;
  1420. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1421. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1422. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1423. eh = (qdf_ether_header_t *)nbuf->data;
  1424. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1425. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1426. } else {
  1427. qdf_dot3_qosframe_t *qos_wh =
  1428. (qdf_dot3_qosframe_t *) nbuf->data;
  1429. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1430. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1431. return;
  1432. }
  1433. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1434. ether_type = eh->ether_type;
  1435. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1436. /*
  1437. * Check if packet is dot3 or eth2 type.
  1438. */
  1439. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1440. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1441. sizeof(*llcHdr));
  1442. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1443. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1444. sizeof(*llcHdr);
  1445. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1446. + sizeof(*llcHdr) +
  1447. sizeof(qdf_net_vlanhdr_t));
  1448. } else {
  1449. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1450. sizeof(*llcHdr);
  1451. }
  1452. } else {
  1453. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1454. evh = (qdf_ethervlan_header_t *) eh;
  1455. ether_type = evh->ether_type;
  1456. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1457. }
  1458. }
  1459. /*
  1460. * Find priority from IP TOS DSCP field
  1461. */
  1462. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1463. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1464. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1465. /* Only for unicast frames */
  1466. if (!is_mcast) {
  1467. /* send it on VO queue */
  1468. msdu_info->tid = DP_VO_TID;
  1469. }
  1470. } else {
  1471. /*
  1472. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1473. * from TOS byte.
  1474. */
  1475. tos = ip->ip_tos;
  1476. dscp_tid_override = 1;
  1477. }
  1478. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1479. /* TODO
  1480. * use flowlabel
  1481. *igmpmld cases to be handled in phase 2
  1482. */
  1483. unsigned long ver_pri_flowlabel;
  1484. unsigned long pri;
  1485. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1486. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1487. DP_IPV6_PRIORITY_SHIFT;
  1488. tos = pri;
  1489. dscp_tid_override = 1;
  1490. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1491. msdu_info->tid = DP_VO_TID;
  1492. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1493. /* Only for unicast frames */
  1494. if (!is_mcast) {
  1495. /* send ucast arp on VO queue */
  1496. msdu_info->tid = DP_VO_TID;
  1497. }
  1498. }
  1499. /*
  1500. * Assign all MCAST packets to BE
  1501. */
  1502. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1503. if (is_mcast) {
  1504. tos = 0;
  1505. dscp_tid_override = 1;
  1506. }
  1507. }
  1508. if (dscp_tid_override == 1) {
  1509. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1510. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1511. }
  1512. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1513. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1514. return;
  1515. }
  1516. /**
  1517. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1518. * @vdev: DP vdev handle
  1519. * @nbuf: skb
  1520. *
  1521. * Software based TID classification is required when more than 2 DSCP-TID
  1522. * mapping tables are needed.
  1523. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1524. *
  1525. * Return: void
  1526. */
  1527. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1528. struct dp_tx_msdu_info_s *msdu_info)
  1529. {
  1530. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1531. /*
  1532. * skip_sw_tid_classification flag will set in below cases-
  1533. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1534. * 2. hlos_tid_override enabled for vdev
  1535. * 3. mesh mode enabled for vdev
  1536. */
  1537. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1538. /* Update tid in msdu_info from skb priority */
  1539. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1540. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1541. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1542. return;
  1543. }
  1544. return;
  1545. }
  1546. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1547. }
  1548. #ifdef FEATURE_WLAN_TDLS
  1549. /**
  1550. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1551. * @soc: datapath SOC
  1552. * @vdev: datapath vdev
  1553. * @tx_desc: TX descriptor
  1554. *
  1555. * Return: None
  1556. */
  1557. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1558. struct dp_vdev *vdev,
  1559. struct dp_tx_desc_s *tx_desc)
  1560. {
  1561. if (vdev) {
  1562. if (vdev->is_tdls_frame) {
  1563. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1564. vdev->is_tdls_frame = false;
  1565. }
  1566. }
  1567. }
  1568. /**
  1569. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1570. * @soc: dp_soc handle
  1571. * @tx_desc: TX descriptor
  1572. * @vdev: datapath vdev handle
  1573. *
  1574. * Return: None
  1575. */
  1576. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1577. struct dp_tx_desc_s *tx_desc)
  1578. {
  1579. struct hal_tx_completion_status ts = {0};
  1580. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1581. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1582. DP_MOD_ID_TDLS);
  1583. if (qdf_unlikely(!vdev)) {
  1584. dp_err_rl("vdev is null!");
  1585. goto error;
  1586. }
  1587. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1588. if (vdev->tx_non_std_data_callback.func) {
  1589. qdf_nbuf_set_next(nbuf, NULL);
  1590. vdev->tx_non_std_data_callback.func(
  1591. vdev->tx_non_std_data_callback.ctxt,
  1592. nbuf, ts.status);
  1593. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1594. return;
  1595. } else {
  1596. dp_err_rl("callback func is null");
  1597. }
  1598. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1599. error:
  1600. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1601. qdf_nbuf_free(nbuf);
  1602. }
  1603. /**
  1604. * dp_tx_msdu_single_map() - do nbuf map
  1605. * @vdev: DP vdev handle
  1606. * @tx_desc: DP TX descriptor pointer
  1607. * @nbuf: skb pointer
  1608. *
  1609. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1610. * operation done in other component.
  1611. *
  1612. * Return: QDF_STATUS
  1613. */
  1614. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1615. struct dp_tx_desc_s *tx_desc,
  1616. qdf_nbuf_t nbuf)
  1617. {
  1618. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1619. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1620. nbuf,
  1621. QDF_DMA_TO_DEVICE,
  1622. nbuf->len);
  1623. else
  1624. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1625. QDF_DMA_TO_DEVICE);
  1626. }
  1627. #else
  1628. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1629. struct dp_vdev *vdev,
  1630. struct dp_tx_desc_s *tx_desc)
  1631. {
  1632. }
  1633. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1634. struct dp_tx_desc_s *tx_desc)
  1635. {
  1636. }
  1637. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1638. struct dp_tx_desc_s *tx_desc,
  1639. qdf_nbuf_t nbuf)
  1640. {
  1641. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1642. nbuf,
  1643. QDF_DMA_TO_DEVICE,
  1644. nbuf->len);
  1645. }
  1646. #endif
  1647. #ifdef MESH_MODE_SUPPORT
  1648. /**
  1649. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1650. * @soc: datapath SOC
  1651. * @vdev: datapath vdev
  1652. * @tx_desc: TX descriptor
  1653. *
  1654. * Return: None
  1655. */
  1656. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1657. struct dp_vdev *vdev,
  1658. struct dp_tx_desc_s *tx_desc)
  1659. {
  1660. if (qdf_unlikely(vdev->mesh_vdev))
  1661. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1662. }
  1663. /**
  1664. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1665. * @soc: dp_soc handle
  1666. * @tx_desc: TX descriptor
  1667. * @vdev: datapath vdev handle
  1668. *
  1669. * Return: None
  1670. */
  1671. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1672. struct dp_tx_desc_s *tx_desc)
  1673. {
  1674. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1675. struct dp_vdev *vdev = NULL;
  1676. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1677. qdf_nbuf_free(nbuf);
  1678. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1679. } else {
  1680. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1681. DP_MOD_ID_MESH);
  1682. if (vdev && vdev->osif_tx_free_ext)
  1683. vdev->osif_tx_free_ext((nbuf));
  1684. else
  1685. qdf_nbuf_free(nbuf);
  1686. if (vdev)
  1687. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1688. }
  1689. }
  1690. #else
  1691. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1692. struct dp_vdev *vdev,
  1693. struct dp_tx_desc_s *tx_desc)
  1694. {
  1695. }
  1696. static inline void dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1697. struct dp_tx_desc_s *tx_desc)
  1698. {
  1699. }
  1700. #endif
  1701. /**
  1702. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1703. * @vdev: DP vdev handle
  1704. * @nbuf: skb
  1705. *
  1706. * Return: 1 if frame needs to be dropped else 0
  1707. */
  1708. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1709. {
  1710. struct dp_pdev *pdev = NULL;
  1711. struct dp_ast_entry *src_ast_entry = NULL;
  1712. struct dp_ast_entry *dst_ast_entry = NULL;
  1713. struct dp_soc *soc = NULL;
  1714. qdf_assert(vdev);
  1715. pdev = vdev->pdev;
  1716. qdf_assert(pdev);
  1717. soc = pdev->soc;
  1718. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1719. (soc, dstmac, vdev->pdev->pdev_id);
  1720. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1721. (soc, srcmac, vdev->pdev->pdev_id);
  1722. if (dst_ast_entry && src_ast_entry) {
  1723. if (dst_ast_entry->peer_id ==
  1724. src_ast_entry->peer_id)
  1725. return 1;
  1726. }
  1727. return 0;
  1728. }
  1729. /**
  1730. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1731. * @vdev: DP vdev handle
  1732. * @nbuf: skb
  1733. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1734. * @meta_data: Metadata to the fw
  1735. * @tx_q: Tx queue to be used for this Tx frame
  1736. * @peer_id: peer_id of the peer in case of NAWDS frames
  1737. * @tx_exc_metadata: Handle that holds exception path metadata
  1738. *
  1739. * Return: NULL on success,
  1740. * nbuf when it fails to send
  1741. */
  1742. qdf_nbuf_t
  1743. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1744. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1745. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1746. {
  1747. struct dp_pdev *pdev = vdev->pdev;
  1748. struct dp_soc *soc = pdev->soc;
  1749. struct dp_tx_desc_s *tx_desc;
  1750. QDF_STATUS status;
  1751. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1752. uint16_t htt_tcl_metadata = 0;
  1753. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1754. uint8_t tid = msdu_info->tid;
  1755. struct cdp_tid_tx_stats *tid_stats = NULL;
  1756. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1757. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1758. msdu_info, tx_exc_metadata);
  1759. if (!tx_desc) {
  1760. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1761. vdev, tx_q->desc_pool_id);
  1762. drop_code = TX_DESC_ERR;
  1763. goto fail_return;
  1764. }
  1765. if (qdf_unlikely(soc->cce_disable)) {
  1766. if (dp_cce_classify(vdev, nbuf) == true) {
  1767. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1768. tid = DP_VO_TID;
  1769. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1770. }
  1771. }
  1772. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  1773. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1774. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1775. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1776. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1777. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1778. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1779. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1780. peer_id);
  1781. } else
  1782. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1783. if (msdu_info->exception_fw)
  1784. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1785. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1786. !pdev->enhanced_stats_en);
  1787. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  1788. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1789. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1790. /* Handle failure */
  1791. dp_err("qdf_nbuf_map failed");
  1792. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1793. drop_code = TX_DMA_MAP_ERR;
  1794. goto release_desc;
  1795. }
  1796. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1797. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1798. tx_desc->id, DP_TX_DESC_MAP);
  1799. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1800. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  1801. htt_tcl_metadata,
  1802. tx_exc_metadata, msdu_info);
  1803. if (status != QDF_STATUS_SUCCESS) {
  1804. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1805. tx_desc, tx_q->ring_id);
  1806. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  1807. tx_desc->id, DP_TX_DESC_UNMAP);
  1808. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1809. QDF_DMA_TO_DEVICE,
  1810. nbuf->len);
  1811. drop_code = TX_HW_ENQUEUE;
  1812. goto release_desc;
  1813. }
  1814. return NULL;
  1815. release_desc:
  1816. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1817. fail_return:
  1818. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1819. tid_stats = &pdev->stats.tid_stats.
  1820. tid_tx_stats[tx_q->ring_id][tid];
  1821. tid_stats->swdrop_cnt[drop_code]++;
  1822. return nbuf;
  1823. }
  1824. /**
  1825. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1826. * @soc: Soc handle
  1827. * @desc: software Tx descriptor to be processed
  1828. *
  1829. * Return: none
  1830. */
  1831. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  1832. struct dp_tx_desc_s *desc)
  1833. {
  1834. qdf_nbuf_t nbuf = desc->nbuf;
  1835. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  1836. /* nbuf already freed in vdev detach path */
  1837. if (!nbuf)
  1838. return;
  1839. /* If it is TDLS mgmt, don't unmap or free the frame */
  1840. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  1841. return dp_non_std_tx_comp_free_buff(soc, desc);
  1842. /* 0 : MSDU buffer, 1 : MLE */
  1843. if (desc->msdu_ext_desc) {
  1844. /* TSO free */
  1845. if (hal_tx_ext_desc_get_tso_enable(
  1846. desc->msdu_ext_desc->vaddr)) {
  1847. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  1848. desc->id, DP_TX_COMP_MSDU_EXT);
  1849. dp_tx_tso_seg_history_add(soc, desc->tso_desc,
  1850. desc->nbuf, desc->id, type);
  1851. /* unmap eash TSO seg before free the nbuf */
  1852. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  1853. desc->tso_num_desc);
  1854. qdf_nbuf_free(nbuf);
  1855. return;
  1856. }
  1857. }
  1858. /* If it's ME frame, dont unmap the cloned nbuf's */
  1859. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  1860. goto nbuf_free;
  1861. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  1862. dp_tx_unmap(soc, desc);
  1863. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  1864. return dp_mesh_tx_comp_free_buff(soc, desc);
  1865. nbuf_free:
  1866. qdf_nbuf_free(nbuf);
  1867. }
  1868. /**
  1869. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1870. * @vdev: DP vdev handle
  1871. * @nbuf: skb
  1872. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1873. *
  1874. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1875. *
  1876. * Return: NULL on success,
  1877. * nbuf when it fails to send
  1878. */
  1879. #if QDF_LOCK_STATS
  1880. noinline
  1881. #else
  1882. #endif
  1883. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1884. struct dp_tx_msdu_info_s *msdu_info)
  1885. {
  1886. uint32_t i;
  1887. struct dp_pdev *pdev = vdev->pdev;
  1888. struct dp_soc *soc = pdev->soc;
  1889. struct dp_tx_desc_s *tx_desc;
  1890. bool is_cce_classified = false;
  1891. QDF_STATUS status;
  1892. uint16_t htt_tcl_metadata = 0;
  1893. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1894. struct cdp_tid_tx_stats *tid_stats = NULL;
  1895. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  1896. if (qdf_unlikely(soc->cce_disable)) {
  1897. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1898. if (is_cce_classified) {
  1899. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1900. msdu_info->tid = DP_VO_TID;
  1901. }
  1902. }
  1903. if (msdu_info->frm_type == dp_tx_frm_me)
  1904. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1905. i = 0;
  1906. /* Print statement to track i and num_seg */
  1907. /*
  1908. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1909. * descriptors using information in msdu_info
  1910. */
  1911. while (i < msdu_info->num_seg) {
  1912. /*
  1913. * Setup Tx descriptor for an MSDU, and MSDU extension
  1914. * descriptor
  1915. */
  1916. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1917. tx_q->desc_pool_id);
  1918. if (!tx_desc) {
  1919. if (msdu_info->frm_type == dp_tx_frm_me) {
  1920. prep_desc_fail++;
  1921. dp_tx_me_free_buf(pdev,
  1922. (void *)(msdu_info->u.sg_info
  1923. .curr_seg->frags[0].vaddr));
  1924. if (prep_desc_fail == msdu_info->num_seg) {
  1925. /*
  1926. * Unmap is needed only if descriptor
  1927. * preparation failed for all segments.
  1928. */
  1929. qdf_nbuf_unmap(soc->osdev,
  1930. msdu_info->u.sg_info.
  1931. curr_seg->nbuf,
  1932. QDF_DMA_TO_DEVICE);
  1933. }
  1934. /*
  1935. * Free the nbuf for the current segment
  1936. * and make it point to the next in the list.
  1937. * For me, there are as many segments as there
  1938. * are no of clients.
  1939. */
  1940. qdf_nbuf_free(msdu_info->u.sg_info
  1941. .curr_seg->nbuf);
  1942. if (msdu_info->u.sg_info.curr_seg->next) {
  1943. msdu_info->u.sg_info.curr_seg =
  1944. msdu_info->u.sg_info
  1945. .curr_seg->next;
  1946. nbuf = msdu_info->u.sg_info
  1947. .curr_seg->nbuf;
  1948. }
  1949. i++;
  1950. continue;
  1951. }
  1952. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1953. dp_tx_tso_seg_history_add(
  1954. soc,
  1955. msdu_info->u.tso_info.curr_seg,
  1956. nbuf, 0, DP_TX_DESC_UNMAP);
  1957. dp_tx_tso_unmap_segment(soc,
  1958. msdu_info->u.tso_info.
  1959. curr_seg,
  1960. msdu_info->u.tso_info.
  1961. tso_num_seg_list);
  1962. if (msdu_info->u.tso_info.curr_seg->next) {
  1963. msdu_info->u.tso_info.curr_seg =
  1964. msdu_info->u.tso_info.curr_seg->next;
  1965. i++;
  1966. continue;
  1967. }
  1968. }
  1969. goto done;
  1970. }
  1971. if (msdu_info->frm_type == dp_tx_frm_me) {
  1972. tx_desc->me_buffer =
  1973. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1974. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1975. }
  1976. if (is_cce_classified)
  1977. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1978. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1979. if (msdu_info->exception_fw) {
  1980. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1981. }
  1982. /*
  1983. * For frames with multiple segments (TSO, ME), jump to next
  1984. * segment.
  1985. */
  1986. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1987. if (msdu_info->u.tso_info.curr_seg->next) {
  1988. msdu_info->u.tso_info.curr_seg =
  1989. msdu_info->u.tso_info.curr_seg->next;
  1990. /*
  1991. * If this is a jumbo nbuf, then increment the
  1992. * number of nbuf users for each additional
  1993. * segment of the msdu. This will ensure that
  1994. * the skb is freed only after receiving tx
  1995. * completion for all segments of an nbuf
  1996. */
  1997. qdf_nbuf_inc_users(nbuf);
  1998. /* Check with MCL if this is needed */
  1999. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2000. */
  2001. }
  2002. }
  2003. /*
  2004. * Enqueue the Tx MSDU descriptor to HW for transmit
  2005. */
  2006. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2007. htt_tcl_metadata,
  2008. NULL, msdu_info);
  2009. if (status != QDF_STATUS_SUCCESS) {
  2010. dp_info("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2011. tx_desc, tx_q->ring_id);
  2012. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2013. tid_stats = &pdev->stats.tid_stats.
  2014. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2015. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2016. if (msdu_info->frm_type == dp_tx_frm_me) {
  2017. hw_enq_fail++;
  2018. if (hw_enq_fail == msdu_info->num_seg) {
  2019. /*
  2020. * Unmap is needed only if enqueue
  2021. * failed for all segments.
  2022. */
  2023. qdf_nbuf_unmap(soc->osdev,
  2024. msdu_info->u.sg_info.
  2025. curr_seg->nbuf,
  2026. QDF_DMA_TO_DEVICE);
  2027. }
  2028. /*
  2029. * Free the nbuf for the current segment
  2030. * and make it point to the next in the list.
  2031. * For me, there are as many segments as there
  2032. * are no of clients.
  2033. */
  2034. qdf_nbuf_free(msdu_info->u.sg_info
  2035. .curr_seg->nbuf);
  2036. if (msdu_info->u.sg_info.curr_seg->next) {
  2037. msdu_info->u.sg_info.curr_seg =
  2038. msdu_info->u.sg_info
  2039. .curr_seg->next;
  2040. nbuf = msdu_info->u.sg_info
  2041. .curr_seg->nbuf;
  2042. } else
  2043. break;
  2044. i++;
  2045. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2046. continue;
  2047. }
  2048. /*
  2049. * For TSO frames, the nbuf users increment done for
  2050. * the current segment has to be reverted, since the
  2051. * hw enqueue for this segment failed
  2052. */
  2053. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2054. msdu_info->u.tso_info.curr_seg) {
  2055. /*
  2056. * unmap and free current,
  2057. * retransmit remaining segments
  2058. */
  2059. dp_tx_comp_free_buf(soc, tx_desc);
  2060. i++;
  2061. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2062. continue;
  2063. }
  2064. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2065. goto done;
  2066. }
  2067. /*
  2068. * TODO
  2069. * if tso_info structure can be modified to have curr_seg
  2070. * as first element, following 2 blocks of code (for TSO and SG)
  2071. * can be combined into 1
  2072. */
  2073. /*
  2074. * For Multicast-Unicast converted packets,
  2075. * each converted frame (for a client) is represented as
  2076. * 1 segment
  2077. */
  2078. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2079. (msdu_info->frm_type == dp_tx_frm_me)) {
  2080. if (msdu_info->u.sg_info.curr_seg->next) {
  2081. msdu_info->u.sg_info.curr_seg =
  2082. msdu_info->u.sg_info.curr_seg->next;
  2083. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2084. } else
  2085. break;
  2086. }
  2087. i++;
  2088. }
  2089. nbuf = NULL;
  2090. done:
  2091. return nbuf;
  2092. }
  2093. /**
  2094. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2095. * for SG frames
  2096. * @vdev: DP vdev handle
  2097. * @nbuf: skb
  2098. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2099. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2100. *
  2101. * Return: NULL on success,
  2102. * nbuf when it fails to send
  2103. */
  2104. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2105. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2106. {
  2107. uint32_t cur_frag, nr_frags, i;
  2108. qdf_dma_addr_t paddr;
  2109. struct dp_tx_sg_info_s *sg_info;
  2110. sg_info = &msdu_info->u.sg_info;
  2111. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2112. if (QDF_STATUS_SUCCESS !=
  2113. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2114. QDF_DMA_TO_DEVICE,
  2115. qdf_nbuf_headlen(nbuf))) {
  2116. dp_tx_err("dma map error");
  2117. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2118. qdf_nbuf_free(nbuf);
  2119. return NULL;
  2120. }
  2121. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2122. seg_info->frags[0].paddr_lo = paddr;
  2123. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2124. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2125. seg_info->frags[0].vaddr = (void *) nbuf;
  2126. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2127. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  2128. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  2129. dp_tx_err("frag dma map error");
  2130. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2131. goto map_err;
  2132. }
  2133. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2134. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2135. seg_info->frags[cur_frag + 1].paddr_hi =
  2136. ((uint64_t) paddr) >> 32;
  2137. seg_info->frags[cur_frag + 1].len =
  2138. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2139. }
  2140. seg_info->frag_cnt = (cur_frag + 1);
  2141. seg_info->total_len = qdf_nbuf_len(nbuf);
  2142. seg_info->next = NULL;
  2143. sg_info->curr_seg = seg_info;
  2144. msdu_info->frm_type = dp_tx_frm_sg;
  2145. msdu_info->num_seg = 1;
  2146. return nbuf;
  2147. map_err:
  2148. /* restore paddr into nbuf before calling unmap */
  2149. qdf_nbuf_mapped_paddr_set(nbuf,
  2150. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2151. ((uint64_t)
  2152. seg_info->frags[0].paddr_hi) << 32));
  2153. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2154. QDF_DMA_TO_DEVICE,
  2155. seg_info->frags[0].len);
  2156. for (i = 1; i <= cur_frag; i++) {
  2157. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2158. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2159. seg_info->frags[i].paddr_hi) << 32),
  2160. seg_info->frags[i].len,
  2161. QDF_DMA_TO_DEVICE);
  2162. }
  2163. qdf_nbuf_free(nbuf);
  2164. return NULL;
  2165. }
  2166. /**
  2167. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2168. * @vdev: DP vdev handle
  2169. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2170. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2171. *
  2172. * Return: NULL on failure,
  2173. * nbuf when extracted successfully
  2174. */
  2175. static
  2176. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2177. struct dp_tx_msdu_info_s *msdu_info,
  2178. uint16_t ppdu_cookie)
  2179. {
  2180. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2181. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2182. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2183. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2184. (msdu_info->meta_data[5], 1);
  2185. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2186. (msdu_info->meta_data[5], 1);
  2187. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2188. (msdu_info->meta_data[6], ppdu_cookie);
  2189. msdu_info->exception_fw = 1;
  2190. msdu_info->is_tx_sniffer = 1;
  2191. }
  2192. #ifdef MESH_MODE_SUPPORT
  2193. /**
  2194. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2195. and prepare msdu_info for mesh frames.
  2196. * @vdev: DP vdev handle
  2197. * @nbuf: skb
  2198. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2199. *
  2200. * Return: NULL on failure,
  2201. * nbuf when extracted successfully
  2202. */
  2203. static
  2204. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2205. struct dp_tx_msdu_info_s *msdu_info)
  2206. {
  2207. struct meta_hdr_s *mhdr;
  2208. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2209. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2210. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2211. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2212. msdu_info->exception_fw = 0;
  2213. goto remove_meta_hdr;
  2214. }
  2215. msdu_info->exception_fw = 1;
  2216. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2217. meta_data->host_tx_desc_pool = 1;
  2218. meta_data->update_peer_cache = 1;
  2219. meta_data->learning_frame = 1;
  2220. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2221. meta_data->power = mhdr->power;
  2222. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2223. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2224. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2225. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2226. meta_data->dyn_bw = 1;
  2227. meta_data->valid_pwr = 1;
  2228. meta_data->valid_mcs_mask = 1;
  2229. meta_data->valid_nss_mask = 1;
  2230. meta_data->valid_preamble_type = 1;
  2231. meta_data->valid_retries = 1;
  2232. meta_data->valid_bw_info = 1;
  2233. }
  2234. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2235. meta_data->encrypt_type = 0;
  2236. meta_data->valid_encrypt_type = 1;
  2237. meta_data->learning_frame = 0;
  2238. }
  2239. meta_data->valid_key_flags = 1;
  2240. meta_data->key_flags = (mhdr->keyix & 0x3);
  2241. remove_meta_hdr:
  2242. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2243. dp_tx_err("qdf_nbuf_pull_head failed");
  2244. qdf_nbuf_free(nbuf);
  2245. return NULL;
  2246. }
  2247. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2248. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2249. " tid %d to_fw %d",
  2250. msdu_info->meta_data[0],
  2251. msdu_info->meta_data[1],
  2252. msdu_info->meta_data[2],
  2253. msdu_info->meta_data[3],
  2254. msdu_info->meta_data[4],
  2255. msdu_info->meta_data[5],
  2256. msdu_info->tid, msdu_info->exception_fw);
  2257. return nbuf;
  2258. }
  2259. #else
  2260. static
  2261. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2262. struct dp_tx_msdu_info_s *msdu_info)
  2263. {
  2264. return nbuf;
  2265. }
  2266. #endif
  2267. /**
  2268. * dp_check_exc_metadata() - Checks if parameters are valid
  2269. * @tx_exc - holds all exception path parameters
  2270. *
  2271. * Returns true when all the parameters are valid else false
  2272. *
  2273. */
  2274. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2275. {
  2276. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2277. HTT_INVALID_TID);
  2278. bool invalid_encap_type =
  2279. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2280. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2281. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2282. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2283. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2284. tx_exc->ppdu_cookie == 0);
  2285. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2286. invalid_cookie) {
  2287. return false;
  2288. }
  2289. return true;
  2290. }
  2291. #ifdef ATH_SUPPORT_IQUE
  2292. /**
  2293. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2294. * @vdev: vdev handle
  2295. * @nbuf: skb
  2296. *
  2297. * Return: true on success,
  2298. * false on failure
  2299. */
  2300. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2301. {
  2302. qdf_ether_header_t *eh;
  2303. /* Mcast to Ucast Conversion*/
  2304. if (qdf_likely(!vdev->mcast_enhancement_en))
  2305. return true;
  2306. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2307. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2308. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2309. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2310. qdf_nbuf_set_next(nbuf, NULL);
  2311. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2312. qdf_nbuf_len(nbuf));
  2313. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2314. QDF_STATUS_SUCCESS) {
  2315. return false;
  2316. }
  2317. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2318. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2319. QDF_STATUS_SUCCESS) {
  2320. return false;
  2321. }
  2322. }
  2323. }
  2324. return true;
  2325. }
  2326. #else
  2327. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2328. {
  2329. return true;
  2330. }
  2331. #endif
  2332. /**
  2333. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2334. * @nbuf: qdf_nbuf_t
  2335. * @vdev: struct dp_vdev *
  2336. *
  2337. * Allow packet for processing only if it is for peer client which is
  2338. * connected with same vap. Drop packet if client is connected to
  2339. * different vap.
  2340. *
  2341. * Return: QDF_STATUS
  2342. */
  2343. static inline QDF_STATUS
  2344. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2345. {
  2346. struct dp_ast_entry *dst_ast_entry = NULL;
  2347. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2348. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2349. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2350. return QDF_STATUS_SUCCESS;
  2351. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2352. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2353. eh->ether_dhost,
  2354. vdev->vdev_id);
  2355. /* If there is no ast entry, return failure */
  2356. if (qdf_unlikely(!dst_ast_entry)) {
  2357. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2358. return QDF_STATUS_E_FAILURE;
  2359. }
  2360. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2361. return QDF_STATUS_SUCCESS;
  2362. }
  2363. /**
  2364. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2365. * @soc: DP soc handle
  2366. * @vdev_id: id of DP vdev handle
  2367. * @nbuf: skb
  2368. * @tx_exc_metadata: Handle that holds exception path meta data
  2369. *
  2370. * Entry point for Core Tx layer (DP_TX) invoked from
  2371. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2372. *
  2373. * Return: NULL on success,
  2374. * nbuf when it fails to send
  2375. */
  2376. qdf_nbuf_t
  2377. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2378. qdf_nbuf_t nbuf,
  2379. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2380. {
  2381. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2382. qdf_ether_header_t *eh = NULL;
  2383. struct dp_tx_msdu_info_s msdu_info;
  2384. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2385. DP_MOD_ID_TX_EXCEPTION);
  2386. if (qdf_unlikely(!vdev))
  2387. goto fail;
  2388. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2389. if (!tx_exc_metadata)
  2390. goto fail;
  2391. msdu_info.tid = tx_exc_metadata->tid;
  2392. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2393. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2394. QDF_MAC_ADDR_REF(nbuf->data));
  2395. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2396. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2397. dp_tx_err("Invalid parameters in exception path");
  2398. goto fail;
  2399. }
  2400. /* Basic sanity checks for unsupported packets */
  2401. /* MESH mode */
  2402. if (qdf_unlikely(vdev->mesh_vdev)) {
  2403. dp_tx_err("Mesh mode is not supported in exception path");
  2404. goto fail;
  2405. }
  2406. /*
  2407. * Classify the frame and call corresponding
  2408. * "prepare" function which extracts the segment (TSO)
  2409. * and fragmentation information (for TSO , SG, ME, or Raw)
  2410. * into MSDU_INFO structure which is later used to fill
  2411. * SW and HW descriptors.
  2412. */
  2413. if (qdf_nbuf_is_tso(nbuf)) {
  2414. dp_verbose_debug("TSO frame %pK", vdev);
  2415. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2416. qdf_nbuf_len(nbuf));
  2417. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2418. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2419. qdf_nbuf_len(nbuf));
  2420. goto fail;
  2421. }
  2422. goto send_multiple;
  2423. }
  2424. /* SG */
  2425. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2426. struct dp_tx_seg_info_s seg_info = {0};
  2427. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2428. if (!nbuf)
  2429. goto fail;
  2430. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2431. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2432. qdf_nbuf_len(nbuf));
  2433. goto send_multiple;
  2434. }
  2435. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2436. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2437. qdf_nbuf_len(nbuf));
  2438. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2439. tx_exc_metadata->ppdu_cookie);
  2440. }
  2441. /*
  2442. * Get HW Queue to use for this frame.
  2443. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2444. * dedicated for data and 1 for command.
  2445. * "queue_id" maps to one hardware ring.
  2446. * With each ring, we also associate a unique Tx descriptor pool
  2447. * to minimize lock contention for these resources.
  2448. */
  2449. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2450. /*
  2451. * Check exception descriptors
  2452. */
  2453. if (dp_tx_exception_limit_check(vdev))
  2454. goto fail;
  2455. /* Single linear frame */
  2456. /*
  2457. * If nbuf is a simple linear frame, use send_single function to
  2458. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2459. * SRNG. There is no need to setup a MSDU extension descriptor.
  2460. */
  2461. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2462. tx_exc_metadata->peer_id, tx_exc_metadata);
  2463. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2464. return nbuf;
  2465. send_multiple:
  2466. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2467. fail:
  2468. if (vdev)
  2469. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2470. dp_verbose_debug("pkt send failed");
  2471. return nbuf;
  2472. }
  2473. /**
  2474. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  2475. * in exception path in special case to avoid regular exception path chk.
  2476. * @soc: DP soc handle
  2477. * @vdev_id: id of DP vdev handle
  2478. * @nbuf: skb
  2479. * @tx_exc_metadata: Handle that holds exception path meta data
  2480. *
  2481. * Entry point for Core Tx layer (DP_TX) invoked from
  2482. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2483. *
  2484. * Return: NULL on success,
  2485. * nbuf when it fails to send
  2486. */
  2487. qdf_nbuf_t
  2488. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2489. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2490. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2491. {
  2492. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2493. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2494. DP_MOD_ID_TX_EXCEPTION);
  2495. if (qdf_unlikely(!vdev))
  2496. goto fail;
  2497. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2498. == QDF_STATUS_E_FAILURE)) {
  2499. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2500. goto fail;
  2501. }
  2502. /* Unref count as it will agin be taken inside dp_tx_exception */
  2503. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2504. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  2505. fail:
  2506. if (vdev)
  2507. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2508. dp_verbose_debug("pkt send failed");
  2509. return nbuf;
  2510. }
  2511. /**
  2512. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  2513. * @soc: DP soc handle
  2514. * @vdev_id: DP vdev handle
  2515. * @nbuf: skb
  2516. *
  2517. * Entry point for Core Tx layer (DP_TX) invoked from
  2518. * hard_start_xmit in OSIF/HDD
  2519. *
  2520. * Return: NULL on success,
  2521. * nbuf when it fails to send
  2522. */
  2523. #ifdef MESH_MODE_SUPPORT
  2524. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2525. qdf_nbuf_t nbuf)
  2526. {
  2527. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2528. struct meta_hdr_s *mhdr;
  2529. qdf_nbuf_t nbuf_mesh = NULL;
  2530. qdf_nbuf_t nbuf_clone = NULL;
  2531. struct dp_vdev *vdev;
  2532. uint8_t no_enc_frame = 0;
  2533. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2534. if (!nbuf_mesh) {
  2535. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2536. "qdf_nbuf_unshare failed");
  2537. return nbuf;
  2538. }
  2539. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  2540. if (!vdev) {
  2541. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2542. "vdev is NULL for vdev_id %d", vdev_id);
  2543. return nbuf;
  2544. }
  2545. nbuf = nbuf_mesh;
  2546. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2547. if ((vdev->sec_type != cdp_sec_type_none) &&
  2548. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2549. no_enc_frame = 1;
  2550. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2551. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2552. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2553. !no_enc_frame) {
  2554. nbuf_clone = qdf_nbuf_clone(nbuf);
  2555. if (!nbuf_clone) {
  2556. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2557. "qdf_nbuf_clone failed");
  2558. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2559. return nbuf;
  2560. }
  2561. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2562. }
  2563. if (nbuf_clone) {
  2564. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2565. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2566. } else {
  2567. qdf_nbuf_free(nbuf_clone);
  2568. }
  2569. }
  2570. if (no_enc_frame)
  2571. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2572. else
  2573. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2574. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2575. if ((!nbuf) && no_enc_frame) {
  2576. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2577. }
  2578. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  2579. return nbuf;
  2580. }
  2581. #else
  2582. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2583. qdf_nbuf_t nbuf)
  2584. {
  2585. return dp_tx_send(soc, vdev_id, nbuf);
  2586. }
  2587. #endif
  2588. /**
  2589. * dp_tx_nawds_handler() - NAWDS handler
  2590. *
  2591. * @soc: DP soc handle
  2592. * @vdev_id: id of DP vdev handle
  2593. * @msdu_info: msdu_info required to create HTT metadata
  2594. * @nbuf: skb
  2595. *
  2596. * This API transfers the multicast frames with the peer id
  2597. * on NAWDS enabled peer.
  2598. * Return: none
  2599. */
  2600. static inline
  2601. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2602. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2603. {
  2604. struct dp_peer *peer = NULL;
  2605. qdf_nbuf_t nbuf_clone = NULL;
  2606. uint16_t peer_id = DP_INVALID_PEER;
  2607. uint16_t sa_peer_id = DP_INVALID_PEER;
  2608. struct dp_ast_entry *ast_entry = NULL;
  2609. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2610. if (!soc->ast_offload_support) {
  2611. qdf_spin_lock_bh(&soc->ast_lock);
  2612. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2613. (soc,
  2614. (uint8_t *)(eh->ether_shost),
  2615. vdev->pdev->pdev_id);
  2616. if (ast_entry)
  2617. sa_peer_id = ast_entry->peer_id;
  2618. qdf_spin_unlock_bh(&soc->ast_lock);
  2619. }
  2620. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2621. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2622. if (!peer->bss_peer && peer->nawds_enabled) {
  2623. peer_id = peer->peer_id;
  2624. /* Multicast packets needs to be
  2625. * dropped in case of intra bss forwarding
  2626. */
  2627. if (!soc->ast_offload_support) {
  2628. if (sa_peer_id == peer->peer_id) {
  2629. dp_tx_debug("multicast packet");
  2630. DP_STATS_INC(peer, tx.nawds_mcast_drop,
  2631. 1);
  2632. continue;
  2633. }
  2634. }
  2635. nbuf_clone = qdf_nbuf_clone(nbuf);
  2636. if (!nbuf_clone) {
  2637. QDF_TRACE(QDF_MODULE_ID_DP,
  2638. QDF_TRACE_LEVEL_ERROR,
  2639. FL("nbuf clone failed"));
  2640. break;
  2641. }
  2642. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2643. msdu_info, peer_id,
  2644. NULL);
  2645. if (nbuf_clone) {
  2646. dp_tx_debug("pkt send failed");
  2647. qdf_nbuf_free(nbuf_clone);
  2648. } else {
  2649. if (peer_id != DP_INVALID_PEER)
  2650. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2651. 1, qdf_nbuf_len(nbuf));
  2652. }
  2653. }
  2654. }
  2655. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2656. }
  2657. /**
  2658. * dp_tx_send() - Transmit a frame on a given VAP
  2659. * @soc: DP soc handle
  2660. * @vdev_id: id of DP vdev handle
  2661. * @nbuf: skb
  2662. *
  2663. * Entry point for Core Tx layer (DP_TX) invoked from
  2664. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2665. * cases
  2666. *
  2667. * Return: NULL on success,
  2668. * nbuf when it fails to send
  2669. */
  2670. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2671. qdf_nbuf_t nbuf)
  2672. {
  2673. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2674. uint16_t peer_id = HTT_INVALID_PEER;
  2675. /*
  2676. * doing a memzero is causing additional function call overhead
  2677. * so doing static stack clearing
  2678. */
  2679. struct dp_tx_msdu_info_s msdu_info = {0};
  2680. struct dp_vdev *vdev = NULL;
  2681. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2682. return nbuf;
  2683. /*
  2684. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2685. * this in per packet path.
  2686. *
  2687. * As in this path vdev memory is already protected with netdev
  2688. * tx lock
  2689. */
  2690. vdev = soc->vdev_id_map[vdev_id];
  2691. if (qdf_unlikely(!vdev))
  2692. return nbuf;
  2693. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2694. QDF_MAC_ADDR_REF(nbuf->data));
  2695. /*
  2696. * Set Default Host TID value to invalid TID
  2697. * (TID override disabled)
  2698. */
  2699. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2700. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2701. if (qdf_unlikely(vdev->mesh_vdev)) {
  2702. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2703. &msdu_info);
  2704. if (!nbuf_mesh) {
  2705. dp_verbose_debug("Extracting mesh metadata failed");
  2706. return nbuf;
  2707. }
  2708. nbuf = nbuf_mesh;
  2709. }
  2710. /*
  2711. * Get HW Queue to use for this frame.
  2712. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2713. * dedicated for data and 1 for command.
  2714. * "queue_id" maps to one hardware ring.
  2715. * With each ring, we also associate a unique Tx descriptor pool
  2716. * to minimize lock contention for these resources.
  2717. */
  2718. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2719. /*
  2720. * TCL H/W supports 2 DSCP-TID mapping tables.
  2721. * Table 1 - Default DSCP-TID mapping table
  2722. * Table 2 - 1 DSCP-TID override table
  2723. *
  2724. * If we need a different DSCP-TID mapping for this vap,
  2725. * call tid_classify to extract DSCP/ToS from frame and
  2726. * map to a TID and store in msdu_info. This is later used
  2727. * to fill in TCL Input descriptor (per-packet TID override).
  2728. */
  2729. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2730. /*
  2731. * Classify the frame and call corresponding
  2732. * "prepare" function which extracts the segment (TSO)
  2733. * and fragmentation information (for TSO , SG, ME, or Raw)
  2734. * into MSDU_INFO structure which is later used to fill
  2735. * SW and HW descriptors.
  2736. */
  2737. if (qdf_nbuf_is_tso(nbuf)) {
  2738. dp_verbose_debug("TSO frame %pK", vdev);
  2739. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2740. qdf_nbuf_len(nbuf));
  2741. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2742. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2743. qdf_nbuf_len(nbuf));
  2744. return nbuf;
  2745. }
  2746. goto send_multiple;
  2747. }
  2748. /* SG */
  2749. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2750. struct dp_tx_seg_info_s seg_info = {0};
  2751. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2752. if (!nbuf)
  2753. return NULL;
  2754. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2755. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2756. qdf_nbuf_len(nbuf));
  2757. goto send_multiple;
  2758. }
  2759. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  2760. return NULL;
  2761. /* RAW */
  2762. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2763. struct dp_tx_seg_info_s seg_info = {0};
  2764. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2765. if (!nbuf)
  2766. return NULL;
  2767. dp_verbose_debug("Raw frame %pK", vdev);
  2768. goto send_multiple;
  2769. }
  2770. if (qdf_unlikely(vdev->nawds_enabled)) {
  2771. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2772. qdf_nbuf_data(nbuf);
  2773. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2774. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2775. peer_id = DP_INVALID_PEER;
  2776. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2777. 1, qdf_nbuf_len(nbuf));
  2778. }
  2779. /* Single linear frame */
  2780. /*
  2781. * If nbuf is a simple linear frame, use send_single function to
  2782. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2783. * SRNG. There is no need to setup a MSDU extension descriptor.
  2784. */
  2785. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2786. return nbuf;
  2787. send_multiple:
  2788. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2789. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2790. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2791. return nbuf;
  2792. }
  2793. /**
  2794. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  2795. * case to vaoid check in perpkt path.
  2796. * @soc: DP soc handle
  2797. * @vdev_id: id of DP vdev handle
  2798. * @nbuf: skb
  2799. *
  2800. * Entry point for Core Tx layer (DP_TX) invoked from
  2801. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  2802. * with special condition to avoid per pkt check in dp_tx_send
  2803. *
  2804. * Return: NULL on success,
  2805. * nbuf when it fails to send
  2806. */
  2807. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2808. uint8_t vdev_id, qdf_nbuf_t nbuf)
  2809. {
  2810. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2811. struct dp_vdev *vdev = NULL;
  2812. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2813. return nbuf;
  2814. /*
  2815. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2816. * this in per packet path.
  2817. *
  2818. * As in this path vdev memory is already protected with netdev
  2819. * tx lock
  2820. */
  2821. vdev = soc->vdev_id_map[vdev_id];
  2822. if (qdf_unlikely(!vdev))
  2823. return nbuf;
  2824. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  2825. == QDF_STATUS_E_FAILURE)) {
  2826. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  2827. return nbuf;
  2828. }
  2829. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  2830. }
  2831. #ifdef UMAC_SUPPORT_PROXY_ARP
  2832. /**
  2833. * dp_tx_proxy_arp() - Tx proxy arp handler
  2834. * @vdev: datapath vdev handle
  2835. * @buf: sk buffer
  2836. *
  2837. * Return: status
  2838. */
  2839. static inline
  2840. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2841. {
  2842. if (vdev->osif_proxy_arp)
  2843. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  2844. /*
  2845. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  2846. * osif_proxy_arp has a valid function pointer assigned
  2847. * to it
  2848. */
  2849. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  2850. return QDF_STATUS_NOT_INITIALIZED;
  2851. }
  2852. #else
  2853. /**
  2854. * dp_tx_proxy_arp() - Tx proxy arp handler
  2855. * @vdev: datapath vdev handle
  2856. * @buf: sk buffer
  2857. *
  2858. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  2859. * is not defined.
  2860. *
  2861. * Return: status
  2862. */
  2863. static inline
  2864. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2865. {
  2866. return QDF_STATUS_SUCCESS;
  2867. }
  2868. #endif
  2869. /**
  2870. * dp_tx_reinject_handler() - Tx Reinject Handler
  2871. * @soc: datapath soc handle
  2872. * @vdev: datapath vdev handle
  2873. * @tx_desc: software descriptor head pointer
  2874. * @status : Tx completion status from HTT descriptor
  2875. *
  2876. * This function reinjects frames back to Target.
  2877. * Todo - Host queue needs to be added
  2878. *
  2879. * Return: none
  2880. */
  2881. static
  2882. void dp_tx_reinject_handler(struct dp_soc *soc,
  2883. struct dp_vdev *vdev,
  2884. struct dp_tx_desc_s *tx_desc,
  2885. uint8_t *status)
  2886. {
  2887. struct dp_peer *peer = NULL;
  2888. uint32_t peer_id = HTT_INVALID_PEER;
  2889. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2890. qdf_nbuf_t nbuf_copy = NULL;
  2891. struct dp_tx_msdu_info_s msdu_info;
  2892. #ifdef WDS_VENDOR_EXTENSION
  2893. int is_mcast = 0, is_ucast = 0;
  2894. int num_peers_3addr = 0;
  2895. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2896. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2897. #endif
  2898. qdf_assert(vdev);
  2899. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2900. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2901. dp_tx_debug("Tx reinject path");
  2902. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2903. qdf_nbuf_len(tx_desc->nbuf));
  2904. #ifdef WDS_VENDOR_EXTENSION
  2905. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2906. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2907. } else {
  2908. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2909. }
  2910. is_ucast = !is_mcast;
  2911. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2912. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2913. if (peer->bss_peer)
  2914. continue;
  2915. /* Detect wds peers that use 3-addr framing for mcast.
  2916. * if there are any, the bss_peer is used to send the
  2917. * the mcast frame using 3-addr format. all wds enabled
  2918. * peers that use 4-addr framing for mcast frames will
  2919. * be duplicated and sent as 4-addr frames below.
  2920. */
  2921. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2922. num_peers_3addr = 1;
  2923. break;
  2924. }
  2925. }
  2926. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2927. #endif
  2928. if (qdf_unlikely(vdev->mesh_vdev)) {
  2929. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2930. } else {
  2931. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2932. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2933. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2934. #ifdef WDS_VENDOR_EXTENSION
  2935. /*
  2936. * . if 3-addr STA, then send on BSS Peer
  2937. * . if Peer WDS enabled and accept 4-addr mcast,
  2938. * send mcast on that peer only
  2939. * . if Peer WDS enabled and accept 4-addr ucast,
  2940. * send ucast on that peer only
  2941. */
  2942. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2943. (peer->wds_enabled &&
  2944. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2945. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2946. #else
  2947. (peer->bss_peer &&
  2948. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  2949. #endif
  2950. peer_id = DP_INVALID_PEER;
  2951. nbuf_copy = qdf_nbuf_copy(nbuf);
  2952. if (!nbuf_copy) {
  2953. dp_tx_debug("nbuf copy failed");
  2954. break;
  2955. }
  2956. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2957. nbuf_copy,
  2958. &msdu_info,
  2959. peer_id,
  2960. NULL);
  2961. if (nbuf_copy) {
  2962. dp_tx_debug("pkt send failed");
  2963. qdf_nbuf_free(nbuf_copy);
  2964. }
  2965. }
  2966. }
  2967. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2968. }
  2969. qdf_nbuf_free(nbuf);
  2970. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2971. }
  2972. /**
  2973. * dp_tx_inspect_handler() - Tx Inspect Handler
  2974. * @soc: datapath soc handle
  2975. * @vdev: datapath vdev handle
  2976. * @tx_desc: software descriptor head pointer
  2977. * @status : Tx completion status from HTT descriptor
  2978. *
  2979. * Handles Tx frames sent back to Host for inspection
  2980. * (ProxyARP)
  2981. *
  2982. * Return: none
  2983. */
  2984. static void dp_tx_inspect_handler(struct dp_soc *soc,
  2985. struct dp_vdev *vdev,
  2986. struct dp_tx_desc_s *tx_desc,
  2987. uint8_t *status)
  2988. {
  2989. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2990. "%s Tx inspect path",
  2991. __func__);
  2992. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  2993. qdf_nbuf_len(tx_desc->nbuf));
  2994. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2995. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2996. }
  2997. #ifdef MESH_MODE_SUPPORT
  2998. /**
  2999. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3000. * in mesh meta header
  3001. * @tx_desc: software descriptor head pointer
  3002. * @ts: pointer to tx completion stats
  3003. * Return: none
  3004. */
  3005. static
  3006. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3007. struct hal_tx_completion_status *ts)
  3008. {
  3009. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3010. if (!tx_desc->msdu_ext_desc) {
  3011. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3012. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3013. "netbuf %pK offset %d",
  3014. netbuf, tx_desc->pkt_offset);
  3015. return;
  3016. }
  3017. }
  3018. }
  3019. #else
  3020. static
  3021. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3022. struct hal_tx_completion_status *ts)
  3023. {
  3024. }
  3025. #endif
  3026. #ifdef QCA_PEER_EXT_STATS
  3027. /*
  3028. * dp_tx_compute_tid_delay() - Compute per TID delay
  3029. * @stats: Per TID delay stats
  3030. * @tx_desc: Software Tx descriptor
  3031. *
  3032. * Compute the software enqueue and hw enqueue delays and
  3033. * update the respective histograms
  3034. *
  3035. * Return: void
  3036. */
  3037. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3038. struct dp_tx_desc_s *tx_desc)
  3039. {
  3040. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3041. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3042. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3043. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3044. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3045. timestamp_hw_enqueue = tx_desc->timestamp;
  3046. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3047. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3048. timestamp_hw_enqueue);
  3049. /*
  3050. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3051. */
  3052. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3053. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3054. }
  3055. /*
  3056. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  3057. * @peer: DP peer context
  3058. * @tx_desc: Tx software descriptor
  3059. * @tid: Transmission ID
  3060. * @ring_id: Rx CPU context ID/CPU_ID
  3061. *
  3062. * Update the peer extended stats. These are enhanced other
  3063. * delay stats per msdu level.
  3064. *
  3065. * Return: void
  3066. */
  3067. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3068. struct dp_tx_desc_s *tx_desc,
  3069. uint8_t tid, uint8_t ring_id)
  3070. {
  3071. struct dp_pdev *pdev = peer->vdev->pdev;
  3072. struct dp_soc *soc = NULL;
  3073. struct cdp_peer_ext_stats *pext_stats = NULL;
  3074. soc = pdev->soc;
  3075. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3076. return;
  3077. pext_stats = peer->pext_stats;
  3078. qdf_assert(pext_stats);
  3079. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3080. /*
  3081. * For non-TID packets use the TID 9
  3082. */
  3083. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3084. tid = CDP_MAX_DATA_TIDS - 1;
  3085. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  3086. tx_desc);
  3087. }
  3088. #else
  3089. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  3090. struct dp_tx_desc_s *tx_desc,
  3091. uint8_t tid, uint8_t ring_id)
  3092. {
  3093. }
  3094. #endif
  3095. /**
  3096. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3097. * to pass in correct fields
  3098. *
  3099. * @vdev: pdev handle
  3100. * @tx_desc: tx descriptor
  3101. * @tid: tid value
  3102. * @ring_id: TCL or WBM ring number for transmit path
  3103. * Return: none
  3104. */
  3105. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  3106. struct dp_tx_desc_s *tx_desc,
  3107. uint8_t tid, uint8_t ring_id)
  3108. {
  3109. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3110. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3111. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  3112. return;
  3113. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3114. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3115. timestamp_hw_enqueue = tx_desc->timestamp;
  3116. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3117. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3118. timestamp_hw_enqueue);
  3119. interframe_delay = (uint32_t)(timestamp_ingress -
  3120. vdev->prev_tx_enq_tstamp);
  3121. /*
  3122. * Delay in software enqueue
  3123. */
  3124. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  3125. CDP_DELAY_STATS_SW_ENQ, ring_id);
  3126. /*
  3127. * Delay between packet enqueued to HW and Tx completion
  3128. */
  3129. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  3130. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  3131. /*
  3132. * Update interframe delay stats calculated at hardstart receive point.
  3133. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3134. * interframe delay will not be calculate correctly for 1st frame.
  3135. * On the other side, this will help in avoiding extra per packet check
  3136. * of !vdev->prev_tx_enq_tstamp.
  3137. */
  3138. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  3139. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  3140. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3141. }
  3142. #ifdef DISABLE_DP_STATS
  3143. static
  3144. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3145. {
  3146. }
  3147. #else
  3148. static
  3149. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  3150. {
  3151. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3152. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3153. if (subtype != QDF_PROTO_INVALID)
  3154. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  3155. }
  3156. #endif
  3157. /**
  3158. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  3159. * per wbm ring
  3160. *
  3161. * @tx_desc: software descriptor head pointer
  3162. * @ts: Tx completion status
  3163. * @peer: peer handle
  3164. * @ring_id: ring number
  3165. *
  3166. * Return: None
  3167. */
  3168. static inline void
  3169. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  3170. struct hal_tx_completion_status *ts,
  3171. struct dp_peer *peer, uint8_t ring_id)
  3172. {
  3173. struct dp_pdev *pdev = peer->vdev->pdev;
  3174. struct dp_soc *soc = NULL;
  3175. uint8_t mcs, pkt_type;
  3176. uint8_t tid = ts->tid;
  3177. uint32_t length;
  3178. struct cdp_tid_tx_stats *tid_stats;
  3179. if (!pdev)
  3180. return;
  3181. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3182. tid = CDP_MAX_DATA_TIDS - 1;
  3183. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3184. soc = pdev->soc;
  3185. mcs = ts->mcs;
  3186. pkt_type = ts->pkt_type;
  3187. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  3188. dp_err("Release source is not from TQM");
  3189. return;
  3190. }
  3191. length = qdf_nbuf_len(tx_desc->nbuf);
  3192. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  3193. if (qdf_unlikely(pdev->delay_stats_flag))
  3194. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  3195. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  3196. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  3197. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  3198. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3199. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  3200. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  3201. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  3202. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  3203. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  3204. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  3205. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  3206. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  3207. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  3208. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  3209. /*
  3210. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  3211. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  3212. * are no completions for failed cases. Hence updating tx_failed from
  3213. * data path. Please note that if tx_failed is fixed to be from ppdu,
  3214. * then this has to be removed
  3215. */
  3216. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  3217. peer->stats.tx.dropped.fw_rem_notx +
  3218. peer->stats.tx.dropped.fw_rem_tx +
  3219. peer->stats.tx.dropped.age_out +
  3220. peer->stats.tx.dropped.fw_reason1 +
  3221. peer->stats.tx.dropped.fw_reason2 +
  3222. peer->stats.tx.dropped.fw_reason3;
  3223. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  3224. tid_stats->tqm_status_cnt[ts->status]++;
  3225. }
  3226. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3227. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  3228. return;
  3229. }
  3230. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  3231. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  3232. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  3233. /*
  3234. * Following Rate Statistics are updated from HTT PPDU events from FW.
  3235. * Return from here if HTT PPDU events are enabled.
  3236. */
  3237. if (!(soc->process_tx_status))
  3238. return;
  3239. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3240. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  3241. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3242. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  3243. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3244. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3245. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3246. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  3247. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3248. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3249. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3250. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  3251. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3252. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3253. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3254. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  3255. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  3256. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3257. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  3258. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  3259. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  3260. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  3261. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  3262. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  3263. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  3264. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  3265. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  3266. if (ts->first_msdu)
  3267. DP_STATS_INCC(peer, tx.mpdu_success_with_retries,
  3268. qdf_do_div(ts->transmit_cnt, DP_RETRY_COUNT),
  3269. ts->transmit_cnt > DP_RETRY_COUNT);
  3270. }
  3271. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3272. /**
  3273. * dp_tx_flow_pool_lock() - take flow pool lock
  3274. * @soc: core txrx main context
  3275. * @tx_desc: tx desc
  3276. *
  3277. * Return: None
  3278. */
  3279. static inline
  3280. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  3281. struct dp_tx_desc_s *tx_desc)
  3282. {
  3283. struct dp_tx_desc_pool_s *pool;
  3284. uint8_t desc_pool_id;
  3285. desc_pool_id = tx_desc->pool_id;
  3286. pool = &soc->tx_desc[desc_pool_id];
  3287. qdf_spin_lock_bh(&pool->flow_pool_lock);
  3288. }
  3289. /**
  3290. * dp_tx_flow_pool_unlock() - release flow pool lock
  3291. * @soc: core txrx main context
  3292. * @tx_desc: tx desc
  3293. *
  3294. * Return: None
  3295. */
  3296. static inline
  3297. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  3298. struct dp_tx_desc_s *tx_desc)
  3299. {
  3300. struct dp_tx_desc_pool_s *pool;
  3301. uint8_t desc_pool_id;
  3302. desc_pool_id = tx_desc->pool_id;
  3303. pool = &soc->tx_desc[desc_pool_id];
  3304. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  3305. }
  3306. #else
  3307. static inline
  3308. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3309. {
  3310. }
  3311. static inline
  3312. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  3313. {
  3314. }
  3315. #endif
  3316. /**
  3317. * dp_tx_notify_completion() - Notify tx completion for this desc
  3318. * @soc: core txrx main context
  3319. * @vdev: datapath vdev handle
  3320. * @tx_desc: tx desc
  3321. * @netbuf: buffer
  3322. * @status: tx status
  3323. *
  3324. * Return: none
  3325. */
  3326. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  3327. struct dp_vdev *vdev,
  3328. struct dp_tx_desc_s *tx_desc,
  3329. qdf_nbuf_t netbuf,
  3330. uint8_t status)
  3331. {
  3332. void *osif_dev;
  3333. ol_txrx_completion_fp tx_compl_cbk = NULL;
  3334. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  3335. qdf_assert(tx_desc);
  3336. dp_tx_flow_pool_lock(soc, tx_desc);
  3337. if (!vdev ||
  3338. !vdev->osif_vdev) {
  3339. dp_tx_flow_pool_unlock(soc, tx_desc);
  3340. return;
  3341. }
  3342. osif_dev = vdev->osif_vdev;
  3343. tx_compl_cbk = vdev->tx_comp;
  3344. dp_tx_flow_pool_unlock(soc, tx_desc);
  3345. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3346. flag |= BIT(QDF_TX_RX_STATUS_OK);
  3347. if (tx_compl_cbk)
  3348. tx_compl_cbk(netbuf, osif_dev, flag);
  3349. }
  3350. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  3351. * @pdev: pdev handle
  3352. * @tid: tid value
  3353. * @txdesc_ts: timestamp from txdesc
  3354. * @ppdu_id: ppdu id
  3355. *
  3356. * Return: none
  3357. */
  3358. #ifdef FEATURE_PERPKT_INFO
  3359. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3360. struct dp_peer *peer,
  3361. uint8_t tid,
  3362. uint64_t txdesc_ts,
  3363. uint32_t ppdu_id)
  3364. {
  3365. uint64_t delta_ms;
  3366. struct cdp_tx_sojourn_stats *sojourn_stats;
  3367. if (qdf_unlikely(!pdev->enhanced_stats_en))
  3368. return;
  3369. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  3370. tid >= CDP_DATA_TID_MAX))
  3371. return;
  3372. if (qdf_unlikely(!pdev->sojourn_buf))
  3373. return;
  3374. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  3375. qdf_nbuf_data(pdev->sojourn_buf);
  3376. sojourn_stats->cookie = (void *)peer->rdkstats_ctx;
  3377. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  3378. txdesc_ts;
  3379. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  3380. delta_ms);
  3381. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  3382. sojourn_stats->num_msdus[tid] = 1;
  3383. sojourn_stats->avg_sojourn_msdu[tid].internal =
  3384. peer->avg_sojourn_msdu[tid].internal;
  3385. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  3386. pdev->sojourn_buf, HTT_INVALID_PEER,
  3387. WDI_NO_VAL, pdev->pdev_id);
  3388. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  3389. sojourn_stats->num_msdus[tid] = 0;
  3390. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  3391. }
  3392. #else
  3393. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  3394. struct dp_peer *peer,
  3395. uint8_t tid,
  3396. uint64_t txdesc_ts,
  3397. uint32_t ppdu_id)
  3398. {
  3399. }
  3400. #endif
  3401. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  3402. /**
  3403. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  3404. * @soc: dp_soc handle
  3405. * @desc: Tx Descriptor
  3406. * @ts: HAL Tx completion descriptor contents
  3407. *
  3408. * This function is used to send tx completion to packet capture
  3409. */
  3410. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  3411. struct dp_tx_desc_s *desc,
  3412. struct hal_tx_completion_status *ts)
  3413. {
  3414. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  3415. desc, ts->peer_id,
  3416. WDI_NO_VAL, desc->pdev->pdev_id);
  3417. }
  3418. #endif
  3419. /**
  3420. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  3421. * @soc: DP Soc handle
  3422. * @tx_desc: software Tx descriptor
  3423. * @ts : Tx completion status from HAL/HTT descriptor
  3424. *
  3425. * Return: none
  3426. */
  3427. static inline void
  3428. dp_tx_comp_process_desc(struct dp_soc *soc,
  3429. struct dp_tx_desc_s *desc,
  3430. struct hal_tx_completion_status *ts,
  3431. struct dp_peer *peer)
  3432. {
  3433. uint64_t time_latency = 0;
  3434. /*
  3435. * m_copy/tx_capture modes are not supported for
  3436. * scatter gather packets
  3437. */
  3438. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3439. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3440. desc->timestamp);
  3441. }
  3442. dp_send_completion_to_pkt_capture(soc, desc, ts);
  3443. if (!(desc->msdu_ext_desc)) {
  3444. dp_tx_enh_unmap(soc, desc);
  3445. if (QDF_STATUS_SUCCESS ==
  3446. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3447. return;
  3448. }
  3449. if (QDF_STATUS_SUCCESS ==
  3450. dp_get_completion_indication_for_stack(soc,
  3451. desc->pdev,
  3452. peer, ts,
  3453. desc->nbuf,
  3454. time_latency)) {
  3455. dp_send_completion_to_stack(soc,
  3456. desc->pdev,
  3457. ts->peer_id,
  3458. ts->ppdu_id,
  3459. desc->nbuf);
  3460. return;
  3461. }
  3462. }
  3463. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  3464. dp_tx_comp_free_buf(soc, desc);
  3465. }
  3466. #ifdef DISABLE_DP_STATS
  3467. /**
  3468. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3469. * @soc: core txrx main context
  3470. * @tx_desc: tx desc
  3471. * @status: tx status
  3472. *
  3473. * Return: none
  3474. */
  3475. static inline
  3476. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3477. struct dp_vdev *vdev,
  3478. struct dp_tx_desc_s *tx_desc,
  3479. uint8_t status)
  3480. {
  3481. }
  3482. #else
  3483. static inline
  3484. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3485. struct dp_vdev *vdev,
  3486. struct dp_tx_desc_s *tx_desc,
  3487. uint8_t status)
  3488. {
  3489. void *osif_dev;
  3490. ol_txrx_stats_rx_fp stats_cbk;
  3491. uint8_t pkt_type;
  3492. qdf_assert(tx_desc);
  3493. if (!vdev ||
  3494. !vdev->osif_vdev ||
  3495. !vdev->stats_cb)
  3496. return;
  3497. osif_dev = vdev->osif_vdev;
  3498. stats_cbk = vdev->stats_cb;
  3499. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3500. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3501. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3502. &pkt_type);
  3503. }
  3504. #endif
  3505. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  3506. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3507. uint32_t delta_tsf)
  3508. {
  3509. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3510. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3511. DP_MOD_ID_CDP);
  3512. if (!vdev) {
  3513. dp_err_rl("vdev %d does not exist", vdev_id);
  3514. return;
  3515. }
  3516. vdev->delta_tsf = delta_tsf;
  3517. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  3518. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3519. }
  3520. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  3521. uint8_t vdev_id, bool enable)
  3522. {
  3523. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3524. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3525. DP_MOD_ID_CDP);
  3526. if (!vdev) {
  3527. dp_err_rl("vdev %d does not exist", vdev_id);
  3528. return QDF_STATUS_E_FAILURE;
  3529. }
  3530. qdf_atomic_set(&vdev->ul_delay_report, enable);
  3531. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3532. return QDF_STATUS_SUCCESS;
  3533. }
  3534. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3535. uint32_t *val)
  3536. {
  3537. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3538. struct dp_vdev *vdev;
  3539. uint32_t delay_accum;
  3540. uint32_t pkts_accum;
  3541. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  3542. if (!vdev) {
  3543. dp_err_rl("vdev %d does not exist", vdev_id);
  3544. return QDF_STATUS_E_FAILURE;
  3545. }
  3546. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  3547. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3548. return QDF_STATUS_E_FAILURE;
  3549. }
  3550. /* Average uplink delay based on current accumulated values */
  3551. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  3552. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  3553. *val = delay_accum / pkts_accum;
  3554. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  3555. delay_accum, pkts_accum);
  3556. /* Reset accumulated values to 0 */
  3557. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  3558. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  3559. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  3560. return QDF_STATUS_SUCCESS;
  3561. }
  3562. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3563. struct hal_tx_completion_status *ts)
  3564. {
  3565. uint32_t buffer_ts;
  3566. uint32_t delta_tsf;
  3567. uint32_t ul_delay;
  3568. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  3569. if (!ts->valid)
  3570. return;
  3571. if (qdf_unlikely(!vdev)) {
  3572. dp_info_rl("vdev is null or delete in progrss");
  3573. return;
  3574. }
  3575. if (!qdf_atomic_read(&vdev->ul_delay_report))
  3576. return;
  3577. delta_tsf = vdev->delta_tsf;
  3578. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  3579. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  3580. * valid up to 29 bits.
  3581. */
  3582. buffer_ts = ts->buffer_timestamp << 10;
  3583. ul_delay = ts->tsf - buffer_ts - delta_tsf;
  3584. ul_delay &= 0x1FFFFFFF; /* mask 29 BITS */
  3585. if (ul_delay > 0x1000000) {
  3586. dp_info_rl("----------------------\n"
  3587. "Tx completion status:\n"
  3588. "----------------------\n"
  3589. "release_src = %d\n"
  3590. "ppdu_id = 0x%x\n"
  3591. "release_reason = %d\n"
  3592. "tsf = %u (0x%x)\n"
  3593. "buffer_timestamp = %u (0x%x)\n"
  3594. "delta_tsf = %u (0x%x)\n",
  3595. ts->release_src, ts->ppdu_id, ts->status,
  3596. ts->tsf, ts->tsf, ts->buffer_timestamp,
  3597. ts->buffer_timestamp, delta_tsf, delta_tsf);
  3598. return;
  3599. }
  3600. ul_delay /= 1000; /* in unit of ms */
  3601. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  3602. qdf_atomic_inc(&vdev->ul_pkts_accum);
  3603. }
  3604. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  3605. static inline
  3606. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  3607. struct hal_tx_completion_status *ts)
  3608. {
  3609. }
  3610. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  3611. /**
  3612. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3613. * @soc: DP soc handle
  3614. * @tx_desc: software descriptor head pointer
  3615. * @ts: Tx completion status
  3616. * @peer: peer handle
  3617. * @ring_id: ring number
  3618. *
  3619. * Return: none
  3620. */
  3621. static inline
  3622. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3623. struct dp_tx_desc_s *tx_desc,
  3624. struct hal_tx_completion_status *ts,
  3625. struct dp_peer *peer, uint8_t ring_id)
  3626. {
  3627. uint32_t length;
  3628. qdf_ether_header_t *eh;
  3629. struct dp_vdev *vdev = NULL;
  3630. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3631. enum qdf_dp_tx_rx_status dp_status;
  3632. if (!nbuf) {
  3633. dp_info_rl("invalid tx descriptor. nbuf NULL");
  3634. goto out;
  3635. }
  3636. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3637. length = qdf_nbuf_len(nbuf);
  3638. dp_status = dp_tx_hw_to_qdf(ts->status);
  3639. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3640. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3641. QDF_TRACE_DEFAULT_PDEV_ID,
  3642. qdf_nbuf_data_addr(nbuf),
  3643. sizeof(qdf_nbuf_data(nbuf)),
  3644. tx_desc->id, ts->status, dp_status));
  3645. dp_tx_comp_debug("-------------------- \n"
  3646. "Tx Completion Stats: \n"
  3647. "-------------------- \n"
  3648. "ack_frame_rssi = %d \n"
  3649. "first_msdu = %d \n"
  3650. "last_msdu = %d \n"
  3651. "msdu_part_of_amsdu = %d \n"
  3652. "rate_stats valid = %d \n"
  3653. "bw = %d \n"
  3654. "pkt_type = %d \n"
  3655. "stbc = %d \n"
  3656. "ldpc = %d \n"
  3657. "sgi = %d \n"
  3658. "mcs = %d \n"
  3659. "ofdma = %d \n"
  3660. "tones_in_ru = %d \n"
  3661. "tsf = %d \n"
  3662. "ppdu_id = %d \n"
  3663. "transmit_cnt = %d \n"
  3664. "tid = %d \n"
  3665. "peer_id = %d\n",
  3666. ts->ack_frame_rssi, ts->first_msdu,
  3667. ts->last_msdu, ts->msdu_part_of_amsdu,
  3668. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3669. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3670. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3671. ts->transmit_cnt, ts->tid, ts->peer_id);
  3672. /* Update SoC level stats */
  3673. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3674. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3675. if (!peer) {
  3676. dp_info_rl("peer is null or deletion in progress");
  3677. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3678. goto out;
  3679. }
  3680. vdev = peer->vdev;
  3681. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  3682. dp_tx_update_uplink_delay(soc, vdev, ts);
  3683. /* Update per-packet stats for mesh mode */
  3684. if (qdf_unlikely(vdev->mesh_vdev) &&
  3685. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3686. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3687. /* Update peer level stats */
  3688. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3689. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3690. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3691. if ((peer->vdev->tx_encap_type ==
  3692. htt_cmn_pkt_type_ethernet) &&
  3693. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3694. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3695. }
  3696. }
  3697. } else {
  3698. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3699. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3700. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3701. if (qdf_unlikely(peer->in_twt)) {
  3702. DP_STATS_INC_PKT(peer,
  3703. tx.tx_success_twt,
  3704. 1, length);
  3705. }
  3706. }
  3707. }
  3708. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3709. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3710. #ifdef QCA_SUPPORT_RDK_STATS
  3711. if (soc->rdkstats_enabled)
  3712. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3713. tx_desc->timestamp,
  3714. ts->ppdu_id);
  3715. #endif
  3716. out:
  3717. return;
  3718. }
  3719. /**
  3720. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3721. * @soc: core txrx main context
  3722. * @comp_head: software descriptor head pointer
  3723. * @ring_id: ring number
  3724. *
  3725. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3726. * and release the software descriptors after processing is complete
  3727. *
  3728. * Return: none
  3729. */
  3730. static void
  3731. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3732. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3733. {
  3734. struct dp_tx_desc_s *desc;
  3735. struct dp_tx_desc_s *next;
  3736. struct hal_tx_completion_status ts;
  3737. struct dp_peer *peer = NULL;
  3738. uint16_t peer_id = DP_INVALID_PEER;
  3739. qdf_nbuf_t netbuf;
  3740. desc = comp_head;
  3741. while (desc) {
  3742. if (peer_id != desc->peer_id) {
  3743. if (peer)
  3744. dp_peer_unref_delete(peer,
  3745. DP_MOD_ID_TX_COMP);
  3746. peer_id = desc->peer_id;
  3747. peer = dp_peer_get_ref_by_id(soc, peer_id,
  3748. DP_MOD_ID_TX_COMP);
  3749. }
  3750. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3751. struct dp_pdev *pdev = desc->pdev;
  3752. if (qdf_likely(peer)) {
  3753. /*
  3754. * Increment peer statistics
  3755. * Minimal statistics update done here
  3756. */
  3757. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3758. desc->length);
  3759. if (desc->tx_status !=
  3760. HAL_TX_TQM_RR_FRAME_ACKED)
  3761. DP_STATS_INC(peer, tx.tx_failed, 1);
  3762. }
  3763. qdf_assert(pdev);
  3764. dp_tx_outstanding_dec(pdev);
  3765. /*
  3766. * Calling a QDF WRAPPER here is creating signifcant
  3767. * performance impact so avoided the wrapper call here
  3768. */
  3769. next = desc->next;
  3770. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  3771. desc->id, DP_TX_COMP_UNMAP);
  3772. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  3773. desc->nbuf,
  3774. desc->dma_addr,
  3775. QDF_DMA_TO_DEVICE,
  3776. desc->length);
  3777. qdf_nbuf_free(desc->nbuf);
  3778. dp_tx_desc_free(soc, desc, desc->pool_id);
  3779. desc = next;
  3780. continue;
  3781. }
  3782. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3783. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3784. netbuf = desc->nbuf;
  3785. /* check tx complete notification */
  3786. if (peer && qdf_nbuf_tx_notify_comp_get(netbuf))
  3787. dp_tx_notify_completion(soc, peer->vdev, desc,
  3788. netbuf, ts.status);
  3789. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3790. next = desc->next;
  3791. dp_tx_desc_release(desc, desc->pool_id);
  3792. desc = next;
  3793. }
  3794. if (peer)
  3795. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3796. }
  3797. /**
  3798. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3799. * @soc: Handle to DP soc structure
  3800. * @tx_desc: software descriptor head pointer
  3801. * @status : Tx completion status from HTT descriptor
  3802. * @ring_id: ring number
  3803. *
  3804. * This function will process HTT Tx indication messages from Target
  3805. *
  3806. * Return: none
  3807. */
  3808. static
  3809. void dp_tx_process_htt_completion(struct dp_soc *soc,
  3810. struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3811. uint8_t ring_id)
  3812. {
  3813. uint8_t tx_status;
  3814. struct dp_pdev *pdev;
  3815. struct dp_vdev *vdev;
  3816. struct hal_tx_completion_status ts = {0};
  3817. uint32_t *htt_desc = (uint32_t *)status;
  3818. struct dp_peer *peer;
  3819. struct cdp_tid_tx_stats *tid_stats = NULL;
  3820. struct htt_soc *htt_handle;
  3821. uint8_t vdev_id;
  3822. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3823. htt_handle = (struct htt_soc *)soc->htt_handle;
  3824. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3825. /*
  3826. * There can be scenario where WBM consuming descriptor enqueued
  3827. * from TQM2WBM first and TQM completion can happen before MEC
  3828. * notification comes from FW2WBM. Avoid access any field of tx
  3829. * descriptor in case of MEC notify.
  3830. */
  3831. if (tx_status == HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY) {
  3832. qdf_assert_always(!soc->mec_fw_offload);
  3833. /*
  3834. * Get vdev id from HTT status word in case of MEC
  3835. * notification
  3836. */
  3837. vdev_id = HTT_TX_WBM_COMPLETION_V2_VDEV_ID_GET(htt_desc[3]);
  3838. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3839. return;
  3840. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3841. DP_MOD_ID_HTT_COMP);
  3842. if (!vdev)
  3843. return;
  3844. dp_tx_mec_handler(vdev, status);
  3845. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3846. return;
  3847. }
  3848. /*
  3849. * If the descriptor is already freed in vdev_detach,
  3850. * continue to next descriptor
  3851. */
  3852. if ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) && !tx_desc->flags) {
  3853. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d", tx_desc->id);
  3854. return;
  3855. }
  3856. pdev = tx_desc->pdev;
  3857. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3858. dp_tx_comp_info_rl("pdev in down state %d", tx_desc->id);
  3859. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  3860. dp_tx_comp_free_buf(soc, tx_desc);
  3861. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3862. return;
  3863. }
  3864. qdf_assert(tx_desc->pdev);
  3865. vdev_id = tx_desc->vdev_id;
  3866. vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3867. DP_MOD_ID_HTT_COMP);
  3868. if (!vdev)
  3869. return;
  3870. switch (tx_status) {
  3871. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3872. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3873. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3874. {
  3875. uint8_t tid;
  3876. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3877. ts.peer_id =
  3878. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3879. htt_desc[2]);
  3880. ts.tid =
  3881. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3882. htt_desc[2]);
  3883. } else {
  3884. ts.peer_id = HTT_INVALID_PEER;
  3885. ts.tid = HTT_INVALID_TID;
  3886. }
  3887. ts.ppdu_id =
  3888. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3889. htt_desc[1]);
  3890. ts.ack_frame_rssi =
  3891. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3892. htt_desc[1]);
  3893. ts.tsf = htt_desc[3];
  3894. ts.first_msdu = 1;
  3895. ts.last_msdu = 1;
  3896. tid = ts.tid;
  3897. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3898. tid = CDP_MAX_DATA_TIDS - 1;
  3899. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3900. if (qdf_unlikely(pdev->delay_stats_flag))
  3901. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3902. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3903. tid_stats->htt_status_cnt[tx_status]++;
  3904. }
  3905. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3906. DP_MOD_ID_HTT_COMP);
  3907. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3908. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3909. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3910. if (qdf_likely(peer))
  3911. dp_peer_unref_delete(peer, DP_MOD_ID_HTT_COMP);
  3912. break;
  3913. }
  3914. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3915. {
  3916. dp_tx_reinject_handler(soc, vdev, tx_desc, status);
  3917. break;
  3918. }
  3919. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3920. {
  3921. dp_tx_inspect_handler(soc, vdev, tx_desc, status);
  3922. break;
  3923. }
  3924. case HTT_TX_FW2WBM_TX_STATUS_VDEVID_MISMATCH:
  3925. {
  3926. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3927. goto release_tx_desc;
  3928. }
  3929. default:
  3930. dp_tx_comp_err("Invalid HTT tx_status %d\n",
  3931. tx_status);
  3932. goto release_tx_desc;
  3933. }
  3934. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3935. return;
  3936. release_tx_desc:
  3937. dp_tx_comp_free_buf(soc, tx_desc);
  3938. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3939. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_HTT_COMP);
  3940. }
  3941. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3942. static inline
  3943. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3944. int max_reap_limit)
  3945. {
  3946. bool limit_hit = false;
  3947. limit_hit =
  3948. (num_reaped >= max_reap_limit) ? true : false;
  3949. if (limit_hit)
  3950. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3951. return limit_hit;
  3952. }
  3953. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3954. {
  3955. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3956. }
  3957. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3958. {
  3959. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3960. return cfg->tx_comp_loop_pkt_limit;
  3961. }
  3962. #else
  3963. static inline
  3964. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  3965. int max_reap_limit)
  3966. {
  3967. return false;
  3968. }
  3969. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3970. {
  3971. return false;
  3972. }
  3973. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  3974. {
  3975. return 0;
  3976. }
  3977. #endif
  3978. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  3979. static inline int
  3980. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3981. int *max_reap_limit)
  3982. {
  3983. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  3984. max_reap_limit);
  3985. }
  3986. #else
  3987. static inline int
  3988. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  3989. int *max_reap_limit)
  3990. {
  3991. return 0;
  3992. }
  3993. #endif
  3994. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3995. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3996. uint32_t quota)
  3997. {
  3998. void *tx_comp_hal_desc;
  3999. uint8_t buffer_src;
  4000. struct dp_tx_desc_s *tx_desc = NULL;
  4001. struct dp_tx_desc_s *head_desc = NULL;
  4002. struct dp_tx_desc_s *tail_desc = NULL;
  4003. uint32_t num_processed = 0;
  4004. uint32_t count;
  4005. uint32_t num_avail_for_reap = 0;
  4006. bool force_break = false;
  4007. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  4008. int max_reap_limit, ring_near_full;
  4009. DP_HIST_INIT();
  4010. more_data:
  4011. /* Re-initialize local variables to be re-used */
  4012. head_desc = NULL;
  4013. tail_desc = NULL;
  4014. count = 0;
  4015. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  4016. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  4017. &max_reap_limit);
  4018. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  4019. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  4020. return 0;
  4021. }
  4022. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  4023. if (num_avail_for_reap >= quota)
  4024. num_avail_for_reap = quota;
  4025. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  4026. /* Find head descriptor from completion ring */
  4027. while (qdf_likely(num_avail_for_reap--)) {
  4028. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  4029. if (qdf_unlikely(!tx_comp_hal_desc))
  4030. break;
  4031. buffer_src = hal_tx_comp_get_buffer_source(soc->hal_soc,
  4032. tx_comp_hal_desc);
  4033. /* If this buffer was not released by TQM or FW, then it is not
  4034. * Tx completion indication, assert */
  4035. if (qdf_unlikely(buffer_src !=
  4036. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  4037. (qdf_unlikely(buffer_src !=
  4038. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  4039. uint8_t wbm_internal_error;
  4040. dp_err_rl(
  4041. "Tx comp release_src != TQM | FW but from %d",
  4042. buffer_src);
  4043. hal_dump_comp_desc(tx_comp_hal_desc);
  4044. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  4045. /* When WBM sees NULL buffer_addr_info in any of
  4046. * ingress rings it sends an error indication,
  4047. * with wbm_internal_error=1, to a specific ring.
  4048. * The WBM2SW ring used to indicate these errors is
  4049. * fixed in HW, and that ring is being used as Tx
  4050. * completion ring. These errors are not related to
  4051. * Tx completions, and should just be ignored
  4052. */
  4053. wbm_internal_error = hal_get_wbm_internal_error(
  4054. soc->hal_soc,
  4055. tx_comp_hal_desc);
  4056. if (wbm_internal_error) {
  4057. dp_err_rl("Tx comp wbm_internal_error!!");
  4058. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  4059. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  4060. buffer_src)
  4061. dp_handle_wbm_internal_error(
  4062. soc,
  4063. tx_comp_hal_desc,
  4064. hal_tx_comp_get_buffer_type(
  4065. tx_comp_hal_desc));
  4066. } else {
  4067. dp_err_rl("Tx comp wbm_internal_error false");
  4068. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  4069. }
  4070. continue;
  4071. }
  4072. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  4073. tx_comp_hal_desc,
  4074. &tx_desc);
  4075. if (!tx_desc) {
  4076. dp_err("unable to retrieve tx_desc!");
  4077. QDF_BUG(0);
  4078. continue;
  4079. }
  4080. tx_desc->buffer_src = buffer_src;
  4081. /*
  4082. * If the release source is FW, process the HTT status
  4083. */
  4084. if (qdf_unlikely(buffer_src ==
  4085. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  4086. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  4087. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  4088. htt_tx_status);
  4089. dp_tx_process_htt_completion(soc, tx_desc,
  4090. htt_tx_status, ring_id);
  4091. } else {
  4092. tx_desc->tx_status =
  4093. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  4094. tx_desc->buffer_src = buffer_src;
  4095. /*
  4096. * If the fast completion mode is enabled extended
  4097. * metadata from descriptor is not copied
  4098. */
  4099. if (qdf_likely(tx_desc->flags &
  4100. DP_TX_DESC_FLAG_SIMPLE))
  4101. goto add_to_pool;
  4102. /*
  4103. * If the descriptor is already freed in vdev_detach,
  4104. * continue to next descriptor
  4105. */
  4106. if (qdf_unlikely
  4107. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  4108. !tx_desc->flags)) {
  4109. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  4110. tx_desc->id);
  4111. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  4112. continue;
  4113. }
  4114. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  4115. dp_tx_comp_info_rl("pdev in down state %d",
  4116. tx_desc->id);
  4117. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  4118. dp_tx_comp_free_buf(soc, tx_desc);
  4119. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  4120. goto next_desc;
  4121. }
  4122. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  4123. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  4124. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  4125. tx_desc->flags, tx_desc->id);
  4126. qdf_assert_always(0);
  4127. }
  4128. /* Collect hw completion contents */
  4129. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  4130. &tx_desc->comp, 1);
  4131. add_to_pool:
  4132. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  4133. /* First ring descriptor on the cycle */
  4134. if (!head_desc) {
  4135. head_desc = tx_desc;
  4136. tail_desc = tx_desc;
  4137. }
  4138. tail_desc->next = tx_desc;
  4139. tx_desc->next = NULL;
  4140. tail_desc = tx_desc;
  4141. }
  4142. next_desc:
  4143. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  4144. /*
  4145. * Processed packet count is more than given quota
  4146. * stop to processing
  4147. */
  4148. count++;
  4149. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  4150. break;
  4151. }
  4152. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  4153. /* Process the reaped descriptors */
  4154. if (head_desc)
  4155. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  4156. /*
  4157. * If we are processing in near-full condition, there are 3 scenario
  4158. * 1) Ring entries has reached critical state
  4159. * 2) Ring entries are still near high threshold
  4160. * 3) Ring entries are below the safe level
  4161. *
  4162. * One more loop will move te state to normal processing and yield
  4163. */
  4164. if (ring_near_full)
  4165. goto more_data;
  4166. if (dp_tx_comp_enable_eol_data_check(soc)) {
  4167. if (num_processed >= quota)
  4168. force_break = true;
  4169. if (!force_break &&
  4170. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  4171. hal_ring_hdl)) {
  4172. DP_STATS_INC(soc, tx.hp_oos2, 1);
  4173. if (!hif_exec_should_yield(soc->hif_handle,
  4174. int_ctx->dp_intr_id))
  4175. goto more_data;
  4176. }
  4177. }
  4178. DP_TX_HIST_STATS_PER_PDEV();
  4179. return num_processed;
  4180. }
  4181. #ifdef FEATURE_WLAN_TDLS
  4182. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4183. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  4184. {
  4185. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4186. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4187. DP_MOD_ID_TDLS);
  4188. if (!vdev) {
  4189. dp_err("vdev handle for id %d is NULL", vdev_id);
  4190. return NULL;
  4191. }
  4192. if (tx_spec & OL_TX_SPEC_NO_FREE)
  4193. vdev->is_tdls_frame = true;
  4194. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  4195. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  4196. }
  4197. #endif
  4198. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  4199. {
  4200. struct wlan_cfg_dp_soc_ctxt *cfg;
  4201. struct dp_soc *soc;
  4202. soc = vdev->pdev->soc;
  4203. if (!soc)
  4204. return;
  4205. cfg = soc->wlan_cfg_ctx;
  4206. if (!cfg)
  4207. return;
  4208. if (vdev->opmode == wlan_op_mode_ndi)
  4209. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  4210. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  4211. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  4212. (vdev->subtype == wlan_op_subtype_p2p_go))
  4213. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  4214. else
  4215. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  4216. }
  4217. /**
  4218. * dp_tx_vdev_attach() - attach vdev to dp tx
  4219. * @vdev: virtual device instance
  4220. *
  4221. * Return: QDF_STATUS_SUCCESS: success
  4222. * QDF_STATUS_E_RESOURCES: Error return
  4223. */
  4224. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  4225. {
  4226. int pdev_id;
  4227. /*
  4228. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  4229. */
  4230. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  4231. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  4232. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  4233. vdev->vdev_id);
  4234. pdev_id =
  4235. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  4236. vdev->pdev->pdev_id);
  4237. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  4238. /*
  4239. * Set HTT Extension Valid bit to 0 by default
  4240. */
  4241. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  4242. dp_tx_vdev_update_search_flags(vdev);
  4243. dp_tx_vdev_update_feature_flags(vdev);
  4244. return QDF_STATUS_SUCCESS;
  4245. }
  4246. #ifndef FEATURE_WDS
  4247. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  4248. {
  4249. return false;
  4250. }
  4251. #endif
  4252. /**
  4253. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  4254. * @vdev: virtual device instance
  4255. *
  4256. * Return: void
  4257. *
  4258. */
  4259. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  4260. {
  4261. struct dp_soc *soc = vdev->pdev->soc;
  4262. /*
  4263. * Enable both AddrY (SA based search) and AddrX (Da based search)
  4264. * for TDLS link
  4265. *
  4266. * Enable AddrY (SA based search) only for non-WDS STA and
  4267. * ProxySTA VAP (in HKv1) modes.
  4268. *
  4269. * In all other VAP modes, only DA based search should be
  4270. * enabled
  4271. */
  4272. if (vdev->opmode == wlan_op_mode_sta &&
  4273. vdev->tdls_link_connected)
  4274. vdev->hal_desc_addr_search_flags =
  4275. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  4276. else if ((vdev->opmode == wlan_op_mode_sta) &&
  4277. !dp_tx_da_search_override(vdev))
  4278. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  4279. else
  4280. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  4281. if (vdev->opmode == wlan_op_mode_sta)
  4282. vdev->search_type = soc->sta_mode_search_policy;
  4283. else
  4284. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  4285. }
  4286. static inline bool
  4287. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  4288. struct dp_vdev *vdev,
  4289. struct dp_tx_desc_s *tx_desc)
  4290. {
  4291. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  4292. return false;
  4293. /*
  4294. * if vdev is given, then only check whether desc
  4295. * vdev match. if vdev is NULL, then check whether
  4296. * desc pdev match.
  4297. */
  4298. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  4299. (tx_desc->pdev == pdev);
  4300. }
  4301. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4302. /**
  4303. * dp_tx_desc_flush() - release resources associated
  4304. * to TX Desc
  4305. *
  4306. * @dp_pdev: Handle to DP pdev structure
  4307. * @vdev: virtual device instance
  4308. * NULL: no specific Vdev is required and check all allcated TX desc
  4309. * on this pdev.
  4310. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  4311. *
  4312. * @force_free:
  4313. * true: flush the TX desc.
  4314. * false: only reset the Vdev in each allocated TX desc
  4315. * that associated to current Vdev.
  4316. *
  4317. * This function will go through the TX desc pool to flush
  4318. * the outstanding TX data or reset Vdev to NULL in associated TX
  4319. * Desc.
  4320. */
  4321. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4322. bool force_free)
  4323. {
  4324. uint8_t i;
  4325. uint32_t j;
  4326. uint32_t num_desc, page_id, offset;
  4327. uint16_t num_desc_per_page;
  4328. struct dp_soc *soc = pdev->soc;
  4329. struct dp_tx_desc_s *tx_desc = NULL;
  4330. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4331. if (!vdev && !force_free) {
  4332. dp_err("Reset TX desc vdev, Vdev param is required!");
  4333. return;
  4334. }
  4335. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  4336. tx_desc_pool = &soc->tx_desc[i];
  4337. if (!(tx_desc_pool->pool_size) ||
  4338. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  4339. !(tx_desc_pool->desc_pages.cacheable_pages))
  4340. continue;
  4341. /*
  4342. * Add flow pool lock protection in case pool is freed
  4343. * due to all tx_desc is recycled when handle TX completion.
  4344. * this is not necessary when do force flush as:
  4345. * a. double lock will happen if dp_tx_desc_release is
  4346. * also trying to acquire it.
  4347. * b. dp interrupt has been disabled before do force TX desc
  4348. * flush in dp_pdev_deinit().
  4349. */
  4350. if (!force_free)
  4351. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  4352. num_desc = tx_desc_pool->pool_size;
  4353. num_desc_per_page =
  4354. tx_desc_pool->desc_pages.num_element_per_page;
  4355. for (j = 0; j < num_desc; j++) {
  4356. page_id = j / num_desc_per_page;
  4357. offset = j % num_desc_per_page;
  4358. if (qdf_unlikely(!(tx_desc_pool->
  4359. desc_pages.cacheable_pages)))
  4360. break;
  4361. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4362. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4363. /*
  4364. * Free TX desc if force free is
  4365. * required, otherwise only reset vdev
  4366. * in this TX desc.
  4367. */
  4368. if (force_free) {
  4369. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4370. dp_tx_comp_free_buf(soc, tx_desc);
  4371. dp_tx_desc_release(tx_desc, i);
  4372. } else {
  4373. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4374. }
  4375. }
  4376. }
  4377. if (!force_free)
  4378. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  4379. }
  4380. }
  4381. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4382. /**
  4383. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  4384. *
  4385. * @soc: Handle to DP soc structure
  4386. * @tx_desc: pointer of one TX desc
  4387. * @desc_pool_id: TX Desc pool id
  4388. */
  4389. static inline void
  4390. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  4391. uint8_t desc_pool_id)
  4392. {
  4393. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  4394. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  4395. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  4396. }
  4397. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  4398. bool force_free)
  4399. {
  4400. uint8_t i, num_pool;
  4401. uint32_t j;
  4402. uint32_t num_desc, page_id, offset;
  4403. uint16_t num_desc_per_page;
  4404. struct dp_soc *soc = pdev->soc;
  4405. struct dp_tx_desc_s *tx_desc = NULL;
  4406. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  4407. if (!vdev && !force_free) {
  4408. dp_err("Reset TX desc vdev, Vdev param is required!");
  4409. return;
  4410. }
  4411. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4412. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4413. for (i = 0; i < num_pool; i++) {
  4414. tx_desc_pool = &soc->tx_desc[i];
  4415. if (!tx_desc_pool->desc_pages.cacheable_pages)
  4416. continue;
  4417. num_desc_per_page =
  4418. tx_desc_pool->desc_pages.num_element_per_page;
  4419. for (j = 0; j < num_desc; j++) {
  4420. page_id = j / num_desc_per_page;
  4421. offset = j % num_desc_per_page;
  4422. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  4423. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  4424. if (force_free) {
  4425. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  4426. dp_tx_comp_free_buf(soc, tx_desc);
  4427. dp_tx_desc_release(tx_desc, i);
  4428. } else {
  4429. dp_tx_desc_reset_vdev(soc, tx_desc,
  4430. i);
  4431. }
  4432. }
  4433. }
  4434. }
  4435. }
  4436. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4437. /**
  4438. * dp_tx_vdev_detach() - detach vdev from dp tx
  4439. * @vdev: virtual device instance
  4440. *
  4441. * Return: QDF_STATUS_SUCCESS: success
  4442. * QDF_STATUS_E_RESOURCES: Error return
  4443. */
  4444. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  4445. {
  4446. struct dp_pdev *pdev = vdev->pdev;
  4447. /* Reset TX desc associated to this Vdev as NULL */
  4448. dp_tx_desc_flush(pdev, vdev, false);
  4449. return QDF_STATUS_SUCCESS;
  4450. }
  4451. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4452. /* Pools will be allocated dynamically */
  4453. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4454. int num_desc)
  4455. {
  4456. uint8_t i;
  4457. for (i = 0; i < num_pool; i++) {
  4458. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  4459. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  4460. }
  4461. return QDF_STATUS_SUCCESS;
  4462. }
  4463. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4464. int num_desc)
  4465. {
  4466. return QDF_STATUS_SUCCESS;
  4467. }
  4468. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4469. {
  4470. }
  4471. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4472. {
  4473. uint8_t i;
  4474. for (i = 0; i < num_pool; i++)
  4475. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  4476. }
  4477. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  4478. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  4479. int num_desc)
  4480. {
  4481. uint8_t i, count;
  4482. /* Allocate software Tx descriptor pools */
  4483. for (i = 0; i < num_pool; i++) {
  4484. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  4485. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4486. FL("Tx Desc Pool alloc %d failed %pK"),
  4487. i, soc);
  4488. goto fail;
  4489. }
  4490. }
  4491. return QDF_STATUS_SUCCESS;
  4492. fail:
  4493. for (count = 0; count < i; count++)
  4494. dp_tx_desc_pool_free(soc, count);
  4495. return QDF_STATUS_E_NOMEM;
  4496. }
  4497. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  4498. int num_desc)
  4499. {
  4500. uint8_t i;
  4501. for (i = 0; i < num_pool; i++) {
  4502. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  4503. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4504. FL("Tx Desc Pool init %d failed %pK"),
  4505. i, soc);
  4506. return QDF_STATUS_E_NOMEM;
  4507. }
  4508. }
  4509. return QDF_STATUS_SUCCESS;
  4510. }
  4511. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  4512. {
  4513. uint8_t i;
  4514. for (i = 0; i < num_pool; i++)
  4515. dp_tx_desc_pool_deinit(soc, i);
  4516. }
  4517. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  4518. {
  4519. uint8_t i;
  4520. for (i = 0; i < num_pool; i++)
  4521. dp_tx_desc_pool_free(soc, i);
  4522. }
  4523. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  4524. /**
  4525. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  4526. * @soc: core txrx main context
  4527. * @num_pool: number of pools
  4528. *
  4529. */
  4530. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  4531. {
  4532. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  4533. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  4534. }
  4535. /**
  4536. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  4537. * @soc: core txrx main context
  4538. * @num_pool: number of pools
  4539. *
  4540. */
  4541. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  4542. {
  4543. dp_tx_tso_desc_pool_free(soc, num_pool);
  4544. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  4545. }
  4546. /**
  4547. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  4548. * @soc: core txrx main context
  4549. *
  4550. * This function frees all tx related descriptors as below
  4551. * 1. Regular TX descriptors (static pools)
  4552. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4553. * 3. TSO descriptors
  4554. *
  4555. */
  4556. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  4557. {
  4558. uint8_t num_pool;
  4559. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4560. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4561. dp_tx_ext_desc_pool_free(soc, num_pool);
  4562. dp_tx_delete_static_pools(soc, num_pool);
  4563. }
  4564. /**
  4565. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  4566. * @soc: core txrx main context
  4567. *
  4568. * This function de-initializes all tx related descriptors as below
  4569. * 1. Regular TX descriptors (static pools)
  4570. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4571. * 3. TSO descriptors
  4572. *
  4573. */
  4574. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4575. {
  4576. uint8_t num_pool;
  4577. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4578. dp_tx_flow_control_deinit(soc);
  4579. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4580. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4581. dp_tx_deinit_static_pools(soc, num_pool);
  4582. }
  4583. /**
  4584. * dp_tso_attach() - TSO attach handler
  4585. * @txrx_soc: Opaque Dp handle
  4586. *
  4587. * Reserve TSO descriptor buffers
  4588. *
  4589. * Return: QDF_STATUS_E_FAILURE on failure or
  4590. * QDF_STATUS_SUCCESS on success
  4591. */
  4592. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4593. uint8_t num_pool,
  4594. uint16_t num_desc)
  4595. {
  4596. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4597. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4598. return QDF_STATUS_E_FAILURE;
  4599. }
  4600. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4601. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4602. num_pool, soc);
  4603. return QDF_STATUS_E_FAILURE;
  4604. }
  4605. return QDF_STATUS_SUCCESS;
  4606. }
  4607. /**
  4608. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4609. * @soc: DP soc handle
  4610. * @num_pool: Number of pools
  4611. * @num_desc: Number of descriptors
  4612. *
  4613. * Initialize TSO descriptor pools
  4614. *
  4615. * Return: QDF_STATUS_E_FAILURE on failure or
  4616. * QDF_STATUS_SUCCESS on success
  4617. */
  4618. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4619. uint8_t num_pool,
  4620. uint16_t num_desc)
  4621. {
  4622. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4623. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4624. return QDF_STATUS_E_FAILURE;
  4625. }
  4626. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4627. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4628. num_pool, soc);
  4629. return QDF_STATUS_E_FAILURE;
  4630. }
  4631. return QDF_STATUS_SUCCESS;
  4632. }
  4633. /**
  4634. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4635. * @soc: core txrx main context
  4636. *
  4637. * This function allocates memory for following descriptor pools
  4638. * 1. regular sw tx descriptor pools (static pools)
  4639. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4640. * 3. TSO descriptor pools
  4641. *
  4642. * Return: QDF_STATUS_SUCCESS: success
  4643. * QDF_STATUS_E_RESOURCES: Error return
  4644. */
  4645. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4646. {
  4647. uint8_t num_pool;
  4648. uint32_t num_desc;
  4649. uint32_t num_ext_desc;
  4650. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4651. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4652. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4653. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4654. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4655. __func__, num_pool, num_desc);
  4656. if ((num_pool > MAX_TXDESC_POOLS) ||
  4657. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4658. goto fail1;
  4659. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4660. goto fail1;
  4661. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4662. goto fail2;
  4663. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4664. return QDF_STATUS_SUCCESS;
  4665. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4666. goto fail3;
  4667. return QDF_STATUS_SUCCESS;
  4668. fail3:
  4669. dp_tx_ext_desc_pool_free(soc, num_pool);
  4670. fail2:
  4671. dp_tx_delete_static_pools(soc, num_pool);
  4672. fail1:
  4673. return QDF_STATUS_E_RESOURCES;
  4674. }
  4675. /**
  4676. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4677. * @soc: core txrx main context
  4678. *
  4679. * This function initializes the following TX descriptor pools
  4680. * 1. regular sw tx descriptor pools (static pools)
  4681. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4682. * 3. TSO descriptor pools
  4683. *
  4684. * Return: QDF_STATUS_SUCCESS: success
  4685. * QDF_STATUS_E_RESOURCES: Error return
  4686. */
  4687. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4688. {
  4689. uint8_t num_pool;
  4690. uint32_t num_desc;
  4691. uint32_t num_ext_desc;
  4692. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4693. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4694. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4695. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4696. goto fail1;
  4697. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4698. goto fail2;
  4699. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4700. return QDF_STATUS_SUCCESS;
  4701. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4702. goto fail3;
  4703. dp_tx_flow_control_init(soc);
  4704. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4705. return QDF_STATUS_SUCCESS;
  4706. fail3:
  4707. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4708. fail2:
  4709. dp_tx_deinit_static_pools(soc, num_pool);
  4710. fail1:
  4711. return QDF_STATUS_E_RESOURCES;
  4712. }
  4713. /**
  4714. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4715. * @txrx_soc: dp soc handle
  4716. *
  4717. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4718. * QDF_STATUS_E_FAILURE
  4719. */
  4720. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4721. {
  4722. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4723. uint8_t num_pool;
  4724. uint32_t num_desc;
  4725. uint32_t num_ext_desc;
  4726. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4727. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4728. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4729. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4730. return QDF_STATUS_E_FAILURE;
  4731. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4732. return QDF_STATUS_E_FAILURE;
  4733. return QDF_STATUS_SUCCESS;
  4734. }
  4735. /**
  4736. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4737. * @txrx_soc: dp soc handle
  4738. *
  4739. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4740. */
  4741. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4742. {
  4743. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4744. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4745. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4746. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4747. return QDF_STATUS_SUCCESS;
  4748. }