3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
119 lines
3.0 KiB
C
119 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "dsi-phy-timing:" fmt
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#include "dsi_phy_timing_calc.h"
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void dsi_phy_hw_v2_0_get_default_phy_params(struct phy_clk_params *params)
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{
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params->clk_prep_buf = 50;
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params->clk_zero_buf = 2;
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params->clk_trail_buf = 30;
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params->hs_prep_buf = 50;
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params->hs_zero_buf = 10;
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params->hs_trail_buf = 30;
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params->hs_rqst_buf = 0;
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params->hs_exit_buf = 10;
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}
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int32_t dsi_phy_hw_v2_0_calc_clk_zero(s64 rec_temp1, s64 mult)
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{
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s64 rec_temp2, rec_temp3;
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rec_temp2 = (rec_temp1 - (11 * mult));
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rec_temp3 = roundup64(div_s64(rec_temp2, 8), mult);
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return (div_s64(rec_temp3, mult) - 3);
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}
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int32_t dsi_phy_hw_v2_0_calc_clk_trail_rec_min(s64 temp_mul,
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s64 frac, s64 mult)
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{
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s64 rec_temp1, rec_temp2, rec_temp3;
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rec_temp1 = temp_mul + frac + (3 * mult);
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rec_temp2 = div_s64(rec_temp1, 8);
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rec_temp3 = roundup64(rec_temp2, mult);
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return div_s64(rec_temp3, mult);
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}
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int32_t dsi_phy_hw_v2_0_calc_clk_trail_rec_max(s64 temp1, s64 mult)
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{
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s64 rec_temp2, rec_temp3;
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rec_temp2 = temp1 + (3 * mult);
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rec_temp3 = rec_temp2 / 8;
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return div_s64(rec_temp3, mult);
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}
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int32_t dsi_phy_hw_v2_0_calc_hs_zero(s64 temp1, s64 mult)
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{
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s64 rec_temp2, rec_temp3, rec_min;
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rec_temp2 = temp1 - (11 * mult);
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rec_temp3 = roundup64((rec_temp2 / 8), mult);
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rec_min = rec_temp3 - (3 * mult);
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return div_s64(rec_min, mult);
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}
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void dsi_phy_hw_v2_0_calc_hs_trail(struct phy_clk_params *clk_params,
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struct phy_timing_desc *desc)
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{
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s64 rec_temp1;
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struct timing_entry *t = &desc->hs_trail;
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t->rec_min = DIV_ROUND_UP(
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((t->mipi_min * clk_params->bitclk_mbps) +
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(3 * clk_params->tlpx_numer_ns)),
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(8 * clk_params->tlpx_numer_ns));
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rec_temp1 = ((t->mipi_max * clk_params->bitclk_mbps) +
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(3 * clk_params->tlpx_numer_ns));
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t->rec_max = DIV_ROUND_UP_ULL(rec_temp1,
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(8 * clk_params->tlpx_numer_ns));
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}
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void dsi_phy_hw_v2_0_update_timing_params(
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struct dsi_phy_per_lane_cfgs *timing,
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struct phy_timing_desc *desc)
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{
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int i = 0;
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for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
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timing->lane[i][0] = desc->hs_exit.reg_value;
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if (i == DSI_LOGICAL_CLOCK_LANE)
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timing->lane[i][1] = desc->clk_zero.reg_value;
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else
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timing->lane[i][1] = desc->hs_zero.reg_value;
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if (i == DSI_LOGICAL_CLOCK_LANE)
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timing->lane[i][2] = desc->clk_prepare.reg_value;
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else
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timing->lane[i][2] = desc->hs_prepare.reg_value;
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if (i == DSI_LOGICAL_CLOCK_LANE)
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timing->lane[i][3] = desc->clk_trail.reg_value;
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else
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timing->lane[i][3] = desc->hs_trail.reg_value;
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if (i == DSI_LOGICAL_CLOCK_LANE)
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timing->lane[i][4] = desc->hs_rqst_clk.reg_value;
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else
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timing->lane[i][4] = desc->hs_rqst.reg_value;
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timing->lane[i][5] = 0x2;
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timing->lane[i][6] = 0x4;
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timing->lane[i][7] = 0xA0;
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pr_debug("[%d][%d %d %d %d %d]\n", i, timing->lane[i][0],
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timing->lane[i][1],
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timing->lane[i][2],
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timing->lane[i][3],
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timing->lane[i][4]);
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}
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timing->count_per_lane = 8;
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}
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