3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
150 baris
4.0 KiB
C
150 baris
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "dsi-hw:" fmt
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#include "dsi_ctrl_hw.h"
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#include "dsi_ctrl_reg.h"
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#include "dsi_hw.h"
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#include "dsi_catalog.h"
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#define DISP_CC_MISC_CMD_REG_OFF 0x00
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/* register to configure DMA scheduling */
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#define DSI_DMA_SCHEDULE_CTRL 0x100
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/**
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* dsi_ctrl_hw_22_phy_reset_config() - to configure clamp control during ulps
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* @ctrl: Pointer to the controller host hardware.
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* @enable: boolean to specify enable/disable.
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*/
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void dsi_ctrl_hw_22_phy_reset_config(struct dsi_ctrl_hw *ctrl,
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bool enable)
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{
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u32 reg = 0;
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reg = DSI_DISP_CC_R32(ctrl, DISP_CC_MISC_CMD_REG_OFF);
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/* Mask/unmask disable PHY reset bit */
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if (enable)
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reg &= ~BIT(ctrl->index);
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else
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reg |= BIT(ctrl->index);
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DSI_DISP_CC_W32(ctrl, DISP_CC_MISC_CMD_REG_OFF, reg);
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}
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/**
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* dsi_ctrl_hw_22_schedule_dma_cmd() - to schedule DMA command transfer
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* @ctrl: Pointer to the controller host hardware.
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* @line_no: Line number at which command needs to be sent.
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*/
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void dsi_ctrl_hw_22_schedule_dma_cmd(struct dsi_ctrl_hw *ctrl, int line_no)
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{
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u32 reg = 0;
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reg = DSI_R32(ctrl, DSI_DMA_SCHEDULE_CTRL);
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reg |= BIT(28);
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reg |= (line_no & 0xffff);
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DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL, reg);
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}
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/*
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* dsi_ctrl_hw_22_get_cont_splash_status() - to verify whether continuous
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* splash is enabled or not
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* @ctrl: Pointer to the controller host hardware.
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*
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* Return: Return Continuous splash status
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*/
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bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl)
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{
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u32 reg = 0;
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/**
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* DSI scratch register 1 is used to notify whether continuous
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* splash is enabled or not by bootloader
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*/
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reg = DSI_R32(ctrl, DSI_SCRATCH_REGISTER_1);
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return reg == 0x1;
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}
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/*
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* dsi_ctrl_hw_kickoff_non_embedded_mode()-Kickoff cmd in non-embedded mode
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* @ctrl: - Pointer to the controller host hardware.
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* @dsi_ctrl_cmd_dma_info: - command buffer information.
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* @flags: - DSI CTRL Flags.
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*/
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void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl,
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struct dsi_ctrl_cmd_dma_info *cmd,
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u32 flags)
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{
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u32 reg = 0;
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reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL);
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reg &= ~BIT(31);/* disable broadcast */
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reg &= ~BIT(30);
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if (cmd->use_lpm)
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reg |= BIT(26);
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else
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reg &= ~BIT(26);
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/* Select non EMBEDDED_MODE, pick the packet header from register */
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reg &= ~BIT(28);
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reg |= BIT(24);/* long packet */
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reg |= BIT(29);/* wc_sel = 1 */
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reg |= (((cmd->datatype) & 0x03f) << 16);/* data type */
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DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg);
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/* Enable WRITE_WATERMARK_DISABLE and READ_WATERMARK_DISABLE bits */
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reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL);
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reg |= BIT(20);
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reg |= BIT(16);
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reg |= 0x33;/* Set READ and WRITE watermark levels to maximum */
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DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg);
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DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset);
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DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, ((cmd->length) & 0xFFFFFF));
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/* wait for writes to complete before kick off */
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wmb();
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if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER))
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DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
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}
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/*
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* dsi_ctrl_hw_22_config_clk_gating() - enable/disable clk gating on DSI PHY
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* @ctrl: Pointer to the controller host hardware.
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* @enable: bool to notify enable/disable.
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* @clk_selection: clock to enable/disable clock gating.
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*
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*/
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void dsi_ctrl_hw_22_config_clk_gating(struct dsi_ctrl_hw *ctrl, bool enable,
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enum dsi_clk_gate_type clk_selection)
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{
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u32 reg = 0;
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u32 enable_select = 0;
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reg = DSI_DISP_CC_R32(ctrl, DISP_CC_MISC_CMD_REG_OFF);
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if (clk_selection & PIXEL_CLK)
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enable_select |= ctrl->index ? BIT(6) : BIT(5);
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if (clk_selection & BYTE_CLK)
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enable_select |= ctrl->index ? BIT(8) : BIT(7);
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if (clk_selection & DSI_PHY)
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enable_select |= ctrl->index ? BIT(10) : BIT(9);
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if (enable)
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reg |= enable_select;
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else
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reg &= ~enable_select;
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DSI_DISP_CC_W32(ctrl, DISP_CC_MISC_CMD_REG_OFF, reg);
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}
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