kona.c 223 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd938x/wcd938x-mbhc.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/wcd938x/wcd938x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "codecs/bolero/wsa-macro.h"
  37. #include "kona-port-config.h"
  38. #define DRV_NAME "kona-asoc-snd"
  39. #define __CHIPSET__ "KONA "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WCD9XXX_MBHC_DEF_RLOADS 5
  55. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  56. #define CODEC_EXT_CLK_RATE 9600000
  57. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  58. #define DEV_NAME_STR_LEN 32
  59. #define WCD_MBHC_HS_V_MAX 1600
  60. #define TDM_CHANNEL_MAX 8
  61. #define DEV_NAME_STR_LEN 32
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 2
  68. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  69. enum {
  70. TDM_0 = 0,
  71. TDM_1,
  72. TDM_2,
  73. TDM_3,
  74. TDM_4,
  75. TDM_5,
  76. TDM_6,
  77. TDM_7,
  78. TDM_PORT_MAX,
  79. };
  80. enum {
  81. TDM_PRI = 0,
  82. TDM_SEC,
  83. TDM_TERT,
  84. TDM_QUAT,
  85. TDM_QUIN,
  86. TDM_SEN,
  87. TDM_INTERFACE_MAX,
  88. };
  89. enum {
  90. PRIM_AUX_PCM = 0,
  91. SEC_AUX_PCM,
  92. TERT_AUX_PCM,
  93. QUAT_AUX_PCM,
  94. QUIN_AUX_PCM,
  95. SEN_AUX_PCM,
  96. AUX_PCM_MAX,
  97. };
  98. enum {
  99. PRIM_MI2S = 0,
  100. SEC_MI2S,
  101. TERT_MI2S,
  102. QUAT_MI2S,
  103. QUIN_MI2S,
  104. SEN_MI2S,
  105. MI2S_MAX,
  106. };
  107. enum {
  108. WSA_CDC_DMA_RX_0 = 0,
  109. WSA_CDC_DMA_RX_1,
  110. RX_CDC_DMA_RX_0,
  111. RX_CDC_DMA_RX_1,
  112. RX_CDC_DMA_RX_2,
  113. RX_CDC_DMA_RX_3,
  114. RX_CDC_DMA_RX_5,
  115. CDC_DMA_RX_MAX,
  116. };
  117. enum {
  118. WSA_CDC_DMA_TX_0 = 0,
  119. WSA_CDC_DMA_TX_1,
  120. WSA_CDC_DMA_TX_2,
  121. TX_CDC_DMA_TX_0,
  122. TX_CDC_DMA_TX_3,
  123. TX_CDC_DMA_TX_4,
  124. VA_CDC_DMA_TX_0,
  125. VA_CDC_DMA_TX_1,
  126. VA_CDC_DMA_TX_2,
  127. CDC_DMA_TX_MAX,
  128. };
  129. enum {
  130. SLIM_RX_7 = 0,
  131. SLIM_RX_MAX,
  132. };
  133. enum {
  134. SLIM_TX_7 = 0,
  135. SLIM_TX_8,
  136. SLIM_TX_MAX,
  137. };
  138. enum {
  139. AFE_LOOPBACK_TX_IDX = 0,
  140. AFE_LOOPBACK_TX_IDX_MAX,
  141. };
  142. struct msm_asoc_mach_data {
  143. struct snd_info_entry *codec_root;
  144. int usbc_en2_gpio; /* used by gpio driver API */
  145. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  146. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  147. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  148. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  149. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  150. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  151. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  152. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  153. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  154. bool is_afe_config_done;
  155. struct device_node *fsa_handle;
  156. };
  157. struct tdm_port {
  158. u32 mode;
  159. u32 channel;
  160. };
  161. enum {
  162. EXT_DISP_RX_IDX_DP = 0,
  163. EXT_DISP_RX_IDX_DP1,
  164. EXT_DISP_RX_IDX_MAX,
  165. };
  166. struct msm_wsa881x_dev_info {
  167. struct device_node *of_node;
  168. u32 index;
  169. };
  170. struct aux_codec_dev_info {
  171. struct device_node *of_node;
  172. u32 index;
  173. };
  174. struct dev_config {
  175. u32 sample_rate;
  176. u32 bit_format;
  177. u32 channels;
  178. };
  179. /* Default configuration of slimbus channels */
  180. static struct dev_config slim_rx_cfg[] = {
  181. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  182. };
  183. static struct dev_config slim_tx_cfg[] = {
  184. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  185. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  186. };
  187. /* Default configuration of external display BE */
  188. static struct dev_config ext_disp_rx_cfg[] = {
  189. [EXT_DISP_RX_IDX_DP] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  190. [EXT_DISP_RX_IDX_DP1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  191. };
  192. static struct dev_config usb_rx_cfg = {
  193. .sample_rate = SAMPLING_RATE_48KHZ,
  194. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  195. .channels = 2,
  196. };
  197. static struct dev_config usb_tx_cfg = {
  198. .sample_rate = SAMPLING_RATE_48KHZ,
  199. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  200. .channels = 1,
  201. };
  202. static struct dev_config proxy_rx_cfg = {
  203. .sample_rate = SAMPLING_RATE_48KHZ,
  204. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  205. .channels = 2,
  206. };
  207. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  208. {
  209. AFE_API_VERSION_I2S_CONFIG,
  210. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  211. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  212. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  213. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  214. 0,
  215. },
  216. {
  217. AFE_API_VERSION_I2S_CONFIG,
  218. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  219. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  220. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  221. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  222. 0,
  223. },
  224. {
  225. AFE_API_VERSION_I2S_CONFIG,
  226. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  227. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  228. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  229. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  230. 0,
  231. },
  232. {
  233. AFE_API_VERSION_I2S_CONFIG,
  234. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  235. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  236. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  237. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  238. 0,
  239. },
  240. {
  241. AFE_API_VERSION_I2S_CONFIG,
  242. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  243. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  244. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  245. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  246. 0,
  247. },
  248. {
  249. AFE_API_VERSION_I2S_CONFIG,
  250. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  251. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  252. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  253. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  254. 0,
  255. },
  256. };
  257. struct mi2s_conf {
  258. struct mutex lock;
  259. u32 ref_cnt;
  260. u32 msm_is_mi2s_master;
  261. };
  262. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  263. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  264. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  265. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  266. };
  267. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  268. /* Default configuration of TDM channels */
  269. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  270. { /* PRI TDM */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  279. },
  280. { /* SEC TDM */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  289. },
  290. { /* TERT TDM */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  299. },
  300. { /* QUAT TDM */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  309. },
  310. { /* QUIN TDM */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  317. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  318. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  319. },
  320. { /* SEN TDM */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  327. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  328. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  329. },
  330. };
  331. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  332. { /* PRI TDM */
  333. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  334. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  335. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  336. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  337. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  338. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  339. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  340. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  341. },
  342. { /* SEC TDM */
  343. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  344. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  345. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  346. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  347. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  348. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  349. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  350. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  351. },
  352. { /* TERT TDM */
  353. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  354. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  355. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  356. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  357. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  358. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  359. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  360. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  361. },
  362. { /* QUAT TDM */
  363. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  364. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  365. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  366. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  367. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  368. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  369. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  370. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  371. },
  372. { /* QUIN TDM */
  373. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  374. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  375. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  376. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  377. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  378. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  379. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  380. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  381. },
  382. { /* SEN TDM */
  383. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  384. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  385. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  386. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  387. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  388. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  389. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  390. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  391. },
  392. };
  393. /* Default configuration of AUX PCM channels */
  394. static struct dev_config aux_pcm_rx_cfg[] = {
  395. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  400. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  401. };
  402. static struct dev_config aux_pcm_tx_cfg[] = {
  403. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  404. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  405. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  406. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  407. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  408. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  409. };
  410. /* Default configuration of MI2S channels */
  411. static struct dev_config mi2s_rx_cfg[] = {
  412. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  413. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  414. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  415. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  416. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  417. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  418. };
  419. static struct dev_config mi2s_tx_cfg[] = {
  420. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  421. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  422. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  423. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  424. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  425. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  426. };
  427. /* Default configuration of Codec DMA Interface RX */
  428. static struct dev_config cdc_dma_rx_cfg[] = {
  429. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  430. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  431. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  432. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  433. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  434. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  435. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  436. };
  437. /* Default configuration of Codec DMA Interface TX */
  438. static struct dev_config cdc_dma_tx_cfg[] = {
  439. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  440. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  441. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  442. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  443. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  444. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  445. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  446. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  447. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  448. };
  449. static struct dev_config afe_loopback_tx_cfg[] = {
  450. [AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  451. };
  452. static int msm_vi_feed_tx_ch = 2;
  453. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  454. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  455. "S32_LE"};
  456. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  457. "Six", "Seven", "Eight"};
  458. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  459. "KHZ_16", "KHZ_22P05",
  460. "KHZ_32", "KHZ_44P1", "KHZ_48",
  461. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  462. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  463. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  464. "Five", "Six", "Seven",
  465. "Eight"};
  466. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  467. "KHZ_48", "KHZ_176P4",
  468. "KHZ_352P8"};
  469. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  470. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  471. "Five", "Six", "Seven", "Eight"};
  472. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  473. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  474. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  475. "KHZ_48", "KHZ_96", "KHZ_192"};
  476. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  477. "Five", "Six", "Seven",
  478. "Eight"};
  479. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  480. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  481. "Five", "Six", "Seven",
  482. "Eight"};
  483. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  484. "KHZ_16", "KHZ_22P05",
  485. "KHZ_32", "KHZ_44P1", "KHZ_48",
  486. "KHZ_88P2", "KHZ_96",
  487. "KHZ_176P4", "KHZ_192",
  488. "KHZ_352P8", "KHZ_384"};
  489. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
  490. "S24_3LE"};
  491. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  492. "KHZ_192", "KHZ_32", "KHZ_44P1",
  493. "KHZ_88P2", "KHZ_176P4"};
  494. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  495. "KHZ_44P1", "KHZ_48",
  496. "KHZ_88P2", "KHZ_96"};
  497. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  498. "KHZ_44P1", "KHZ_48",
  499. "KHZ_88P2", "KHZ_96"};
  500. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  501. "KHZ_44P1", "KHZ_48",
  502. "KHZ_88P2", "KHZ_96"};
  503. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  504. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  568. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  569. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  570. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  571. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  572. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  573. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  574. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  575. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  576. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  577. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  578. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  579. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  580. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  581. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  582. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  583. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  584. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  585. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  586. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  587. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  588. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  589. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  590. cdc_dma_sample_rate_text);
  591. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  592. cdc_dma_sample_rate_text);
  593. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  594. cdc_dma_sample_rate_text);
  595. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  596. cdc_dma_sample_rate_text);
  597. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  598. cdc_dma_sample_rate_text);
  599. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  600. cdc_dma_sample_rate_text);
  601. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  602. cdc_dma_sample_rate_text);
  603. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  604. cdc_dma_sample_rate_text);
  605. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  606. cdc_dma_sample_rate_text);
  607. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  608. cdc_dma_sample_rate_text);
  609. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  610. cdc_dma_sample_rate_text);
  611. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  612. cdc_dma_sample_rate_text);
  613. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  614. cdc_dma_sample_rate_text);
  615. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  616. cdc_dma_sample_rate_text);
  617. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  618. cdc_dma_sample_rate_text);
  619. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  620. cdc_dma_sample_rate_text);
  621. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  622. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  623. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  624. ext_disp_sample_rate_text);
  625. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  626. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  627. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  628. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  629. static bool is_initial_boot;
  630. static bool codec_reg_done;
  631. static struct snd_soc_aux_dev *msm_aux_dev;
  632. static struct snd_soc_codec_conf *msm_codec_conf;
  633. static struct snd_soc_card snd_soc_card_kona_msm;
  634. static int dmic_0_1_gpio_cnt;
  635. static int dmic_2_3_gpio_cnt;
  636. static int dmic_4_5_gpio_cnt;
  637. static void *def_wcd_mbhc_cal(void);
  638. /*
  639. * Need to report LINEIN
  640. * if R/L channel impedance is larger than 5K ohm
  641. */
  642. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  643. .read_fw_bin = false,
  644. .calibration = NULL,
  645. .detect_extn_cable = true,
  646. .mono_stero_detection = false,
  647. .swap_gnd_mic = NULL,
  648. .hs_ext_micbias = true,
  649. .key_code[0] = KEY_MEDIA,
  650. .key_code[1] = KEY_VOICECOMMAND,
  651. .key_code[2] = KEY_VOLUMEUP,
  652. .key_code[3] = KEY_VOLUMEDOWN,
  653. .key_code[4] = 0,
  654. .key_code[5] = 0,
  655. .key_code[6] = 0,
  656. .key_code[7] = 0,
  657. .linein_th = 5000,
  658. .moisture_en = false,
  659. .mbhc_micbias = MIC_BIAS_2,
  660. .anc_micbias = MIC_BIAS_2,
  661. .enable_anc_mic_detect = false,
  662. .moisture_duty_cycle_en = true,
  663. };
  664. static inline int param_is_mask(int p)
  665. {
  666. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  667. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  668. }
  669. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  670. int n)
  671. {
  672. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  673. }
  674. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  675. unsigned int bit)
  676. {
  677. if (bit >= SNDRV_MASK_MAX)
  678. return;
  679. if (param_is_mask(n)) {
  680. struct snd_mask *m = param_to_mask(p, n);
  681. m->bits[0] = 0;
  682. m->bits[1] = 0;
  683. m->bits[bit >> 5] |= (1 << (bit & 31));
  684. }
  685. }
  686. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  687. struct snd_ctl_elem_value *ucontrol)
  688. {
  689. int sample_rate_val = 0;
  690. switch (usb_rx_cfg.sample_rate) {
  691. case SAMPLING_RATE_384KHZ:
  692. sample_rate_val = 12;
  693. break;
  694. case SAMPLING_RATE_352P8KHZ:
  695. sample_rate_val = 11;
  696. break;
  697. case SAMPLING_RATE_192KHZ:
  698. sample_rate_val = 10;
  699. break;
  700. case SAMPLING_RATE_176P4KHZ:
  701. sample_rate_val = 9;
  702. break;
  703. case SAMPLING_RATE_96KHZ:
  704. sample_rate_val = 8;
  705. break;
  706. case SAMPLING_RATE_88P2KHZ:
  707. sample_rate_val = 7;
  708. break;
  709. case SAMPLING_RATE_48KHZ:
  710. sample_rate_val = 6;
  711. break;
  712. case SAMPLING_RATE_44P1KHZ:
  713. sample_rate_val = 5;
  714. break;
  715. case SAMPLING_RATE_32KHZ:
  716. sample_rate_val = 4;
  717. break;
  718. case SAMPLING_RATE_22P05KHZ:
  719. sample_rate_val = 3;
  720. break;
  721. case SAMPLING_RATE_16KHZ:
  722. sample_rate_val = 2;
  723. break;
  724. case SAMPLING_RATE_11P025KHZ:
  725. sample_rate_val = 1;
  726. break;
  727. case SAMPLING_RATE_8KHZ:
  728. default:
  729. sample_rate_val = 0;
  730. break;
  731. }
  732. ucontrol->value.integer.value[0] = sample_rate_val;
  733. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  734. usb_rx_cfg.sample_rate);
  735. return 0;
  736. }
  737. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  738. struct snd_ctl_elem_value *ucontrol)
  739. {
  740. switch (ucontrol->value.integer.value[0]) {
  741. case 12:
  742. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  743. break;
  744. case 11:
  745. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  746. break;
  747. case 10:
  748. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  749. break;
  750. case 9:
  751. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  752. break;
  753. case 8:
  754. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  755. break;
  756. case 7:
  757. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  758. break;
  759. case 6:
  760. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  761. break;
  762. case 5:
  763. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  764. break;
  765. case 4:
  766. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  767. break;
  768. case 3:
  769. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  770. break;
  771. case 2:
  772. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  773. break;
  774. case 1:
  775. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  776. break;
  777. case 0:
  778. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  779. break;
  780. default:
  781. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  782. break;
  783. }
  784. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  785. __func__, ucontrol->value.integer.value[0],
  786. usb_rx_cfg.sample_rate);
  787. return 0;
  788. }
  789. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  790. struct snd_ctl_elem_value *ucontrol)
  791. {
  792. int sample_rate_val = 0;
  793. switch (usb_tx_cfg.sample_rate) {
  794. case SAMPLING_RATE_384KHZ:
  795. sample_rate_val = 12;
  796. break;
  797. case SAMPLING_RATE_352P8KHZ:
  798. sample_rate_val = 11;
  799. break;
  800. case SAMPLING_RATE_192KHZ:
  801. sample_rate_val = 10;
  802. break;
  803. case SAMPLING_RATE_176P4KHZ:
  804. sample_rate_val = 9;
  805. break;
  806. case SAMPLING_RATE_96KHZ:
  807. sample_rate_val = 8;
  808. break;
  809. case SAMPLING_RATE_88P2KHZ:
  810. sample_rate_val = 7;
  811. break;
  812. case SAMPLING_RATE_48KHZ:
  813. sample_rate_val = 6;
  814. break;
  815. case SAMPLING_RATE_44P1KHZ:
  816. sample_rate_val = 5;
  817. break;
  818. case SAMPLING_RATE_32KHZ:
  819. sample_rate_val = 4;
  820. break;
  821. case SAMPLING_RATE_22P05KHZ:
  822. sample_rate_val = 3;
  823. break;
  824. case SAMPLING_RATE_16KHZ:
  825. sample_rate_val = 2;
  826. break;
  827. case SAMPLING_RATE_11P025KHZ:
  828. sample_rate_val = 1;
  829. break;
  830. case SAMPLING_RATE_8KHZ:
  831. sample_rate_val = 0;
  832. break;
  833. default:
  834. sample_rate_val = 6;
  835. break;
  836. }
  837. ucontrol->value.integer.value[0] = sample_rate_val;
  838. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  839. usb_tx_cfg.sample_rate);
  840. return 0;
  841. }
  842. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  843. struct snd_ctl_elem_value *ucontrol)
  844. {
  845. switch (ucontrol->value.integer.value[0]) {
  846. case 12:
  847. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  848. break;
  849. case 11:
  850. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  851. break;
  852. case 10:
  853. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  854. break;
  855. case 9:
  856. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  857. break;
  858. case 8:
  859. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  860. break;
  861. case 7:
  862. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  863. break;
  864. case 6:
  865. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  866. break;
  867. case 5:
  868. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  869. break;
  870. case 4:
  871. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  872. break;
  873. case 3:
  874. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  875. break;
  876. case 2:
  877. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  878. break;
  879. case 1:
  880. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  881. break;
  882. case 0:
  883. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  884. break;
  885. default:
  886. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  887. break;
  888. }
  889. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  890. __func__, ucontrol->value.integer.value[0],
  891. usb_tx_cfg.sample_rate);
  892. return 0;
  893. }
  894. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  895. struct snd_ctl_elem_value *ucontrol)
  896. {
  897. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  898. afe_loopback_tx_cfg[0].channels);
  899. ucontrol->value.enumerated.item[0] =
  900. afe_loopback_tx_cfg[0].channels - 1;
  901. return 0;
  902. }
  903. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  904. struct snd_ctl_elem_value *ucontrol)
  905. {
  906. afe_loopback_tx_cfg[0].channels =
  907. ucontrol->value.enumerated.item[0] + 1;
  908. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  909. afe_loopback_tx_cfg[0].channels);
  910. return 1;
  911. }
  912. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  913. struct snd_ctl_elem_value *ucontrol)
  914. {
  915. switch (usb_rx_cfg.bit_format) {
  916. case SNDRV_PCM_FORMAT_S32_LE:
  917. ucontrol->value.integer.value[0] = 3;
  918. break;
  919. case SNDRV_PCM_FORMAT_S24_3LE:
  920. ucontrol->value.integer.value[0] = 2;
  921. break;
  922. case SNDRV_PCM_FORMAT_S24_LE:
  923. ucontrol->value.integer.value[0] = 1;
  924. break;
  925. case SNDRV_PCM_FORMAT_S16_LE:
  926. default:
  927. ucontrol->value.integer.value[0] = 0;
  928. break;
  929. }
  930. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  931. __func__, usb_rx_cfg.bit_format,
  932. ucontrol->value.integer.value[0]);
  933. return 0;
  934. }
  935. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  936. struct snd_ctl_elem_value *ucontrol)
  937. {
  938. int rc = 0;
  939. switch (ucontrol->value.integer.value[0]) {
  940. case 3:
  941. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  942. break;
  943. case 2:
  944. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  945. break;
  946. case 1:
  947. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  948. break;
  949. case 0:
  950. default:
  951. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  952. break;
  953. }
  954. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  955. __func__, usb_rx_cfg.bit_format,
  956. ucontrol->value.integer.value[0]);
  957. return rc;
  958. }
  959. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  960. struct snd_ctl_elem_value *ucontrol)
  961. {
  962. switch (usb_tx_cfg.bit_format) {
  963. case SNDRV_PCM_FORMAT_S32_LE:
  964. ucontrol->value.integer.value[0] = 3;
  965. break;
  966. case SNDRV_PCM_FORMAT_S24_3LE:
  967. ucontrol->value.integer.value[0] = 2;
  968. break;
  969. case SNDRV_PCM_FORMAT_S24_LE:
  970. ucontrol->value.integer.value[0] = 1;
  971. break;
  972. case SNDRV_PCM_FORMAT_S16_LE:
  973. default:
  974. ucontrol->value.integer.value[0] = 0;
  975. break;
  976. }
  977. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  978. __func__, usb_tx_cfg.bit_format,
  979. ucontrol->value.integer.value[0]);
  980. return 0;
  981. }
  982. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  983. struct snd_ctl_elem_value *ucontrol)
  984. {
  985. int rc = 0;
  986. switch (ucontrol->value.integer.value[0]) {
  987. case 3:
  988. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  989. break;
  990. case 2:
  991. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  992. break;
  993. case 1:
  994. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  995. break;
  996. case 0:
  997. default:
  998. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  999. break;
  1000. }
  1001. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1002. __func__, usb_tx_cfg.bit_format,
  1003. ucontrol->value.integer.value[0]);
  1004. return rc;
  1005. }
  1006. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1007. struct snd_ctl_elem_value *ucontrol)
  1008. {
  1009. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1010. usb_rx_cfg.channels);
  1011. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1012. return 0;
  1013. }
  1014. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1015. struct snd_ctl_elem_value *ucontrol)
  1016. {
  1017. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1018. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1019. return 1;
  1020. }
  1021. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1022. struct snd_ctl_elem_value *ucontrol)
  1023. {
  1024. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1025. usb_tx_cfg.channels);
  1026. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1027. return 0;
  1028. }
  1029. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1030. struct snd_ctl_elem_value *ucontrol)
  1031. {
  1032. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1033. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1034. return 1;
  1035. }
  1036. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1037. struct snd_ctl_elem_value *ucontrol)
  1038. {
  1039. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1040. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1041. ucontrol->value.integer.value[0]);
  1042. return 0;
  1043. }
  1044. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1045. struct snd_ctl_elem_value *ucontrol)
  1046. {
  1047. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1048. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1049. return 1;
  1050. }
  1051. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1052. {
  1053. int idx = 0;
  1054. if (strnstr(kcontrol->id.name, "Display Port RX",
  1055. sizeof("Display Port RX"))) {
  1056. idx = EXT_DISP_RX_IDX_DP;
  1057. } else if (strnstr(kcontrol->id.name, "Display Port1 RX",
  1058. sizeof("Display Port1 RX"))) {
  1059. idx = EXT_DISP_RX_IDX_DP1;
  1060. } else {
  1061. pr_err("%s: unsupported BE: %s\n",
  1062. __func__, kcontrol->id.name);
  1063. idx = -EINVAL;
  1064. }
  1065. return idx;
  1066. }
  1067. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1068. struct snd_ctl_elem_value *ucontrol)
  1069. {
  1070. int idx = ext_disp_get_port_idx(kcontrol);
  1071. if (idx < 0)
  1072. return idx;
  1073. switch (ext_disp_rx_cfg[idx].bit_format) {
  1074. case SNDRV_PCM_FORMAT_S24_3LE:
  1075. ucontrol->value.integer.value[0] = 2;
  1076. break;
  1077. case SNDRV_PCM_FORMAT_S24_LE:
  1078. ucontrol->value.integer.value[0] = 1;
  1079. break;
  1080. case SNDRV_PCM_FORMAT_S16_LE:
  1081. default:
  1082. ucontrol->value.integer.value[0] = 0;
  1083. break;
  1084. }
  1085. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1086. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1087. ucontrol->value.integer.value[0]);
  1088. return 0;
  1089. }
  1090. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1091. struct snd_ctl_elem_value *ucontrol)
  1092. {
  1093. int idx = ext_disp_get_port_idx(kcontrol);
  1094. if (idx < 0)
  1095. return idx;
  1096. switch (ucontrol->value.integer.value[0]) {
  1097. case 2:
  1098. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1099. break;
  1100. case 1:
  1101. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1102. break;
  1103. case 0:
  1104. default:
  1105. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1106. break;
  1107. }
  1108. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1109. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1110. ucontrol->value.integer.value[0]);
  1111. return 0;
  1112. }
  1113. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1114. struct snd_ctl_elem_value *ucontrol)
  1115. {
  1116. int idx = ext_disp_get_port_idx(kcontrol);
  1117. if (idx < 0)
  1118. return idx;
  1119. ucontrol->value.integer.value[0] =
  1120. ext_disp_rx_cfg[idx].channels - 2;
  1121. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1122. idx, ext_disp_rx_cfg[idx].channels);
  1123. return 0;
  1124. }
  1125. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1126. struct snd_ctl_elem_value *ucontrol)
  1127. {
  1128. int idx = ext_disp_get_port_idx(kcontrol);
  1129. if (idx < 0)
  1130. return idx;
  1131. ext_disp_rx_cfg[idx].channels =
  1132. ucontrol->value.integer.value[0] + 2;
  1133. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1134. idx, ext_disp_rx_cfg[idx].channels);
  1135. return 1;
  1136. }
  1137. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1138. struct snd_ctl_elem_value *ucontrol)
  1139. {
  1140. int sample_rate_val;
  1141. int idx = ext_disp_get_port_idx(kcontrol);
  1142. if (idx < 0)
  1143. return idx;
  1144. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1145. case SAMPLING_RATE_176P4KHZ:
  1146. sample_rate_val = 6;
  1147. break;
  1148. case SAMPLING_RATE_88P2KHZ:
  1149. sample_rate_val = 5;
  1150. break;
  1151. case SAMPLING_RATE_44P1KHZ:
  1152. sample_rate_val = 4;
  1153. break;
  1154. case SAMPLING_RATE_32KHZ:
  1155. sample_rate_val = 3;
  1156. break;
  1157. case SAMPLING_RATE_192KHZ:
  1158. sample_rate_val = 2;
  1159. break;
  1160. case SAMPLING_RATE_96KHZ:
  1161. sample_rate_val = 1;
  1162. break;
  1163. case SAMPLING_RATE_48KHZ:
  1164. default:
  1165. sample_rate_val = 0;
  1166. break;
  1167. }
  1168. ucontrol->value.integer.value[0] = sample_rate_val;
  1169. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1170. idx, ext_disp_rx_cfg[idx].sample_rate);
  1171. return 0;
  1172. }
  1173. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1174. struct snd_ctl_elem_value *ucontrol)
  1175. {
  1176. int idx = ext_disp_get_port_idx(kcontrol);
  1177. if (idx < 0)
  1178. return idx;
  1179. switch (ucontrol->value.integer.value[0]) {
  1180. case 6:
  1181. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  1182. break;
  1183. case 5:
  1184. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  1185. break;
  1186. case 4:
  1187. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  1188. break;
  1189. case 3:
  1190. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  1191. break;
  1192. case 2:
  1193. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1194. break;
  1195. case 1:
  1196. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1197. break;
  1198. case 0:
  1199. default:
  1200. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1201. break;
  1202. }
  1203. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1204. __func__, ucontrol->value.integer.value[0], idx,
  1205. ext_disp_rx_cfg[idx].sample_rate);
  1206. return 0;
  1207. }
  1208. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1209. struct snd_ctl_elem_value *ucontrol)
  1210. {
  1211. pr_debug("%s: proxy_rx channels = %d\n",
  1212. __func__, proxy_rx_cfg.channels);
  1213. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1214. return 0;
  1215. }
  1216. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1217. struct snd_ctl_elem_value *ucontrol)
  1218. {
  1219. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1220. pr_debug("%s: proxy_rx channels = %d\n",
  1221. __func__, proxy_rx_cfg.channels);
  1222. return 1;
  1223. }
  1224. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1225. struct tdm_port *port)
  1226. {
  1227. if (port) {
  1228. if (strnstr(kcontrol->id.name, "PRI",
  1229. sizeof(kcontrol->id.name))) {
  1230. port->mode = TDM_PRI;
  1231. } else if (strnstr(kcontrol->id.name, "SEC",
  1232. sizeof(kcontrol->id.name))) {
  1233. port->mode = TDM_SEC;
  1234. } else if (strnstr(kcontrol->id.name, "TERT",
  1235. sizeof(kcontrol->id.name))) {
  1236. port->mode = TDM_TERT;
  1237. } else if (strnstr(kcontrol->id.name, "QUAT",
  1238. sizeof(kcontrol->id.name))) {
  1239. port->mode = TDM_QUAT;
  1240. } else if (strnstr(kcontrol->id.name, "QUIN",
  1241. sizeof(kcontrol->id.name))) {
  1242. port->mode = TDM_QUIN;
  1243. } else if (strnstr(kcontrol->id.name, "SEN",
  1244. sizeof(kcontrol->id.name))) {
  1245. port->mode = TDM_SEN;
  1246. } else {
  1247. pr_err("%s: unsupported mode in: %s\n",
  1248. __func__, kcontrol->id.name);
  1249. return -EINVAL;
  1250. }
  1251. if (strnstr(kcontrol->id.name, "RX_0",
  1252. sizeof(kcontrol->id.name)) ||
  1253. strnstr(kcontrol->id.name, "TX_0",
  1254. sizeof(kcontrol->id.name))) {
  1255. port->channel = TDM_0;
  1256. } else if (strnstr(kcontrol->id.name, "RX_1",
  1257. sizeof(kcontrol->id.name)) ||
  1258. strnstr(kcontrol->id.name, "TX_1",
  1259. sizeof(kcontrol->id.name))) {
  1260. port->channel = TDM_1;
  1261. } else if (strnstr(kcontrol->id.name, "RX_2",
  1262. sizeof(kcontrol->id.name)) ||
  1263. strnstr(kcontrol->id.name, "TX_2",
  1264. sizeof(kcontrol->id.name))) {
  1265. port->channel = TDM_2;
  1266. } else if (strnstr(kcontrol->id.name, "RX_3",
  1267. sizeof(kcontrol->id.name)) ||
  1268. strnstr(kcontrol->id.name, "TX_3",
  1269. sizeof(kcontrol->id.name))) {
  1270. port->channel = TDM_3;
  1271. } else if (strnstr(kcontrol->id.name, "RX_4",
  1272. sizeof(kcontrol->id.name)) ||
  1273. strnstr(kcontrol->id.name, "TX_4",
  1274. sizeof(kcontrol->id.name))) {
  1275. port->channel = TDM_4;
  1276. } else if (strnstr(kcontrol->id.name, "RX_5",
  1277. sizeof(kcontrol->id.name)) ||
  1278. strnstr(kcontrol->id.name, "TX_5",
  1279. sizeof(kcontrol->id.name))) {
  1280. port->channel = TDM_5;
  1281. } else if (strnstr(kcontrol->id.name, "RX_6",
  1282. sizeof(kcontrol->id.name)) ||
  1283. strnstr(kcontrol->id.name, "TX_6",
  1284. sizeof(kcontrol->id.name))) {
  1285. port->channel = TDM_6;
  1286. } else if (strnstr(kcontrol->id.name, "RX_7",
  1287. sizeof(kcontrol->id.name)) ||
  1288. strnstr(kcontrol->id.name, "TX_7",
  1289. sizeof(kcontrol->id.name))) {
  1290. port->channel = TDM_7;
  1291. } else {
  1292. pr_err("%s: unsupported channel in: %s\n",
  1293. __func__, kcontrol->id.name);
  1294. return -EINVAL;
  1295. }
  1296. } else {
  1297. return -EINVAL;
  1298. }
  1299. return 0;
  1300. }
  1301. static int tdm_get_sample_rate(int value)
  1302. {
  1303. int sample_rate = 0;
  1304. switch (value) {
  1305. case 0:
  1306. sample_rate = SAMPLING_RATE_8KHZ;
  1307. break;
  1308. case 1:
  1309. sample_rate = SAMPLING_RATE_16KHZ;
  1310. break;
  1311. case 2:
  1312. sample_rate = SAMPLING_RATE_32KHZ;
  1313. break;
  1314. case 3:
  1315. sample_rate = SAMPLING_RATE_48KHZ;
  1316. break;
  1317. case 4:
  1318. sample_rate = SAMPLING_RATE_176P4KHZ;
  1319. break;
  1320. case 5:
  1321. sample_rate = SAMPLING_RATE_352P8KHZ;
  1322. break;
  1323. default:
  1324. sample_rate = SAMPLING_RATE_48KHZ;
  1325. break;
  1326. }
  1327. return sample_rate;
  1328. }
  1329. static int tdm_get_sample_rate_val(int sample_rate)
  1330. {
  1331. int sample_rate_val = 0;
  1332. switch (sample_rate) {
  1333. case SAMPLING_RATE_8KHZ:
  1334. sample_rate_val = 0;
  1335. break;
  1336. case SAMPLING_RATE_16KHZ:
  1337. sample_rate_val = 1;
  1338. break;
  1339. case SAMPLING_RATE_32KHZ:
  1340. sample_rate_val = 2;
  1341. break;
  1342. case SAMPLING_RATE_48KHZ:
  1343. sample_rate_val = 3;
  1344. break;
  1345. case SAMPLING_RATE_176P4KHZ:
  1346. sample_rate_val = 4;
  1347. break;
  1348. case SAMPLING_RATE_352P8KHZ:
  1349. sample_rate_val = 5;
  1350. break;
  1351. default:
  1352. sample_rate_val = 3;
  1353. break;
  1354. }
  1355. return sample_rate_val;
  1356. }
  1357. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1358. struct snd_ctl_elem_value *ucontrol)
  1359. {
  1360. struct tdm_port port;
  1361. int ret = tdm_get_port_idx(kcontrol, &port);
  1362. if (ret) {
  1363. pr_err("%s: unsupported control: %s\n",
  1364. __func__, kcontrol->id.name);
  1365. } else {
  1366. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1367. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1368. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1369. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1370. ucontrol->value.enumerated.item[0]);
  1371. }
  1372. return ret;
  1373. }
  1374. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1375. struct snd_ctl_elem_value *ucontrol)
  1376. {
  1377. struct tdm_port port;
  1378. int ret = tdm_get_port_idx(kcontrol, &port);
  1379. if (ret) {
  1380. pr_err("%s: unsupported control: %s\n",
  1381. __func__, kcontrol->id.name);
  1382. } else {
  1383. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1384. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1385. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1386. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1387. ucontrol->value.enumerated.item[0]);
  1388. }
  1389. return ret;
  1390. }
  1391. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1392. struct snd_ctl_elem_value *ucontrol)
  1393. {
  1394. struct tdm_port port;
  1395. int ret = tdm_get_port_idx(kcontrol, &port);
  1396. if (ret) {
  1397. pr_err("%s: unsupported control: %s\n",
  1398. __func__, kcontrol->id.name);
  1399. } else {
  1400. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1401. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1402. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1403. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1404. ucontrol->value.enumerated.item[0]);
  1405. }
  1406. return ret;
  1407. }
  1408. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1409. struct snd_ctl_elem_value *ucontrol)
  1410. {
  1411. struct tdm_port port;
  1412. int ret = tdm_get_port_idx(kcontrol, &port);
  1413. if (ret) {
  1414. pr_err("%s: unsupported control: %s\n",
  1415. __func__, kcontrol->id.name);
  1416. } else {
  1417. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1418. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1419. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1420. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1421. ucontrol->value.enumerated.item[0]);
  1422. }
  1423. return ret;
  1424. }
  1425. static int tdm_get_format(int value)
  1426. {
  1427. int format = 0;
  1428. switch (value) {
  1429. case 0:
  1430. format = SNDRV_PCM_FORMAT_S16_LE;
  1431. break;
  1432. case 1:
  1433. format = SNDRV_PCM_FORMAT_S24_LE;
  1434. break;
  1435. case 2:
  1436. format = SNDRV_PCM_FORMAT_S32_LE;
  1437. break;
  1438. default:
  1439. format = SNDRV_PCM_FORMAT_S16_LE;
  1440. break;
  1441. }
  1442. return format;
  1443. }
  1444. static int tdm_get_format_val(int format)
  1445. {
  1446. int value = 0;
  1447. switch (format) {
  1448. case SNDRV_PCM_FORMAT_S16_LE:
  1449. value = 0;
  1450. break;
  1451. case SNDRV_PCM_FORMAT_S24_LE:
  1452. value = 1;
  1453. break;
  1454. case SNDRV_PCM_FORMAT_S32_LE:
  1455. value = 2;
  1456. break;
  1457. default:
  1458. value = 0;
  1459. break;
  1460. }
  1461. return value;
  1462. }
  1463. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1464. struct snd_ctl_elem_value *ucontrol)
  1465. {
  1466. struct tdm_port port;
  1467. int ret = tdm_get_port_idx(kcontrol, &port);
  1468. if (ret) {
  1469. pr_err("%s: unsupported control: %s\n",
  1470. __func__, kcontrol->id.name);
  1471. } else {
  1472. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1473. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1474. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1475. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1476. ucontrol->value.enumerated.item[0]);
  1477. }
  1478. return ret;
  1479. }
  1480. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1481. struct snd_ctl_elem_value *ucontrol)
  1482. {
  1483. struct tdm_port port;
  1484. int ret = tdm_get_port_idx(kcontrol, &port);
  1485. if (ret) {
  1486. pr_err("%s: unsupported control: %s\n",
  1487. __func__, kcontrol->id.name);
  1488. } else {
  1489. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1490. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1491. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1492. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1493. ucontrol->value.enumerated.item[0]);
  1494. }
  1495. return ret;
  1496. }
  1497. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1498. struct snd_ctl_elem_value *ucontrol)
  1499. {
  1500. struct tdm_port port;
  1501. int ret = tdm_get_port_idx(kcontrol, &port);
  1502. if (ret) {
  1503. pr_err("%s: unsupported control: %s\n",
  1504. __func__, kcontrol->id.name);
  1505. } else {
  1506. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1507. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1508. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1509. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1510. ucontrol->value.enumerated.item[0]);
  1511. }
  1512. return ret;
  1513. }
  1514. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1515. struct snd_ctl_elem_value *ucontrol)
  1516. {
  1517. struct tdm_port port;
  1518. int ret = tdm_get_port_idx(kcontrol, &port);
  1519. if (ret) {
  1520. pr_err("%s: unsupported control: %s\n",
  1521. __func__, kcontrol->id.name);
  1522. } else {
  1523. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1524. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1525. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1526. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1527. ucontrol->value.enumerated.item[0]);
  1528. }
  1529. return ret;
  1530. }
  1531. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1532. struct snd_ctl_elem_value *ucontrol)
  1533. {
  1534. struct tdm_port port;
  1535. int ret = tdm_get_port_idx(kcontrol, &port);
  1536. if (ret) {
  1537. pr_err("%s: unsupported control: %s\n",
  1538. __func__, kcontrol->id.name);
  1539. } else {
  1540. ucontrol->value.enumerated.item[0] =
  1541. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1542. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1543. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1544. ucontrol->value.enumerated.item[0]);
  1545. }
  1546. return ret;
  1547. }
  1548. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1549. struct snd_ctl_elem_value *ucontrol)
  1550. {
  1551. struct tdm_port port;
  1552. int ret = tdm_get_port_idx(kcontrol, &port);
  1553. if (ret) {
  1554. pr_err("%s: unsupported control: %s\n",
  1555. __func__, kcontrol->id.name);
  1556. } else {
  1557. tdm_rx_cfg[port.mode][port.channel].channels =
  1558. ucontrol->value.enumerated.item[0] + 1;
  1559. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1560. tdm_rx_cfg[port.mode][port.channel].channels,
  1561. ucontrol->value.enumerated.item[0] + 1);
  1562. }
  1563. return ret;
  1564. }
  1565. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1566. struct snd_ctl_elem_value *ucontrol)
  1567. {
  1568. struct tdm_port port;
  1569. int ret = tdm_get_port_idx(kcontrol, &port);
  1570. if (ret) {
  1571. pr_err("%s: unsupported control: %s\n",
  1572. __func__, kcontrol->id.name);
  1573. } else {
  1574. ucontrol->value.enumerated.item[0] =
  1575. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1576. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1577. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1578. ucontrol->value.enumerated.item[0]);
  1579. }
  1580. return ret;
  1581. }
  1582. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1583. struct snd_ctl_elem_value *ucontrol)
  1584. {
  1585. struct tdm_port port;
  1586. int ret = tdm_get_port_idx(kcontrol, &port);
  1587. if (ret) {
  1588. pr_err("%s: unsupported control: %s\n",
  1589. __func__, kcontrol->id.name);
  1590. } else {
  1591. tdm_tx_cfg[port.mode][port.channel].channels =
  1592. ucontrol->value.enumerated.item[0] + 1;
  1593. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1594. tdm_tx_cfg[port.mode][port.channel].channels,
  1595. ucontrol->value.enumerated.item[0] + 1);
  1596. }
  1597. return ret;
  1598. }
  1599. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1600. {
  1601. int idx = 0;
  1602. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1603. sizeof("PRIM_AUX_PCM"))) {
  1604. idx = PRIM_AUX_PCM;
  1605. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1606. sizeof("SEC_AUX_PCM"))) {
  1607. idx = SEC_AUX_PCM;
  1608. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1609. sizeof("TERT_AUX_PCM"))) {
  1610. idx = TERT_AUX_PCM;
  1611. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1612. sizeof("QUAT_AUX_PCM"))) {
  1613. idx = QUAT_AUX_PCM;
  1614. } else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  1615. sizeof("QUIN_AUX_PCM"))) {
  1616. idx = QUIN_AUX_PCM;
  1617. } else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  1618. sizeof("SEN_AUX_PCM"))) {
  1619. idx = SEN_AUX_PCM;
  1620. } else {
  1621. pr_err("%s: unsupported port: %s\n",
  1622. __func__, kcontrol->id.name);
  1623. idx = -EINVAL;
  1624. }
  1625. return idx;
  1626. }
  1627. static int aux_pcm_get_sample_rate(int value)
  1628. {
  1629. int sample_rate = 0;
  1630. switch (value) {
  1631. case 1:
  1632. sample_rate = SAMPLING_RATE_16KHZ;
  1633. break;
  1634. case 0:
  1635. default:
  1636. sample_rate = SAMPLING_RATE_8KHZ;
  1637. break;
  1638. }
  1639. return sample_rate;
  1640. }
  1641. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1642. {
  1643. int sample_rate_val = 0;
  1644. switch (sample_rate) {
  1645. case SAMPLING_RATE_16KHZ:
  1646. sample_rate_val = 1;
  1647. break;
  1648. case SAMPLING_RATE_8KHZ:
  1649. default:
  1650. sample_rate_val = 0;
  1651. break;
  1652. }
  1653. return sample_rate_val;
  1654. }
  1655. static int mi2s_auxpcm_get_format(int value)
  1656. {
  1657. int format = 0;
  1658. switch (value) {
  1659. case 0:
  1660. format = SNDRV_PCM_FORMAT_S16_LE;
  1661. break;
  1662. case 1:
  1663. format = SNDRV_PCM_FORMAT_S24_LE;
  1664. break;
  1665. case 2:
  1666. format = SNDRV_PCM_FORMAT_S24_3LE;
  1667. break;
  1668. case 3:
  1669. format = SNDRV_PCM_FORMAT_S32_LE;
  1670. break;
  1671. default:
  1672. format = SNDRV_PCM_FORMAT_S16_LE;
  1673. break;
  1674. }
  1675. return format;
  1676. }
  1677. static int mi2s_auxpcm_get_format_value(int format)
  1678. {
  1679. int value = 0;
  1680. switch (format) {
  1681. case SNDRV_PCM_FORMAT_S16_LE:
  1682. value = 0;
  1683. break;
  1684. case SNDRV_PCM_FORMAT_S24_LE:
  1685. value = 1;
  1686. break;
  1687. case SNDRV_PCM_FORMAT_S24_3LE:
  1688. value = 2;
  1689. break;
  1690. case SNDRV_PCM_FORMAT_S32_LE:
  1691. value = 3;
  1692. break;
  1693. default:
  1694. value = 0;
  1695. break;
  1696. }
  1697. return value;
  1698. }
  1699. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1700. struct snd_ctl_elem_value *ucontrol)
  1701. {
  1702. int idx = aux_pcm_get_port_idx(kcontrol);
  1703. if (idx < 0)
  1704. return idx;
  1705. ucontrol->value.enumerated.item[0] =
  1706. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1707. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1708. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1709. ucontrol->value.enumerated.item[0]);
  1710. return 0;
  1711. }
  1712. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1713. struct snd_ctl_elem_value *ucontrol)
  1714. {
  1715. int idx = aux_pcm_get_port_idx(kcontrol);
  1716. if (idx < 0)
  1717. return idx;
  1718. aux_pcm_rx_cfg[idx].sample_rate =
  1719. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1720. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1721. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1722. ucontrol->value.enumerated.item[0]);
  1723. return 0;
  1724. }
  1725. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1726. struct snd_ctl_elem_value *ucontrol)
  1727. {
  1728. int idx = aux_pcm_get_port_idx(kcontrol);
  1729. if (idx < 0)
  1730. return idx;
  1731. ucontrol->value.enumerated.item[0] =
  1732. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1733. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1734. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1735. ucontrol->value.enumerated.item[0]);
  1736. return 0;
  1737. }
  1738. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1739. struct snd_ctl_elem_value *ucontrol)
  1740. {
  1741. int idx = aux_pcm_get_port_idx(kcontrol);
  1742. if (idx < 0)
  1743. return idx;
  1744. aux_pcm_tx_cfg[idx].sample_rate =
  1745. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1746. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1747. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1748. ucontrol->value.enumerated.item[0]);
  1749. return 0;
  1750. }
  1751. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1752. struct snd_ctl_elem_value *ucontrol)
  1753. {
  1754. int idx = aux_pcm_get_port_idx(kcontrol);
  1755. if (idx < 0)
  1756. return idx;
  1757. ucontrol->value.enumerated.item[0] =
  1758. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1759. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1760. idx, aux_pcm_rx_cfg[idx].bit_format,
  1761. ucontrol->value.enumerated.item[0]);
  1762. return 0;
  1763. }
  1764. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1765. struct snd_ctl_elem_value *ucontrol)
  1766. {
  1767. int idx = aux_pcm_get_port_idx(kcontrol);
  1768. if (idx < 0)
  1769. return idx;
  1770. aux_pcm_rx_cfg[idx].bit_format =
  1771. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1772. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1773. idx, aux_pcm_rx_cfg[idx].bit_format,
  1774. ucontrol->value.enumerated.item[0]);
  1775. return 0;
  1776. }
  1777. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1778. struct snd_ctl_elem_value *ucontrol)
  1779. {
  1780. int idx = aux_pcm_get_port_idx(kcontrol);
  1781. if (idx < 0)
  1782. return idx;
  1783. ucontrol->value.enumerated.item[0] =
  1784. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1785. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1786. idx, aux_pcm_tx_cfg[idx].bit_format,
  1787. ucontrol->value.enumerated.item[0]);
  1788. return 0;
  1789. }
  1790. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1791. struct snd_ctl_elem_value *ucontrol)
  1792. {
  1793. int idx = aux_pcm_get_port_idx(kcontrol);
  1794. if (idx < 0)
  1795. return idx;
  1796. aux_pcm_tx_cfg[idx].bit_format =
  1797. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1798. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1799. idx, aux_pcm_tx_cfg[idx].bit_format,
  1800. ucontrol->value.enumerated.item[0]);
  1801. return 0;
  1802. }
  1803. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1804. {
  1805. int idx = 0;
  1806. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1807. sizeof("PRIM_MI2S_RX"))) {
  1808. idx = PRIM_MI2S;
  1809. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1810. sizeof("SEC_MI2S_RX"))) {
  1811. idx = SEC_MI2S;
  1812. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1813. sizeof("TERT_MI2S_RX"))) {
  1814. idx = TERT_MI2S;
  1815. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  1816. sizeof("QUAT_MI2S_RX"))) {
  1817. idx = QUAT_MI2S;
  1818. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  1819. sizeof("QUIN_MI2S_RX"))) {
  1820. idx = QUIN_MI2S;
  1821. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  1822. sizeof("SEN_MI2S_RX"))) {
  1823. idx = SEN_MI2S;
  1824. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1825. sizeof("PRIM_MI2S_TX"))) {
  1826. idx = PRIM_MI2S;
  1827. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1828. sizeof("SEC_MI2S_TX"))) {
  1829. idx = SEC_MI2S;
  1830. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1831. sizeof("TERT_MI2S_TX"))) {
  1832. idx = TERT_MI2S;
  1833. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1834. sizeof("QUAT_MI2S_TX"))) {
  1835. idx = QUAT_MI2S;
  1836. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  1837. sizeof("QUIN_MI2S_TX"))) {
  1838. idx = QUIN_MI2S;
  1839. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  1840. sizeof("SEN_MI2S_TX"))) {
  1841. idx = SEN_MI2S;
  1842. } else {
  1843. pr_err("%s: unsupported channel: %s\n",
  1844. __func__, kcontrol->id.name);
  1845. idx = -EINVAL;
  1846. }
  1847. return idx;
  1848. }
  1849. static int mi2s_get_sample_rate(int value)
  1850. {
  1851. int sample_rate = 0;
  1852. switch (value) {
  1853. case 0:
  1854. sample_rate = SAMPLING_RATE_8KHZ;
  1855. break;
  1856. case 1:
  1857. sample_rate = SAMPLING_RATE_11P025KHZ;
  1858. break;
  1859. case 2:
  1860. sample_rate = SAMPLING_RATE_16KHZ;
  1861. break;
  1862. case 3:
  1863. sample_rate = SAMPLING_RATE_22P05KHZ;
  1864. break;
  1865. case 4:
  1866. sample_rate = SAMPLING_RATE_32KHZ;
  1867. break;
  1868. case 5:
  1869. sample_rate = SAMPLING_RATE_44P1KHZ;
  1870. break;
  1871. case 6:
  1872. sample_rate = SAMPLING_RATE_48KHZ;
  1873. break;
  1874. case 7:
  1875. sample_rate = SAMPLING_RATE_96KHZ;
  1876. break;
  1877. case 8:
  1878. sample_rate = SAMPLING_RATE_192KHZ;
  1879. break;
  1880. default:
  1881. sample_rate = SAMPLING_RATE_48KHZ;
  1882. break;
  1883. }
  1884. return sample_rate;
  1885. }
  1886. static int mi2s_get_sample_rate_val(int sample_rate)
  1887. {
  1888. int sample_rate_val = 0;
  1889. switch (sample_rate) {
  1890. case SAMPLING_RATE_8KHZ:
  1891. sample_rate_val = 0;
  1892. break;
  1893. case SAMPLING_RATE_11P025KHZ:
  1894. sample_rate_val = 1;
  1895. break;
  1896. case SAMPLING_RATE_16KHZ:
  1897. sample_rate_val = 2;
  1898. break;
  1899. case SAMPLING_RATE_22P05KHZ:
  1900. sample_rate_val = 3;
  1901. break;
  1902. case SAMPLING_RATE_32KHZ:
  1903. sample_rate_val = 4;
  1904. break;
  1905. case SAMPLING_RATE_44P1KHZ:
  1906. sample_rate_val = 5;
  1907. break;
  1908. case SAMPLING_RATE_48KHZ:
  1909. sample_rate_val = 6;
  1910. break;
  1911. case SAMPLING_RATE_96KHZ:
  1912. sample_rate_val = 7;
  1913. break;
  1914. case SAMPLING_RATE_192KHZ:
  1915. sample_rate_val = 8;
  1916. break;
  1917. default:
  1918. sample_rate_val = 6;
  1919. break;
  1920. }
  1921. return sample_rate_val;
  1922. }
  1923. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1924. struct snd_ctl_elem_value *ucontrol)
  1925. {
  1926. int idx = mi2s_get_port_idx(kcontrol);
  1927. if (idx < 0)
  1928. return idx;
  1929. ucontrol->value.enumerated.item[0] =
  1930. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1931. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1932. idx, mi2s_rx_cfg[idx].sample_rate,
  1933. ucontrol->value.enumerated.item[0]);
  1934. return 0;
  1935. }
  1936. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1937. struct snd_ctl_elem_value *ucontrol)
  1938. {
  1939. int idx = mi2s_get_port_idx(kcontrol);
  1940. if (idx < 0)
  1941. return idx;
  1942. mi2s_rx_cfg[idx].sample_rate =
  1943. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1944. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1945. idx, mi2s_rx_cfg[idx].sample_rate,
  1946. ucontrol->value.enumerated.item[0]);
  1947. return 0;
  1948. }
  1949. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1950. struct snd_ctl_elem_value *ucontrol)
  1951. {
  1952. int idx = mi2s_get_port_idx(kcontrol);
  1953. if (idx < 0)
  1954. return idx;
  1955. ucontrol->value.enumerated.item[0] =
  1956. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1957. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1958. idx, mi2s_tx_cfg[idx].sample_rate,
  1959. ucontrol->value.enumerated.item[0]);
  1960. return 0;
  1961. }
  1962. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1963. struct snd_ctl_elem_value *ucontrol)
  1964. {
  1965. int idx = mi2s_get_port_idx(kcontrol);
  1966. if (idx < 0)
  1967. return idx;
  1968. mi2s_tx_cfg[idx].sample_rate =
  1969. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1970. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1971. idx, mi2s_tx_cfg[idx].sample_rate,
  1972. ucontrol->value.enumerated.item[0]);
  1973. return 0;
  1974. }
  1975. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1976. struct snd_ctl_elem_value *ucontrol)
  1977. {
  1978. int idx = mi2s_get_port_idx(kcontrol);
  1979. if (idx < 0)
  1980. return idx;
  1981. ucontrol->value.enumerated.item[0] =
  1982. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1983. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1984. idx, mi2s_rx_cfg[idx].bit_format,
  1985. ucontrol->value.enumerated.item[0]);
  1986. return 0;
  1987. }
  1988. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1989. struct snd_ctl_elem_value *ucontrol)
  1990. {
  1991. int idx = mi2s_get_port_idx(kcontrol);
  1992. if (idx < 0)
  1993. return idx;
  1994. mi2s_rx_cfg[idx].bit_format =
  1995. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1996. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1997. idx, mi2s_rx_cfg[idx].bit_format,
  1998. ucontrol->value.enumerated.item[0]);
  1999. return 0;
  2000. }
  2001. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2002. struct snd_ctl_elem_value *ucontrol)
  2003. {
  2004. int idx = mi2s_get_port_idx(kcontrol);
  2005. if (idx < 0)
  2006. return idx;
  2007. ucontrol->value.enumerated.item[0] =
  2008. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2009. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2010. idx, mi2s_tx_cfg[idx].bit_format,
  2011. ucontrol->value.enumerated.item[0]);
  2012. return 0;
  2013. }
  2014. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2015. struct snd_ctl_elem_value *ucontrol)
  2016. {
  2017. int idx = mi2s_get_port_idx(kcontrol);
  2018. if (idx < 0)
  2019. return idx;
  2020. mi2s_tx_cfg[idx].bit_format =
  2021. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2022. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2023. idx, mi2s_tx_cfg[idx].bit_format,
  2024. ucontrol->value.enumerated.item[0]);
  2025. return 0;
  2026. }
  2027. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2028. struct snd_ctl_elem_value *ucontrol)
  2029. {
  2030. int idx = mi2s_get_port_idx(kcontrol);
  2031. if (idx < 0)
  2032. return idx;
  2033. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2034. idx, mi2s_rx_cfg[idx].channels);
  2035. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2036. return 0;
  2037. }
  2038. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2039. struct snd_ctl_elem_value *ucontrol)
  2040. {
  2041. int idx = mi2s_get_port_idx(kcontrol);
  2042. if (idx < 0)
  2043. return idx;
  2044. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2045. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2046. idx, mi2s_rx_cfg[idx].channels);
  2047. return 1;
  2048. }
  2049. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2050. struct snd_ctl_elem_value *ucontrol)
  2051. {
  2052. int idx = mi2s_get_port_idx(kcontrol);
  2053. if (idx < 0)
  2054. return idx;
  2055. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2056. idx, mi2s_tx_cfg[idx].channels);
  2057. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2058. return 0;
  2059. }
  2060. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2061. struct snd_ctl_elem_value *ucontrol)
  2062. {
  2063. int idx = mi2s_get_port_idx(kcontrol);
  2064. if (idx < 0)
  2065. return idx;
  2066. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2067. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2068. idx, mi2s_tx_cfg[idx].channels);
  2069. return 1;
  2070. }
  2071. static int msm_get_port_id(int be_id)
  2072. {
  2073. int afe_port_id = 0;
  2074. switch (be_id) {
  2075. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2076. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2077. break;
  2078. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2079. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2080. break;
  2081. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2082. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2083. break;
  2084. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2085. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2086. break;
  2087. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2088. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2089. break;
  2090. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2091. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2092. break;
  2093. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2094. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2095. break;
  2096. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2097. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2098. break;
  2099. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2100. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2101. break;
  2102. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2103. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2104. break;
  2105. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  2106. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  2107. break;
  2108. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  2109. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  2110. break;
  2111. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2112. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2113. break;
  2114. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2115. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2116. break;
  2117. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2118. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2119. break;
  2120. default:
  2121. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2122. afe_port_id = -EINVAL;
  2123. }
  2124. return afe_port_id;
  2125. }
  2126. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2127. {
  2128. u32 bit_per_sample = 0;
  2129. switch (bit_format) {
  2130. case SNDRV_PCM_FORMAT_S32_LE:
  2131. case SNDRV_PCM_FORMAT_S24_3LE:
  2132. case SNDRV_PCM_FORMAT_S24_LE:
  2133. bit_per_sample = 32;
  2134. break;
  2135. case SNDRV_PCM_FORMAT_S16_LE:
  2136. default:
  2137. bit_per_sample = 16;
  2138. break;
  2139. }
  2140. return bit_per_sample;
  2141. }
  2142. static void update_mi2s_clk_val(int dai_id, int stream)
  2143. {
  2144. u32 bit_per_sample = 0;
  2145. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2146. bit_per_sample =
  2147. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2148. mi2s_clk[dai_id].clk_freq_in_hz =
  2149. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2150. } else {
  2151. bit_per_sample =
  2152. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2153. mi2s_clk[dai_id].clk_freq_in_hz =
  2154. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2155. }
  2156. }
  2157. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2158. {
  2159. int ret = 0;
  2160. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2161. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2162. int port_id = 0;
  2163. int index = cpu_dai->id;
  2164. port_id = msm_get_port_id(rtd->dai_link->id);
  2165. if (port_id < 0) {
  2166. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2167. ret = port_id;
  2168. goto err;
  2169. }
  2170. if (enable) {
  2171. update_mi2s_clk_val(index, substream->stream);
  2172. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2173. mi2s_clk[index].clk_freq_in_hz);
  2174. }
  2175. mi2s_clk[index].enable = enable;
  2176. ret = afe_set_lpass_clock_v2(port_id,
  2177. &mi2s_clk[index]);
  2178. if (ret < 0) {
  2179. dev_err(rtd->card->dev,
  2180. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2181. __func__, port_id, ret);
  2182. goto err;
  2183. }
  2184. err:
  2185. return ret;
  2186. }
  2187. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2188. {
  2189. int idx = 0;
  2190. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  2191. sizeof("WSA_CDC_DMA_RX_0")))
  2192. idx = WSA_CDC_DMA_RX_0;
  2193. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  2194. sizeof("WSA_CDC_DMA_RX_0")))
  2195. idx = WSA_CDC_DMA_RX_1;
  2196. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2197. sizeof("RX_CDC_DMA_RX_0")))
  2198. idx = RX_CDC_DMA_RX_0;
  2199. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2200. sizeof("RX_CDC_DMA_RX_1")))
  2201. idx = RX_CDC_DMA_RX_1;
  2202. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2203. sizeof("RX_CDC_DMA_RX_2")))
  2204. idx = RX_CDC_DMA_RX_2;
  2205. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2206. sizeof("RX_CDC_DMA_RX_3")))
  2207. idx = RX_CDC_DMA_RX_3;
  2208. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2209. sizeof("RX_CDC_DMA_RX_5")))
  2210. idx = RX_CDC_DMA_RX_5;
  2211. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  2212. sizeof("WSA_CDC_DMA_TX_0")))
  2213. idx = WSA_CDC_DMA_TX_0;
  2214. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  2215. sizeof("WSA_CDC_DMA_TX_1")))
  2216. idx = WSA_CDC_DMA_TX_1;
  2217. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  2218. sizeof("WSA_CDC_DMA_TX_2")))
  2219. idx = WSA_CDC_DMA_TX_2;
  2220. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2221. sizeof("TX_CDC_DMA_TX_0")))
  2222. idx = TX_CDC_DMA_TX_0;
  2223. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2224. sizeof("TX_CDC_DMA_TX_3")))
  2225. idx = TX_CDC_DMA_TX_3;
  2226. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2227. sizeof("TX_CDC_DMA_TX_4")))
  2228. idx = TX_CDC_DMA_TX_4;
  2229. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2230. sizeof("VA_CDC_DMA_TX_0")))
  2231. idx = VA_CDC_DMA_TX_0;
  2232. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2233. sizeof("VA_CDC_DMA_TX_1")))
  2234. idx = VA_CDC_DMA_TX_1;
  2235. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2236. sizeof("VA_CDC_DMA_TX_2")))
  2237. idx = VA_CDC_DMA_TX_2;
  2238. else {
  2239. pr_err("%s: unsupported channel: %s\n",
  2240. __func__, kcontrol->id.name);
  2241. return -EINVAL;
  2242. }
  2243. return idx;
  2244. }
  2245. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2246. struct snd_ctl_elem_value *ucontrol)
  2247. {
  2248. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2249. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2250. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2251. return ch_num;
  2252. }
  2253. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2254. cdc_dma_rx_cfg[ch_num].channels - 1);
  2255. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2256. return 0;
  2257. }
  2258. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2259. struct snd_ctl_elem_value *ucontrol)
  2260. {
  2261. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2262. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2263. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2264. return ch_num;
  2265. }
  2266. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2267. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2268. cdc_dma_rx_cfg[ch_num].channels);
  2269. return 1;
  2270. }
  2271. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2272. struct snd_ctl_elem_value *ucontrol)
  2273. {
  2274. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2275. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2276. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2277. return ch_num;
  2278. }
  2279. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2280. case SNDRV_PCM_FORMAT_S32_LE:
  2281. ucontrol->value.integer.value[0] = 3;
  2282. break;
  2283. case SNDRV_PCM_FORMAT_S24_3LE:
  2284. ucontrol->value.integer.value[0] = 2;
  2285. break;
  2286. case SNDRV_PCM_FORMAT_S24_LE:
  2287. ucontrol->value.integer.value[0] = 1;
  2288. break;
  2289. case SNDRV_PCM_FORMAT_S16_LE:
  2290. default:
  2291. ucontrol->value.integer.value[0] = 0;
  2292. break;
  2293. }
  2294. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2295. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2296. ucontrol->value.integer.value[0]);
  2297. return 0;
  2298. }
  2299. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2300. struct snd_ctl_elem_value *ucontrol)
  2301. {
  2302. int rc = 0;
  2303. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2304. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2305. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2306. return ch_num;
  2307. }
  2308. switch (ucontrol->value.integer.value[0]) {
  2309. case 3:
  2310. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2311. break;
  2312. case 2:
  2313. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2314. break;
  2315. case 1:
  2316. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2317. break;
  2318. case 0:
  2319. default:
  2320. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2321. break;
  2322. }
  2323. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2324. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2325. ucontrol->value.integer.value[0]);
  2326. return rc;
  2327. }
  2328. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2329. {
  2330. int sample_rate_val = 0;
  2331. switch (sample_rate) {
  2332. case SAMPLING_RATE_8KHZ:
  2333. sample_rate_val = 0;
  2334. break;
  2335. case SAMPLING_RATE_11P025KHZ:
  2336. sample_rate_val = 1;
  2337. break;
  2338. case SAMPLING_RATE_16KHZ:
  2339. sample_rate_val = 2;
  2340. break;
  2341. case SAMPLING_RATE_22P05KHZ:
  2342. sample_rate_val = 3;
  2343. break;
  2344. case SAMPLING_RATE_32KHZ:
  2345. sample_rate_val = 4;
  2346. break;
  2347. case SAMPLING_RATE_44P1KHZ:
  2348. sample_rate_val = 5;
  2349. break;
  2350. case SAMPLING_RATE_48KHZ:
  2351. sample_rate_val = 6;
  2352. break;
  2353. case SAMPLING_RATE_88P2KHZ:
  2354. sample_rate_val = 7;
  2355. break;
  2356. case SAMPLING_RATE_96KHZ:
  2357. sample_rate_val = 8;
  2358. break;
  2359. case SAMPLING_RATE_176P4KHZ:
  2360. sample_rate_val = 9;
  2361. break;
  2362. case SAMPLING_RATE_192KHZ:
  2363. sample_rate_val = 10;
  2364. break;
  2365. case SAMPLING_RATE_352P8KHZ:
  2366. sample_rate_val = 11;
  2367. break;
  2368. case SAMPLING_RATE_384KHZ:
  2369. sample_rate_val = 12;
  2370. break;
  2371. default:
  2372. sample_rate_val = 6;
  2373. break;
  2374. }
  2375. return sample_rate_val;
  2376. }
  2377. static int cdc_dma_get_sample_rate(int value)
  2378. {
  2379. int sample_rate = 0;
  2380. switch (value) {
  2381. case 0:
  2382. sample_rate = SAMPLING_RATE_8KHZ;
  2383. break;
  2384. case 1:
  2385. sample_rate = SAMPLING_RATE_11P025KHZ;
  2386. break;
  2387. case 2:
  2388. sample_rate = SAMPLING_RATE_16KHZ;
  2389. break;
  2390. case 3:
  2391. sample_rate = SAMPLING_RATE_22P05KHZ;
  2392. break;
  2393. case 4:
  2394. sample_rate = SAMPLING_RATE_32KHZ;
  2395. break;
  2396. case 5:
  2397. sample_rate = SAMPLING_RATE_44P1KHZ;
  2398. break;
  2399. case 6:
  2400. sample_rate = SAMPLING_RATE_48KHZ;
  2401. break;
  2402. case 7:
  2403. sample_rate = SAMPLING_RATE_88P2KHZ;
  2404. break;
  2405. case 8:
  2406. sample_rate = SAMPLING_RATE_96KHZ;
  2407. break;
  2408. case 9:
  2409. sample_rate = SAMPLING_RATE_176P4KHZ;
  2410. break;
  2411. case 10:
  2412. sample_rate = SAMPLING_RATE_192KHZ;
  2413. break;
  2414. case 11:
  2415. sample_rate = SAMPLING_RATE_352P8KHZ;
  2416. break;
  2417. case 12:
  2418. sample_rate = SAMPLING_RATE_384KHZ;
  2419. break;
  2420. default:
  2421. sample_rate = SAMPLING_RATE_48KHZ;
  2422. break;
  2423. }
  2424. return sample_rate;
  2425. }
  2426. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2427. struct snd_ctl_elem_value *ucontrol)
  2428. {
  2429. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2430. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2431. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2432. return ch_num;
  2433. }
  2434. ucontrol->value.enumerated.item[0] =
  2435. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2436. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2437. cdc_dma_rx_cfg[ch_num].sample_rate);
  2438. return 0;
  2439. }
  2440. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2441. struct snd_ctl_elem_value *ucontrol)
  2442. {
  2443. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2444. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2445. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2446. return ch_num;
  2447. }
  2448. cdc_dma_rx_cfg[ch_num].sample_rate =
  2449. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2450. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2451. __func__, ucontrol->value.enumerated.item[0],
  2452. cdc_dma_rx_cfg[ch_num].sample_rate);
  2453. return 0;
  2454. }
  2455. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2456. struct snd_ctl_elem_value *ucontrol)
  2457. {
  2458. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2459. if (ch_num < 0) {
  2460. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2461. return ch_num;
  2462. }
  2463. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2464. cdc_dma_tx_cfg[ch_num].channels);
  2465. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2466. return 0;
  2467. }
  2468. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2469. struct snd_ctl_elem_value *ucontrol)
  2470. {
  2471. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2472. if (ch_num < 0) {
  2473. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2474. return ch_num;
  2475. }
  2476. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2477. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2478. cdc_dma_tx_cfg[ch_num].channels);
  2479. return 1;
  2480. }
  2481. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2482. struct snd_ctl_elem_value *ucontrol)
  2483. {
  2484. int sample_rate_val;
  2485. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2486. if (ch_num < 0) {
  2487. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2488. return ch_num;
  2489. }
  2490. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2491. case SAMPLING_RATE_384KHZ:
  2492. sample_rate_val = 12;
  2493. break;
  2494. case SAMPLING_RATE_352P8KHZ:
  2495. sample_rate_val = 11;
  2496. break;
  2497. case SAMPLING_RATE_192KHZ:
  2498. sample_rate_val = 10;
  2499. break;
  2500. case SAMPLING_RATE_176P4KHZ:
  2501. sample_rate_val = 9;
  2502. break;
  2503. case SAMPLING_RATE_96KHZ:
  2504. sample_rate_val = 8;
  2505. break;
  2506. case SAMPLING_RATE_88P2KHZ:
  2507. sample_rate_val = 7;
  2508. break;
  2509. case SAMPLING_RATE_48KHZ:
  2510. sample_rate_val = 6;
  2511. break;
  2512. case SAMPLING_RATE_44P1KHZ:
  2513. sample_rate_val = 5;
  2514. break;
  2515. case SAMPLING_RATE_32KHZ:
  2516. sample_rate_val = 4;
  2517. break;
  2518. case SAMPLING_RATE_22P05KHZ:
  2519. sample_rate_val = 3;
  2520. break;
  2521. case SAMPLING_RATE_16KHZ:
  2522. sample_rate_val = 2;
  2523. break;
  2524. case SAMPLING_RATE_11P025KHZ:
  2525. sample_rate_val = 1;
  2526. break;
  2527. case SAMPLING_RATE_8KHZ:
  2528. sample_rate_val = 0;
  2529. break;
  2530. default:
  2531. sample_rate_val = 6;
  2532. break;
  2533. }
  2534. ucontrol->value.integer.value[0] = sample_rate_val;
  2535. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2536. cdc_dma_tx_cfg[ch_num].sample_rate);
  2537. return 0;
  2538. }
  2539. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2540. struct snd_ctl_elem_value *ucontrol)
  2541. {
  2542. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2543. if (ch_num < 0) {
  2544. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2545. return ch_num;
  2546. }
  2547. switch (ucontrol->value.integer.value[0]) {
  2548. case 12:
  2549. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2550. break;
  2551. case 11:
  2552. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2553. break;
  2554. case 10:
  2555. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2556. break;
  2557. case 9:
  2558. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2559. break;
  2560. case 8:
  2561. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2562. break;
  2563. case 7:
  2564. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2565. break;
  2566. case 6:
  2567. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2568. break;
  2569. case 5:
  2570. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2571. break;
  2572. case 4:
  2573. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2574. break;
  2575. case 3:
  2576. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2577. break;
  2578. case 2:
  2579. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2580. break;
  2581. case 1:
  2582. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2583. break;
  2584. case 0:
  2585. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2586. break;
  2587. default:
  2588. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2589. break;
  2590. }
  2591. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2592. __func__, ucontrol->value.integer.value[0],
  2593. cdc_dma_tx_cfg[ch_num].sample_rate);
  2594. return 0;
  2595. }
  2596. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2597. struct snd_ctl_elem_value *ucontrol)
  2598. {
  2599. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2600. if (ch_num < 0) {
  2601. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2602. return ch_num;
  2603. }
  2604. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2605. case SNDRV_PCM_FORMAT_S32_LE:
  2606. ucontrol->value.integer.value[0] = 3;
  2607. break;
  2608. case SNDRV_PCM_FORMAT_S24_3LE:
  2609. ucontrol->value.integer.value[0] = 2;
  2610. break;
  2611. case SNDRV_PCM_FORMAT_S24_LE:
  2612. ucontrol->value.integer.value[0] = 1;
  2613. break;
  2614. case SNDRV_PCM_FORMAT_S16_LE:
  2615. default:
  2616. ucontrol->value.integer.value[0] = 0;
  2617. break;
  2618. }
  2619. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2620. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2621. ucontrol->value.integer.value[0]);
  2622. return 0;
  2623. }
  2624. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2625. struct snd_ctl_elem_value *ucontrol)
  2626. {
  2627. int rc = 0;
  2628. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2629. if (ch_num < 0) {
  2630. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2631. return ch_num;
  2632. }
  2633. switch (ucontrol->value.integer.value[0]) {
  2634. case 3:
  2635. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2636. break;
  2637. case 2:
  2638. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2639. break;
  2640. case 1:
  2641. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2642. break;
  2643. case 0:
  2644. default:
  2645. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2646. break;
  2647. }
  2648. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2649. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2650. ucontrol->value.integer.value[0]);
  2651. return rc;
  2652. }
  2653. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2654. {
  2655. int idx = 0;
  2656. switch (be_id) {
  2657. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  2658. idx = WSA_CDC_DMA_RX_0;
  2659. break;
  2660. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  2661. idx = WSA_CDC_DMA_TX_0;
  2662. break;
  2663. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  2664. idx = WSA_CDC_DMA_RX_1;
  2665. break;
  2666. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  2667. idx = WSA_CDC_DMA_TX_1;
  2668. break;
  2669. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  2670. idx = WSA_CDC_DMA_TX_2;
  2671. break;
  2672. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2673. idx = RX_CDC_DMA_RX_0;
  2674. break;
  2675. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2676. idx = RX_CDC_DMA_RX_1;
  2677. break;
  2678. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2679. idx = RX_CDC_DMA_RX_2;
  2680. break;
  2681. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2682. idx = RX_CDC_DMA_RX_3;
  2683. break;
  2684. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2685. idx = RX_CDC_DMA_RX_5;
  2686. break;
  2687. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2688. idx = TX_CDC_DMA_TX_0;
  2689. break;
  2690. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2691. idx = TX_CDC_DMA_TX_3;
  2692. break;
  2693. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2694. idx = TX_CDC_DMA_TX_4;
  2695. break;
  2696. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2697. idx = VA_CDC_DMA_TX_0;
  2698. break;
  2699. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2700. idx = VA_CDC_DMA_TX_1;
  2701. break;
  2702. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2703. idx = VA_CDC_DMA_TX_2;
  2704. break;
  2705. default:
  2706. idx = RX_CDC_DMA_RX_0;
  2707. break;
  2708. }
  2709. return idx;
  2710. }
  2711. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2712. struct snd_ctl_elem_value *ucontrol)
  2713. {
  2714. /*
  2715. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2716. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2717. * value.
  2718. */
  2719. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2720. case SAMPLING_RATE_96KHZ:
  2721. ucontrol->value.integer.value[0] = 5;
  2722. break;
  2723. case SAMPLING_RATE_88P2KHZ:
  2724. ucontrol->value.integer.value[0] = 4;
  2725. break;
  2726. case SAMPLING_RATE_48KHZ:
  2727. ucontrol->value.integer.value[0] = 3;
  2728. break;
  2729. case SAMPLING_RATE_44P1KHZ:
  2730. ucontrol->value.integer.value[0] = 2;
  2731. break;
  2732. case SAMPLING_RATE_16KHZ:
  2733. ucontrol->value.integer.value[0] = 1;
  2734. break;
  2735. case SAMPLING_RATE_8KHZ:
  2736. default:
  2737. ucontrol->value.integer.value[0] = 0;
  2738. break;
  2739. }
  2740. pr_debug("%s: sample rate = %d\n", __func__,
  2741. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2742. return 0;
  2743. }
  2744. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2745. struct snd_ctl_elem_value *ucontrol)
  2746. {
  2747. switch (ucontrol->value.integer.value[0]) {
  2748. case 1:
  2749. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2750. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2751. break;
  2752. case 2:
  2753. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2754. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2755. break;
  2756. case 3:
  2757. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2758. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2759. break;
  2760. case 4:
  2761. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2762. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2763. break;
  2764. case 5:
  2765. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2766. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2767. break;
  2768. case 0:
  2769. default:
  2770. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2771. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2772. break;
  2773. }
  2774. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2775. __func__,
  2776. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2777. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2778. ucontrol->value.enumerated.item[0]);
  2779. return 0;
  2780. }
  2781. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2782. struct snd_ctl_elem_value *ucontrol)
  2783. {
  2784. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2785. case SAMPLING_RATE_96KHZ:
  2786. ucontrol->value.integer.value[0] = 5;
  2787. break;
  2788. case SAMPLING_RATE_88P2KHZ:
  2789. ucontrol->value.integer.value[0] = 4;
  2790. break;
  2791. case SAMPLING_RATE_48KHZ:
  2792. ucontrol->value.integer.value[0] = 3;
  2793. break;
  2794. case SAMPLING_RATE_44P1KHZ:
  2795. ucontrol->value.integer.value[0] = 2;
  2796. break;
  2797. case SAMPLING_RATE_16KHZ:
  2798. ucontrol->value.integer.value[0] = 1;
  2799. break;
  2800. case SAMPLING_RATE_8KHZ:
  2801. default:
  2802. ucontrol->value.integer.value[0] = 0;
  2803. break;
  2804. }
  2805. pr_debug("%s: sample rate rx = %d\n", __func__,
  2806. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2807. return 0;
  2808. }
  2809. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2810. struct snd_ctl_elem_value *ucontrol)
  2811. {
  2812. switch (ucontrol->value.integer.value[0]) {
  2813. case 1:
  2814. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2815. break;
  2816. case 2:
  2817. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2818. break;
  2819. case 3:
  2820. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2821. break;
  2822. case 4:
  2823. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2824. break;
  2825. case 5:
  2826. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2827. break;
  2828. case 0:
  2829. default:
  2830. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2831. break;
  2832. }
  2833. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2834. __func__,
  2835. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2836. ucontrol->value.enumerated.item[0]);
  2837. return 0;
  2838. }
  2839. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2840. struct snd_ctl_elem_value *ucontrol)
  2841. {
  2842. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2843. case SAMPLING_RATE_96KHZ:
  2844. ucontrol->value.integer.value[0] = 5;
  2845. break;
  2846. case SAMPLING_RATE_88P2KHZ:
  2847. ucontrol->value.integer.value[0] = 4;
  2848. break;
  2849. case SAMPLING_RATE_48KHZ:
  2850. ucontrol->value.integer.value[0] = 3;
  2851. break;
  2852. case SAMPLING_RATE_44P1KHZ:
  2853. ucontrol->value.integer.value[0] = 2;
  2854. break;
  2855. case SAMPLING_RATE_16KHZ:
  2856. ucontrol->value.integer.value[0] = 1;
  2857. break;
  2858. case SAMPLING_RATE_8KHZ:
  2859. default:
  2860. ucontrol->value.integer.value[0] = 0;
  2861. break;
  2862. }
  2863. pr_debug("%s: sample rate tx = %d\n", __func__,
  2864. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2865. return 0;
  2866. }
  2867. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2868. struct snd_ctl_elem_value *ucontrol)
  2869. {
  2870. switch (ucontrol->value.integer.value[0]) {
  2871. case 1:
  2872. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2873. break;
  2874. case 2:
  2875. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2876. break;
  2877. case 3:
  2878. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2879. break;
  2880. case 4:
  2881. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2882. break;
  2883. case 5:
  2884. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2885. break;
  2886. case 0:
  2887. default:
  2888. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2889. break;
  2890. }
  2891. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2892. __func__,
  2893. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2894. ucontrol->value.enumerated.item[0]);
  2895. return 0;
  2896. }
  2897. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2898. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2899. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2900. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2901. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2902. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2903. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2904. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2905. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2906. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2907. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2908. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2909. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2910. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2911. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2912. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2913. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2914. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2915. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2916. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2917. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2918. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2919. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2920. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2921. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2922. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2923. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2924. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2925. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2926. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2927. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2928. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2929. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2930. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2931. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2932. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2933. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2934. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2935. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2936. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2937. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2938. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2939. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2940. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2941. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2942. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2943. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2944. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2945. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2946. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2947. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2948. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2949. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2950. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2951. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2952. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2953. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2954. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2955. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2956. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2957. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2958. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2959. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2960. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2961. wsa_cdc_dma_rx_0_sample_rate,
  2962. cdc_dma_rx_sample_rate_get,
  2963. cdc_dma_rx_sample_rate_put),
  2964. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2965. wsa_cdc_dma_rx_1_sample_rate,
  2966. cdc_dma_rx_sample_rate_get,
  2967. cdc_dma_rx_sample_rate_put),
  2968. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2969. rx_cdc_dma_rx_0_sample_rate,
  2970. cdc_dma_rx_sample_rate_get,
  2971. cdc_dma_rx_sample_rate_put),
  2972. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2973. rx_cdc_dma_rx_1_sample_rate,
  2974. cdc_dma_rx_sample_rate_get,
  2975. cdc_dma_rx_sample_rate_put),
  2976. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2977. rx_cdc_dma_rx_2_sample_rate,
  2978. cdc_dma_rx_sample_rate_get,
  2979. cdc_dma_rx_sample_rate_put),
  2980. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2981. rx_cdc_dma_rx_3_sample_rate,
  2982. cdc_dma_rx_sample_rate_get,
  2983. cdc_dma_rx_sample_rate_put),
  2984. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2985. rx_cdc_dma_rx_5_sample_rate,
  2986. cdc_dma_rx_sample_rate_get,
  2987. cdc_dma_rx_sample_rate_put),
  2988. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2989. wsa_cdc_dma_tx_0_sample_rate,
  2990. cdc_dma_tx_sample_rate_get,
  2991. cdc_dma_tx_sample_rate_put),
  2992. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2993. wsa_cdc_dma_tx_1_sample_rate,
  2994. cdc_dma_tx_sample_rate_get,
  2995. cdc_dma_tx_sample_rate_put),
  2996. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2997. wsa_cdc_dma_tx_2_sample_rate,
  2998. cdc_dma_tx_sample_rate_get,
  2999. cdc_dma_tx_sample_rate_put),
  3000. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  3001. tx_cdc_dma_tx_0_sample_rate,
  3002. cdc_dma_tx_sample_rate_get,
  3003. cdc_dma_tx_sample_rate_put),
  3004. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  3005. tx_cdc_dma_tx_3_sample_rate,
  3006. cdc_dma_tx_sample_rate_get,
  3007. cdc_dma_tx_sample_rate_put),
  3008. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  3009. tx_cdc_dma_tx_4_sample_rate,
  3010. cdc_dma_tx_sample_rate_get,
  3011. cdc_dma_tx_sample_rate_put),
  3012. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3013. va_cdc_dma_tx_0_sample_rate,
  3014. cdc_dma_tx_sample_rate_get,
  3015. cdc_dma_tx_sample_rate_put),
  3016. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3017. va_cdc_dma_tx_1_sample_rate,
  3018. cdc_dma_tx_sample_rate_get,
  3019. cdc_dma_tx_sample_rate_put),
  3020. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  3021. va_cdc_dma_tx_2_sample_rate,
  3022. cdc_dma_tx_sample_rate_get,
  3023. cdc_dma_tx_sample_rate_put),
  3024. };
  3025. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  3026. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3027. usb_audio_rx_sample_rate_get,
  3028. usb_audio_rx_sample_rate_put),
  3029. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3030. usb_audio_tx_sample_rate_get,
  3031. usb_audio_tx_sample_rate_put),
  3032. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3033. tdm_rx_sample_rate_get,
  3034. tdm_rx_sample_rate_put),
  3035. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3036. tdm_rx_sample_rate_get,
  3037. tdm_rx_sample_rate_put),
  3038. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3039. tdm_rx_sample_rate_get,
  3040. tdm_rx_sample_rate_put),
  3041. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3042. tdm_rx_sample_rate_get,
  3043. tdm_rx_sample_rate_put),
  3044. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3045. tdm_rx_sample_rate_get,
  3046. tdm_rx_sample_rate_put),
  3047. SOC_ENUM_EXT("SEN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3048. tdm_rx_sample_rate_get,
  3049. tdm_rx_sample_rate_put),
  3050. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3051. tdm_tx_sample_rate_get,
  3052. tdm_tx_sample_rate_put),
  3053. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3054. tdm_tx_sample_rate_get,
  3055. tdm_tx_sample_rate_put),
  3056. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3057. tdm_tx_sample_rate_get,
  3058. tdm_tx_sample_rate_put),
  3059. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3060. tdm_tx_sample_rate_get,
  3061. tdm_tx_sample_rate_put),
  3062. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3063. tdm_tx_sample_rate_get,
  3064. tdm_tx_sample_rate_put),
  3065. SOC_ENUM_EXT("SEN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3066. tdm_tx_sample_rate_get,
  3067. tdm_tx_sample_rate_put),
  3068. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3069. aux_pcm_rx_sample_rate_get,
  3070. aux_pcm_rx_sample_rate_put),
  3071. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3072. aux_pcm_rx_sample_rate_get,
  3073. aux_pcm_rx_sample_rate_put),
  3074. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3075. aux_pcm_rx_sample_rate_get,
  3076. aux_pcm_rx_sample_rate_put),
  3077. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3078. aux_pcm_rx_sample_rate_get,
  3079. aux_pcm_rx_sample_rate_put),
  3080. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3081. aux_pcm_rx_sample_rate_get,
  3082. aux_pcm_rx_sample_rate_put),
  3083. SOC_ENUM_EXT("SEN_AUX_PCM_RX SampleRate", sen_aux_pcm_rx_sample_rate,
  3084. aux_pcm_rx_sample_rate_get,
  3085. aux_pcm_rx_sample_rate_put),
  3086. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3087. aux_pcm_tx_sample_rate_get,
  3088. aux_pcm_tx_sample_rate_put),
  3089. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3090. aux_pcm_tx_sample_rate_get,
  3091. aux_pcm_tx_sample_rate_put),
  3092. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3093. aux_pcm_tx_sample_rate_get,
  3094. aux_pcm_tx_sample_rate_put),
  3095. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3096. aux_pcm_tx_sample_rate_get,
  3097. aux_pcm_tx_sample_rate_put),
  3098. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3099. aux_pcm_tx_sample_rate_get,
  3100. aux_pcm_tx_sample_rate_put),
  3101. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3102. aux_pcm_tx_sample_rate_get,
  3103. aux_pcm_tx_sample_rate_put),
  3104. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3105. mi2s_rx_sample_rate_get,
  3106. mi2s_rx_sample_rate_put),
  3107. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3108. mi2s_rx_sample_rate_get,
  3109. mi2s_rx_sample_rate_put),
  3110. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3111. mi2s_rx_sample_rate_get,
  3112. mi2s_rx_sample_rate_put),
  3113. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3114. mi2s_rx_sample_rate_get,
  3115. mi2s_rx_sample_rate_put),
  3116. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3117. mi2s_rx_sample_rate_get,
  3118. mi2s_rx_sample_rate_put),
  3119. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3120. mi2s_rx_sample_rate_get,
  3121. mi2s_rx_sample_rate_put),
  3122. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3123. mi2s_tx_sample_rate_get,
  3124. mi2s_tx_sample_rate_put),
  3125. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3126. mi2s_tx_sample_rate_get,
  3127. mi2s_tx_sample_rate_put),
  3128. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3129. mi2s_tx_sample_rate_get,
  3130. mi2s_tx_sample_rate_put),
  3131. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3132. mi2s_tx_sample_rate_get,
  3133. mi2s_tx_sample_rate_put),
  3134. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3135. mi2s_tx_sample_rate_get,
  3136. mi2s_tx_sample_rate_put),
  3137. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3138. mi2s_tx_sample_rate_get,
  3139. mi2s_tx_sample_rate_put),
  3140. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3141. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3142. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3143. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3144. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3145. tdm_rx_format_get,
  3146. tdm_rx_format_put),
  3147. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3148. tdm_rx_format_get,
  3149. tdm_rx_format_put),
  3150. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3151. tdm_rx_format_get,
  3152. tdm_rx_format_put),
  3153. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3154. tdm_rx_format_get,
  3155. tdm_rx_format_put),
  3156. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3157. tdm_rx_format_get,
  3158. tdm_rx_format_put),
  3159. SOC_ENUM_EXT("SEN_TDM_RX_0 Format", tdm_rx_format,
  3160. tdm_rx_format_get,
  3161. tdm_rx_format_put),
  3162. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3163. tdm_tx_format_get,
  3164. tdm_tx_format_put),
  3165. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3166. tdm_tx_format_get,
  3167. tdm_tx_format_put),
  3168. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3169. tdm_tx_format_get,
  3170. tdm_tx_format_put),
  3171. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3172. tdm_tx_format_get,
  3173. tdm_tx_format_put),
  3174. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3175. tdm_tx_format_get,
  3176. tdm_tx_format_put),
  3177. SOC_ENUM_EXT("SEN_TDM_TX_0 Format", tdm_tx_format,
  3178. tdm_tx_format_get,
  3179. tdm_tx_format_put),
  3180. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3181. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3182. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3183. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3184. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3185. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3186. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3187. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3188. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3189. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3190. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3191. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3192. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3193. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3194. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3195. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3196. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3197. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3198. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3199. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3200. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3201. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3202. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3203. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3204. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3205. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3206. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3207. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3208. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3209. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3210. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3211. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3212. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3213. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3214. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3215. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3216. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3217. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3218. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3219. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3220. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3221. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3222. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3223. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3224. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3225. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3226. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3227. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3228. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3229. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3230. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3231. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3232. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3233. proxy_rx_ch_get, proxy_rx_ch_put),
  3234. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3235. tdm_rx_ch_get,
  3236. tdm_rx_ch_put),
  3237. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3238. tdm_rx_ch_get,
  3239. tdm_rx_ch_put),
  3240. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3241. tdm_rx_ch_get,
  3242. tdm_rx_ch_put),
  3243. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3244. tdm_rx_ch_get,
  3245. tdm_rx_ch_put),
  3246. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3247. tdm_rx_ch_get,
  3248. tdm_rx_ch_put),
  3249. SOC_ENUM_EXT("SEN_TDM_RX_0 Channels", tdm_rx_chs,
  3250. tdm_rx_ch_get,
  3251. tdm_rx_ch_put),
  3252. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3253. tdm_tx_ch_get,
  3254. tdm_tx_ch_put),
  3255. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3256. tdm_tx_ch_get,
  3257. tdm_tx_ch_put),
  3258. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3259. tdm_tx_ch_get,
  3260. tdm_tx_ch_put),
  3261. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3262. tdm_tx_ch_get,
  3263. tdm_tx_ch_put),
  3264. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3265. tdm_tx_ch_get,
  3266. tdm_tx_ch_put),
  3267. SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs,
  3268. tdm_tx_ch_get,
  3269. tdm_tx_ch_put),
  3270. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3271. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3272. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3273. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3274. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3275. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3276. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3277. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3278. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3279. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3280. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3281. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3282. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3283. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3284. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3285. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3286. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3287. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3288. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3289. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3290. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3291. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3292. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3293. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3294. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  3295. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3296. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  3297. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3298. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  3299. ext_disp_rx_sample_rate_get,
  3300. ext_disp_rx_sample_rate_put),
  3301. SOC_ENUM_EXT("Display Port1 RX Channels", ext_disp_rx_chs,
  3302. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3303. SOC_ENUM_EXT("Display Port1 RX Bit Format", ext_disp_rx_format,
  3304. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3305. SOC_ENUM_EXT("Display Port1 RX SampleRate", ext_disp_rx_sample_rate,
  3306. ext_disp_rx_sample_rate_get,
  3307. ext_disp_rx_sample_rate_put),
  3308. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3309. msm_bt_sample_rate_get,
  3310. msm_bt_sample_rate_put),
  3311. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3312. msm_bt_sample_rate_rx_get,
  3313. msm_bt_sample_rate_rx_put),
  3314. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3315. msm_bt_sample_rate_tx_get,
  3316. msm_bt_sample_rate_tx_put),
  3317. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3318. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3319. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3320. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3321. };
  3322. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3323. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3324. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3325. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3326. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3327. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3328. aux_pcm_rx_sample_rate_get,
  3329. aux_pcm_rx_sample_rate_put),
  3330. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3331. aux_pcm_tx_sample_rate_get,
  3332. aux_pcm_tx_sample_rate_put),
  3333. };
  3334. static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
  3335. {
  3336. int idx;
  3337. switch (be_id) {
  3338. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3339. idx = EXT_DISP_RX_IDX_DP;
  3340. break;
  3341. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3342. idx = EXT_DISP_RX_IDX_DP1;
  3343. break;
  3344. default:
  3345. pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
  3346. idx = -EINVAL;
  3347. break;
  3348. }
  3349. return idx;
  3350. }
  3351. static int kona_send_island_va_config(int32_t be_id)
  3352. {
  3353. int rc = 0;
  3354. int port_id = 0xFFFF;
  3355. port_id = msm_get_port_id(be_id);
  3356. if (port_id < 0) {
  3357. pr_err("%s: Invalid island interface, be_id: %d\n",
  3358. __func__, be_id);
  3359. rc = -EINVAL;
  3360. } else {
  3361. /*
  3362. * send island mode config
  3363. * This should be the first configuration
  3364. */
  3365. rc = afe_send_port_island_mode(port_id);
  3366. if (rc)
  3367. pr_err("%s: afe send island mode failed %d\n",
  3368. __func__, rc);
  3369. }
  3370. return rc;
  3371. }
  3372. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3373. struct snd_pcm_hw_params *params)
  3374. {
  3375. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3376. struct snd_interval *rate = hw_param_interval(params,
  3377. SNDRV_PCM_HW_PARAM_RATE);
  3378. struct snd_interval *channels = hw_param_interval(params,
  3379. SNDRV_PCM_HW_PARAM_CHANNELS);
  3380. int idx = 0, rc = 0;
  3381. pr_debug("%s: format = %d, rate = %d\n",
  3382. __func__, params_format(params), params_rate(params));
  3383. switch (dai_link->id) {
  3384. case MSM_BACKEND_DAI_USB_RX:
  3385. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3386. usb_rx_cfg.bit_format);
  3387. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3388. channels->min = channels->max = usb_rx_cfg.channels;
  3389. break;
  3390. case MSM_BACKEND_DAI_USB_TX:
  3391. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3392. usb_tx_cfg.bit_format);
  3393. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3394. channels->min = channels->max = usb_tx_cfg.channels;
  3395. break;
  3396. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3397. case MSM_BACKEND_DAI_DISPLAY_PORT_RX_1:
  3398. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  3399. if (idx < 0) {
  3400. pr_err("%s: Incorrect ext disp idx %d\n",
  3401. __func__, idx);
  3402. rc = idx;
  3403. goto done;
  3404. }
  3405. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3406. ext_disp_rx_cfg[idx].bit_format);
  3407. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  3408. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  3409. break;
  3410. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3411. channels->min = channels->max = proxy_rx_cfg.channels;
  3412. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3413. break;
  3414. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3415. channels->min = channels->max =
  3416. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3417. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3418. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3419. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3420. break;
  3421. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3422. channels->min = channels->max =
  3423. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3424. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3425. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3426. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3427. break;
  3428. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3429. channels->min = channels->max =
  3430. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3431. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3432. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3433. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3434. break;
  3435. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3436. channels->min = channels->max =
  3437. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3438. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3439. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3440. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3441. break;
  3442. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3443. channels->min = channels->max =
  3444. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3445. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3446. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3447. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3448. break;
  3449. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3450. channels->min = channels->max =
  3451. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3452. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3453. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3454. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3455. break;
  3456. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3457. channels->min = channels->max =
  3458. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3459. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3460. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3461. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3462. break;
  3463. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3464. channels->min = channels->max =
  3465. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3466. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3467. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3468. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3469. break;
  3470. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3471. channels->min = channels->max =
  3472. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3473. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3474. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3475. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3476. break;
  3477. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3478. channels->min = channels->max =
  3479. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3480. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3481. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3482. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3483. break;
  3484. case MSM_BACKEND_DAI_SEN_TDM_RX_0:
  3485. channels->min = channels->max =
  3486. tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3487. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3488. tdm_rx_cfg[TDM_SEN][TDM_0].bit_format);
  3489. rate->min = rate->max = tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate;
  3490. break;
  3491. case MSM_BACKEND_DAI_SEN_TDM_TX_0:
  3492. channels->min = channels->max =
  3493. tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3494. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3495. tdm_tx_cfg[TDM_SEN][TDM_0].bit_format);
  3496. rate->min = rate->max = tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate;
  3497. break;
  3498. case MSM_BACKEND_DAI_AUXPCM_RX:
  3499. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3500. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3501. rate->min = rate->max =
  3502. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3503. channels->min = channels->max =
  3504. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3505. break;
  3506. case MSM_BACKEND_DAI_AUXPCM_TX:
  3507. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3508. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3509. rate->min = rate->max =
  3510. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3511. channels->min = channels->max =
  3512. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3513. break;
  3514. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3515. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3516. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3517. rate->min = rate->max =
  3518. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3519. channels->min = channels->max =
  3520. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3521. break;
  3522. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3523. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3524. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3525. rate->min = rate->max =
  3526. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3527. channels->min = channels->max =
  3528. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3529. break;
  3530. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3531. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3532. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3533. rate->min = rate->max =
  3534. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3535. channels->min = channels->max =
  3536. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3537. break;
  3538. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3539. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3540. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3541. rate->min = rate->max =
  3542. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3543. channels->min = channels->max =
  3544. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3545. break;
  3546. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3547. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3548. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3549. rate->min = rate->max =
  3550. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3551. channels->min = channels->max =
  3552. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3553. break;
  3554. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3555. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3556. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3557. rate->min = rate->max =
  3558. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3559. channels->min = channels->max =
  3560. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3561. break;
  3562. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3563. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3564. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3565. rate->min = rate->max =
  3566. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3567. channels->min = channels->max =
  3568. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3569. break;
  3570. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3571. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3572. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3573. rate->min = rate->max =
  3574. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3575. channels->min = channels->max =
  3576. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3577. break;
  3578. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3579. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3580. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3581. rate->min = rate->max =
  3582. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3583. channels->min = channels->max =
  3584. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3585. break;
  3586. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3587. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3588. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3589. rate->min = rate->max =
  3590. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3591. channels->min = channels->max =
  3592. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3593. break;
  3594. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3595. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3596. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3597. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3598. channels->min = channels->max =
  3599. mi2s_rx_cfg[PRIM_MI2S].channels;
  3600. break;
  3601. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3602. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3603. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3604. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3605. channels->min = channels->max =
  3606. mi2s_tx_cfg[PRIM_MI2S].channels;
  3607. break;
  3608. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3609. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3610. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3611. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3612. channels->min = channels->max =
  3613. mi2s_rx_cfg[SEC_MI2S].channels;
  3614. break;
  3615. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3616. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3617. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3618. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3619. channels->min = channels->max =
  3620. mi2s_tx_cfg[SEC_MI2S].channels;
  3621. break;
  3622. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3623. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3624. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3625. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3626. channels->min = channels->max =
  3627. mi2s_rx_cfg[TERT_MI2S].channels;
  3628. break;
  3629. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3630. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3631. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3632. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3633. channels->min = channels->max =
  3634. mi2s_tx_cfg[TERT_MI2S].channels;
  3635. break;
  3636. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3637. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3638. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3639. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3640. channels->min = channels->max =
  3641. mi2s_rx_cfg[QUAT_MI2S].channels;
  3642. break;
  3643. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3644. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3645. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3646. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3647. channels->min = channels->max =
  3648. mi2s_tx_cfg[QUAT_MI2S].channels;
  3649. break;
  3650. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3651. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3652. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3653. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3654. channels->min = channels->max =
  3655. mi2s_rx_cfg[QUIN_MI2S].channels;
  3656. break;
  3657. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3658. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3659. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3660. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3661. channels->min = channels->max =
  3662. mi2s_tx_cfg[QUIN_MI2S].channels;
  3663. break;
  3664. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3665. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3666. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3667. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3668. channels->min = channels->max =
  3669. mi2s_rx_cfg[SEN_MI2S].channels;
  3670. break;
  3671. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3672. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3673. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3674. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3675. channels->min = channels->max =
  3676. mi2s_tx_cfg[SEN_MI2S].channels;
  3677. break;
  3678. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3679. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3680. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3681. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3682. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3683. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3684. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3685. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3686. cdc_dma_rx_cfg[idx].bit_format);
  3687. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3688. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3689. break;
  3690. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3691. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3692. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3693. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3694. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3695. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3696. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3697. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3698. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3699. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3700. cdc_dma_tx_cfg[idx].bit_format);
  3701. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3702. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3703. break;
  3704. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3705. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3706. SNDRV_PCM_FORMAT_S32_LE);
  3707. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3708. channels->min = channels->max = msm_vi_feed_tx_ch;
  3709. break;
  3710. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3711. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3712. slim_rx_cfg[SLIM_RX_7].bit_format);
  3713. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3714. channels->min = channels->max =
  3715. slim_rx_cfg[SLIM_RX_7].channels;
  3716. break;
  3717. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3718. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3719. channels->min = channels->max =
  3720. slim_tx_cfg[SLIM_TX_7].channels;
  3721. break;
  3722. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3723. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3724. channels->min = channels->max =
  3725. slim_tx_cfg[SLIM_TX_8].channels;
  3726. break;
  3727. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3728. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3729. afe_loopback_tx_cfg[idx].bit_format);
  3730. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3731. channels->min = channels->max =
  3732. afe_loopback_tx_cfg[idx].channels;
  3733. break;
  3734. default:
  3735. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3736. break;
  3737. }
  3738. done:
  3739. return rc;
  3740. }
  3741. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3742. {
  3743. struct snd_soc_card *card = component->card;
  3744. struct msm_asoc_mach_data *pdata =
  3745. snd_soc_card_get_drvdata(card);
  3746. if (!pdata->fsa_handle)
  3747. return false;
  3748. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3749. }
  3750. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3751. {
  3752. int value = 0;
  3753. bool ret = false;
  3754. struct snd_soc_card *card;
  3755. struct msm_asoc_mach_data *pdata;
  3756. if (!component) {
  3757. pr_err("%s component is NULL\n", __func__);
  3758. return false;
  3759. }
  3760. card = component->card;
  3761. pdata = snd_soc_card_get_drvdata(card);
  3762. if (!pdata)
  3763. return false;
  3764. if (wcd_mbhc_cfg.enable_usbc_analog)
  3765. return msm_usbc_swap_gnd_mic(component, active);
  3766. /* if usbc is not defined, swap using us_euro_gpio_p */
  3767. if (pdata->us_euro_gpio_p) {
  3768. value = msm_cdc_pinctrl_get_state(
  3769. pdata->us_euro_gpio_p);
  3770. if (value)
  3771. msm_cdc_pinctrl_select_sleep_state(
  3772. pdata->us_euro_gpio_p);
  3773. else
  3774. msm_cdc_pinctrl_select_active_state(
  3775. pdata->us_euro_gpio_p);
  3776. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3777. __func__, value, !value);
  3778. ret = true;
  3779. }
  3780. return ret;
  3781. }
  3782. static int kona_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3783. struct snd_pcm_hw_params *params)
  3784. {
  3785. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3786. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3787. int ret = 0;
  3788. int slot_width = 32;
  3789. int channels, slots;
  3790. unsigned int slot_mask, rate, clk_freq;
  3791. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  3792. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3793. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  3794. switch (cpu_dai->id) {
  3795. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3796. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3797. break;
  3798. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3799. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3800. break;
  3801. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3802. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3803. break;
  3804. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3805. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3806. break;
  3807. case AFE_PORT_ID_QUINARY_TDM_RX:
  3808. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3809. break;
  3810. case AFE_PORT_ID_SENARY_TDM_RX:
  3811. slots = tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3812. break;
  3813. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3814. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3815. break;
  3816. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3817. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3818. break;
  3819. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3820. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3821. break;
  3822. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3823. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3824. break;
  3825. case AFE_PORT_ID_QUINARY_TDM_TX:
  3826. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3827. break;
  3828. case AFE_PORT_ID_SENARY_TDM_TX:
  3829. slots = tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3830. break;
  3831. default:
  3832. pr_err("%s: dai id 0x%x not supported\n",
  3833. __func__, cpu_dai->id);
  3834. return -EINVAL;
  3835. }
  3836. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3837. /*2 slot config - bits 0 and 1 set for the first two slots */
  3838. slot_mask = 0x0000FFFF >> (16 - slots);
  3839. channels = slots;
  3840. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  3841. __func__, slot_width, slots);
  3842. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3843. slots, slot_width);
  3844. if (ret < 0) {
  3845. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3846. __func__, ret);
  3847. goto end;
  3848. }
  3849. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3850. 0, NULL, channels, slot_offset);
  3851. if (ret < 0) {
  3852. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3853. __func__, ret);
  3854. goto end;
  3855. }
  3856. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3857. /*2 slot config - bits 0 and 1 set for the first two slots */
  3858. slot_mask = 0x0000FFFF >> (16 - slots);
  3859. channels = slots;
  3860. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  3861. __func__, slot_width, slots);
  3862. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3863. slots, slot_width);
  3864. if (ret < 0) {
  3865. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3866. __func__, ret);
  3867. goto end;
  3868. }
  3869. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3870. channels, slot_offset, 0, NULL);
  3871. if (ret < 0) {
  3872. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3873. __func__, ret);
  3874. goto end;
  3875. }
  3876. } else {
  3877. ret = -EINVAL;
  3878. pr_err("%s: invalid use case, err:%d\n",
  3879. __func__, ret);
  3880. goto end;
  3881. }
  3882. rate = params_rate(params);
  3883. clk_freq = rate * slot_width * slots;
  3884. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3885. if (ret < 0)
  3886. pr_err("%s: failed to set tdm clk, err:%d\n",
  3887. __func__, ret);
  3888. end:
  3889. return ret;
  3890. }
  3891. static int msm_get_tdm_mode(u32 port_id)
  3892. {
  3893. int tdm_mode;
  3894. switch (port_id) {
  3895. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3896. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3897. tdm_mode = TDM_PRI;
  3898. break;
  3899. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3900. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3901. tdm_mode = TDM_SEC;
  3902. break;
  3903. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3904. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3905. tdm_mode = TDM_TERT;
  3906. break;
  3907. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3908. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3909. tdm_mode = TDM_QUAT;
  3910. break;
  3911. case AFE_PORT_ID_QUINARY_TDM_RX:
  3912. case AFE_PORT_ID_QUINARY_TDM_TX:
  3913. tdm_mode = TDM_QUIN;
  3914. break;
  3915. case AFE_PORT_ID_SENARY_TDM_RX:
  3916. case AFE_PORT_ID_SENARY_TDM_TX:
  3917. tdm_mode = TDM_SEN;
  3918. break;
  3919. default:
  3920. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  3921. tdm_mode = -EINVAL;
  3922. }
  3923. return tdm_mode;
  3924. }
  3925. static int kona_tdm_snd_startup(struct snd_pcm_substream *substream)
  3926. {
  3927. int ret = 0;
  3928. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3929. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3930. struct snd_soc_card *card = rtd->card;
  3931. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3932. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3933. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3934. ret = -EINVAL;
  3935. pr_err("%s: Invalid TDM interface %d\n",
  3936. __func__, ret);
  3937. return ret;
  3938. }
  3939. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3940. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3941. == 0) {
  3942. ret = msm_cdc_pinctrl_select_active_state(
  3943. pdata->mi2s_gpio_p[tdm_mode]);
  3944. if (ret) {
  3945. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  3946. __func__, ret);
  3947. goto done;
  3948. }
  3949. }
  3950. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3951. }
  3952. done:
  3953. return ret;
  3954. }
  3955. static void kona_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  3956. {
  3957. int ret = 0;
  3958. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3959. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3960. struct snd_soc_card *card = rtd->card;
  3961. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3962. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3963. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3964. ret = -EINVAL;
  3965. pr_err("%s: Invalid TDM interface %d\n",
  3966. __func__, ret);
  3967. return;
  3968. }
  3969. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3970. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3971. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3972. == 0) {
  3973. ret = msm_cdc_pinctrl_select_sleep_state(
  3974. pdata->mi2s_gpio_p[tdm_mode]);
  3975. if (ret)
  3976. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  3977. __func__, ret);
  3978. }
  3979. }
  3980. }
  3981. static int kona_aux_snd_startup(struct snd_pcm_substream *substream)
  3982. {
  3983. int ret = 0;
  3984. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3985. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3986. struct snd_soc_card *card = rtd->card;
  3987. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3988. u32 aux_mode = cpu_dai->id - 1;
  3989. if (aux_mode >= AUX_PCM_MAX) {
  3990. ret = -EINVAL;
  3991. pr_err("%s: Invalid AUX interface %d\n",
  3992. __func__, ret);
  3993. return ret;
  3994. }
  3995. if (pdata->mi2s_gpio_p[aux_mode]) {
  3996. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3997. == 0) {
  3998. ret = msm_cdc_pinctrl_select_active_state(
  3999. pdata->mi2s_gpio_p[aux_mode]);
  4000. if (ret) {
  4001. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  4002. __func__, ret);
  4003. goto done;
  4004. }
  4005. }
  4006. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4007. }
  4008. done:
  4009. return ret;
  4010. }
  4011. static void kona_aux_snd_shutdown(struct snd_pcm_substream *substream)
  4012. {
  4013. int ret = 0;
  4014. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4015. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4016. struct snd_soc_card *card = rtd->card;
  4017. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4018. u32 aux_mode = cpu_dai->id - 1;
  4019. if (aux_mode >= AUX_PCM_MAX) {
  4020. pr_err("%s: Invalid AUX interface %d\n",
  4021. __func__, ret);
  4022. return;
  4023. }
  4024. if (pdata->mi2s_gpio_p[aux_mode]) {
  4025. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4026. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4027. == 0) {
  4028. ret = msm_cdc_pinctrl_select_sleep_state(
  4029. pdata->mi2s_gpio_p[aux_mode]);
  4030. if (ret)
  4031. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  4032. __func__, ret);
  4033. }
  4034. }
  4035. }
  4036. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4037. {
  4038. int ret = 0;
  4039. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4040. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4041. switch (dai_link->id) {
  4042. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4043. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4044. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4045. ret = kona_send_island_va_config(dai_link->id);
  4046. if (ret)
  4047. pr_err("%s: send island va cfg failed, err: %d\n",
  4048. __func__, ret);
  4049. break;
  4050. }
  4051. return ret;
  4052. }
  4053. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4054. struct snd_pcm_hw_params *params)
  4055. {
  4056. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4057. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4058. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4059. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4060. int ret = 0;
  4061. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4062. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4063. u32 user_set_tx_ch = 0;
  4064. u32 user_set_rx_ch = 0;
  4065. u32 ch_id;
  4066. ret = snd_soc_dai_get_channel_map(codec_dai,
  4067. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4068. &rx_ch_cdc_dma);
  4069. if (ret < 0) {
  4070. pr_err("%s: failed to get codec chan map, err:%d\n",
  4071. __func__, ret);
  4072. goto err;
  4073. }
  4074. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4075. switch (dai_link->id) {
  4076. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4077. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4078. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  4079. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  4080. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  4081. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  4082. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  4083. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  4084. {
  4085. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4086. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4087. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4088. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4089. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4090. user_set_rx_ch, &rx_ch_cdc_dma);
  4091. if (ret < 0) {
  4092. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4093. __func__, ret);
  4094. goto err;
  4095. }
  4096. }
  4097. break;
  4098. }
  4099. } else {
  4100. switch (dai_link->id) {
  4101. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4102. {
  4103. user_set_tx_ch = msm_vi_feed_tx_ch;
  4104. }
  4105. break;
  4106. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4107. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4108. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  4109. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  4110. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  4111. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4112. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4113. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4114. {
  4115. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4116. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4117. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4118. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4119. }
  4120. break;
  4121. }
  4122. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4123. &tx_ch_cdc_dma, 0, 0);
  4124. if (ret < 0) {
  4125. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4126. __func__, ret);
  4127. goto err;
  4128. }
  4129. }
  4130. err:
  4131. return ret;
  4132. }
  4133. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4134. {
  4135. cpumask_t mask;
  4136. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4137. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4138. cpumask_clear(&mask);
  4139. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4140. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4141. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4142. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4143. pm_qos_add_request(&substream->latency_pm_qos_req,
  4144. PM_QOS_CPU_DMA_LATENCY,
  4145. MSM_LL_QOS_VALUE);
  4146. return 0;
  4147. }
  4148. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4149. {
  4150. int ret = 0;
  4151. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4152. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4153. int index = cpu_dai->id;
  4154. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4155. struct snd_soc_card *card = rtd->card;
  4156. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4157. dev_dbg(rtd->card->dev,
  4158. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4159. __func__, substream->name, substream->stream,
  4160. cpu_dai->name, cpu_dai->id);
  4161. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4162. ret = -EINVAL;
  4163. dev_err(rtd->card->dev,
  4164. "%s: CPU DAI id (%d) out of range\n",
  4165. __func__, cpu_dai->id);
  4166. goto err;
  4167. }
  4168. /*
  4169. * Mutex protection in case the same MI2S
  4170. * interface using for both TX and RX so
  4171. * that the same clock won't be enable twice.
  4172. */
  4173. mutex_lock(&mi2s_intf_conf[index].lock);
  4174. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4175. /* Check if msm needs to provide the clock to the interface */
  4176. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4177. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4178. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4179. }
  4180. ret = msm_mi2s_set_sclk(substream, true);
  4181. if (ret < 0) {
  4182. dev_err(rtd->card->dev,
  4183. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4184. __func__, ret);
  4185. goto clean_up;
  4186. }
  4187. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4188. if (ret < 0) {
  4189. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4190. __func__, index, ret);
  4191. goto clk_off;
  4192. }
  4193. if (pdata->mi2s_gpio_p[index]) {
  4194. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4195. == 0) {
  4196. ret = msm_cdc_pinctrl_select_active_state(
  4197. pdata->mi2s_gpio_p[index]);
  4198. if (ret) {
  4199. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  4200. __func__, ret);
  4201. goto clk_off;
  4202. }
  4203. }
  4204. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  4205. }
  4206. }
  4207. clk_off:
  4208. if (ret < 0)
  4209. msm_mi2s_set_sclk(substream, false);
  4210. clean_up:
  4211. if (ret < 0)
  4212. mi2s_intf_conf[index].ref_cnt--;
  4213. mutex_unlock(&mi2s_intf_conf[index].lock);
  4214. err:
  4215. return ret;
  4216. }
  4217. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4218. {
  4219. int ret = 0;
  4220. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4221. int index = rtd->cpu_dai->id;
  4222. struct snd_soc_card *card = rtd->card;
  4223. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4224. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4225. substream->name, substream->stream);
  4226. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4227. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4228. return;
  4229. }
  4230. mutex_lock(&mi2s_intf_conf[index].lock);
  4231. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4232. if (pdata->mi2s_gpio_p[index]) {
  4233. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  4234. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4235. == 0) {
  4236. ret = msm_cdc_pinctrl_select_sleep_state(
  4237. pdata->mi2s_gpio_p[index]);
  4238. if (ret)
  4239. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  4240. __func__, ret);
  4241. }
  4242. }
  4243. ret = msm_mi2s_set_sclk(substream, false);
  4244. if (ret < 0)
  4245. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4246. __func__, index, ret);
  4247. }
  4248. mutex_unlock(&mi2s_intf_conf[index].lock);
  4249. }
  4250. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  4251. struct snd_pcm_hw_params *params)
  4252. {
  4253. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4254. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4255. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4256. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4257. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4258. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4259. int ret = 0;
  4260. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4261. codec_dai->name, codec_dai->id);
  4262. ret = snd_soc_dai_get_channel_map(codec_dai,
  4263. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4264. if (ret) {
  4265. dev_err(rtd->dev,
  4266. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4267. __func__, ret);
  4268. goto err;
  4269. }
  4270. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4271. __func__, tx_ch_cnt, dai_link->id);
  4272. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4273. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4274. if (ret)
  4275. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4276. __func__, ret);
  4277. err:
  4278. return ret;
  4279. }
  4280. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4281. struct snd_pcm_hw_params *params)
  4282. {
  4283. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4284. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4285. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4286. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4287. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4288. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4289. int ret = 0;
  4290. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4291. codec_dai->name, codec_dai->id);
  4292. ret = snd_soc_dai_get_channel_map(codec_dai,
  4293. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4294. if (ret) {
  4295. dev_err(rtd->dev,
  4296. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4297. __func__, ret);
  4298. goto err;
  4299. }
  4300. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4301. __func__, tx_ch_cnt, dai_link->id);
  4302. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4303. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4304. if (ret)
  4305. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4306. __func__, ret);
  4307. err:
  4308. return ret;
  4309. }
  4310. static struct snd_soc_ops kona_aux_be_ops = {
  4311. .startup = kona_aux_snd_startup,
  4312. .shutdown = kona_aux_snd_shutdown
  4313. };
  4314. static struct snd_soc_ops kona_tdm_be_ops = {
  4315. .hw_params = kona_tdm_snd_hw_params,
  4316. .startup = kona_tdm_snd_startup,
  4317. .shutdown = kona_tdm_snd_shutdown
  4318. };
  4319. static struct snd_soc_ops msm_mi2s_be_ops = {
  4320. .startup = msm_mi2s_snd_startup,
  4321. .shutdown = msm_mi2s_snd_shutdown,
  4322. };
  4323. static struct snd_soc_ops msm_fe_qos_ops = {
  4324. .prepare = msm_fe_qos_prepare,
  4325. };
  4326. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4327. .startup = msm_snd_cdc_dma_startup,
  4328. .hw_params = msm_snd_cdc_dma_hw_params,
  4329. };
  4330. static struct snd_soc_ops msm_wcn_ops = {
  4331. .hw_params = msm_wcn_hw_params,
  4332. };
  4333. static struct snd_soc_ops msm_wcn_ops_lito = {
  4334. .hw_params = msm_wcn_hw_params_lito,
  4335. };
  4336. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4337. struct snd_kcontrol *kcontrol, int event)
  4338. {
  4339. struct msm_asoc_mach_data *pdata = NULL;
  4340. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  4341. int ret = 0;
  4342. u32 dmic_idx;
  4343. int *dmic_gpio_cnt;
  4344. struct device_node *dmic_gpio;
  4345. char *wname;
  4346. wname = strpbrk(w->name, "012345");
  4347. if (!wname) {
  4348. dev_err(component->dev, "%s: widget not found\n", __func__);
  4349. return -EINVAL;
  4350. }
  4351. ret = kstrtouint(wname, 10, &dmic_idx);
  4352. if (ret < 0) {
  4353. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4354. __func__);
  4355. return -EINVAL;
  4356. }
  4357. pdata = snd_soc_card_get_drvdata(component->card);
  4358. switch (dmic_idx) {
  4359. case 0:
  4360. case 1:
  4361. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4362. dmic_gpio = pdata->dmic01_gpio_p;
  4363. break;
  4364. case 2:
  4365. case 3:
  4366. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4367. dmic_gpio = pdata->dmic23_gpio_p;
  4368. break;
  4369. case 4:
  4370. case 5:
  4371. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4372. dmic_gpio = pdata->dmic45_gpio_p;
  4373. break;
  4374. default:
  4375. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4376. __func__);
  4377. return -EINVAL;
  4378. }
  4379. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4380. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4381. switch (event) {
  4382. case SND_SOC_DAPM_PRE_PMU:
  4383. (*dmic_gpio_cnt)++;
  4384. if (*dmic_gpio_cnt == 1) {
  4385. ret = msm_cdc_pinctrl_select_active_state(
  4386. dmic_gpio);
  4387. if (ret < 0) {
  4388. pr_err("%s: gpio set cannot be activated %sd",
  4389. __func__, "dmic_gpio");
  4390. return ret;
  4391. }
  4392. }
  4393. break;
  4394. case SND_SOC_DAPM_POST_PMD:
  4395. (*dmic_gpio_cnt)--;
  4396. if (*dmic_gpio_cnt == 0) {
  4397. ret = msm_cdc_pinctrl_select_sleep_state(
  4398. dmic_gpio);
  4399. if (ret < 0) {
  4400. pr_err("%s: gpio set cannot be de-activated %sd",
  4401. __func__, "dmic_gpio");
  4402. return ret;
  4403. }
  4404. }
  4405. break;
  4406. default:
  4407. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4408. return -EINVAL;
  4409. }
  4410. return 0;
  4411. }
  4412. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4413. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4414. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4415. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4416. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4417. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4418. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4419. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4420. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4421. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4422. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4423. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4424. SND_SOC_DAPM_MIC("Digital Mic6", NULL),
  4425. SND_SOC_DAPM_MIC("Digital Mic7", NULL),
  4426. };
  4427. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4428. {
  4429. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4430. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160};
  4431. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4432. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4433. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4434. }
  4435. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4436. {
  4437. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4438. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4439. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4440. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4441. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4442. }
  4443. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4444. {
  4445. int ret = -EINVAL;
  4446. struct snd_soc_component *component;
  4447. struct snd_soc_dapm_context *dapm;
  4448. struct snd_card *card;
  4449. struct snd_info_entry *entry;
  4450. struct snd_soc_component *aux_comp;
  4451. struct msm_asoc_mach_data *pdata =
  4452. snd_soc_card_get_drvdata(rtd->card);
  4453. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4454. if (!component) {
  4455. pr_err("%s: could not find component for bolero_codec\n",
  4456. __func__);
  4457. return ret;
  4458. }
  4459. dapm = snd_soc_component_get_dapm(component);
  4460. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  4461. ARRAY_SIZE(msm_int_snd_controls));
  4462. if (ret < 0) {
  4463. pr_err("%s: add_component_controls failed: %d\n",
  4464. __func__, ret);
  4465. return ret;
  4466. }
  4467. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  4468. ARRAY_SIZE(msm_common_snd_controls));
  4469. if (ret < 0) {
  4470. pr_err("%s: add common snd controls failed: %d\n",
  4471. __func__, ret);
  4472. return ret;
  4473. }
  4474. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  4475. ARRAY_SIZE(msm_int_dapm_widgets));
  4476. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4477. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4478. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4479. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4480. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4481. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4482. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4483. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4484. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  4485. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  4486. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4487. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4488. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  4489. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4490. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4491. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4492. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4493. snd_soc_dapm_sync(dapm);
  4494. /*
  4495. * Send speaker configuration only for WSA8810.
  4496. * Default configuration is for WSA8815.
  4497. */
  4498. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4499. __func__, rtd->card->num_aux_devs);
  4500. if (rtd->card->num_aux_devs &&
  4501. !list_empty(&rtd->card->component_dev_list)) {
  4502. list_for_each_entry(aux_comp,
  4503. &rtd->card->aux_comp_list,
  4504. card_aux_list) {
  4505. if (aux_comp->name != NULL && (
  4506. !strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4507. !strcmp(aux_comp->name, WSA8810_NAME_2))) {
  4508. wsa_macro_set_spkr_mode(component,
  4509. WSA_MACRO_SPKR_MODE_1);
  4510. wsa_macro_set_spkr_gain_offset(component,
  4511. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4512. }
  4513. }
  4514. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  4515. sm_port_map);
  4516. }
  4517. card = rtd->card->snd_card;
  4518. if (!pdata->codec_root) {
  4519. entry = snd_info_create_subdir(card->module, "codecs",
  4520. card->proc_root);
  4521. if (!entry) {
  4522. pr_debug("%s: Cannot create codecs module entry\n",
  4523. __func__);
  4524. ret = 0;
  4525. goto err;
  4526. }
  4527. pdata->codec_root = entry;
  4528. }
  4529. bolero_info_create_codec_entry(pdata->codec_root, component);
  4530. bolero_register_wake_irq(component, false);
  4531. codec_reg_done = true;
  4532. return 0;
  4533. err:
  4534. return ret;
  4535. }
  4536. static void *def_wcd_mbhc_cal(void)
  4537. {
  4538. void *wcd_mbhc_cal;
  4539. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4540. u16 *btn_high;
  4541. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4542. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4543. if (!wcd_mbhc_cal)
  4544. return NULL;
  4545. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4546. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4547. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4548. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4549. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4550. btn_high[0] = 75;
  4551. btn_high[1] = 150;
  4552. btn_high[2] = 237;
  4553. btn_high[3] = 500;
  4554. btn_high[4] = 500;
  4555. btn_high[5] = 500;
  4556. btn_high[6] = 500;
  4557. btn_high[7] = 500;
  4558. return wcd_mbhc_cal;
  4559. }
  4560. /* Digital audio interface glue - connects codec <---> CPU */
  4561. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4562. /* FrontEnd DAI Links */
  4563. {/* hw:x,0 */
  4564. .name = MSM_DAILINK_NAME(Media1),
  4565. .stream_name = "MultiMedia1",
  4566. .cpu_dai_name = "MultiMedia1",
  4567. .platform_name = "msm-pcm-dsp.0",
  4568. .dynamic = 1,
  4569. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4570. .dpcm_playback = 1,
  4571. .dpcm_capture = 1,
  4572. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4573. SND_SOC_DPCM_TRIGGER_POST},
  4574. .codec_dai_name = "snd-soc-dummy-dai",
  4575. .codec_name = "snd-soc-dummy",
  4576. .ignore_suspend = 1,
  4577. /* this dainlink has playback support */
  4578. .ignore_pmdown_time = 1,
  4579. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4580. },
  4581. {/* hw:x,1 */
  4582. .name = MSM_DAILINK_NAME(Media2),
  4583. .stream_name = "MultiMedia2",
  4584. .cpu_dai_name = "MultiMedia2",
  4585. .platform_name = "msm-pcm-dsp.0",
  4586. .dynamic = 1,
  4587. .dpcm_playback = 1,
  4588. .dpcm_capture = 1,
  4589. .codec_dai_name = "snd-soc-dummy-dai",
  4590. .codec_name = "snd-soc-dummy",
  4591. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4592. SND_SOC_DPCM_TRIGGER_POST},
  4593. .ignore_suspend = 1,
  4594. /* this dainlink has playback support */
  4595. .ignore_pmdown_time = 1,
  4596. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4597. },
  4598. {/* hw:x,2 */
  4599. .name = "VoiceMMode1",
  4600. .stream_name = "VoiceMMode1",
  4601. .cpu_dai_name = "VoiceMMode1",
  4602. .platform_name = "msm-pcm-voice",
  4603. .dynamic = 1,
  4604. .dpcm_playback = 1,
  4605. .dpcm_capture = 1,
  4606. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4607. SND_SOC_DPCM_TRIGGER_POST},
  4608. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4609. .ignore_suspend = 1,
  4610. .ignore_pmdown_time = 1,
  4611. .codec_dai_name = "snd-soc-dummy-dai",
  4612. .codec_name = "snd-soc-dummy",
  4613. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4614. },
  4615. {/* hw:x,3 */
  4616. .name = "MSM VoIP",
  4617. .stream_name = "VoIP",
  4618. .cpu_dai_name = "VoIP",
  4619. .platform_name = "msm-voip-dsp",
  4620. .dynamic = 1,
  4621. .dpcm_playback = 1,
  4622. .dpcm_capture = 1,
  4623. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4624. SND_SOC_DPCM_TRIGGER_POST},
  4625. .codec_dai_name = "snd-soc-dummy-dai",
  4626. .codec_name = "snd-soc-dummy",
  4627. .ignore_suspend = 1,
  4628. /* this dainlink has playback support */
  4629. .ignore_pmdown_time = 1,
  4630. .id = MSM_FRONTEND_DAI_VOIP,
  4631. },
  4632. {/* hw:x,4 */
  4633. .name = MSM_DAILINK_NAME(ULL),
  4634. .stream_name = "MultiMedia3",
  4635. .cpu_dai_name = "MultiMedia3",
  4636. .platform_name = "msm-pcm-dsp.2",
  4637. .dynamic = 1,
  4638. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4639. .dpcm_playback = 1,
  4640. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4641. SND_SOC_DPCM_TRIGGER_POST},
  4642. .codec_dai_name = "snd-soc-dummy-dai",
  4643. .codec_name = "snd-soc-dummy",
  4644. .ignore_suspend = 1,
  4645. /* this dainlink has playback support */
  4646. .ignore_pmdown_time = 1,
  4647. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4648. },
  4649. {/* hw:x,5 */
  4650. .name = "MSM AFE-PCM RX",
  4651. .stream_name = "AFE-PROXY RX",
  4652. .cpu_dai_name = "msm-dai-q6-dev.241",
  4653. .codec_name = "msm-stub-codec.1",
  4654. .codec_dai_name = "msm-stub-rx",
  4655. .platform_name = "msm-pcm-afe",
  4656. .dpcm_playback = 1,
  4657. .ignore_suspend = 1,
  4658. /* this dainlink has playback support */
  4659. .ignore_pmdown_time = 1,
  4660. },
  4661. {/* hw:x,6 */
  4662. .name = "MSM AFE-PCM TX",
  4663. .stream_name = "AFE-PROXY TX",
  4664. .cpu_dai_name = "msm-dai-q6-dev.240",
  4665. .codec_name = "msm-stub-codec.1",
  4666. .codec_dai_name = "msm-stub-tx",
  4667. .platform_name = "msm-pcm-afe",
  4668. .dpcm_capture = 1,
  4669. .ignore_suspend = 1,
  4670. },
  4671. {/* hw:x,7 */
  4672. .name = MSM_DAILINK_NAME(Compress1),
  4673. .stream_name = "Compress1",
  4674. .cpu_dai_name = "MultiMedia4",
  4675. .platform_name = "msm-compress-dsp",
  4676. .dynamic = 1,
  4677. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4678. .dpcm_playback = 1,
  4679. .dpcm_capture = 1,
  4680. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4681. SND_SOC_DPCM_TRIGGER_POST},
  4682. .codec_dai_name = "snd-soc-dummy-dai",
  4683. .codec_name = "snd-soc-dummy",
  4684. .ignore_suspend = 1,
  4685. .ignore_pmdown_time = 1,
  4686. /* this dainlink has playback support */
  4687. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4688. },
  4689. /* Hostless PCM purpose */
  4690. {/* hw:x,8 */
  4691. .name = "AUXPCM Hostless",
  4692. .stream_name = "AUXPCM Hostless",
  4693. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4694. .platform_name = "msm-pcm-hostless",
  4695. .dynamic = 1,
  4696. .dpcm_playback = 1,
  4697. .dpcm_capture = 1,
  4698. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4699. SND_SOC_DPCM_TRIGGER_POST},
  4700. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4701. .ignore_suspend = 1,
  4702. /* this dainlink has playback support */
  4703. .ignore_pmdown_time = 1,
  4704. .codec_dai_name = "snd-soc-dummy-dai",
  4705. .codec_name = "snd-soc-dummy",
  4706. },
  4707. {/* hw:x,9 */
  4708. .name = MSM_DAILINK_NAME(LowLatency),
  4709. .stream_name = "MultiMedia5",
  4710. .cpu_dai_name = "MultiMedia5",
  4711. .platform_name = "msm-pcm-dsp.1",
  4712. .dynamic = 1,
  4713. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4714. .dpcm_playback = 1,
  4715. .dpcm_capture = 1,
  4716. .codec_dai_name = "snd-soc-dummy-dai",
  4717. .codec_name = "snd-soc-dummy",
  4718. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4719. SND_SOC_DPCM_TRIGGER_POST},
  4720. .ignore_suspend = 1,
  4721. /* this dainlink has playback support */
  4722. .ignore_pmdown_time = 1,
  4723. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4724. .ops = &msm_fe_qos_ops,
  4725. },
  4726. {/* hw:x,10 */
  4727. .name = "Listen 1 Audio Service",
  4728. .stream_name = "Listen 1 Audio Service",
  4729. .cpu_dai_name = "LSM1",
  4730. .platform_name = "msm-lsm-client",
  4731. .dynamic = 1,
  4732. .dpcm_capture = 1,
  4733. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4734. SND_SOC_DPCM_TRIGGER_POST },
  4735. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4736. .ignore_suspend = 1,
  4737. .codec_dai_name = "snd-soc-dummy-dai",
  4738. .codec_name = "snd-soc-dummy",
  4739. .id = MSM_FRONTEND_DAI_LSM1,
  4740. },
  4741. /* Multiple Tunnel instances */
  4742. {/* hw:x,11 */
  4743. .name = MSM_DAILINK_NAME(Compress2),
  4744. .stream_name = "Compress2",
  4745. .cpu_dai_name = "MultiMedia7",
  4746. .platform_name = "msm-compress-dsp",
  4747. .dynamic = 1,
  4748. .dpcm_playback = 1,
  4749. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4750. SND_SOC_DPCM_TRIGGER_POST},
  4751. .codec_dai_name = "snd-soc-dummy-dai",
  4752. .codec_name = "snd-soc-dummy",
  4753. .ignore_suspend = 1,
  4754. .ignore_pmdown_time = 1,
  4755. /* this dainlink has playback support */
  4756. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4757. },
  4758. {/* hw:x,12 */
  4759. .name = MSM_DAILINK_NAME(MultiMedia10),
  4760. .stream_name = "MultiMedia10",
  4761. .cpu_dai_name = "MultiMedia10",
  4762. .platform_name = "msm-pcm-dsp.1",
  4763. .dynamic = 1,
  4764. .dpcm_playback = 1,
  4765. .dpcm_capture = 1,
  4766. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4767. SND_SOC_DPCM_TRIGGER_POST},
  4768. .codec_dai_name = "snd-soc-dummy-dai",
  4769. .codec_name = "snd-soc-dummy",
  4770. .ignore_suspend = 1,
  4771. .ignore_pmdown_time = 1,
  4772. /* this dainlink has playback support */
  4773. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4774. },
  4775. {/* hw:x,13 */
  4776. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4777. .stream_name = "MM_NOIRQ",
  4778. .cpu_dai_name = "MultiMedia8",
  4779. .platform_name = "msm-pcm-dsp-noirq",
  4780. .dynamic = 1,
  4781. .dpcm_playback = 1,
  4782. .dpcm_capture = 1,
  4783. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4784. SND_SOC_DPCM_TRIGGER_POST},
  4785. .codec_dai_name = "snd-soc-dummy-dai",
  4786. .codec_name = "snd-soc-dummy",
  4787. .ignore_suspend = 1,
  4788. .ignore_pmdown_time = 1,
  4789. /* this dainlink has playback support */
  4790. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4791. .ops = &msm_fe_qos_ops,
  4792. },
  4793. /* HDMI Hostless */
  4794. {/* hw:x,14 */
  4795. .name = "HDMI_RX_HOSTLESS",
  4796. .stream_name = "HDMI_RX_HOSTLESS",
  4797. .cpu_dai_name = "HDMI_HOSTLESS",
  4798. .platform_name = "msm-pcm-hostless",
  4799. .dynamic = 1,
  4800. .dpcm_playback = 1,
  4801. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4802. SND_SOC_DPCM_TRIGGER_POST},
  4803. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4804. .ignore_suspend = 1,
  4805. .ignore_pmdown_time = 1,
  4806. .codec_dai_name = "snd-soc-dummy-dai",
  4807. .codec_name = "snd-soc-dummy",
  4808. },
  4809. {/* hw:x,15 */
  4810. .name = "VoiceMMode2",
  4811. .stream_name = "VoiceMMode2",
  4812. .cpu_dai_name = "VoiceMMode2",
  4813. .platform_name = "msm-pcm-voice",
  4814. .dynamic = 1,
  4815. .dpcm_playback = 1,
  4816. .dpcm_capture = 1,
  4817. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4818. SND_SOC_DPCM_TRIGGER_POST},
  4819. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4820. .ignore_suspend = 1,
  4821. .ignore_pmdown_time = 1,
  4822. .codec_dai_name = "snd-soc-dummy-dai",
  4823. .codec_name = "snd-soc-dummy",
  4824. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4825. },
  4826. /* LSM FE */
  4827. {/* hw:x,16 */
  4828. .name = "Listen 2 Audio Service",
  4829. .stream_name = "Listen 2 Audio Service",
  4830. .cpu_dai_name = "LSM2",
  4831. .platform_name = "msm-lsm-client",
  4832. .dynamic = 1,
  4833. .dpcm_capture = 1,
  4834. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4835. SND_SOC_DPCM_TRIGGER_POST },
  4836. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4837. .ignore_suspend = 1,
  4838. .codec_dai_name = "snd-soc-dummy-dai",
  4839. .codec_name = "snd-soc-dummy",
  4840. .id = MSM_FRONTEND_DAI_LSM2,
  4841. },
  4842. {/* hw:x,17 */
  4843. .name = "Listen 3 Audio Service",
  4844. .stream_name = "Listen 3 Audio Service",
  4845. .cpu_dai_name = "LSM3",
  4846. .platform_name = "msm-lsm-client",
  4847. .dynamic = 1,
  4848. .dpcm_capture = 1,
  4849. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4850. SND_SOC_DPCM_TRIGGER_POST },
  4851. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4852. .ignore_suspend = 1,
  4853. .codec_dai_name = "snd-soc-dummy-dai",
  4854. .codec_name = "snd-soc-dummy",
  4855. .id = MSM_FRONTEND_DAI_LSM3,
  4856. },
  4857. {/* hw:x,18 */
  4858. .name = "Listen 4 Audio Service",
  4859. .stream_name = "Listen 4 Audio Service",
  4860. .cpu_dai_name = "LSM4",
  4861. .platform_name = "msm-lsm-client",
  4862. .dynamic = 1,
  4863. .dpcm_capture = 1,
  4864. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4865. SND_SOC_DPCM_TRIGGER_POST },
  4866. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4867. .ignore_suspend = 1,
  4868. .codec_dai_name = "snd-soc-dummy-dai",
  4869. .codec_name = "snd-soc-dummy",
  4870. .id = MSM_FRONTEND_DAI_LSM4,
  4871. },
  4872. {/* hw:x,19 */
  4873. .name = "Listen 5 Audio Service",
  4874. .stream_name = "Listen 5 Audio Service",
  4875. .cpu_dai_name = "LSM5",
  4876. .platform_name = "msm-lsm-client",
  4877. .dynamic = 1,
  4878. .dpcm_capture = 1,
  4879. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4880. SND_SOC_DPCM_TRIGGER_POST },
  4881. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4882. .ignore_suspend = 1,
  4883. .codec_dai_name = "snd-soc-dummy-dai",
  4884. .codec_name = "snd-soc-dummy",
  4885. .id = MSM_FRONTEND_DAI_LSM5,
  4886. },
  4887. {/* hw:x,20 */
  4888. .name = "Listen 6 Audio Service",
  4889. .stream_name = "Listen 6 Audio Service",
  4890. .cpu_dai_name = "LSM6",
  4891. .platform_name = "msm-lsm-client",
  4892. .dynamic = 1,
  4893. .dpcm_capture = 1,
  4894. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4895. SND_SOC_DPCM_TRIGGER_POST },
  4896. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4897. .ignore_suspend = 1,
  4898. .codec_dai_name = "snd-soc-dummy-dai",
  4899. .codec_name = "snd-soc-dummy",
  4900. .id = MSM_FRONTEND_DAI_LSM6,
  4901. },
  4902. {/* hw:x,21 */
  4903. .name = "Listen 7 Audio Service",
  4904. .stream_name = "Listen 7 Audio Service",
  4905. .cpu_dai_name = "LSM7",
  4906. .platform_name = "msm-lsm-client",
  4907. .dynamic = 1,
  4908. .dpcm_capture = 1,
  4909. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4910. SND_SOC_DPCM_TRIGGER_POST },
  4911. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4912. .ignore_suspend = 1,
  4913. .codec_dai_name = "snd-soc-dummy-dai",
  4914. .codec_name = "snd-soc-dummy",
  4915. .id = MSM_FRONTEND_DAI_LSM7,
  4916. },
  4917. {/* hw:x,22 */
  4918. .name = "Listen 8 Audio Service",
  4919. .stream_name = "Listen 8 Audio Service",
  4920. .cpu_dai_name = "LSM8",
  4921. .platform_name = "msm-lsm-client",
  4922. .dynamic = 1,
  4923. .dpcm_capture = 1,
  4924. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4925. SND_SOC_DPCM_TRIGGER_POST },
  4926. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4927. .ignore_suspend = 1,
  4928. .codec_dai_name = "snd-soc-dummy-dai",
  4929. .codec_name = "snd-soc-dummy",
  4930. .id = MSM_FRONTEND_DAI_LSM8,
  4931. },
  4932. {/* hw:x,23 */
  4933. .name = MSM_DAILINK_NAME(Media9),
  4934. .stream_name = "MultiMedia9",
  4935. .cpu_dai_name = "MultiMedia9",
  4936. .platform_name = "msm-pcm-dsp.0",
  4937. .dynamic = 1,
  4938. .dpcm_playback = 1,
  4939. .dpcm_capture = 1,
  4940. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4941. SND_SOC_DPCM_TRIGGER_POST},
  4942. .codec_dai_name = "snd-soc-dummy-dai",
  4943. .codec_name = "snd-soc-dummy",
  4944. .ignore_suspend = 1,
  4945. /* this dainlink has playback support */
  4946. .ignore_pmdown_time = 1,
  4947. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4948. },
  4949. {/* hw:x,24 */
  4950. .name = MSM_DAILINK_NAME(Compress4),
  4951. .stream_name = "Compress4",
  4952. .cpu_dai_name = "MultiMedia11",
  4953. .platform_name = "msm-compress-dsp",
  4954. .dynamic = 1,
  4955. .dpcm_playback = 1,
  4956. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4957. SND_SOC_DPCM_TRIGGER_POST},
  4958. .codec_dai_name = "snd-soc-dummy-dai",
  4959. .codec_name = "snd-soc-dummy",
  4960. .ignore_suspend = 1,
  4961. .ignore_pmdown_time = 1,
  4962. /* this dainlink has playback support */
  4963. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4964. },
  4965. {/* hw:x,25 */
  4966. .name = MSM_DAILINK_NAME(Compress5),
  4967. .stream_name = "Compress5",
  4968. .cpu_dai_name = "MultiMedia12",
  4969. .platform_name = "msm-compress-dsp",
  4970. .dynamic = 1,
  4971. .dpcm_playback = 1,
  4972. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4973. SND_SOC_DPCM_TRIGGER_POST},
  4974. .codec_dai_name = "snd-soc-dummy-dai",
  4975. .codec_name = "snd-soc-dummy",
  4976. .ignore_suspend = 1,
  4977. .ignore_pmdown_time = 1,
  4978. /* this dainlink has playback support */
  4979. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4980. },
  4981. {/* hw:x,26 */
  4982. .name = MSM_DAILINK_NAME(Compress6),
  4983. .stream_name = "Compress6",
  4984. .cpu_dai_name = "MultiMedia13",
  4985. .platform_name = "msm-compress-dsp",
  4986. .dynamic = 1,
  4987. .dpcm_playback = 1,
  4988. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4989. SND_SOC_DPCM_TRIGGER_POST},
  4990. .codec_dai_name = "snd-soc-dummy-dai",
  4991. .codec_name = "snd-soc-dummy",
  4992. .ignore_suspend = 1,
  4993. .ignore_pmdown_time = 1,
  4994. /* this dainlink has playback support */
  4995. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4996. },
  4997. {/* hw:x,27 */
  4998. .name = MSM_DAILINK_NAME(Compress7),
  4999. .stream_name = "Compress7",
  5000. .cpu_dai_name = "MultiMedia14",
  5001. .platform_name = "msm-compress-dsp",
  5002. .dynamic = 1,
  5003. .dpcm_playback = 1,
  5004. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5005. SND_SOC_DPCM_TRIGGER_POST},
  5006. .codec_dai_name = "snd-soc-dummy-dai",
  5007. .codec_name = "snd-soc-dummy",
  5008. .ignore_suspend = 1,
  5009. .ignore_pmdown_time = 1,
  5010. /* this dainlink has playback support */
  5011. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  5012. },
  5013. {/* hw:x,28 */
  5014. .name = MSM_DAILINK_NAME(Compress8),
  5015. .stream_name = "Compress8",
  5016. .cpu_dai_name = "MultiMedia15",
  5017. .platform_name = "msm-compress-dsp",
  5018. .dynamic = 1,
  5019. .dpcm_playback = 1,
  5020. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5021. SND_SOC_DPCM_TRIGGER_POST},
  5022. .codec_dai_name = "snd-soc-dummy-dai",
  5023. .codec_name = "snd-soc-dummy",
  5024. .ignore_suspend = 1,
  5025. .ignore_pmdown_time = 1,
  5026. /* this dainlink has playback support */
  5027. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5028. },
  5029. {/* hw:x,29 */
  5030. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5031. .stream_name = "MM_NOIRQ_2",
  5032. .cpu_dai_name = "MultiMedia16",
  5033. .platform_name = "msm-pcm-dsp-noirq",
  5034. .dynamic = 1,
  5035. .dpcm_playback = 1,
  5036. .dpcm_capture = 1,
  5037. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5038. SND_SOC_DPCM_TRIGGER_POST},
  5039. .codec_dai_name = "snd-soc-dummy-dai",
  5040. .codec_name = "snd-soc-dummy",
  5041. .ignore_suspend = 1,
  5042. .ignore_pmdown_time = 1,
  5043. /* this dainlink has playback support */
  5044. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5045. .ops = &msm_fe_qos_ops,
  5046. },
  5047. {/* hw:x,30 */
  5048. .name = "CDC_DMA Hostless",
  5049. .stream_name = "CDC_DMA Hostless",
  5050. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5051. .platform_name = "msm-pcm-hostless",
  5052. .dynamic = 1,
  5053. .dpcm_playback = 1,
  5054. .dpcm_capture = 1,
  5055. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5056. SND_SOC_DPCM_TRIGGER_POST},
  5057. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5058. .ignore_suspend = 1,
  5059. /* this dailink has playback support */
  5060. .ignore_pmdown_time = 1,
  5061. .codec_dai_name = "snd-soc-dummy-dai",
  5062. .codec_name = "snd-soc-dummy",
  5063. },
  5064. {/* hw:x,31 */
  5065. .name = "TX3_CDC_DMA Hostless",
  5066. .stream_name = "TX3_CDC_DMA Hostless",
  5067. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  5068. .platform_name = "msm-pcm-hostless",
  5069. .dynamic = 1,
  5070. .dpcm_capture = 1,
  5071. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5072. SND_SOC_DPCM_TRIGGER_POST},
  5073. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5074. .ignore_suspend = 1,
  5075. .codec_dai_name = "snd-soc-dummy-dai",
  5076. .codec_name = "snd-soc-dummy",
  5077. },
  5078. {/* hw:x,32 */
  5079. .name = "Tertiary MI2S TX_Hostless",
  5080. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  5081. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  5082. .platform_name = "msm-pcm-hostless",
  5083. .dynamic = 1,
  5084. .dpcm_capture = 1,
  5085. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5086. SND_SOC_DPCM_TRIGGER_POST},
  5087. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5088. .ignore_suspend = 1,
  5089. .ignore_pmdown_time = 1,
  5090. .codec_dai_name = "snd-soc-dummy-dai",
  5091. .codec_name = "snd-soc-dummy",
  5092. },
  5093. };
  5094. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5095. {/* hw:x,33 */
  5096. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5097. .stream_name = "WSA CDC DMA0 Capture",
  5098. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5099. .platform_name = "msm-pcm-hostless",
  5100. .codec_name = "bolero_codec",
  5101. .codec_dai_name = "wsa_macro_vifeedback",
  5102. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5103. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5104. .ignore_suspend = 1,
  5105. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5106. .ops = &msm_cdc_dma_be_ops,
  5107. },
  5108. };
  5109. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5110. {/* hw:x,34 */
  5111. .name = MSM_DAILINK_NAME(ASM Loopback),
  5112. .stream_name = "MultiMedia6",
  5113. .cpu_dai_name = "MultiMedia6",
  5114. .platform_name = "msm-pcm-loopback",
  5115. .dynamic = 1,
  5116. .dpcm_playback = 1,
  5117. .dpcm_capture = 1,
  5118. .codec_dai_name = "snd-soc-dummy-dai",
  5119. .codec_name = "snd-soc-dummy",
  5120. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5121. SND_SOC_DPCM_TRIGGER_POST},
  5122. .ignore_suspend = 1,
  5123. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5124. .ignore_pmdown_time = 1,
  5125. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5126. },
  5127. {/* hw:x,35 */
  5128. .name = "USB Audio Hostless",
  5129. .stream_name = "USB Audio Hostless",
  5130. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5131. .platform_name = "msm-pcm-hostless",
  5132. .dynamic = 1,
  5133. .dpcm_playback = 1,
  5134. .dpcm_capture = 1,
  5135. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5136. SND_SOC_DPCM_TRIGGER_POST},
  5137. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5138. .ignore_suspend = 1,
  5139. .ignore_pmdown_time = 1,
  5140. .codec_dai_name = "snd-soc-dummy-dai",
  5141. .codec_name = "snd-soc-dummy",
  5142. },
  5143. {/* hw:x,36 */
  5144. .name = "SLIMBUS_7 Hostless",
  5145. .stream_name = "SLIMBUS_7 Hostless",
  5146. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5147. .platform_name = "msm-pcm-hostless",
  5148. .dynamic = 1,
  5149. .dpcm_capture = 1,
  5150. .dpcm_playback = 1,
  5151. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5152. SND_SOC_DPCM_TRIGGER_POST},
  5153. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5154. .ignore_suspend = 1,
  5155. .ignore_pmdown_time = 1,
  5156. .codec_dai_name = "snd-soc-dummy-dai",
  5157. .codec_name = "snd-soc-dummy",
  5158. },
  5159. {/* hw:x,37 */
  5160. .name = "Compress Capture",
  5161. .stream_name = "Compress9",
  5162. .cpu_dai_name = "MultiMedia17",
  5163. .platform_name = "msm-compress-dsp",
  5164. .dynamic = 1,
  5165. .dpcm_capture = 1,
  5166. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5167. SND_SOC_DPCM_TRIGGER_POST},
  5168. .codec_dai_name = "snd-soc-dummy-dai",
  5169. .codec_name = "snd-soc-dummy",
  5170. .ignore_suspend = 1,
  5171. .ignore_pmdown_time = 1,
  5172. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  5173. },
  5174. {/* hw:x,38 */
  5175. .name = "SLIMBUS_8 Hostless",
  5176. .stream_name = "SLIMBUS_8 Hostless",
  5177. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5178. .platform_name = "msm-pcm-hostless",
  5179. .dynamic = 1,
  5180. .dpcm_capture = 1,
  5181. .dpcm_playback = 1,
  5182. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5183. SND_SOC_DPCM_TRIGGER_POST},
  5184. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5185. .ignore_suspend = 1,
  5186. .ignore_pmdown_time = 1,
  5187. .codec_dai_name = "snd-soc-dummy-dai",
  5188. .codec_name = "snd-soc-dummy",
  5189. },
  5190. {/* hw:x,39 */
  5191. .name = LPASS_BE_TX_CDC_DMA_TX_5,
  5192. .stream_name = "TX CDC DMA5 Capture",
  5193. .cpu_dai_name = "msm-dai-cdc-dma-dev.45115",
  5194. .platform_name = "msm-pcm-hostless",
  5195. .codec_name = "bolero_codec",
  5196. .codec_dai_name = "tx_macro_tx3",
  5197. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_5,
  5198. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5199. .ignore_suspend = 1,
  5200. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5201. .ops = &msm_cdc_dma_be_ops,
  5202. },
  5203. };
  5204. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5205. /* Backend AFE DAI Links */
  5206. {
  5207. .name = LPASS_BE_AFE_PCM_RX,
  5208. .stream_name = "AFE Playback",
  5209. .cpu_dai_name = "msm-dai-q6-dev.224",
  5210. .platform_name = "msm-pcm-routing",
  5211. .codec_name = "msm-stub-codec.1",
  5212. .codec_dai_name = "msm-stub-rx",
  5213. .no_pcm = 1,
  5214. .dpcm_playback = 1,
  5215. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5216. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5217. /* this dainlink has playback support */
  5218. .ignore_pmdown_time = 1,
  5219. .ignore_suspend = 1,
  5220. },
  5221. {
  5222. .name = LPASS_BE_AFE_PCM_TX,
  5223. .stream_name = "AFE Capture",
  5224. .cpu_dai_name = "msm-dai-q6-dev.225",
  5225. .platform_name = "msm-pcm-routing",
  5226. .codec_name = "msm-stub-codec.1",
  5227. .codec_dai_name = "msm-stub-tx",
  5228. .no_pcm = 1,
  5229. .dpcm_capture = 1,
  5230. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5231. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5232. .ignore_suspend = 1,
  5233. },
  5234. /* Incall Record Uplink BACK END DAI Link */
  5235. {
  5236. .name = LPASS_BE_INCALL_RECORD_TX,
  5237. .stream_name = "Voice Uplink Capture",
  5238. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5239. .platform_name = "msm-pcm-routing",
  5240. .codec_name = "msm-stub-codec.1",
  5241. .codec_dai_name = "msm-stub-tx",
  5242. .no_pcm = 1,
  5243. .dpcm_capture = 1,
  5244. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5245. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5246. .ignore_suspend = 1,
  5247. },
  5248. /* Incall Record Downlink BACK END DAI Link */
  5249. {
  5250. .name = LPASS_BE_INCALL_RECORD_RX,
  5251. .stream_name = "Voice Downlink Capture",
  5252. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5253. .platform_name = "msm-pcm-routing",
  5254. .codec_name = "msm-stub-codec.1",
  5255. .codec_dai_name = "msm-stub-tx",
  5256. .no_pcm = 1,
  5257. .dpcm_capture = 1,
  5258. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5259. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5260. .ignore_suspend = 1,
  5261. },
  5262. /* Incall Music BACK END DAI Link */
  5263. {
  5264. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5265. .stream_name = "Voice Farend Playback",
  5266. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5267. .platform_name = "msm-pcm-routing",
  5268. .codec_name = "msm-stub-codec.1",
  5269. .codec_dai_name = "msm-stub-rx",
  5270. .no_pcm = 1,
  5271. .dpcm_playback = 1,
  5272. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5273. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5274. .ignore_suspend = 1,
  5275. .ignore_pmdown_time = 1,
  5276. },
  5277. /* Incall Music 2 BACK END DAI Link */
  5278. {
  5279. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5280. .stream_name = "Voice2 Farend Playback",
  5281. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5282. .platform_name = "msm-pcm-routing",
  5283. .codec_name = "msm-stub-codec.1",
  5284. .codec_dai_name = "msm-stub-rx",
  5285. .no_pcm = 1,
  5286. .dpcm_playback = 1,
  5287. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5288. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5289. .ignore_suspend = 1,
  5290. .ignore_pmdown_time = 1,
  5291. },
  5292. {
  5293. .name = LPASS_BE_USB_AUDIO_RX,
  5294. .stream_name = "USB Audio Playback",
  5295. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5296. .platform_name = "msm-pcm-routing",
  5297. .codec_name = "msm-stub-codec.1",
  5298. .codec_dai_name = "msm-stub-rx",
  5299. .dynamic_be = 1,
  5300. .no_pcm = 1,
  5301. .dpcm_playback = 1,
  5302. .id = MSM_BACKEND_DAI_USB_RX,
  5303. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5304. .ignore_pmdown_time = 1,
  5305. .ignore_suspend = 1,
  5306. },
  5307. {
  5308. .name = LPASS_BE_USB_AUDIO_TX,
  5309. .stream_name = "USB Audio Capture",
  5310. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5311. .platform_name = "msm-pcm-routing",
  5312. .codec_name = "msm-stub-codec.1",
  5313. .codec_dai_name = "msm-stub-tx",
  5314. .no_pcm = 1,
  5315. .dpcm_capture = 1,
  5316. .id = MSM_BACKEND_DAI_USB_TX,
  5317. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5318. .ignore_suspend = 1,
  5319. },
  5320. {
  5321. .name = LPASS_BE_PRI_TDM_RX_0,
  5322. .stream_name = "Primary TDM0 Playback",
  5323. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5324. .platform_name = "msm-pcm-routing",
  5325. .codec_name = "msm-stub-codec.1",
  5326. .codec_dai_name = "msm-stub-rx",
  5327. .no_pcm = 1,
  5328. .dpcm_playback = 1,
  5329. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5330. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5331. .ops = &kona_tdm_be_ops,
  5332. .ignore_suspend = 1,
  5333. .ignore_pmdown_time = 1,
  5334. },
  5335. {
  5336. .name = LPASS_BE_PRI_TDM_TX_0,
  5337. .stream_name = "Primary TDM0 Capture",
  5338. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5339. .platform_name = "msm-pcm-routing",
  5340. .codec_name = "msm-stub-codec.1",
  5341. .codec_dai_name = "msm-stub-tx",
  5342. .no_pcm = 1,
  5343. .dpcm_capture = 1,
  5344. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5345. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5346. .ops = &kona_tdm_be_ops,
  5347. .ignore_suspend = 1,
  5348. },
  5349. {
  5350. .name = LPASS_BE_SEC_TDM_RX_0,
  5351. .stream_name = "Secondary TDM0 Playback",
  5352. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5353. .platform_name = "msm-pcm-routing",
  5354. .codec_name = "msm-stub-codec.1",
  5355. .codec_dai_name = "msm-stub-rx",
  5356. .no_pcm = 1,
  5357. .dpcm_playback = 1,
  5358. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5359. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5360. .ops = &kona_tdm_be_ops,
  5361. .ignore_suspend = 1,
  5362. .ignore_pmdown_time = 1,
  5363. },
  5364. {
  5365. .name = LPASS_BE_SEC_TDM_TX_0,
  5366. .stream_name = "Secondary TDM0 Capture",
  5367. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5368. .platform_name = "msm-pcm-routing",
  5369. .codec_name = "msm-stub-codec.1",
  5370. .codec_dai_name = "msm-stub-tx",
  5371. .no_pcm = 1,
  5372. .dpcm_capture = 1,
  5373. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5374. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5375. .ops = &kona_tdm_be_ops,
  5376. .ignore_suspend = 1,
  5377. },
  5378. {
  5379. .name = LPASS_BE_TERT_TDM_RX_0,
  5380. .stream_name = "Tertiary TDM0 Playback",
  5381. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5382. .platform_name = "msm-pcm-routing",
  5383. .codec_name = "msm-stub-codec.1",
  5384. .codec_dai_name = "msm-stub-rx",
  5385. .no_pcm = 1,
  5386. .dpcm_playback = 1,
  5387. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5388. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5389. .ops = &kona_tdm_be_ops,
  5390. .ignore_suspend = 1,
  5391. .ignore_pmdown_time = 1,
  5392. },
  5393. {
  5394. .name = LPASS_BE_TERT_TDM_TX_0,
  5395. .stream_name = "Tertiary TDM0 Capture",
  5396. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5397. .platform_name = "msm-pcm-routing",
  5398. .codec_name = "msm-stub-codec.1",
  5399. .codec_dai_name = "msm-stub-tx",
  5400. .no_pcm = 1,
  5401. .dpcm_capture = 1,
  5402. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5403. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5404. .ops = &kona_tdm_be_ops,
  5405. .ignore_suspend = 1,
  5406. },
  5407. {
  5408. .name = LPASS_BE_QUAT_TDM_RX_0,
  5409. .stream_name = "Quaternary TDM0 Playback",
  5410. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5411. .platform_name = "msm-pcm-routing",
  5412. .codec_name = "msm-stub-codec.1",
  5413. .codec_dai_name = "msm-stub-rx",
  5414. .no_pcm = 1,
  5415. .dpcm_playback = 1,
  5416. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5417. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5418. .ops = &kona_tdm_be_ops,
  5419. .ignore_suspend = 1,
  5420. .ignore_pmdown_time = 1,
  5421. },
  5422. {
  5423. .name = LPASS_BE_QUAT_TDM_TX_0,
  5424. .stream_name = "Quaternary TDM0 Capture",
  5425. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5426. .platform_name = "msm-pcm-routing",
  5427. .codec_name = "msm-stub-codec.1",
  5428. .codec_dai_name = "msm-stub-tx",
  5429. .no_pcm = 1,
  5430. .dpcm_capture = 1,
  5431. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5432. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5433. .ops = &kona_tdm_be_ops,
  5434. .ignore_suspend = 1,
  5435. },
  5436. {
  5437. .name = LPASS_BE_QUIN_TDM_RX_0,
  5438. .stream_name = "Quinary TDM0 Playback",
  5439. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5440. .platform_name = "msm-pcm-routing",
  5441. .codec_name = "msm-stub-codec.1",
  5442. .codec_dai_name = "msm-stub-rx",
  5443. .no_pcm = 1,
  5444. .dpcm_playback = 1,
  5445. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5446. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5447. .ops = &kona_tdm_be_ops,
  5448. .ignore_suspend = 1,
  5449. .ignore_pmdown_time = 1,
  5450. },
  5451. {
  5452. .name = LPASS_BE_QUIN_TDM_TX_0,
  5453. .stream_name = "Quinary TDM0 Capture",
  5454. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5455. .platform_name = "msm-pcm-routing",
  5456. .codec_name = "msm-stub-codec.1",
  5457. .codec_dai_name = "msm-stub-tx",
  5458. .no_pcm = 1,
  5459. .dpcm_capture = 1,
  5460. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5461. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5462. .ops = &kona_tdm_be_ops,
  5463. .ignore_suspend = 1,
  5464. },
  5465. {
  5466. .name = LPASS_BE_SEN_TDM_RX_0,
  5467. .stream_name = "Senary TDM0 Playback",
  5468. .cpu_dai_name = "msm-dai-q6-tdm.36944",
  5469. .platform_name = "msm-pcm-routing",
  5470. .codec_name = "msm-stub-codec.1",
  5471. .codec_dai_name = "msm-stub-rx",
  5472. .no_pcm = 1,
  5473. .dpcm_playback = 1,
  5474. .id = MSM_BACKEND_DAI_SEN_TDM_RX_0,
  5475. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5476. .ops = &kona_tdm_be_ops,
  5477. .ignore_suspend = 1,
  5478. .ignore_pmdown_time = 1,
  5479. },
  5480. {
  5481. .name = LPASS_BE_SEN_TDM_TX_0,
  5482. .stream_name = "Senary TDM0 Capture",
  5483. .cpu_dai_name = "msm-dai-q6-tdm.36945",
  5484. .platform_name = "msm-pcm-routing",
  5485. .codec_name = "msm-stub-codec.1",
  5486. .codec_dai_name = "msm-stub-tx",
  5487. .no_pcm = 1,
  5488. .dpcm_capture = 1,
  5489. .id = MSM_BACKEND_DAI_SEN_TDM_TX_0,
  5490. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5491. .ops = &kona_tdm_be_ops,
  5492. .ignore_suspend = 1,
  5493. },
  5494. };
  5495. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5496. {
  5497. .name = LPASS_BE_SLIMBUS_7_RX,
  5498. .stream_name = "Slimbus7 Playback",
  5499. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5500. .platform_name = "msm-pcm-routing",
  5501. .codec_name = "btfmslim_slave",
  5502. /* BT codec driver determines capabilities based on
  5503. * dai name, bt codecdai name should always contains
  5504. * supported usecase information
  5505. */
  5506. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5507. .no_pcm = 1,
  5508. .dpcm_playback = 1,
  5509. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5510. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5511. .init = &msm_wcn_init,
  5512. .ops = &msm_wcn_ops,
  5513. /* dai link has playback support */
  5514. .ignore_pmdown_time = 1,
  5515. .ignore_suspend = 1,
  5516. },
  5517. {
  5518. .name = LPASS_BE_SLIMBUS_7_TX,
  5519. .stream_name = "Slimbus7 Capture",
  5520. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5521. .platform_name = "msm-pcm-routing",
  5522. .codec_name = "btfmslim_slave",
  5523. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5524. .no_pcm = 1,
  5525. .dpcm_capture = 1,
  5526. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5527. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5528. .ops = &msm_wcn_ops,
  5529. .ignore_suspend = 1,
  5530. },
  5531. };
  5532. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  5533. {
  5534. .name = LPASS_BE_SLIMBUS_7_RX,
  5535. .stream_name = "Slimbus7 Playback",
  5536. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5537. .platform_name = "msm-pcm-routing",
  5538. .codec_name = "btfmslim_slave",
  5539. /* BT codec driver determines capabilities based on
  5540. * dai name, bt codecdai name should always contains
  5541. * supported usecase information
  5542. */
  5543. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5544. .no_pcm = 1,
  5545. .dpcm_playback = 1,
  5546. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5547. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5548. .init = &msm_wcn_init_lito,
  5549. .ops = &msm_wcn_ops_lito,
  5550. /* dai link has playback support */
  5551. .ignore_pmdown_time = 1,
  5552. .ignore_suspend = 1,
  5553. },
  5554. {
  5555. .name = LPASS_BE_SLIMBUS_7_TX,
  5556. .stream_name = "Slimbus7 Capture",
  5557. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5558. .platform_name = "msm-pcm-routing",
  5559. .codec_name = "btfmslim_slave",
  5560. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5561. .no_pcm = 1,
  5562. .dpcm_capture = 1,
  5563. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5564. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5565. .ops = &msm_wcn_ops_lito,
  5566. .ignore_suspend = 1,
  5567. },
  5568. {
  5569. .name = LPASS_BE_SLIMBUS_8_TX,
  5570. .stream_name = "Slimbus8 Capture",
  5571. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5572. .platform_name = "msm-pcm-routing",
  5573. .codec_name = "btfmslim_slave",
  5574. .codec_dai_name = "btfm_fm_slim_tx",
  5575. .no_pcm = 1,
  5576. .dpcm_capture = 1,
  5577. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5578. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5579. .ops = &msm_wcn_ops_lito,
  5580. .ignore_suspend = 1,
  5581. },
  5582. };
  5583. static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
  5584. /* DISP PORT BACK END DAI Link */
  5585. {
  5586. .name = LPASS_BE_DISPLAY_PORT,
  5587. .stream_name = "Display Port Playback",
  5588. .cpu_dai_name = "msm-dai-q6-dp.0",
  5589. .platform_name = "msm-pcm-routing",
  5590. .codec_name = "msm-ext-disp-audio-codec-rx",
  5591. .codec_dai_name = "msm_dp_audio_codec_rx_dai",
  5592. .no_pcm = 1,
  5593. .dpcm_playback = 1,
  5594. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
  5595. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5596. .ignore_pmdown_time = 1,
  5597. .ignore_suspend = 1,
  5598. },
  5599. /* DISP PORT 1 BACK END DAI Link */
  5600. {
  5601. .name = LPASS_BE_DISPLAY_PORT1,
  5602. .stream_name = "Display Port1 Playback",
  5603. .cpu_dai_name = "msm-dai-q6-dp.1",
  5604. .platform_name = "msm-pcm-routing",
  5605. .codec_name = "msm-ext-disp-audio-codec-rx",
  5606. .codec_dai_name = "msm_dp_audio_codec_rx1_dai",
  5607. .no_pcm = 1,
  5608. .dpcm_playback = 1,
  5609. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
  5610. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5611. .ignore_pmdown_time = 1,
  5612. .ignore_suspend = 1,
  5613. },
  5614. };
  5615. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5616. {
  5617. .name = LPASS_BE_PRI_MI2S_RX,
  5618. .stream_name = "Primary MI2S Playback",
  5619. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5620. .platform_name = "msm-pcm-routing",
  5621. .codec_name = "msm-stub-codec.1",
  5622. .codec_dai_name = "msm-stub-rx",
  5623. .no_pcm = 1,
  5624. .dpcm_playback = 1,
  5625. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5626. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5627. .ops = &msm_mi2s_be_ops,
  5628. .ignore_suspend = 1,
  5629. .ignore_pmdown_time = 1,
  5630. },
  5631. {
  5632. .name = LPASS_BE_PRI_MI2S_TX,
  5633. .stream_name = "Primary MI2S Capture",
  5634. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5635. .platform_name = "msm-pcm-routing",
  5636. .codec_name = "msm-stub-codec.1",
  5637. .codec_dai_name = "msm-stub-tx",
  5638. .no_pcm = 1,
  5639. .dpcm_capture = 1,
  5640. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5641. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5642. .ops = &msm_mi2s_be_ops,
  5643. .ignore_suspend = 1,
  5644. },
  5645. {
  5646. .name = LPASS_BE_SEC_MI2S_RX,
  5647. .stream_name = "Secondary MI2S Playback",
  5648. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5649. .platform_name = "msm-pcm-routing",
  5650. .codec_name = "msm-stub-codec.1",
  5651. .codec_dai_name = "msm-stub-rx",
  5652. .no_pcm = 1,
  5653. .dpcm_playback = 1,
  5654. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5655. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5656. .ops = &msm_mi2s_be_ops,
  5657. .ignore_suspend = 1,
  5658. .ignore_pmdown_time = 1,
  5659. },
  5660. {
  5661. .name = LPASS_BE_SEC_MI2S_TX,
  5662. .stream_name = "Secondary MI2S Capture",
  5663. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5664. .platform_name = "msm-pcm-routing",
  5665. .codec_name = "msm-stub-codec.1",
  5666. .codec_dai_name = "msm-stub-tx",
  5667. .no_pcm = 1,
  5668. .dpcm_capture = 1,
  5669. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5670. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5671. .ops = &msm_mi2s_be_ops,
  5672. .ignore_suspend = 1,
  5673. },
  5674. {
  5675. .name = LPASS_BE_TERT_MI2S_RX,
  5676. .stream_name = "Tertiary MI2S Playback",
  5677. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5678. .platform_name = "msm-pcm-routing",
  5679. .codec_name = "msm-stub-codec.1",
  5680. .codec_dai_name = "msm-stub-rx",
  5681. .no_pcm = 1,
  5682. .dpcm_playback = 1,
  5683. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5684. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5685. .ops = &msm_mi2s_be_ops,
  5686. .ignore_suspend = 1,
  5687. .ignore_pmdown_time = 1,
  5688. },
  5689. {
  5690. .name = LPASS_BE_TERT_MI2S_TX,
  5691. .stream_name = "Tertiary MI2S Capture",
  5692. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5693. .platform_name = "msm-pcm-routing",
  5694. .codec_name = "msm-stub-codec.1",
  5695. .codec_dai_name = "msm-stub-tx",
  5696. .no_pcm = 1,
  5697. .dpcm_capture = 1,
  5698. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5699. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5700. .ops = &msm_mi2s_be_ops,
  5701. .ignore_suspend = 1,
  5702. },
  5703. {
  5704. .name = LPASS_BE_QUAT_MI2S_RX,
  5705. .stream_name = "Quaternary MI2S Playback",
  5706. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5707. .platform_name = "msm-pcm-routing",
  5708. .codec_name = "msm-stub-codec.1",
  5709. .codec_dai_name = "msm-stub-rx",
  5710. .no_pcm = 1,
  5711. .dpcm_playback = 1,
  5712. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5713. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5714. .ops = &msm_mi2s_be_ops,
  5715. .ignore_suspend = 1,
  5716. .ignore_pmdown_time = 1,
  5717. },
  5718. {
  5719. .name = LPASS_BE_QUAT_MI2S_TX,
  5720. .stream_name = "Quaternary MI2S Capture",
  5721. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5722. .platform_name = "msm-pcm-routing",
  5723. .codec_name = "msm-stub-codec.1",
  5724. .codec_dai_name = "msm-stub-tx",
  5725. .no_pcm = 1,
  5726. .dpcm_capture = 1,
  5727. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5728. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5729. .ops = &msm_mi2s_be_ops,
  5730. .ignore_suspend = 1,
  5731. },
  5732. {
  5733. .name = LPASS_BE_QUIN_MI2S_RX,
  5734. .stream_name = "Quinary MI2S Playback",
  5735. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5736. .platform_name = "msm-pcm-routing",
  5737. .codec_name = "msm-stub-codec.1",
  5738. .codec_dai_name = "msm-stub-rx",
  5739. .no_pcm = 1,
  5740. .dpcm_playback = 1,
  5741. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5742. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5743. .ops = &msm_mi2s_be_ops,
  5744. .ignore_suspend = 1,
  5745. .ignore_pmdown_time = 1,
  5746. },
  5747. {
  5748. .name = LPASS_BE_QUIN_MI2S_TX,
  5749. .stream_name = "Quinary MI2S Capture",
  5750. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5751. .platform_name = "msm-pcm-routing",
  5752. .codec_name = "msm-stub-codec.1",
  5753. .codec_dai_name = "msm-stub-tx",
  5754. .no_pcm = 1,
  5755. .dpcm_capture = 1,
  5756. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5757. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5758. .ops = &msm_mi2s_be_ops,
  5759. .ignore_suspend = 1,
  5760. },
  5761. {
  5762. .name = LPASS_BE_SENARY_MI2S_RX,
  5763. .stream_name = "Senary MI2S Playback",
  5764. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  5765. .platform_name = "msm-pcm-routing",
  5766. .codec_name = "msm-stub-codec.1",
  5767. .codec_dai_name = "msm-stub-rx",
  5768. .no_pcm = 1,
  5769. .dpcm_playback = 1,
  5770. .id = MSM_BACKEND_DAI_SENARY_MI2S_RX,
  5771. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5772. .ops = &msm_mi2s_be_ops,
  5773. .ignore_suspend = 1,
  5774. .ignore_pmdown_time = 1,
  5775. },
  5776. {
  5777. .name = LPASS_BE_SENARY_MI2S_TX,
  5778. .stream_name = "Senary MI2S Capture",
  5779. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  5780. .platform_name = "msm-pcm-routing",
  5781. .codec_name = "msm-stub-codec.1",
  5782. .codec_dai_name = "msm-stub-tx",
  5783. .no_pcm = 1,
  5784. .dpcm_capture = 1,
  5785. .id = MSM_BACKEND_DAI_SENARY_MI2S_TX,
  5786. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5787. .ops = &msm_mi2s_be_ops,
  5788. .ignore_suspend = 1,
  5789. },
  5790. };
  5791. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5792. /* Primary AUX PCM Backend DAI Links */
  5793. {
  5794. .name = LPASS_BE_AUXPCM_RX,
  5795. .stream_name = "AUX PCM Playback",
  5796. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5797. .platform_name = "msm-pcm-routing",
  5798. .codec_name = "msm-stub-codec.1",
  5799. .codec_dai_name = "msm-stub-rx",
  5800. .no_pcm = 1,
  5801. .dpcm_playback = 1,
  5802. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5803. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5804. .ops = &kona_aux_be_ops,
  5805. .ignore_pmdown_time = 1,
  5806. .ignore_suspend = 1,
  5807. },
  5808. {
  5809. .name = LPASS_BE_AUXPCM_TX,
  5810. .stream_name = "AUX PCM Capture",
  5811. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5812. .platform_name = "msm-pcm-routing",
  5813. .codec_name = "msm-stub-codec.1",
  5814. .codec_dai_name = "msm-stub-tx",
  5815. .no_pcm = 1,
  5816. .dpcm_capture = 1,
  5817. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5818. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5819. .ops = &kona_aux_be_ops,
  5820. .ignore_suspend = 1,
  5821. },
  5822. /* Secondary AUX PCM Backend DAI Links */
  5823. {
  5824. .name = LPASS_BE_SEC_AUXPCM_RX,
  5825. .stream_name = "Sec AUX PCM Playback",
  5826. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5827. .platform_name = "msm-pcm-routing",
  5828. .codec_name = "msm-stub-codec.1",
  5829. .codec_dai_name = "msm-stub-rx",
  5830. .no_pcm = 1,
  5831. .dpcm_playback = 1,
  5832. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5833. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5834. .ops = &kona_aux_be_ops,
  5835. .ignore_pmdown_time = 1,
  5836. .ignore_suspend = 1,
  5837. },
  5838. {
  5839. .name = LPASS_BE_SEC_AUXPCM_TX,
  5840. .stream_name = "Sec AUX PCM Capture",
  5841. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5842. .platform_name = "msm-pcm-routing",
  5843. .codec_name = "msm-stub-codec.1",
  5844. .codec_dai_name = "msm-stub-tx",
  5845. .no_pcm = 1,
  5846. .dpcm_capture = 1,
  5847. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5848. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5849. .ops = &kona_aux_be_ops,
  5850. .ignore_suspend = 1,
  5851. },
  5852. /* Tertiary AUX PCM Backend DAI Links */
  5853. {
  5854. .name = LPASS_BE_TERT_AUXPCM_RX,
  5855. .stream_name = "Tert AUX PCM Playback",
  5856. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5857. .platform_name = "msm-pcm-routing",
  5858. .codec_name = "msm-stub-codec.1",
  5859. .codec_dai_name = "msm-stub-rx",
  5860. .no_pcm = 1,
  5861. .dpcm_playback = 1,
  5862. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5863. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5864. .ops = &kona_aux_be_ops,
  5865. .ignore_suspend = 1,
  5866. },
  5867. {
  5868. .name = LPASS_BE_TERT_AUXPCM_TX,
  5869. .stream_name = "Tert AUX PCM Capture",
  5870. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5871. .platform_name = "msm-pcm-routing",
  5872. .codec_name = "msm-stub-codec.1",
  5873. .codec_dai_name = "msm-stub-tx",
  5874. .no_pcm = 1,
  5875. .dpcm_capture = 1,
  5876. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5877. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5878. .ops = &kona_aux_be_ops,
  5879. .ignore_suspend = 1,
  5880. },
  5881. /* Quaternary AUX PCM Backend DAI Links */
  5882. {
  5883. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5884. .stream_name = "Quat AUX PCM Playback",
  5885. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5886. .platform_name = "msm-pcm-routing",
  5887. .codec_name = "msm-stub-codec.1",
  5888. .codec_dai_name = "msm-stub-rx",
  5889. .no_pcm = 1,
  5890. .dpcm_playback = 1,
  5891. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5892. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5893. .ops = &kona_aux_be_ops,
  5894. .ignore_suspend = 1,
  5895. },
  5896. {
  5897. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5898. .stream_name = "Quat AUX PCM Capture",
  5899. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5900. .platform_name = "msm-pcm-routing",
  5901. .codec_name = "msm-stub-codec.1",
  5902. .codec_dai_name = "msm-stub-tx",
  5903. .no_pcm = 1,
  5904. .dpcm_capture = 1,
  5905. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5906. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5907. .ops = &kona_aux_be_ops,
  5908. .ignore_suspend = 1,
  5909. },
  5910. /* Quinary AUX PCM Backend DAI Links */
  5911. {
  5912. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5913. .stream_name = "Quin AUX PCM Playback",
  5914. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5915. .platform_name = "msm-pcm-routing",
  5916. .codec_name = "msm-stub-codec.1",
  5917. .codec_dai_name = "msm-stub-rx",
  5918. .no_pcm = 1,
  5919. .dpcm_playback = 1,
  5920. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5921. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5922. .ops = &kona_aux_be_ops,
  5923. .ignore_suspend = 1,
  5924. },
  5925. {
  5926. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5927. .stream_name = "Quin AUX PCM Capture",
  5928. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5929. .platform_name = "msm-pcm-routing",
  5930. .codec_name = "msm-stub-codec.1",
  5931. .codec_dai_name = "msm-stub-tx",
  5932. .no_pcm = 1,
  5933. .dpcm_capture = 1,
  5934. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5935. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5936. .ops = &kona_aux_be_ops,
  5937. .ignore_suspend = 1,
  5938. },
  5939. /* Senary AUX PCM Backend DAI Links */
  5940. {
  5941. .name = LPASS_BE_SEN_AUXPCM_RX,
  5942. .stream_name = "Sen AUX PCM Playback",
  5943. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  5944. .platform_name = "msm-pcm-routing",
  5945. .codec_name = "msm-stub-codec.1",
  5946. .codec_dai_name = "msm-stub-rx",
  5947. .no_pcm = 1,
  5948. .dpcm_playback = 1,
  5949. .id = MSM_BACKEND_DAI_SEN_AUXPCM_RX,
  5950. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5951. .ops = &kona_aux_be_ops,
  5952. .ignore_suspend = 1,
  5953. },
  5954. {
  5955. .name = LPASS_BE_SEN_AUXPCM_TX,
  5956. .stream_name = "Sen AUX PCM Capture",
  5957. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  5958. .platform_name = "msm-pcm-routing",
  5959. .codec_name = "msm-stub-codec.1",
  5960. .codec_dai_name = "msm-stub-tx",
  5961. .no_pcm = 1,
  5962. .dpcm_capture = 1,
  5963. .id = MSM_BACKEND_DAI_SEN_AUXPCM_TX,
  5964. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5965. .ops = &kona_aux_be_ops,
  5966. .ignore_suspend = 1,
  5967. },
  5968. };
  5969. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5970. /* WSA CDC DMA Backend DAI Links */
  5971. {
  5972. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5973. .stream_name = "WSA CDC DMA0 Playback",
  5974. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  5975. .platform_name = "msm-pcm-routing",
  5976. .codec_name = "bolero_codec",
  5977. .codec_dai_name = "wsa_macro_rx1",
  5978. .no_pcm = 1,
  5979. .dpcm_playback = 1,
  5980. .init = &msm_int_audrx_init,
  5981. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5982. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5983. .ignore_pmdown_time = 1,
  5984. .ignore_suspend = 1,
  5985. .ops = &msm_cdc_dma_be_ops,
  5986. },
  5987. {
  5988. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5989. .stream_name = "WSA CDC DMA1 Playback",
  5990. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  5991. .platform_name = "msm-pcm-routing",
  5992. .codec_name = "bolero_codec",
  5993. .codec_dai_name = "wsa_macro_rx_mix",
  5994. .no_pcm = 1,
  5995. .dpcm_playback = 1,
  5996. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5997. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5998. .ignore_pmdown_time = 1,
  5999. .ignore_suspend = 1,
  6000. .ops = &msm_cdc_dma_be_ops,
  6001. },
  6002. {
  6003. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  6004. .stream_name = "WSA CDC DMA1 Capture",
  6005. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  6006. .platform_name = "msm-pcm-routing",
  6007. .codec_name = "bolero_codec",
  6008. .codec_dai_name = "wsa_macro_echo",
  6009. .no_pcm = 1,
  6010. .dpcm_capture = 1,
  6011. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  6012. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6013. .ignore_suspend = 1,
  6014. .ops = &msm_cdc_dma_be_ops,
  6015. },
  6016. };
  6017. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  6018. /* RX CDC DMA Backend DAI Links */
  6019. {
  6020. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  6021. .stream_name = "RX CDC DMA0 Playback",
  6022. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  6023. .platform_name = "msm-pcm-routing",
  6024. .codec_name = "bolero_codec",
  6025. .codec_dai_name = "rx_macro_rx1",
  6026. .dynamic_be = 1,
  6027. .no_pcm = 1,
  6028. .dpcm_playback = 1,
  6029. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  6030. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6031. .ignore_pmdown_time = 1,
  6032. .ignore_suspend = 1,
  6033. .ops = &msm_cdc_dma_be_ops,
  6034. },
  6035. {
  6036. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  6037. .stream_name = "RX CDC DMA1 Playback",
  6038. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  6039. .platform_name = "msm-pcm-routing",
  6040. .codec_name = "bolero_codec",
  6041. .codec_dai_name = "rx_macro_rx2",
  6042. .dynamic_be = 1,
  6043. .no_pcm = 1,
  6044. .dpcm_playback = 1,
  6045. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  6046. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6047. .ignore_pmdown_time = 1,
  6048. .ignore_suspend = 1,
  6049. .ops = &msm_cdc_dma_be_ops,
  6050. },
  6051. {
  6052. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  6053. .stream_name = "RX CDC DMA2 Playback",
  6054. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  6055. .platform_name = "msm-pcm-routing",
  6056. .codec_name = "bolero_codec",
  6057. .codec_dai_name = "rx_macro_rx3",
  6058. .dynamic_be = 1,
  6059. .no_pcm = 1,
  6060. .dpcm_playback = 1,
  6061. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  6062. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6063. .ignore_pmdown_time = 1,
  6064. .ignore_suspend = 1,
  6065. .ops = &msm_cdc_dma_be_ops,
  6066. },
  6067. {
  6068. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  6069. .stream_name = "RX CDC DMA3 Playback",
  6070. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  6071. .platform_name = "msm-pcm-routing",
  6072. .codec_name = "bolero_codec",
  6073. .codec_dai_name = "rx_macro_rx4",
  6074. .dynamic_be = 1,
  6075. .no_pcm = 1,
  6076. .dpcm_playback = 1,
  6077. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  6078. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6079. .ignore_pmdown_time = 1,
  6080. .ignore_suspend = 1,
  6081. .ops = &msm_cdc_dma_be_ops,
  6082. },
  6083. /* TX CDC DMA Backend DAI Links */
  6084. {
  6085. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  6086. .stream_name = "TX CDC DMA3 Capture",
  6087. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  6088. .platform_name = "msm-pcm-routing",
  6089. .codec_name = "bolero_codec",
  6090. .codec_dai_name = "tx_macro_tx1",
  6091. .no_pcm = 1,
  6092. .dpcm_capture = 1,
  6093. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  6094. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6095. .ignore_suspend = 1,
  6096. .ops = &msm_cdc_dma_be_ops,
  6097. },
  6098. {
  6099. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  6100. .stream_name = "TX CDC DMA4 Capture",
  6101. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  6102. .platform_name = "msm-pcm-routing",
  6103. .codec_name = "bolero_codec",
  6104. .codec_dai_name = "tx_macro_tx2",
  6105. .no_pcm = 1,
  6106. .dpcm_capture = 1,
  6107. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  6108. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6109. .ignore_suspend = 1,
  6110. .ops = &msm_cdc_dma_be_ops,
  6111. },
  6112. };
  6113. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6114. {
  6115. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6116. .stream_name = "VA CDC DMA0 Capture",
  6117. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6118. .platform_name = "msm-pcm-routing",
  6119. .codec_name = "bolero_codec",
  6120. .codec_dai_name = "va_macro_tx1",
  6121. .no_pcm = 1,
  6122. .dpcm_capture = 1,
  6123. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6124. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6125. .ignore_suspend = 1,
  6126. .ops = &msm_cdc_dma_be_ops,
  6127. },
  6128. {
  6129. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6130. .stream_name = "VA CDC DMA1 Capture",
  6131. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6132. .platform_name = "msm-pcm-routing",
  6133. .codec_name = "bolero_codec",
  6134. .codec_dai_name = "va_macro_tx2",
  6135. .no_pcm = 1,
  6136. .dpcm_capture = 1,
  6137. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6138. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6139. .ignore_suspend = 1,
  6140. .ops = &msm_cdc_dma_be_ops,
  6141. },
  6142. {
  6143. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  6144. .stream_name = "VA CDC DMA2 Capture",
  6145. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  6146. .platform_name = "msm-pcm-routing",
  6147. .codec_name = "bolero_codec",
  6148. .codec_dai_name = "va_macro_tx3",
  6149. .no_pcm = 1,
  6150. .dpcm_capture = 1,
  6151. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  6152. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6153. .ignore_suspend = 1,
  6154. .ops = &msm_cdc_dma_be_ops,
  6155. },
  6156. };
  6157. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  6158. {
  6159. .name = LPASS_BE_AFE_LOOPBACK_TX,
  6160. .stream_name = "AFE Loopback Capture",
  6161. .cpu_dai_name = "msm-dai-q6-dev.24577",
  6162. .platform_name = "msm-pcm-routing",
  6163. .codec_name = "msm-stub-codec.1",
  6164. .codec_dai_name = "msm-stub-tx",
  6165. .no_pcm = 1,
  6166. .dpcm_capture = 1,
  6167. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  6168. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6169. .ignore_pmdown_time = 1,
  6170. .ignore_suspend = 1,
  6171. },
  6172. };
  6173. static struct snd_soc_dai_link msm_kona_dai_links[
  6174. ARRAY_SIZE(msm_common_dai_links) +
  6175. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6176. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6177. ARRAY_SIZE(msm_common_be_dai_links) +
  6178. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6179. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6180. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6181. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  6182. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6183. ARRAY_SIZE(ext_disp_be_dai_link) +
  6184. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6185. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  6186. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  6187. static int msm_populate_dai_link_component_of_node(
  6188. struct snd_soc_card *card)
  6189. {
  6190. int i, index, ret = 0;
  6191. struct device *cdev = card->dev;
  6192. struct snd_soc_dai_link *dai_link = card->dai_link;
  6193. struct device_node *np;
  6194. if (!cdev) {
  6195. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  6196. return -ENODEV;
  6197. }
  6198. for (i = 0; i < card->num_links; i++) {
  6199. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6200. continue;
  6201. /* populate platform_of_node for snd card dai links */
  6202. if (dai_link[i].platform_name &&
  6203. !dai_link[i].platform_of_node) {
  6204. index = of_property_match_string(cdev->of_node,
  6205. "asoc-platform-names",
  6206. dai_link[i].platform_name);
  6207. if (index < 0) {
  6208. dev_err(cdev, "%s: No match found for platform name: %s\n",
  6209. __func__, dai_link[i].platform_name);
  6210. ret = index;
  6211. goto err;
  6212. }
  6213. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6214. index);
  6215. if (!np) {
  6216. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  6217. __func__, dai_link[i].platform_name,
  6218. index);
  6219. ret = -ENODEV;
  6220. goto err;
  6221. }
  6222. dai_link[i].platform_of_node = np;
  6223. dai_link[i].platform_name = NULL;
  6224. }
  6225. /* populate cpu_of_node for snd card dai links */
  6226. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6227. index = of_property_match_string(cdev->of_node,
  6228. "asoc-cpu-names",
  6229. dai_link[i].cpu_dai_name);
  6230. if (index >= 0) {
  6231. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6232. index);
  6233. if (!np) {
  6234. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  6235. __func__,
  6236. dai_link[i].cpu_dai_name);
  6237. ret = -ENODEV;
  6238. goto err;
  6239. }
  6240. dai_link[i].cpu_of_node = np;
  6241. dai_link[i].cpu_dai_name = NULL;
  6242. }
  6243. }
  6244. /* populate codec_of_node for snd card dai links */
  6245. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6246. index = of_property_match_string(cdev->of_node,
  6247. "asoc-codec-names",
  6248. dai_link[i].codec_name);
  6249. if (index < 0)
  6250. continue;
  6251. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6252. index);
  6253. if (!np) {
  6254. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  6255. __func__, dai_link[i].codec_name);
  6256. ret = -ENODEV;
  6257. goto err;
  6258. }
  6259. dai_link[i].codec_of_node = np;
  6260. dai_link[i].codec_name = NULL;
  6261. }
  6262. }
  6263. err:
  6264. return ret;
  6265. }
  6266. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  6267. {
  6268. int ret = -EINVAL;
  6269. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  6270. if (!component) {
  6271. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  6272. return ret;
  6273. }
  6274. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  6275. ARRAY_SIZE(msm_snd_controls));
  6276. if (ret < 0) {
  6277. dev_err(component->dev,
  6278. "%s: add_codec_controls failed, err = %d\n",
  6279. __func__, ret);
  6280. return ret;
  6281. }
  6282. return ret;
  6283. }
  6284. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  6285. struct snd_pcm_hw_params *params)
  6286. {
  6287. return 0;
  6288. }
  6289. static struct snd_soc_ops msm_stub_be_ops = {
  6290. .hw_params = msm_snd_stub_hw_params,
  6291. };
  6292. struct snd_soc_card snd_soc_card_stub_msm = {
  6293. .name = "kona-stub-snd-card",
  6294. };
  6295. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6296. /* FrontEnd DAI Links */
  6297. {
  6298. .name = "MSMSTUB Media1",
  6299. .stream_name = "MultiMedia1",
  6300. .cpu_dai_name = "MultiMedia1",
  6301. .platform_name = "msm-pcm-dsp.0",
  6302. .dynamic = 1,
  6303. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6304. .dpcm_playback = 1,
  6305. .dpcm_capture = 1,
  6306. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6307. SND_SOC_DPCM_TRIGGER_POST},
  6308. .codec_dai_name = "snd-soc-dummy-dai",
  6309. .codec_name = "snd-soc-dummy",
  6310. .ignore_suspend = 1,
  6311. /* this dainlink has playback support */
  6312. .ignore_pmdown_time = 1,
  6313. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6314. },
  6315. };
  6316. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6317. /* Backend DAI Links */
  6318. {
  6319. .name = LPASS_BE_AUXPCM_RX,
  6320. .stream_name = "AUX PCM Playback",
  6321. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6322. .platform_name = "msm-pcm-routing",
  6323. .codec_name = "msm-stub-codec.1",
  6324. .codec_dai_name = "msm-stub-rx",
  6325. .no_pcm = 1,
  6326. .dpcm_playback = 1,
  6327. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6328. .init = &msm_audrx_stub_init,
  6329. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6330. .ignore_pmdown_time = 1,
  6331. .ignore_suspend = 1,
  6332. .ops = &msm_stub_be_ops,
  6333. },
  6334. {
  6335. .name = LPASS_BE_AUXPCM_TX,
  6336. .stream_name = "AUX PCM Capture",
  6337. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6338. .platform_name = "msm-pcm-routing",
  6339. .codec_name = "msm-stub-codec.1",
  6340. .codec_dai_name = "msm-stub-tx",
  6341. .no_pcm = 1,
  6342. .dpcm_capture = 1,
  6343. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6344. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6345. .ignore_suspend = 1,
  6346. .ops = &msm_stub_be_ops,
  6347. },
  6348. };
  6349. static struct snd_soc_dai_link msm_stub_dai_links[
  6350. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6351. ARRAY_SIZE(msm_stub_be_dai_links)];
  6352. static const struct of_device_id kona_asoc_machine_of_match[] = {
  6353. { .compatible = "qcom,kona-asoc-snd",
  6354. .data = "codec"},
  6355. { .compatible = "qcom,kona-asoc-snd-stub",
  6356. .data = "stub_codec"},
  6357. {},
  6358. };
  6359. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6360. {
  6361. struct snd_soc_card *card = NULL;
  6362. struct snd_soc_dai_link *dailink = NULL;
  6363. int len_1 = 0;
  6364. int len_2 = 0;
  6365. int total_links = 0;
  6366. int rc = 0;
  6367. u32 mi2s_audio_intf = 0;
  6368. u32 auxpcm_audio_intf = 0;
  6369. u32 val = 0;
  6370. u32 wcn_btfm_intf = 0;
  6371. const struct of_device_id *match;
  6372. match = of_match_node(kona_asoc_machine_of_match, dev->of_node);
  6373. if (!match) {
  6374. dev_err(dev, "%s: No DT match found for sound card\n",
  6375. __func__);
  6376. return NULL;
  6377. }
  6378. if (!strcmp(match->data, "codec")) {
  6379. card = &snd_soc_card_kona_msm;
  6380. memcpy(msm_kona_dai_links + total_links,
  6381. msm_common_dai_links,
  6382. sizeof(msm_common_dai_links));
  6383. total_links += ARRAY_SIZE(msm_common_dai_links);
  6384. memcpy(msm_kona_dai_links + total_links,
  6385. msm_bolero_fe_dai_links,
  6386. sizeof(msm_bolero_fe_dai_links));
  6387. total_links +=
  6388. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6389. memcpy(msm_kona_dai_links + total_links,
  6390. msm_common_misc_fe_dai_links,
  6391. sizeof(msm_common_misc_fe_dai_links));
  6392. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6393. memcpy(msm_kona_dai_links + total_links,
  6394. msm_common_be_dai_links,
  6395. sizeof(msm_common_be_dai_links));
  6396. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6397. memcpy(msm_kona_dai_links + total_links,
  6398. msm_wsa_cdc_dma_be_dai_links,
  6399. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6400. total_links +=
  6401. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6402. memcpy(msm_kona_dai_links + total_links,
  6403. msm_rx_tx_cdc_dma_be_dai_links,
  6404. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  6405. total_links +=
  6406. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  6407. memcpy(msm_kona_dai_links + total_links,
  6408. msm_va_cdc_dma_be_dai_links,
  6409. sizeof(msm_va_cdc_dma_be_dai_links));
  6410. total_links +=
  6411. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6412. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6413. &mi2s_audio_intf);
  6414. if (rc) {
  6415. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6416. __func__);
  6417. } else {
  6418. if (mi2s_audio_intf) {
  6419. memcpy(msm_kona_dai_links + total_links,
  6420. msm_mi2s_be_dai_links,
  6421. sizeof(msm_mi2s_be_dai_links));
  6422. total_links +=
  6423. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6424. }
  6425. }
  6426. rc = of_property_read_u32(dev->of_node,
  6427. "qcom,auxpcm-audio-intf",
  6428. &auxpcm_audio_intf);
  6429. if (rc) {
  6430. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6431. __func__);
  6432. } else {
  6433. if (auxpcm_audio_intf) {
  6434. memcpy(msm_kona_dai_links + total_links,
  6435. msm_auxpcm_be_dai_links,
  6436. sizeof(msm_auxpcm_be_dai_links));
  6437. total_links +=
  6438. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6439. }
  6440. }
  6441. rc = of_property_read_u32(dev->of_node,
  6442. "qcom,ext-disp-audio-rx", &val);
  6443. if (!rc && val) {
  6444. dev_dbg(dev, "%s(): ext disp audio support present\n",
  6445. __func__);
  6446. memcpy(msm_kona_dai_links + total_links,
  6447. ext_disp_be_dai_link,
  6448. sizeof(ext_disp_be_dai_link));
  6449. total_links += ARRAY_SIZE(ext_disp_be_dai_link);
  6450. }
  6451. rc = of_property_read_u32(dev->of_node, "qcom,wcn-bt", &val);
  6452. if (!rc && val) {
  6453. dev_dbg(dev, "%s(): WCN BT support present\n",
  6454. __func__);
  6455. memcpy(msm_kona_dai_links + total_links,
  6456. msm_wcn_be_dai_links,
  6457. sizeof(msm_wcn_be_dai_links));
  6458. total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
  6459. }
  6460. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  6461. &val);
  6462. if (!rc && val) {
  6463. memcpy(msm_kona_dai_links + total_links,
  6464. msm_afe_rxtx_lb_be_dai_link,
  6465. sizeof(msm_afe_rxtx_lb_be_dai_link));
  6466. total_links +=
  6467. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  6468. }
  6469. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  6470. &wcn_btfm_intf);
  6471. if (rc) {
  6472. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  6473. __func__);
  6474. } else {
  6475. if (wcn_btfm_intf) {
  6476. memcpy(msm_kona_dai_links + total_links,
  6477. msm_wcn_btfm_be_dai_links,
  6478. sizeof(msm_wcn_btfm_be_dai_links));
  6479. total_links +=
  6480. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  6481. }
  6482. }
  6483. dailink = msm_kona_dai_links;
  6484. } else if(!strcmp(match->data, "stub_codec")) {
  6485. card = &snd_soc_card_stub_msm;
  6486. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  6487. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  6488. memcpy(msm_stub_dai_links,
  6489. msm_stub_fe_dai_links,
  6490. sizeof(msm_stub_fe_dai_links));
  6491. memcpy(msm_stub_dai_links + len_1,
  6492. msm_stub_be_dai_links,
  6493. sizeof(msm_stub_be_dai_links));
  6494. dailink = msm_stub_dai_links;
  6495. total_links = len_2;
  6496. }
  6497. if (card) {
  6498. card->dai_link = dailink;
  6499. card->num_links = total_links;
  6500. }
  6501. return card;
  6502. }
  6503. static int msm_wsa881x_init(struct snd_soc_component *component)
  6504. {
  6505. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6506. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6507. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6508. SPKR_L_BOOST, SPKR_L_VI};
  6509. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6510. SPKR_R_BOOST, SPKR_R_VI};
  6511. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6512. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6513. struct msm_asoc_mach_data *pdata;
  6514. struct snd_soc_dapm_context *dapm;
  6515. struct snd_card *card;
  6516. struct snd_info_entry *entry;
  6517. int ret = 0;
  6518. if (!component) {
  6519. pr_err("%s component is NULL\n", __func__);
  6520. return -EINVAL;
  6521. }
  6522. card = component->card->snd_card;
  6523. dapm = snd_soc_component_get_dapm(component);
  6524. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6525. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  6526. __func__, component->name);
  6527. wsa881x_set_channel_map(component, &spkleft_ports[0],
  6528. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6529. &ch_rate[0], &spkleft_port_types[0]);
  6530. if (dapm->component) {
  6531. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6532. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6533. }
  6534. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6535. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  6536. __func__, component->name);
  6537. wsa881x_set_channel_map(component, &spkright_ports[0],
  6538. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6539. &ch_rate[0], &spkright_port_types[0]);
  6540. if (dapm->component) {
  6541. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6542. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6543. }
  6544. } else {
  6545. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  6546. component->name);
  6547. ret = -EINVAL;
  6548. goto err;
  6549. }
  6550. pdata = snd_soc_card_get_drvdata(component->card);
  6551. if (!pdata->codec_root) {
  6552. entry = snd_info_create_subdir(card->module, "codecs",
  6553. card->proc_root);
  6554. if (!entry) {
  6555. pr_err("%s: Cannot create codecs module entry\n",
  6556. __func__);
  6557. ret = 0;
  6558. goto err;
  6559. }
  6560. pdata->codec_root = entry;
  6561. }
  6562. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6563. component);
  6564. err:
  6565. return ret;
  6566. }
  6567. static int msm_aux_codec_init(struct snd_soc_component *component)
  6568. {
  6569. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  6570. int ret = 0;
  6571. void *mbhc_calibration;
  6572. struct snd_info_entry *entry;
  6573. struct snd_card *card = component->card->snd_card;
  6574. struct msm_asoc_mach_data *pdata;
  6575. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  6576. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  6577. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  6578. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  6579. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  6580. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  6581. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  6582. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  6583. snd_soc_dapm_sync(dapm);
  6584. pdata = snd_soc_card_get_drvdata(component->card);
  6585. if (!pdata->codec_root) {
  6586. entry = snd_info_create_subdir(card->module, "codecs",
  6587. card->proc_root);
  6588. if (!entry) {
  6589. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  6590. __func__);
  6591. ret = 0;
  6592. goto mbhc_cfg_cal;
  6593. }
  6594. pdata->codec_root = entry;
  6595. }
  6596. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  6597. mbhc_cfg_cal:
  6598. mbhc_calibration = def_wcd_mbhc_cal();
  6599. if (!mbhc_calibration)
  6600. return -ENOMEM;
  6601. wcd_mbhc_cfg.calibration = mbhc_calibration;
  6602. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  6603. if (ret) {
  6604. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  6605. __func__, ret);
  6606. goto err_hs_detect;
  6607. }
  6608. return 0;
  6609. err_hs_detect:
  6610. kfree(mbhc_calibration);
  6611. return ret;
  6612. }
  6613. static int msm_init_aux_dev(struct platform_device *pdev,
  6614. struct snd_soc_card *card)
  6615. {
  6616. struct device_node *wsa_of_node;
  6617. struct device_node *aux_codec_of_node;
  6618. u32 wsa_max_devs;
  6619. u32 wsa_dev_cnt;
  6620. u32 codec_max_aux_devs = 0;
  6621. u32 codec_aux_dev_cnt = 0;
  6622. int i;
  6623. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6624. struct aux_codec_dev_info *aux_cdc_dev_info;
  6625. const char *auxdev_name_prefix[1];
  6626. char *dev_name_str = NULL;
  6627. int found = 0;
  6628. int codecs_found = 0;
  6629. int ret = 0;
  6630. /* Get maximum WSA device count for this platform */
  6631. ret = of_property_read_u32(pdev->dev.of_node,
  6632. "qcom,wsa-max-devs", &wsa_max_devs);
  6633. if (ret) {
  6634. dev_info(&pdev->dev,
  6635. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6636. __func__, pdev->dev.of_node->full_name, ret);
  6637. wsa_max_devs = 0;
  6638. goto codec_aux_dev;
  6639. }
  6640. if (wsa_max_devs == 0) {
  6641. dev_warn(&pdev->dev,
  6642. "%s: Max WSA devices is 0 for this target?\n",
  6643. __func__);
  6644. goto codec_aux_dev;
  6645. }
  6646. /* Get count of WSA device phandles for this platform */
  6647. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6648. "qcom,wsa-devs", NULL);
  6649. if (wsa_dev_cnt == -ENOENT) {
  6650. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6651. __func__);
  6652. goto err;
  6653. } else if (wsa_dev_cnt <= 0) {
  6654. dev_err(&pdev->dev,
  6655. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6656. __func__, wsa_dev_cnt);
  6657. ret = -EINVAL;
  6658. goto err;
  6659. }
  6660. /*
  6661. * Expect total phandles count to be NOT less than maximum possible
  6662. * WSA count. However, if it is less, then assign same value to
  6663. * max count as well.
  6664. */
  6665. if (wsa_dev_cnt < wsa_max_devs) {
  6666. dev_dbg(&pdev->dev,
  6667. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6668. __func__, wsa_max_devs, wsa_dev_cnt);
  6669. wsa_max_devs = wsa_dev_cnt;
  6670. }
  6671. /* Make sure prefix string passed for each WSA device */
  6672. ret = of_property_count_strings(pdev->dev.of_node,
  6673. "qcom,wsa-aux-dev-prefix");
  6674. if (ret != wsa_dev_cnt) {
  6675. dev_err(&pdev->dev,
  6676. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6677. __func__, wsa_dev_cnt, ret);
  6678. ret = -EINVAL;
  6679. goto err;
  6680. }
  6681. /*
  6682. * Alloc mem to store phandle and index info of WSA device, if already
  6683. * registered with ALSA core
  6684. */
  6685. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6686. sizeof(struct msm_wsa881x_dev_info),
  6687. GFP_KERNEL);
  6688. if (!wsa881x_dev_info) {
  6689. ret = -ENOMEM;
  6690. goto err;
  6691. }
  6692. /*
  6693. * search and check whether all WSA devices are already
  6694. * registered with ALSA core or not. If found a node, store
  6695. * the node and the index in a local array of struct for later
  6696. * use.
  6697. */
  6698. for (i = 0; i < wsa_dev_cnt; i++) {
  6699. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6700. "qcom,wsa-devs", i);
  6701. if (unlikely(!wsa_of_node)) {
  6702. /* we should not be here */
  6703. dev_err(&pdev->dev,
  6704. "%s: wsa dev node is not present\n",
  6705. __func__);
  6706. ret = -EINVAL;
  6707. goto err;
  6708. }
  6709. if (soc_find_component(wsa_of_node, NULL)) {
  6710. /* WSA device registered with ALSA core */
  6711. wsa881x_dev_info[found].of_node = wsa_of_node;
  6712. wsa881x_dev_info[found].index = i;
  6713. found++;
  6714. if (found == wsa_max_devs)
  6715. break;
  6716. }
  6717. }
  6718. if (found < wsa_max_devs) {
  6719. dev_dbg(&pdev->dev,
  6720. "%s: failed to find %d components. Found only %d\n",
  6721. __func__, wsa_max_devs, found);
  6722. return -EPROBE_DEFER;
  6723. }
  6724. dev_info(&pdev->dev,
  6725. "%s: found %d wsa881x devices registered with ALSA core\n",
  6726. __func__, found);
  6727. codec_aux_dev:
  6728. /* Get maximum aux codec device count for this platform */
  6729. ret = of_property_read_u32(pdev->dev.of_node,
  6730. "qcom,codec-max-aux-devs",
  6731. &codec_max_aux_devs);
  6732. if (ret) {
  6733. dev_err(&pdev->dev,
  6734. "%s: codec-max-aux-devs property missing in DT %s, ret = %d\n",
  6735. __func__, pdev->dev.of_node->full_name, ret);
  6736. codec_max_aux_devs = 0;
  6737. goto aux_dev_register;
  6738. }
  6739. if (codec_max_aux_devs == 0) {
  6740. dev_dbg(&pdev->dev,
  6741. "%s: Max aux codec devices is 0 for this target?\n",
  6742. __func__);
  6743. goto aux_dev_register;
  6744. }
  6745. /* Get count of aux codec device phandles for this platform */
  6746. codec_aux_dev_cnt = of_count_phandle_with_args(
  6747. pdev->dev.of_node,
  6748. "qcom,codec-aux-devs", NULL);
  6749. if (codec_aux_dev_cnt == -ENOENT) {
  6750. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  6751. __func__);
  6752. goto err;
  6753. } else if (codec_aux_dev_cnt <= 0) {
  6754. dev_err(&pdev->dev,
  6755. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  6756. __func__, codec_aux_dev_cnt);
  6757. ret = -EINVAL;
  6758. goto err;
  6759. }
  6760. /*
  6761. * Expect total phandles count to be NOT less than maximum possible
  6762. * AUX device count. However, if it is less, then assign same value to
  6763. * max count as well.
  6764. */
  6765. if (codec_aux_dev_cnt < codec_max_aux_devs) {
  6766. dev_dbg(&pdev->dev,
  6767. "%s: codec_max_aux_devs = %d cannot exceed codec_aux_dev_cnt = %d\n",
  6768. __func__, codec_max_aux_devs,
  6769. codec_aux_dev_cnt);
  6770. codec_max_aux_devs = codec_aux_dev_cnt;
  6771. }
  6772. /*
  6773. * Alloc mem to store phandle and index info of aux codec
  6774. * if already registered with ALSA core
  6775. */
  6776. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  6777. sizeof(struct aux_codec_dev_info),
  6778. GFP_KERNEL);
  6779. if (!aux_cdc_dev_info) {
  6780. ret = -ENOMEM;
  6781. goto err;
  6782. }
  6783. /*
  6784. * search and check whether all aux codecs are already
  6785. * registered with ALSA core or not. If found a node, store
  6786. * the node and the index in a local array of struct for later
  6787. * use.
  6788. */
  6789. for (i = 0; i < codec_aux_dev_cnt; i++) {
  6790. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  6791. "qcom,codec-aux-devs", i);
  6792. if (unlikely(!aux_codec_of_node)) {
  6793. /* we should not be here */
  6794. dev_err(&pdev->dev,
  6795. "%s: aux codec dev node is not present\n",
  6796. __func__);
  6797. ret = -EINVAL;
  6798. goto err;
  6799. }
  6800. if (soc_find_component(aux_codec_of_node, NULL)) {
  6801. /* AUX codec registered with ALSA core */
  6802. aux_cdc_dev_info[codecs_found].of_node =
  6803. aux_codec_of_node;
  6804. aux_cdc_dev_info[codecs_found].index = i;
  6805. codecs_found++;
  6806. }
  6807. }
  6808. if (codecs_found < codec_aux_dev_cnt) {
  6809. dev_dbg(&pdev->dev,
  6810. "%s: failed to find %d components. Found only %d\n",
  6811. __func__, codec_aux_dev_cnt, codecs_found);
  6812. return -EPROBE_DEFER;
  6813. }
  6814. dev_info(&pdev->dev,
  6815. "%s: found %d AUX codecs registered with ALSA core\n",
  6816. __func__, codecs_found);
  6817. aux_dev_register:
  6818. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  6819. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  6820. /* Alloc array of AUX devs struct */
  6821. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6822. sizeof(struct snd_soc_aux_dev),
  6823. GFP_KERNEL);
  6824. if (!msm_aux_dev) {
  6825. ret = -ENOMEM;
  6826. goto err;
  6827. }
  6828. /* Alloc array of codec conf struct */
  6829. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  6830. sizeof(struct snd_soc_codec_conf),
  6831. GFP_KERNEL);
  6832. if (!msm_codec_conf) {
  6833. ret = -ENOMEM;
  6834. goto err;
  6835. }
  6836. for (i = 0; i < wsa_max_devs; i++) {
  6837. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6838. GFP_KERNEL);
  6839. if (!dev_name_str) {
  6840. ret = -ENOMEM;
  6841. goto err;
  6842. }
  6843. ret = of_property_read_string_index(pdev->dev.of_node,
  6844. "qcom,wsa-aux-dev-prefix",
  6845. wsa881x_dev_info[i].index,
  6846. auxdev_name_prefix);
  6847. if (ret) {
  6848. dev_err(&pdev->dev,
  6849. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6850. __func__, ret);
  6851. ret = -EINVAL;
  6852. goto err;
  6853. }
  6854. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6855. msm_aux_dev[i].name = dev_name_str;
  6856. msm_aux_dev[i].codec_name = NULL;
  6857. msm_aux_dev[i].codec_of_node =
  6858. wsa881x_dev_info[i].of_node;
  6859. msm_aux_dev[i].init = msm_wsa881x_init;
  6860. msm_codec_conf[i].dev_name = NULL;
  6861. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  6862. msm_codec_conf[i].of_node =
  6863. wsa881x_dev_info[i].of_node;
  6864. }
  6865. for (i = 0; i < codec_aux_dev_cnt; i++) {
  6866. msm_aux_dev[wsa_max_devs + i].name = NULL;
  6867. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  6868. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  6869. aux_cdc_dev_info[i].of_node;
  6870. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  6871. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  6872. msm_codec_conf[wsa_max_devs + i].name_prefix =
  6873. NULL;
  6874. msm_codec_conf[wsa_max_devs + i].of_node =
  6875. aux_cdc_dev_info[i].of_node;
  6876. }
  6877. card->codec_conf = msm_codec_conf;
  6878. card->aux_dev = msm_aux_dev;
  6879. err:
  6880. return ret;
  6881. }
  6882. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6883. {
  6884. int count = 0;
  6885. u32 mi2s_master_slave[MI2S_MAX];
  6886. int ret = 0;
  6887. for (count = 0; count < MI2S_MAX; count++) {
  6888. mutex_init(&mi2s_intf_conf[count].lock);
  6889. mi2s_intf_conf[count].ref_cnt = 0;
  6890. }
  6891. ret = of_property_read_u32_array(pdev->dev.of_node,
  6892. "qcom,msm-mi2s-master",
  6893. mi2s_master_slave, MI2S_MAX);
  6894. if (ret) {
  6895. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6896. __func__);
  6897. } else {
  6898. for (count = 0; count < MI2S_MAX; count++) {
  6899. mi2s_intf_conf[count].msm_is_mi2s_master =
  6900. mi2s_master_slave[count];
  6901. }
  6902. }
  6903. }
  6904. static void msm_i2s_auxpcm_deinit(void)
  6905. {
  6906. int count = 0;
  6907. for (count = 0; count < MI2S_MAX; count++) {
  6908. mutex_destroy(&mi2s_intf_conf[count].lock);
  6909. mi2s_intf_conf[count].ref_cnt = 0;
  6910. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6911. }
  6912. }
  6913. static int kona_ssr_enable(struct device *dev, void *data)
  6914. {
  6915. struct platform_device *pdev = to_platform_device(dev);
  6916. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6917. int ret = 0;
  6918. if (!card) {
  6919. dev_err(dev, "%s: card is NULL\n", __func__);
  6920. ret = -EINVAL;
  6921. goto err;
  6922. }
  6923. if (!strcmp(card->name, "kona-stub-snd-card")) {
  6924. /* TODO */
  6925. dev_dbg(dev, "%s: TODO \n", __func__);
  6926. }
  6927. snd_soc_card_change_online_state(card, 1);
  6928. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  6929. err:
  6930. return ret;
  6931. }
  6932. static void kona_ssr_disable(struct device *dev, void *data)
  6933. {
  6934. struct platform_device *pdev = to_platform_device(dev);
  6935. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6936. if (!card) {
  6937. dev_err(dev, "%s: card is NULL\n", __func__);
  6938. return;
  6939. }
  6940. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  6941. snd_soc_card_change_online_state(card, 0);
  6942. if (!strcmp(card->name, "kona-stub-snd-card")) {
  6943. /* TODO */
  6944. dev_dbg(dev, "%s: TODO \n", __func__);
  6945. }
  6946. }
  6947. static const struct snd_event_ops kona_ssr_ops = {
  6948. .enable = kona_ssr_enable,
  6949. .disable = kona_ssr_disable,
  6950. };
  6951. static int msm_audio_ssr_compare(struct device *dev, void *data)
  6952. {
  6953. struct device_node *node = data;
  6954. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  6955. __func__, dev->of_node, node);
  6956. return (dev->of_node && dev->of_node == node);
  6957. }
  6958. static int msm_audio_ssr_register(struct device *dev)
  6959. {
  6960. struct device_node *np = dev->of_node;
  6961. struct snd_event_clients *ssr_clients = NULL;
  6962. struct device_node *node = NULL;
  6963. int ret = 0;
  6964. int i = 0;
  6965. for (i = 0; ; i++) {
  6966. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  6967. if (!node)
  6968. break;
  6969. snd_event_mstr_add_client(&ssr_clients,
  6970. msm_audio_ssr_compare, node);
  6971. }
  6972. ret = snd_event_master_register(dev, &kona_ssr_ops,
  6973. ssr_clients, NULL);
  6974. if (!ret)
  6975. snd_event_notify(dev, SND_EVENT_UP);
  6976. return ret;
  6977. }
  6978. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6979. {
  6980. struct snd_soc_card *card = NULL;
  6981. struct msm_asoc_mach_data *pdata = NULL;
  6982. const char *mbhc_audio_jack_type = NULL;
  6983. int ret = 0;
  6984. uint index = 0;
  6985. if (!pdev->dev.of_node) {
  6986. dev_err(&pdev->dev, "%s: No platform supplied from device tree\n", __func__);
  6987. return -EINVAL;
  6988. }
  6989. pdata = devm_kzalloc(&pdev->dev,
  6990. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6991. if (!pdata)
  6992. return -ENOMEM;
  6993. card = populate_snd_card_dailinks(&pdev->dev);
  6994. if (!card) {
  6995. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6996. ret = -EINVAL;
  6997. goto err;
  6998. }
  6999. card->dev = &pdev->dev;
  7000. platform_set_drvdata(pdev, card);
  7001. snd_soc_card_set_drvdata(card, pdata);
  7002. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  7003. if (ret) {
  7004. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  7005. __func__, ret);
  7006. goto err;
  7007. }
  7008. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  7009. if (ret) {
  7010. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  7011. __func__, ret);
  7012. goto err;
  7013. }
  7014. ret = msm_populate_dai_link_component_of_node(card);
  7015. if (ret) {
  7016. ret = -EPROBE_DEFER;
  7017. goto err;
  7018. }
  7019. ret = msm_init_aux_dev(pdev, card);
  7020. if (ret)
  7021. goto err;
  7022. ret = devm_snd_soc_register_card(&pdev->dev, card);
  7023. if (ret == -EPROBE_DEFER) {
  7024. if (codec_reg_done)
  7025. ret = -EINVAL;
  7026. goto err;
  7027. } else if (ret) {
  7028. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  7029. __func__, ret);
  7030. goto err;
  7031. }
  7032. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  7033. __func__, card->name);
  7034. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7035. "qcom,hph-en1-gpio", 0);
  7036. if (!pdata->hph_en1_gpio_p) {
  7037. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7038. __func__, "qcom,hph-en1-gpio",
  7039. pdev->dev.of_node->full_name);
  7040. }
  7041. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7042. "qcom,hph-en0-gpio", 0);
  7043. if (!pdata->hph_en0_gpio_p) {
  7044. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  7045. __func__, "qcom,hph-en0-gpio",
  7046. pdev->dev.of_node->full_name);
  7047. }
  7048. ret = of_property_read_string(pdev->dev.of_node,
  7049. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  7050. if (ret) {
  7051. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  7052. __func__, "qcom,mbhc-audio-jack-type",
  7053. pdev->dev.of_node->full_name);
  7054. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  7055. } else {
  7056. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  7057. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7058. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  7059. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  7060. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7061. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  7062. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  7063. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  7064. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  7065. } else {
  7066. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  7067. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  7068. }
  7069. }
  7070. /*
  7071. * Parse US-Euro gpio info from DT. Report no error if us-euro
  7072. * entry is not found in DT file as some targets do not support
  7073. * US-Euro detection
  7074. */
  7075. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7076. "qcom,us-euro-gpios", 0);
  7077. if (!pdata->us_euro_gpio_p) {
  7078. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  7079. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  7080. } else {
  7081. dev_dbg(&pdev->dev, "%s detected\n",
  7082. "qcom,us-euro-gpios");
  7083. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  7084. }
  7085. if (wcd_mbhc_cfg.enable_usbc_analog)
  7086. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  7087. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  7088. "fsa4480-i2c-handle", 0);
  7089. if (!pdata->fsa_handle)
  7090. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  7091. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  7092. msm_i2s_auxpcm_init(pdev);
  7093. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7094. "qcom,cdc-dmic01-gpios",
  7095. 0);
  7096. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7097. "qcom,cdc-dmic23-gpios",
  7098. 0);
  7099. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7100. "qcom,cdc-dmic45-gpios",
  7101. 0);
  7102. if (pdata->dmic45_gpio_p)
  7103. msm_cdc_pinctrl_set_wakeup_capable(pdata->dmic45_gpio_p, false);
  7104. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7105. "qcom,pri-mi2s-gpios", 0);
  7106. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7107. "qcom,sec-mi2s-gpios", 0);
  7108. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7109. "qcom,tert-mi2s-gpios", 0);
  7110. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7111. "qcom,quat-mi2s-gpios", 0);
  7112. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7113. "qcom,quin-mi2s-gpios", 0);
  7114. pdata->mi2s_gpio_p[SEN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7115. "qcom,sen-mi2s-gpios", 0);
  7116. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  7117. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  7118. ret = msm_audio_ssr_register(&pdev->dev);
  7119. if (ret)
  7120. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  7121. __func__, ret);
  7122. is_initial_boot = true;
  7123. return 0;
  7124. err:
  7125. devm_kfree(&pdev->dev, pdata);
  7126. return ret;
  7127. }
  7128. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7129. {
  7130. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7131. snd_event_master_deregister(&pdev->dev);
  7132. snd_soc_unregister_card(card);
  7133. msm_i2s_auxpcm_deinit();
  7134. return 0;
  7135. }
  7136. static struct platform_driver kona_asoc_machine_driver = {
  7137. .driver = {
  7138. .name = DRV_NAME,
  7139. .owner = THIS_MODULE,
  7140. .pm = &snd_soc_pm_ops,
  7141. .of_match_table = kona_asoc_machine_of_match,
  7142. .suppress_bind_attrs = true,
  7143. },
  7144. .probe = msm_asoc_machine_probe,
  7145. .remove = msm_asoc_machine_remove,
  7146. };
  7147. module_platform_driver(kona_asoc_machine_driver);
  7148. MODULE_DESCRIPTION("ALSA SoC msm");
  7149. MODULE_LICENSE("GPL v2");
  7150. MODULE_ALIAS("platform:" DRV_NAME);
  7151. MODULE_DEVICE_TABLE(of, kona_asoc_machine_of_match);