wcd9378.c 126 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <sound/soc.h>
  13. #include <sound/tlv.h>
  14. #include <soc/soundwire.h>
  15. #include <linux/regmap.h>
  16. #include <sound/soc.h>
  17. #include <sound/soc-dapm.h>
  18. #include <asoc/msm-cdc-pinctrl.h>
  19. #include <asoc/msm-cdc-supply.h>
  20. #include <bindings/audio-codec-port-types.h>
  21. #include <linux/qti-regmap-debugfs.h>
  22. #include "wcd9378-reg-masks.h"
  23. #include "wcd9378.h"
  24. #include "internal.h"
  25. #include "asoc/bolero-slave-internal.h"
  26. #define NUM_SWRS_DT_PARAMS 5
  27. #define WCD9378_MOBILE_MODE 0x01
  28. #define WCD9378_VERSION_1_0 1
  29. #define WCD9378_VERSION_ENTRY_SIZE 32
  30. #define EAR_RX_PATH_RX0 1
  31. #define AUX_RX_PATH_RX1 1
  32. #define SWR_BASECLK_19P2MHZ (0x01)
  33. #define SWR_BASECLK_24P576MHZ (0x03)
  34. #define SWR_BASECLK_22P5792MHZ (0x04)
  35. #define SWR_CLKSCALE_DIV2 (0x02)
  36. #define ADC_MODE_VAL_HIFI 0x01
  37. #define ADC_MODE_VAL_NORMAL 0x03
  38. #define ADC_MODE_VAL_LP 0x05
  39. #define PWR_LEVEL_LOHIFI_VAL 0x00
  40. #define PWR_LEVEL_LP_VAL 0x01
  41. #define PWR_LEVEL_HIFI_VAL 0x02
  42. #define PWR_LEVEL_ULP_VAL 0x03
  43. #define WCD9378_MBQ_ENABLE_MASK 0x2000
  44. #define MICB_USAGE_VAL_DISABLE 0x00
  45. #define MICB_USAGE_VAL_PULL_DOWN 0x01
  46. #define MICB_USAGE_VAL_1P2V 0x02
  47. #define MICB_USAGE_VAL_1P8VORPULLUP 0x03
  48. #define MICB_USAGE_VAL_2P5V 0x04
  49. #define MICB_USAGE_VAL_2P75V 0x05
  50. #define MICB_USAGE_VAL_2P2V 0xF0
  51. #define MICB_USAGE_VAL_2P7V 0xF1
  52. #define MICB_USAGE_VAL_2P8V 0xF2
  53. #define MICB_USAGE_VAL_MICB1_TABLE_VAL 0xF3
  54. #define MICB_USAGE_VAL_MICB2_TABLE_VAL 0xF4
  55. #define MICB_USAGE_VAL_MICB3_TABLE_VAL 0xF5
  56. #define MICB_NUM_MAX 3
  57. #define NUM_ATTEMPTS 20
  58. #define WCD9378_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  59. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  60. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  61. SNDRV_PCM_RATE_384000)
  62. /* Fractional Rates */
  63. #define WCD9378_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  64. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  65. #define WCD9378_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  66. SNDRV_PCM_FMTBIT_S24_LE |\
  67. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  68. #define WCD9378_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  69. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  70. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  71. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  72. .tlv.p = (tlv_array), \
  73. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  74. .put = wcd9378_ear_pa_put_gain, \
  75. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  76. #define WCD9378_AUX_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  77. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  78. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  79. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  80. .tlv.p = (tlv_array), \
  81. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  82. .put = wcd9378_aux_pa_put_gain, \
  83. .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  84. enum {
  85. CODEC_TX = 0,
  86. CODEC_RX,
  87. };
  88. enum {
  89. RX2_HP_MODE,
  90. RX2_NORMAL_MODE,
  91. };
  92. enum {
  93. WCD_ADC1 = 0,
  94. WCD_ADC2,
  95. WCD_ADC3,
  96. WCD_ADC4,
  97. ALLOW_BUCK_DISABLE,
  98. HPH_COMP_DELAY,
  99. HPH_PA_DELAY,
  100. AMIC2_BCS_ENABLE,
  101. WCD_SUPPLIES_LPM_MODE,
  102. WCD_ADC1_MODE,
  103. WCD_ADC2_MODE,
  104. WCD_ADC3_MODE,
  105. WCD_ADC4_MODE,
  106. WCD_AUX_EN,
  107. WCD_EAR_EN,
  108. };
  109. enum {
  110. NOSJ_SA_STEREO_3SM = 0,
  111. SJ_SA_AUX_2SM,
  112. NOSJ_SA_STEREO_3SM_1HDR,
  113. SJ_SA_AUX_2SM_1HDR,
  114. NOSJ_SA_EAR_3SM,
  115. SJ_SA_EAR_2SM,
  116. NOSJ_SA_EAR_3SM_1HDR,
  117. SJ_SA_EAR_2SM_1HDR,
  118. SJ_1HDR_SA_AUX_1SM,
  119. SJ_1HDR_SA_EAR_1SM,
  120. SJ_SA_STEREO_2SM,
  121. SJ_NOMIC_SA_EAR_3SM,
  122. SJ_NOMIC_SA_AUX_3SM,
  123. WCD_SYS_USAGE_MAX,
  124. };
  125. enum {
  126. NO_MICB_USED,
  127. MICB1,
  128. MICB2,
  129. MICB3,
  130. MICB_NUM,
  131. };
  132. enum {
  133. ADC_MODE_INVALID = 0,
  134. ADC_MODE_HIFI,
  135. ADC_MODE_NORMAL,
  136. ADC_MODE_LP,
  137. };
  138. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
  139. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(aux_pa_gain, 600, -600);
  140. static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
  141. static int wcd9378_reset(struct device *dev);
  142. static int wcd9378_reset_low(struct device *dev);
  143. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable);
  144. static void wcd9378_class_load(struct snd_soc_component *component);
  145. static const struct regmap_irq wcd9378_regmap_irqs[WCD9378_NUM_IRQS] = {
  146. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  147. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  148. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  149. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  150. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_SW_DET, 0, 0x10),
  151. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_OCP_INT, 0, 0x20),
  152. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_CNP_INT, 0, 0x40),
  153. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_OCP_INT, 0, 0x80),
  154. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_CNP_INT, 1, 0x01),
  155. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_CNP_INT, 1, 0x02),
  156. REGMAP_IRQ_REG(WCD9378_IRQ_EAR_SCD_INT, 1, 0x04),
  157. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_CNP_INT, 1, 0x08),
  158. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_SCD_INT, 1, 0x10),
  159. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  160. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  161. REGMAP_IRQ_REG(WCD9378_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  162. REGMAP_IRQ_REG(WCD9378_IRQ_LDORT_SCD_INT, 2, 0x01),
  163. REGMAP_IRQ_REG(WCD9378_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  164. REGMAP_IRQ_REG(WCD9378_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  165. REGMAP_IRQ_REG(WCD9378_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  166. };
  167. static int wcd9378_handle_post_irq(void *data)
  168. {
  169. struct wcd9378_priv *wcd9378 = data;
  170. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  171. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_1, &sts1);
  172. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_2, &sts2);
  173. regmap_read(wcd9378->regmap, SWRS_SCP_SDCA_INTSTAT_3, &sts3);
  174. wcd9378->tx_swr_dev->slave_irq_pending =
  175. ((sts1 || sts2 || !sts3) ? true : false);
  176. return IRQ_HANDLED;
  177. }
  178. static struct regmap_irq_chip wcd9378_regmap_irq_chip = {
  179. .name = "wcd9378",
  180. .irqs = wcd9378_regmap_irqs,
  181. .num_irqs = ARRAY_SIZE(wcd9378_regmap_irqs),
  182. .num_regs = 3,
  183. .status_base = SWRS_SCP_SDCA_INTSTAT_1,
  184. .unmask_base = SWRS_SCP_SDCA_INTMASK_1,
  185. .type_base = SWRS_SCP_SDCA_INTRTYPE_1,
  186. .ack_base = SWRS_SCP_SDCA_INTSTAT_1,
  187. .use_ack = 1,
  188. .runtime_pm = false,
  189. .handle_post_irq = wcd9378_handle_post_irq,
  190. .irq_drv_data = NULL,
  191. };
  192. static int wcd9378_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  193. {
  194. int ret = 0;
  195. int bank = 0;
  196. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  197. if (ret)
  198. return -EINVAL;
  199. return ((bank & 0x40) ? 1 : 0);
  200. }
  201. static int wcd9378_init_reg(struct snd_soc_component *component)
  202. {
  203. u32 val = 0;
  204. val = snd_soc_component_read(component, WCD9378_EFUSE_REG_16);
  205. if (!val)
  206. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  207. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  208. 0x03);
  209. else
  210. snd_soc_component_update_bits(component, WCD9378_MBHC_CTL_SPARE_1,
  211. WCD9378_MBHC_CTL_SPARE_1_BIASGEN_RES_CTRL_MASK,
  212. 0x01);
  213. /*0.9 Volts*/
  214. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  215. WCD9378_SLEEP_CTL_BG_CTL_MASK, 0x0E);
  216. /*BG_EN ENABLE*/
  217. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  218. WCD9378_SLEEP_CTL_BG_EN_MASK, 0x80);
  219. usleep_range(1000, 1010);
  220. /*LDOL_BG_SEL SLEEP_BG*/
  221. snd_soc_component_update_bits(component, WCD9378_SLEEP_CTL,
  222. WCD9378_SLEEP_CTL_LDOL_BG_SEL_MASK, 0x40);
  223. usleep_range(1000, 1010);
  224. /*Start up analog master bias. Sequence cannot change*/
  225. /*VBG_FINE_ADJ 0.005 Volts*/
  226. snd_soc_component_update_bits(component, WCD9378_BIAS_VBG_FINE_ADJ,
  227. WCD9378_BIAS_VBG_FINE_ADJ_VBG_FINE_ADJ_MASK, 0xB0);
  228. /*ANALOG_BIAS_EN ENABLE*/
  229. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  230. WCD9378_ANA_BIAS_ANALOG_BIAS_EN_MASK, 0x80);
  231. /*PRECHRG_EN ENABLE*/
  232. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  233. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x40);
  234. usleep_range(10000, 10010);
  235. /*PRECHRG_EN DISABLE*/
  236. snd_soc_component_update_bits(component, WCD9378_ANA_BIAS,
  237. WCD9378_ANA_BIAS_PRECHRG_EN_MASK, 0x00);
  238. /*End Analog Master Bias enable*/
  239. /*SEQ_BYPASS ENABLE*/
  240. snd_soc_component_update_bits(component, WCD9378_TX_COM_TXFE_DIV_CTL,
  241. WCD9378_TX_COM_TXFE_DIV_CTL_SEQ_BYPASS_MASK, 0x80);
  242. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  243. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL0,
  244. WCD9378_PDM_WD_CTL0_TIME_OUT_SEL_PCM_MASK, 0x10);
  245. /*TIME_OUT_SEL_PCM 160_CYCLES*/
  246. snd_soc_component_update_bits(component, WCD9378_PDM_WD_CTL1,
  247. WCD9378_PDM_WD_CTL1_TIME_OUT_SEL_PCM_MASK, 0x10);
  248. /*IBIAS_LDO_DRIVER 5e-06*/
  249. snd_soc_component_update_bits(component, WCD9378_MICB1_TEST_CTL_2,
  250. WCD9378_MICB1_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  251. /*IBIAS_LDO_DRIVER 5e-06*/
  252. snd_soc_component_update_bits(component, WCD9378_MICB3_TEST_CTL_2,
  253. WCD9378_MICB3_TEST_CTL_2_IBIAS_LDO_DRIVER_MASK, 0x01);
  254. /*SHORT_PROT_EN ENABLE*/
  255. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  256. WCD9378_ANA_EAR_SHORT_PROT_EN_MASK, 0x40);
  257. /*OCP FSM EN*/
  258. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  259. WCD9378_HPH_OCP_CTL_OCP_FSM_EN_MASK, 0x10);
  260. /*SCD OP EN*/
  261. snd_soc_component_update_bits(component, WCD9378_HPH_OCP_CTL,
  262. WCD9378_HPH_OCP_CTL_SCD_OP_EN_MASK, 0x02);
  263. /*OCP DET EN*/
  264. snd_soc_component_update_bits(component, WCD9378_HPH_L_TEST,
  265. WCD9378_HPH_L_TEST_OCP_DET_EN_MASK, 0x01);
  266. /*OCP DET EN*/
  267. snd_soc_component_update_bits(component, WCD9378_HPH_R_TEST,
  268. WCD9378_HPH_R_TEST_OCP_DET_EN_MASK, 0x01);
  269. /*HD2_RES_DIV_CTL_L 82.77*/
  270. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L,
  271. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L_MASK, 0x04);
  272. /*HD2_RES_DIV_CTL_R 82.77*/
  273. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R,
  274. WCD9378_HPH_NEW_INT_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R_MASK, 0x04);
  275. /*OPAMP_CHOP_CLK_EN DISABLE*/
  276. snd_soc_component_update_bits(component, WCD9378_HPH_RDAC_CLK_CTL1,
  277. WCD9378_HPH_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN_MASK, 0x00);
  278. /*RDAC_GAINCTL 0.55*/
  279. snd_soc_component_update_bits(component, WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL,
  280. WCD9378_HPH_NEW_INT_RDAC_GAIN_CTL_RDAC_GAINCTL_MASK, 0x50);
  281. /*HPH_UP_T0: 0.002*/
  282. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T0,
  283. WCD9378_HPH_UP_T0_HPH_UP_T0_MASK, 0x05);
  284. /*HPH_UP_T9: 0.002*/
  285. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T9,
  286. WCD9378_HPH_UP_T9_HPH_UP_T9_MASK, 0x05);
  287. /*HPH_DN_T0: 0.007*/
  288. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T0,
  289. WCD9378_HPH_DN_T0_HPH_DN_T0_MASK, 0x06);
  290. wcd9378_class_load(component);
  291. return 0;
  292. }
  293. static int wcd9378_set_port_params(struct snd_soc_component *component,
  294. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  295. u8 *ch_mask, u32 *ch_rate,
  296. u8 *port_type, u8 path)
  297. {
  298. int i, j;
  299. u8 num_ports = 0;
  300. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  301. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  302. switch (path) {
  303. case CODEC_RX:
  304. map = &wcd9378->rx_port_mapping;
  305. num_ports = wcd9378->num_rx_ports;
  306. break;
  307. case CODEC_TX:
  308. map = &wcd9378->tx_port_mapping;
  309. num_ports = wcd9378->num_tx_ports;
  310. break;
  311. default:
  312. dev_err(component->dev, "%s Invalid path selected %u\n",
  313. __func__, path);
  314. return -EINVAL;
  315. }
  316. for (i = 0; i <= num_ports; i++) {
  317. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  318. if ((*map)[i][j].slave_port_type == slv_prt_type)
  319. goto found;
  320. }
  321. }
  322. found:
  323. if (i > num_ports || j == MAX_CH_PER_PORT) {
  324. dev_err(component->dev, "%s Failed to find slave port for type %u\n",
  325. __func__, slv_prt_type);
  326. return -EINVAL;
  327. }
  328. *port_id = i;
  329. *num_ch = (*map)[i][j].num_ch;
  330. *ch_mask = (*map)[i][j].ch_mask;
  331. *ch_rate = (*map)[i][j].ch_rate;
  332. *port_type = (*map)[i][j].master_port_type;
  333. return 0;
  334. }
  335. static int wcd9378_parse_port_params(struct device *dev,
  336. char *prop, u8 path)
  337. {
  338. u32 *dt_array, map_size, max_uc;
  339. int ret = 0;
  340. u32 cnt = 0;
  341. u32 i, j;
  342. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  343. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  344. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  345. switch (path) {
  346. case CODEC_TX:
  347. map = &wcd9378->tx_port_params;
  348. map_uc = &wcd9378->swr_tx_port_params;
  349. break;
  350. default:
  351. ret = -EINVAL;
  352. goto err_port_map;
  353. }
  354. if (!of_find_property(dev->of_node, prop,
  355. &map_size)) {
  356. dev_err(dev, "missing port mapping prop %s\n", prop);
  357. ret = -EINVAL;
  358. goto err_port_map;
  359. }
  360. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  361. if (max_uc != SWR_UC_MAX) {
  362. dev_err(dev, "%s: port params not provided for all usecases\n",
  363. __func__);
  364. ret = -EINVAL;
  365. goto err_port_map;
  366. }
  367. dt_array = kzalloc(map_size, GFP_KERNEL);
  368. if (!dt_array) {
  369. ret = -ENOMEM;
  370. goto err_alloc;
  371. }
  372. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  373. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  374. if (ret) {
  375. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  376. __func__, prop);
  377. goto err_pdata_fail;
  378. }
  379. for (i = 0; i < max_uc; i++) {
  380. for (j = 0; j < SWR_NUM_PORTS; j++) {
  381. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  382. (*map)[i][j].offset1 = dt_array[cnt];
  383. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  384. }
  385. (*map_uc)[i].pp = &(*map)[i][0];
  386. }
  387. kfree(dt_array);
  388. return 0;
  389. err_pdata_fail:
  390. kfree(dt_array);
  391. err_alloc:
  392. err_port_map:
  393. return ret;
  394. }
  395. static int wcd9378_parse_port_mapping(struct device *dev,
  396. char *prop, u8 path)
  397. {
  398. u32 *dt_array, map_size, map_length;
  399. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  400. u32 slave_port_type, master_port_type;
  401. u32 i, ch_iter = 0;
  402. int ret = 0;
  403. u8 *num_ports = NULL;
  404. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  405. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  406. switch (path) {
  407. case CODEC_RX:
  408. map = &wcd9378->rx_port_mapping;
  409. num_ports = &wcd9378->num_rx_ports;
  410. break;
  411. case CODEC_TX:
  412. map = &wcd9378->tx_port_mapping;
  413. num_ports = &wcd9378->num_tx_ports;
  414. break;
  415. default:
  416. dev_err(dev, "%s Invalid path selected %u\n",
  417. __func__, path);
  418. return -EINVAL;
  419. }
  420. if (!of_find_property(dev->of_node, prop,
  421. &map_size)) {
  422. dev_err(dev, "missing port mapping prop %s\n", prop);
  423. ret = -EINVAL;
  424. goto err_port_map;
  425. }
  426. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  427. dt_array = kzalloc(map_size, GFP_KERNEL);
  428. if (!dt_array) {
  429. ret = -ENOMEM;
  430. goto err_alloc;
  431. }
  432. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  433. NUM_SWRS_DT_PARAMS * map_length);
  434. if (ret) {
  435. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  436. __func__, prop);
  437. goto err_pdata_fail;
  438. }
  439. for (i = 0; i < map_length; i++) {
  440. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  441. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  442. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  443. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  444. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  445. if (port_num != old_port_num)
  446. ch_iter = 0;
  447. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  448. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  449. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  450. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  451. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  452. old_port_num = port_num;
  453. }
  454. *num_ports = port_num;
  455. kfree(dt_array);
  456. return 0;
  457. err_pdata_fail:
  458. kfree(dt_array);
  459. err_alloc:
  460. err_port_map:
  461. return ret;
  462. }
  463. static int wcd9378_tx_connect_port(struct snd_soc_component *component,
  464. u8 slv_port_type, int clk_rate,
  465. u8 enable)
  466. {
  467. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  468. u8 port_id, num_ch, ch_mask;
  469. u8 ch_type = 0;
  470. u32 ch_rate;
  471. int slave_ch_idx;
  472. u8 num_port = 1;
  473. int ret = 0;
  474. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  475. &num_ch, &ch_mask, &ch_rate,
  476. &ch_type, CODEC_TX);
  477. if (ret)
  478. return ret;
  479. if (clk_rate)
  480. ch_rate = clk_rate;
  481. slave_ch_idx = wcd9378_slave_get_slave_ch_val(slv_port_type);
  482. if (slave_ch_idx != -EINVAL)
  483. ch_type = wcd9378->tx_master_ch_map[slave_ch_idx];
  484. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  485. __func__, slave_ch_idx, ch_type);
  486. if (enable)
  487. ret = swr_connect_port(wcd9378->tx_swr_dev, &port_id,
  488. num_port, &ch_mask, &ch_rate,
  489. &num_ch, &ch_type);
  490. else
  491. ret = swr_disconnect_port(wcd9378->tx_swr_dev, &port_id,
  492. num_port, &ch_mask, &ch_type);
  493. return ret;
  494. }
  495. static int wcd9378_rx_connect_port(struct snd_soc_component *component,
  496. u8 slv_port_type, u8 enable)
  497. {
  498. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  499. u8 port_id, num_ch, ch_mask, port_type;
  500. u32 ch_rate;
  501. u8 num_port = 1;
  502. int ret = 0;
  503. ret = wcd9378_set_port_params(component, slv_port_type, &port_id,
  504. &num_ch, &ch_mask, &ch_rate,
  505. &port_type, CODEC_RX);
  506. if (ret)
  507. return ret;
  508. if (enable)
  509. ret = swr_connect_port(wcd9378->rx_swr_dev, &port_id,
  510. num_port, &ch_mask, &ch_rate,
  511. &num_ch, &port_type);
  512. else
  513. ret = swr_disconnect_port(wcd9378->rx_swr_dev, &port_id,
  514. num_port, &ch_mask, &port_type);
  515. return ret;
  516. }
  517. static int wcd9378_enable_clsh(struct snd_soc_dapm_widget *w,
  518. struct snd_kcontrol *kcontrol,
  519. int event)
  520. {
  521. struct snd_soc_component *component =
  522. snd_soc_dapm_to_component(w->dapm);
  523. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  524. int mode = wcd9378->hph_mode;
  525. int ret = 0;
  526. int bank = 0;
  527. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  528. w->name, event);
  529. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  530. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  531. wcd9378_rx_connect_port(component, CLSH,
  532. SND_SOC_DAPM_EVENT_ON(event));
  533. }
  534. if (SND_SOC_DAPM_EVENT_OFF(event)) {
  535. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  536. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  537. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, false);
  538. ret = swr_slvdev_datapath_control(
  539. wcd9378->rx_swr_dev,
  540. wcd9378->rx_swr_dev->dev_num,
  541. false);
  542. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, false);
  543. }
  544. return ret;
  545. }
  546. static int wcd9378_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  547. struct snd_kcontrol *kcontrol,
  548. int event)
  549. {
  550. struct snd_soc_component *component =
  551. snd_soc_dapm_to_component(w->dapm);
  552. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  553. u32 dmic_clk_reg, dmic_clk_en_reg;
  554. s32 *dmic_clk_cnt;
  555. u8 dmic_ctl_shift = 0;
  556. u8 dmic_clk_shift = 0;
  557. u8 dmic_clk_mask = 0;
  558. u32 dmic2_left_en = 0;
  559. int ret = 0;
  560. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  561. w->name, event);
  562. switch (w->shift) {
  563. case 0:
  564. case 1:
  565. dmic_clk_cnt = &(wcd9378->dmic_0_1_clk_cnt);
  566. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  567. dmic_clk_en_reg = WCD9378_CDC_DMIC1_CTL;
  568. dmic_clk_mask = 0x0F;
  569. dmic_clk_shift = 0x00;
  570. dmic_ctl_shift = 0x00;
  571. break;
  572. case 2:
  573. dmic2_left_en = WCD9378_CDC_DMIC2_CTL;
  574. fallthrough;
  575. case 3:
  576. dmic_clk_cnt = &(wcd9378->dmic_2_3_clk_cnt);
  577. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_1_2;
  578. dmic_clk_en_reg = WCD9378_CDC_DMIC2_CTL;
  579. dmic_clk_mask = 0xF0;
  580. dmic_clk_shift = 0x04;
  581. dmic_ctl_shift = 0x01;
  582. break;
  583. case 4:
  584. case 5:
  585. dmic_clk_cnt = &(wcd9378->dmic_4_5_clk_cnt);
  586. dmic_clk_reg = WCD9378_CDC_DMIC_RATE_3_4;
  587. dmic_clk_en_reg = WCD9378_CDC_DMIC3_CTL;
  588. dmic_clk_mask = 0x0F;
  589. dmic_clk_shift = 0x00;
  590. dmic_ctl_shift = 0x02;
  591. break;
  592. default:
  593. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  594. __func__);
  595. return -EINVAL;
  596. };
  597. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  598. __func__, event, (w->shift + 1), *dmic_clk_cnt);
  599. switch (event) {
  600. case SND_SOC_DAPM_PRE_PMU:
  601. snd_soc_component_update_bits(component,
  602. WCD9378_CDC_AMIC_CTL,
  603. (0x01 << dmic_ctl_shift), 0x00);
  604. /* 250us sleep as per HW requirement */
  605. usleep_range(250, 260);
  606. if (dmic2_left_en)
  607. snd_soc_component_update_bits(component,
  608. dmic2_left_en, 0x80, 0x80);
  609. /* Setting DMIC clock rate to 2.4MHz */
  610. snd_soc_component_update_bits(component,
  611. dmic_clk_reg, dmic_clk_mask,
  612. (0x03 << dmic_clk_shift));
  613. snd_soc_component_update_bits(component,
  614. dmic_clk_en_reg, 0x08, 0x08);
  615. /* enable clock scaling */
  616. snd_soc_component_update_bits(component,
  617. WCD9378_CDC_DMIC_CTL, 0x06, 0x06);
  618. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  619. wcd9378->tx_swr_dev->dev_num,
  620. true);
  621. break;
  622. case SND_SOC_DAPM_POST_PMD:
  623. wcd9378_tx_connect_port(component, DMIC0 + (w->shift), 0,
  624. false);
  625. snd_soc_component_update_bits(component,
  626. WCD9378_CDC_AMIC_CTL,
  627. (0x01 << dmic_ctl_shift),
  628. (0x01 << dmic_ctl_shift));
  629. if (dmic2_left_en)
  630. snd_soc_component_update_bits(component,
  631. dmic2_left_en, 0x80, 0x00);
  632. snd_soc_component_update_bits(component,
  633. dmic_clk_en_reg, 0x08, 0x00);
  634. break;
  635. };
  636. return ret;
  637. }
  638. /*
  639. * wcd9378_get_micb_vout_ctl_val: converts micbias from volts to register value
  640. * @micb_mv: micbias in mv
  641. *
  642. * return register value converted
  643. */
  644. int wcd9378_get_micb_vout_ctl_val(u32 micb_mv)
  645. {
  646. /* min micbias voltage is 1V and maximum is 2.85V */
  647. if (micb_mv < 1000 || micb_mv > 2850) {
  648. pr_err("%s: unsupported micbias voltage\n", __func__);
  649. return -EINVAL;
  650. }
  651. return (micb_mv - 1000) / 50;
  652. }
  653. EXPORT_SYMBOL_GPL(wcd9378_get_micb_vout_ctl_val);
  654. /*
  655. * wcd9378_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  656. * @component: handle to snd_soc_component *
  657. * @req_volt: micbias voltage to be set
  658. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  659. *
  660. * return 0 if adjustment is success or error code in case of failure
  661. */
  662. static int wcd9378_micb_table_value_set(struct snd_soc_component *component,
  663. u32 micb_mv, int micb_num)
  664. {
  665. int vcout_ctl;
  666. switch (micb_mv) {
  667. case 2200:
  668. return MICB_USAGE_VAL_2P2V;
  669. case 2700:
  670. return MICB_USAGE_VAL_2P7V;
  671. case 2800:
  672. return MICB_USAGE_VAL_2P8V;
  673. default:
  674. vcout_ctl = wcd9378_get_micb_vout_ctl_val(micb_mv);
  675. if (micb_num == MIC_BIAS_1) {
  676. snd_soc_component_update_bits(component,
  677. WCD9378_MICB_REMAP_TABLE_VAL_3,
  678. WCD9378_MICB_REMAP_TABLE_VAL_3_MICB_REMAP_TABLE_VAL_3_MASK,
  679. vcout_ctl);
  680. return MICB_USAGE_VAL_MICB1_TABLE_VAL;
  681. } else if (micb_num == MIC_BIAS_2) {
  682. snd_soc_component_update_bits(component,
  683. WCD9378_MICB_REMAP_TABLE_VAL_4,
  684. WCD9378_MICB_REMAP_TABLE_VAL_4_MICB_REMAP_TABLE_VAL_4_MASK,
  685. vcout_ctl);
  686. return MICB_USAGE_VAL_MICB2_TABLE_VAL;
  687. } else if (micb_num == MIC_BIAS_3) {
  688. snd_soc_component_update_bits(component,
  689. WCD9378_MICB_REMAP_TABLE_VAL_5,
  690. WCD9378_MICB_REMAP_TABLE_VAL_5_MICB_REMAP_TABLE_VAL_5_MASK,
  691. vcout_ctl);
  692. return MICB_USAGE_VAL_MICB3_TABLE_VAL;
  693. }
  694. }
  695. return 0;
  696. }
  697. static int wcd9378_micb_usage_value_convert(struct snd_soc_component *component,
  698. u32 micb_mv, int micb_num)
  699. {
  700. switch (micb_mv) {
  701. case 0:
  702. return MICB_USAGE_VAL_PULL_DOWN;
  703. case 1200:
  704. return MICB_USAGE_VAL_1P2V;
  705. case 1800:
  706. return MICB_USAGE_VAL_1P8VORPULLUP;
  707. case 2500:
  708. return MICB_USAGE_VAL_2P5V;
  709. case 2750:
  710. return MICB_USAGE_VAL_2P75V;
  711. default:
  712. return wcd9378_micb_table_value_set(component, micb_mv, micb_num);
  713. }
  714. return MICB_USAGE_VAL_DISABLE;
  715. }
  716. int wcd9378_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  717. int req_volt, int micb_num)
  718. {
  719. struct wcd9378_priv *wcd9378 =
  720. snd_soc_component_get_drvdata(component);
  721. int micb_usage = 0, micb_mask = 0, req_vout_ctl;
  722. int sm_num = 0;
  723. struct wcd9378_pdata *pdata = NULL;
  724. pdata = dev_get_platdata(wcd9378->dev);
  725. if (wcd9378 == NULL) {
  726. dev_err(component->dev,
  727. "%s: wcd9378 private data is NULL\n", __func__);
  728. return -EINVAL;
  729. }
  730. for (sm_num = 0; sm_num < SIM_MIC_NUM; sm_num++)
  731. if (wcd9378->micb_sel[sm_num] == micb_num)
  732. break;
  733. if ((sm_num == SIM_MIC_NUM) && (micb_num != MIC_BIAS_2)) {
  734. pr_err("%s: cannot find the simple mic function which connect to micbias_%d\n",
  735. __func__, micb_num);
  736. return -EINVAL;
  737. }
  738. switch (sm_num) {
  739. case SIM_MIC0:
  740. micb_usage = WCD9378_IT11_USAGE;
  741. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  742. break;
  743. case SIM_MIC1:
  744. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  745. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  746. break;
  747. case SIM_MIC2:
  748. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  749. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  750. break;
  751. default:
  752. if (micb_num == MIC_BIAS_2) {
  753. micb_usage = WCD9378_IT31_MICB;
  754. micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
  755. }
  756. break;
  757. }
  758. mutex_lock(&wcd9378->micb_lock);
  759. req_vout_ctl =
  760. wcd9378_micb_usage_value_convert(component, req_volt, micb_num);
  761. snd_soc_component_update_bits(component,
  762. micb_usage, micb_mask, req_vout_ctl);
  763. mutex_unlock(&wcd9378->micb_lock);
  764. return 0;
  765. }
  766. EXPORT_SYMBOL_GPL(wcd9378_mbhc_micb_adjust_voltage);
  767. void wcd9378_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  768. bool bcs_disable)
  769. {
  770. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  771. if (wcd9378->update_wcd_event) {
  772. if (bcs_disable)
  773. wcd9378->update_wcd_event(wcd9378->handle,
  774. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  775. else
  776. wcd9378->update_wcd_event(wcd9378->handle,
  777. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  778. }
  779. }
  780. static int wcd9378_get_clk_rate(int mode)
  781. {
  782. int rate;
  783. switch (mode) {
  784. case ADC_MODE_LP:
  785. rate = SWR_CLK_RATE_4P8MHZ;
  786. break;
  787. case ADC_MODE_INVALID:
  788. case ADC_MODE_NORMAL:
  789. case ADC_MODE_HIFI:
  790. default:
  791. rate = SWR_CLK_RATE_9P6MHZ;
  792. break;
  793. }
  794. pr_debug("%s: mode: %d, rate: %d\n", __func__, mode, rate);
  795. return rate;
  796. }
  797. static int wcd9378_get_adc_mode_val(int mode)
  798. {
  799. int ret = 0;
  800. switch (mode) {
  801. case ADC_MODE_INVALID:
  802. case ADC_MODE_NORMAL:
  803. ret = ADC_MODE_VAL_NORMAL;
  804. break;
  805. case ADC_MODE_HIFI:
  806. ret = ADC_MODE_VAL_HIFI;
  807. break;
  808. case ADC_MODE_LP:
  809. ret = ADC_MODE_VAL_LP;
  810. break;
  811. default:
  812. ret = -EINVAL;
  813. pr_err("%s: invalid ADC mode value %d\n", __func__, mode);
  814. break;
  815. }
  816. return ret;
  817. }
  818. static int wcd9378_tx_sequencer_enable(struct snd_soc_dapm_widget *w,
  819. struct snd_kcontrol *kcontrol, int event)
  820. {
  821. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  822. struct wcd9378_priv *wcd9378 =
  823. snd_soc_component_get_drvdata(component);
  824. int mode_val = 0, bank = 0, ret = 0, rate = 0;
  825. int act_ps = 0;
  826. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->tx_swr_dev,
  827. wcd9378->tx_swr_dev->dev_num) ? 0 : 1);
  828. dev_dbg(component->dev, "%s wname: %s wshift: %d event: %d\n", __func__,
  829. w->name, w->shift, event);
  830. switch (event) {
  831. case SND_SOC_DAPM_PRE_PMU:
  832. mode_val = wcd9378_get_adc_mode_val(wcd9378->tx_mode[w->shift - ADC1]);
  833. if (mode_val < 0) {
  834. dev_dbg(component->dev,
  835. "%s: invalid mode, setting to normal mode\n",
  836. __func__);
  837. mode_val = ADC_MODE_VAL_NORMAL;
  838. }
  839. rate = wcd9378_get_clk_rate(wcd9378->tx_mode[w->shift - ADC1]);
  840. if (w->shift == ADC2 && !((snd_soc_component_read(component,
  841. WCD9378_TX_NEW_TX_CH12_MUX) &
  842. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_MASK) == 0x10)) {
  843. if (!wcd9378->bcs_dis) {
  844. wcd9378_tx_connect_port(component, MBHC,
  845. SWR_CLK_RATE_4P8MHZ, true);
  846. set_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  847. }
  848. }
  849. set_bit(w->shift - ADC1, &wcd9378->status_mask);
  850. wcd9378_tx_connect_port(component, w->shift, rate,
  851. true);
  852. if (wcd9378->va_amic_en)
  853. wcd9378_micbias_control(component, w->shift,
  854. MICB_PULLUP_ENABLE, true);
  855. else
  856. wcd9378_micbias_control(component, w->shift,
  857. MICB_ENABLE, true);
  858. switch (w->shift) {
  859. case ADC1:
  860. /*SMP MIC0 IT11 USAGE SET*/
  861. snd_soc_component_update_bits(component, WCD9378_IT11_USAGE,
  862. WCD9378_IT11_USAGE_IT11_USAGE_MASK, mode_val);
  863. /*Hold TXFE in Initialization During Startup*/
  864. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  865. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x40);
  866. /*Power up TX0 sequencer*/
  867. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  868. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  869. break;
  870. case ADC2:
  871. if (wcd9378->sjmic_support) {
  872. /*SMP JACK IT31 USAGE SET*/
  873. snd_soc_component_update_bits(component,
  874. WCD9378_IT31_USAGE,
  875. WCD9378_IT31_USAGE_IT31_USAGE_MASK, mode_val);
  876. /*Power up TX1 sequencer*/
  877. snd_soc_component_update_bits(component,
  878. WCD9378_PDE34_REQ_PS,
  879. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x00);
  880. } else {
  881. /*SMP MIC1 IT11 USAGE SET*/
  882. snd_soc_component_update_bits(component,
  883. WCD9378_SMP_MIC_CTRL1_IT11_USAGE,
  884. WCD9378_SMP_MIC_CTRL1_IT11_USAGE_IT11_USAGE_MASK,
  885. mode_val);
  886. /*Hold TXFE in Initialization During Startup*/
  887. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  888. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x20);
  889. /*Power up TX1 sequencer*/
  890. snd_soc_component_update_bits(component,
  891. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS,
  892. WCD9378_SMP_MIC_CTRL1_PDE11_REQ_PS_PDE11_REQ_PS_MASK,
  893. 0x00);
  894. }
  895. break;
  896. case ADC3:
  897. /*SMP MIC2 IT11 USAGE SET*/
  898. snd_soc_component_update_bits(component,
  899. WCD9378_SMP_MIC_CTRL2_IT11_USAGE,
  900. WCD9378_SMP_MIC_CTRL2_IT11_USAGE_IT11_USAGE_MASK,
  901. mode_val);
  902. /*Hold TXFE in Initialization During Startup*/
  903. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  904. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x40);
  905. /*Power up TX2 sequencer*/
  906. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS,
  907. WCD9378_SMP_MIC_CTRL2_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x00);
  908. break;
  909. default:
  910. break;
  911. }
  912. /*default delay 800us*/
  913. usleep_range(800, 810);
  914. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, true);
  915. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  916. wcd9378->tx_swr_dev->dev_num,
  917. true);
  918. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, true);
  919. switch (w->shift) {
  920. case ADC1:
  921. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  922. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  923. act_ps = snd_soc_component_read(component, WCD9378_PDE11_ACT_PS);
  924. if (act_ps)
  925. dev_dbg(component->dev, "%s: tx0 sequencer didnot power on, act_ps: 0x%0x\n",
  926. __func__, act_ps);
  927. else
  928. dev_dbg(component->dev, "%s: tx0 sequencer power on successful, act_ps: 0x%0x\n",
  929. __func__, act_ps);
  930. break;
  931. case ADC2:
  932. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  933. WCD9378_ANA_TX_CH2_HPF2_INIT_MASK, 0x00);
  934. if (wcd9378->sjmic_support)
  935. act_ps = snd_soc_component_read(component,
  936. WCD9378_PDE34_ACT_PS);
  937. else
  938. act_ps = snd_soc_component_read(component,
  939. WCD9378_SMP_MIC_CTRL1_PDE11_ACT_PS);
  940. if (act_ps)
  941. dev_dbg(component->dev, "%s: tx1 sequencer didnot power on, act_ps: 0x%0x\n",
  942. __func__, act_ps);
  943. else
  944. dev_dbg(component->dev, "%s: tx1 sequencer power on successful, act_ps: 0x%0x\n",
  945. __func__, act_ps);
  946. break;
  947. case ADC3:
  948. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  949. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  950. act_ps = snd_soc_component_read(component,
  951. WCD9378_SMP_MIC_CTRL2_PDE11_ACT_PS);
  952. if (act_ps)
  953. dev_dbg(component->dev, "%s: tx2 sequencer didnot power on, act_ps: 0x%0x\n",
  954. __func__, act_ps);
  955. else
  956. dev_dbg(component->dev, "%s: tx2 sequencer power on successful, act_ps: 0x%0x\n",
  957. __func__, act_ps);
  958. break;
  959. };
  960. break;
  961. case SND_SOC_DAPM_POST_PMD:
  962. wcd9378_tx_connect_port(component, w->shift, 0, false);
  963. if (w->shift == ADC2 &&
  964. test_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask)) {
  965. wcd9378_tx_connect_port(component, MBHC, 0,
  966. false);
  967. clear_bit(AMIC2_BCS_ENABLE, &wcd9378->status_mask);
  968. }
  969. switch (w->shift) {
  970. case ADC1:
  971. /*Normal TXFE Startup*/
  972. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  973. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  974. /*tear down TX0 sequencer*/
  975. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  976. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  977. break;
  978. case ADC2:
  979. /*tear down TX1 sequencer*/
  980. snd_soc_component_update_bits(component, WCD9378_PDE34_REQ_PS,
  981. WCD9378_PDE34_REQ_PS_PDE34_REQ_PS_MASK, 0x03);
  982. /*Normal TXFE Startup*/
  983. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH2,
  984. WCD9378_ANA_TX_CH2_HPF1_INIT_MASK, 0x00);
  985. /*tear down TX1 sequencer*/
  986. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  987. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  988. break;
  989. case ADC3:
  990. /*Normal TXFE Startup*/
  991. snd_soc_component_update_bits(component, WCD9378_ANA_TX_CH3_HPF,
  992. WCD9378_ANA_TX_CH3_HPF_HPF3_INIT_MASK, 0x00);
  993. /*tear down TX2 sequencer*/
  994. snd_soc_component_update_bits(component, WCD9378_PDE11_REQ_PS,
  995. WCD9378_PDE11_REQ_PS_PDE11_REQ_PS_MASK, 0x03);
  996. break;
  997. default:
  998. break;
  999. }
  1000. /*default delay 800us*/
  1001. usleep_range(800, 810);
  1002. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, TX_PATH, false);
  1003. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1004. wcd9378->tx_swr_dev->dev_num,
  1005. false);
  1006. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, TX_PATH, false);
  1007. if (wcd9378->va_amic_en)
  1008. wcd9378_micbias_control(component, w->shift,
  1009. MICB_PULLUP_DISABLE, true);
  1010. else
  1011. wcd9378_micbias_control(component, w->shift,
  1012. MICB_DISABLE, true);
  1013. break;
  1014. default:
  1015. break;
  1016. }
  1017. return ret;
  1018. }
  1019. static int wcd9378_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1020. struct snd_kcontrol *kcontrol,
  1021. int event)
  1022. {
  1023. struct snd_soc_component *component =
  1024. snd_soc_dapm_to_component(w->dapm);
  1025. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1026. int ret = 0;
  1027. switch (event) {
  1028. case SND_SOC_DAPM_PRE_PMU:
  1029. wcd9378_tx_connect_port(component, w->shift,
  1030. SWR_CLK_RATE_2P4MHZ, true);
  1031. break;
  1032. case SND_SOC_DAPM_POST_PMD:
  1033. ret = swr_slvdev_datapath_control(wcd9378->tx_swr_dev,
  1034. wcd9378->tx_swr_dev->dev_num,
  1035. false);
  1036. break;
  1037. };
  1038. return ret;
  1039. }
  1040. static int wcd9378_tx_num_get(struct snd_soc_component *component,
  1041. int micb_num)
  1042. {
  1043. int sm_num = 0;
  1044. struct wcd9378_priv *wcd9378 =
  1045. snd_soc_component_get_drvdata(component);
  1046. for (sm_num = SIM_MIC0; sm_num <= SIM_MIC2; sm_num++) {
  1047. if (wcd9378->micb_sel[sm_num] == micb_num) {
  1048. if (sm_num == SIM_MIC0)
  1049. return ADC1;
  1050. else if (sm_num == SIM_MIC1)
  1051. return ADC2;
  1052. else if (sm_num == SIM_MIC2)
  1053. return ADC3;
  1054. else
  1055. return -EINVAL;
  1056. }
  1057. }
  1058. return -EINVAL;
  1059. }
  1060. static int wcd9378_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  1061. struct snd_kcontrol *kcontrol,
  1062. int event)
  1063. {
  1064. struct snd_soc_component *component =
  1065. snd_soc_dapm_to_component(w->dapm);
  1066. int micb_num = 0, tx_num = 0;
  1067. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1068. __func__, w->name, event);
  1069. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  1070. micb_num = MIC_BIAS_1;
  1071. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  1072. micb_num = MIC_BIAS_2;
  1073. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  1074. micb_num = MIC_BIAS_3;
  1075. else
  1076. return -EINVAL;
  1077. tx_num = wcd9378_tx_num_get(component, micb_num);
  1078. if (tx_num < 0)
  1079. pr_err("%s: SM MB SEL should be set properly\n", __func__);
  1080. switch (event) {
  1081. case SND_SOC_DAPM_PRE_PMU:
  1082. wcd9378_micbias_control(component, tx_num,
  1083. MICB_ENABLE, true);
  1084. break;
  1085. case SND_SOC_DAPM_POST_PMU:
  1086. usleep_range(1000, 1100);
  1087. break;
  1088. case SND_SOC_DAPM_POST_PMD:
  1089. wcd9378_micbias_control(component, tx_num,
  1090. MICB_DISABLE, true);
  1091. break;
  1092. };
  1093. return 0;
  1094. }
  1095. static int wcd9378_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  1096. struct snd_kcontrol *kcontrol,
  1097. int event)
  1098. {
  1099. struct snd_soc_component *component =
  1100. snd_soc_dapm_to_component(w->dapm);
  1101. int micb_num = 0, tx_num = 0;
  1102. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  1103. __func__, w->name, event);
  1104. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  1105. micb_num = MIC_BIAS_1;
  1106. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  1107. micb_num = MIC_BIAS_2;
  1108. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  1109. micb_num = MIC_BIAS_3;
  1110. else
  1111. return -EINVAL;
  1112. tx_num = wcd9378_tx_num_get(component, micb_num);
  1113. if (tx_num < 0)
  1114. pr_err("%s: SM MB SEL should be set properly\n", __func__);
  1115. switch (event) {
  1116. case SND_SOC_DAPM_PRE_PMU:
  1117. wcd9378_micbias_control(component, tx_num,
  1118. MICB_PULLUP_ENABLE, true);
  1119. break;
  1120. case SND_SOC_DAPM_POST_PMU:
  1121. usleep_range(1000, 1100);
  1122. break;
  1123. case SND_SOC_DAPM_POST_PMD:
  1124. wcd9378_micbias_control(component, tx_num,
  1125. MICB_PULLUP_DISABLE, true);
  1126. break;
  1127. };
  1128. return 0;
  1129. }
  1130. /*
  1131. * wcd9378_soc_get_mbhc: get wcd9378_mbhc handle of corresponding component
  1132. * @component: handle to snd_soc_component *
  1133. *
  1134. * return wcd9378_mbhc handle or error code in case of failure
  1135. */
  1136. struct wcd9378_mbhc *wcd9378_soc_get_mbhc(struct snd_soc_component *component)
  1137. {
  1138. struct wcd9378_priv *wcd9378;
  1139. if (!component) {
  1140. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  1141. return NULL;
  1142. }
  1143. wcd9378 = snd_soc_component_get_drvdata(component);
  1144. if (!wcd9378) {
  1145. pr_err_ratelimited("%s: wcd9378 is NULL\n", __func__);
  1146. return NULL;
  1147. }
  1148. return wcd9378->mbhc;
  1149. }
  1150. EXPORT_SYMBOL_GPL(wcd9378_soc_get_mbhc);
  1151. static int wcd9378_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  1152. struct snd_kcontrol *kcontrol,
  1153. int event)
  1154. {
  1155. struct snd_soc_component *component =
  1156. snd_soc_dapm_to_component(w->dapm);
  1157. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1158. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1159. w->name, event);
  1160. switch (event) {
  1161. case SND_SOC_DAPM_PRE_PMU:
  1162. /*HPHL ENABLE*/
  1163. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1164. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x04);
  1165. wcd9378_rx_connect_port(component, HPH_L, true);
  1166. if (wcd9378->comp1_enable) {
  1167. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1168. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x02);
  1169. wcd9378_rx_connect_port(component, COMP_L, true);
  1170. }
  1171. if (wcd9378->update_wcd_event)
  1172. wcd9378->update_wcd_event(wcd9378->handle,
  1173. SLV_BOLERO_EVT_RX_MUTE,
  1174. (WCD_RX1 << 0x10));
  1175. break;
  1176. case SND_SOC_DAPM_POST_PMD:
  1177. /*HPHL DISABLE*/
  1178. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1179. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1180. wcd9378_rx_connect_port(component, HPH_L, false);
  1181. if (wcd9378->comp1_enable) {
  1182. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1183. WCD9378_CDC_COMP_CTL_0_HPHL_COMP_EN_MASK, 0x00);
  1184. wcd9378_rx_connect_port(component, COMP_R, false);
  1185. }
  1186. break;
  1187. default:
  1188. break;
  1189. };
  1190. return 0;
  1191. }
  1192. static int wcd9378_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  1193. struct snd_kcontrol *kcontrol,
  1194. int event)
  1195. {
  1196. struct snd_soc_component *component =
  1197. snd_soc_dapm_to_component(w->dapm);
  1198. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1199. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1200. w->name, event);
  1201. switch (event) {
  1202. case SND_SOC_DAPM_PRE_PMU:
  1203. /*HPHR ENABLE*/
  1204. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1205. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x08);
  1206. wcd9378_rx_connect_port(component, HPH_R, true);
  1207. if (wcd9378->comp2_enable) {
  1208. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1209. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x01);
  1210. wcd9378_rx_connect_port(component, COMP_R, true);
  1211. }
  1212. break;
  1213. case SND_SOC_DAPM_POST_PMD:
  1214. /*HPHR DISABLE*/
  1215. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1216. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK, 0x00);
  1217. wcd9378_rx_connect_port(component, HPH_R, false);
  1218. if (wcd9378->comp2_enable) {
  1219. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1220. WCD9378_CDC_COMP_CTL_0_HPHR_COMP_EN_MASK, 0x00);
  1221. wcd9378_rx_connect_port(component, COMP_R, false);
  1222. }
  1223. break;
  1224. default:
  1225. break;
  1226. };
  1227. return 0;
  1228. }
  1229. static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  1230. struct snd_kcontrol *kcontrol,
  1231. int event)
  1232. {
  1233. struct snd_soc_component *component =
  1234. snd_soc_dapm_to_component(w->dapm);
  1235. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1236. int bank = 0;
  1237. int act_ps = 0;
  1238. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1239. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1240. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1241. w->name, event);
  1242. switch (event) {
  1243. case SND_SOC_DAPM_PRE_PMU:
  1244. if (wcd9378->update_wcd_event)
  1245. wcd9378->update_wcd_event(wcd9378->handle,
  1246. SLV_BOLERO_EVT_RX_MUTE,
  1247. (WCD_RX1 << 0x10 | 0x01));
  1248. if (wcd9378->update_wcd_event)
  1249. wcd9378->update_wcd_event(wcd9378->handle,
  1250. SLV_BOLERO_EVT_RX_MUTE,
  1251. (WCD_RX1 << 0x10));
  1252. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1253. if (act_ps)
  1254. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1255. __func__, act_ps);
  1256. else
  1257. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1258. __func__, act_ps);
  1259. break;
  1260. case SND_SOC_DAPM_POST_PMD:
  1261. if (wcd9378->update_wcd_event)
  1262. wcd9378->update_wcd_event(wcd9378->handle,
  1263. SLV_BOLERO_EVT_RX_MUTE,
  1264. (WCD_RX1 << 0x10 | 0x1));
  1265. if (wcd9378->update_wcd_event && wcd9378->comp1_enable)
  1266. wcd9378->update_wcd_event(wcd9378->handle,
  1267. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1268. (WCD_RX1 << 0x10));
  1269. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1270. WCD_EVENT_POST_HPHL_PA_OFF,
  1271. &wcd9378->mbhc->wcd_mbhc);
  1272. break;
  1273. default:
  1274. break;
  1275. };
  1276. return 0;
  1277. }
  1278. static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  1279. struct snd_kcontrol *kcontrol,
  1280. int event)
  1281. {
  1282. struct snd_soc_component *component =
  1283. snd_soc_dapm_to_component(w->dapm);
  1284. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1285. int act_ps = 0;
  1286. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1287. w->name, event);
  1288. switch (event) {
  1289. case SND_SOC_DAPM_PRE_PMU:
  1290. if (wcd9378->update_wcd_event)
  1291. wcd9378->update_wcd_event(wcd9378->handle,
  1292. SLV_BOLERO_EVT_RX_MUTE,
  1293. (WCD_RX2 << 0x10 | 0x1));
  1294. if (wcd9378->update_wcd_event)
  1295. wcd9378->update_wcd_event(wcd9378->handle,
  1296. SLV_BOLERO_EVT_RX_MUTE,
  1297. (WCD_RX2 << 0x10));
  1298. act_ps = snd_soc_component_read(component, WCD9378_PDE47_ACT_PS);
  1299. if (act_ps)
  1300. dev_dbg(component->dev, "%s: hph sequencer didnot power on, act_ps: 0x%0x\n",
  1301. __func__, act_ps);
  1302. else
  1303. dev_dbg(component->dev, "%s: hph sequencer power on successful, act_ps: 0x%0x\n",
  1304. __func__, act_ps);
  1305. break;
  1306. case SND_SOC_DAPM_POST_PMD:
  1307. if (wcd9378->update_wcd_event)
  1308. wcd9378->update_wcd_event(wcd9378->handle,
  1309. SLV_BOLERO_EVT_RX_MUTE,
  1310. (WCD_RX2 << 0x10 | 0x1));
  1311. if (wcd9378->update_wcd_event && wcd9378->comp2_enable)
  1312. wcd9378->update_wcd_event(wcd9378->handle,
  1313. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  1314. (WCD_RX2 << 0x10));
  1315. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1316. WCD_EVENT_POST_HPHR_PA_OFF,
  1317. &wcd9378->mbhc->wcd_mbhc);
  1318. break;
  1319. default:
  1320. break;
  1321. };
  1322. return 0;
  1323. }
  1324. static int wcd9378_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1325. struct snd_kcontrol *kcontrol,
  1326. int event)
  1327. {
  1328. struct snd_soc_component *component =
  1329. snd_soc_dapm_to_component(w->dapm);
  1330. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1331. int ret = 0;
  1332. int bank = 0;
  1333. int act_ps = 0;
  1334. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1335. w->name, event);
  1336. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1337. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1338. switch (event) {
  1339. case SND_SOC_DAPM_PRE_PMU:
  1340. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1341. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1342. wcd9378->rx_swr_dev->dev_num,
  1343. true);
  1344. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1345. wcd9378->aux_rx_path =
  1346. (snd_soc_component_read(
  1347. component, WCD9378_CDC_HPH_GAIN_CTL) &
  1348. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK) >> 0x03;
  1349. if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
  1350. if (wcd9378->update_wcd_event)
  1351. wcd9378->update_wcd_event(wcd9378->handle,
  1352. SLV_BOLERO_EVT_RX_MUTE,
  1353. (WCD_RX2 << 0x10));
  1354. } else {
  1355. if (wcd9378->update_wcd_event)
  1356. wcd9378->update_wcd_event(wcd9378->handle,
  1357. SLV_BOLERO_EVT_RX_MUTE,
  1358. (WCD_RX3 << 0x10));
  1359. }
  1360. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1361. if (act_ps)
  1362. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1363. __func__, act_ps);
  1364. else
  1365. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1366. __func__, act_ps);
  1367. break;
  1368. case SND_SOC_DAPM_POST_PMD:
  1369. if (wcd9378->aux_rx_path & AUX_RX_PATH_RX1) {
  1370. if (wcd9378->update_wcd_event)
  1371. wcd9378->update_wcd_event(wcd9378->handle,
  1372. SLV_BOLERO_EVT_RX_MUTE,
  1373. (WCD_RX2 << 0x10 | 0x1));
  1374. } else {
  1375. if (wcd9378->update_wcd_event)
  1376. wcd9378->update_wcd_event(wcd9378->handle,
  1377. SLV_BOLERO_EVT_RX_MUTE,
  1378. (WCD_RX3 << 0x10 | 0x1));
  1379. }
  1380. break;
  1381. };
  1382. return ret;
  1383. }
  1384. static int wcd9378_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1385. struct snd_kcontrol *kcontrol,
  1386. int event)
  1387. {
  1388. struct snd_soc_component *component =
  1389. snd_soc_dapm_to_component(w->dapm);
  1390. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1391. int ret = 0, bank = 0;
  1392. int act_ps = 0;
  1393. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1394. w->name, event);
  1395. bank = (wcd9378_swr_slv_get_current_bank(wcd9378->rx_swr_dev,
  1396. wcd9378->rx_swr_dev->dev_num) ? 0 : 1);
  1397. switch (event) {
  1398. case SND_SOC_DAPM_PRE_PMU:
  1399. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1400. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1401. wcd9378->rx_swr_dev->dev_num,
  1402. true);
  1403. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1404. wcd9378->ear_rx_path =
  1405. (snd_soc_component_read(
  1406. component, WCD9378_CDC_HPH_GAIN_CTL) &
  1407. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK) >> 0x02;
  1408. if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
  1409. if (wcd9378->update_wcd_event)
  1410. wcd9378->update_wcd_event(wcd9378->handle,
  1411. SLV_BOLERO_EVT_RX_MUTE,
  1412. (WCD_RX1 << 0x10));
  1413. } else {
  1414. if (wcd9378->update_wcd_event)
  1415. wcd9378->update_wcd_event(wcd9378->handle,
  1416. SLV_BOLERO_EVT_RX_MUTE,
  1417. (WCD_RX3 << 0x10));
  1418. }
  1419. act_ps = snd_soc_component_read(component, WCD9378_PDE23_ACT_PS);
  1420. if (act_ps)
  1421. dev_dbg(component->dev, "%s: sa sequencer didnot power on, act_ps: 0x%0x\n",
  1422. __func__, act_ps);
  1423. else
  1424. dev_dbg(component->dev, "%s: sa sequencer power on successful, act_ps: 0x%0x\n",
  1425. __func__, act_ps);
  1426. break;
  1427. case SND_SOC_DAPM_POST_PMD:
  1428. if (wcd9378->ear_rx_path & EAR_RX_PATH_RX0) {
  1429. if (wcd9378->update_wcd_event)
  1430. wcd9378->update_wcd_event(wcd9378->handle,
  1431. SLV_BOLERO_EVT_RX_MUTE,
  1432. (WCD_RX1 << 0x10 | 0x1));
  1433. } else {
  1434. if (wcd9378->update_wcd_event)
  1435. wcd9378->update_wcd_event(wcd9378->handle,
  1436. SLV_BOLERO_EVT_RX_MUTE,
  1437. (WCD_RX3 << 0x10 | 0x1));
  1438. }
  1439. break;
  1440. };
  1441. return ret;
  1442. }
  1443. static int wcd9378_get_hph_pwr_level(int hph_mode)
  1444. {
  1445. switch (hph_mode) {
  1446. case CLS_H_LOHIFI:
  1447. case CLS_AB_LOHIFI:
  1448. return PWR_LEVEL_LOHIFI_VAL;
  1449. case CLS_H_LP:
  1450. case CLS_AB_LP:
  1451. return PWR_LEVEL_LP_VAL;
  1452. case CLS_H_HIFI:
  1453. case CLS_AB_HIFI:
  1454. return PWR_LEVEL_HIFI_VAL;
  1455. case CLS_H_ULP:
  1456. case CLS_AB:
  1457. case CLS_H_NORMAL:
  1458. default:
  1459. return PWR_LEVEL_ULP_VAL;
  1460. }
  1461. return PWR_LEVEL_ULP_VAL;
  1462. }
  1463. static void wcd9378_hph_set_channel_volume(struct snd_soc_component *component)
  1464. {
  1465. struct wcd9378_priv *wcd9378 =
  1466. snd_soc_component_get_drvdata(component);
  1467. if ((!wcd9378->comp1_enable) &&
  1468. (!wcd9378->comp2_enable)) {
  1469. dev_err(component->dev, "%s hph gainis 0x%0xd\n", __func__, wcd9378->hph_gain);
  1470. snd_soc_component_update_bits(component,
  1471. (WCD9378_FU42_CH_VOL_CH1 | WCD9378_MBQ_ENABLE_MASK),
  1472. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1473. wcd9378->hph_gain >> 8);
  1474. snd_soc_component_update_bits(component,
  1475. WCD9378_FU42_CH_VOL_CH1,
  1476. WCD9378_FU42_CH_VOL_CH1_FU42_CH_VOL_CH1_MASK,
  1477. wcd9378->hph_gain & 0x00ff);
  1478. snd_soc_component_update_bits(component,
  1479. (WCD9378_FU42_CH_VOL_CH2 | WCD9378_MBQ_ENABLE_MASK),
  1480. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1481. wcd9378->hph_gain >> 8);
  1482. snd_soc_component_update_bits(component,
  1483. WCD9378_FU42_CH_VOL_CH2,
  1484. WCD9378_FU42_CH_VOL_CH2_FU42_CH_VOL_CH2_MASK,
  1485. wcd9378->hph_gain & 0x00ff);
  1486. }
  1487. }
  1488. static int wcd9378_swr_slave_clk_set(struct device *dev, int bank, int path, bool enable)
  1489. {
  1490. u16 clk_scale_reg = 0;
  1491. u8 clk_rst = 0x00, scale_rst = 0x00;
  1492. u8 swr_base_clk = 0, swr_clk_scale = 0;
  1493. struct wcd9378_priv *wcd9378 = NULL;
  1494. struct swr_device *swr_dev = NULL;
  1495. wcd9378 = dev_get_drvdata(dev);
  1496. if (!wcd9378)
  1497. return -EINVAL;
  1498. if (path == RX_PATH) {
  1499. swr_dev = wcd9378->rx_swr_dev;
  1500. swr_base_clk = wcd9378->swr_base_clk;
  1501. swr_clk_scale = wcd9378->swr_clk_scale;
  1502. } else {
  1503. swr_dev = wcd9378->tx_swr_dev;
  1504. swr_base_clk = SWR_BASECLK_19P2MHZ;
  1505. swr_clk_scale = SWR_CLKSCALE_DIV2;
  1506. }
  1507. clk_scale_reg = (bank ? SWRS_SCP_BUSCLOCK_SCALE_BANK1 :
  1508. SWRS_SCP_BUSCLOCK_SCALE_BANK0);
  1509. if (enable) {
  1510. swr_write(swr_dev, swr_dev->dev_num,
  1511. SWRS_SCP_BASE_CLK_BASE, &swr_base_clk);
  1512. swr_write(swr_dev, swr_dev->dev_num,
  1513. clk_scale_reg, &swr_clk_scale);
  1514. } else {
  1515. swr_write(swr_dev, swr_dev->dev_num,
  1516. SWRS_SCP_BASE_CLK_BASE, &clk_rst);
  1517. swr_write(swr_dev, swr_dev->dev_num,
  1518. clk_scale_reg, &scale_rst);
  1519. }
  1520. return 0;
  1521. }
  1522. static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
  1523. struct snd_kcontrol *kcontrol, int event)
  1524. {
  1525. struct snd_soc_component *component =
  1526. snd_soc_dapm_to_component(w->dapm);
  1527. struct wcd9378_priv *wcd9378 =
  1528. snd_soc_component_get_drvdata(component);
  1529. int power_level, bank = 0;
  1530. int ret = 0;
  1531. struct swr_device *swr_dev = wcd9378->tx_swr_dev;
  1532. u8 scp_commit_val = 0x2;
  1533. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1534. w->name, event);
  1535. switch (event) {
  1536. case SND_SOC_DAPM_PRE_PMU:
  1537. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable)) {
  1538. snd_soc_component_update_bits(component, WCD9378_HPH_UP_T7,
  1539. WCD9378_HPH_UP_T7_HPH_UP_T7_MASK, 0x07);
  1540. snd_soc_component_update_bits(component, WCD9378_HPH_DN_T1,
  1541. WCD9378_HPH_DN_T1_HPH_DN_T1_MASK, 0x07);
  1542. }
  1543. if ((wcd9378->hph_mode == CLS_AB) ||
  1544. (wcd9378->hph_mode == CLS_AB_HIFI) ||
  1545. (wcd9378->hph_mode == CLS_AB_LP) ||
  1546. (wcd9378->hph_mode == CLS_AB_LOHIFI))
  1547. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1548. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1549. /*GET HPH_MODE*/
  1550. power_level = wcd9378_get_hph_pwr_level(wcd9378->hph_mode);
  1551. /*SET HPH_MODE*/
  1552. snd_soc_component_update_bits(component, WCD9378_IT41_USAGE,
  1553. WCD9378_IT41_USAGE_IT41_USAGE_MASK, power_level);
  1554. /*TURN ON HPH SEQUENCER*/
  1555. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1556. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x00);
  1557. /*TBD: SET SDCA GAIN, NEED CHECK THE LOGIC*/
  1558. wcd9378_hph_set_channel_volume(component);
  1559. if ((!wcd9378->comp1_enable) || (!wcd9378->comp2_enable))
  1560. /*PA delay is 22400us*/
  1561. usleep_range(22500, 22510);
  1562. else
  1563. /*COMP delay is 9400us*/
  1564. usleep_range(9500, 9510);
  1565. /*RX0 unmute*/
  1566. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1567. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x00);
  1568. /*RX1 unmute*/
  1569. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1570. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
  1571. swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
  1572. wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
  1573. ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
  1574. wcd9378->rx_swr_dev->dev_num,
  1575. true);
  1576. wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
  1577. break;
  1578. case SND_SOC_DAPM_POST_PMD:
  1579. /*RX0 mute*/
  1580. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH1,
  1581. WCD9378_FU42_MUTE_CH1_FU42_MUTE_CH1_MASK, 0x01);
  1582. /*RX1 mute*/
  1583. snd_soc_component_update_bits(component, WCD9378_FU42_MUTE_CH2,
  1584. WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x01);
  1585. /*TEAR DOWN HPH SEQUENCER*/
  1586. snd_soc_component_update_bits(component, WCD9378_PDE47_REQ_PS,
  1587. WCD9378_PDE47_REQ_PS_PDE47_REQ_PS_MASK, 0x03);
  1588. if (!wcd9378->comp1_enable || !wcd9378->comp2_enable)
  1589. /*PA delay is 24250us*/
  1590. usleep_range(24300, 24310);
  1591. else
  1592. /*COMP delay is 11250us*/
  1593. usleep_range(11300, 11310);
  1594. break;
  1595. default:
  1596. break;
  1597. };
  1598. return ret;
  1599. }
  1600. static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  1601. struct snd_kcontrol *kcontrol,
  1602. int event)
  1603. {
  1604. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1605. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1606. int ear_rx0 = 0;
  1607. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1608. w->name, event);
  1609. ear_rx0 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
  1610. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK;
  1611. switch (event) {
  1612. case SND_SOC_DAPM_PRE_PMU:
  1613. /*CHECK IF EAR CONNET TO RX2*/
  1614. if (!ear_rx0) {
  1615. pr_debug("%s: ear rx2 enter\n", __func__);
  1616. /*FORCE CLASS_AB EN*/
  1617. snd_soc_component_update_bits(component, WCD9378_SEQ_OVRRIDE_CTL0,
  1618. WCD9378_SEQ_OVRRIDE_CTL0_CLASSAB_EN_OVR_MASK, 0x20);
  1619. snd_soc_component_update_bits(component, WCD9378_CP_CP_DTOP_CTRL_14,
  1620. WCD9378_CP_CP_DTOP_CTRL_14_OVERRIDE_VREF_MASK, 0x80);
  1621. /*RX2 ENABLE*/
  1622. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1623. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
  1624. if (wcd9378->rx2_clk_mode)
  1625. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1626. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1627. wcd9378_rx_connect_port(component, LO, true);
  1628. } else {
  1629. pr_debug("%s: ear rx0 enter\n", __func__);
  1630. if (wcd9378->comp1_enable) {
  1631. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1632. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x04);
  1633. wcd9378_rx_connect_port(component, COMP_L, true);
  1634. }
  1635. wcd9378_rx_connect_port(component, HPH_L, true);
  1636. }
  1637. break;
  1638. case SND_SOC_DAPM_POST_PMD:
  1639. if (ear_rx0) {
  1640. /*RX0 DISABLE*/
  1641. snd_soc_component_update_bits(component, WCD9378_CDC_HPH_GAIN_CTL,
  1642. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_MASK, 0x00);
  1643. wcd9378_rx_connect_port(component, HPH_L, false);
  1644. if (wcd9378->comp1_enable) {
  1645. snd_soc_component_update_bits(component, WCD9378_CDC_COMP_CTL_0,
  1646. WCD9378_CDC_COMP_CTL_0_EAR_COMP_EN_MASK, 0x00);
  1647. wcd9378_rx_connect_port(component, COMP_L, false);
  1648. }
  1649. } else {
  1650. /*RX1 DISABLE*/
  1651. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1652. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
  1653. wcd9378_rx_connect_port(component, LO, false);
  1654. }
  1655. break;
  1656. };
  1657. return 0;
  1658. }
  1659. static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  1660. struct snd_kcontrol *kcontrol,
  1661. int event)
  1662. {
  1663. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  1664. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  1665. int aux_rx1 = 0;
  1666. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1667. w->name, event);
  1668. aux_rx1 = snd_soc_component_read(component, WCD9378_CDC_HPH_GAIN_CTL) &
  1669. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_MASK;
  1670. switch (event) {
  1671. case SND_SOC_DAPM_PRE_PMU:
  1672. if (aux_rx1) {
  1673. wcd9378_rx_connect_port(component, HPH_R, true);
  1674. } else {
  1675. /*RX2 ENABLE*/
  1676. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1677. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x01);
  1678. if (wcd9378->rx2_clk_mode)
  1679. snd_soc_component_update_bits(component, WCD9378_CDC_PATH_MODE,
  1680. WCD9378_CDC_PATH_MODE_RX2_CLK_RATE_MASK, 0x40);
  1681. wcd9378_rx_connect_port(component, LO, true);
  1682. }
  1683. break;
  1684. case SND_SOC_DAPM_POST_PMD:
  1685. if (aux_rx1) {
  1686. wcd9378_rx_connect_port(component, HPH_R, false);
  1687. } else {
  1688. snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
  1689. WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
  1690. wcd9378_rx_connect_port(component, LO, false);
  1691. }
  1692. break;
  1693. };
  1694. return 0;
  1695. }
  1696. static int wcd9378_sa_sequencer_enable(struct snd_soc_dapm_widget *w,
  1697. struct snd_kcontrol *kcontrol, int event)
  1698. {
  1699. struct snd_soc_component *component =
  1700. snd_soc_dapm_to_component(w->dapm);
  1701. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1702. w->name, event);
  1703. switch (event) {
  1704. case SND_SOC_DAPM_PRE_PMU:
  1705. /*TURN ON AMP SEQUENCER*/
  1706. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1707. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x00);
  1708. /*default delay 8550us*/
  1709. usleep_range(8600, 8610);
  1710. /*FU23 UNMUTE*/
  1711. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1712. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x00);
  1713. break;
  1714. case SND_SOC_DAPM_POST_PMD:
  1715. /*FU23 MUTE*/
  1716. snd_soc_component_update_bits(component, WCD9378_FU23_MUTE,
  1717. WCD9378_FU23_MUTE_FU23_MUTE_MASK, 0x01);
  1718. /*TEAR DOWN AMP SEQUENCER*/
  1719. snd_soc_component_update_bits(component, WCD9378_PDE23_REQ_PS,
  1720. WCD9378_PDE23_REQ_PS_PDE23_REQ_PS_MASK, 0x03);
  1721. /*default delay 1530us*/
  1722. usleep_range(15400, 15410);
  1723. break;
  1724. default:
  1725. break;
  1726. };
  1727. return 0;
  1728. }
  1729. int wcd9378_micbias_control(struct snd_soc_component *component,
  1730. unsigned char tx_path, int req, bool is_dapm)
  1731. {
  1732. struct wcd9378_priv *wcd9378 =
  1733. snd_soc_component_get_drvdata(component);
  1734. struct wcd9378_pdata *pdata =
  1735. dev_get_platdata(wcd9378->dev);
  1736. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  1737. int micb_num = 0, micb_usage = 0, micb_mask = 0, micb_usage_val = 0;
  1738. int pre_off_event = 0, post_off_event = 0;
  1739. int post_on_event = 0, post_dapm_off = 0;
  1740. int post_dapm_on = 0;
  1741. int pull_up_mask = 0, pull_up_en = 0;
  1742. int micb_index = 0, ret = 0;
  1743. switch (tx_path) {
  1744. case ADC1:
  1745. micb_num = wcd9378->micb_sel[0];
  1746. micb_usage = WCD9378_IT11_MICB;
  1747. micb_mask = WCD9378_IT11_MICB_IT11_MICB_MASK;
  1748. break;
  1749. case ADC2:
  1750. if (wcd9378->sjmic_support) {
  1751. micb_num = MIC_BIAS_2;
  1752. micb_usage = WCD9378_IT31_MICB;
  1753. micb_mask = WCD9378_IT31_MICB_IT31_MICB_MASK;
  1754. } else {
  1755. micb_num = wcd9378->micb_sel[1];
  1756. micb_usage = WCD9378_SMP_MIC_CTRL1_IT11_MICB;
  1757. micb_mask = WCD9378_SMP_MIC_CTRL1_IT11_MICB_IT11_MICB_MASK;
  1758. }
  1759. break;
  1760. case ADC3:
  1761. micb_num = wcd9378->micb_sel[2];
  1762. micb_usage = WCD9378_SMP_MIC_CTRL2_IT11_MICB;
  1763. micb_mask = WCD9378_SMP_MIC_CTRL2_IT11_MICB_IT11_MICB_MASK;
  1764. break;
  1765. default:
  1766. pr_err("%s: unsupport tx path\n", __func__);
  1767. return -EINVAL;
  1768. }
  1769. switch (micb_num) {
  1770. case MIC_BIAS_1:
  1771. pull_up_mask = WCD9378_MB_PULLUP_EN_MB1_1P8V_OR_PULLUP_SEL_MASK;
  1772. pull_up_en = 0x01;
  1773. micb_usage_val = mb->micb1_usage_val;
  1774. break;
  1775. case MIC_BIAS_2:
  1776. pull_up_mask = WCD9378_MB_PULLUP_EN_MB2_1P8V_OR_PULLUP_SEL_MASK;
  1777. pull_up_en = 0x02;
  1778. micb_usage_val = mb->micb2_usage_val;
  1779. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1780. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1781. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1782. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1783. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1784. break;
  1785. case MIC_BIAS_3:
  1786. pull_up_mask = WCD9378_MB_PULLUP_EN_MB3_1P8V_OR_PULLUP_SEL_MASK;
  1787. pull_up_en = 0x04;
  1788. micb_usage_val = mb->micb3_usage_val;
  1789. break;
  1790. default:
  1791. dev_err(component->dev, "%s: Invalid micbias number: %d\n",
  1792. __func__, micb_num);
  1793. return -EINVAL;
  1794. }
  1795. mutex_lock(&wcd9378->micb_lock);
  1796. micb_index = micb_num - 1;
  1797. switch (req) {
  1798. case MICB_PULLUP_ENABLE:
  1799. wcd9378->pullup_ref[micb_index]++;
  1800. if ((wcd9378->pullup_ref[micb_index] == 1) &&
  1801. (wcd9378->micb_ref[micb_index] == 0)) {
  1802. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1803. pull_up_mask, pull_up_en);
  1804. snd_soc_component_update_bits(component,
  1805. micb_usage, micb_mask, 0x03);
  1806. }
  1807. break;
  1808. case MICB_PULLUP_DISABLE:
  1809. if (wcd9378->pullup_ref[micb_index] > 0)
  1810. wcd9378->pullup_ref[micb_index]--;
  1811. if ((wcd9378->pullup_ref[micb_index] == 0) &&
  1812. (wcd9378->micb_ref[micb_index] == 0))
  1813. snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
  1814. break;
  1815. case MICB_ENABLE:
  1816. dev_dbg(component->dev, "%s: micbias enable enter\n",
  1817. __func__);
  1818. if (!wcd9378->dev_up) {
  1819. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1820. __func__, req);
  1821. ret = -ENODEV;
  1822. goto done;
  1823. }
  1824. wcd9378->micb_ref[micb_index]++;
  1825. if (wcd9378->micb_ref[micb_index] == 1) {
  1826. dev_dbg(component->dev, "%s: enable micbias, micb_usage:0x%0x, val:0x%0x\n",
  1827. __func__, micb_usage, micb_usage_val);
  1828. snd_soc_component_update_bits(component,
  1829. micb_usage, micb_mask, micb_usage_val);
  1830. if (post_on_event)
  1831. blocking_notifier_call_chain(
  1832. &wcd9378->mbhc->notifier,
  1833. post_on_event,
  1834. &wcd9378->mbhc->wcd_mbhc);
  1835. }
  1836. if (is_dapm && post_dapm_on && wcd9378->mbhc)
  1837. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1838. post_dapm_on,
  1839. &wcd9378->mbhc->wcd_mbhc);
  1840. break;
  1841. case MICB_DISABLE:
  1842. if (wcd9378->micb_ref[micb_index] > 0)
  1843. wcd9378->micb_ref[micb_index]--;
  1844. if ((wcd9378->micb_ref[micb_index] == 0) &&
  1845. (wcd9378->pullup_ref[micb_index] > 0)) {
  1846. /*PULL UP?*/
  1847. snd_soc_component_update_bits(component, WCD9378_MB_PULLUP_EN,
  1848. pull_up_mask, pull_up_en);
  1849. snd_soc_component_update_bits(component, micb_usage,
  1850. micb_mask, 0x03);
  1851. } else if ((wcd9378->micb_ref[micb_index] == 0) &&
  1852. (wcd9378->pullup_ref[micb_index] == 0)) {
  1853. if (pre_off_event && wcd9378->mbhc)
  1854. blocking_notifier_call_chain(
  1855. &wcd9378->mbhc->notifier,
  1856. pre_off_event,
  1857. &wcd9378->mbhc->wcd_mbhc);
  1858. snd_soc_component_update_bits(component, micb_usage,
  1859. micb_mask, 0x00);
  1860. if (post_off_event && wcd9378->mbhc)
  1861. blocking_notifier_call_chain(
  1862. &wcd9378->mbhc->notifier,
  1863. post_off_event,
  1864. &wcd9378->mbhc->wcd_mbhc);
  1865. }
  1866. if (is_dapm && post_dapm_off && wcd9378->mbhc)
  1867. blocking_notifier_call_chain(&wcd9378->mbhc->notifier,
  1868. post_dapm_off,
  1869. &wcd9378->mbhc->wcd_mbhc);
  1870. break;
  1871. default:
  1872. dev_err(component->dev, "%s: Invalid req event: %d\n",
  1873. __func__, req);
  1874. return -EINVAL;
  1875. }
  1876. dev_dbg(component->dev,
  1877. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1878. __func__, micb_num, wcd9378->micb_ref[micb_index],
  1879. wcd9378->pullup_ref[micb_index]);
  1880. done:
  1881. mutex_unlock(&wcd9378->micb_lock);
  1882. return ret;
  1883. }
  1884. EXPORT_SYMBOL_GPL(wcd9378_micbias_control);
  1885. static int wcd9378_get_logical_addr(struct swr_device *swr_dev)
  1886. {
  1887. int ret = 0;
  1888. uint8_t devnum = 0;
  1889. int num_retry = NUM_ATTEMPTS;
  1890. do {
  1891. /* retry after 4ms */
  1892. usleep_range(4000, 4010);
  1893. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1894. } while (ret && --num_retry);
  1895. if (ret)
  1896. dev_err(&swr_dev->dev,
  1897. "%s get devnum %d for dev addr %llx failed\n",
  1898. __func__, devnum, swr_dev->addr);
  1899. swr_dev->dev_num = devnum;
  1900. return 0;
  1901. }
  1902. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1903. struct wcd_mbhc_config *mbhc_cfg)
  1904. {
  1905. if (mbhc_cfg->enable_usbc_analog) {
  1906. if (!(snd_soc_component_read(component, WCD9378_ANA_MBHC_MECH)
  1907. & 0x20))
  1908. return true;
  1909. }
  1910. return false;
  1911. }
  1912. int wcd9378_swr_dmic_register_notifier(struct snd_soc_component *component,
  1913. struct notifier_block *nblock,
  1914. bool enable)
  1915. {
  1916. struct wcd9378_priv *wcd9378_priv = NULL;
  1917. if (component == NULL) {
  1918. pr_err_ratelimited("%s: wcd9378 component is NULL\n", __func__);
  1919. return -EINVAL;
  1920. }
  1921. wcd9378_priv = snd_soc_component_get_drvdata(component);
  1922. wcd9378_priv->notify_swr_dmic = enable;
  1923. if (enable)
  1924. return blocking_notifier_chain_register(&wcd9378_priv->notifier,
  1925. nblock);
  1926. else
  1927. return blocking_notifier_chain_unregister(
  1928. &wcd9378_priv->notifier, nblock);
  1929. }
  1930. EXPORT_SYMBOL_GPL(wcd9378_swr_dmic_register_notifier);
  1931. static int wcd9378_event_notify(struct notifier_block *block,
  1932. unsigned long val,
  1933. void *data)
  1934. {
  1935. u16 event = (val & 0xffff);
  1936. int ret = 0;
  1937. struct wcd9378_priv *wcd9378 = dev_get_drvdata((struct device *)data);
  1938. struct snd_soc_component *component = wcd9378->component;
  1939. struct wcd_mbhc *mbhc;
  1940. int rx_clk_type;
  1941. switch (event) {
  1942. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  1943. if (test_bit(WCD_ADC1, &wcd9378->status_mask)) {
  1944. snd_soc_component_update_bits(component,
  1945. WCD9378_ANA_TX_CH2, 0x40, 0x00);
  1946. set_bit(WCD_ADC1_MODE, &wcd9378->status_mask);
  1947. clear_bit(WCD_ADC1, &wcd9378->status_mask);
  1948. }
  1949. if (test_bit(WCD_ADC2, &wcd9378->status_mask)) {
  1950. snd_soc_component_update_bits(component,
  1951. WCD9378_ANA_TX_CH2, 0x20, 0x00);
  1952. set_bit(WCD_ADC2_MODE, &wcd9378->status_mask);
  1953. clear_bit(WCD_ADC2, &wcd9378->status_mask);
  1954. }
  1955. if (test_bit(WCD_ADC3, &wcd9378->status_mask)) {
  1956. snd_soc_component_update_bits(component,
  1957. WCD9378_ANA_TX_CH3_HPF, 0x40, 0x00);
  1958. set_bit(WCD_ADC3_MODE, &wcd9378->status_mask);
  1959. clear_bit(WCD_ADC3, &wcd9378->status_mask);
  1960. }
  1961. break;
  1962. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1963. snd_soc_component_update_bits(component, WCD9378_ANA_HPH,
  1964. 0xC0, 0x00);
  1965. snd_soc_component_update_bits(component, WCD9378_ANA_EAR,
  1966. 0x80, 0x00);
  1967. snd_soc_component_update_bits(component, WCD9378_AUX_AUXPA,
  1968. 0x80, 0x00);
  1969. break;
  1970. case BOLERO_SLV_EVT_SSR_DOWN:
  1971. wcd9378->dev_up = false;
  1972. if (wcd9378->notify_swr_dmic)
  1973. blocking_notifier_call_chain(&wcd9378->notifier,
  1974. WCD9378_EVT_SSR_DOWN,
  1975. NULL);
  1976. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = true;
  1977. mbhc = &wcd9378->mbhc->wcd_mbhc;
  1978. wcd9378->usbc_hs_status = get_usbc_hs_status(component,
  1979. mbhc->mbhc_cfg);
  1980. wcd9378_mbhc_ssr_down(wcd9378->mbhc, component);
  1981. wcd9378_reset_low(wcd9378->dev);
  1982. break;
  1983. case BOLERO_SLV_EVT_SSR_UP:
  1984. wcd9378_reset(wcd9378->dev);
  1985. /* allow reset to take effect */
  1986. usleep_range(10000, 10010);
  1987. wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
  1988. wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
  1989. wcd9378->tx_swr_dev->scp1_val = 0;
  1990. wcd9378->tx_swr_dev->scp2_val = 0;
  1991. wcd9378->rx_swr_dev->scp1_val = 0;
  1992. wcd9378->rx_swr_dev->scp2_val = 0;
  1993. wcd9378_init_reg(component);
  1994. regcache_mark_dirty(wcd9378->regmap);
  1995. regcache_sync(wcd9378->regmap);
  1996. /* Initialize MBHC module */
  1997. mbhc = &wcd9378->mbhc->wcd_mbhc;
  1998. ret = wcd9378_mbhc_post_ssr_init(wcd9378->mbhc, component);
  1999. if (ret) {
  2000. dev_err(component->dev, "%s: mbhc initialization failed\n",
  2001. __func__);
  2002. } else {
  2003. wcd9378_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2004. }
  2005. wcd9378->mbhc->wcd_mbhc.deinit_in_progress = false;
  2006. wcd9378->dev_up = true;
  2007. if (wcd9378->notify_swr_dmic)
  2008. blocking_notifier_call_chain(&wcd9378->notifier,
  2009. WCD9378_EVT_SSR_UP,
  2010. NULL);
  2011. if (wcd9378->usbc_hs_status)
  2012. mdelay(500);
  2013. break;
  2014. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2015. snd_soc_component_update_bits(component,
  2016. WCD9378_TOP_CLK_CFG, 0x06,
  2017. ((val >> 0x10) << 0x01));
  2018. rx_clk_type = (val >> 0x10);
  2019. switch (rx_clk_type) {
  2020. case RX_CLK_12P288MHZ:
  2021. wcd9378->swr_base_clk = SWR_BASECLK_24P576MHZ;
  2022. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2023. break;
  2024. case RX_CLK_11P2896MHZ:
  2025. wcd9378->swr_base_clk = SWR_BASECLK_22P5792MHZ;
  2026. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2027. break;
  2028. default:
  2029. wcd9378->swr_base_clk = SWR_BASECLK_19P2MHZ;
  2030. wcd9378->swr_clk_scale = SWR_CLKSCALE_DIV2;
  2031. break;
  2032. }
  2033. dev_dbg(component->dev, "%s: base_clk:0x%0x, clk_scale:0x%x\n",
  2034. __func__, wcd9378->swr_base_clk, wcd9378->swr_clk_scale);
  2035. break;
  2036. default:
  2037. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2038. break;
  2039. }
  2040. return 0;
  2041. }
  2042. static int wcd9378_wakeup(void *handle, bool enable)
  2043. {
  2044. struct wcd9378_priv *priv;
  2045. int ret = 0;
  2046. if (!handle) {
  2047. pr_err("%s: NULL handle\n", __func__);
  2048. return -EINVAL;
  2049. }
  2050. priv = (struct wcd9378_priv *)handle;
  2051. if (!priv->tx_swr_dev) {
  2052. pr_err("%s: tx swr dev is NULL\n", __func__);
  2053. return -EINVAL;
  2054. }
  2055. mutex_lock(&priv->wakeup_lock);
  2056. if (enable)
  2057. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2058. else
  2059. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2060. mutex_unlock(&priv->wakeup_lock);
  2061. return ret;
  2062. }
  2063. static inline int wcd9378_tx_path_get(const char *wname,
  2064. unsigned int *path_num)
  2065. {
  2066. int ret = 0;
  2067. char *widget_name = NULL;
  2068. char *w_name = NULL;
  2069. char *path_num_char = NULL;
  2070. char *path_name = NULL;
  2071. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2072. if (!widget_name)
  2073. return -EINVAL;
  2074. w_name = widget_name;
  2075. path_name = strsep(&widget_name, " ");
  2076. if (!path_name) {
  2077. pr_err("%s: Invalid widget name = %s\n",
  2078. __func__, widget_name);
  2079. ret = -EINVAL;
  2080. goto err;
  2081. }
  2082. path_num_char = strpbrk(path_name, "0123");
  2083. if (!path_num_char) {
  2084. pr_err("%s: tx path index not found\n",
  2085. __func__);
  2086. ret = -EINVAL;
  2087. goto err;
  2088. }
  2089. ret = kstrtouint(path_num_char, 10, path_num);
  2090. if (ret < 0)
  2091. pr_err("%s: Invalid tx path = %s\n",
  2092. __func__, w_name);
  2093. err:
  2094. kfree(w_name);
  2095. return ret;
  2096. }
  2097. static int wcd9378_tx_mode_get(struct snd_kcontrol *kcontrol,
  2098. struct snd_ctl_elem_value *ucontrol)
  2099. {
  2100. struct snd_soc_component *component =
  2101. snd_soc_kcontrol_component(kcontrol);
  2102. struct wcd9378_priv *wcd9378 = NULL;
  2103. int ret = 0;
  2104. unsigned int path = 0;
  2105. if (!component)
  2106. return -EINVAL;
  2107. wcd9378 = snd_soc_component_get_drvdata(component);
  2108. if (!wcd9378)
  2109. return -EINVAL;
  2110. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2111. if (ret < 0)
  2112. return ret;
  2113. ucontrol->value.integer.value[0] = wcd9378->tx_mode[path];
  2114. return 0;
  2115. }
  2116. static int wcd9378_tx_mode_put(struct snd_kcontrol *kcontrol,
  2117. struct snd_ctl_elem_value *ucontrol)
  2118. {
  2119. struct snd_soc_component *component =
  2120. snd_soc_kcontrol_component(kcontrol);
  2121. struct wcd9378_priv *wcd9378 = NULL;
  2122. u32 mode_val;
  2123. unsigned int path = 0;
  2124. int ret = 0;
  2125. if (!component)
  2126. return -EINVAL;
  2127. wcd9378 = snd_soc_component_get_drvdata(component);
  2128. if (!wcd9378)
  2129. return -EINVAL;
  2130. ret = wcd9378_tx_path_get(kcontrol->id.name, &path);
  2131. if (ret)
  2132. return ret;
  2133. mode_val = ucontrol->value.enumerated.item[0];
  2134. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2135. wcd9378->tx_mode[path] = mode_val;
  2136. return 0;
  2137. }
  2138. static int wcd9378_sys_usage_get(struct snd_kcontrol *kcontrol,
  2139. struct snd_ctl_elem_value *ucontrol)
  2140. {
  2141. struct snd_soc_component *component =
  2142. snd_soc_kcontrol_component(kcontrol);
  2143. u32 sys_usage_val = 0;
  2144. if (!component)
  2145. return -EINVAL;
  2146. sys_usage_val = (snd_soc_component_read(component, WCD9378_SYS_USAGE_CTRL) &
  2147. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK);
  2148. ucontrol->value.integer.value[0] = sys_usage_val;
  2149. return 0;
  2150. }
  2151. static int wcd9378_sys_usage_put(struct snd_kcontrol *kcontrol,
  2152. struct snd_ctl_elem_value *ucontrol)
  2153. {
  2154. struct snd_soc_component *component =
  2155. snd_soc_kcontrol_component(kcontrol);
  2156. struct wcd9378_priv *wcd9378 = NULL;
  2157. u32 sys_usage_val = 0;
  2158. if (!component)
  2159. return -EINVAL;
  2160. wcd9378 = snd_soc_component_get_drvdata(component);
  2161. if (!wcd9378)
  2162. return -EINVAL;
  2163. sys_usage_val = ucontrol->value.enumerated.item[0];
  2164. if (sys_usage_val >= WCD_SYS_USAGE_MAX) {
  2165. dev_err(component->dev, "%s: unsupport sys_usage_val: %d\n",
  2166. __func__, sys_usage_val);
  2167. return -EINVAL;
  2168. }
  2169. if (wcd9378->sys_usage != sys_usage_val)
  2170. snd_soc_component_update_bits(component,
  2171. WCD9378_SYS_USAGE_CTRL,
  2172. WCD9378_SYS_USAGE_CTRL_SYS_USAGE_CTRL_MASK,
  2173. sys_usage_val);
  2174. wcd9378->sys_usage = sys_usage_val;
  2175. switch (wcd9378->sys_usage) {
  2176. case SJ_SA_AUX_2SM:
  2177. case SJ_SA_AUX_2SM_1HDR:
  2178. case SJ_SA_EAR_2SM:
  2179. case SJ_SA_EAR_2SM_1HDR:
  2180. case SJ_1HDR_SA_AUX_1SM:
  2181. case SJ_1HDR_SA_EAR_1SM:
  2182. wcd9378->sjmic_support = true;
  2183. break;
  2184. case NOSJ_SA_STEREO_3SM:
  2185. case NOSJ_SA_STEREO_3SM_1HDR:
  2186. case NOSJ_SA_EAR_3SM:
  2187. case NOSJ_SA_EAR_3SM_1HDR:
  2188. case SJ_NOMIC_SA_EAR_3SM:
  2189. case SJ_NOMIC_SA_AUX_3SM:
  2190. wcd9378->sjmic_support = false;
  2191. break;
  2192. default:
  2193. dev_err(component->dev, "%s: unsupport sys_usage: %d\n",
  2194. __func__, wcd9378->sys_usage);
  2195. return -EINVAL;
  2196. }
  2197. dev_err(component->dev, "%s: sys_usage_val: %d, sjmic_support: %d\n",
  2198. __func__, wcd9378->sys_usage, wcd9378->sjmic_support);
  2199. return 0;
  2200. }
  2201. static int wcd9378_loopback_mode_get(struct snd_kcontrol *kcontrol,
  2202. struct snd_ctl_elem_value *ucontrol)
  2203. {
  2204. struct snd_soc_component *component =
  2205. snd_soc_kcontrol_component(kcontrol);
  2206. u32 loopback_mode = 0;
  2207. if (!component)
  2208. return -EINVAL;
  2209. loopback_mode = (snd_soc_component_read(component, WCD9378_LOOP_BACK_MODE) &
  2210. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK);
  2211. ucontrol->value.integer.value[0] = loopback_mode;
  2212. return 0;
  2213. }
  2214. static int wcd9378_loopback_mode_put(struct snd_kcontrol *kcontrol,
  2215. struct snd_ctl_elem_value *ucontrol)
  2216. {
  2217. struct snd_soc_component *component =
  2218. snd_soc_kcontrol_component(kcontrol);
  2219. u32 loopback_mode = 0;
  2220. if (!component)
  2221. return -EINVAL;
  2222. loopback_mode = ucontrol->value.enumerated.item[0];
  2223. snd_soc_component_update_bits(component,
  2224. WCD9378_LOOP_BACK_MODE,
  2225. WCD9378_LOOP_BACK_MODE_LOOPBACK_MODE_MASK,
  2226. loopback_mode);
  2227. dev_dbg(component->dev, "%s: loopback_mode: %d\n",
  2228. __func__, loopback_mode);
  2229. return 0;
  2230. }
  2231. static int wcd9378_aux_dsm_get(struct snd_kcontrol *kcontrol,
  2232. struct snd_ctl_elem_value *ucontrol)
  2233. {
  2234. struct snd_soc_component *component =
  2235. snd_soc_kcontrol_component(kcontrol);
  2236. u32 aux_dsm_in = 0;
  2237. if (!component)
  2238. return -EINVAL;
  2239. aux_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2240. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK);
  2241. ucontrol->value.integer.value[0] = aux_dsm_in;
  2242. return 0;
  2243. }
  2244. static int wcd9378_aux_dsm_put(struct snd_kcontrol *kcontrol,
  2245. struct snd_ctl_elem_value *ucontrol)
  2246. {
  2247. struct snd_soc_component *component =
  2248. snd_soc_kcontrol_component(kcontrol);
  2249. u32 aux_dsm_in = 0;
  2250. if (!component)
  2251. return -EINVAL;
  2252. aux_dsm_in = ucontrol->value.enumerated.item[0];
  2253. snd_soc_component_update_bits(component,
  2254. WCD9378_LB_IN_SEL_CTL,
  2255. WCD9378_LB_IN_SEL_CTL_AUX_LB_IN_SEL_MASK,
  2256. aux_dsm_in);
  2257. dev_dbg(component->dev, "%s: aux_dsm input: %d\n",
  2258. __func__, aux_dsm_in);
  2259. return 0;
  2260. }
  2261. static int wcd9378_hph_dsm_get(struct snd_kcontrol *kcontrol,
  2262. struct snd_ctl_elem_value *ucontrol)
  2263. {
  2264. struct snd_soc_component *component =
  2265. snd_soc_kcontrol_component(kcontrol);
  2266. u32 hph_dsm_in = 0;
  2267. if (!component)
  2268. return -EINVAL;
  2269. hph_dsm_in = (snd_soc_component_read(component, WCD9378_LB_IN_SEL_CTL) &
  2270. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK);
  2271. ucontrol->value.integer.value[0] = hph_dsm_in;
  2272. return 0;
  2273. }
  2274. static int wcd9378_hph_dsm_put(struct snd_kcontrol *kcontrol,
  2275. struct snd_ctl_elem_value *ucontrol)
  2276. {
  2277. struct snd_soc_component *component =
  2278. snd_soc_kcontrol_component(kcontrol);
  2279. u32 hph_dsm_in = 0;
  2280. if (!component)
  2281. return -EINVAL;
  2282. hph_dsm_in = ucontrol->value.enumerated.item[0];
  2283. snd_soc_component_update_bits(component,
  2284. WCD9378_LB_IN_SEL_CTL,
  2285. WCD9378_LB_IN_SEL_CTL_HPH_LB_IN_SEL_MASK,
  2286. hph_dsm_in);
  2287. dev_dbg(component->dev, "%s: hph_dsm input: %d\n",
  2288. __func__, hph_dsm_in);
  2289. return 0;
  2290. }
  2291. static inline int wcd9378_simple_mic_num_get(const char *wname,
  2292. unsigned int *sm_num)
  2293. {
  2294. int ret = 0;
  2295. char *widget_name = NULL;
  2296. char *w_name = NULL;
  2297. char *sm_num_char = NULL;
  2298. char *sm_name = NULL;
  2299. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2300. if (!widget_name)
  2301. return -EINVAL;
  2302. w_name = widget_name;
  2303. sm_name = strsep(&widget_name, " ");
  2304. if (!sm_name) {
  2305. pr_err("%s: Invalid widget name = %s\n",
  2306. __func__, widget_name);
  2307. ret = -EINVAL;
  2308. goto err;
  2309. }
  2310. sm_num_char = strpbrk(sm_name, "0123");
  2311. if (!sm_num_char) {
  2312. pr_err("%s: simple mic index not found\n",
  2313. __func__);
  2314. ret = -EINVAL;
  2315. goto err;
  2316. }
  2317. ret = kstrtouint(sm_num_char, 10, sm_num);
  2318. if (ret < 0)
  2319. pr_err("%s: Invalid micb num = %s\n",
  2320. __func__, w_name);
  2321. err:
  2322. kfree(w_name);
  2323. return ret;
  2324. }
  2325. static int wcd9378_mb_sel_get(struct snd_kcontrol *kcontrol,
  2326. struct snd_ctl_elem_value *ucontrol)
  2327. {
  2328. struct snd_soc_component *component =
  2329. snd_soc_kcontrol_component(kcontrol);
  2330. struct wcd9378_priv *wcd9378 = NULL;
  2331. int ret = 0;
  2332. unsigned int sm_num = 0;
  2333. if (!component)
  2334. return -EINVAL;
  2335. wcd9378 = snd_soc_component_get_drvdata(component);
  2336. if (!wcd9378)
  2337. return -EINVAL;
  2338. ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
  2339. if (ret < 0)
  2340. return ret;
  2341. ucontrol->value.integer.value[0] = wcd9378->micb_sel[sm_num];
  2342. return 0;
  2343. }
  2344. static int wcd9378_mb_sel_put(struct snd_kcontrol *kcontrol,
  2345. struct snd_ctl_elem_value *ucontrol)
  2346. {
  2347. struct snd_soc_component *component =
  2348. snd_soc_kcontrol_component(kcontrol);
  2349. struct wcd9378_priv *wcd9378 = NULL;
  2350. u32 micb_num = 0, sm_sel = 0, sm_sel_mask = 0;
  2351. unsigned int sm_num = 0;
  2352. int ret = 0;
  2353. if (!component)
  2354. return -EINVAL;
  2355. wcd9378 = snd_soc_component_get_drvdata(component);
  2356. if (!wcd9378)
  2357. return -EINVAL;
  2358. ret = wcd9378_simple_mic_num_get(kcontrol->id.name, &sm_num);
  2359. if (ret)
  2360. return ret;
  2361. switch (sm_num) {
  2362. case SIM_MIC0:
  2363. sm_sel = WCD9378_SM0_MB_SEL;
  2364. sm_sel_mask = WCD9378_SM0_MB_SEL_SM0_MB_SEL_MASK;
  2365. break;
  2366. case SIM_MIC1:
  2367. sm_sel = WCD9378_SM1_MB_SEL;
  2368. sm_sel_mask = WCD9378_SM1_MB_SEL_SM1_MB_SEL_MASK;
  2369. break;
  2370. case SIM_MIC2:
  2371. sm_sel = WCD9378_SM2_MB_SEL;
  2372. sm_sel_mask = WCD9378_SM2_MB_SEL_SM2_MB_SEL_MASK;
  2373. break;
  2374. default:
  2375. pr_err("%s: unsupport sm_num: %d\n", __func__, sm_num);
  2376. return -EINVAL;
  2377. }
  2378. micb_num = ucontrol->value.enumerated.item[0];
  2379. if (micb_num >= MICB_NUM) {
  2380. pr_err("%s: unsupport micb num\n", __func__);
  2381. return -EINVAL;
  2382. }
  2383. snd_soc_component_update_bits(component, sm_sel,
  2384. sm_sel_mask, micb_num);
  2385. wcd9378->micb_sel[sm_num] = micb_num;
  2386. dev_err(component->dev, "%s: sm%d_mb_sel :%d\n",
  2387. __func__, sm_num, micb_num);
  2388. return 0;
  2389. }
  2390. /*TBD: NEED CHECK THE LOGIC*/
  2391. static int wcd9378_hph_put_gain(struct snd_kcontrol *kcontrol,
  2392. struct snd_ctl_elem_value *ucontrol)
  2393. {
  2394. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2395. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2396. u16 offset = ucontrol->value.enumerated.item[0];
  2397. u32 temp = 0;
  2398. temp = 0x00 - offset * 0x180;
  2399. wcd9378->hph_gain = (u16)(temp & 0xffff);
  2400. dev_dbg(component->dev, "%s: hph gain is 0x%0x\n", __func__, wcd9378->hph_gain);
  2401. return 0;
  2402. }
  2403. static int wcd9378_hph_get_gain(struct snd_kcontrol *kcontrol,
  2404. struct snd_ctl_elem_value *ucontrol)
  2405. {
  2406. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2407. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2408. u32 temp = 0;
  2409. u16 offset = 0;
  2410. temp = 0 - wcd9378->hph_gain;
  2411. offset = (u16)(temp & 0xffff);
  2412. offset /= 0x180;
  2413. ucontrol->value.enumerated.item[0] = offset;
  2414. dev_dbg(component->dev, "%s: offset is 0x%0x\n", __func__, offset);
  2415. return 0;
  2416. }
  2417. static int wcd9378_rx2_mode_put(struct snd_kcontrol *kcontrol,
  2418. struct snd_ctl_elem_value *ucontrol)
  2419. {
  2420. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2421. struct wcd9378_priv *wcd9378 =
  2422. snd_soc_component_get_drvdata(component);
  2423. if (ucontrol->value.enumerated.item[0])
  2424. wcd9378->rx2_clk_mode = RX2_NORMAL_MODE;
  2425. else
  2426. wcd9378->rx2_clk_mode = RX2_HP_MODE;
  2427. return 1;
  2428. }
  2429. static int wcd9378_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2430. struct snd_ctl_elem_value *ucontrol)
  2431. {
  2432. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2433. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2434. ucontrol->value.enumerated.item[0] = wcd9378->hph_mode;
  2435. return 0;
  2436. }
  2437. static int wcd9378_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2438. struct snd_ctl_elem_value *ucontrol)
  2439. {
  2440. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2441. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2442. if (wcd9378->hph_mode == ucontrol->value.enumerated.item[0])
  2443. return 0;
  2444. wcd9378->hph_mode = ucontrol->value.enumerated.item[0];
  2445. return 1;
  2446. }
  2447. /* wcd9378_codec_get_dev_num - returns swr device number
  2448. * @component: Codec instance
  2449. *
  2450. * Return: swr device number on success or negative error
  2451. * code on failure.
  2452. */
  2453. int wcd9378_codec_get_dev_num(struct snd_soc_component *component)
  2454. {
  2455. struct wcd9378_priv *wcd9378;
  2456. if (!component)
  2457. return -EINVAL;
  2458. wcd9378 = snd_soc_component_get_drvdata(component);
  2459. if (!wcd9378 || !wcd9378->rx_swr_dev) {
  2460. pr_err("%s: wcd9378 component is NULL\n", __func__);
  2461. return -EINVAL;
  2462. }
  2463. return wcd9378->rx_swr_dev->dev_num;
  2464. }
  2465. EXPORT_SYMBOL_GPL(wcd9378_codec_get_dev_num);
  2466. static int wcd9378_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
  2467. struct snd_ctl_elem_value *ucontrol)
  2468. {
  2469. struct snd_soc_component *component =
  2470. snd_soc_kcontrol_component(kcontrol);
  2471. struct wcd9378_priv *wcd9378 =
  2472. snd_soc_component_get_drvdata(component);
  2473. if (wcd9378->comp1_enable) {
  2474. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2475. return -EINVAL;
  2476. }
  2477. snd_soc_component_update_bits(component, WCD9378_AUX_INT_MISC,
  2478. WCD9378_ANA_EAR_COMPANDER_CTL_EAR_GAIN_MASK,
  2479. ucontrol->value.integer.value[0]);
  2480. return 1;
  2481. }
  2482. static int wcd9378_aux_pa_put_gain(struct snd_kcontrol *kcontrol,
  2483. struct snd_ctl_elem_value *ucontrol)
  2484. {
  2485. struct snd_soc_component *component =
  2486. snd_soc_kcontrol_component(kcontrol);
  2487. struct wcd9378_priv *wcd9378 =
  2488. snd_soc_component_get_drvdata(component);
  2489. if (wcd9378->comp1_enable) {
  2490. dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
  2491. return -EINVAL;
  2492. }
  2493. snd_soc_component_update_bits(component, WCD9378_ANA_EAR_COMPANDER_CTL,
  2494. WCD9378_AUX_INT_MISC_PA_GAIN_MASK,
  2495. ucontrol->value.integer.value[0]);
  2496. return 1;
  2497. }
  2498. static int wcd9378_get_compander(struct snd_kcontrol *kcontrol,
  2499. struct snd_ctl_elem_value *ucontrol)
  2500. {
  2501. struct snd_soc_component *component =
  2502. snd_soc_kcontrol_component(kcontrol);
  2503. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2504. bool hphr;
  2505. struct soc_multi_mixer_control *mc;
  2506. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2507. hphr = mc->shift;
  2508. ucontrol->value.integer.value[0] = hphr ? wcd9378->comp2_enable :
  2509. wcd9378->comp1_enable;
  2510. return 0;
  2511. }
  2512. static int wcd9378_set_compander(struct snd_kcontrol *kcontrol,
  2513. struct snd_ctl_elem_value *ucontrol)
  2514. {
  2515. struct snd_soc_component *component =
  2516. snd_soc_kcontrol_component(kcontrol);
  2517. struct wcd9378_priv *wcd9378 =
  2518. snd_soc_component_get_drvdata(component);
  2519. int value = ucontrol->value.integer.value[0];
  2520. bool hphr;
  2521. struct soc_multi_mixer_control *mc;
  2522. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2523. hphr = mc->shift;
  2524. if (hphr)
  2525. wcd9378->comp2_enable = value;
  2526. else
  2527. wcd9378->comp1_enable = value;
  2528. dev_dbg(component->dev, "%s: set compander: %d\n", __func__, value);
  2529. return 0;
  2530. }
  2531. static int wcd9378_get_va_amic_switch(struct snd_kcontrol *kcontrol,
  2532. struct snd_ctl_elem_value *ucontrol)
  2533. {
  2534. struct snd_soc_component *component =
  2535. snd_soc_kcontrol_component(kcontrol);
  2536. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2537. ucontrol->value.integer.value[0] = wcd9378->va_amic_en;
  2538. return 0;
  2539. }
  2540. static int wcd9378_set_va_amic_switch(struct snd_kcontrol *kcontrol,
  2541. struct snd_ctl_elem_value *ucontrol)
  2542. {
  2543. struct snd_soc_component *component =
  2544. snd_soc_kcontrol_component(kcontrol);
  2545. struct wcd9378_priv *wcd9378 =
  2546. snd_soc_component_get_drvdata(component);
  2547. int value = ucontrol->value.integer.value[0];
  2548. wcd9378->va_amic_en = value;
  2549. return 0;
  2550. }
  2551. static int wcd9378_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2552. struct snd_kcontrol *kcontrol,
  2553. int event)
  2554. {
  2555. struct snd_soc_component *component =
  2556. snd_soc_dapm_to_component(w->dapm);
  2557. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2558. struct wcd9378_pdata *pdata = NULL;
  2559. int ret = 0;
  2560. pdata = dev_get_platdata(wcd9378->dev);
  2561. if (!pdata) {
  2562. dev_err(component->dev, "%s: pdata is NULL\n", __func__);
  2563. return -EINVAL;
  2564. }
  2565. if (!msm_cdc_is_ondemand_supply(wcd9378->dev,
  2566. wcd9378->supplies,
  2567. pdata->regulator,
  2568. pdata->num_supplies,
  2569. "cdc-vdd-buck"))
  2570. return 0;
  2571. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2572. w->name, event);
  2573. switch (event) {
  2574. case SND_SOC_DAPM_PRE_PMU:
  2575. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  2576. dev_dbg(component->dev,
  2577. "%s: buck already in enabled state\n",
  2578. __func__);
  2579. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2580. return 0;
  2581. }
  2582. ret = msm_cdc_enable_ondemand_supply(wcd9378->dev,
  2583. wcd9378->supplies,
  2584. pdata->regulator,
  2585. pdata->num_supplies,
  2586. "cdc-vdd-buck");
  2587. if (ret == -EINVAL) {
  2588. dev_err(component->dev, "%s: vdd buck is not enabled\n",
  2589. __func__);
  2590. return ret;
  2591. }
  2592. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2593. /*
  2594. * 200us sleep is required after LDO is enabled as per
  2595. * HW requirement
  2596. */
  2597. usleep_range(200, 250);
  2598. break;
  2599. case SND_SOC_DAPM_POST_PMD:
  2600. set_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  2601. break;
  2602. }
  2603. return 0;
  2604. }
  2605. const char * const tx_master_ch_text[] = {
  2606. "ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
  2607. "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
  2608. "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
  2609. "SWRM_PCM_IN",
  2610. };
  2611. const struct soc_enum tx_master_ch_enum =
  2612. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2613. tx_master_ch_text);
  2614. static void wcd9378_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2615. {
  2616. u8 ch_type = 0;
  2617. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2618. ch_type = ADC1;
  2619. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2620. ch_type = ADC2;
  2621. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2622. ch_type = ADC3;
  2623. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2624. ch_type = ADC4;
  2625. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2626. ch_type = DMIC0;
  2627. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2628. ch_type = DMIC1;
  2629. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2630. ch_type = MBHC;
  2631. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2632. ch_type = DMIC2;
  2633. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2634. ch_type = DMIC3;
  2635. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2636. ch_type = DMIC4;
  2637. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2638. ch_type = DMIC5;
  2639. else
  2640. pr_err("%s: port name: %s is not listed\n", __func__, wname);
  2641. if (ch_type)
  2642. *ch_idx = wcd9378_slave_get_slave_ch_val(ch_type);
  2643. else
  2644. *ch_idx = -EINVAL;
  2645. }
  2646. static int wcd9378_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2647. struct snd_ctl_elem_value *ucontrol)
  2648. {
  2649. struct snd_soc_component *component =
  2650. snd_soc_kcontrol_component(kcontrol);
  2651. struct wcd9378_priv *wcd9378 = NULL;
  2652. int slave_ch_idx = -EINVAL;
  2653. if (component == NULL)
  2654. return -EINVAL;
  2655. wcd9378 = snd_soc_component_get_drvdata(component);
  2656. if (wcd9378 == NULL)
  2657. return -EINVAL;
  2658. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2659. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2660. return -EINVAL;
  2661. ucontrol->value.integer.value[0] = wcd9378_slave_get_master_ch_val(
  2662. wcd9378->tx_master_ch_map[slave_ch_idx]);
  2663. return 0;
  2664. }
  2665. static int wcd9378_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2666. struct snd_ctl_elem_value *ucontrol)
  2667. {
  2668. struct snd_soc_component *component =
  2669. snd_soc_kcontrol_component(kcontrol);
  2670. struct wcd9378_priv *wcd9378 = NULL;
  2671. int slave_ch_idx = -EINVAL, idx = 0;
  2672. if (component == NULL)
  2673. return -EINVAL;
  2674. wcd9378 = snd_soc_component_get_drvdata(component);
  2675. if (wcd9378 == NULL)
  2676. return -EINVAL;
  2677. wcd9378_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2678. if (slave_ch_idx < 0 || slave_ch_idx >= WCD9378_MAX_SLAVE_CH_TYPES)
  2679. return -EINVAL;
  2680. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2681. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2682. __func__, ucontrol->value.enumerated.item[0]);
  2683. idx = ucontrol->value.enumerated.item[0];
  2684. if (idx < 0 || idx >= ARRAY_SIZE(wcd9378_swr_master_ch_map))
  2685. return -EINVAL;
  2686. wcd9378->tx_master_ch_map[slave_ch_idx] = wcd9378_slave_get_master_ch(idx);
  2687. return 0;
  2688. }
  2689. static int wcd9378_bcs_get(struct snd_kcontrol *kcontrol,
  2690. struct snd_ctl_elem_value *ucontrol)
  2691. {
  2692. struct snd_soc_component *component =
  2693. snd_soc_kcontrol_component(kcontrol);
  2694. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2695. ucontrol->value.integer.value[0] = wcd9378->bcs_dis;
  2696. return 0;
  2697. }
  2698. static int wcd9378_bcs_put(struct snd_kcontrol *kcontrol,
  2699. struct snd_ctl_elem_value *ucontrol)
  2700. {
  2701. struct snd_soc_component *component =
  2702. snd_soc_kcontrol_component(kcontrol);
  2703. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  2704. wcd9378->bcs_dis = ucontrol->value.integer.value[0];
  2705. return 0;
  2706. }
  2707. static const char * const sys_usage_text[] = {
  2708. "NOSJ_SA_STEREO_3SM", "SJ_SA_AUX_2SM", "NOSJ_SA_STEREO_3SM_1HDR",
  2709. "SJ_SA_AUX_2SM_1HDR", "NOSJ_SA_EAR_3SM", "SJ_SA_EAR_2SM", "NOSJ_SA_EAR_3SM_1HDR",
  2710. "SJ_SA_EAR_2SM_1HDR", "SJ_1HDR_SA_AUX_1SM", "SJ_1HDR_SA_EAR_1SM",
  2711. "SJ_SA_STEREO_2SM", "SJ_NOMIC_SA_EAR_3SM", "SJ_NOMIC_SA_AUX_3SM",
  2712. };
  2713. static const struct soc_enum sys_usage_enum =
  2714. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(sys_usage_text),
  2715. sys_usage_text);
  2716. static const char * const loopback_mode_text[] = {
  2717. "NO_LP", "SWR_LP1", "SWR_LP2", "SWR_LP3",
  2718. };
  2719. static const struct soc_enum loopback_mode_enum =
  2720. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mode_text),
  2721. loopback_mode_text);
  2722. static const char * const aux_dsm_text[] = {
  2723. "TX2->AUX", "TX3->AUX", "TX0->AUX", "TX1->AUX",
  2724. };
  2725. static const struct soc_enum aux_dsm_enum =
  2726. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aux_dsm_text),
  2727. aux_dsm_text);
  2728. static const char * const hph_dsm_text[] = {
  2729. "HPH_DSM_IN0", "HPH_DSM_IN1", "HPH_DSM_IN2", "HPH_DSM_IN3",
  2730. };
  2731. static const struct soc_enum hph_dsm_enum =
  2732. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(hph_dsm_text),
  2733. hph_dsm_text);
  2734. static const char * const tx_mode_mux_text[] = {
  2735. "ADC_INVALID", "ADC_HIFI", "ADC_NORMAL", "ADC_LP",
  2736. };
  2737. static const struct soc_enum tx_mode_mux_enum =
  2738. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2739. tx_mode_mux_text);
  2740. static const char * const micb_sel_text[] = {
  2741. "NO_MICB", "MICB1", "MICB2", "MICB3",
  2742. };
  2743. static const struct soc_enum sm_micb_enum =
  2744. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micb_sel_text),
  2745. micb_sel_text);
  2746. static const char * const rx2_mode_text[] = {
  2747. "HP", "NORMAL",
  2748. };
  2749. static const struct soc_enum rx2_mode_enum =
  2750. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx2_mode_text),
  2751. rx2_mode_text);
  2752. static const char * const rx_hph_mode_mux_text[] = {
  2753. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2754. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2755. };
  2756. static const struct soc_enum rx_hph_mode_mux_enum =
  2757. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2758. rx_hph_mode_mux_text);
  2759. static const struct snd_kcontrol_new wcd9378_snd_controls[] = {
  2760. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2761. wcd9378_get_compander, wcd9378_set_compander),
  2762. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2763. wcd9378_get_compander, wcd9378_set_compander),
  2764. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2765. wcd9378_bcs_get, wcd9378_bcs_put),
  2766. SOC_SINGLE_EXT("VA_AMIC_MIXER Switch", SND_SOC_NOPM, 0, 1, 0,
  2767. wcd9378_get_va_amic_switch, wcd9378_set_va_amic_switch),
  2768. SOC_ENUM_EXT("SYS_USAGE Mode", sys_usage_enum,
  2769. wcd9378_sys_usage_get, wcd9378_sys_usage_put),
  2770. SOC_ENUM_EXT("LOOPBACK Mode", loopback_mode_enum,
  2771. wcd9378_loopback_mode_get, wcd9378_loopback_mode_put),
  2772. SOC_ENUM_EXT("AUX_LB_IN SEL", aux_dsm_enum,
  2773. wcd9378_aux_dsm_get, wcd9378_aux_dsm_put),
  2774. SOC_ENUM_EXT("HPH_LB_IN SEL", hph_dsm_enum,
  2775. wcd9378_hph_dsm_get, wcd9378_hph_dsm_put),
  2776. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2777. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2778. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2779. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2780. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2781. wcd9378_tx_mode_get, wcd9378_tx_mode_put),
  2782. SOC_ENUM_EXT("SM0 MICB SEL", sm_micb_enum,
  2783. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2784. SOC_ENUM_EXT("SM1 MICB SEL", sm_micb_enum,
  2785. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2786. SOC_ENUM_EXT("SM2 MICB SEL", sm_micb_enum,
  2787. wcd9378_mb_sel_get, wcd9378_mb_sel_put),
  2788. SOC_ENUM_EXT("RX2 Mode", rx2_mode_enum,
  2789. NULL, wcd9378_rx2_mode_put),
  2790. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2791. wcd9378_rx_hph_mode_get, wcd9378_rx_hph_mode_put),
  2792. SOC_SINGLE_EXT("HPH Volume", SND_SOC_NOPM, 0, 0x14, 0,
  2793. wcd9378_hph_get_gain, wcd9378_hph_put_gain),
  2794. WCD9378_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD9378_ANA_EAR_COMPANDER_CTL,
  2795. 2, 0x10, 0, ear_pa_gain),
  2796. WCD9378_AUX_PA_GAIN_TLV("AUX_PA Volume", WCD9378_AUX_INT_MISC,
  2797. 0, 0x8, 0, aux_pa_gain),
  2798. SOC_SINGLE_TLV("ADC1 Volume", WCD9378_ANA_TX_CH1, 0, 20, 0,
  2799. analog_gain),
  2800. SOC_SINGLE_TLV("ADC2 Volume", WCD9378_ANA_TX_CH2, 0, 20, 0,
  2801. analog_gain),
  2802. SOC_SINGLE_TLV("ADC3 Volume", WCD9378_ANA_TX_CH3, 0, 20, 0,
  2803. analog_gain),
  2804. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2805. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2806. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2807. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2808. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2809. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2810. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2811. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2812. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2813. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2814. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2815. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2816. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2817. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2818. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2819. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2820. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2821. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2822. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2823. wcd9378_tx_master_ch_get, wcd9378_tx_master_ch_put),
  2824. };
  2825. static const struct snd_kcontrol_new dmic1_switch[] = {
  2826. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2827. };
  2828. static const struct snd_kcontrol_new dmic2_switch[] = {
  2829. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2830. };
  2831. static const struct snd_kcontrol_new dmic3_switch[] = {
  2832. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2833. };
  2834. static const struct snd_kcontrol_new dmic4_switch[] = {
  2835. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2836. };
  2837. static const struct snd_kcontrol_new dmic5_switch[] = {
  2838. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2839. };
  2840. static const struct snd_kcontrol_new dmic6_switch[] = {
  2841. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2842. };
  2843. static const char * const adc1_mux_text[] = {
  2844. "CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4"
  2845. };
  2846. static const char * const adc2_mux_text[] = {
  2847. "CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4"
  2848. };
  2849. static const char * const adc3_mux_text[] = {
  2850. "CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC2", "CH3_AMIC3", "CH3_AMIC4"
  2851. };
  2852. static const char * const ear_mux_text[] = {
  2853. "RX2", "RX0"
  2854. };
  2855. static const char * const aux_mux_text[] = {
  2856. "RX2", "RX1"
  2857. };
  2858. static const struct soc_enum adc1_enum =
  2859. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2860. WCD9378_TX_NEW_TX_CH12_MUX_CH1_SEL_SHIFT,
  2861. ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
  2862. static const struct soc_enum adc2_enum =
  2863. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH12_MUX,
  2864. WCD9378_TX_NEW_TX_CH12_MUX_CH2_SEL_SHIFT,
  2865. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2866. static const struct soc_enum adc3_enum =
  2867. SOC_ENUM_SINGLE(WCD9378_TX_NEW_TX_CH34_MUX,
  2868. WCD9378_TX_NEW_TX_CH34_MUX_CH3_SEL_SHIFT,
  2869. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2870. static const struct soc_enum ear_enum =
  2871. SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
  2872. WCD9378_CDC_HPH_GAIN_CTL_HPHL_RX_EN_SHIFT,
  2873. ARRAY_SIZE(ear_mux_text), ear_mux_text);
  2874. static const struct soc_enum aux_enum =
  2875. SOC_ENUM_SINGLE(WCD9378_CDC_HPH_GAIN_CTL,
  2876. WCD9378_CDC_HPH_GAIN_CTL_HPHR_RX_EN_SHIFT,
  2877. ARRAY_SIZE(aux_mux_text), aux_mux_text);
  2878. static const struct snd_kcontrol_new tx_adc1_mux =
  2879. SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
  2880. static const struct snd_kcontrol_new tx_adc2_mux =
  2881. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2882. static const struct snd_kcontrol_new tx_adc3_mux =
  2883. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2884. static const struct snd_kcontrol_new ear_mux =
  2885. SOC_DAPM_ENUM("EAR Mux", ear_enum);
  2886. static const struct snd_kcontrol_new aux_mux =
  2887. SOC_DAPM_ENUM("AUX Mux", aux_enum);
  2888. static const struct snd_kcontrol_new dac1_switch[] = {
  2889. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2890. };
  2891. static const struct snd_kcontrol_new dac2_switch[] = {
  2892. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2893. };
  2894. static const struct snd_kcontrol_new ear_mixer_switch[] = {
  2895. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2896. };
  2897. static const struct snd_kcontrol_new aux_mixer_switch[] = {
  2898. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2899. };
  2900. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2901. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2902. };
  2903. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2904. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2905. };
  2906. static const struct snd_kcontrol_new rx0_switch[] = {
  2907. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2908. };
  2909. static const struct snd_kcontrol_new rx1_switch[] = {
  2910. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2911. };
  2912. static const struct snd_soc_dapm_widget wcd9378_dapm_widgets[] = {
  2913. /*input widgets*/
  2914. SND_SOC_DAPM_INPUT("AMIC1"),
  2915. SND_SOC_DAPM_INPUT("AMIC2"),
  2916. SND_SOC_DAPM_INPUT("AMIC3"),
  2917. SND_SOC_DAPM_INPUT("AMIC4"),
  2918. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2919. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2920. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2921. /*tx widgets*/
  2922. SND_SOC_DAPM_MIXER_E("TX0 SEQUENCER", SND_SOC_NOPM, ADC1, 0,
  2923. NULL, 0, wcd9378_tx_sequencer_enable,
  2924. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2925. SND_SOC_DAPM_MIXER_E("TX1 SEQUENCER", SND_SOC_NOPM, ADC2, 0,
  2926. NULL, 0, wcd9378_tx_sequencer_enable,
  2927. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2928. SND_SOC_DAPM_MIXER_E("TX2 SEQUENCER", SND_SOC_NOPM, ADC3, 0,
  2929. NULL, 0, wcd9378_tx_sequencer_enable,
  2930. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2931. SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0,
  2932. &tx_adc1_mux),
  2933. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  2934. &tx_adc2_mux),
  2935. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  2936. &tx_adc3_mux),
  2937. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  2938. wcd9378_codec_enable_dmic,
  2939. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2940. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  2941. wcd9378_codec_enable_dmic,
  2942. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2943. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  2944. wcd9378_codec_enable_dmic,
  2945. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2946. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  2947. wcd9378_codec_enable_dmic,
  2948. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2949. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  2950. wcd9378_codec_enable_dmic,
  2951. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2952. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  2953. wcd9378_codec_enable_dmic,
  2954. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2955. /*rx widgets*/
  2956. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  2957. wcd9378_codec_hphl_dac_event,
  2958. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2959. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  2960. wcd9378_codec_hphr_dac_event,
  2961. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2962. SND_SOC_DAPM_MIXER_E("HPH SEQUENCER", SND_SOC_NOPM, 0, 0, NULL, 0,
  2963. wcd9378_hph_sequencer_enable,
  2964. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2965. SND_SOC_DAPM_PGA_E("HPHL PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2966. wcd9378_codec_enable_hphl_pa,
  2967. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2968. SND_SOC_DAPM_PGA_E("HPHR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2969. wcd9378_codec_enable_hphr_pa,
  2970. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2971. SND_SOC_DAPM_MIXER_E("SA SEQUENCER", SND_SOC_NOPM, 0, 0,
  2972. NULL, 0, wcd9378_sa_sequencer_enable,
  2973. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2974. SND_SOC_DAPM_DAC_E("EAR_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2975. wcd9378_codec_ear_dac_event,
  2976. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2977. SND_SOC_DAPM_DAC_E("AUX_RDAC", NULL, SND_SOC_NOPM, 0, 0,
  2978. wcd9378_codec_aux_dac_event,
  2979. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2980. SND_SOC_DAPM_PGA_E("EAR PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2981. wcd9378_codec_enable_ear_pa,
  2982. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2983. SND_SOC_DAPM_PGA_E("AUX PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
  2984. wcd9378_codec_enable_aux_pa,
  2985. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2986. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  2987. wcd9378_codec_enable_vdd_buck,
  2988. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2989. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  2990. wcd9378_enable_clsh,
  2991. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2992. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  2993. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  2994. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2995. SND_SOC_DAPM_POST_PMD),
  2996. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  2997. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  2998. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  2999. SND_SOC_DAPM_POST_PMD),
  3000. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3001. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3002. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3003. SND_SOC_DAPM_POST_PMD),
  3004. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3005. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3006. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3007. SND_SOC_DAPM_POST_PMD),
  3008. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3009. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3010. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3011. SND_SOC_DAPM_POST_PMD),
  3012. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3013. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3014. wcd9378_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3015. SND_SOC_DAPM_POST_PMD),
  3016. /* micbias widgets*/
  3017. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3018. wcd9378_codec_enable_micbias,
  3019. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3020. SND_SOC_DAPM_POST_PMD),
  3021. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3022. wcd9378_codec_enable_micbias,
  3023. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3024. SND_SOC_DAPM_POST_PMD),
  3025. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3026. wcd9378_codec_enable_micbias,
  3027. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3028. SND_SOC_DAPM_POST_PMD),
  3029. /* micbias pull up widgets*/
  3030. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3031. wcd9378_codec_enable_micbias_pullup,
  3032. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3033. SND_SOC_DAPM_POST_PMD),
  3034. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3035. wcd9378_codec_enable_micbias_pullup,
  3036. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3037. SND_SOC_DAPM_POST_PMD),
  3038. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3039. wcd9378_codec_enable_micbias_pullup,
  3040. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3041. SND_SOC_DAPM_POST_PMD),
  3042. /* rx mixer widgets*/
  3043. SND_SOC_DAPM_MUX("EAR_MUX", SND_SOC_NOPM, 0, 0, &ear_mux),
  3044. SND_SOC_DAPM_MUX("AUX_MUX", SND_SOC_NOPM, 0, 0, &aux_mux),
  3045. SND_SOC_DAPM_MIXER("EAR_MIXER", SND_SOC_NOPM, 0, 0,
  3046. ear_mixer_switch, ARRAY_SIZE(ear_mixer_switch)),
  3047. SND_SOC_DAPM_MIXER("AUX_MIXER", SND_SOC_NOPM, 0, 0,
  3048. aux_mixer_switch, ARRAY_SIZE(aux_mixer_switch)),
  3049. SND_SOC_DAPM_MIXER("DAC1", SND_SOC_NOPM, 0, 0,
  3050. dac1_switch, ARRAY_SIZE(dac1_switch)),
  3051. SND_SOC_DAPM_MIXER("DAC2", SND_SOC_NOPM, 0, 0,
  3052. dac2_switch, ARRAY_SIZE(dac2_switch)),
  3053. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3054. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3055. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3056. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3057. /*output widgets tx*/
  3058. SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
  3059. SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
  3060. SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
  3061. SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
  3062. SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
  3063. SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
  3064. SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
  3065. SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
  3066. SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
  3067. /*output widgets rx*/
  3068. SND_SOC_DAPM_OUTPUT("EAR"),
  3069. SND_SOC_DAPM_OUTPUT("AUX"),
  3070. SND_SOC_DAPM_OUTPUT("HPHL"),
  3071. SND_SOC_DAPM_OUTPUT("HPHR"),
  3072. };
  3073. static const struct snd_soc_dapm_route wcd9378_audio_map[] = {
  3074. /*ADC-1 (channel-1)*/
  3075. {"ADC1_OUTPUT", NULL, "TX0 SEQUENCER"},
  3076. {"TX0 SEQUENCER", NULL, "ADC1 MUX"},
  3077. {"ADC1 MUX", "CH1_AMIC1", "AMIC1"},
  3078. {"ADC1 MUX", "CH1_AMIC2", "AMIC2"},
  3079. {"ADC1 MUX", "CH1_AMIC3", "AMIC3"},
  3080. {"ADC1 MUX", "CH1_AMIC4", "AMIC4"},
  3081. /*ADC-2 (channel-2)*/
  3082. {"ADC2_OUTPUT", NULL, "TX1 SEQUENCER"},
  3083. {"TX1 SEQUENCER", NULL, "ADC2 MUX"},
  3084. {"ADC2 MUX", "CH2_AMIC1", "AMIC1"},
  3085. {"ADC2 MUX", "CH2_AMIC2", "AMIC2"},
  3086. {"ADC2 MUX", "CH2_AMIC3", "AMIC3"},
  3087. {"ADC2 MUX", "CH2_AMIC4", "AMIC4"},
  3088. /*ADC-3 (channel-3)*/
  3089. {"ADC3_OUTPUT", NULL, "TX2 SEQUENCER"},
  3090. {"TX2 SEQUENCER", NULL, "ADC3 MUX"},
  3091. {"ADC3 MUX", "CH3_AMIC1", "AMIC1"},
  3092. {"ADC3 MUX", "CH3_AMIC2", "AMIC2"},
  3093. {"ADC3 MUX", "CH3_AMIC3", "AMIC3"},
  3094. {"ADC3 MUX", "CH3_AMIC4", "AMIC4"},
  3095. {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
  3096. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3097. {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
  3098. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3099. {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
  3100. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3101. {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
  3102. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3103. {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
  3104. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3105. {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
  3106. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3107. /*Headphone playback*/
  3108. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3109. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3110. {"HPH SEQUENCER", NULL, "IN1_HPHL"},
  3111. {"RDAC1", NULL, "HPH SEQUENCER"},
  3112. {"HPHL_RDAC", "Switch", "RDAC1"},
  3113. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3114. {"HPHL", NULL, "HPHL PGA"},
  3115. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3116. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3117. {"HPH SEQUENCER", NULL, "IN2_HPHR"},
  3118. {"RDAC2", NULL, "HPH SEQUENCER"},
  3119. {"HPHR_RDAC", "Switch", "RDAC2"},
  3120. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3121. {"HPHR", NULL, "HPHR PGA"},
  3122. /*Amplier playback*/
  3123. {"IN3_AUX", NULL, "VDD_BUCK"},
  3124. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3125. {"EAR_MUX", "RX0", "IN1_HPHL"},
  3126. {"EAR_MUX", "RX2", "IN3_AUX"},
  3127. {"DAC1", "Switch", "EAR_MUX"},
  3128. {"EAR_RDAC", NULL, "DAC1"},
  3129. {"SA SEQUENCER", NULL, "EAR_RDAC"},
  3130. {"EAR_MIXER", "Switch", "SA SEQUENCER"},
  3131. {"EAR PGA", NULL, "EAR_MIXER"},
  3132. {"EAR", NULL, "EAR PGA"},
  3133. {"AUX_MUX", "RX1", "IN2_HPHR"},
  3134. {"AUX_MUX", "RX2", "IN3_AUX"},
  3135. {"DAC2", "Switch", "AUX_MUX"},
  3136. {"AUX_RDAC", NULL, "DAC2"},
  3137. {"SA SEQUENCER", NULL, "AUX_RDAC"},
  3138. {"AUX_MIXER", "Switch", "SA SEQUENCER",},
  3139. {"AUX PGA", NULL, "AUX_MIXER"},
  3140. {"AUX", NULL, "AUX PGA"},
  3141. };
  3142. static ssize_t wcd9378_version_read(struct snd_info_entry *entry,
  3143. void *file_private_data,
  3144. struct file *file,
  3145. char __user *buf, size_t count,
  3146. loff_t pos)
  3147. {
  3148. struct wcd9378_priv *priv;
  3149. char buffer[WCD9378_VERSION_ENTRY_SIZE];
  3150. int len = 0;
  3151. priv = (struct wcd9378_priv *) entry->private_data;
  3152. if (!priv) {
  3153. pr_err("%s: wcd9378 priv is null\n", __func__);
  3154. return -EINVAL;
  3155. }
  3156. switch (priv->version) {
  3157. case WCD9378_VERSION_1_0:
  3158. len = scnprintf(buffer, sizeof(buffer), "WCD9378_1_0\n");
  3159. break;
  3160. default:
  3161. len = scnprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3162. }
  3163. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3164. }
  3165. static struct snd_info_entry_ops wcd9378_info_ops = {
  3166. .read = wcd9378_version_read,
  3167. };
  3168. /*
  3169. * wcd9378_info_create_codec_entry - creates wcd9378 module
  3170. * @codec_root: The parent directory
  3171. * @component: component instance
  3172. *
  3173. * Creates wcd9378 module, version entry under the given
  3174. * parent directory.
  3175. *
  3176. * Return: 0 on success or negative error code on failure.
  3177. */
  3178. int wcd9378_info_create_codec_entry(struct snd_info_entry *codec_root,
  3179. struct snd_soc_component *component)
  3180. {
  3181. struct snd_info_entry *version_entry;
  3182. struct wcd9378_priv *priv;
  3183. struct snd_soc_card *card;
  3184. if (!codec_root || !component)
  3185. return -EINVAL;
  3186. priv = snd_soc_component_get_drvdata(component);
  3187. if (priv->entry) {
  3188. dev_dbg(priv->dev,
  3189. "%s:wcd9378 module already created\n", __func__);
  3190. return 0;
  3191. }
  3192. card = component->card;
  3193. priv->entry = snd_info_create_module_entry(codec_root->module,
  3194. "wcd9378", codec_root);
  3195. if (!priv->entry) {
  3196. dev_dbg(component->dev, "%s: failed to create wcd9378 entry\n",
  3197. __func__);
  3198. return -ENOMEM;
  3199. }
  3200. priv->entry->mode = S_IFDIR | 0555;
  3201. if (snd_info_register(priv->entry) < 0) {
  3202. snd_info_free_entry(priv->entry);
  3203. return -ENOMEM;
  3204. }
  3205. version_entry = snd_info_create_card_entry(card->snd_card,
  3206. "version",
  3207. priv->entry);
  3208. if (!version_entry) {
  3209. dev_dbg(component->dev, "%s: failed to create wcd9378 version entry\n",
  3210. __func__);
  3211. snd_info_free_entry(priv->entry);
  3212. return -ENOMEM;
  3213. }
  3214. version_entry->private_data = priv;
  3215. version_entry->size = WCD9378_VERSION_ENTRY_SIZE;
  3216. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3217. version_entry->c.ops = &wcd9378_info_ops;
  3218. if (snd_info_register(version_entry) < 0) {
  3219. snd_info_free_entry(version_entry);
  3220. snd_info_free_entry(priv->entry);
  3221. return -ENOMEM;
  3222. }
  3223. priv->version_entry = version_entry;
  3224. return 0;
  3225. }
  3226. EXPORT_SYMBOL_GPL(wcd9378_info_create_codec_entry);
  3227. static void wcd9378_class_load(struct snd_soc_component *component)
  3228. {
  3229. /*SMP AMP CLASS LOADING*/
  3230. snd_soc_component_update_bits(component, WCD9378_FUNC_ACT,
  3231. WCD9378_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3232. usleep_range(20000, 20010);
  3233. snd_soc_component_update_bits(component, WCD9378_SMP_AMP_FUNC_STAT,
  3234. WCD9378_SMP_AMP_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3235. /*SMP JACK CLASS LOADING*/
  3236. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_ACT,
  3237. WCD9378_SMP_JACK_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3238. usleep_range(30000, 30010);
  3239. snd_soc_component_update_bits(component, WCD9378_CMT_GRP_MASK,
  3240. WCD9378_CMT_GRP_MASK_CMT_GRP_MASK_MASK, 0x02);
  3241. snd_soc_component_update_bits(component, WCD9378_SMP_JACK_FUNC_STAT,
  3242. WCD9378_SMP_JACK_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3243. /*SMP MIC0 CLASS LOADING*/
  3244. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_ACT,
  3245. WCD9378_SMP_MIC_CTRL0_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3246. usleep_range(5000, 5010);
  3247. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL0_FUNC_STAT,
  3248. WCD9378_SMP_MIC_CTRL0_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3249. /*SMP MIC1 CLASS LOADING*/
  3250. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_ACT,
  3251. WCD9378_SMP_MIC_CTRL1_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3252. usleep_range(5000, 5010);
  3253. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL1_FUNC_STAT,
  3254. WCD9378_SMP_MIC_CTRL1_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3255. /*SMP MIC2 CLASS LOADING*/
  3256. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_ACT,
  3257. WCD9378_SMP_MIC_CTRL2_FUNC_ACT_FUNC_ACT_MASK, 0x01);
  3258. usleep_range(5000, 5010);
  3259. snd_soc_component_update_bits(component, WCD9378_SMP_MIC_CTRL2_FUNC_STAT,
  3260. WCD9378_SMP_MIC_CTRL2_FUNC_STAT_FUNC_STAT_MASK, 0xFF);
  3261. }
  3262. static void wcd9378_micb_value_convert(struct snd_soc_component *component)
  3263. {
  3264. struct wcd9378_priv *wcd9378 =
  3265. snd_soc_component_get_drvdata(component);
  3266. struct wcd9378_pdata *pdata =
  3267. dev_get_platdata(wcd9378->dev);
  3268. struct wcd9378_micbias_setting *mb = &pdata->micbias;
  3269. mb->micb1_usage_val = wcd9378_micb_usage_value_convert(component,
  3270. mb->micb1_mv, MIC_BIAS_1);
  3271. mb->micb2_usage_val = wcd9378_micb_usage_value_convert(component,
  3272. mb->micb2_mv, MIC_BIAS_2);
  3273. mb->micb3_usage_val = wcd9378_micb_usage_value_convert(component,
  3274. mb->micb3_mv, MIC_BIAS_3);
  3275. pr_debug("%s: micb1_usage: 0x%x, micb2_usage: 0x%x, micb3_usage: 0x%x\n", __func__,
  3276. mb->micb1_usage_val, mb->micb2_usage_val, mb->micb3_usage_val);
  3277. }
  3278. static int wcd9378_wcd_mode_check(struct snd_soc_component *component)
  3279. {
  3280. struct wcd9378_priv *wcd9378 =
  3281. snd_soc_component_get_drvdata(component);
  3282. if (snd_soc_component_read(component,
  3283. WCD9378_EFUSE_REG_29)
  3284. & WCD9378_EFUSE_REG_29_PLATFORM_BLOWN_MASK) {
  3285. if (((snd_soc_component_read(component,
  3286. WCD9378_EFUSE_REG_29) &
  3287. WCD9378_EFUSE_REG_29_PLATFORM_MASK) >> 1) == wcd9378->wcd_mode)
  3288. return true;
  3289. else
  3290. return false;
  3291. } else {
  3292. if ((snd_soc_component_read(component, WCD9378_PLATFORM_CTL)
  3293. & WCD9378_PLATFORM_CTL_MODE_MASK) == wcd9378->wcd_mode)
  3294. return true;
  3295. else
  3296. return false;
  3297. }
  3298. return 0;
  3299. }
  3300. static int wcd9378_soc_codec_probe(struct snd_soc_component *component)
  3301. {
  3302. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3303. struct snd_soc_dapm_context *dapm =
  3304. snd_soc_component_get_dapm(component);
  3305. int ret = -EINVAL;
  3306. wcd9378 = snd_soc_component_get_drvdata(component);
  3307. if (!wcd9378)
  3308. return -EINVAL;
  3309. wcd9378->component = component;
  3310. snd_soc_component_init_regmap(component, wcd9378->regmap);
  3311. devm_regmap_qti_debugfs_register(&wcd9378->tx_swr_dev->dev, wcd9378->regmap);
  3312. ret = wcd9378_wcd_mode_check(component);
  3313. if (!ret) {
  3314. dev_err(component->dev, "wcd mode check failed\n");
  3315. ret = -EINVAL;
  3316. goto exit;
  3317. }
  3318. ret = wcd9378_mbhc_init(&wcd9378->mbhc, component);
  3319. if (ret) {
  3320. pr_err("%s: mbhc initialization failed\n", __func__);
  3321. ret = -EINVAL;
  3322. goto exit;
  3323. }
  3324. dev_dbg(component->dev, "%s: mbhc init done\n", __func__);
  3325. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3326. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3327. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3328. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3329. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3330. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3331. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3332. snd_soc_dapm_ignore_suspend(dapm, "ADC1_OUTPUT");
  3333. snd_soc_dapm_ignore_suspend(dapm, "ADC2_OUTPUT");
  3334. snd_soc_dapm_ignore_suspend(dapm, "ADC3_OUTPUT");
  3335. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3336. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3337. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3338. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3339. snd_soc_dapm_sync(dapm);
  3340. wcd_cls_h_init(&wcd9378->clsh_info);
  3341. wcd9378_init_reg(component);
  3342. wcd9378_micb_value_convert(component);
  3343. wcd9378->version = WCD9378_VERSION_1_0;
  3344. /* Register event notifier */
  3345. wcd9378->nblock.notifier_call = wcd9378_event_notify;
  3346. if (wcd9378->register_notifier) {
  3347. ret = wcd9378->register_notifier(wcd9378->handle,
  3348. &wcd9378->nblock,
  3349. true);
  3350. if (ret) {
  3351. dev_err(component->dev,
  3352. "%s: Failed to register notifier %d\n",
  3353. __func__, ret);
  3354. return ret;
  3355. }
  3356. }
  3357. exit:
  3358. return ret;
  3359. }
  3360. static void wcd9378_soc_codec_remove(struct snd_soc_component *component)
  3361. {
  3362. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3363. if (!wcd9378) {
  3364. dev_err(component->dev, "%s: wcd9378 is already NULL\n",
  3365. __func__);
  3366. return;
  3367. }
  3368. if (wcd9378->register_notifier)
  3369. wcd9378->register_notifier(wcd9378->handle,
  3370. &wcd9378->nblock,
  3371. false);
  3372. }
  3373. static int wcd9378_soc_codec_suspend(struct snd_soc_component *component)
  3374. {
  3375. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3376. if (!wcd9378)
  3377. return 0;
  3378. wcd9378->dapm_bias_off = true;
  3379. return 0;
  3380. }
  3381. static int wcd9378_soc_codec_resume(struct snd_soc_component *component)
  3382. {
  3383. struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
  3384. if (!wcd9378)
  3385. return 0;
  3386. wcd9378->dapm_bias_off = false;
  3387. return 0;
  3388. }
  3389. static const struct snd_soc_component_driver soc_codec_dev_wcd9378 = {
  3390. .name = WCD9378_DRV_NAME,
  3391. .probe = wcd9378_soc_codec_probe,
  3392. .remove = wcd9378_soc_codec_remove,
  3393. .controls = wcd9378_snd_controls,
  3394. .num_controls = ARRAY_SIZE(wcd9378_snd_controls),
  3395. .dapm_widgets = wcd9378_dapm_widgets,
  3396. .num_dapm_widgets = ARRAY_SIZE(wcd9378_dapm_widgets),
  3397. .dapm_routes = wcd9378_audio_map,
  3398. .num_dapm_routes = ARRAY_SIZE(wcd9378_audio_map),
  3399. .suspend = wcd9378_soc_codec_suspend,
  3400. .resume = wcd9378_soc_codec_resume,
  3401. };
  3402. static int wcd9378_reset(struct device *dev)
  3403. {
  3404. struct wcd9378_priv *wcd9378 = NULL;
  3405. int rc = 0;
  3406. int value = 0;
  3407. if (!dev)
  3408. return -ENODEV;
  3409. wcd9378 = dev_get_drvdata(dev);
  3410. if (!wcd9378)
  3411. return -EINVAL;
  3412. if (!wcd9378->rst_np) {
  3413. dev_err(dev, "%s: reset gpio device node not specified\n",
  3414. __func__);
  3415. return -EINVAL;
  3416. }
  3417. value = msm_cdc_pinctrl_get_state(wcd9378->rst_np);
  3418. if (value > 0)
  3419. return 0;
  3420. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3421. if (rc) {
  3422. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3423. __func__);
  3424. return -EPROBE_DEFER;
  3425. }
  3426. /* 20us sleep required after pulling the reset gpio to LOW */
  3427. usleep_range(20, 30);
  3428. rc = msm_cdc_pinctrl_select_active_state(wcd9378->rst_np);
  3429. if (rc) {
  3430. dev_err(dev, "%s: wcd active state request fail!\n",
  3431. __func__);
  3432. return -EPROBE_DEFER;
  3433. }
  3434. /* 20us sleep required after pulling the reset gpio to HIGH */
  3435. usleep_range(20, 30);
  3436. return rc;
  3437. }
  3438. static int wcd9378_read_of_property_u32(struct device *dev, const char *name,
  3439. u32 *val)
  3440. {
  3441. int rc = 0;
  3442. rc = of_property_read_u32(dev->of_node, name, val);
  3443. if (rc)
  3444. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3445. __func__, name, dev->of_node->full_name);
  3446. return rc;
  3447. }
  3448. static void wcd9378_dt_parse_micbias_info(struct device *dev,
  3449. struct wcd9378_micbias_setting *mb)
  3450. {
  3451. u32 prop_val = 0;
  3452. int rc = 0;
  3453. /* MB1 */
  3454. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3455. NULL)) {
  3456. rc = wcd9378_read_of_property_u32(dev,
  3457. "qcom,cdc-micbias1-mv",
  3458. &prop_val);
  3459. if (!rc)
  3460. mb->micb1_mv = prop_val;
  3461. } else {
  3462. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3463. __func__);
  3464. }
  3465. /* MB2 */
  3466. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3467. NULL)) {
  3468. rc = wcd9378_read_of_property_u32(dev,
  3469. "qcom,cdc-micbias2-mv",
  3470. &prop_val);
  3471. if (!rc)
  3472. mb->micb2_mv = prop_val;
  3473. } else {
  3474. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3475. __func__);
  3476. }
  3477. /* MB3 */
  3478. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3479. NULL)) {
  3480. rc = wcd9378_read_of_property_u32(dev,
  3481. "qcom,cdc-micbias3-mv",
  3482. &prop_val);
  3483. if (!rc)
  3484. mb->micb3_mv = prop_val;
  3485. } else {
  3486. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3487. __func__);
  3488. }
  3489. }
  3490. static int wcd9378_reset_low(struct device *dev)
  3491. {
  3492. struct wcd9378_priv *wcd9378 = NULL;
  3493. int rc = 0;
  3494. if (!dev)
  3495. return -ENODEV;
  3496. wcd9378 = dev_get_drvdata(dev);
  3497. if (!wcd9378)
  3498. return -EINVAL;
  3499. if (!wcd9378->rst_np) {
  3500. dev_err(dev, "%s: reset gpio device node not specified\n",
  3501. __func__);
  3502. return -EINVAL;
  3503. }
  3504. rc = msm_cdc_pinctrl_select_sleep_state(wcd9378->rst_np);
  3505. if (rc) {
  3506. dev_err(dev, "%s: wcd sleep state request fail!\n",
  3507. __func__);
  3508. return rc;
  3509. }
  3510. /* 20us sleep required after pulling the reset gpio to LOW */
  3511. usleep_range(20, 30);
  3512. return rc;
  3513. }
  3514. struct wcd9378_pdata *wcd9378_populate_dt_data(struct device *dev)
  3515. {
  3516. struct wcd9378_pdata *pdata = NULL;
  3517. pdata = devm_kzalloc(dev, sizeof(struct wcd9378_pdata),
  3518. GFP_KERNEL);
  3519. if (!pdata)
  3520. return NULL;
  3521. pdata->rst_np = of_parse_phandle(dev->of_node,
  3522. "qcom,wcd-rst-gpio-node", 0);
  3523. if (!pdata->rst_np) {
  3524. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3525. __func__, "qcom,wcd-rst-gpio-node",
  3526. dev->of_node->full_name);
  3527. return NULL;
  3528. }
  3529. /* Parse power supplies */
  3530. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3531. &pdata->num_supplies);
  3532. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3533. dev_err(dev, "%s: no power supplies defined for codec\n",
  3534. __func__);
  3535. return NULL;
  3536. }
  3537. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3538. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3539. wcd9378_dt_parse_micbias_info(dev, &pdata->micbias);
  3540. return pdata;
  3541. }
  3542. static struct snd_soc_dai_driver wcd9378_dai[] = {
  3543. {
  3544. .name = "wcd9378_cdc",
  3545. .playback = {
  3546. .stream_name = "WCD9378_AIF Playback",
  3547. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3548. .formats = WCD9378_FORMATS,
  3549. .rate_max = 384000,
  3550. .rate_min = 8000,
  3551. .channels_min = 1,
  3552. .channels_max = 4,
  3553. },
  3554. .capture = {
  3555. .stream_name = "WCD9378_AIF Capture",
  3556. .rates = WCD9378_RATES | WCD9378_FRAC_RATES,
  3557. .formats = WCD9378_FORMATS,
  3558. .rate_max = 384000,
  3559. .rate_min = 8000,
  3560. .channels_min = 1,
  3561. .channels_max = 4,
  3562. },
  3563. },
  3564. };
  3565. static int wcd9378_bind(struct device *dev)
  3566. {
  3567. int ret = 0;
  3568. struct wcd9378_pdata *pdata = dev_get_platdata(dev);
  3569. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3570. /*
  3571. * Add 5msec delay to provide sufficient time for
  3572. * soundwire auto enumeration of slave devices as
  3573. * per HW requirement.
  3574. */
  3575. usleep_range(5000, 5010);
  3576. ret = component_bind_all(dev, wcd9378);
  3577. if (ret) {
  3578. dev_err(dev, "%s: Slave bind failed, ret = %d\n",
  3579. __func__, ret);
  3580. return ret;
  3581. }
  3582. wcd9378->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3583. if (!wcd9378->rx_swr_dev) {
  3584. dev_err(dev, "%s: Could not find RX swr slave device\n",
  3585. __func__);
  3586. ret = -ENODEV;
  3587. goto err;
  3588. }
  3589. wcd9378->rx_swr_dev->paging_support = true;
  3590. wcd9378->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3591. if (!wcd9378->tx_swr_dev) {
  3592. dev_err(dev, "%s: Could not find TX swr slave device\n",
  3593. __func__);
  3594. ret = -ENODEV;
  3595. goto err;
  3596. }
  3597. wcd9378->tx_swr_dev->paging_support = true;
  3598. swr_init_port_params(wcd9378->tx_swr_dev, SWR_NUM_PORTS,
  3599. wcd9378->swr_tx_port_params);
  3600. wcd9378->regmap = devm_regmap_init_swr(wcd9378->tx_swr_dev,
  3601. &wcd9378_regmap_config);
  3602. if (!wcd9378->regmap) {
  3603. dev_err(dev, "%s: Regmap init failed\n",
  3604. __func__);
  3605. goto err;
  3606. }
  3607. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_1, 0xff);
  3608. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_2, 0x0b);
  3609. regmap_write(wcd9378->regmap, SWRS_SCP_SDCA_INTRTYPE_3, 0xff);
  3610. wcd9378_regmap_irq_chip.irq_drv_data = wcd9378;
  3611. wcd9378->irq_info.wcd_regmap_irq_chip = &wcd9378_regmap_irq_chip;
  3612. wcd9378->irq_info.codec_name = "WCD9378";
  3613. wcd9378->irq_info.regmap = wcd9378->regmap;
  3614. wcd9378->irq_info.dev = dev;
  3615. ret = wcd_irq_init(&wcd9378->irq_info, &wcd9378->virq);
  3616. if (ret) {
  3617. dev_err(wcd9378->dev, "%s: IRQ init failed: %d\n",
  3618. __func__, ret);
  3619. goto err;
  3620. }
  3621. dev_err(wcd9378->dev, "%s: wcd irq init done\n",
  3622. __func__);
  3623. wcd9378->tx_swr_dev->slave_irq = wcd9378->virq;
  3624. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd9378,
  3625. wcd9378_dai, ARRAY_SIZE(wcd9378_dai));
  3626. if (ret) {
  3627. dev_err(dev, "%s: Codec registration failed\n",
  3628. __func__);
  3629. goto err_irq;
  3630. }
  3631. wcd9378->dev_up = true;
  3632. return ret;
  3633. err_irq:
  3634. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3635. err:
  3636. component_unbind_all(dev, wcd9378);
  3637. return ret;
  3638. }
  3639. static void wcd9378_unbind(struct device *dev)
  3640. {
  3641. struct wcd9378_priv *wcd9378 = dev_get_drvdata(dev);
  3642. wcd_irq_exit(&wcd9378->irq_info, wcd9378->virq);
  3643. snd_soc_unregister_component(dev);
  3644. component_unbind_all(dev, wcd9378);
  3645. }
  3646. static const struct of_device_id wcd9378_dt_match[] = {
  3647. { .compatible = "qcom,wcd9378-codec", .data = "wcd9378"},
  3648. {}
  3649. };
  3650. static const struct component_master_ops wcd9378_comp_ops = {
  3651. .bind = wcd9378_bind,
  3652. .unbind = wcd9378_unbind,
  3653. };
  3654. static int wcd9378_compare_of(struct device *dev, void *data)
  3655. {
  3656. return dev->of_node == data;
  3657. }
  3658. static void wcd9378_release_of(struct device *dev, void *data)
  3659. {
  3660. of_node_put(data);
  3661. }
  3662. static int wcd9378_add_slave_components(struct device *dev,
  3663. struct component_match **matchptr)
  3664. {
  3665. struct device_node *np, *rx_node, *tx_node;
  3666. np = dev->of_node;
  3667. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3668. if (!rx_node) {
  3669. dev_err(dev, "%s: Rx-slave node not defined\n", __func__);
  3670. return -ENODEV;
  3671. }
  3672. of_node_get(rx_node);
  3673. component_match_add_release(dev, matchptr,
  3674. wcd9378_release_of,
  3675. wcd9378_compare_of,
  3676. rx_node);
  3677. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3678. if (!tx_node) {
  3679. dev_err(dev, "%s: Tx-slave node not defined\n", __func__);
  3680. return -ENODEV;
  3681. }
  3682. of_node_get(tx_node);
  3683. component_match_add_release(dev, matchptr,
  3684. wcd9378_release_of,
  3685. wcd9378_compare_of,
  3686. tx_node);
  3687. return 0;
  3688. }
  3689. static int wcd9378_probe(struct platform_device *pdev)
  3690. {
  3691. struct component_match *match = NULL;
  3692. struct wcd9378_priv *wcd9378 = NULL;
  3693. struct wcd9378_pdata *pdata = NULL;
  3694. struct wcd_ctrl_platform_data *plat_data = NULL;
  3695. struct device *dev = &pdev->dev;
  3696. int ret;
  3697. wcd9378 = devm_kzalloc(dev, sizeof(struct wcd9378_priv),
  3698. GFP_KERNEL);
  3699. if (!wcd9378)
  3700. return -ENOMEM;
  3701. dev_set_drvdata(dev, wcd9378);
  3702. wcd9378->dev = dev;
  3703. pdata = wcd9378_populate_dt_data(dev);
  3704. if (!pdata) {
  3705. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  3706. return -EINVAL;
  3707. }
  3708. dev->platform_data = pdata;
  3709. wcd9378->rst_np = pdata->rst_np;
  3710. ret = msm_cdc_init_supplies(dev, &wcd9378->supplies,
  3711. pdata->regulator, pdata->num_supplies);
  3712. if (!wcd9378->supplies) {
  3713. dev_err(dev, "%s: Cannot init wcd supplies\n",
  3714. __func__);
  3715. return ret;
  3716. }
  3717. plat_data = dev_get_platdata(dev->parent);
  3718. if (!plat_data) {
  3719. dev_err(dev, "%s: platform data from parent is NULL\n",
  3720. __func__);
  3721. return -EINVAL;
  3722. }
  3723. wcd9378->handle = (void *)plat_data->handle;
  3724. if (!wcd9378->handle) {
  3725. dev_err(dev, "%s: handle is NULL\n", __func__);
  3726. return -EINVAL;
  3727. }
  3728. wcd9378->update_wcd_event = plat_data->update_wcd_event;
  3729. if (!wcd9378->update_wcd_event) {
  3730. dev_err(dev, "%s: update_wcd_event api is null!\n",
  3731. __func__);
  3732. return -EINVAL;
  3733. }
  3734. wcd9378->register_notifier = plat_data->register_notifier;
  3735. if (!wcd9378->register_notifier) {
  3736. dev_err(dev, "%s: register_notifier api is null!\n",
  3737. __func__);
  3738. return -EINVAL;
  3739. }
  3740. ret = of_property_read_u32(dev->of_node, "qcom,wcd-mode",
  3741. &wcd9378->wcd_mode);
  3742. if (ret) {
  3743. dev_dbg(dev, "%s: wcd-mode read failed, use mobile mode\n",
  3744. __func__);
  3745. wcd9378->wcd_mode = WCD9378_MOBILE_MODE;
  3746. }
  3747. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd9378->supplies,
  3748. pdata->regulator,
  3749. pdata->num_supplies);
  3750. if (ret) {
  3751. dev_err(dev, "%s: wcd static supply enable failed!\n",
  3752. __func__);
  3753. return ret;
  3754. }
  3755. ret = wcd9378_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  3756. CODEC_RX);
  3757. ret |= wcd9378_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  3758. CODEC_TX);
  3759. if (ret) {
  3760. dev_err(dev, "Failed to read port mapping\n");
  3761. goto err;
  3762. }
  3763. ret = wcd9378_parse_port_params(dev, "qcom,swr-tx-port-params",
  3764. CODEC_TX);
  3765. if (ret) {
  3766. dev_err(dev, "Failed to read port params\n");
  3767. goto err;
  3768. }
  3769. mutex_init(&wcd9378->wakeup_lock);
  3770. mutex_init(&wcd9378->micb_lock);
  3771. ret = wcd9378_add_slave_components(dev, &match);
  3772. if (ret)
  3773. goto err_lock_init;
  3774. ret = wcd9378_reset(dev);
  3775. if (ret == -EPROBE_DEFER) {
  3776. dev_err(dev, "%s: wcd reset failed!\n", __func__);
  3777. goto err_lock_init;
  3778. }
  3779. wcd9378->wakeup = wcd9378_wakeup;
  3780. return component_master_add_with_match(dev,
  3781. &wcd9378_comp_ops, match);
  3782. err_lock_init:
  3783. mutex_destroy(&wcd9378->micb_lock);
  3784. mutex_destroy(&wcd9378->wakeup_lock);
  3785. err:
  3786. return ret;
  3787. }
  3788. static int wcd9378_remove(struct platform_device *pdev)
  3789. {
  3790. struct wcd9378_priv *wcd9378 = NULL;
  3791. wcd9378 = platform_get_drvdata(pdev);
  3792. component_master_del(&pdev->dev, &wcd9378_comp_ops);
  3793. mutex_destroy(&wcd9378->micb_lock);
  3794. mutex_destroy(&wcd9378->wakeup_lock);
  3795. dev_set_drvdata(&pdev->dev, NULL);
  3796. return 0;
  3797. }
  3798. #ifdef CONFIG_PM_SLEEP
  3799. static int wcd9378_suspend(struct device *dev)
  3800. {
  3801. struct wcd9378_priv *wcd9378 = NULL;
  3802. int ret = 0;
  3803. struct wcd9378_pdata *pdata = NULL;
  3804. if (!dev)
  3805. return -ENODEV;
  3806. wcd9378 = dev_get_drvdata(dev);
  3807. if (!wcd9378)
  3808. return -EINVAL;
  3809. pdata = dev_get_platdata(wcd9378->dev);
  3810. if (!pdata) {
  3811. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3812. return -EINVAL;
  3813. }
  3814. if (test_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask)) {
  3815. ret = msm_cdc_disable_ondemand_supply(wcd9378->dev,
  3816. wcd9378->supplies,
  3817. pdata->regulator,
  3818. pdata->num_supplies,
  3819. "cdc-vdd-buck");
  3820. if (ret == -EINVAL) {
  3821. dev_err(dev, "%s: vdd buck is not disabled\n",
  3822. __func__);
  3823. return 0;
  3824. }
  3825. clear_bit(ALLOW_BUCK_DISABLE, &wcd9378->status_mask);
  3826. }
  3827. if (wcd9378->dapm_bias_off) {
  3828. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3829. wcd9378->supplies,
  3830. pdata->regulator,
  3831. pdata->num_supplies,
  3832. true);
  3833. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3834. }
  3835. return 0;
  3836. }
  3837. static int wcd9378_resume(struct device *dev)
  3838. {
  3839. struct wcd9378_priv *wcd9378 = NULL;
  3840. struct wcd9378_pdata *pdata = NULL;
  3841. if (!dev)
  3842. return -ENODEV;
  3843. wcd9378 = dev_get_drvdata(dev);
  3844. if (!wcd9378)
  3845. return -EINVAL;
  3846. pdata = dev_get_platdata(wcd9378->dev);
  3847. if (!pdata) {
  3848. dev_err(dev, "%s: pdata is NULL\n", __func__);
  3849. return -EINVAL;
  3850. }
  3851. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask)) {
  3852. msm_cdc_set_supplies_lpm_mode(wcd9378->dev,
  3853. wcd9378->supplies,
  3854. pdata->regulator,
  3855. pdata->num_supplies,
  3856. false);
  3857. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd9378->status_mask);
  3858. }
  3859. return 0;
  3860. }
  3861. static const struct dev_pm_ops wcd9378_dev_pm_ops = {
  3862. .suspend_late = wcd9378_suspend,
  3863. .resume_early = wcd9378_resume,
  3864. };
  3865. #endif
  3866. static struct platform_driver wcd9378_codec_driver = {
  3867. .probe = wcd9378_probe,
  3868. .remove = wcd9378_remove,
  3869. .driver = {
  3870. .name = "wcd9378_codec",
  3871. .of_match_table = of_match_ptr(wcd9378_dt_match),
  3872. #ifdef CONFIG_PM_SLEEP
  3873. .pm = &wcd9378_dev_pm_ops,
  3874. #endif
  3875. .suppress_bind_attrs = true,
  3876. },
  3877. };
  3878. module_platform_driver(wcd9378_codec_driver);
  3879. MODULE_DESCRIPTION("WCD9378 Codec driver");
  3880. MODULE_LICENSE("GPL");