dp_ctrl.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/types.h>
  6. #include <linux/completion.h>
  7. #include <linux/delay.h>
  8. #include <drm/drm_fixed.h>
  9. #include <linux/version.h>
  10. #include "dp_ctrl.h"
  11. #include "dp_debug.h"
  12. #include "sde_dbg.h"
  13. #define DP_MST_DEBUG(fmt, ...) DP_DEBUG(fmt, ##__VA_ARGS__)
  14. #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
  15. #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3)
  16. #define DP_CTRL_INTR_MST_DP0_VCPF_SENT BIT(0)
  17. #define DP_CTRL_INTR_MST_DP1_VCPF_SENT BIT(3)
  18. /* dp state ctrl */
  19. #define ST_TRAIN_PATTERN_1 BIT(0)
  20. #define ST_TRAIN_PATTERN_2 BIT(1)
  21. #define ST_TRAIN_PATTERN_3 BIT(2)
  22. #define ST_TRAIN_PATTERN_4 BIT(3)
  23. #define ST_SYMBOL_ERR_RATE_MEASUREMENT BIT(4)
  24. #define ST_PRBS7 BIT(5)
  25. #define ST_CUSTOM_80_BIT_PATTERN BIT(6)
  26. #define ST_SEND_VIDEO BIT(7)
  27. #define ST_PUSH_IDLE BIT(8)
  28. #define MST_DP0_PUSH_VCPF BIT(12)
  29. #define MST_DP0_FORCE_VCPF BIT(13)
  30. #define MST_DP1_PUSH_VCPF BIT(14)
  31. #define MST_DP1_FORCE_VCPF BIT(15)
  32. #define MR_LINK_TRAINING1 0x8
  33. #define MR_LINK_SYMBOL_ERM 0x80
  34. #define MR_LINK_PRBS7 0x100
  35. #define MR_LINK_CUSTOM80 0x200
  36. #define MR_LINK_TRAINING4 0x40
  37. #define DP_MAX_LANES 4
  38. struct dp_mst_ch_slot_info {
  39. u32 start_slot;
  40. u32 tot_slots;
  41. };
  42. struct dp_mst_channel_info {
  43. struct dp_mst_ch_slot_info slot_info[DP_STREAM_MAX];
  44. };
  45. struct dp_ctrl_private {
  46. struct dp_ctrl dp_ctrl;
  47. struct device *dev;
  48. struct dp_aux *aux;
  49. struct dp_panel *panel;
  50. struct dp_link *link;
  51. struct dp_power *power;
  52. struct dp_parser *parser;
  53. struct dp_catalog_ctrl *catalog;
  54. struct dp_pll *pll;
  55. struct completion idle_comp;
  56. struct completion video_comp;
  57. bool orientation;
  58. bool power_on;
  59. bool mst_mode;
  60. bool fec_mode;
  61. bool dsc_mode;
  62. bool sim_mode;
  63. atomic_t aborted;
  64. u8 initial_lane_count;
  65. u8 initial_bw_code;
  66. u32 vic;
  67. u32 stream_count;
  68. u32 training_2_pattern;
  69. struct dp_mst_channel_info mst_ch_info;
  70. };
  71. enum notification_status {
  72. NOTIFY_UNKNOWN,
  73. NOTIFY_CONNECT,
  74. NOTIFY_DISCONNECT,
  75. NOTIFY_CONNECT_IRQ_HPD,
  76. NOTIFY_DISCONNECT_IRQ_HPD,
  77. };
  78. static void dp_ctrl_idle_patterns_sent(struct dp_ctrl_private *ctrl)
  79. {
  80. complete(&ctrl->idle_comp);
  81. }
  82. static void dp_ctrl_video_ready(struct dp_ctrl_private *ctrl)
  83. {
  84. complete(&ctrl->video_comp);
  85. }
  86. static void dp_ctrl_abort(struct dp_ctrl *dp_ctrl, bool abort)
  87. {
  88. struct dp_ctrl_private *ctrl;
  89. if (!dp_ctrl) {
  90. DP_ERR("Invalid input data\n");
  91. return;
  92. }
  93. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  94. atomic_set(&ctrl->aborted, abort);
  95. }
  96. static void dp_ctrl_state_ctrl(struct dp_ctrl_private *ctrl, u32 state)
  97. {
  98. ctrl->catalog->state_ctrl(ctrl->catalog, state);
  99. }
  100. static void dp_ctrl_push_idle(struct dp_ctrl_private *ctrl,
  101. enum dp_stream_id strm)
  102. {
  103. int const idle_pattern_completion_timeout_ms = HZ / 10;
  104. u32 state = 0x0;
  105. if (!ctrl->power_on)
  106. return;
  107. if (!ctrl->mst_mode) {
  108. state = ST_PUSH_IDLE;
  109. goto trigger_idle;
  110. }
  111. if (strm >= DP_STREAM_MAX) {
  112. DP_ERR("mst push idle, invalid stream:%d\n", strm);
  113. return;
  114. }
  115. state |= (strm == DP_STREAM_0) ? MST_DP0_PUSH_VCPF : MST_DP1_PUSH_VCPF;
  116. trigger_idle:
  117. reinit_completion(&ctrl->idle_comp);
  118. dp_ctrl_state_ctrl(ctrl, state);
  119. if (!wait_for_completion_timeout(&ctrl->idle_comp,
  120. idle_pattern_completion_timeout_ms))
  121. DP_WARN("time out\n");
  122. else
  123. DP_DEBUG("mainlink off done\n");
  124. }
  125. /**
  126. * dp_ctrl_configure_source_link_params() - configures DP TX source params
  127. * @ctrl: Display Port Driver data
  128. * @enable: enable or disable DP transmitter
  129. *
  130. * Configures the DP transmitter source params including details such as lane
  131. * configuration, output format and sink/panel timing information.
  132. */
  133. static void dp_ctrl_configure_source_link_params(struct dp_ctrl_private *ctrl,
  134. bool enable)
  135. {
  136. if (!ctrl->power->clk_status(ctrl->power, DP_LINK_PM)) {
  137. DP_WARN("DP link clocks are off\n");
  138. return;
  139. }
  140. if (!ctrl->power->clk_status(ctrl->power, DP_CORE_PM)) {
  141. DP_WARN("DP core clocks are off\n");
  142. return;
  143. }
  144. if (enable) {
  145. ctrl->catalog->lane_mapping(ctrl->catalog, ctrl->orientation,
  146. ctrl->parser->l_map);
  147. ctrl->catalog->lane_pnswap(ctrl->catalog,
  148. ctrl->parser->l_pnswap);
  149. ctrl->catalog->mst_config(ctrl->catalog, ctrl->mst_mode);
  150. ctrl->catalog->config_ctrl(ctrl->catalog,
  151. ctrl->link->link_params.lane_count);
  152. ctrl->catalog->mainlink_levels(ctrl->catalog,
  153. ctrl->link->link_params.lane_count);
  154. ctrl->catalog->mainlink_ctrl(ctrl->catalog, true);
  155. } else {
  156. ctrl->catalog->mainlink_ctrl(ctrl->catalog, false);
  157. }
  158. }
  159. static void dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl)
  160. {
  161. if (!wait_for_completion_timeout(&ctrl->video_comp, HZ / 2))
  162. DP_WARN("SEND_VIDEO time out\n");
  163. else
  164. DP_DEBUG("SEND_VIDEO triggered\n");
  165. }
  166. static int dp_ctrl_update_sink_vx_px(struct dp_ctrl_private *ctrl)
  167. {
  168. int i, ret;
  169. u8 buf[DP_MAX_LANES];
  170. u8 v_level = ctrl->link->phy_params.v_level;
  171. u8 p_level = ctrl->link->phy_params.p_level;
  172. u8 size = min_t(u8, sizeof(buf), ctrl->link->link_params.lane_count);
  173. u32 max_level_reached = 0;
  174. if (v_level == ctrl->link->phy_params.max_v_level) {
  175. DP_DEBUG("max voltage swing level reached %d\n", v_level);
  176. max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
  177. }
  178. if (p_level == ctrl->link->phy_params.max_p_level) {
  179. DP_DEBUG("max pre-emphasis level reached %d\n", p_level);
  180. max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  181. }
  182. p_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT;
  183. for (i = 0; i < size; i++)
  184. buf[i] = v_level | p_level | max_level_reached;
  185. DP_DEBUG("lanes: %d, swing: 0x%x, pre-emp: 0x%x\n",
  186. size, v_level, p_level);
  187. ret = drm_dp_dpcd_write(ctrl->aux->drm_aux,
  188. DP_TRAINING_LANE0_SET, buf, size);
  189. return ret <= 0 ? -EINVAL : 0;
  190. }
  191. static void dp_ctrl_update_hw_vx_px(struct dp_ctrl_private *ctrl)
  192. {
  193. struct dp_link *link = ctrl->link;
  194. bool high = false;
  195. if (ctrl->link->link_params.bw_code == DP_LINK_BW_5_4 ||
  196. ctrl->link->link_params.bw_code == DP_LINK_BW_8_1)
  197. high = true;
  198. ctrl->catalog->update_vx_px(ctrl->catalog,
  199. link->phy_params.v_level, link->phy_params.p_level, high);
  200. }
  201. static int dp_ctrl_update_sink_pattern(struct dp_ctrl_private *ctrl, u8 pattern)
  202. {
  203. u8 buf = pattern;
  204. int ret;
  205. DP_DEBUG("sink: pattern=%x\n", pattern);
  206. if (pattern && pattern != DP_TRAINING_PATTERN_4)
  207. buf |= DP_LINK_SCRAMBLING_DISABLE;
  208. ret = drm_dp_dpcd_writeb(ctrl->aux->drm_aux,
  209. DP_TRAINING_PATTERN_SET, buf);
  210. return ret <= 0 ? -EINVAL : 0;
  211. }
  212. static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl,
  213. u8 *link_status)
  214. {
  215. int ret = 0, len;
  216. u32 const offset = DP_LANE_ALIGN_STATUS_UPDATED - DP_LANE0_1_STATUS;
  217. u32 link_status_read_max_retries = 100;
  218. while (--link_status_read_max_retries) {
  219. len = drm_dp_dpcd_read_link_status(ctrl->aux->drm_aux,
  220. link_status);
  221. if (len != DP_LINK_STATUS_SIZE) {
  222. DP_ERR("DP link status read failed, err: %d\n", len);
  223. ret = len;
  224. break;
  225. }
  226. if (!(link_status[offset] & DP_LINK_STATUS_UPDATED))
  227. break;
  228. }
  229. return ret;
  230. }
  231. static int dp_ctrl_lane_count_down_shift(struct dp_ctrl_private *ctrl)
  232. {
  233. int ret = -EAGAIN;
  234. u8 lanes = ctrl->link->link_params.lane_count;
  235. if (ctrl->panel->link_info.revision != 0x14)
  236. return -EINVAL;
  237. switch (lanes) {
  238. case 4:
  239. ctrl->link->link_params.lane_count = 2;
  240. break;
  241. case 2:
  242. ctrl->link->link_params.lane_count = 1;
  243. break;
  244. default:
  245. if (lanes != ctrl->initial_lane_count)
  246. ret = -EINVAL;
  247. break;
  248. }
  249. DP_DEBUG("new lane count=%d\n", ctrl->link->link_params.lane_count);
  250. return ret;
  251. }
  252. static bool dp_ctrl_is_link_rate_rbr(struct dp_ctrl_private *ctrl)
  253. {
  254. return ctrl->link->link_params.bw_code == DP_LINK_BW_1_62;
  255. }
  256. static u8 dp_ctrl_get_active_lanes(struct dp_ctrl_private *ctrl,
  257. u8 *link_status)
  258. {
  259. u8 lane, count = 0;
  260. for (lane = 0; lane < ctrl->link->link_params.lane_count; lane++) {
  261. if (link_status[lane / 2] & (1 << (lane * 4)))
  262. count++;
  263. else
  264. break;
  265. }
  266. return count;
  267. }
  268. static int dp_ctrl_link_training_1(struct dp_ctrl_private *ctrl)
  269. {
  270. int tries, old_v_level, ret = -EINVAL;
  271. u8 link_status[DP_LINK_STATUS_SIZE];
  272. u8 pattern = 0;
  273. int const maximum_retries = 5;
  274. ctrl->aux->state &= ~DP_STATE_TRAIN_1_FAILED;
  275. ctrl->aux->state &= ~DP_STATE_TRAIN_1_SUCCEEDED;
  276. ctrl->aux->state |= DP_STATE_TRAIN_1_STARTED;
  277. if (ctrl->sim_mode) {
  278. DP_DEBUG("simulation enabled, skip clock recovery\n");
  279. ret = 0;
  280. goto skip_training;
  281. }
  282. dp_ctrl_state_ctrl(ctrl, 0);
  283. /* Make sure to clear the current pattern before starting a new one */
  284. wmb();
  285. tries = 0;
  286. old_v_level = ctrl->link->phy_params.v_level;
  287. while (!atomic_read(&ctrl->aborted)) {
  288. /* update hardware with current swing/pre-emp values */
  289. dp_ctrl_update_hw_vx_px(ctrl);
  290. if (!pattern) {
  291. pattern = DP_TRAINING_PATTERN_1;
  292. ctrl->catalog->set_pattern(ctrl->catalog, pattern);
  293. /* update sink with current settings */
  294. ret = dp_ctrl_update_sink_pattern(ctrl, pattern);
  295. if (ret)
  296. break;
  297. }
  298. ret = dp_ctrl_update_sink_vx_px(ctrl);
  299. if (ret)
  300. break;
  301. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  302. drm_dp_link_train_clock_recovery_delay(ctrl->aux->drm_aux, ctrl->panel->dpcd);
  303. #else
  304. drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd);
  305. #endif
  306. ret = dp_ctrl_read_link_status(ctrl, link_status);
  307. if (ret)
  308. break;
  309. if (!drm_dp_clock_recovery_ok(link_status,
  310. ctrl->link->link_params.lane_count))
  311. ret = -EINVAL;
  312. else
  313. break;
  314. if (ctrl->link->phy_params.v_level == ctrl->link->phy_params.max_v_level) {
  315. pr_err_ratelimited("max v_level reached\n");
  316. break;
  317. }
  318. if (old_v_level == ctrl->link->phy_params.v_level) {
  319. if (++tries >= maximum_retries) {
  320. DP_ERR("max tries reached\n");
  321. ret = -ETIMEDOUT;
  322. break;
  323. }
  324. } else {
  325. tries = 0;
  326. old_v_level = ctrl->link->phy_params.v_level;
  327. }
  328. DP_DEBUG("clock recovery not done, adjusting vx px\n");
  329. ctrl->link->adjust_levels(ctrl->link, link_status);
  330. }
  331. if (ret && dp_ctrl_is_link_rate_rbr(ctrl)) {
  332. u8 active_lanes = dp_ctrl_get_active_lanes(ctrl, link_status);
  333. if (active_lanes) {
  334. ctrl->link->link_params.lane_count = active_lanes;
  335. ctrl->link->link_params.bw_code = ctrl->initial_bw_code;
  336. /* retry with new settings */
  337. ret = -EAGAIN;
  338. }
  339. }
  340. skip_training:
  341. ctrl->aux->state &= ~DP_STATE_TRAIN_1_STARTED;
  342. if (ret)
  343. ctrl->aux->state |= DP_STATE_TRAIN_1_FAILED;
  344. else
  345. ctrl->aux->state |= DP_STATE_TRAIN_1_SUCCEEDED;
  346. return ret;
  347. }
  348. static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl)
  349. {
  350. int ret = 0;
  351. if (!ctrl)
  352. return -EINVAL;
  353. switch (ctrl->link->link_params.bw_code) {
  354. case DP_LINK_BW_8_1:
  355. ctrl->link->link_params.bw_code = DP_LINK_BW_5_4;
  356. break;
  357. case DP_LINK_BW_5_4:
  358. ctrl->link->link_params.bw_code = DP_LINK_BW_2_7;
  359. break;
  360. case DP_LINK_BW_2_7:
  361. case DP_LINK_BW_1_62:
  362. default:
  363. ctrl->link->link_params.bw_code = DP_LINK_BW_1_62;
  364. break;
  365. }
  366. DP_DEBUG("new bw code=0x%x\n", ctrl->link->link_params.bw_code);
  367. return ret;
  368. }
  369. static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl)
  370. {
  371. dp_ctrl_update_sink_pattern(ctrl, 0);
  372. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  373. drm_dp_link_train_channel_eq_delay(ctrl->aux->drm_aux, ctrl->panel->dpcd);
  374. #else
  375. drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd);
  376. #endif
  377. }
  378. static int dp_ctrl_link_training_2(struct dp_ctrl_private *ctrl)
  379. {
  380. int tries = 0, ret = -EINVAL;
  381. u8 dpcd_pattern, pattern = 0;
  382. int const maximum_retries = 5;
  383. u8 link_status[DP_LINK_STATUS_SIZE];
  384. ctrl->aux->state &= ~DP_STATE_TRAIN_2_FAILED;
  385. ctrl->aux->state &= ~DP_STATE_TRAIN_2_SUCCEEDED;
  386. ctrl->aux->state |= DP_STATE_TRAIN_2_STARTED;
  387. if (ctrl->sim_mode) {
  388. DP_DEBUG("simulation enabled, skip channel equalization\n");
  389. ret = 0;
  390. goto skip_training;
  391. }
  392. dp_ctrl_state_ctrl(ctrl, 0);
  393. /* Make sure to clear the current pattern before starting a new one */
  394. wmb();
  395. dpcd_pattern = ctrl->training_2_pattern;
  396. while (!atomic_read(&ctrl->aborted)) {
  397. /* update hardware with current swing/pre-emp values */
  398. dp_ctrl_update_hw_vx_px(ctrl);
  399. if (!pattern) {
  400. pattern = dpcd_pattern;
  401. /* program hw to send pattern */
  402. ctrl->catalog->set_pattern(ctrl->catalog, pattern);
  403. /* update sink with current pattern */
  404. ret = dp_ctrl_update_sink_pattern(ctrl, pattern);
  405. if (ret)
  406. break;
  407. }
  408. ret = dp_ctrl_update_sink_vx_px(ctrl);
  409. if (ret)
  410. break;
  411. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  412. drm_dp_link_train_channel_eq_delay(ctrl->aux->drm_aux, ctrl->panel->dpcd);
  413. #else
  414. drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd);
  415. #endif
  416. ret = dp_ctrl_read_link_status(ctrl, link_status);
  417. if (ret)
  418. break;
  419. /* check if CR bits still remain set */
  420. if (!drm_dp_clock_recovery_ok(link_status,
  421. ctrl->link->link_params.lane_count)) {
  422. ret = -EINVAL;
  423. break;
  424. }
  425. if (!drm_dp_channel_eq_ok(link_status,
  426. ctrl->link->link_params.lane_count))
  427. ret = -EINVAL;
  428. else
  429. break;
  430. if (tries >= maximum_retries) {
  431. ret = dp_ctrl_lane_count_down_shift(ctrl);
  432. break;
  433. }
  434. tries++;
  435. ctrl->link->adjust_levels(ctrl->link, link_status);
  436. }
  437. skip_training:
  438. ctrl->aux->state &= ~DP_STATE_TRAIN_2_STARTED;
  439. if (ret)
  440. ctrl->aux->state |= DP_STATE_TRAIN_2_FAILED;
  441. else
  442. ctrl->aux->state |= DP_STATE_TRAIN_2_SUCCEEDED;
  443. return ret;
  444. }
  445. static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl)
  446. {
  447. int ret = 0;
  448. u8 const encoding = 0x1, downspread = 0x00;
  449. struct drm_dp_link link_info = {0};
  450. ctrl->link->phy_params.p_level = 0;
  451. ctrl->link->phy_params.v_level = 0;
  452. link_info.num_lanes = ctrl->link->link_params.lane_count;
  453. link_info.rate = drm_dp_bw_code_to_link_rate(
  454. ctrl->link->link_params.bw_code);
  455. link_info.capabilities = ctrl->panel->link_info.capabilities;
  456. ret = dp_link_configure(ctrl->aux->drm_aux, &link_info);
  457. if (ret)
  458. goto end;
  459. ret = drm_dp_dpcd_writeb(ctrl->aux->drm_aux,
  460. DP_DOWNSPREAD_CTRL, downspread);
  461. if (ret <= 0) {
  462. ret = -EINVAL;
  463. goto end;
  464. }
  465. ret = drm_dp_dpcd_writeb(ctrl->aux->drm_aux,
  466. DP_MAIN_LINK_CHANNEL_CODING_SET, encoding);
  467. if (ret <= 0) {
  468. ret = -EINVAL;
  469. goto end;
  470. }
  471. /* disable FEC before link training */
  472. ctrl->catalog->fec_config(ctrl->catalog, false);
  473. ret = dp_ctrl_link_training_1(ctrl);
  474. if (ret) {
  475. DP_ERR("link training #1 failed\n");
  476. goto end;
  477. }
  478. /* print success info as this is a result of user initiated action */
  479. DP_INFO("link training #1 successful\n");
  480. ret = dp_ctrl_link_training_2(ctrl);
  481. if (ret) {
  482. DP_ERR("link training #2 failed\n");
  483. goto end;
  484. }
  485. /* print success info as this is a result of user initiated action */
  486. DP_INFO("link training #2 successful\n");
  487. end:
  488. dp_ctrl_state_ctrl(ctrl, 0);
  489. /* Make sure to clear the current pattern before starting a new one */
  490. wmb();
  491. dp_ctrl_clear_training_pattern(ctrl);
  492. return ret;
  493. }
  494. static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl)
  495. {
  496. int ret = 0;
  497. if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
  498. goto end;
  499. /*
  500. * As part of previous calls, DP controller state might have
  501. * transitioned to PUSH_IDLE. In order to start transmitting a link
  502. * training pattern, we have to first to a DP software reset.
  503. */
  504. ctrl->catalog->reset(ctrl->catalog);
  505. if (ctrl->fec_mode)
  506. drm_dp_dpcd_writeb(ctrl->aux->drm_aux, DP_FEC_CONFIGURATION,
  507. 0x01);
  508. ret = dp_ctrl_link_train(ctrl);
  509. end:
  510. return ret;
  511. }
  512. static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
  513. char *name, enum dp_pm_type clk_type, u32 rate)
  514. {
  515. u32 num = ctrl->parser->mp[clk_type].num_clk;
  516. struct dss_clk *cfg = ctrl->parser->mp[clk_type].clk_config;
  517. while (num && strcmp(cfg->clk_name, name)) {
  518. num--;
  519. cfg++;
  520. }
  521. DP_DEBUG("setting rate=%d on clk=%s\n", rate, name);
  522. if (num)
  523. cfg->rate = rate;
  524. else
  525. DP_ERR("%s clock could not be set with rate %d\n", name, rate);
  526. }
  527. static int dp_ctrl_enable_link_clock(struct dp_ctrl_private *ctrl)
  528. {
  529. int ret = 0;
  530. u32 rate = drm_dp_bw_code_to_link_rate(ctrl->link->link_params.bw_code);
  531. enum dp_pm_type type = DP_LINK_PM;
  532. DP_DEBUG("rate=%d\n", rate);
  533. dp_ctrl_set_clock_rate(ctrl, "link_clk_src", type, rate);
  534. if (ctrl->pll->pll_cfg) {
  535. ret = ctrl->pll->pll_cfg(ctrl->pll, rate);
  536. if (ret < 0) {
  537. DP_ERR("DP pll cfg failed\n");
  538. return ret;
  539. }
  540. }
  541. if (ctrl->pll->pll_prepare) {
  542. ret = ctrl->pll->pll_prepare(ctrl->pll);
  543. if (ret < 0) {
  544. DP_ERR("DP pll prepare failed\n");
  545. return ret;
  546. }
  547. }
  548. ret = ctrl->power->clk_enable(ctrl->power, type, true);
  549. if (ret) {
  550. DP_ERR("Unabled to start link clocks\n");
  551. ret = -EINVAL;
  552. }
  553. return ret;
  554. }
  555. static void dp_ctrl_disable_link_clock(struct dp_ctrl_private *ctrl)
  556. {
  557. int rc = 0;
  558. ctrl->power->clk_enable(ctrl->power, DP_LINK_PM, false);
  559. if (ctrl->pll->pll_unprepare) {
  560. rc = ctrl->pll->pll_unprepare(ctrl->pll);
  561. if (rc < 0)
  562. DP_ERR("pll unprepare failed\n");
  563. }
  564. }
  565. static void dp_ctrl_select_training_pattern(struct dp_ctrl_private *ctrl,
  566. bool downgrade)
  567. {
  568. u32 pattern;
  569. if (drm_dp_tps4_supported(ctrl->panel->dpcd))
  570. pattern = DP_TRAINING_PATTERN_4;
  571. else if (drm_dp_tps3_supported(ctrl->panel->dpcd))
  572. pattern = DP_TRAINING_PATTERN_3;
  573. else
  574. pattern = DP_TRAINING_PATTERN_2;
  575. if (!downgrade)
  576. goto end;
  577. switch (pattern) {
  578. case DP_TRAINING_PATTERN_4:
  579. pattern = DP_TRAINING_PATTERN_3;
  580. break;
  581. case DP_TRAINING_PATTERN_3:
  582. pattern = DP_TRAINING_PATTERN_2;
  583. break;
  584. default:
  585. break;
  586. }
  587. end:
  588. ctrl->training_2_pattern = pattern;
  589. }
  590. static int dp_ctrl_link_setup(struct dp_ctrl_private *ctrl, bool shallow)
  591. {
  592. int rc = -EINVAL;
  593. bool downgrade = false;
  594. u32 link_train_max_retries = 100;
  595. struct dp_catalog_ctrl *catalog;
  596. struct dp_link_params *link_params;
  597. catalog = ctrl->catalog;
  598. link_params = &ctrl->link->link_params;
  599. catalog->phy_lane_cfg(catalog, ctrl->orientation,
  600. link_params->lane_count);
  601. while (1) {
  602. DP_DEBUG("bw_code=%d, lane_count=%d\n",
  603. link_params->bw_code, link_params->lane_count);
  604. rc = dp_ctrl_enable_link_clock(ctrl);
  605. if (rc)
  606. break;
  607. ctrl->catalog->late_phy_init(ctrl->catalog,
  608. ctrl->link->link_params.lane_count,
  609. ctrl->orientation);
  610. dp_ctrl_configure_source_link_params(ctrl, true);
  611. if (!(--link_train_max_retries % 10)) {
  612. struct dp_link_params *link = &ctrl->link->link_params;
  613. link->lane_count = ctrl->initial_lane_count;
  614. link->bw_code = ctrl->initial_bw_code;
  615. downgrade = true;
  616. }
  617. dp_ctrl_select_training_pattern(ctrl, downgrade);
  618. rc = dp_ctrl_setup_main_link(ctrl);
  619. if (!rc)
  620. break;
  621. /*
  622. * Shallow means link training failure is not important.
  623. * If it fails, we still keep the link clocks on.
  624. * In this mode, the system expects DP to be up
  625. * even though the cable is removed. Disconnect interrupt
  626. * will eventually trigger and shutdown DP.
  627. */
  628. if (shallow) {
  629. rc = 0;
  630. break;
  631. }
  632. if (!link_train_max_retries || atomic_read(&ctrl->aborted)) {
  633. dp_ctrl_disable_link_clock(ctrl);
  634. break;
  635. }
  636. if (rc != -EAGAIN)
  637. dp_ctrl_link_rate_down_shift(ctrl);
  638. dp_ctrl_configure_source_link_params(ctrl, false);
  639. dp_ctrl_disable_link_clock(ctrl);
  640. /* hw recommended delays before retrying link training */
  641. msleep(20);
  642. }
  643. return rc;
  644. }
  645. static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl,
  646. struct dp_panel *dp_panel)
  647. {
  648. int ret = 0;
  649. u32 pclk;
  650. enum dp_pm_type clk_type;
  651. char clk_name[32] = "";
  652. ret = ctrl->power->set_pixel_clk_parent(ctrl->power,
  653. dp_panel->stream_id);
  654. if (ret)
  655. return ret;
  656. if (dp_panel->stream_id == DP_STREAM_0) {
  657. clk_type = DP_STREAM0_PM;
  658. strlcpy(clk_name, "strm0_pixel_clk", 32);
  659. } else if (dp_panel->stream_id == DP_STREAM_1) {
  660. clk_type = DP_STREAM1_PM;
  661. strlcpy(clk_name, "strm1_pixel_clk", 32);
  662. } else {
  663. DP_ERR("Invalid stream:%d for clk enable\n",
  664. dp_panel->stream_id);
  665. return -EINVAL;
  666. }
  667. pclk = dp_panel->pinfo.widebus_en ?
  668. (dp_panel->pinfo.pixel_clk_khz >> 1) :
  669. (dp_panel->pinfo.pixel_clk_khz);
  670. dp_ctrl_set_clock_rate(ctrl, clk_name, clk_type, pclk);
  671. ret = ctrl->power->clk_enable(ctrl->power, clk_type, true);
  672. if (ret) {
  673. DP_ERR("Unabled to start stream:%d clocks\n",
  674. dp_panel->stream_id);
  675. ret = -EINVAL;
  676. }
  677. return ret;
  678. }
  679. static int dp_ctrl_disable_stream_clocks(struct dp_ctrl_private *ctrl,
  680. struct dp_panel *dp_panel)
  681. {
  682. int ret = 0;
  683. if (dp_panel->stream_id == DP_STREAM_0) {
  684. return ctrl->power->clk_enable(ctrl->power,
  685. DP_STREAM0_PM, false);
  686. } else if (dp_panel->stream_id == DP_STREAM_1) {
  687. return ctrl->power->clk_enable(ctrl->power,
  688. DP_STREAM1_PM, false);
  689. } else {
  690. DP_ERR("Invalid stream:%d for clk disable\n",
  691. dp_panel->stream_id);
  692. ret = -EINVAL;
  693. }
  694. return ret;
  695. }
  696. static int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
  697. {
  698. struct dp_ctrl_private *ctrl;
  699. struct dp_catalog_ctrl *catalog;
  700. if (!dp_ctrl) {
  701. DP_ERR("Invalid input data\n");
  702. return -EINVAL;
  703. }
  704. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  705. ctrl->orientation = flip;
  706. catalog = ctrl->catalog;
  707. if (reset) {
  708. catalog->usb_reset(ctrl->catalog, flip);
  709. catalog->phy_reset(ctrl->catalog);
  710. }
  711. catalog->enable_irq(ctrl->catalog, true);
  712. atomic_set(&ctrl->aborted, 0);
  713. return 0;
  714. }
  715. /**
  716. * dp_ctrl_host_deinit() - Uninitialize DP controller
  717. * @ctrl: Display Port Driver data
  718. *
  719. * Perform required steps to uninitialize DP controller
  720. * and its resources.
  721. */
  722. static void dp_ctrl_host_deinit(struct dp_ctrl *dp_ctrl)
  723. {
  724. struct dp_ctrl_private *ctrl;
  725. if (!dp_ctrl) {
  726. DP_ERR("Invalid input data\n");
  727. return;
  728. }
  729. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  730. ctrl->catalog->enable_irq(ctrl->catalog, false);
  731. DP_DEBUG("Host deinitialized successfully\n");
  732. }
  733. static void dp_ctrl_send_video(struct dp_ctrl_private *ctrl)
  734. {
  735. reinit_completion(&ctrl->video_comp);
  736. ctrl->catalog->state_ctrl(ctrl->catalog, ST_SEND_VIDEO);
  737. }
  738. static void dp_ctrl_fec_setup(struct dp_ctrl_private *ctrl)
  739. {
  740. u8 fec_sts = 0;
  741. int i, max_retries = 3;
  742. bool fec_en_detected = false;
  743. if (!ctrl->fec_mode)
  744. return;
  745. /* FEC should be set only for the first stream */
  746. if (ctrl->stream_count > 1)
  747. return;
  748. /* Need to try to enable multiple times due to BS symbols collisions */
  749. for (i = 0; i < max_retries; i++) {
  750. ctrl->catalog->fec_config(ctrl->catalog, ctrl->fec_mode);
  751. /* wait for controller to start fec sequence */
  752. usleep_range(900, 1000);
  753. /* read back FEC status and check if it is enabled */
  754. drm_dp_dpcd_readb(ctrl->aux->drm_aux, DP_FEC_STATUS, &fec_sts);
  755. if (fec_sts & DP_FEC_DECODE_EN_DETECTED) {
  756. fec_en_detected = true;
  757. break;
  758. }
  759. }
  760. SDE_EVT32_EXTERNAL(i, fec_en_detected);
  761. DP_DEBUG("retries %d, fec_en_detected %d\n", i, fec_en_detected);
  762. if (!fec_en_detected)
  763. DP_WARN("failed to enable sink fec\n");
  764. }
  765. static int dp_ctrl_link_maintenance(struct dp_ctrl *dp_ctrl)
  766. {
  767. int ret = 0;
  768. struct dp_ctrl_private *ctrl;
  769. if (!dp_ctrl) {
  770. DP_ERR("Invalid input data\n");
  771. return -EINVAL;
  772. }
  773. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  774. ctrl->aux->state &= ~DP_STATE_LINK_MAINTENANCE_COMPLETED;
  775. ctrl->aux->state &= ~DP_STATE_LINK_MAINTENANCE_FAILED;
  776. if (!ctrl->power_on) {
  777. DP_ERR("ctrl off\n");
  778. ret = -EINVAL;
  779. goto end;
  780. }
  781. if (atomic_read(&ctrl->aborted))
  782. goto end;
  783. ctrl->aux->state |= DP_STATE_LINK_MAINTENANCE_STARTED;
  784. ret = dp_ctrl_setup_main_link(ctrl);
  785. ctrl->aux->state &= ~DP_STATE_LINK_MAINTENANCE_STARTED;
  786. if (ret) {
  787. ctrl->aux->state |= DP_STATE_LINK_MAINTENANCE_FAILED;
  788. goto end;
  789. }
  790. ctrl->aux->state |= DP_STATE_LINK_MAINTENANCE_COMPLETED;
  791. if (ctrl->stream_count) {
  792. dp_ctrl_send_video(ctrl);
  793. dp_ctrl_wait4video_ready(ctrl);
  794. dp_ctrl_fec_setup(ctrl);
  795. }
  796. end:
  797. return ret;
  798. }
  799. static void dp_ctrl_process_phy_test_request(struct dp_ctrl *dp_ctrl)
  800. {
  801. int ret = 0;
  802. struct dp_ctrl_private *ctrl;
  803. if (!dp_ctrl) {
  804. DP_ERR("Invalid input data\n");
  805. return;
  806. }
  807. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  808. if (!ctrl->link->phy_params.phy_test_pattern_sel) {
  809. DP_DEBUG("no test pattern selected by sink\n");
  810. return;
  811. }
  812. DP_DEBUG("start\n");
  813. /*
  814. * The global reset will need DP link ralated clocks to be
  815. * running. Add the global reset just before disabling the
  816. * link clocks and core clocks.
  817. */
  818. ctrl->catalog->reset(ctrl->catalog);
  819. ctrl->dp_ctrl.stream_pre_off(&ctrl->dp_ctrl, ctrl->panel);
  820. ctrl->dp_ctrl.stream_off(&ctrl->dp_ctrl, ctrl->panel);
  821. ctrl->dp_ctrl.off(&ctrl->dp_ctrl);
  822. ctrl->aux->init(ctrl->aux, ctrl->parser->aux_cfg);
  823. ret = ctrl->dp_ctrl.on(&ctrl->dp_ctrl, ctrl->mst_mode,
  824. ctrl->fec_mode, ctrl->dsc_mode, false);
  825. if (ret)
  826. DP_ERR("failed to enable DP controller\n");
  827. ctrl->dp_ctrl.stream_on(&ctrl->dp_ctrl, ctrl->panel);
  828. DP_DEBUG("end\n");
  829. }
  830. static void dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl)
  831. {
  832. bool success = false;
  833. u32 pattern_sent = 0x0;
  834. u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
  835. dp_ctrl_update_hw_vx_px(ctrl);
  836. ctrl->catalog->send_phy_pattern(ctrl->catalog, pattern_requested);
  837. dp_ctrl_update_sink_vx_px(ctrl);
  838. ctrl->link->send_test_response(ctrl->link);
  839. pattern_sent = ctrl->catalog->read_phy_pattern(ctrl->catalog);
  840. DP_DEBUG("pattern_request: %s. pattern_sent: 0x%x\n",
  841. dp_link_get_phy_test_pattern(pattern_requested),
  842. pattern_sent);
  843. switch (pattern_sent) {
  844. case MR_LINK_TRAINING1:
  845. if (pattern_requested == DP_PHY_TEST_PATTERN_D10_2)
  846. success = true;
  847. break;
  848. case MR_LINK_SYMBOL_ERM:
  849. if ((pattern_requested == DP_PHY_TEST_PATTERN_ERROR_COUNT)
  850. || (pattern_requested == DP_PHY_TEST_PATTERN_CP2520))
  851. success = true;
  852. break;
  853. case MR_LINK_PRBS7:
  854. if (pattern_requested == DP_PHY_TEST_PATTERN_PRBS7)
  855. success = true;
  856. break;
  857. case MR_LINK_CUSTOM80:
  858. if (pattern_requested == DP_PHY_TEST_PATTERN_80BIT_CUSTOM)
  859. success = true;
  860. break;
  861. case MR_LINK_TRAINING4:
  862. if (pattern_requested == DP_PHY_TEST_PATTERN_CP2520_3)
  863. success = true;
  864. break;
  865. default:
  866. success = false;
  867. break;
  868. }
  869. DP_DEBUG("%s: %s\n", success ? "success" : "failed",
  870. dp_link_get_phy_test_pattern(pattern_requested));
  871. }
  872. static void dp_ctrl_mst_calculate_rg(struct dp_ctrl_private *ctrl,
  873. struct dp_panel *panel, u32 *p_x_int, u32 *p_y_frac_enum)
  874. {
  875. u64 min_slot_cnt, max_slot_cnt;
  876. u64 raw_target_sc, target_sc_fixp;
  877. u64 ts_denom, ts_enum, ts_int;
  878. u64 pclk = panel->pinfo.pixel_clk_khz;
  879. u64 lclk = 0;
  880. u64 lanes = ctrl->link->link_params.lane_count;
  881. u64 bpp = panel->pinfo.bpp;
  882. u64 pbn = panel->pbn;
  883. u64 numerator, denominator, temp, temp1, temp2;
  884. u32 x_int = 0, y_frac_enum = 0;
  885. u64 target_strm_sym, ts_int_fixp, ts_frac_fixp, y_frac_enum_fixp;
  886. lclk = drm_dp_bw_code_to_link_rate(ctrl->link->link_params.bw_code);
  887. if (panel->pinfo.comp_info.enabled)
  888. bpp = DSC_BPP(panel->pinfo.comp_info.dsc_info.config);
  889. /* min_slot_cnt */
  890. numerator = pclk * bpp * 64 * 1000;
  891. denominator = lclk * lanes * 8 * 1000;
  892. min_slot_cnt = drm_fixp_from_fraction(numerator, denominator);
  893. /* max_slot_cnt */
  894. numerator = pbn * 54 * 1000;
  895. denominator = lclk * lanes;
  896. max_slot_cnt = drm_fixp_from_fraction(numerator, denominator);
  897. /* raw_target_sc */
  898. numerator = max_slot_cnt + min_slot_cnt;
  899. denominator = drm_fixp_from_fraction(2, 1);
  900. raw_target_sc = drm_fixp_div(numerator, denominator);
  901. DP_DEBUG("raw_target_sc before overhead:0x%llx\n", raw_target_sc);
  902. DP_DEBUG("dsc_overhead_fp:0x%llx\n", panel->pinfo.dsc_overhead_fp);
  903. /* apply fec and dsc overhead factor */
  904. if (panel->pinfo.dsc_overhead_fp)
  905. raw_target_sc = drm_fixp_mul(raw_target_sc,
  906. panel->pinfo.dsc_overhead_fp);
  907. if (panel->fec_overhead_fp)
  908. raw_target_sc = drm_fixp_mul(raw_target_sc,
  909. panel->fec_overhead_fp);
  910. DP_DEBUG("raw_target_sc after overhead:0x%llx\n", raw_target_sc);
  911. /* target_sc */
  912. temp = drm_fixp_from_fraction(256 * lanes, 1);
  913. numerator = drm_fixp_mul(raw_target_sc, temp);
  914. denominator = drm_fixp_from_fraction(256 * lanes, 1);
  915. target_sc_fixp = drm_fixp_div(numerator, denominator);
  916. ts_enum = 256 * lanes;
  917. ts_denom = drm_fixp_from_fraction(256 * lanes, 1);
  918. ts_int = drm_fixp2int(target_sc_fixp);
  919. temp = drm_fixp2int_ceil(raw_target_sc);
  920. if (temp != ts_int) {
  921. temp = drm_fixp_from_fraction(ts_int, 1);
  922. temp1 = raw_target_sc - temp;
  923. temp2 = drm_fixp_mul(temp1, ts_denom);
  924. ts_enum = drm_fixp2int(temp2);
  925. }
  926. /* target_strm_sym */
  927. ts_int_fixp = drm_fixp_from_fraction(ts_int, 1);
  928. ts_frac_fixp = drm_fixp_from_fraction(ts_enum, drm_fixp2int(ts_denom));
  929. temp = ts_int_fixp + ts_frac_fixp;
  930. temp1 = drm_fixp_from_fraction(lanes, 1);
  931. target_strm_sym = drm_fixp_mul(temp, temp1);
  932. /* x_int */
  933. x_int = drm_fixp2int(target_strm_sym);
  934. /* y_enum_frac */
  935. temp = drm_fixp_from_fraction(x_int, 1);
  936. temp1 = target_strm_sym - temp;
  937. temp2 = drm_fixp_from_fraction(256, 1);
  938. y_frac_enum_fixp = drm_fixp_mul(temp1, temp2);
  939. temp1 = drm_fixp2int(y_frac_enum_fixp);
  940. temp2 = drm_fixp2int_ceil(y_frac_enum_fixp);
  941. y_frac_enum = (u32)((temp1 == temp2) ? temp1 : temp1 + 1);
  942. panel->mst_target_sc = raw_target_sc;
  943. *p_x_int = x_int;
  944. *p_y_frac_enum = y_frac_enum;
  945. DP_DEBUG("x_int: %d, y_frac_enum: %d\n", x_int, y_frac_enum);
  946. }
  947. static int dp_ctrl_mst_send_act(struct dp_ctrl_private *ctrl)
  948. {
  949. bool act_complete;
  950. if (!ctrl->mst_mode)
  951. return 0;
  952. ctrl->catalog->trigger_act(ctrl->catalog);
  953. msleep(20); /* needs 1 frame time */
  954. ctrl->catalog->read_act_complete_sts(ctrl->catalog, &act_complete);
  955. if (!act_complete)
  956. DP_ERR("mst act trigger complete failed\n");
  957. else
  958. DP_MST_DEBUG("mst ACT trigger complete SUCCESS\n");
  959. return 0;
  960. }
  961. static void dp_ctrl_mst_stream_setup(struct dp_ctrl_private *ctrl,
  962. struct dp_panel *panel)
  963. {
  964. u32 x_int, y_frac_enum, lanes, bw_code;
  965. int i;
  966. if (!ctrl->mst_mode)
  967. return;
  968. DP_MST_DEBUG("mst stream channel allocation\n");
  969. for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) {
  970. ctrl->catalog->channel_alloc(ctrl->catalog,
  971. i,
  972. ctrl->mst_ch_info.slot_info[i].start_slot,
  973. ctrl->mst_ch_info.slot_info[i].tot_slots);
  974. }
  975. lanes = ctrl->link->link_params.lane_count;
  976. bw_code = ctrl->link->link_params.bw_code;
  977. dp_ctrl_mst_calculate_rg(ctrl, panel, &x_int, &y_frac_enum);
  978. ctrl->catalog->update_rg(ctrl->catalog, panel->stream_id,
  979. x_int, y_frac_enum);
  980. DP_MST_DEBUG("mst stream:%d, start_slot:%d, tot_slots:%d\n",
  981. panel->stream_id,
  982. panel->channel_start_slot, panel->channel_total_slots);
  983. DP_MST_DEBUG("mst lane_cnt:%d, bw:%d, x_int:%d, y_frac:%d\n",
  984. lanes, bw_code, x_int, y_frac_enum);
  985. }
  986. static void dp_ctrl_dsc_setup(struct dp_ctrl_private *ctrl)
  987. {
  988. int rlen;
  989. u32 dsc_enable;
  990. if (!ctrl->fec_mode)
  991. return;
  992. dsc_enable = ctrl->dsc_mode ? 1 : 0;
  993. rlen = drm_dp_dpcd_writeb(ctrl->aux->drm_aux, DP_DSC_ENABLE,
  994. dsc_enable);
  995. if (rlen < 1)
  996. DP_WARN("failed to enable sink dsc\n");
  997. }
  998. static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel)
  999. {
  1000. int rc = 0;
  1001. bool link_ready = false;
  1002. struct dp_ctrl_private *ctrl;
  1003. if (!dp_ctrl || !panel)
  1004. return -EINVAL;
  1005. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1006. if (!ctrl->power_on) {
  1007. DP_DEBUG("controller powered off\n");
  1008. return -EPERM;
  1009. }
  1010. rc = dp_ctrl_enable_stream_clocks(ctrl, panel);
  1011. if (rc) {
  1012. DP_ERR("failure on stream clock enable\n");
  1013. return rc;
  1014. }
  1015. rc = panel->hw_cfg(panel, true);
  1016. if (rc)
  1017. return rc;
  1018. if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
  1019. dp_ctrl_send_phy_test_pattern(ctrl);
  1020. return 0;
  1021. }
  1022. dp_ctrl_mst_stream_setup(ctrl, panel);
  1023. dp_ctrl_send_video(ctrl);
  1024. dp_ctrl_mst_send_act(ctrl);
  1025. dp_ctrl_wait4video_ready(ctrl);
  1026. ctrl->stream_count++;
  1027. link_ready = ctrl->catalog->mainlink_ready(ctrl->catalog);
  1028. DP_DEBUG("mainlink %s\n", link_ready ? "READY" : "NOT READY");
  1029. /* wait for link training completion before fec config as per spec */
  1030. dp_ctrl_fec_setup(ctrl);
  1031. dp_ctrl_dsc_setup(ctrl);
  1032. return rc;
  1033. }
  1034. static void dp_ctrl_mst_stream_pre_off(struct dp_ctrl *dp_ctrl,
  1035. struct dp_panel *panel)
  1036. {
  1037. struct dp_ctrl_private *ctrl;
  1038. bool act_complete;
  1039. int i;
  1040. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1041. if (!ctrl->mst_mode)
  1042. return;
  1043. for (i = DP_STREAM_0; i < DP_STREAM_MAX; i++) {
  1044. ctrl->catalog->channel_alloc(ctrl->catalog,
  1045. i,
  1046. ctrl->mst_ch_info.slot_info[i].start_slot,
  1047. ctrl->mst_ch_info.slot_info[i].tot_slots);
  1048. }
  1049. ctrl->catalog->trigger_act(ctrl->catalog);
  1050. msleep(20); /* needs 1 frame time */
  1051. ctrl->catalog->read_act_complete_sts(ctrl->catalog, &act_complete);
  1052. if (!act_complete)
  1053. DP_ERR("mst stream_off act trigger complete failed\n");
  1054. else
  1055. DP_MST_DEBUG("mst stream_off ACT trigger complete SUCCESS\n");
  1056. }
  1057. static void dp_ctrl_stream_pre_off(struct dp_ctrl *dp_ctrl,
  1058. struct dp_panel *panel)
  1059. {
  1060. struct dp_ctrl_private *ctrl;
  1061. if (!dp_ctrl || !panel) {
  1062. DP_ERR("invalid input\n");
  1063. return;
  1064. }
  1065. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1066. dp_ctrl_push_idle(ctrl, panel->stream_id);
  1067. dp_ctrl_mst_stream_pre_off(dp_ctrl, panel);
  1068. }
  1069. static void dp_ctrl_stream_off(struct dp_ctrl *dp_ctrl, struct dp_panel *panel)
  1070. {
  1071. struct dp_ctrl_private *ctrl;
  1072. if (!dp_ctrl || !panel)
  1073. return;
  1074. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1075. if (!ctrl->power_on)
  1076. return;
  1077. panel->hw_cfg(panel, false);
  1078. dp_ctrl_disable_stream_clocks(ctrl, panel);
  1079. ctrl->stream_count--;
  1080. }
  1081. static int dp_ctrl_on(struct dp_ctrl *dp_ctrl, bool mst_mode,
  1082. bool fec_mode, bool dsc_mode, bool shallow)
  1083. {
  1084. int rc = 0;
  1085. struct dp_ctrl_private *ctrl;
  1086. u32 rate = 0;
  1087. if (!dp_ctrl) {
  1088. rc = -EINVAL;
  1089. goto end;
  1090. }
  1091. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1092. if (ctrl->power_on)
  1093. goto end;
  1094. if (atomic_read(&ctrl->aborted)) {
  1095. rc = -EPERM;
  1096. goto end;
  1097. }
  1098. ctrl->mst_mode = mst_mode;
  1099. if (fec_mode) {
  1100. ctrl->fec_mode = fec_mode;
  1101. ctrl->dsc_mode = dsc_mode;
  1102. }
  1103. rate = ctrl->panel->link_info.rate;
  1104. if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
  1105. DP_DEBUG("using phy test link parameters\n");
  1106. } else {
  1107. ctrl->link->link_params.bw_code =
  1108. drm_dp_link_rate_to_bw_code(rate);
  1109. ctrl->link->link_params.lane_count =
  1110. ctrl->panel->link_info.num_lanes;
  1111. }
  1112. DP_DEBUG("bw_code=%d, lane_count=%d\n",
  1113. ctrl->link->link_params.bw_code,
  1114. ctrl->link->link_params.lane_count);
  1115. /* backup initial lane count and bw code */
  1116. ctrl->initial_lane_count = ctrl->link->link_params.lane_count;
  1117. ctrl->initial_bw_code = ctrl->link->link_params.bw_code;
  1118. rc = dp_ctrl_link_setup(ctrl, shallow);
  1119. if (!rc)
  1120. ctrl->power_on = true;
  1121. end:
  1122. return rc;
  1123. }
  1124. static void dp_ctrl_off(struct dp_ctrl *dp_ctrl)
  1125. {
  1126. struct dp_ctrl_private *ctrl;
  1127. if (!dp_ctrl)
  1128. return;
  1129. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1130. if (!ctrl->power_on)
  1131. return;
  1132. ctrl->catalog->fec_config(ctrl->catalog, false);
  1133. dp_ctrl_configure_source_link_params(ctrl, false);
  1134. ctrl->catalog->reset(ctrl->catalog);
  1135. /* Make sure DP is disabled before clk disable */
  1136. wmb();
  1137. dp_ctrl_disable_link_clock(ctrl);
  1138. ctrl->mst_mode = false;
  1139. ctrl->fec_mode = false;
  1140. ctrl->dsc_mode = false;
  1141. ctrl->power_on = false;
  1142. memset(&ctrl->mst_ch_info, 0, sizeof(ctrl->mst_ch_info));
  1143. DP_DEBUG("DP off done\n");
  1144. }
  1145. static void dp_ctrl_set_mst_channel_info(struct dp_ctrl *dp_ctrl,
  1146. enum dp_stream_id strm,
  1147. u32 start_slot, u32 tot_slots)
  1148. {
  1149. struct dp_ctrl_private *ctrl;
  1150. if (!dp_ctrl || strm >= DP_STREAM_MAX) {
  1151. DP_ERR("invalid input\n");
  1152. return;
  1153. }
  1154. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1155. ctrl->mst_ch_info.slot_info[strm].start_slot = start_slot;
  1156. ctrl->mst_ch_info.slot_info[strm].tot_slots = tot_slots;
  1157. }
  1158. static void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
  1159. {
  1160. struct dp_ctrl_private *ctrl;
  1161. SDE_EVT32_EXTERNAL(SDE_EVTLOG_FUNC_ENTRY);
  1162. if (!dp_ctrl)
  1163. return;
  1164. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1165. ctrl->catalog->get_interrupt(ctrl->catalog);
  1166. SDE_EVT32_EXTERNAL(ctrl->catalog->isr);
  1167. if (ctrl->catalog->isr & DP_CTRL_INTR_READY_FOR_VIDEO)
  1168. dp_ctrl_video_ready(ctrl);
  1169. if (ctrl->catalog->isr & DP_CTRL_INTR_IDLE_PATTERN_SENT)
  1170. dp_ctrl_idle_patterns_sent(ctrl);
  1171. if (ctrl->catalog->isr5 & DP_CTRL_INTR_MST_DP0_VCPF_SENT)
  1172. dp_ctrl_idle_patterns_sent(ctrl);
  1173. if (ctrl->catalog->isr5 & DP_CTRL_INTR_MST_DP1_VCPF_SENT)
  1174. dp_ctrl_idle_patterns_sent(ctrl);
  1175. SDE_EVT32_EXTERNAL(SDE_EVTLOG_FUNC_EXIT);
  1176. }
  1177. void dp_ctrl_set_sim_mode(struct dp_ctrl *dp_ctrl, bool en)
  1178. {
  1179. struct dp_ctrl_private *ctrl;
  1180. if (!dp_ctrl)
  1181. return;
  1182. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1183. ctrl->sim_mode = en;
  1184. DP_INFO("sim_mode=%d\n", ctrl->sim_mode);
  1185. }
  1186. struct dp_ctrl *dp_ctrl_get(struct dp_ctrl_in *in)
  1187. {
  1188. int rc = 0;
  1189. struct dp_ctrl_private *ctrl;
  1190. struct dp_ctrl *dp_ctrl;
  1191. if (!in->dev || !in->panel || !in->aux ||
  1192. !in->link || !in->catalog) {
  1193. DP_ERR("invalid input\n");
  1194. rc = -EINVAL;
  1195. goto error;
  1196. }
  1197. ctrl = devm_kzalloc(in->dev, sizeof(*ctrl), GFP_KERNEL);
  1198. if (!ctrl) {
  1199. rc = -ENOMEM;
  1200. goto error;
  1201. }
  1202. init_completion(&ctrl->idle_comp);
  1203. init_completion(&ctrl->video_comp);
  1204. /* in parameters */
  1205. ctrl->parser = in->parser;
  1206. ctrl->panel = in->panel;
  1207. ctrl->power = in->power;
  1208. ctrl->aux = in->aux;
  1209. ctrl->link = in->link;
  1210. ctrl->catalog = in->catalog;
  1211. ctrl->pll = in->pll;
  1212. ctrl->dev = in->dev;
  1213. ctrl->mst_mode = false;
  1214. ctrl->fec_mode = false;
  1215. dp_ctrl = &ctrl->dp_ctrl;
  1216. /* out parameters */
  1217. dp_ctrl->init = dp_ctrl_host_init;
  1218. dp_ctrl->deinit = dp_ctrl_host_deinit;
  1219. dp_ctrl->on = dp_ctrl_on;
  1220. dp_ctrl->off = dp_ctrl_off;
  1221. dp_ctrl->abort = dp_ctrl_abort;
  1222. dp_ctrl->isr = dp_ctrl_isr;
  1223. dp_ctrl->link_maintenance = dp_ctrl_link_maintenance;
  1224. dp_ctrl->process_phy_test_request = dp_ctrl_process_phy_test_request;
  1225. dp_ctrl->stream_on = dp_ctrl_stream_on;
  1226. dp_ctrl->stream_off = dp_ctrl_stream_off;
  1227. dp_ctrl->stream_pre_off = dp_ctrl_stream_pre_off;
  1228. dp_ctrl->set_mst_channel_info = dp_ctrl_set_mst_channel_info;
  1229. dp_ctrl->set_sim_mode = dp_ctrl_set_sim_mode;
  1230. return dp_ctrl;
  1231. error:
  1232. return ERR_PTR(rc);
  1233. }
  1234. void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
  1235. {
  1236. struct dp_ctrl_private *ctrl;
  1237. if (!dp_ctrl)
  1238. return;
  1239. ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
  1240. devm_kfree(ctrl->dev, ctrl);
  1241. }