3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
189 lines
5.6 KiB
C
189 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef __MDSS_DP_PLL_14NM_H
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#define __MDSS_DP_PLL_14NM_H
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#define DP_PHY_REVISION_ID0 0x0000
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#define DP_PHY_REVISION_ID1 0x0004
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#define DP_PHY_REVISION_ID2 0x0008
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#define DP_PHY_REVISION_ID3 0x000C
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#define DP_PHY_CFG 0x0010
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#define DP_PHY_CFG_1 0x0014
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#define DP_PHY_PD_CTL 0x0018
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#define DP_PHY_MODE 0x001C
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#define DP_PHY_AUX_CFG0 0x0020
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#define DP_PHY_AUX_CFG1 0x0024
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#define DP_PHY_AUX_CFG2 0x0028
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#define DP_PHY_AUX_CFG3 0x002C
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#define DP_PHY_AUX_CFG4 0x0030
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#define DP_PHY_AUX_CFG5 0x0034
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#define DP_PHY_AUX_CFG6 0x0038
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#define DP_PHY_AUX_CFG7 0x003C
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#define DP_PHY_AUX_CFG8 0x0040
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#define DP_PHY_AUX_CFG9 0x0044
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#define DP_PHY_AUX_INTERRUPT_MASK 0x0048
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#define DP_PHY_AUX_INTERRUPT_CLEAR 0x004C
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#define DP_PHY_AUX_BIST_CFG 0x0050
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#define DP_PHY_VCO_DIV 0x0068
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#define DP_PHY_TX0_TX1_LANE_CTL 0x006C
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#define DP_PHY_TX2_TX3_LANE_CTL 0x0088
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#define DP_PHY_SPARE0 0x00AC
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#define DP_PHY_STATUS 0x00C0
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/* Tx registers */
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#define QSERDES_TX0_OFFSET 0x0400
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#define QSERDES_TX1_OFFSET 0x0800
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#define TXn_BIST_MODE_LANENO 0x0000
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#define TXn_CLKBUF_ENABLE 0x0008
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#define TXn_TX_EMP_POST1_LVL 0x000C
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#define TXn_TX_DRV_LVL 0x001C
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#define TXn_RESET_TSYNC_EN 0x0024
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#define TXn_PRE_STALL_LDO_BOOST_EN 0x0028
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#define TXn_TX_BAND 0x002C
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#define TXn_SLEW_CNTL 0x0030
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#define TXn_INTERFACE_SELECT 0x0034
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#define TXn_RES_CODE_LANE_TX 0x003C
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#define TXn_RES_CODE_LANE_RX 0x0040
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#define TXn_RES_CODE_LANE_OFFSET_TX 0x0044
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#define TXn_RES_CODE_LANE_OFFSET_RX 0x0048
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#define TXn_DEBUG_BUS_SEL 0x0058
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#define TXn_TRANSCEIVER_BIAS_EN 0x005C
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#define TXn_HIGHZ_DRVR_EN 0x0060
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#define TXn_TX_POL_INV 0x0064
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#define TXn_PARRATE_REC_DETECT_IDLE_EN 0x0068
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#define TXn_LANE_MODE_1 0x008C
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#define TXn_TRAN_DRVR_EMP_EN 0x00C0
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#define TXn_TX_INTERFACE_MODE 0x00C4
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#define TXn_VMODE_CTRL1 0x00F0
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/* PLL register offset */
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#define QSERDES_COM_ATB_SEL1 0x0000
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#define QSERDES_COM_ATB_SEL2 0x0004
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#define QSERDES_COM_FREQ_UPDATE 0x0008
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#define QSERDES_COM_BG_TIMER 0x000C
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#define QSERDES_COM_SSC_EN_CENTER 0x0010
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#define QSERDES_COM_SSC_ADJ_PER1 0x0014
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#define QSERDES_COM_SSC_ADJ_PER2 0x0018
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#define QSERDES_COM_SSC_PER1 0x001C
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#define QSERDES_COM_SSC_PER2 0x0020
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#define QSERDES_COM_SSC_STEP_SIZE1 0x0024
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#define QSERDES_COM_SSC_STEP_SIZE2 0x0028
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#define QSERDES_COM_POST_DIV 0x002C
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#define QSERDES_COM_POST_DIV_MUX 0x0030
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#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0034
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#define QSERDES_COM_CLK_ENABLE1 0x0038
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#define QSERDES_COM_SYS_CLK_CTRL 0x003C
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#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x0040
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#define QSERDES_COM_PLL_EN 0x0044
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#define QSERDES_COM_PLL_IVCO 0x0048
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#define QSERDES_COM_LOCK_CMP1_MODE0 0x004C
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#define QSERDES_COM_LOCK_CMP2_MODE0 0x0050
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#define QSERDES_COM_LOCK_CMP3_MODE0 0x0054
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#define QSERDES_COM_CP_CTRL_MODE0 0x0078
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#define QSERDES_COM_CP_CTRL_MODE1 0x007C
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#define QSERDES_COM_PLL_RCTRL_MODE0 0x0084
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#define QSERDES_COM_PLL_CCTRL_MODE0 0x0090
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#define QSERDES_COM_PLL_CNTRL 0x009C
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#define QSERDES_COM_SYSCLK_EN_SEL 0x00AC
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#define QSERDES_COM_CML_SYSCLK_SEL 0x00B0
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#define QSERDES_COM_RESETSM_CNTRL 0x00B4
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#define QSERDES_COM_RESETSM_CNTRL2 0x00B8
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#define QSERDES_COM_LOCK_CMP_EN 0x00C8
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#define QSERDES_COM_LOCK_CMP_CFG 0x00CC
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#define QSERDES_COM_DEC_START_MODE0 0x00D0
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#define QSERDES_COM_DEC_START_MODE1 0x00D4
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#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x00DC
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#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x00E0
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#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x00E4
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#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x0108
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#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x010C
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#define QSERDES_COM_VCO_TUNE_CTRL 0x0124
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#define QSERDES_COM_VCO_TUNE_MAP 0x0128
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#define QSERDES_COM_VCO_TUNE1_MODE0 0x012C
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#define QSERDES_COM_VCO_TUNE2_MODE0 0x0130
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#define QSERDES_COM_CMN_STATUS 0x015C
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#define QSERDES_COM_RESET_SM_STATUS 0x0160
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#define QSERDES_COM_BG_CTRL 0x0170
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#define QSERDES_COM_CLK_SELECT 0x0174
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#define QSERDES_COM_HSCLK_SEL 0x0178
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#define QSERDES_COM_CORECLK_DIV 0x0184
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#define QSERDES_COM_SW_RESET 0x0188
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#define QSERDES_COM_CORE_CLK_EN 0x018C
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#define QSERDES_COM_C_READY_STATUS 0x0190
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#define QSERDES_COM_CMN_CONFIG 0x0194
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#define QSERDES_COM_SVS_MODE_CLK_SEL 0x019C
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#define DP_PLL_POLL_SLEEP_US 500
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#define DP_PLL_POLL_TIMEOUT_US 10000
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#define DP_PHY_POLL_SLEEP_US 500
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#define DP_PHY_POLL_TIMEOUT_US 10000
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#define DP_VCO_RATE_8100MHZDIV1000 8100000UL
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#define DP_VCO_RATE_10800MHZDIV1000 10800000UL
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#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL
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#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL
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#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL
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struct dp_pll_db {
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struct mdss_pll_resources *pll;
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/* lane and orientation settings */
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u8 lane_cnt;
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u8 orientation;
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/* COM PHY settings */
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u32 hsclk_sel;
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u32 dec_start_mode0;
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u32 div_frac_start1_mode0;
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u32 div_frac_start2_mode0;
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u32 div_frac_start3_mode0;
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u32 lock_cmp1_mode0;
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u32 lock_cmp2_mode0;
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u32 lock_cmp3_mode0;
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/* PHY vco divider */
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u32 phy_vco_div;
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/* TX settings */
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u32 lane_mode_1;
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};
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int dp_vco_set_rate_14nm(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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unsigned long dp_vco_recalc_rate_14nm(struct clk_hw *hw,
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unsigned long parent_rate);
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long dp_vco_round_rate_14nm(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate);
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int dp_vco_prepare_14nm(struct clk_hw *hw);
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void dp_vco_unprepare_14nm(struct clk_hw *hw);
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int dp_mux_set_parent_14nm(void *context,
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unsigned int reg, unsigned int val);
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int dp_mux_get_parent_14nm(void *context,
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unsigned int reg, unsigned int *val);
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#endif /* __MDSS_DP_PLL_14NM_H */
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