dsi_phy_timing_v3_0.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "dsi-phy-timing:" fmt
  6. #include "dsi_phy_timing_calc.h"
  7. void dsi_phy_hw_v3_0_get_default_phy_params(
  8. struct phy_clk_params *params)
  9. {
  10. params->clk_prep_buf = 0;
  11. params->clk_zero_buf = 0;
  12. params->clk_trail_buf = 0;
  13. params->hs_prep_buf = 0;
  14. params->hs_zero_buf = 0;
  15. params->hs_trail_buf = 0;
  16. params->hs_rqst_buf = 0;
  17. params->hs_exit_buf = 0;
  18. }
  19. int32_t dsi_phy_hw_v3_0_calc_clk_zero(s64 rec_temp1, s64 mult)
  20. {
  21. s64 rec_temp2, rec_temp3;
  22. rec_temp2 = (rec_temp1 - mult);
  23. rec_temp3 = roundup64(div_s64(rec_temp2, 8), mult);
  24. return (div_s64(rec_temp3, mult) - 1);
  25. }
  26. int32_t dsi_phy_hw_v3_0_calc_clk_trail_rec_min(s64 temp_mul,
  27. s64 frac, s64 mult)
  28. {
  29. s64 rec_temp1, rec_temp2, rec_temp3;
  30. rec_temp1 = temp_mul + frac;
  31. rec_temp2 = div_s64(rec_temp1, 8);
  32. rec_temp3 = roundup64(rec_temp2, mult);
  33. return (div_s64(rec_temp3, mult) - 1);
  34. }
  35. int32_t dsi_phy_hw_v3_0_calc_clk_trail_rec_max(s64 temp1, s64 mult)
  36. {
  37. s64 rec_temp2;
  38. rec_temp2 = temp1 / 8;
  39. return (div_s64(rec_temp2, mult) - 1);
  40. }
  41. int32_t dsi_phy_hw_v3_0_calc_hs_zero(s64 temp1, s64 mult)
  42. {
  43. s64 rec_temp2, rec_min;
  44. rec_temp2 = roundup64((temp1 / 8), mult);
  45. rec_min = rec_temp2 - (1 * mult);
  46. return div_s64(rec_min, mult);
  47. }
  48. void dsi_phy_hw_v3_0_calc_hs_trail(struct phy_clk_params *clk_params,
  49. struct phy_timing_desc *desc)
  50. {
  51. s64 rec_temp1;
  52. struct timing_entry *t = &desc->hs_trail;
  53. t->rec_min = DIV_ROUND_UP(
  54. (t->mipi_min * clk_params->bitclk_mbps),
  55. (8 * clk_params->tlpx_numer_ns)) - 1;
  56. rec_temp1 = (t->mipi_max * clk_params->bitclk_mbps);
  57. t->rec_max =
  58. (div_s64(rec_temp1, (8 * clk_params->tlpx_numer_ns))) - 1;
  59. }
  60. void dsi_phy_hw_v3_0_update_timing_params(
  61. struct dsi_phy_per_lane_cfgs *timing,
  62. struct phy_timing_desc *desc)
  63. {
  64. timing->lane_v3[0] = 0x00;
  65. timing->lane_v3[1] = desc->clk_zero.reg_value;
  66. timing->lane_v3[2] = desc->clk_prepare.reg_value;
  67. timing->lane_v3[3] = desc->clk_trail.reg_value;
  68. timing->lane_v3[4] = desc->hs_exit.reg_value;
  69. timing->lane_v3[5] = desc->hs_zero.reg_value;
  70. timing->lane_v3[6] = desc->hs_prepare.reg_value;
  71. timing->lane_v3[7] = desc->hs_trail.reg_value;
  72. timing->lane_v3[8] = desc->hs_rqst.reg_value;
  73. timing->lane_v3[9] = 0x02;
  74. timing->lane_v3[10] = 0x04;
  75. timing->lane_v3[11] = 0x00;
  76. pr_debug("[%d %d %d %d]\n", timing->lane_v3[0],
  77. timing->lane_v3[1], timing->lane_v3[2], timing->lane_v3[3]);
  78. pr_debug("[%d %d %d %d]\n", timing->lane_v3[4],
  79. timing->lane_v3[5], timing->lane_v3[6], timing->lane_v3[7]);
  80. pr_debug("[%d %d %d %d]\n", timing->lane_v3[8],
  81. timing->lane_v3[9], timing->lane_v3[10], timing->lane_v3[11]);
  82. timing->count_per_lane = 12;
  83. }