sde_kms.c 84 KB

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  1. /*
  2. * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/dma-buf.h>
  24. #include <linux/memblock.h>
  25. #include <linux/bootmem.h>
  26. #include "msm_drv.h"
  27. #include "msm_mmu.h"
  28. #include "msm_gem.h"
  29. #include "dsi_display.h"
  30. #include "dsi_drm.h"
  31. #include "sde_wb.h"
  32. #include "dp_display.h"
  33. #include "dp_drm.h"
  34. #include "sde_kms.h"
  35. #include "sde_core_irq.h"
  36. #include "sde_formats.h"
  37. #include "sde_hw_vbif.h"
  38. #include "sde_vbif.h"
  39. #include "sde_encoder.h"
  40. #include "sde_plane.h"
  41. #include "sde_crtc.h"
  42. #include "sde_reg_dma.h"
  43. #include <soc/qcom/scm.h>
  44. #include "soc/qcom/secure_buffer.h"
  45. #define CREATE_TRACE_POINTS
  46. #include "sde_trace.h"
  47. /* defines for secure channel call */
  48. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  49. #define MDP_DEVICE_ID 0x1A
  50. static const char * const iommu_ports[] = {
  51. "mdp_0",
  52. };
  53. /**
  54. * Controls size of event log buffer. Specified as a power of 2.
  55. */
  56. #define SDE_EVTLOG_SIZE 1024
  57. /*
  58. * To enable overall DRM driver logging
  59. * # echo 0x2 > /sys/module/drm/parameters/debug
  60. *
  61. * To enable DRM driver h/w logging
  62. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  63. *
  64. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  65. */
  66. #define SDE_DEBUGFS_DIR "msm_sde"
  67. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  68. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  69. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  70. /**
  71. * sdecustom - enable certain driver customizations for sde clients
  72. * Enabling this modifies the standard DRM behavior slightly and assumes
  73. * that the clients have specific knowledge about the modifications that
  74. * are involved, so don't enable this unless you know what you're doing.
  75. *
  76. * Parts of the driver that are affected by this setting may be located by
  77. * searching for invocations of the 'sde_is_custom_client()' function.
  78. *
  79. * This is disabled by default.
  80. */
  81. static bool sdecustom = true;
  82. module_param(sdecustom, bool, 0400);
  83. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  84. static int sde_kms_hw_init(struct msm_kms *kms);
  85. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  86. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  87. static int _sde_kms_register_events(struct msm_kms *kms,
  88. struct drm_mode_object *obj, u32 event, bool en);
  89. bool sde_is_custom_client(void)
  90. {
  91. return sdecustom;
  92. }
  93. #ifdef CONFIG_DEBUG_FS
  94. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  95. {
  96. struct msm_drm_private *priv;
  97. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  98. return NULL;
  99. priv = sde_kms->dev->dev_private;
  100. return priv->debug_root;
  101. }
  102. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  103. {
  104. void *p;
  105. int rc;
  106. void *debugfs_root;
  107. p = sde_hw_util_get_log_mask_ptr();
  108. if (!sde_kms || !p)
  109. return -EINVAL;
  110. debugfs_root = sde_debugfs_get_root(sde_kms);
  111. if (!debugfs_root)
  112. return -EINVAL;
  113. /* allow debugfs_root to be NULL */
  114. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  115. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  116. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  117. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  118. if (rc) {
  119. SDE_ERROR("failed to init perf %d\n", rc);
  120. return rc;
  121. }
  122. return 0;
  123. }
  124. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  125. {
  126. /* don't need to NULL check debugfs_root */
  127. if (sde_kms) {
  128. sde_debugfs_vbif_destroy(sde_kms);
  129. sde_debugfs_core_irq_destroy(sde_kms);
  130. }
  131. }
  132. #else
  133. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  134. {
  135. return 0;
  136. }
  137. static void _sde_debugfs_destroy(struct sde_kms *sde_kms)
  138. {
  139. }
  140. #endif
  141. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  142. {
  143. int ret = 0;
  144. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  145. ret = sde_crtc_vblank(crtc, true);
  146. SDE_ATRACE_END("sde_kms_enable_vblank");
  147. return ret;
  148. }
  149. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  150. {
  151. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  152. sde_crtc_vblank(crtc, false);
  153. SDE_ATRACE_END("sde_kms_disable_vblank");
  154. }
  155. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  156. struct drm_crtc *crtc)
  157. {
  158. struct drm_encoder *encoder;
  159. struct drm_device *dev;
  160. int ret;
  161. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  162. SDE_ERROR("invalid params\n");
  163. return;
  164. }
  165. if (!crtc->state->enable) {
  166. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  167. return;
  168. }
  169. if (!crtc->state->active) {
  170. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  171. return;
  172. }
  173. dev = crtc->dev;
  174. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  175. if (encoder->crtc != crtc)
  176. continue;
  177. /*
  178. * Video Mode - Wait for VSYNC
  179. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  180. * complete
  181. */
  182. SDE_EVT32_VERBOSE(DRMID(crtc));
  183. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  184. if (ret && ret != -EWOULDBLOCK) {
  185. SDE_ERROR(
  186. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  187. crtc->base.id, encoder->base.id, ret);
  188. break;
  189. }
  190. }
  191. }
  192. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  193. struct drm_crtc *crtc, bool enable)
  194. {
  195. struct drm_device *dev;
  196. struct msm_drm_private *priv;
  197. struct sde_mdss_cfg *sde_cfg;
  198. struct drm_plane *plane;
  199. int i, ret;
  200. dev = sde_kms->dev;
  201. priv = dev->dev_private;
  202. sde_cfg = sde_kms->catalog;
  203. ret = sde_vbif_halt_xin_mask(sde_kms,
  204. sde_cfg->sui_block_xin_mask, enable);
  205. if (ret) {
  206. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  207. return ret;
  208. }
  209. if (enable) {
  210. for (i = 0; i < priv->num_planes; i++) {
  211. plane = priv->planes[i];
  212. sde_plane_secure_ctrl_xin_client(plane, crtc);
  213. }
  214. }
  215. return 0;
  216. }
  217. /**
  218. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  219. * @sde_kms: Pointer to sde_kms struct
  220. * @vimd: switch the stage 2 translation to this VMID
  221. */
  222. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  223. {
  224. struct scm_desc desc = {0};
  225. uint32_t num_sids;
  226. uint32_t *sec_sid;
  227. uint32_t mem_protect_sd_ctrl_id = MEM_PROTECT_SD_CTRL_SWITCH;
  228. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  229. int ret = 0, i;
  230. num_sids = sde_cfg->sec_sid_mask_count;
  231. if (!num_sids) {
  232. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  233. return -EINVAL;
  234. }
  235. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  236. if (!sec_sid)
  237. return -ENOMEM;
  238. for (i = 0; i < num_sids; i++) {
  239. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  240. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  241. }
  242. dmac_flush_range(sec_sid, sec_sid + num_sids);
  243. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d",
  244. vmid, num_sids);
  245. desc.arginfo = SCM_ARGS(4, SCM_VAL, SCM_RW, SCM_VAL, SCM_VAL);
  246. desc.args[0] = MDP_DEVICE_ID;
  247. desc.args[1] = SCM_BUFFER_PHYS(sec_sid);
  248. desc.args[2] = sizeof(uint32_t) * num_sids;
  249. desc.args[3] = vmid;
  250. ret = scm_call2(SCM_SIP_FNID(SCM_SVC_MP,
  251. mem_protect_sd_ctrl_id), &desc);
  252. if (ret)
  253. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  254. desc.args[3], ret);
  255. SDE_EVT32(mem_protect_sd_ctrl_id,
  256. desc.args[0], desc.args[3], num_sids, ret);
  257. kfree(sec_sid);
  258. return ret;
  259. }
  260. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  261. {
  262. u32 ret = 0;
  263. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  264. goto end;
  265. /* detach_all_contexts */
  266. ret = sde_kms_mmu_detach(sde_kms, false);
  267. if (ret) {
  268. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  269. goto end;
  270. }
  271. ret = _sde_kms_scm_call(sde_kms, vmid);
  272. if (ret)
  273. goto end;
  274. end:
  275. return ret;
  276. }
  277. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, int vmid)
  278. {
  279. u32 ret = 0;
  280. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  281. goto end;
  282. ret = _sde_kms_scm_call(sde_kms, vmid);
  283. if (ret)
  284. goto end;
  285. /* attach_all_contexts */
  286. ret = sde_kms_mmu_attach(sde_kms, false);
  287. if (ret) {
  288. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  289. goto end;
  290. }
  291. end:
  292. return ret;
  293. }
  294. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  295. {
  296. u32 ret = 0;
  297. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  298. goto end;
  299. /* detach secure_context */
  300. ret = sde_kms_mmu_detach(sde_kms, true);
  301. if (ret) {
  302. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  303. goto end;
  304. }
  305. ret = _sde_kms_scm_call(sde_kms, vmid);
  306. if (ret)
  307. goto end;
  308. end:
  309. return ret;
  310. }
  311. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, int vmid)
  312. {
  313. u32 ret = 0;
  314. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  315. goto end;
  316. ret = _sde_kms_scm_call(sde_kms, vmid);
  317. if (ret)
  318. goto end;
  319. ret = sde_kms_mmu_attach(sde_kms, true);
  320. if (ret) {
  321. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  322. goto end;
  323. }
  324. end:
  325. return ret;
  326. }
  327. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  328. struct drm_crtc *crtc, bool enable)
  329. {
  330. int ret;
  331. if (enable) {
  332. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  333. if (ret < 0) {
  334. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  335. return ret;
  336. }
  337. sde_crtc_misr_setup(crtc, true, 1);
  338. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  339. if (ret) {
  340. pm_runtime_put_sync(sde_kms->dev->dev);
  341. return ret;
  342. }
  343. } else {
  344. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  345. sde_crtc_misr_setup(crtc, false, 0);
  346. pm_runtime_put_sync(sde_kms->dev->dev);
  347. }
  348. return 0;
  349. }
  350. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  351. bool post_commit)
  352. {
  353. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  354. int old_smmu_state = smmu_state->state;
  355. int ret = 0;
  356. u32 vmid;
  357. if (!sde_kms || !crtc) {
  358. SDE_ERROR("invalid argument(s)\n");
  359. return -EINVAL;
  360. }
  361. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  362. post_commit, smmu_state->sui_misr_state,
  363. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  364. if ((!smmu_state->transition_type) ||
  365. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  366. /* Bail out */
  367. return 0;
  368. /* enable sui misr if requested, before the transition */
  369. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  370. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  371. if (ret)
  372. goto end;
  373. }
  374. mutex_lock(&sde_kms->secure_transition_lock);
  375. switch (smmu_state->state) {
  376. case DETACH_ALL_REQ:
  377. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  378. if (!ret)
  379. smmu_state->state = DETACHED;
  380. break;
  381. case ATTACH_ALL_REQ:
  382. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL);
  383. if (!ret) {
  384. smmu_state->state = ATTACHED;
  385. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  386. }
  387. break;
  388. case DETACH_SEC_REQ:
  389. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  390. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  391. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  392. if (!ret)
  393. smmu_state->state = DETACHED_SEC;
  394. break;
  395. case ATTACH_SEC_REQ:
  396. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL);
  397. if (!ret) {
  398. smmu_state->state = ATTACHED;
  399. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  400. }
  401. break;
  402. default:
  403. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  404. DRMID(crtc), smmu_state->state,
  405. smmu_state->transition_type);
  406. ret = -EINVAL;
  407. break;
  408. }
  409. mutex_unlock(&sde_kms->secure_transition_lock);
  410. /* disable sui misr if requested, after the transition */
  411. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  412. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  413. if (ret)
  414. goto end;
  415. }
  416. end:
  417. smmu_state->sui_misr_state = NONE;
  418. smmu_state->transition_type = NONE;
  419. smmu_state->transition_error = ret ? true : false;
  420. SDE_DEBUG("crtc %d: old_state %d, new_state %d, sec_lvl %d, ret %d\n",
  421. DRMID(crtc), old_smmu_state, smmu_state->state,
  422. smmu_state->secure_level, ret);
  423. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  424. smmu_state->transition_error, smmu_state->secure_level,
  425. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  426. return ret;
  427. }
  428. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  429. struct drm_atomic_state *state)
  430. {
  431. struct drm_crtc *crtc;
  432. struct drm_crtc_state *old_crtc_state;
  433. struct drm_plane *plane;
  434. struct drm_plane_state *plane_state;
  435. struct sde_kms *sde_kms = to_sde_kms(kms);
  436. struct drm_device *dev = sde_kms->dev;
  437. int i, ops = 0, ret = 0;
  438. bool old_valid_fb = false;
  439. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  440. if (!crtc->state || !crtc->state->active)
  441. continue;
  442. /*
  443. * It is safe to assume only one active crtc,
  444. * and compatible translation modes on the
  445. * planes staged on this crtc.
  446. * otherwise validation would have failed.
  447. * For this CRTC,
  448. */
  449. /*
  450. * 1. Check if old state on the CRTC has planes
  451. * staged with valid fbs
  452. */
  453. for_each_old_plane_in_state(state, plane, plane_state, i) {
  454. if (!plane_state->crtc)
  455. continue;
  456. if (plane_state->fb) {
  457. old_valid_fb = true;
  458. break;
  459. }
  460. }
  461. /*
  462. * 2.Get the operations needed to be performed before
  463. * secure transition can be initiated.
  464. */
  465. ops = sde_crtc_get_secure_transition_ops(crtc,
  466. old_crtc_state, old_valid_fb);
  467. if (ops < 0) {
  468. SDE_ERROR("invalid secure operations %x\n", ops);
  469. return ops;
  470. }
  471. if (!ops)
  472. goto no_ops;
  473. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  474. crtc->base.id, ops, crtc->state);
  475. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  476. /* 3. Perform operations needed for secure transition */
  477. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  478. SDE_DEBUG("wait_for_transfer_done\n");
  479. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  480. }
  481. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  482. SDE_DEBUG("cleanup planes\n");
  483. drm_atomic_helper_cleanup_planes(dev, state);
  484. }
  485. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  486. SDE_DEBUG("secure ctrl\n");
  487. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  488. }
  489. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  490. SDE_DEBUG("prepare planes %d",
  491. crtc->state->plane_mask);
  492. drm_atomic_crtc_for_each_plane(plane,
  493. crtc) {
  494. const struct drm_plane_helper_funcs *funcs;
  495. plane_state = plane->state;
  496. funcs = plane->helper_private;
  497. SDE_DEBUG("psde:%d FB[%u]\n",
  498. plane->base.id,
  499. plane->fb->base.id);
  500. if (!funcs)
  501. continue;
  502. if (funcs->prepare_fb(plane, plane_state)) {
  503. ret = funcs->prepare_fb(plane,
  504. plane_state);
  505. if (ret)
  506. return ret;
  507. }
  508. }
  509. }
  510. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  511. SDE_DEBUG("secure operations completed\n");
  512. }
  513. no_ops:
  514. return 0;
  515. }
  516. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  517. unsigned int splash_buffer_size,
  518. unsigned int ramdump_base,
  519. unsigned int ramdump_buffer_size)
  520. {
  521. unsigned long pfn_start, pfn_end, pfn_idx;
  522. int ret = 0;
  523. if (!mem_addr || !splash_buffer_size) {
  524. SDE_ERROR("invalid params\n");
  525. return -EINVAL;
  526. }
  527. /* leave ramdump memory only if base address matches */
  528. if (ramdump_base == mem_addr &&
  529. ramdump_buffer_size <= splash_buffer_size) {
  530. mem_addr += ramdump_buffer_size;
  531. splash_buffer_size -= ramdump_buffer_size;
  532. }
  533. pfn_start = mem_addr >> PAGE_SHIFT;
  534. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  535. ret = memblock_free(mem_addr, splash_buffer_size);
  536. if (ret) {
  537. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  538. return ret;
  539. }
  540. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  541. free_reserved_page(pfn_to_page(pfn_idx));
  542. return ret;
  543. }
  544. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  545. struct sde_splash_mem *splash)
  546. {
  547. struct msm_mmu *mmu = NULL;
  548. int ret = 0;
  549. if (!sde_kms->aspace[0]) {
  550. SDE_ERROR("aspace not found for sde kms node\n");
  551. return -EINVAL;
  552. }
  553. mmu = sde_kms->aspace[0]->mmu;
  554. if (!mmu) {
  555. SDE_ERROR("mmu not found for aspace\n");
  556. return -EINVAL;
  557. }
  558. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  559. SDE_ERROR("invalid input params for map\n");
  560. return -EINVAL;
  561. }
  562. if (!splash->ref_cnt) {
  563. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  564. splash->splash_buf_base,
  565. splash->splash_buf_size,
  566. IOMMU_READ | IOMMU_NOEXEC);
  567. if (ret)
  568. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  569. }
  570. splash->ref_cnt++;
  571. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  572. splash->splash_buf_base,
  573. splash->splash_buf_size,
  574. splash->ref_cnt);
  575. return ret;
  576. }
  577. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  578. {
  579. int i = 0;
  580. int ret = 0;
  581. if (!sde_kms)
  582. return -EINVAL;
  583. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  584. ret = _sde_kms_splash_mem_get(sde_kms,
  585. sde_kms->splash_data.splash_display[i].splash);
  586. if (ret)
  587. return ret;
  588. }
  589. return ret;
  590. }
  591. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  592. struct sde_splash_mem *splash)
  593. {
  594. struct msm_mmu *mmu = NULL;
  595. int rc = 0;
  596. if (!sde_kms)
  597. return -EINVAL;
  598. if (!sde_kms->aspace[0]) {
  599. SDE_ERROR("aspace not found for sde kms node\n");
  600. return -EINVAL;
  601. }
  602. mmu = sde_kms->aspace[0]->mmu;
  603. if (!mmu) {
  604. SDE_ERROR("mmu not found for aspace\n");
  605. return -EINVAL;
  606. }
  607. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  608. return -EINVAL;
  609. splash->ref_cnt--;
  610. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  611. splash->splash_buf_base, splash->ref_cnt);
  612. if (!splash->ref_cnt) {
  613. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  614. splash->splash_buf_size);
  615. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  616. splash->splash_buf_size, splash->ramdump_base,
  617. splash->ramdump_size);
  618. splash->splash_buf_base = 0;
  619. splash->splash_buf_size = 0;
  620. }
  621. return rc;
  622. }
  623. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  624. {
  625. int i = 0;
  626. int ret = 0;
  627. if (!sde_kms)
  628. return -EINVAL;
  629. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  630. ret = _sde_kms_splash_mem_put(sde_kms,
  631. sde_kms->splash_data.splash_display[i].splash);
  632. if (ret)
  633. return ret;
  634. }
  635. return ret;
  636. }
  637. static void sde_kms_prepare_commit(struct msm_kms *kms,
  638. struct drm_atomic_state *state)
  639. {
  640. struct sde_kms *sde_kms;
  641. struct msm_drm_private *priv;
  642. struct drm_device *dev;
  643. struct drm_encoder *encoder;
  644. struct drm_crtc *crtc;
  645. struct drm_crtc_state *crtc_state;
  646. int i, rc;
  647. if (!kms)
  648. return;
  649. sde_kms = to_sde_kms(kms);
  650. dev = sde_kms->dev;
  651. if (!dev || !dev->dev_private)
  652. return;
  653. priv = dev->dev_private;
  654. SDE_ATRACE_BEGIN("prepare_commit");
  655. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  656. if (rc < 0) {
  657. SDE_ERROR("failed to enable power resources %d\n", rc);
  658. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  659. goto end;
  660. }
  661. if (sde_kms->first_kickoff) {
  662. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  663. sde_kms->first_kickoff = false;
  664. }
  665. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  666. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  667. head) {
  668. if (encoder->crtc != crtc)
  669. continue;
  670. sde_encoder_prepare_commit(encoder);
  671. }
  672. }
  673. /*
  674. * NOTE: for secure use cases we want to apply the new HW
  675. * configuration only after completing preparation for secure
  676. * transitions prepare below if any transtions is required.
  677. */
  678. sde_kms_prepare_secure_transition(kms, state);
  679. end:
  680. SDE_ATRACE_END("prepare_commit");
  681. }
  682. static void sde_kms_commit(struct msm_kms *kms,
  683. struct drm_atomic_state *old_state)
  684. {
  685. struct sde_kms *sde_kms;
  686. struct drm_crtc *crtc;
  687. struct drm_crtc_state *old_crtc_state;
  688. int i;
  689. if (!kms || !old_state)
  690. return;
  691. sde_kms = to_sde_kms(kms);
  692. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  693. SDE_ERROR("power resource is not enabled\n");
  694. return;
  695. }
  696. SDE_ATRACE_BEGIN("sde_kms_commit");
  697. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  698. if (crtc->state->active) {
  699. SDE_EVT32(DRMID(crtc));
  700. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  701. }
  702. }
  703. SDE_ATRACE_END("sde_kms_commit");
  704. }
  705. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  706. struct drm_crtc *crtc)
  707. {
  708. struct msm_drm_private *priv;
  709. struct sde_splash_display *splash_display;
  710. int i;
  711. if (!sde_kms || !crtc)
  712. return;
  713. priv = sde_kms->dev->dev_private;
  714. SDE_EVT32(crtc->base.id, crtc->state->active,
  715. sde_kms->splash_data.num_splash_displays);
  716. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  717. return;
  718. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  719. splash_display = &sde_kms->splash_data.splash_display[i];
  720. if (splash_display->encoder &&
  721. crtc == splash_display->encoder->crtc)
  722. break;
  723. }
  724. if (i >= MAX_DSI_DISPLAYS)
  725. return;
  726. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  727. if (splash_display->cont_splash_enabled) {
  728. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  729. splash_display, false);
  730. splash_display->cont_splash_enabled = false;
  731. sde_kms->splash_data.num_splash_displays--;
  732. SDE_DEBUG("cont_splash handoff done for dpy:%d remaining:%d\n",
  733. i, sde_kms->splash_data.num_splash_displays);
  734. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  735. }
  736. /* remove the votes if all displays are done with splash */
  737. if (!sde_kms->splash_data.num_splash_displays) {
  738. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  739. sde_power_data_bus_set_quota(&priv->phandle, i,
  740. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  741. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  742. pm_runtime_put_sync(sde_kms->dev->dev);
  743. }
  744. }
  745. static void sde_kms_complete_commit(struct msm_kms *kms,
  746. struct drm_atomic_state *old_state)
  747. {
  748. struct sde_kms *sde_kms;
  749. struct msm_drm_private *priv;
  750. struct drm_crtc *crtc;
  751. struct drm_crtc_state *old_crtc_state;
  752. struct drm_connector *connector;
  753. struct drm_connector_state *old_conn_state;
  754. int i, rc = 0;
  755. if (!kms || !old_state)
  756. return;
  757. sde_kms = to_sde_kms(kms);
  758. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  759. return;
  760. priv = sde_kms->dev->dev_private;
  761. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  762. SDE_ERROR("power resource is not enabled\n");
  763. return;
  764. }
  765. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  766. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  767. sde_crtc_complete_commit(crtc, old_crtc_state);
  768. /* complete secure transitions if any */
  769. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  770. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  771. }
  772. for_each_old_connector_in_state(old_state, connector,
  773. old_conn_state, i) {
  774. struct sde_connector *c_conn;
  775. c_conn = to_sde_connector(connector);
  776. if (!c_conn->ops.post_kickoff)
  777. continue;
  778. rc = c_conn->ops.post_kickoff(connector);
  779. if (rc) {
  780. pr_err("Connector Post kickoff failed rc=%d\n",
  781. rc);
  782. }
  783. }
  784. pm_runtime_put_sync(sde_kms->dev->dev);
  785. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  786. _sde_kms_release_splash_resource(sde_kms, crtc);
  787. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  788. SDE_ATRACE_END("sde_kms_complete_commit");
  789. }
  790. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  791. struct drm_crtc *crtc)
  792. {
  793. struct drm_encoder *encoder;
  794. struct drm_device *dev;
  795. int ret;
  796. if (!kms || !crtc || !crtc->state) {
  797. SDE_ERROR("invalid params\n");
  798. return;
  799. }
  800. dev = crtc->dev;
  801. if (!crtc->state->enable) {
  802. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  803. return;
  804. }
  805. if (!crtc->state->active) {
  806. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  807. return;
  808. }
  809. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  810. SDE_ERROR("power resource is not enabled\n");
  811. return;
  812. }
  813. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  814. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  815. if (encoder->crtc != crtc)
  816. continue;
  817. /*
  818. * Wait for post-flush if necessary to delay before
  819. * plane_cleanup. For example, wait for vsync in case of video
  820. * mode panels. This may be a no-op for command mode panels.
  821. */
  822. SDE_EVT32_VERBOSE(DRMID(crtc));
  823. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  824. if (ret && ret != -EWOULDBLOCK) {
  825. SDE_ERROR("wait for commit done returned %d\n", ret);
  826. sde_crtc_request_frame_reset(crtc);
  827. break;
  828. }
  829. sde_crtc_complete_flip(crtc, NULL);
  830. }
  831. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  832. }
  833. static void sde_kms_prepare_fence(struct msm_kms *kms,
  834. struct drm_atomic_state *old_state)
  835. {
  836. struct drm_crtc *crtc;
  837. struct drm_crtc_state *old_crtc_state;
  838. int i, rc;
  839. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  840. SDE_ERROR("invalid argument(s)\n");
  841. return;
  842. }
  843. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  844. retry:
  845. /* attempt to acquire ww mutex for connection */
  846. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  847. old_state->acquire_ctx);
  848. if (rc == -EDEADLK) {
  849. drm_modeset_backoff(old_state->acquire_ctx);
  850. goto retry;
  851. }
  852. /* old_state actually contains updated crtc pointers */
  853. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  854. if (crtc->state->active)
  855. sde_crtc_prepare_commit(crtc, old_crtc_state);
  856. }
  857. SDE_ATRACE_END("sde_kms_prepare_fence");
  858. }
  859. /**
  860. * _sde_kms_get_displays - query for underlying display handles and cache them
  861. * @sde_kms: Pointer to sde kms structure
  862. * Returns: Zero on success
  863. */
  864. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  865. {
  866. int rc = -ENOMEM;
  867. if (!sde_kms) {
  868. SDE_ERROR("invalid sde kms\n");
  869. return -EINVAL;
  870. }
  871. /* dsi */
  872. sde_kms->dsi_displays = NULL;
  873. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  874. if (sde_kms->dsi_display_count) {
  875. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  876. sizeof(void *),
  877. GFP_KERNEL);
  878. if (!sde_kms->dsi_displays) {
  879. SDE_ERROR("failed to allocate dsi displays\n");
  880. goto exit_deinit_dsi;
  881. }
  882. sde_kms->dsi_display_count =
  883. dsi_display_get_active_displays(sde_kms->dsi_displays,
  884. sde_kms->dsi_display_count);
  885. }
  886. /* wb */
  887. sde_kms->wb_displays = NULL;
  888. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  889. if (sde_kms->wb_display_count) {
  890. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  891. sizeof(void *),
  892. GFP_KERNEL);
  893. if (!sde_kms->wb_displays) {
  894. SDE_ERROR("failed to allocate wb displays\n");
  895. goto exit_deinit_wb;
  896. }
  897. sde_kms->wb_display_count =
  898. wb_display_get_displays(sde_kms->wb_displays,
  899. sde_kms->wb_display_count);
  900. }
  901. /* dp */
  902. sde_kms->dp_displays = NULL;
  903. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  904. if (sde_kms->dp_display_count) {
  905. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  906. sizeof(void *), GFP_KERNEL);
  907. if (!sde_kms->dp_displays) {
  908. SDE_ERROR("failed to allocate dp displays\n");
  909. goto exit_deinit_dp;
  910. }
  911. sde_kms->dp_display_count =
  912. dp_display_get_displays(sde_kms->dp_displays,
  913. sde_kms->dp_display_count);
  914. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  915. }
  916. return 0;
  917. exit_deinit_dp:
  918. kfree(sde_kms->dp_displays);
  919. sde_kms->dp_stream_count = 0;
  920. sde_kms->dp_display_count = 0;
  921. sde_kms->dp_displays = NULL;
  922. exit_deinit_wb:
  923. kfree(sde_kms->wb_displays);
  924. sde_kms->wb_display_count = 0;
  925. sde_kms->wb_displays = NULL;
  926. exit_deinit_dsi:
  927. kfree(sde_kms->dsi_displays);
  928. sde_kms->dsi_display_count = 0;
  929. sde_kms->dsi_displays = NULL;
  930. return rc;
  931. }
  932. /**
  933. * _sde_kms_release_displays - release cache of underlying display handles
  934. * @sde_kms: Pointer to sde kms structure
  935. */
  936. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  937. {
  938. if (!sde_kms) {
  939. SDE_ERROR("invalid sde kms\n");
  940. return;
  941. }
  942. kfree(sde_kms->wb_displays);
  943. sde_kms->wb_displays = NULL;
  944. sde_kms->wb_display_count = 0;
  945. kfree(sde_kms->dsi_displays);
  946. sde_kms->dsi_displays = NULL;
  947. sde_kms->dsi_display_count = 0;
  948. }
  949. /**
  950. * _sde_kms_setup_displays - create encoders, bridges and connectors
  951. * for underlying displays
  952. * @dev: Pointer to drm device structure
  953. * @priv: Pointer to private drm device data
  954. * @sde_kms: Pointer to sde kms structure
  955. * Returns: Zero on success
  956. */
  957. static int _sde_kms_setup_displays(struct drm_device *dev,
  958. struct msm_drm_private *priv,
  959. struct sde_kms *sde_kms)
  960. {
  961. static const struct sde_connector_ops dsi_ops = {
  962. .set_info_blob = dsi_conn_set_info_blob,
  963. .detect = dsi_conn_detect,
  964. .get_modes = dsi_connector_get_modes,
  965. .pre_destroy = dsi_connector_put_modes,
  966. .mode_valid = dsi_conn_mode_valid,
  967. .get_info = dsi_display_get_info,
  968. .set_backlight = dsi_display_set_backlight,
  969. .soft_reset = dsi_display_soft_reset,
  970. .pre_kickoff = dsi_conn_pre_kickoff,
  971. .clk_ctrl = dsi_display_clk_ctrl,
  972. .set_power = dsi_display_set_power,
  973. .get_mode_info = dsi_conn_get_mode_info,
  974. .get_dst_format = dsi_display_get_dst_format,
  975. .post_kickoff = dsi_conn_post_kickoff,
  976. .check_status = dsi_display_check_status,
  977. .enable_event = dsi_conn_enable_event,
  978. .cmd_transfer = dsi_display_cmd_transfer,
  979. .cont_splash_config = dsi_display_cont_splash_config,
  980. .get_panel_vfp = dsi_display_get_panel_vfp,
  981. .get_default_lms = dsi_display_get_default_lms,
  982. };
  983. static const struct sde_connector_ops wb_ops = {
  984. .post_init = sde_wb_connector_post_init,
  985. .set_info_blob = sde_wb_connector_set_info_blob,
  986. .detect = sde_wb_connector_detect,
  987. .get_modes = sde_wb_connector_get_modes,
  988. .set_property = sde_wb_connector_set_property,
  989. .get_info = sde_wb_get_info,
  990. .soft_reset = NULL,
  991. .get_mode_info = sde_wb_get_mode_info,
  992. .get_dst_format = NULL,
  993. .check_status = NULL,
  994. .cmd_transfer = NULL,
  995. .cont_splash_config = NULL,
  996. .get_panel_vfp = NULL,
  997. };
  998. static const struct sde_connector_ops dp_ops = {
  999. .post_init = dp_connector_post_init,
  1000. .detect = dp_connector_detect,
  1001. .get_modes = dp_connector_get_modes,
  1002. .mode_valid = dp_connector_mode_valid,
  1003. .get_info = dp_connector_get_info,
  1004. .get_mode_info = dp_connector_get_mode_info,
  1005. .post_open = dp_connector_post_open,
  1006. .check_status = NULL,
  1007. .config_hdr = dp_connector_config_hdr,
  1008. .cmd_transfer = NULL,
  1009. .cont_splash_config = NULL,
  1010. .get_panel_vfp = NULL,
  1011. .update_pps = dp_connector_update_pps,
  1012. };
  1013. struct msm_display_info info;
  1014. struct drm_encoder *encoder;
  1015. void *display, *connector;
  1016. int i, max_encoders;
  1017. int rc = 0;
  1018. if (!dev || !priv || !sde_kms) {
  1019. SDE_ERROR("invalid argument(s)\n");
  1020. return -EINVAL;
  1021. }
  1022. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1023. sde_kms->dp_display_count +
  1024. sde_kms->dp_stream_count;
  1025. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1026. max_encoders = ARRAY_SIZE(priv->encoders);
  1027. SDE_ERROR("capping number of displays to %d", max_encoders);
  1028. }
  1029. /* dsi */
  1030. for (i = 0; i < sde_kms->dsi_display_count &&
  1031. priv->num_encoders < max_encoders; ++i) {
  1032. display = sde_kms->dsi_displays[i];
  1033. encoder = NULL;
  1034. memset(&info, 0x0, sizeof(info));
  1035. rc = dsi_display_get_info(NULL, &info, display);
  1036. if (rc) {
  1037. SDE_ERROR("dsi get_info %d failed\n", i);
  1038. continue;
  1039. }
  1040. encoder = sde_encoder_init(dev, &info);
  1041. if (IS_ERR_OR_NULL(encoder)) {
  1042. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1043. continue;
  1044. }
  1045. rc = dsi_display_drm_bridge_init(display, encoder);
  1046. if (rc) {
  1047. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1048. sde_encoder_destroy(encoder);
  1049. continue;
  1050. }
  1051. connector = sde_connector_init(dev,
  1052. encoder,
  1053. 0,
  1054. display,
  1055. &dsi_ops,
  1056. DRM_CONNECTOR_POLL_HPD,
  1057. DRM_MODE_CONNECTOR_DSI);
  1058. if (connector) {
  1059. priv->encoders[priv->num_encoders++] = encoder;
  1060. priv->connectors[priv->num_connectors++] = connector;
  1061. } else {
  1062. SDE_ERROR("dsi %d connector init failed\n", i);
  1063. dsi_display_drm_bridge_deinit(display);
  1064. sde_encoder_destroy(encoder);
  1065. }
  1066. }
  1067. /* wb */
  1068. for (i = 0; i < sde_kms->wb_display_count &&
  1069. priv->num_encoders < max_encoders; ++i) {
  1070. display = sde_kms->wb_displays[i];
  1071. encoder = NULL;
  1072. memset(&info, 0x0, sizeof(info));
  1073. rc = sde_wb_get_info(NULL, &info, display);
  1074. if (rc) {
  1075. SDE_ERROR("wb get_info %d failed\n", i);
  1076. continue;
  1077. }
  1078. encoder = sde_encoder_init(dev, &info);
  1079. if (IS_ERR_OR_NULL(encoder)) {
  1080. SDE_ERROR("encoder init failed for wb %d\n", i);
  1081. continue;
  1082. }
  1083. rc = sde_wb_drm_init(display, encoder);
  1084. if (rc) {
  1085. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1086. sde_encoder_destroy(encoder);
  1087. continue;
  1088. }
  1089. connector = sde_connector_init(dev,
  1090. encoder,
  1091. 0,
  1092. display,
  1093. &wb_ops,
  1094. DRM_CONNECTOR_POLL_HPD,
  1095. DRM_MODE_CONNECTOR_VIRTUAL);
  1096. if (connector) {
  1097. priv->encoders[priv->num_encoders++] = encoder;
  1098. priv->connectors[priv->num_connectors++] = connector;
  1099. } else {
  1100. SDE_ERROR("wb %d connector init failed\n", i);
  1101. sde_wb_drm_deinit(display);
  1102. sde_encoder_destroy(encoder);
  1103. }
  1104. }
  1105. /* dp */
  1106. for (i = 0; i < sde_kms->dp_display_count &&
  1107. priv->num_encoders < max_encoders; ++i) {
  1108. int idx;
  1109. display = sde_kms->dp_displays[i];
  1110. encoder = NULL;
  1111. memset(&info, 0x0, sizeof(info));
  1112. rc = dp_connector_get_info(NULL, &info, display);
  1113. if (rc) {
  1114. SDE_ERROR("dp get_info %d failed\n", i);
  1115. continue;
  1116. }
  1117. encoder = sde_encoder_init(dev, &info);
  1118. if (IS_ERR_OR_NULL(encoder)) {
  1119. SDE_ERROR("dp encoder init failed %d\n", i);
  1120. continue;
  1121. }
  1122. rc = dp_drm_bridge_init(display, encoder);
  1123. if (rc) {
  1124. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1125. sde_encoder_destroy(encoder);
  1126. continue;
  1127. }
  1128. connector = sde_connector_init(dev,
  1129. encoder,
  1130. NULL,
  1131. display,
  1132. &dp_ops,
  1133. DRM_CONNECTOR_POLL_HPD,
  1134. DRM_MODE_CONNECTOR_DisplayPort);
  1135. if (connector) {
  1136. priv->encoders[priv->num_encoders++] = encoder;
  1137. priv->connectors[priv->num_connectors++] = connector;
  1138. } else {
  1139. SDE_ERROR("dp %d connector init failed\n", i);
  1140. dp_drm_bridge_deinit(display);
  1141. sde_encoder_destroy(encoder);
  1142. }
  1143. /* update display cap to MST_MODE for DP MST encoders */
  1144. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1145. for (idx = 0; idx < sde_kms->dp_stream_count; idx++) {
  1146. info.h_tile_instance[0] = idx;
  1147. encoder = sde_encoder_init(dev, &info);
  1148. if (IS_ERR_OR_NULL(encoder)) {
  1149. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1150. continue;
  1151. }
  1152. rc = dp_mst_drm_bridge_init(display, encoder);
  1153. if (rc) {
  1154. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1155. i, rc);
  1156. sde_encoder_destroy(encoder);
  1157. continue;
  1158. }
  1159. priv->encoders[priv->num_encoders++] = encoder;
  1160. }
  1161. }
  1162. return 0;
  1163. }
  1164. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1165. {
  1166. struct msm_drm_private *priv;
  1167. int i;
  1168. if (!sde_kms) {
  1169. SDE_ERROR("invalid sde_kms\n");
  1170. return;
  1171. } else if (!sde_kms->dev) {
  1172. SDE_ERROR("invalid dev\n");
  1173. return;
  1174. } else if (!sde_kms->dev->dev_private) {
  1175. SDE_ERROR("invalid dev_private\n");
  1176. return;
  1177. }
  1178. priv = sde_kms->dev->dev_private;
  1179. for (i = 0; i < priv->num_crtcs; i++)
  1180. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1181. priv->num_crtcs = 0;
  1182. for (i = 0; i < priv->num_planes; i++)
  1183. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1184. priv->num_planes = 0;
  1185. for (i = 0; i < priv->num_connectors; i++)
  1186. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1187. priv->num_connectors = 0;
  1188. for (i = 0; i < priv->num_encoders; i++)
  1189. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1190. priv->num_encoders = 0;
  1191. _sde_kms_release_displays(sde_kms);
  1192. }
  1193. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1194. {
  1195. struct drm_device *dev;
  1196. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1197. struct drm_crtc *crtc;
  1198. struct msm_drm_private *priv;
  1199. struct sde_mdss_cfg *catalog;
  1200. int primary_planes_idx = 0, i, ret;
  1201. int max_crtc_count;
  1202. u32 sspp_id[MAX_PLANES];
  1203. u32 master_plane_id[MAX_PLANES];
  1204. u32 num_virt_planes = 0;
  1205. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1206. SDE_ERROR("invalid sde_kms\n");
  1207. return -EINVAL;
  1208. }
  1209. dev = sde_kms->dev;
  1210. priv = dev->dev_private;
  1211. catalog = sde_kms->catalog;
  1212. ret = sde_core_irq_domain_add(sde_kms);
  1213. if (ret)
  1214. goto fail_irq;
  1215. /*
  1216. * Query for underlying display drivers, and create connectors,
  1217. * bridges and encoders for them.
  1218. */
  1219. if (!_sde_kms_get_displays(sde_kms))
  1220. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1221. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1222. /* Create the planes */
  1223. for (i = 0; i < catalog->sspp_count; i++) {
  1224. bool primary = true;
  1225. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1226. || primary_planes_idx >= max_crtc_count)
  1227. primary = false;
  1228. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1229. (1UL << max_crtc_count) - 1, 0);
  1230. if (IS_ERR(plane)) {
  1231. SDE_ERROR("sde_plane_init failed\n");
  1232. ret = PTR_ERR(plane);
  1233. goto fail;
  1234. }
  1235. priv->planes[priv->num_planes++] = plane;
  1236. if (primary)
  1237. primary_planes[primary_planes_idx++] = plane;
  1238. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1239. sde_is_custom_client()) {
  1240. int priority =
  1241. catalog->sspp[i].sblk->smart_dma_priority;
  1242. sspp_id[priority - 1] = catalog->sspp[i].id;
  1243. master_plane_id[priority - 1] = plane->base.id;
  1244. num_virt_planes++;
  1245. }
  1246. }
  1247. /* Initialize smart DMA virtual planes */
  1248. for (i = 0; i < num_virt_planes; i++) {
  1249. plane = sde_plane_init(dev, sspp_id[i], false,
  1250. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1251. if (IS_ERR(plane)) {
  1252. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1253. ret = PTR_ERR(plane);
  1254. goto fail;
  1255. }
  1256. priv->planes[priv->num_planes++] = plane;
  1257. }
  1258. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1259. /* Create one CRTC per encoder */
  1260. for (i = 0; i < max_crtc_count; i++) {
  1261. crtc = sde_crtc_init(dev, primary_planes[i]);
  1262. if (IS_ERR(crtc)) {
  1263. ret = PTR_ERR(crtc);
  1264. goto fail;
  1265. }
  1266. priv->crtcs[priv->num_crtcs++] = crtc;
  1267. }
  1268. if (sde_is_custom_client()) {
  1269. /* All CRTCs are compatible with all planes */
  1270. for (i = 0; i < priv->num_planes; i++)
  1271. priv->planes[i]->possible_crtcs =
  1272. (1 << priv->num_crtcs) - 1;
  1273. }
  1274. /* All CRTCs are compatible with all encoders */
  1275. for (i = 0; i < priv->num_encoders; i++)
  1276. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1277. return 0;
  1278. fail:
  1279. _sde_kms_drm_obj_destroy(sde_kms);
  1280. fail_irq:
  1281. sde_core_irq_domain_fini(sde_kms);
  1282. return ret;
  1283. }
  1284. /**
  1285. * sde_kms_timeline_status - provides current timeline status
  1286. * This API should be called without mode config lock.
  1287. * @dev: Pointer to drm device
  1288. */
  1289. void sde_kms_timeline_status(struct drm_device *dev)
  1290. {
  1291. struct drm_crtc *crtc;
  1292. struct drm_connector *conn;
  1293. struct drm_connector_list_iter conn_iter;
  1294. if (!dev) {
  1295. SDE_ERROR("invalid drm device node\n");
  1296. return;
  1297. }
  1298. drm_for_each_crtc(crtc, dev)
  1299. sde_crtc_timeline_status(crtc);
  1300. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1301. /*
  1302. *Probably locked from last close dumping status anyway
  1303. */
  1304. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1305. drm_connector_list_iter_begin(dev, &conn_iter);
  1306. drm_for_each_connector_iter(conn, &conn_iter)
  1307. sde_conn_timeline_status(conn);
  1308. drm_connector_list_iter_end(&conn_iter);
  1309. return;
  1310. }
  1311. mutex_lock(&dev->mode_config.mutex);
  1312. drm_connector_list_iter_begin(dev, &conn_iter);
  1313. drm_for_each_connector_iter(conn, &conn_iter)
  1314. sde_conn_timeline_status(conn);
  1315. drm_connector_list_iter_end(&conn_iter);
  1316. mutex_unlock(&dev->mode_config.mutex);
  1317. }
  1318. static int sde_kms_postinit(struct msm_kms *kms)
  1319. {
  1320. struct sde_kms *sde_kms = to_sde_kms(kms);
  1321. struct drm_device *dev;
  1322. struct drm_crtc *crtc;
  1323. int rc;
  1324. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1325. SDE_ERROR("invalid sde_kms\n");
  1326. return -EINVAL;
  1327. }
  1328. dev = sde_kms->dev;
  1329. rc = _sde_debugfs_init(sde_kms);
  1330. if (rc)
  1331. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1332. drm_for_each_crtc(crtc, dev)
  1333. sde_crtc_post_init(dev, crtc);
  1334. return rc;
  1335. }
  1336. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1337. struct drm_encoder *encoder)
  1338. {
  1339. return rate;
  1340. }
  1341. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1342. struct platform_device *pdev)
  1343. {
  1344. struct drm_device *dev;
  1345. struct msm_drm_private *priv;
  1346. int i;
  1347. if (!sde_kms || !pdev)
  1348. return;
  1349. dev = sde_kms->dev;
  1350. if (!dev)
  1351. return;
  1352. priv = dev->dev_private;
  1353. if (!priv)
  1354. return;
  1355. if (sde_kms->genpd_init) {
  1356. sde_kms->genpd_init = false;
  1357. pm_genpd_remove(&sde_kms->genpd);
  1358. of_genpd_del_provider(pdev->dev.of_node);
  1359. }
  1360. if (sde_kms->hw_intr)
  1361. sde_hw_intr_destroy(sde_kms->hw_intr);
  1362. sde_kms->hw_intr = NULL;
  1363. if (sde_kms->power_event)
  1364. sde_power_handle_unregister_event(
  1365. &priv->phandle, sde_kms->power_event);
  1366. _sde_kms_release_displays(sde_kms);
  1367. _sde_kms_unmap_all_splash_regions(sde_kms);
  1368. /* safe to call these more than once during shutdown */
  1369. _sde_debugfs_destroy(sde_kms);
  1370. _sde_kms_mmu_destroy(sde_kms);
  1371. if (sde_kms->catalog) {
  1372. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1373. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1374. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1375. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1376. }
  1377. }
  1378. if (sde_kms->rm_init)
  1379. sde_rm_destroy(&sde_kms->rm);
  1380. sde_kms->rm_init = false;
  1381. if (sde_kms->catalog)
  1382. sde_hw_catalog_deinit(sde_kms->catalog);
  1383. sde_kms->catalog = NULL;
  1384. if (sde_kms->sid)
  1385. msm_iounmap(pdev, sde_kms->sid);
  1386. sde_kms->sid = NULL;
  1387. if (sde_kms->reg_dma)
  1388. msm_iounmap(pdev, sde_kms->reg_dma);
  1389. sde_kms->reg_dma = NULL;
  1390. if (sde_kms->vbif[VBIF_NRT])
  1391. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1392. sde_kms->vbif[VBIF_NRT] = NULL;
  1393. if (sde_kms->vbif[VBIF_RT])
  1394. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1395. sde_kms->vbif[VBIF_RT] = NULL;
  1396. if (sde_kms->mmio)
  1397. msm_iounmap(pdev, sde_kms->mmio);
  1398. sde_kms->mmio = NULL;
  1399. sde_reg_dma_deinit();
  1400. }
  1401. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1402. {
  1403. int i;
  1404. if (!sde_kms)
  1405. return -EINVAL;
  1406. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1407. struct msm_mmu *mmu;
  1408. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1409. if (!aspace)
  1410. continue;
  1411. mmu = sde_kms->aspace[i]->mmu;
  1412. if (secure_only &&
  1413. !aspace->mmu->funcs->is_domain_secure(mmu))
  1414. continue;
  1415. /* cleanup aspace before detaching */
  1416. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1417. SDE_DEBUG("Detaching domain:%d\n", i);
  1418. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1419. ARRAY_SIZE(iommu_ports));
  1420. aspace->domain_attached = false;
  1421. }
  1422. return 0;
  1423. }
  1424. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1425. {
  1426. int i;
  1427. if (!sde_kms)
  1428. return -EINVAL;
  1429. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1430. struct msm_mmu *mmu;
  1431. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1432. if (!aspace)
  1433. continue;
  1434. mmu = sde_kms->aspace[i]->mmu;
  1435. if (secure_only &&
  1436. !aspace->mmu->funcs->is_domain_secure(mmu))
  1437. continue;
  1438. SDE_DEBUG("Attaching domain:%d\n", i);
  1439. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1440. ARRAY_SIZE(iommu_ports));
  1441. aspace->domain_attached = true;
  1442. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1443. }
  1444. return 0;
  1445. }
  1446. static void sde_kms_destroy(struct msm_kms *kms)
  1447. {
  1448. struct sde_kms *sde_kms;
  1449. struct drm_device *dev;
  1450. if (!kms) {
  1451. SDE_ERROR("invalid kms\n");
  1452. return;
  1453. }
  1454. sde_kms = to_sde_kms(kms);
  1455. dev = sde_kms->dev;
  1456. if (!dev || !dev->dev) {
  1457. SDE_ERROR("invalid device\n");
  1458. return;
  1459. }
  1460. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1461. kfree(sde_kms);
  1462. }
  1463. static void _sde_kms_plane_force_remove(struct drm_plane *plane,
  1464. struct drm_atomic_state *state)
  1465. {
  1466. struct drm_plane_state *plane_state;
  1467. int ret = 0;
  1468. plane_state = drm_atomic_get_plane_state(state, plane);
  1469. if (IS_ERR(plane_state)) {
  1470. ret = PTR_ERR(plane_state);
  1471. SDE_ERROR("error %d getting plane %d state\n",
  1472. ret, plane->base.id);
  1473. return;
  1474. }
  1475. plane->old_fb = plane->fb;
  1476. SDE_DEBUG("disabling plane %d\n", plane->base.id);
  1477. ret = __drm_atomic_helper_disable_plane(plane, plane_state);
  1478. if (ret != 0)
  1479. SDE_ERROR("error %d disabling plane %d\n", ret,
  1480. plane->base.id);
  1481. }
  1482. static int _sde_kms_remove_fbs(struct sde_kms *sde_kms, struct drm_file *file,
  1483. struct drm_atomic_state *state)
  1484. {
  1485. struct drm_device *dev = sde_kms->dev;
  1486. struct drm_framebuffer *fb, *tfb;
  1487. struct list_head fbs;
  1488. struct drm_plane *plane;
  1489. int ret = 0;
  1490. u32 plane_mask = 0;
  1491. INIT_LIST_HEAD(&fbs);
  1492. list_for_each_entry_safe(fb, tfb, &file->fbs, filp_head) {
  1493. if (drm_framebuffer_read_refcount(fb) > 1) {
  1494. list_move_tail(&fb->filp_head, &fbs);
  1495. drm_for_each_plane(plane, dev) {
  1496. if (plane->fb == fb) {
  1497. plane_mask |=
  1498. 1 << drm_plane_index(plane);
  1499. _sde_kms_plane_force_remove(
  1500. plane, state);
  1501. }
  1502. }
  1503. } else {
  1504. list_del_init(&fb->filp_head);
  1505. drm_framebuffer_put(fb);
  1506. }
  1507. }
  1508. if (list_empty(&fbs)) {
  1509. SDE_DEBUG("skip commit as no fb(s)\n");
  1510. drm_atomic_state_put(state);
  1511. return 0;
  1512. }
  1513. SDE_DEBUG("committing after removing all the pipes\n");
  1514. ret = drm_atomic_commit(state);
  1515. if (ret) {
  1516. /*
  1517. * move the fbs back to original list, so it would be
  1518. * handled during drm_release
  1519. */
  1520. list_for_each_entry_safe(fb, tfb, &fbs, filp_head)
  1521. list_move_tail(&fb->filp_head, &file->fbs);
  1522. SDE_ERROR("atomic commit failed in preclose, ret:%d\n", ret);
  1523. goto end;
  1524. }
  1525. while (!list_empty(&fbs)) {
  1526. fb = list_first_entry(&fbs, typeof(*fb), filp_head);
  1527. list_del_init(&fb->filp_head);
  1528. drm_framebuffer_put(fb);
  1529. }
  1530. end:
  1531. return ret;
  1532. }
  1533. static void sde_kms_preclose(struct msm_kms *kms, struct drm_file *file)
  1534. {
  1535. struct sde_kms *sde_kms = to_sde_kms(kms);
  1536. struct drm_device *dev = sde_kms->dev;
  1537. struct msm_drm_private *priv = dev->dev_private;
  1538. unsigned int i;
  1539. struct drm_atomic_state *state = NULL;
  1540. struct drm_modeset_acquire_ctx ctx;
  1541. int ret = 0;
  1542. /* cancel pending flip event */
  1543. for (i = 0; i < priv->num_crtcs; i++)
  1544. sde_crtc_complete_flip(priv->crtcs[i], file);
  1545. drm_modeset_acquire_init(&ctx, 0);
  1546. retry:
  1547. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  1548. if (ret == -EDEADLK) {
  1549. drm_modeset_backoff(&ctx);
  1550. goto retry;
  1551. } else if (WARN_ON(ret)) {
  1552. goto end;
  1553. }
  1554. state = drm_atomic_state_alloc(dev);
  1555. if (!state) {
  1556. ret = -ENOMEM;
  1557. goto end;
  1558. }
  1559. state->acquire_ctx = &ctx;
  1560. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  1561. ret = _sde_kms_remove_fbs(sde_kms, file, state);
  1562. if (ret != -EDEADLK)
  1563. break;
  1564. drm_atomic_state_clear(state);
  1565. drm_modeset_backoff(&ctx);
  1566. }
  1567. end:
  1568. if (state)
  1569. drm_atomic_state_put(state);
  1570. SDE_DEBUG("sde preclose done, ret:%d\n", ret);
  1571. drm_modeset_drop_locks(&ctx);
  1572. drm_modeset_acquire_fini(&ctx);
  1573. }
  1574. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1575. struct drm_atomic_state *state)
  1576. {
  1577. struct drm_device *dev = sde_kms->dev;
  1578. struct drm_plane *plane;
  1579. struct drm_plane_state *plane_state;
  1580. struct drm_crtc *crtc;
  1581. struct drm_crtc_state *crtc_state;
  1582. struct drm_connector *conn;
  1583. struct drm_connector_state *conn_state;
  1584. struct drm_connector_list_iter conn_iter;
  1585. int ret = 0;
  1586. drm_for_each_plane(plane, dev) {
  1587. plane_state = drm_atomic_get_plane_state(state, plane);
  1588. if (IS_ERR(plane_state)) {
  1589. ret = PTR_ERR(plane_state);
  1590. SDE_ERROR("error %d getting plane %d state\n",
  1591. ret, DRMID(plane));
  1592. return ret;
  1593. }
  1594. ret = sde_plane_helper_reset_custom_properties(plane,
  1595. plane_state);
  1596. if (ret) {
  1597. SDE_ERROR("error %d resetting plane props %d\n",
  1598. ret, DRMID(plane));
  1599. return ret;
  1600. }
  1601. }
  1602. drm_for_each_crtc(crtc, dev) {
  1603. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1604. if (IS_ERR(crtc_state)) {
  1605. ret = PTR_ERR(crtc_state);
  1606. SDE_ERROR("error %d getting crtc %d state\n",
  1607. ret, DRMID(crtc));
  1608. return ret;
  1609. }
  1610. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1611. if (ret) {
  1612. SDE_ERROR("error %d resetting crtc props %d\n",
  1613. ret, DRMID(crtc));
  1614. return ret;
  1615. }
  1616. }
  1617. drm_connector_list_iter_begin(dev, &conn_iter);
  1618. drm_for_each_connector_iter(conn, &conn_iter) {
  1619. conn_state = drm_atomic_get_connector_state(state, conn);
  1620. if (IS_ERR(conn_state)) {
  1621. ret = PTR_ERR(conn_state);
  1622. SDE_ERROR("error %d getting connector %d state\n",
  1623. ret, DRMID(conn));
  1624. return ret;
  1625. }
  1626. ret = sde_connector_helper_reset_custom_properties(conn,
  1627. conn_state);
  1628. if (ret) {
  1629. SDE_ERROR("error %d resetting connector props %d\n",
  1630. ret, DRMID(conn));
  1631. return ret;
  1632. }
  1633. }
  1634. drm_connector_list_iter_end(&conn_iter);
  1635. return ret;
  1636. }
  1637. static void sde_kms_lastclose(struct msm_kms *kms,
  1638. struct drm_modeset_acquire_ctx *ctx)
  1639. {
  1640. struct sde_kms *sde_kms;
  1641. struct drm_device *dev;
  1642. struct drm_atomic_state *state;
  1643. int ret, i;
  1644. if (!kms) {
  1645. SDE_ERROR("invalid argument\n");
  1646. return;
  1647. }
  1648. sde_kms = to_sde_kms(kms);
  1649. dev = sde_kms->dev;
  1650. state = drm_atomic_state_alloc(dev);
  1651. if (!state)
  1652. return;
  1653. state->acquire_ctx = ctx;
  1654. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  1655. /* add reset of custom properties to the state */
  1656. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  1657. if (ret)
  1658. break;
  1659. ret = drm_atomic_commit(state);
  1660. if (ret != -EDEADLK)
  1661. break;
  1662. drm_atomic_state_clear(state);
  1663. drm_modeset_backoff(ctx);
  1664. SDE_DEBUG("deadlock backoff on attempt %d\n", i);
  1665. }
  1666. if (ret)
  1667. SDE_ERROR("failed to run last close: %d\n", ret);
  1668. drm_atomic_state_put(state);
  1669. }
  1670. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  1671. struct drm_atomic_state *state)
  1672. {
  1673. struct sde_kms *sde_kms;
  1674. struct drm_device *dev;
  1675. struct drm_crtc *crtc;
  1676. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  1677. struct drm_crtc_state *crtc_state;
  1678. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  1679. bool sec_session = false, global_sec_session = false;
  1680. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  1681. int i;
  1682. if (!kms || !state) {
  1683. return -EINVAL;
  1684. SDE_ERROR("invalid arguments\n");
  1685. }
  1686. sde_kms = to_sde_kms(kms);
  1687. dev = sde_kms->dev;
  1688. /* iterate state object for active secure/non-secure crtc */
  1689. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  1690. if (!crtc_state->active)
  1691. continue;
  1692. active_crtc_cnt++;
  1693. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  1694. &fb_sec, &fb_sec_dir);
  1695. if (fb_sec_dir)
  1696. sec_session = true;
  1697. cur_crtc = crtc;
  1698. }
  1699. /* iterate global list for active and secure/non-secure crtc */
  1700. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1701. if (!crtc->state->active)
  1702. continue;
  1703. global_active_crtc_cnt++;
  1704. /* update only when crtc is not the same as current crtc */
  1705. if (crtc != cur_crtc) {
  1706. fb_ns = fb_sec = fb_sec_dir = 0;
  1707. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  1708. &fb_sec, &fb_sec_dir);
  1709. if (fb_sec_dir)
  1710. global_sec_session = true;
  1711. global_crtc = crtc;
  1712. }
  1713. }
  1714. if (!global_sec_session && !sec_session)
  1715. return 0;
  1716. /*
  1717. * - fail crtc commit, if secure-camera/secure-ui session is
  1718. * in-progress in any other display
  1719. * - fail secure-camera/secure-ui crtc commit, if any other display
  1720. * session is in-progress
  1721. */
  1722. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  1723. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  1724. SDE_ERROR(
  1725. "crtc%d secure check failed global_active:%d active:%d\n",
  1726. cur_crtc ? cur_crtc->base.id : -1,
  1727. global_active_crtc_cnt, active_crtc_cnt);
  1728. return -EPERM;
  1729. /*
  1730. * As only one crtc is allowed during secure session, the crtc
  1731. * in this commit should match with the global crtc
  1732. */
  1733. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  1734. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  1735. cur_crtc->base.id, sec_session,
  1736. global_crtc->base.id, global_sec_session);
  1737. return -EPERM;
  1738. }
  1739. return 0;
  1740. }
  1741. static int sde_kms_atomic_check(struct msm_kms *kms,
  1742. struct drm_atomic_state *state)
  1743. {
  1744. struct sde_kms *sde_kms;
  1745. struct drm_device *dev;
  1746. int ret;
  1747. if (!kms || !state)
  1748. return -EINVAL;
  1749. sde_kms = to_sde_kms(kms);
  1750. dev = sde_kms->dev;
  1751. SDE_ATRACE_BEGIN("atomic_check");
  1752. if (sde_kms_is_suspend_blocked(dev)) {
  1753. SDE_DEBUG("suspended, skip atomic_check\n");
  1754. ret = -EBUSY;
  1755. goto end;
  1756. }
  1757. ret = drm_atomic_helper_check(dev, state);
  1758. if (ret)
  1759. goto end;
  1760. /*
  1761. * Check if any secure transition(moving CRTC between secure and
  1762. * non-secure state and vice-versa) is allowed or not. when moving
  1763. * to secure state, planes with fb_mode set to dir_translated only can
  1764. * be staged on the CRTC, and only one CRTC can be active during
  1765. * Secure state
  1766. */
  1767. ret = sde_kms_check_secure_transition(kms, state);
  1768. end:
  1769. SDE_ATRACE_END("atomic_check");
  1770. return ret;
  1771. }
  1772. static struct msm_gem_address_space*
  1773. _sde_kms_get_address_space(struct msm_kms *kms,
  1774. unsigned int domain)
  1775. {
  1776. struct sde_kms *sde_kms;
  1777. if (!kms) {
  1778. SDE_ERROR("invalid kms\n");
  1779. return NULL;
  1780. }
  1781. sde_kms = to_sde_kms(kms);
  1782. if (!sde_kms) {
  1783. SDE_ERROR("invalid sde_kms\n");
  1784. return NULL;
  1785. }
  1786. if (domain >= MSM_SMMU_DOMAIN_MAX)
  1787. return NULL;
  1788. return (sde_kms->aspace[domain] &&
  1789. sde_kms->aspace[domain]->domain_attached) ?
  1790. sde_kms->aspace[domain] : NULL;
  1791. }
  1792. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  1793. unsigned int domain)
  1794. {
  1795. struct msm_gem_address_space *aspace =
  1796. _sde_kms_get_address_space(kms, domain);
  1797. return (aspace && aspace->domain_attached) ?
  1798. msm_gem_get_aspace_device(aspace) : NULL;
  1799. }
  1800. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  1801. {
  1802. struct drm_device *dev = NULL;
  1803. struct sde_kms *sde_kms = NULL;
  1804. struct drm_connector *connector = NULL;
  1805. struct drm_connector_list_iter conn_iter;
  1806. struct sde_connector *sde_conn = NULL;
  1807. int i;
  1808. if (!kms) {
  1809. SDE_ERROR("invalid kms\n");
  1810. return;
  1811. }
  1812. sde_kms = to_sde_kms(kms);
  1813. dev = sde_kms->dev;
  1814. if (!dev) {
  1815. SDE_ERROR("invalid device\n");
  1816. return;
  1817. }
  1818. if (!dev->mode_config.poll_enabled)
  1819. return;
  1820. /* init external dsi bridge here to make sure ext bridge is probed*/
  1821. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  1822. struct dsi_display *dsi_display;
  1823. dsi_display = sde_kms->dsi_displays[i];
  1824. if (dsi_display->bridge) {
  1825. dsi_display_drm_ext_bridge_init(dsi_display,
  1826. dsi_display->bridge->base.encoder,
  1827. dsi_display->drm_conn);
  1828. }
  1829. }
  1830. mutex_lock(&dev->mode_config.mutex);
  1831. drm_connector_list_iter_begin(dev, &conn_iter);
  1832. drm_for_each_connector_iter(connector, &conn_iter) {
  1833. /* Only handle HPD capable connectors. */
  1834. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  1835. continue;
  1836. sde_conn = to_sde_connector(connector);
  1837. if (sde_conn->ops.post_open)
  1838. sde_conn->ops.post_open(&sde_conn->base,
  1839. sde_conn->display);
  1840. }
  1841. drm_connector_list_iter_end(&conn_iter);
  1842. mutex_unlock(&dev->mode_config.mutex);
  1843. }
  1844. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  1845. struct sde_splash_display *splash_display,
  1846. struct drm_crtc *crtc)
  1847. {
  1848. struct msm_drm_private *priv;
  1849. struct drm_plane *plane;
  1850. struct sde_splash_mem *splash;
  1851. enum sde_sspp plane_id;
  1852. bool is_virtual;
  1853. int i, j;
  1854. if (!sde_kms || !splash_display || !crtc) {
  1855. SDE_ERROR("invalid input args\n");
  1856. return -EINVAL;
  1857. }
  1858. priv = sde_kms->dev->dev_private;
  1859. for (i = 0; i < priv->num_planes; i++) {
  1860. plane = priv->planes[i];
  1861. plane_id = sde_plane_pipe(plane);
  1862. is_virtual = is_sde_plane_virtual(plane);
  1863. splash = splash_display->splash;
  1864. for (j = 0; j < splash_display->pipe_cnt; j++) {
  1865. if ((plane_id != splash_display->pipes[j].sspp) ||
  1866. (splash_display->pipes[j].is_virtual
  1867. != is_virtual))
  1868. continue;
  1869. if (splash && sde_plane_validate_src_addr(plane,
  1870. splash->splash_buf_base,
  1871. splash->splash_buf_size)) {
  1872. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  1873. plane_id, crtc->base.id);
  1874. }
  1875. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  1876. crtc->base.id, plane_id, is_virtual);
  1877. }
  1878. }
  1879. return 0;
  1880. }
  1881. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  1882. {
  1883. void *display;
  1884. struct dsi_display *dsi_display;
  1885. struct msm_display_info info;
  1886. struct drm_encoder *encoder = NULL;
  1887. struct drm_crtc *crtc = NULL;
  1888. int i, rc = 0;
  1889. struct drm_display_mode *drm_mode = NULL;
  1890. struct drm_device *dev;
  1891. struct msm_drm_private *priv;
  1892. struct sde_kms *sde_kms;
  1893. struct drm_connector_list_iter conn_iter;
  1894. struct drm_connector *connector = NULL;
  1895. struct sde_connector *sde_conn = NULL;
  1896. struct sde_splash_display *splash_display;
  1897. if (!kms) {
  1898. SDE_ERROR("invalid kms\n");
  1899. return -EINVAL;
  1900. }
  1901. sde_kms = to_sde_kms(kms);
  1902. dev = sde_kms->dev;
  1903. if (!dev) {
  1904. SDE_ERROR("invalid device\n");
  1905. return -EINVAL;
  1906. }
  1907. if (!sde_kms->splash_data.num_splash_regions ||
  1908. !sde_kms->splash_data.num_splash_displays) {
  1909. DRM_INFO("cont_splash feature not enabled\n");
  1910. return rc;
  1911. }
  1912. if (sde_kms->dsi_display_count !=
  1913. sde_kms->splash_data.num_splash_displays) {
  1914. SDE_ERROR("mismatch - displays:%d vs splash-displays:%d\n",
  1915. sde_kms->dsi_display_count,
  1916. sde_kms->splash_data.num_splash_displays);
  1917. return rc;
  1918. }
  1919. /* dsi */
  1920. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  1921. display = sde_kms->dsi_displays[i];
  1922. dsi_display = (struct dsi_display *)display;
  1923. splash_display = &sde_kms->splash_data.splash_display[i];
  1924. if (!splash_display->cont_splash_enabled) {
  1925. SDE_DEBUG("display->name = %s splash not enabled\n",
  1926. dsi_display->name);
  1927. continue;
  1928. }
  1929. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  1930. if (dsi_display->bridge->base.encoder) {
  1931. encoder = dsi_display->bridge->base.encoder;
  1932. SDE_DEBUG("encoder name = %s\n", encoder->name);
  1933. }
  1934. memset(&info, 0x0, sizeof(info));
  1935. rc = dsi_display_get_info(NULL, &info, display);
  1936. if (rc) {
  1937. SDE_ERROR("dsi get_info %d failed\n", i);
  1938. encoder = NULL;
  1939. continue;
  1940. }
  1941. SDE_DEBUG("info.is_connected = %s, info.is_primary = %s\n",
  1942. ((info.is_connected) ? "true" : "false"),
  1943. ((info.is_primary) ? "true" : "false"));
  1944. if (!encoder) {
  1945. SDE_ERROR("encoder not initialized\n");
  1946. return -EINVAL;
  1947. }
  1948. priv = sde_kms->dev->dev_private;
  1949. encoder->crtc = priv->crtcs[i];
  1950. crtc = encoder->crtc;
  1951. splash_display->encoder = encoder;
  1952. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  1953. i, crtc->base.id, encoder->base.id);
  1954. mutex_lock(&dev->mode_config.mutex);
  1955. drm_connector_list_iter_begin(dev, &conn_iter);
  1956. drm_for_each_connector_iter(connector, &conn_iter) {
  1957. /**
  1958. * SDE_KMS doesn't attach more than one encoder to
  1959. * a DSI connector. So it is safe to check only with
  1960. * the first encoder entry. Revisit this logic if we
  1961. * ever have to support continuous splash for
  1962. * external displays in MST configuration.
  1963. */
  1964. if (connector->encoder_ids[0] == encoder->base.id)
  1965. break;
  1966. }
  1967. drm_connector_list_iter_end(&conn_iter);
  1968. if (!connector) {
  1969. SDE_ERROR("connector not initialized\n");
  1970. mutex_unlock(&dev->mode_config.mutex);
  1971. return -EINVAL;
  1972. }
  1973. if (connector->funcs->fill_modes) {
  1974. connector->funcs->fill_modes(connector,
  1975. dev->mode_config.max_width,
  1976. dev->mode_config.max_height);
  1977. } else {
  1978. SDE_ERROR("fill_modes api not defined\n");
  1979. mutex_unlock(&dev->mode_config.mutex);
  1980. return -EINVAL;
  1981. }
  1982. mutex_unlock(&dev->mode_config.mutex);
  1983. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  1984. /* currently consider modes[0] as the preferred mode */
  1985. drm_mode = list_first_entry(&connector->modes,
  1986. struct drm_display_mode, head);
  1987. SDE_DEBUG("drm_mode->name = %s, id=%d, type=0x%x, flags=0x%x\n",
  1988. drm_mode->name, drm_mode->base.id,
  1989. drm_mode->type, drm_mode->flags);
  1990. /* Update CRTC drm structure */
  1991. crtc->state->active = true;
  1992. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  1993. if (rc) {
  1994. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  1995. return rc;
  1996. }
  1997. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  1998. drm_mode_copy(&crtc->mode, drm_mode);
  1999. /* Update encoder structure */
  2000. sde_encoder_update_caps_for_cont_splash(encoder,
  2001. splash_display, true);
  2002. sde_crtc_update_cont_splash_settings(crtc);
  2003. sde_conn = to_sde_connector(connector);
  2004. if (sde_conn && sde_conn->ops.cont_splash_config)
  2005. sde_conn->ops.cont_splash_config(sde_conn->display);
  2006. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2007. splash_display, crtc);
  2008. if (rc) {
  2009. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2010. return rc;
  2011. }
  2012. }
  2013. return rc;
  2014. }
  2015. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2016. {
  2017. struct sde_kms *sde_kms;
  2018. if (!kms) {
  2019. SDE_ERROR("invalid kms\n");
  2020. return false;
  2021. }
  2022. sde_kms = to_sde_kms(kms);
  2023. return sde_kms->splash_data.num_splash_displays;
  2024. }
  2025. static void _sde_kms_null_commit(struct drm_device *dev,
  2026. struct drm_encoder *enc)
  2027. {
  2028. struct drm_modeset_acquire_ctx ctx;
  2029. struct drm_connector *conn = NULL;
  2030. struct drm_connector *tmp_conn = NULL;
  2031. struct drm_connector_list_iter conn_iter;
  2032. struct drm_atomic_state *state = NULL;
  2033. struct drm_crtc_state *crtc_state = NULL;
  2034. struct drm_connector_state *conn_state = NULL;
  2035. int retry_cnt = 0;
  2036. int ret = 0;
  2037. drm_modeset_acquire_init(&ctx, 0);
  2038. retry:
  2039. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2040. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2041. drm_modeset_backoff(&ctx);
  2042. retry_cnt++;
  2043. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2044. goto retry;
  2045. } else if (WARN_ON(ret)) {
  2046. goto end;
  2047. }
  2048. state = drm_atomic_state_alloc(dev);
  2049. if (!state) {
  2050. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2051. goto end;
  2052. }
  2053. state->acquire_ctx = &ctx;
  2054. drm_connector_list_iter_begin(dev, &conn_iter);
  2055. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2056. if (enc == tmp_conn->state->best_encoder) {
  2057. conn = tmp_conn;
  2058. break;
  2059. }
  2060. }
  2061. drm_connector_list_iter_end(&conn_iter);
  2062. if (!conn) {
  2063. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2064. goto end;
  2065. }
  2066. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2067. conn_state = drm_atomic_get_connector_state(state, conn);
  2068. if (IS_ERR(conn_state)) {
  2069. SDE_ERROR("error %d getting connector %d state\n",
  2070. ret, DRMID(conn));
  2071. goto end;
  2072. }
  2073. crtc_state->active = true;
  2074. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2075. if (ret)
  2076. SDE_ERROR("error %d setting the crtc\n", ret);
  2077. ret = drm_atomic_commit(state);
  2078. if (ret)
  2079. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2080. end:
  2081. if (state)
  2082. drm_atomic_state_put(state);
  2083. drm_modeset_drop_locks(&ctx);
  2084. drm_modeset_acquire_fini(&ctx);
  2085. }
  2086. static int sde_kms_pm_suspend(struct device *dev)
  2087. {
  2088. struct drm_device *ddev;
  2089. struct drm_modeset_acquire_ctx ctx;
  2090. struct drm_connector *conn;
  2091. struct drm_encoder *enc;
  2092. struct drm_connector_list_iter conn_iter;
  2093. struct drm_atomic_state *state = NULL;
  2094. struct sde_kms *sde_kms;
  2095. int ret = 0, num_crtcs = 0;
  2096. if (!dev)
  2097. return -EINVAL;
  2098. ddev = dev_get_drvdata(dev);
  2099. if (!ddev || !ddev_to_msm_kms(ddev))
  2100. return -EINVAL;
  2101. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2102. SDE_EVT32(0);
  2103. /* disable hot-plug polling */
  2104. drm_kms_helper_poll_disable(ddev);
  2105. /* if a display stuck in CS trigger a null commit to complete handoff */
  2106. drm_for_each_encoder(enc, ddev) {
  2107. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2108. _sde_kms_null_commit(ddev, enc);
  2109. }
  2110. /* acquire modeset lock(s) */
  2111. drm_modeset_acquire_init(&ctx, 0);
  2112. retry:
  2113. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2114. if (ret)
  2115. goto unlock;
  2116. /* save current state for resume */
  2117. if (sde_kms->suspend_state)
  2118. drm_atomic_state_put(sde_kms->suspend_state);
  2119. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2120. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2121. ret = PTR_ERR(sde_kms->suspend_state);
  2122. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2123. sde_kms->suspend_state = NULL;
  2124. goto unlock;
  2125. }
  2126. /* create atomic state to disable all CRTCs */
  2127. state = drm_atomic_state_alloc(ddev);
  2128. if (!state) {
  2129. ret = -ENOMEM;
  2130. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2131. goto unlock;
  2132. }
  2133. state->acquire_ctx = &ctx;
  2134. drm_connector_list_iter_begin(ddev, &conn_iter);
  2135. drm_for_each_connector_iter(conn, &conn_iter) {
  2136. struct drm_crtc_state *crtc_state;
  2137. uint64_t lp;
  2138. if (!conn->state || !conn->state->crtc ||
  2139. conn->dpms != DRM_MODE_DPMS_ON)
  2140. continue;
  2141. lp = sde_connector_get_lp(conn);
  2142. if (lp == SDE_MODE_DPMS_LP1) {
  2143. /* transition LP1->LP2 on pm suspend */
  2144. ret = sde_connector_set_property_for_commit(conn, state,
  2145. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2146. if (ret) {
  2147. DRM_ERROR("failed to set lp2 for conn %d\n",
  2148. conn->base.id);
  2149. drm_connector_list_iter_end(&conn_iter);
  2150. goto unlock;
  2151. }
  2152. }
  2153. if (lp != SDE_MODE_DPMS_LP2) {
  2154. /* force CRTC to be inactive */
  2155. crtc_state = drm_atomic_get_crtc_state(state,
  2156. conn->state->crtc);
  2157. if (IS_ERR_OR_NULL(crtc_state)) {
  2158. DRM_ERROR("failed to get crtc %d state\n",
  2159. conn->state->crtc->base.id);
  2160. drm_connector_list_iter_end(&conn_iter);
  2161. goto unlock;
  2162. }
  2163. if (lp != SDE_MODE_DPMS_LP1)
  2164. crtc_state->active = false;
  2165. ++num_crtcs;
  2166. }
  2167. }
  2168. drm_connector_list_iter_end(&conn_iter);
  2169. /* check for nothing to do */
  2170. if (num_crtcs == 0) {
  2171. DRM_DEBUG("all crtcs are already in the off state\n");
  2172. sde_kms->suspend_block = true;
  2173. goto unlock;
  2174. }
  2175. /* commit the "disable all" state */
  2176. ret = drm_atomic_commit(state);
  2177. if (ret < 0) {
  2178. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2179. goto unlock;
  2180. }
  2181. sde_kms->suspend_block = true;
  2182. drm_connector_list_iter_begin(ddev, &conn_iter);
  2183. drm_for_each_connector_iter(conn, &conn_iter) {
  2184. uint64_t lp;
  2185. lp = sde_connector_get_lp(conn);
  2186. if (lp != SDE_MODE_DPMS_LP2)
  2187. continue;
  2188. ret = sde_encoder_wait_for_event(conn->encoder,
  2189. MSM_ENC_TX_COMPLETE);
  2190. if (ret && ret != -EWOULDBLOCK)
  2191. SDE_ERROR(
  2192. "[enc: %d] wait for commit done returned %d\n",
  2193. conn->encoder->base.id, ret);
  2194. else if (!ret)
  2195. sde_encoder_idle_request(conn->encoder);
  2196. }
  2197. drm_connector_list_iter_end(&conn_iter);
  2198. unlock:
  2199. if (state) {
  2200. drm_atomic_state_put(state);
  2201. state = NULL;
  2202. }
  2203. if (ret == -EDEADLK) {
  2204. drm_modeset_backoff(&ctx);
  2205. goto retry;
  2206. }
  2207. drm_modeset_drop_locks(&ctx);
  2208. drm_modeset_acquire_fini(&ctx);
  2209. return ret;
  2210. }
  2211. static int sde_kms_pm_resume(struct device *dev)
  2212. {
  2213. struct drm_device *ddev;
  2214. struct sde_kms *sde_kms;
  2215. struct drm_modeset_acquire_ctx ctx;
  2216. int ret, i;
  2217. if (!dev)
  2218. return -EINVAL;
  2219. ddev = dev_get_drvdata(dev);
  2220. if (!ddev || !ddev_to_msm_kms(ddev))
  2221. return -EINVAL;
  2222. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2223. SDE_EVT32(sde_kms->suspend_state != NULL);
  2224. drm_mode_config_reset(ddev);
  2225. drm_modeset_acquire_init(&ctx, 0);
  2226. retry:
  2227. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2228. if (ret == -EDEADLK) {
  2229. drm_modeset_backoff(&ctx);
  2230. goto retry;
  2231. } else if (WARN_ON(ret)) {
  2232. goto end;
  2233. }
  2234. sde_kms->suspend_block = false;
  2235. if (sde_kms->suspend_state) {
  2236. sde_kms->suspend_state->acquire_ctx = &ctx;
  2237. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2238. ret = drm_atomic_helper_commit_duplicated_state(
  2239. sde_kms->suspend_state, &ctx);
  2240. if (ret != -EDEADLK)
  2241. break;
  2242. drm_modeset_backoff(&ctx);
  2243. }
  2244. if (ret < 0)
  2245. DRM_ERROR("failed to restore state, %d\n", ret);
  2246. drm_atomic_state_put(sde_kms->suspend_state);
  2247. sde_kms->suspend_state = NULL;
  2248. }
  2249. end:
  2250. drm_modeset_drop_locks(&ctx);
  2251. drm_modeset_acquire_fini(&ctx);
  2252. /* enable hot-plug polling */
  2253. drm_kms_helper_poll_enable(ddev);
  2254. return 0;
  2255. }
  2256. static const struct msm_kms_funcs kms_funcs = {
  2257. .hw_init = sde_kms_hw_init,
  2258. .postinit = sde_kms_postinit,
  2259. .irq_preinstall = sde_irq_preinstall,
  2260. .irq_postinstall = sde_irq_postinstall,
  2261. .irq_uninstall = sde_irq_uninstall,
  2262. .irq = sde_irq,
  2263. .preclose = sde_kms_preclose,
  2264. .lastclose = sde_kms_lastclose,
  2265. .prepare_fence = sde_kms_prepare_fence,
  2266. .prepare_commit = sde_kms_prepare_commit,
  2267. .commit = sde_kms_commit,
  2268. .complete_commit = sde_kms_complete_commit,
  2269. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2270. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  2271. .enable_vblank = sde_kms_enable_vblank,
  2272. .disable_vblank = sde_kms_disable_vblank,
  2273. .check_modified_format = sde_format_check_modified_format,
  2274. .atomic_check = sde_kms_atomic_check,
  2275. .get_format = sde_get_msm_format,
  2276. .round_pixclk = sde_kms_round_pixclk,
  2277. .pm_suspend = sde_kms_pm_suspend,
  2278. .pm_resume = sde_kms_pm_resume,
  2279. .destroy = sde_kms_destroy,
  2280. .cont_splash_config = sde_kms_cont_splash_config,
  2281. .register_events = _sde_kms_register_events,
  2282. .get_address_space = _sde_kms_get_address_space,
  2283. .get_address_space_device = _sde_kms_get_address_space_device,
  2284. .postopen = _sde_kms_post_open,
  2285. .check_for_splash = sde_kms_check_for_splash,
  2286. };
  2287. /* the caller api needs to turn on clock before calling it */
  2288. static inline void _sde_kms_core_hw_rev_init(struct sde_kms *sde_kms)
  2289. {
  2290. sde_kms->core_rev = readl_relaxed(sde_kms->mmio + 0x0);
  2291. }
  2292. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  2293. {
  2294. int i;
  2295. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  2296. if (!sde_kms->aspace[i])
  2297. continue;
  2298. msm_gem_address_space_put(sde_kms->aspace[i]);
  2299. sde_kms->aspace[i] = NULL;
  2300. }
  2301. return 0;
  2302. }
  2303. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  2304. {
  2305. struct msm_mmu *mmu;
  2306. int i, ret;
  2307. int early_map = 0;
  2308. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  2309. struct msm_gem_address_space *aspace;
  2310. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  2311. if (IS_ERR(mmu)) {
  2312. ret = PTR_ERR(mmu);
  2313. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  2314. i, ret);
  2315. continue;
  2316. }
  2317. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  2318. mmu, "sde");
  2319. if (IS_ERR(aspace)) {
  2320. ret = PTR_ERR(aspace);
  2321. goto fail;
  2322. }
  2323. sde_kms->aspace[i] = aspace;
  2324. aspace->domain_attached = true;
  2325. /* Mapping splash memory block */
  2326. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  2327. sde_kms->splash_data.num_splash_regions) {
  2328. ret = _sde_kms_map_all_splash_regions(sde_kms);
  2329. if (ret) {
  2330. SDE_ERROR("failed to map ret:%d\n", ret);
  2331. goto fail;
  2332. }
  2333. }
  2334. /*
  2335. * disable early-map which would have been enabled during
  2336. * bootup by smmu through the device-tree hint for cont-spash
  2337. */
  2338. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  2339. &early_map);
  2340. if (ret) {
  2341. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  2342. ret, early_map);
  2343. goto early_map_fail;
  2344. }
  2345. }
  2346. return 0;
  2347. early_map_fail:
  2348. _sde_kms_unmap_all_splash_regions(sde_kms);
  2349. fail:
  2350. mmu->funcs->destroy(mmu);
  2351. _sde_kms_mmu_destroy(sde_kms);
  2352. return ret;
  2353. }
  2354. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  2355. {
  2356. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  2357. return;
  2358. if (sde_kms->hw_mdp->ops.reset_ubwc)
  2359. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  2360. sde_kms->catalog);
  2361. sde_hw_sid_rotator_set(sde_kms->hw_sid);
  2362. }
  2363. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  2364. {
  2365. struct sde_vbif_set_qos_params qos_params;
  2366. struct sde_mdss_cfg *catalog;
  2367. if (!sde_kms->catalog)
  2368. return;
  2369. catalog = sde_kms->catalog;
  2370. memset(&qos_params, 0, sizeof(qos_params));
  2371. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  2372. qos_params.xin_id = catalog->dma_cfg.xin_id;
  2373. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  2374. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  2375. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  2376. }
  2377. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  2378. {
  2379. struct sde_kms *sde_kms = usr;
  2380. struct msm_kms *msm_kms;
  2381. msm_kms = &sde_kms->base;
  2382. if (!sde_kms)
  2383. return;
  2384. SDE_DEBUG("event_type:%d\n", event_type);
  2385. SDE_EVT32_VERBOSE(event_type);
  2386. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  2387. sde_irq_update(msm_kms, true);
  2388. sde_vbif_init_memtypes(sde_kms);
  2389. sde_kms_init_shared_hw(sde_kms);
  2390. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  2391. sde_kms->first_kickoff = true;
  2392. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  2393. sde_irq_update(msm_kms, false);
  2394. sde_kms->first_kickoff = false;
  2395. }
  2396. }
  2397. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  2398. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  2399. {
  2400. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2401. int rc = -EINVAL;
  2402. SDE_DEBUG("\n");
  2403. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2404. if (rc > 0)
  2405. rc = 0;
  2406. SDE_EVT32(rc, genpd->device_count);
  2407. return rc;
  2408. }
  2409. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  2410. {
  2411. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  2412. SDE_DEBUG("\n");
  2413. pm_runtime_put_sync(sde_kms->dev->dev);
  2414. SDE_EVT32(genpd->device_count);
  2415. return 0;
  2416. }
  2417. static int _sde_kms_get_splash_data(struct sde_splash_data *data)
  2418. {
  2419. int i = 0;
  2420. int ret = 0;
  2421. struct device_node *parent, *node, *node1;
  2422. struct resource r, r1;
  2423. const char *node_name = "cont_splash_region";
  2424. struct sde_splash_mem *mem;
  2425. bool share_splash_mem = false;
  2426. int num_displays, num_regions;
  2427. struct sde_splash_display *splash_display;
  2428. if (!data)
  2429. return -EINVAL;
  2430. memset(data, 0, sizeof(*data));
  2431. parent = of_find_node_by_path("/reserved-memory");
  2432. if (!parent) {
  2433. SDE_ERROR("failed to find reserved-memory node\n");
  2434. return -EINVAL;
  2435. }
  2436. node = of_find_node_by_name(parent, node_name);
  2437. if (!node) {
  2438. SDE_DEBUG("failed to find node %s\n", node_name);
  2439. return -EINVAL;
  2440. }
  2441. node1 = of_find_node_by_name(parent, "disp_rdump_region");
  2442. if (!node1)
  2443. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  2444. /**
  2445. * Support sharing a single splash memory for all the built in displays
  2446. * and also independent splash region per displays. Incase of
  2447. * independent splash region for each connected display, dtsi node of
  2448. * cont_splash_region should be collection of all memory regions
  2449. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  2450. */
  2451. num_displays = dsi_display_get_num_of_displays();
  2452. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  2453. data->num_splash_displays = num_displays;
  2454. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  2455. if (num_displays > num_regions) {
  2456. share_splash_mem = true;
  2457. pr_info(":%d displays share same splash buf\n", num_displays);
  2458. }
  2459. for (i = 0; i < num_displays; i++) {
  2460. splash_display = &data->splash_display[i];
  2461. if (!i || !share_splash_mem) {
  2462. if (of_address_to_resource(node, i, &r)) {
  2463. SDE_ERROR("invalid data for:%s\n", node_name);
  2464. return -EINVAL;
  2465. }
  2466. mem = &data->splash_mem[i];
  2467. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  2468. SDE_DEBUG("failed to find ramdump memory\n");
  2469. mem->ramdump_base = 0;
  2470. mem->ramdump_size = 0;
  2471. } else {
  2472. mem->ramdump_base = (unsigned long)r1.start;
  2473. mem->ramdump_size = (r1.end - r1.start) + 1;
  2474. }
  2475. mem->splash_buf_base = (unsigned long)r.start;
  2476. mem->splash_buf_size = (r.end - r.start) + 1;
  2477. mem->ref_cnt = 0;
  2478. splash_display->splash = mem;
  2479. data->num_splash_regions++;
  2480. } else {
  2481. data->splash_display[i].splash = &data->splash_mem[0];
  2482. }
  2483. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  2484. splash_display->splash->splash_buf_base,
  2485. splash_display->splash->splash_buf_size);
  2486. }
  2487. return ret;
  2488. }
  2489. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  2490. struct platform_device *platformdev)
  2491. {
  2492. int rc = -EINVAL;
  2493. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  2494. if (IS_ERR(sde_kms->mmio)) {
  2495. rc = PTR_ERR(sde_kms->mmio);
  2496. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  2497. sde_kms->mmio = NULL;
  2498. goto error;
  2499. }
  2500. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  2501. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  2502. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  2503. sde_kms->mmio_len);
  2504. if (rc)
  2505. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  2506. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  2507. "vbif_phys");
  2508. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  2509. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  2510. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  2511. sde_kms->vbif[VBIF_RT] = NULL;
  2512. goto error;
  2513. }
  2514. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  2515. "vbif_phys");
  2516. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  2517. sde_kms->vbif_len[VBIF_RT]);
  2518. if (rc)
  2519. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  2520. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  2521. "vbif_nrt_phys");
  2522. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  2523. sde_kms->vbif[VBIF_NRT] = NULL;
  2524. SDE_DEBUG("VBIF NRT is not defined");
  2525. } else {
  2526. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  2527. "vbif_nrt_phys");
  2528. rc = sde_dbg_reg_register_base("vbif_nrt",
  2529. sde_kms->vbif[VBIF_NRT],
  2530. sde_kms->vbif_len[VBIF_NRT]);
  2531. if (rc)
  2532. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  2533. rc);
  2534. }
  2535. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  2536. "regdma_phys");
  2537. if (IS_ERR(sde_kms->reg_dma)) {
  2538. sde_kms->reg_dma = NULL;
  2539. SDE_DEBUG("REG_DMA is not defined");
  2540. } else {
  2541. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  2542. "regdma_phys");
  2543. rc = sde_dbg_reg_register_base("reg_dma",
  2544. sde_kms->reg_dma,
  2545. sde_kms->reg_dma_len);
  2546. if (rc)
  2547. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  2548. rc);
  2549. }
  2550. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  2551. "sid_phys");
  2552. if (IS_ERR(sde_kms->sid)) {
  2553. rc = PTR_ERR(sde_kms->sid);
  2554. SDE_ERROR("sid register memory map failed: %d\n", rc);
  2555. sde_kms->sid = NULL;
  2556. goto error;
  2557. }
  2558. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  2559. rc = sde_dbg_reg_register_base("sid", sde_kms->sid, sde_kms->sid_len);
  2560. if (rc)
  2561. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  2562. error:
  2563. return rc;
  2564. }
  2565. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  2566. struct sde_kms *sde_kms)
  2567. {
  2568. int rc = 0;
  2569. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  2570. sde_kms->genpd.name = dev->unique;
  2571. sde_kms->genpd.power_off = sde_kms_pd_disable;
  2572. sde_kms->genpd.power_on = sde_kms_pd_enable;
  2573. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  2574. if (rc < 0) {
  2575. SDE_ERROR("failed to init genpd provider %s: %d\n",
  2576. sde_kms->genpd.name, rc);
  2577. return rc;
  2578. }
  2579. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  2580. &sde_kms->genpd);
  2581. if (rc < 0) {
  2582. SDE_ERROR("failed to add genpd provider %s: %d\n",
  2583. sde_kms->genpd.name, rc);
  2584. pm_genpd_remove(&sde_kms->genpd);
  2585. return rc;
  2586. }
  2587. sde_kms->genpd_init = true;
  2588. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  2589. }
  2590. return rc;
  2591. }
  2592. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  2593. struct drm_device *dev,
  2594. struct msm_drm_private *priv)
  2595. {
  2596. struct sde_rm *rm = NULL;
  2597. int i, rc = -EINVAL;
  2598. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2599. sde_power_data_bus_set_quota(&priv->phandle, i,
  2600. SDE_POWER_HANDLE_CONT_SPLASH_BUS_AB_QUOTA,
  2601. SDE_POWER_HANDLE_CONT_SPLASH_BUS_IB_QUOTA);
  2602. _sde_kms_core_hw_rev_init(sde_kms);
  2603. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  2604. sde_kms->catalog = sde_hw_catalog_init(dev, sde_kms->core_rev);
  2605. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  2606. rc = PTR_ERR(sde_kms->catalog);
  2607. if (!sde_kms->catalog)
  2608. rc = -EINVAL;
  2609. SDE_ERROR("catalog init failed: %d\n", rc);
  2610. sde_kms->catalog = NULL;
  2611. goto power_error;
  2612. }
  2613. /* initialize power domain if defined */
  2614. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  2615. if (rc) {
  2616. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  2617. goto genpd_err;
  2618. }
  2619. rc = _sde_kms_mmu_init(sde_kms);
  2620. if (rc) {
  2621. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  2622. goto power_error;
  2623. }
  2624. /* Initialize reg dma block which is a singleton */
  2625. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  2626. sde_kms->dev);
  2627. if (rc) {
  2628. SDE_ERROR("failed: reg dma init failed\n");
  2629. goto power_error;
  2630. }
  2631. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  2632. rm = &sde_kms->rm;
  2633. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  2634. sde_kms->dev);
  2635. if (rc) {
  2636. SDE_ERROR("rm init failed: %d\n", rc);
  2637. goto power_error;
  2638. }
  2639. sde_kms->rm_init = true;
  2640. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  2641. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  2642. rc = PTR_ERR(sde_kms->hw_intr);
  2643. SDE_ERROR("hw_intr init failed: %d\n", rc);
  2644. sde_kms->hw_intr = NULL;
  2645. goto hw_intr_init_err;
  2646. }
  2647. /*
  2648. * Attempt continuous splash handoff only if reserved
  2649. * splash memory is found & release resources on any error
  2650. * in finding display hw config in splash
  2651. */
  2652. if (sde_kms->splash_data.num_splash_regions &&
  2653. sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  2654. &sde_kms->splash_data,
  2655. sde_kms->catalog)) {
  2656. SDE_DEBUG("freeing continuous splash resources\n");
  2657. _sde_kms_unmap_all_splash_regions(sde_kms);
  2658. memset(&sde_kms->splash_data, 0x0,
  2659. sizeof(struct sde_splash_data));
  2660. }
  2661. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  2662. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  2663. rc = PTR_ERR(sde_kms->hw_mdp);
  2664. if (!sde_kms->hw_mdp)
  2665. rc = -EINVAL;
  2666. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  2667. sde_kms->hw_mdp = NULL;
  2668. goto power_error;
  2669. }
  2670. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  2671. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  2672. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  2673. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  2674. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  2675. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  2676. if (!sde_kms->hw_vbif[vbif_idx])
  2677. rc = -EINVAL;
  2678. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  2679. sde_kms->hw_vbif[vbif_idx] = NULL;
  2680. goto power_error;
  2681. }
  2682. }
  2683. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  2684. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  2685. sde_kms->mmio_len, sde_kms->catalog);
  2686. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  2687. rc = PTR_ERR(sde_kms->hw_uidle);
  2688. if (!sde_kms->hw_uidle)
  2689. rc = -EINVAL;
  2690. /* uidle is optional, so do not make it a fatal error */
  2691. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  2692. sde_kms->hw_uidle = NULL;
  2693. rc = 0;
  2694. }
  2695. } else {
  2696. sde_kms->hw_uidle = NULL;
  2697. }
  2698. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  2699. sde_kms->sid_len, sde_kms->catalog);
  2700. if (IS_ERR(sde_kms->hw_sid)) {
  2701. SDE_ERROR("failed to init sid %ld\n", PTR_ERR(sde_kms->hw_sid));
  2702. sde_kms->hw_sid = NULL;
  2703. goto power_error;
  2704. }
  2705. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  2706. &priv->phandle, "core_clk");
  2707. if (rc) {
  2708. SDE_ERROR("failed to init perf %d\n", rc);
  2709. goto perf_err;
  2710. }
  2711. /*
  2712. * _sde_kms_drm_obj_init should create the DRM related objects
  2713. * i.e. CRTCs, planes, encoders, connectors and so forth
  2714. */
  2715. rc = _sde_kms_drm_obj_init(sde_kms);
  2716. if (rc) {
  2717. SDE_ERROR("modeset init failed: %d\n", rc);
  2718. goto drm_obj_init_err;
  2719. }
  2720. return 0;
  2721. genpd_err:
  2722. drm_obj_init_err:
  2723. sde_core_perf_destroy(&sde_kms->perf);
  2724. hw_intr_init_err:
  2725. perf_err:
  2726. power_error:
  2727. return rc;
  2728. }
  2729. static int sde_kms_hw_init(struct msm_kms *kms)
  2730. {
  2731. struct sde_kms *sde_kms;
  2732. struct drm_device *dev;
  2733. struct msm_drm_private *priv;
  2734. struct platform_device *platformdev;
  2735. int i, rc = -EINVAL;
  2736. if (!kms) {
  2737. SDE_ERROR("invalid kms\n");
  2738. goto end;
  2739. }
  2740. sde_kms = to_sde_kms(kms);
  2741. dev = sde_kms->dev;
  2742. if (!dev || !dev->dev) {
  2743. SDE_ERROR("invalid device\n");
  2744. goto end;
  2745. }
  2746. platformdev = to_platform_device(dev->dev);
  2747. priv = dev->dev_private;
  2748. if (!priv) {
  2749. SDE_ERROR("invalid private data\n");
  2750. goto end;
  2751. }
  2752. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  2753. if (rc)
  2754. goto error;
  2755. rc = _sde_kms_get_splash_data(&sde_kms->splash_data);
  2756. if (rc)
  2757. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  2758. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  2759. if (rc < 0) {
  2760. SDE_ERROR("resource enable failed: %d\n", rc);
  2761. goto error;
  2762. }
  2763. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  2764. if (rc)
  2765. goto hw_init_err;
  2766. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  2767. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  2768. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  2769. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  2770. mutex_init(&sde_kms->secure_transition_lock);
  2771. atomic_set(&sde_kms->detach_sec_cb, 0);
  2772. atomic_set(&sde_kms->detach_all_cb, 0);
  2773. /*
  2774. * Support format modifiers for compression etc.
  2775. */
  2776. dev->mode_config.allow_fb_modifiers = true;
  2777. /*
  2778. * Handle (re)initializations during power enable
  2779. */
  2780. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  2781. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  2782. SDE_POWER_EVENT_POST_ENABLE |
  2783. SDE_POWER_EVENT_PRE_DISABLE,
  2784. sde_kms_handle_power_event, sde_kms, "kms");
  2785. if (sde_kms->splash_data.num_splash_displays) {
  2786. SDE_DEBUG("Skipping MDP Resources disable\n");
  2787. } else {
  2788. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  2789. sde_power_data_bus_set_quota(&priv->phandle, i,
  2790. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  2791. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  2792. pm_runtime_put_sync(sde_kms->dev->dev);
  2793. }
  2794. return 0;
  2795. hw_init_err:
  2796. pm_runtime_put_sync(sde_kms->dev->dev);
  2797. error:
  2798. _sde_kms_hw_destroy(sde_kms, platformdev);
  2799. end:
  2800. return rc;
  2801. }
  2802. struct msm_kms *sde_kms_init(struct drm_device *dev)
  2803. {
  2804. struct msm_drm_private *priv;
  2805. struct sde_kms *sde_kms;
  2806. if (!dev || !dev->dev_private) {
  2807. SDE_ERROR("drm device node invalid\n");
  2808. return ERR_PTR(-EINVAL);
  2809. }
  2810. priv = dev->dev_private;
  2811. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  2812. if (!sde_kms) {
  2813. SDE_ERROR("failed to allocate sde kms\n");
  2814. return ERR_PTR(-ENOMEM);
  2815. }
  2816. msm_kms_init(&sde_kms->base, &kms_funcs);
  2817. sde_kms->dev = dev;
  2818. return &sde_kms->base;
  2819. }
  2820. static int _sde_kms_register_events(struct msm_kms *kms,
  2821. struct drm_mode_object *obj, u32 event, bool en)
  2822. {
  2823. int ret = 0;
  2824. struct drm_crtc *crtc = NULL;
  2825. struct drm_connector *conn = NULL;
  2826. struct sde_kms *sde_kms = NULL;
  2827. if (!kms || !obj) {
  2828. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  2829. return -EINVAL;
  2830. }
  2831. sde_kms = to_sde_kms(kms);
  2832. switch (obj->type) {
  2833. case DRM_MODE_OBJECT_CRTC:
  2834. crtc = obj_to_crtc(obj);
  2835. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  2836. break;
  2837. case DRM_MODE_OBJECT_CONNECTOR:
  2838. conn = obj_to_connector(obj);
  2839. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  2840. en);
  2841. break;
  2842. }
  2843. return ret;
  2844. }
  2845. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  2846. {
  2847. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  2848. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  2849. }