dp_tx.c 129 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838
  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_htt.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_tx.h"
  22. #include "dp_tx_desc.h"
  23. #include "dp_peer.h"
  24. #include "dp_types.h"
  25. #include "hal_tx.h"
  26. #include "qdf_mem.h"
  27. #include "qdf_nbuf.h"
  28. #include "qdf_net_types.h"
  29. #include <wlan_cfg.h>
  30. #include "dp_ipa.h"
  31. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  32. #include "if_meta_hdr.h"
  33. #endif
  34. #include "enet.h"
  35. #include "dp_internal.h"
  36. #ifdef FEATURE_WDS
  37. #include "dp_txrx_wds.h"
  38. #endif
  39. #ifdef ATH_SUPPORT_IQUE
  40. #include "dp_txrx_me.h"
  41. #endif
  42. #include "dp_hist.h"
  43. /* TODO Add support in TSO */
  44. #define DP_DESC_NUM_FRAG(x) 0
  45. /* disable TQM_BYPASS */
  46. #define TQM_BYPASS_WAR 0
  47. /* invalid peer id for reinject*/
  48. #define DP_INVALID_PEER 0XFFFE
  49. /*mapping between hal encrypt type and cdp_sec_type*/
  50. #define MAX_CDP_SEC_TYPE 12
  51. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  52. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  53. HAL_TX_ENCRYPT_TYPE_WEP_128,
  54. HAL_TX_ENCRYPT_TYPE_WEP_104,
  55. HAL_TX_ENCRYPT_TYPE_WEP_40,
  56. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  57. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  58. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  59. HAL_TX_ENCRYPT_TYPE_WAPI,
  60. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  61. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  62. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  63. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  64. #ifdef QCA_TX_LIMIT_CHECK
  65. /**
  66. * dp_tx_limit_check - Check if allocated tx descriptors reached
  67. * soc max limit and pdev max limit
  68. * @vdev: DP vdev handle
  69. *
  70. * Return: true if allocated tx descriptors reached max configured value, else
  71. * false
  72. */
  73. static inline bool
  74. dp_tx_limit_check(struct dp_vdev *vdev)
  75. {
  76. struct dp_pdev *pdev = vdev->pdev;
  77. struct dp_soc *soc = pdev->soc;
  78. if (qdf_atomic_read(&soc->num_tx_outstanding) >=
  79. soc->num_tx_allowed) {
  80. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  81. "%s: queued packets are more than max tx, drop the frame",
  82. __func__);
  83. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  84. return true;
  85. }
  86. if (qdf_atomic_read(&pdev->num_tx_outstanding) >=
  87. pdev->num_tx_allowed) {
  88. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  89. "%s: queued packets are more than max tx, drop the frame",
  90. __func__);
  91. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  92. return true;
  93. }
  94. return false;
  95. }
  96. /**
  97. * dp_tx_exception_limit_check - Check if allocated tx exception descriptors
  98. * reached soc max limit
  99. * @vdev: DP vdev handle
  100. *
  101. * Return: true if allocated tx descriptors reached max configured value, else
  102. * false
  103. */
  104. static inline bool
  105. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  106. {
  107. struct dp_pdev *pdev = vdev->pdev;
  108. struct dp_soc *soc = pdev->soc;
  109. if (qdf_atomic_read(&soc->num_tx_exception) >=
  110. soc->num_msdu_exception_desc) {
  111. dp_info("exc packets are more than max drop the exc pkt");
  112. DP_STATS_INC(vdev, tx_i.dropped.exc_desc_na.num, 1);
  113. return true;
  114. }
  115. return false;
  116. }
  117. /**
  118. * dp_tx_outstanding_inc - Increment outstanding tx desc values on pdev and soc
  119. * @vdev: DP pdev handle
  120. *
  121. * Return: void
  122. */
  123. static inline void
  124. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  125. {
  126. struct dp_soc *soc = pdev->soc;
  127. qdf_atomic_inc(&pdev->num_tx_outstanding);
  128. qdf_atomic_inc(&soc->num_tx_outstanding);
  129. }
  130. /**
  131. * dp_tx_outstanding__dec - Decrement outstanding tx desc values on pdev and soc
  132. * @vdev: DP pdev handle
  133. *
  134. * Return: void
  135. */
  136. static inline void
  137. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  138. {
  139. struct dp_soc *soc = pdev->soc;
  140. qdf_atomic_dec(&pdev->num_tx_outstanding);
  141. qdf_atomic_dec(&soc->num_tx_outstanding);
  142. }
  143. #else //QCA_TX_LIMIT_CHECK
  144. static inline bool
  145. dp_tx_limit_check(struct dp_vdev *vdev)
  146. {
  147. return false;
  148. }
  149. static inline bool
  150. dp_tx_exception_limit_check(struct dp_vdev *vdev)
  151. {
  152. return false;
  153. }
  154. static inline void
  155. dp_tx_outstanding_inc(struct dp_pdev *pdev)
  156. {
  157. qdf_atomic_inc(&pdev->num_tx_outstanding);
  158. }
  159. static inline void
  160. dp_tx_outstanding_dec(struct dp_pdev *pdev)
  161. {
  162. qdf_atomic_dec(&pdev->num_tx_outstanding);
  163. }
  164. #endif //QCA_TX_LIMIT_CHECK
  165. #if defined(FEATURE_TSO)
  166. /**
  167. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  168. *
  169. * @soc - core txrx main context
  170. * @seg_desc - tso segment descriptor
  171. * @num_seg_desc - tso number segment descriptor
  172. */
  173. static void dp_tx_tso_unmap_segment(
  174. struct dp_soc *soc,
  175. struct qdf_tso_seg_elem_t *seg_desc,
  176. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  177. {
  178. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  179. if (qdf_unlikely(!seg_desc)) {
  180. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  181. __func__, __LINE__);
  182. qdf_assert(0);
  183. } else if (qdf_unlikely(!num_seg_desc)) {
  184. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  185. __func__, __LINE__);
  186. qdf_assert(0);
  187. } else {
  188. bool is_last_seg;
  189. /* no tso segment left to do dma unmap */
  190. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  191. return;
  192. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  193. true : false;
  194. qdf_nbuf_unmap_tso_segment(soc->osdev,
  195. seg_desc, is_last_seg);
  196. num_seg_desc->num_seg.tso_cmn_num_seg--;
  197. }
  198. }
  199. /**
  200. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  201. * back to the freelist
  202. *
  203. * @soc - soc device handle
  204. * @tx_desc - Tx software descriptor
  205. */
  206. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  207. struct dp_tx_desc_s *tx_desc)
  208. {
  209. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  210. if (qdf_unlikely(!tx_desc->tso_desc)) {
  211. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  212. "%s %d TSO desc is NULL!",
  213. __func__, __LINE__);
  214. qdf_assert(0);
  215. } else if (qdf_unlikely(!tx_desc->tso_num_desc)) {
  216. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  217. "%s %d TSO num desc is NULL!",
  218. __func__, __LINE__);
  219. qdf_assert(0);
  220. } else {
  221. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  222. (struct qdf_tso_num_seg_elem_t *)tx_desc->tso_num_desc;
  223. /* Add the tso num segment into the free list */
  224. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  225. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  226. tx_desc->tso_num_desc);
  227. tx_desc->tso_num_desc = NULL;
  228. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  229. }
  230. /* Add the tso segment into the free list*/
  231. dp_tx_tso_desc_free(soc,
  232. tx_desc->pool_id, tx_desc->tso_desc);
  233. tx_desc->tso_desc = NULL;
  234. }
  235. }
  236. #else
  237. static void dp_tx_tso_unmap_segment(
  238. struct dp_soc *soc,
  239. struct qdf_tso_seg_elem_t *seg_desc,
  240. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  241. {
  242. }
  243. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  244. struct dp_tx_desc_s *tx_desc)
  245. {
  246. }
  247. #endif
  248. /**
  249. * dp_tx_desc_release() - Release Tx Descriptor
  250. * @tx_desc : Tx Descriptor
  251. * @desc_pool_id: Descriptor Pool ID
  252. *
  253. * Deallocate all resources attached to Tx descriptor and free the Tx
  254. * descriptor.
  255. *
  256. * Return:
  257. */
  258. static void
  259. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  260. {
  261. struct dp_pdev *pdev = tx_desc->pdev;
  262. struct dp_soc *soc;
  263. uint8_t comp_status = 0;
  264. qdf_assert(pdev);
  265. soc = pdev->soc;
  266. dp_tx_outstanding_dec(pdev);
  267. if (tx_desc->frm_type == dp_tx_frm_tso)
  268. dp_tx_tso_desc_release(soc, tx_desc);
  269. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  270. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  271. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  272. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  273. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  274. qdf_atomic_dec(&soc->num_tx_exception);
  275. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  276. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  277. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  278. soc->hal_soc);
  279. else
  280. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  281. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  282. "Tx Completion Release desc %d status %d outstanding %d",
  283. tx_desc->id, comp_status,
  284. qdf_atomic_read(&pdev->num_tx_outstanding));
  285. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  286. return;
  287. }
  288. /**
  289. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  290. * @vdev: DP vdev Handle
  291. * @nbuf: skb
  292. * @msdu_info: msdu_info required to create HTT metadata
  293. *
  294. * Prepares and fills HTT metadata in the frame pre-header for special frames
  295. * that should be transmitted using varying transmit parameters.
  296. * There are 2 VDEV modes that currently needs this special metadata -
  297. * 1) Mesh Mode
  298. * 2) DSRC Mode
  299. *
  300. * Return: HTT metadata size
  301. *
  302. */
  303. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  304. struct dp_tx_msdu_info_s *msdu_info)
  305. {
  306. uint32_t *meta_data = msdu_info->meta_data;
  307. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  308. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  309. uint8_t htt_desc_size;
  310. /* Size rounded of multiple of 8 bytes */
  311. uint8_t htt_desc_size_aligned;
  312. uint8_t *hdr = NULL;
  313. /*
  314. * Metadata - HTT MSDU Extension header
  315. */
  316. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  317. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  318. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  319. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  320. meta_data[0])) {
  321. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  322. htt_desc_size_aligned)) {
  323. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  324. htt_desc_size_aligned);
  325. if (!nbuf) {
  326. /*
  327. * qdf_nbuf_realloc_headroom won't do skb_clone
  328. * as skb_realloc_headroom does. so, no free is
  329. * needed here.
  330. */
  331. DP_STATS_INC(vdev,
  332. tx_i.dropped.headroom_insufficient,
  333. 1);
  334. qdf_print(" %s[%d] skb_realloc_headroom failed",
  335. __func__, __LINE__);
  336. return 0;
  337. }
  338. }
  339. /* Fill and add HTT metaheader */
  340. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  341. if (!hdr) {
  342. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  343. "Error in filling HTT metadata");
  344. return 0;
  345. }
  346. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  347. } else if (vdev->opmode == wlan_op_mode_ocb) {
  348. /* Todo - Add support for DSRC */
  349. }
  350. return htt_desc_size_aligned;
  351. }
  352. /**
  353. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  354. * @tso_seg: TSO segment to process
  355. * @ext_desc: Pointer to MSDU extension descriptor
  356. *
  357. * Return: void
  358. */
  359. #if defined(FEATURE_TSO)
  360. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  361. void *ext_desc)
  362. {
  363. uint8_t num_frag;
  364. uint32_t tso_flags;
  365. /*
  366. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  367. * tcp_flag_mask
  368. *
  369. * Checksum enable flags are set in TCL descriptor and not in Extension
  370. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  371. */
  372. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  373. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  374. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  375. tso_seg->tso_flags.ip_len);
  376. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  377. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  378. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  379. uint32_t lo = 0;
  380. uint32_t hi = 0;
  381. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  382. (tso_seg->tso_frags[num_frag].length));
  383. qdf_dmaaddr_to_32s(
  384. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  385. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  386. tso_seg->tso_frags[num_frag].length);
  387. }
  388. return;
  389. }
  390. #else
  391. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  392. void *ext_desc)
  393. {
  394. return;
  395. }
  396. #endif
  397. #if defined(FEATURE_TSO)
  398. /**
  399. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  400. * allocated and free them
  401. *
  402. * @soc: soc handle
  403. * @free_seg: list of tso segments
  404. * @msdu_info: msdu descriptor
  405. *
  406. * Return - void
  407. */
  408. static void dp_tx_free_tso_seg_list(
  409. struct dp_soc *soc,
  410. struct qdf_tso_seg_elem_t *free_seg,
  411. struct dp_tx_msdu_info_s *msdu_info)
  412. {
  413. struct qdf_tso_seg_elem_t *next_seg;
  414. while (free_seg) {
  415. next_seg = free_seg->next;
  416. dp_tx_tso_desc_free(soc,
  417. msdu_info->tx_queue.desc_pool_id,
  418. free_seg);
  419. free_seg = next_seg;
  420. }
  421. }
  422. /**
  423. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  424. * allocated and free them
  425. *
  426. * @soc: soc handle
  427. * @free_num_seg: list of tso number segments
  428. * @msdu_info: msdu descriptor
  429. * Return - void
  430. */
  431. static void dp_tx_free_tso_num_seg_list(
  432. struct dp_soc *soc,
  433. struct qdf_tso_num_seg_elem_t *free_num_seg,
  434. struct dp_tx_msdu_info_s *msdu_info)
  435. {
  436. struct qdf_tso_num_seg_elem_t *next_num_seg;
  437. while (free_num_seg) {
  438. next_num_seg = free_num_seg->next;
  439. dp_tso_num_seg_free(soc,
  440. msdu_info->tx_queue.desc_pool_id,
  441. free_num_seg);
  442. free_num_seg = next_num_seg;
  443. }
  444. }
  445. /**
  446. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  447. * do dma unmap for each segment
  448. *
  449. * @soc: soc handle
  450. * @free_seg: list of tso segments
  451. * @num_seg_desc: tso number segment descriptor
  452. *
  453. * Return - void
  454. */
  455. static void dp_tx_unmap_tso_seg_list(
  456. struct dp_soc *soc,
  457. struct qdf_tso_seg_elem_t *free_seg,
  458. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  459. {
  460. struct qdf_tso_seg_elem_t *next_seg;
  461. if (qdf_unlikely(!num_seg_desc)) {
  462. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  463. return;
  464. }
  465. while (free_seg) {
  466. next_seg = free_seg->next;
  467. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  468. free_seg = next_seg;
  469. }
  470. }
  471. #ifdef FEATURE_TSO_STATS
  472. /**
  473. * dp_tso_get_stats_idx: Retrieve the tso packet id
  474. * @pdev - pdev handle
  475. *
  476. * Return: id
  477. */
  478. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  479. {
  480. uint32_t stats_idx;
  481. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  482. % CDP_MAX_TSO_PACKETS);
  483. return stats_idx;
  484. }
  485. #else
  486. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  487. {
  488. return 0;
  489. }
  490. #endif /* FEATURE_TSO_STATS */
  491. /**
  492. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  493. * free the tso segments descriptor and
  494. * tso num segments descriptor
  495. *
  496. * @soc: soc handle
  497. * @msdu_info: msdu descriptor
  498. * @tso_seg_unmap: flag to show if dma unmap is necessary
  499. *
  500. * Return - void
  501. */
  502. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  503. struct dp_tx_msdu_info_s *msdu_info,
  504. bool tso_seg_unmap)
  505. {
  506. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  507. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  508. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  509. tso_info->tso_num_seg_list;
  510. /* do dma unmap for each segment */
  511. if (tso_seg_unmap)
  512. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  513. /* free all tso number segment descriptor though looks only have 1 */
  514. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  515. /* free all tso segment descriptor */
  516. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  517. }
  518. /**
  519. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  520. * @vdev: virtual device handle
  521. * @msdu: network buffer
  522. * @msdu_info: meta data associated with the msdu
  523. *
  524. * Return: QDF_STATUS_SUCCESS success
  525. */
  526. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  527. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  528. {
  529. struct qdf_tso_seg_elem_t *tso_seg;
  530. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  531. struct dp_soc *soc = vdev->pdev->soc;
  532. struct dp_pdev *pdev = vdev->pdev;
  533. struct qdf_tso_info_t *tso_info;
  534. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  535. tso_info = &msdu_info->u.tso_info;
  536. tso_info->curr_seg = NULL;
  537. tso_info->tso_seg_list = NULL;
  538. tso_info->num_segs = num_seg;
  539. msdu_info->frm_type = dp_tx_frm_tso;
  540. tso_info->tso_num_seg_list = NULL;
  541. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  542. while (num_seg) {
  543. tso_seg = dp_tx_tso_desc_alloc(
  544. soc, msdu_info->tx_queue.desc_pool_id);
  545. if (tso_seg) {
  546. tso_seg->next = tso_info->tso_seg_list;
  547. tso_info->tso_seg_list = tso_seg;
  548. num_seg--;
  549. } else {
  550. dp_err_rl("Failed to alloc tso seg desc");
  551. DP_STATS_INC_PKT(vdev->pdev,
  552. tso_stats.tso_no_mem_dropped, 1,
  553. qdf_nbuf_len(msdu));
  554. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  555. return QDF_STATUS_E_NOMEM;
  556. }
  557. }
  558. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  559. tso_num_seg = dp_tso_num_seg_alloc(soc,
  560. msdu_info->tx_queue.desc_pool_id);
  561. if (tso_num_seg) {
  562. tso_num_seg->next = tso_info->tso_num_seg_list;
  563. tso_info->tso_num_seg_list = tso_num_seg;
  564. } else {
  565. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  566. __func__);
  567. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  568. return QDF_STATUS_E_NOMEM;
  569. }
  570. msdu_info->num_seg =
  571. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  572. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  573. msdu_info->num_seg);
  574. if (!(msdu_info->num_seg)) {
  575. /*
  576. * Free allocated TSO seg desc and number seg desc,
  577. * do unmap for segments if dma map has done.
  578. */
  579. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  580. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  581. return QDF_STATUS_E_INVAL;
  582. }
  583. tso_info->curr_seg = tso_info->tso_seg_list;
  584. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  585. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  586. msdu, msdu_info->num_seg);
  587. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  588. tso_info->msdu_stats_idx);
  589. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  590. return QDF_STATUS_SUCCESS;
  591. }
  592. #else
  593. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  594. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  595. {
  596. return QDF_STATUS_E_NOMEM;
  597. }
  598. #endif
  599. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  600. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  601. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  602. /**
  603. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  604. * @vdev: DP Vdev handle
  605. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  606. * @desc_pool_id: Descriptor Pool ID
  607. *
  608. * Return:
  609. */
  610. static
  611. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  612. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  613. {
  614. uint8_t i;
  615. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  616. struct dp_tx_seg_info_s *seg_info;
  617. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  618. struct dp_soc *soc = vdev->pdev->soc;
  619. /* Allocate an extension descriptor */
  620. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  621. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  622. if (!msdu_ext_desc) {
  623. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  624. return NULL;
  625. }
  626. if (msdu_info->exception_fw &&
  627. qdf_unlikely(vdev->mesh_vdev)) {
  628. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  629. &msdu_info->meta_data[0],
  630. sizeof(struct htt_tx_msdu_desc_ext2_t));
  631. qdf_atomic_inc(&soc->num_tx_exception);
  632. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  633. }
  634. switch (msdu_info->frm_type) {
  635. case dp_tx_frm_sg:
  636. case dp_tx_frm_me:
  637. case dp_tx_frm_raw:
  638. seg_info = msdu_info->u.sg_info.curr_seg;
  639. /* Update the buffer pointers in MSDU Extension Descriptor */
  640. for (i = 0; i < seg_info->frag_cnt; i++) {
  641. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  642. seg_info->frags[i].paddr_lo,
  643. seg_info->frags[i].paddr_hi,
  644. seg_info->frags[i].len);
  645. }
  646. break;
  647. case dp_tx_frm_tso:
  648. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  649. &cached_ext_desc[0]);
  650. break;
  651. default:
  652. break;
  653. }
  654. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  655. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  656. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  657. msdu_ext_desc->vaddr);
  658. return msdu_ext_desc;
  659. }
  660. /**
  661. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  662. *
  663. * @skb: skb to be traced
  664. * @msdu_id: msdu_id of the packet
  665. * @vdev_id: vdev_id of the packet
  666. *
  667. * Return: None
  668. */
  669. #ifdef DP_DISABLE_TX_PKT_TRACE
  670. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  671. uint8_t vdev_id)
  672. {
  673. }
  674. #else
  675. static void dp_tx_trace_pkt(qdf_nbuf_t skb, uint16_t msdu_id,
  676. uint8_t vdev_id)
  677. {
  678. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  679. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  680. DPTRACE(qdf_dp_trace_ptr(skb,
  681. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  682. QDF_TRACE_DEFAULT_PDEV_ID,
  683. qdf_nbuf_data_addr(skb),
  684. sizeof(qdf_nbuf_data(skb)),
  685. msdu_id, vdev_id));
  686. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  687. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  688. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  689. msdu_id, QDF_TX));
  690. }
  691. #endif
  692. /**
  693. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  694. * @vdev: DP vdev handle
  695. * @nbuf: skb
  696. * @desc_pool_id: Descriptor pool ID
  697. * @meta_data: Metadata to the fw
  698. * @tx_exc_metadata: Handle that holds exception path metadata
  699. * Allocate and prepare Tx descriptor with msdu information.
  700. *
  701. * Return: Pointer to Tx Descriptor on success,
  702. * NULL on failure
  703. */
  704. static
  705. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  706. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  707. struct dp_tx_msdu_info_s *msdu_info,
  708. struct cdp_tx_exception_metadata *tx_exc_metadata)
  709. {
  710. uint8_t align_pad;
  711. uint8_t is_exception = 0;
  712. uint8_t htt_hdr_size;
  713. struct dp_tx_desc_s *tx_desc;
  714. struct dp_pdev *pdev = vdev->pdev;
  715. struct dp_soc *soc = pdev->soc;
  716. if (dp_tx_limit_check(vdev))
  717. return NULL;
  718. /* Allocate software Tx descriptor */
  719. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  720. if (qdf_unlikely(!tx_desc)) {
  721. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  722. return NULL;
  723. }
  724. dp_tx_outstanding_inc(pdev);
  725. /* Initialize the SW tx descriptor */
  726. tx_desc->nbuf = nbuf;
  727. tx_desc->frm_type = dp_tx_frm_std;
  728. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  729. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  730. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  731. tx_desc->vdev = vdev;
  732. tx_desc->pdev = pdev;
  733. tx_desc->msdu_ext_desc = NULL;
  734. tx_desc->pkt_offset = 0;
  735. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  736. if (qdf_unlikely(vdev->multipass_en)) {
  737. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  738. goto failure;
  739. }
  740. /*
  741. * For special modes (vdev_type == ocb or mesh), data frames should be
  742. * transmitted using varying transmit parameters (tx spec) which include
  743. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  744. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  745. * These frames are sent as exception packets to firmware.
  746. *
  747. * HW requirement is that metadata should always point to a
  748. * 8-byte aligned address. So we add alignment pad to start of buffer.
  749. * HTT Metadata should be ensured to be multiple of 8-bytes,
  750. * to get 8-byte aligned start address along with align_pad added
  751. *
  752. * |-----------------------------|
  753. * | |
  754. * |-----------------------------| <-----Buffer Pointer Address given
  755. * | | ^ in HW descriptor (aligned)
  756. * | HTT Metadata | |
  757. * | | |
  758. * | | | Packet Offset given in descriptor
  759. * | | |
  760. * |-----------------------------| |
  761. * | Alignment Pad | v
  762. * |-----------------------------| <----- Actual buffer start address
  763. * | SKB Data | (Unaligned)
  764. * | |
  765. * | |
  766. * | |
  767. * | |
  768. * | |
  769. * |-----------------------------|
  770. */
  771. if (qdf_unlikely((msdu_info->exception_fw)) ||
  772. (vdev->opmode == wlan_op_mode_ocb) ||
  773. (tx_exc_metadata &&
  774. tx_exc_metadata->is_tx_sniffer)) {
  775. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  776. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  777. DP_STATS_INC(vdev,
  778. tx_i.dropped.headroom_insufficient, 1);
  779. goto failure;
  780. }
  781. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  782. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  783. "qdf_nbuf_push_head failed");
  784. goto failure;
  785. }
  786. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  787. msdu_info);
  788. if (htt_hdr_size == 0)
  789. goto failure;
  790. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  791. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  792. is_exception = 1;
  793. }
  794. #if !TQM_BYPASS_WAR
  795. if (is_exception || tx_exc_metadata)
  796. #endif
  797. {
  798. /* Temporary WAR due to TQM VP issues */
  799. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  800. qdf_atomic_inc(&soc->num_tx_exception);
  801. }
  802. return tx_desc;
  803. failure:
  804. dp_tx_desc_release(tx_desc, desc_pool_id);
  805. return NULL;
  806. }
  807. /**
  808. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  809. * @vdev: DP vdev handle
  810. * @nbuf: skb
  811. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  812. * @desc_pool_id : Descriptor Pool ID
  813. *
  814. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  815. * information. For frames wth fragments, allocate and prepare
  816. * an MSDU extension descriptor
  817. *
  818. * Return: Pointer to Tx Descriptor on success,
  819. * NULL on failure
  820. */
  821. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  822. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  823. uint8_t desc_pool_id)
  824. {
  825. struct dp_tx_desc_s *tx_desc;
  826. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  827. struct dp_pdev *pdev = vdev->pdev;
  828. struct dp_soc *soc = pdev->soc;
  829. if (dp_tx_limit_check(vdev))
  830. return NULL;
  831. /* Allocate software Tx descriptor */
  832. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  833. if (!tx_desc) {
  834. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  835. return NULL;
  836. }
  837. dp_tx_outstanding_inc(pdev);
  838. /* Initialize the SW tx descriptor */
  839. tx_desc->nbuf = nbuf;
  840. tx_desc->frm_type = msdu_info->frm_type;
  841. tx_desc->tx_encap_type = vdev->tx_encap_type;
  842. tx_desc->vdev = vdev;
  843. tx_desc->pdev = pdev;
  844. tx_desc->pkt_offset = 0;
  845. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  846. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  847. dp_tx_trace_pkt(nbuf, tx_desc->id, vdev->vdev_id);
  848. /* Handle scattered frames - TSO/SG/ME */
  849. /* Allocate and prepare an extension descriptor for scattered frames */
  850. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  851. if (!msdu_ext_desc) {
  852. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  853. "%s Tx Extension Descriptor Alloc Fail",
  854. __func__);
  855. goto failure;
  856. }
  857. #if TQM_BYPASS_WAR
  858. /* Temporary WAR due to TQM VP issues */
  859. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  860. qdf_atomic_inc(&soc->num_tx_exception);
  861. #endif
  862. if (qdf_unlikely(msdu_info->exception_fw))
  863. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  864. tx_desc->msdu_ext_desc = msdu_ext_desc;
  865. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  866. return tx_desc;
  867. failure:
  868. dp_tx_desc_release(tx_desc, desc_pool_id);
  869. return NULL;
  870. }
  871. /**
  872. * dp_tx_prepare_raw() - Prepare RAW packet TX
  873. * @vdev: DP vdev handle
  874. * @nbuf: buffer pointer
  875. * @seg_info: Pointer to Segment info Descriptor to be prepared
  876. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  877. * descriptor
  878. *
  879. * Return:
  880. */
  881. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  882. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  883. {
  884. qdf_nbuf_t curr_nbuf = NULL;
  885. uint16_t total_len = 0;
  886. qdf_dma_addr_t paddr;
  887. int32_t i;
  888. int32_t mapped_buf_num = 0;
  889. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  890. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  891. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  892. /* Continue only if frames are of DATA type */
  893. if (!DP_FRAME_IS_DATA(qos_wh)) {
  894. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  895. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  896. "Pkt. recd is of not data type");
  897. goto error;
  898. }
  899. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  900. if (vdev->raw_mode_war &&
  901. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  902. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  903. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  904. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  905. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  906. if (QDF_STATUS_SUCCESS !=
  907. qdf_nbuf_map_nbytes_single(vdev->osdev,
  908. curr_nbuf,
  909. QDF_DMA_TO_DEVICE,
  910. curr_nbuf->len)) {
  911. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  912. "%s dma map error ", __func__);
  913. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  914. mapped_buf_num = i;
  915. goto error;
  916. }
  917. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  918. seg_info->frags[i].paddr_lo = paddr;
  919. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  920. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  921. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  922. total_len += qdf_nbuf_len(curr_nbuf);
  923. }
  924. seg_info->frag_cnt = i;
  925. seg_info->total_len = total_len;
  926. seg_info->next = NULL;
  927. sg_info->curr_seg = seg_info;
  928. msdu_info->frm_type = dp_tx_frm_raw;
  929. msdu_info->num_seg = 1;
  930. return nbuf;
  931. error:
  932. i = 0;
  933. while (nbuf) {
  934. curr_nbuf = nbuf;
  935. if (i < mapped_buf_num) {
  936. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  937. QDF_DMA_TO_DEVICE,
  938. curr_nbuf->len);
  939. i++;
  940. }
  941. nbuf = qdf_nbuf_next(nbuf);
  942. qdf_nbuf_free(curr_nbuf);
  943. }
  944. return NULL;
  945. }
  946. /**
  947. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  948. * @soc: DP soc handle
  949. * @nbuf: Buffer pointer
  950. *
  951. * unmap the chain of nbufs that belong to this RAW frame.
  952. *
  953. * Return: None
  954. */
  955. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  956. qdf_nbuf_t nbuf)
  957. {
  958. qdf_nbuf_t cur_nbuf = nbuf;
  959. do {
  960. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  961. QDF_DMA_TO_DEVICE,
  962. cur_nbuf->len);
  963. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  964. } while (cur_nbuf);
  965. }
  966. #ifdef VDEV_PEER_PROTOCOL_COUNT
  967. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, nbuf) \
  968. { \
  969. qdf_nbuf_t nbuf_local; \
  970. struct dp_vdev *vdev_local = vdev_hdl; \
  971. do { \
  972. if (qdf_likely(!((vdev_local)->peer_protocol_count_track))) \
  973. break; \
  974. nbuf_local = nbuf; \
  975. if (qdf_unlikely(((vdev_local)->tx_encap_type) == \
  976. htt_cmn_pkt_type_raw)) \
  977. break; \
  978. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local)))) \
  979. break; \
  980. else if (qdf_nbuf_is_tso((nbuf_local))) \
  981. break; \
  982. dp_vdev_peer_stats_update_protocol_cnt((vdev_local), \
  983. (nbuf_local), \
  984. NULL, 1, 0); \
  985. } while (0); \
  986. }
  987. #else
  988. #define dp_vdev_peer_stats_update_protocol_cnt_tx(vdev_hdl, skb)
  989. #endif
  990. /**
  991. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  992. * @soc: DP Soc Handle
  993. * @vdev: DP vdev handle
  994. * @tx_desc: Tx Descriptor Handle
  995. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  996. * @fw_metadata: Metadata to send to Target Firmware along with frame
  997. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  998. * @tx_exc_metadata: Handle that holds exception path meta data
  999. *
  1000. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  1001. * from software Tx descriptor
  1002. *
  1003. * Return: QDF_STATUS_SUCCESS: success
  1004. * QDF_STATUS_E_RESOURCES: Error return
  1005. */
  1006. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  1007. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  1008. uint16_t fw_metadata, uint8_t ring_id,
  1009. struct cdp_tx_exception_metadata
  1010. *tx_exc_metadata)
  1011. {
  1012. uint8_t type;
  1013. void *hal_tx_desc;
  1014. uint32_t *hal_tx_desc_cached;
  1015. /*
  1016. * Setting it initialization statically here to avoid
  1017. * a memset call jump with qdf_mem_set call
  1018. */
  1019. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES] = { 0 };
  1020. enum cdp_sec_type sec_type = ((tx_exc_metadata &&
  1021. tx_exc_metadata->sec_type != CDP_INVALID_SEC_TYPE) ?
  1022. tx_exc_metadata->sec_type : vdev->sec_type);
  1023. /* Return Buffer Manager ID */
  1024. uint8_t bm_id = dp_tx_get_rbm_id(soc, ring_id);
  1025. hal_ring_handle_t hal_ring_hdl = NULL;
  1026. QDF_STATUS status = QDF_STATUS_E_RESOURCES;
  1027. if (!dp_tx_is_desc_id_valid(soc, tx_desc->id)) {
  1028. dp_err_rl("Invalid tx desc id:%d", tx_desc->id);
  1029. return QDF_STATUS_E_RESOURCES;
  1030. }
  1031. hal_tx_desc_cached = (void *) cached_desc;
  1032. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  1033. type = HAL_TX_BUF_TYPE_EXT_DESC;
  1034. tx_desc->dma_addr = tx_desc->msdu_ext_desc->paddr;
  1035. if (tx_desc->msdu_ext_desc->flags &
  1036. DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1037. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1038. else
  1039. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1040. } else {
  1041. tx_desc->length = qdf_nbuf_len(tx_desc->nbuf) -
  1042. tx_desc->pkt_offset;
  1043. type = HAL_TX_BUF_TYPE_BUFFER;
  1044. tx_desc->dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  1045. }
  1046. qdf_assert_always(tx_desc->dma_addr);
  1047. hal_tx_desc_set_buf_addr(soc->hal_soc, hal_tx_desc_cached,
  1048. tx_desc->dma_addr, bm_id, tx_desc->id,
  1049. type);
  1050. hal_tx_desc_set_lmac_id(soc->hal_soc, hal_tx_desc_cached,
  1051. vdev->lmac_id);
  1052. hal_tx_desc_set_search_type(soc->hal_soc, hal_tx_desc_cached,
  1053. vdev->search_type);
  1054. hal_tx_desc_set_search_index(soc->hal_soc, hal_tx_desc_cached,
  1055. vdev->bss_ast_idx);
  1056. hal_tx_desc_set_dscp_tid_table_id(soc->hal_soc, hal_tx_desc_cached,
  1057. vdev->dscp_tid_map_id);
  1058. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  1059. sec_type_map[sec_type]);
  1060. hal_tx_desc_set_cache_set_num(soc->hal_soc, hal_tx_desc_cached,
  1061. (vdev->bss_ast_hash & 0xF));
  1062. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  1063. hal_tx_desc_set_buf_length(hal_tx_desc_cached, tx_desc->length);
  1064. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  1065. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  1066. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  1067. vdev->hal_desc_addr_search_flags);
  1068. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  1069. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  1070. /* verify checksum offload configuration*/
  1071. if (vdev->csum_enabled &&
  1072. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  1073. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  1074. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  1075. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  1076. }
  1077. if (tid != HTT_TX_EXT_TID_INVALID)
  1078. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  1079. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  1080. hal_tx_desc_set_mesh_en(soc->hal_soc, hal_tx_desc_cached, 1);
  1081. if (qdf_unlikely(vdev->pdev->delay_stats_flag) ||
  1082. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  1083. soc->wlan_cfg_ctx)))
  1084. tx_desc->timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  1085. dp_verbose_debug("length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  1086. tx_desc->length, type, (uint64_t)tx_desc->dma_addr,
  1087. tx_desc->pkt_offset, tx_desc->id);
  1088. hal_ring_hdl = dp_tx_get_hal_ring_hdl(soc, ring_id);
  1089. if (qdf_unlikely(dp_tx_hal_ring_access_start(soc, hal_ring_hdl))) {
  1090. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1091. "%s %d : HAL RING Access Failed -- %pK",
  1092. __func__, __LINE__, hal_ring_hdl);
  1093. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1094. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1095. return status;
  1096. }
  1097. /* Sync cached descriptor with HW */
  1098. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_ring_hdl);
  1099. if (qdf_unlikely(!hal_tx_desc)) {
  1100. dp_verbose_debug("TCL ring full ring_id:%d", ring_id);
  1101. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  1102. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  1103. goto ring_access_fail;
  1104. }
  1105. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  1106. dp_vdev_peer_stats_update_protocol_cnt_tx(vdev, tx_desc->nbuf);
  1107. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  1108. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, tx_desc->length);
  1109. status = QDF_STATUS_SUCCESS;
  1110. ring_access_fail:
  1111. if (hif_pm_runtime_get(soc->hif_handle,
  1112. RTPM_ID_DW_TX_HW_ENQUEUE) == 0) {
  1113. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1114. hif_pm_runtime_put(soc->hif_handle,
  1115. RTPM_ID_DW_TX_HW_ENQUEUE);
  1116. } else {
  1117. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1118. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1119. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1120. }
  1121. return status;
  1122. }
  1123. /**
  1124. * dp_cce_classify() - Classify the frame based on CCE rules
  1125. * @vdev: DP vdev handle
  1126. * @nbuf: skb
  1127. *
  1128. * Classify frames based on CCE rules
  1129. * Return: bool( true if classified,
  1130. * else false)
  1131. */
  1132. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  1133. {
  1134. qdf_ether_header_t *eh = NULL;
  1135. uint16_t ether_type;
  1136. qdf_llc_t *llcHdr;
  1137. qdf_nbuf_t nbuf_clone = NULL;
  1138. qdf_dot3_qosframe_t *qos_wh = NULL;
  1139. /* for mesh packets don't do any classification */
  1140. if (qdf_unlikely(vdev->mesh_vdev))
  1141. return false;
  1142. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1143. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1144. ether_type = eh->ether_type;
  1145. llcHdr = (qdf_llc_t *)(nbuf->data +
  1146. sizeof(qdf_ether_header_t));
  1147. } else {
  1148. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1149. /* For encrypted packets don't do any classification */
  1150. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  1151. return false;
  1152. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  1153. if (qdf_unlikely(
  1154. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  1155. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  1156. ether_type = *(uint16_t *)(nbuf->data
  1157. + QDF_IEEE80211_4ADDR_HDR_LEN
  1158. + sizeof(qdf_llc_t)
  1159. - sizeof(ether_type));
  1160. llcHdr = (qdf_llc_t *)(nbuf->data +
  1161. QDF_IEEE80211_4ADDR_HDR_LEN);
  1162. } else {
  1163. ether_type = *(uint16_t *)(nbuf->data
  1164. + QDF_IEEE80211_3ADDR_HDR_LEN
  1165. + sizeof(qdf_llc_t)
  1166. - sizeof(ether_type));
  1167. llcHdr = (qdf_llc_t *)(nbuf->data +
  1168. QDF_IEEE80211_3ADDR_HDR_LEN);
  1169. }
  1170. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  1171. && (ether_type ==
  1172. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  1173. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  1174. return true;
  1175. }
  1176. }
  1177. return false;
  1178. }
  1179. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  1180. ether_type = *(uint16_t *)(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1181. sizeof(*llcHdr));
  1182. nbuf_clone = qdf_nbuf_clone(nbuf);
  1183. if (qdf_unlikely(nbuf_clone)) {
  1184. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  1185. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1186. qdf_nbuf_pull_head(nbuf_clone,
  1187. sizeof(qdf_net_vlanhdr_t));
  1188. }
  1189. }
  1190. } else {
  1191. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1192. nbuf_clone = qdf_nbuf_clone(nbuf);
  1193. if (qdf_unlikely(nbuf_clone)) {
  1194. qdf_nbuf_pull_head(nbuf_clone,
  1195. sizeof(qdf_net_vlanhdr_t));
  1196. }
  1197. }
  1198. }
  1199. if (qdf_unlikely(nbuf_clone))
  1200. nbuf = nbuf_clone;
  1201. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  1202. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  1203. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  1204. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  1205. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  1206. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  1207. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  1208. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  1209. if (qdf_unlikely(nbuf_clone))
  1210. qdf_nbuf_free(nbuf_clone);
  1211. return true;
  1212. }
  1213. if (qdf_unlikely(nbuf_clone))
  1214. qdf_nbuf_free(nbuf_clone);
  1215. return false;
  1216. }
  1217. /**
  1218. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1219. * @vdev: DP vdev handle
  1220. * @nbuf: skb
  1221. *
  1222. * Extract the DSCP or PCP information from frame and map into TID value.
  1223. *
  1224. * Return: void
  1225. */
  1226. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1227. struct dp_tx_msdu_info_s *msdu_info)
  1228. {
  1229. uint8_t tos = 0, dscp_tid_override = 0;
  1230. uint8_t *hdr_ptr, *L3datap;
  1231. uint8_t is_mcast = 0;
  1232. qdf_ether_header_t *eh = NULL;
  1233. qdf_ethervlan_header_t *evh = NULL;
  1234. uint16_t ether_type;
  1235. qdf_llc_t *llcHdr;
  1236. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1237. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1238. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1239. eh = (qdf_ether_header_t *)nbuf->data;
  1240. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1241. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1242. } else {
  1243. qdf_dot3_qosframe_t *qos_wh =
  1244. (qdf_dot3_qosframe_t *) nbuf->data;
  1245. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1246. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1247. return;
  1248. }
  1249. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1250. ether_type = eh->ether_type;
  1251. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1252. /*
  1253. * Check if packet is dot3 or eth2 type.
  1254. */
  1255. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1256. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1257. sizeof(*llcHdr));
  1258. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1259. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1260. sizeof(*llcHdr);
  1261. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1262. + sizeof(*llcHdr) +
  1263. sizeof(qdf_net_vlanhdr_t));
  1264. } else {
  1265. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1266. sizeof(*llcHdr);
  1267. }
  1268. } else {
  1269. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1270. evh = (qdf_ethervlan_header_t *) eh;
  1271. ether_type = evh->ether_type;
  1272. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1273. }
  1274. }
  1275. /*
  1276. * Find priority from IP TOS DSCP field
  1277. */
  1278. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1279. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1280. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1281. /* Only for unicast frames */
  1282. if (!is_mcast) {
  1283. /* send it on VO queue */
  1284. msdu_info->tid = DP_VO_TID;
  1285. }
  1286. } else {
  1287. /*
  1288. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1289. * from TOS byte.
  1290. */
  1291. tos = ip->ip_tos;
  1292. dscp_tid_override = 1;
  1293. }
  1294. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1295. /* TODO
  1296. * use flowlabel
  1297. *igmpmld cases to be handled in phase 2
  1298. */
  1299. unsigned long ver_pri_flowlabel;
  1300. unsigned long pri;
  1301. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1302. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1303. DP_IPV6_PRIORITY_SHIFT;
  1304. tos = pri;
  1305. dscp_tid_override = 1;
  1306. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1307. msdu_info->tid = DP_VO_TID;
  1308. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1309. /* Only for unicast frames */
  1310. if (!is_mcast) {
  1311. /* send ucast arp on VO queue */
  1312. msdu_info->tid = DP_VO_TID;
  1313. }
  1314. }
  1315. /*
  1316. * Assign all MCAST packets to BE
  1317. */
  1318. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1319. if (is_mcast) {
  1320. tos = 0;
  1321. dscp_tid_override = 1;
  1322. }
  1323. }
  1324. if (dscp_tid_override == 1) {
  1325. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1326. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1327. }
  1328. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1329. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1330. return;
  1331. }
  1332. /**
  1333. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1334. * @vdev: DP vdev handle
  1335. * @nbuf: skb
  1336. *
  1337. * Software based TID classification is required when more than 2 DSCP-TID
  1338. * mapping tables are needed.
  1339. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1340. *
  1341. * Return: void
  1342. */
  1343. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1344. struct dp_tx_msdu_info_s *msdu_info)
  1345. {
  1346. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1347. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1348. if (pdev->soc && vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map)
  1349. return;
  1350. /* for mesh packets don't do any classification */
  1351. if (qdf_unlikely(vdev->mesh_vdev))
  1352. return;
  1353. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1354. }
  1355. #ifdef FEATURE_WLAN_TDLS
  1356. /**
  1357. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1358. * @tx_desc: TX descriptor
  1359. *
  1360. * Return: None
  1361. */
  1362. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1363. {
  1364. if (tx_desc->vdev) {
  1365. if (tx_desc->vdev->is_tdls_frame) {
  1366. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1367. tx_desc->vdev->is_tdls_frame = false;
  1368. }
  1369. }
  1370. }
  1371. /**
  1372. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1373. * @soc: dp_soc handle
  1374. * @tx_desc: TX descriptor
  1375. * @vdev: datapath vdev handle
  1376. *
  1377. * Return: None
  1378. */
  1379. static void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1380. struct dp_tx_desc_s *tx_desc,
  1381. struct dp_vdev *vdev)
  1382. {
  1383. struct hal_tx_completion_status ts = {0};
  1384. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1385. if (qdf_unlikely(!vdev)) {
  1386. dp_err_rl("vdev is null!");
  1387. goto error;
  1388. }
  1389. hal_tx_comp_get_status(&tx_desc->comp, &ts, vdev->pdev->soc->hal_soc);
  1390. if (vdev->tx_non_std_data_callback.func) {
  1391. qdf_nbuf_set_next(nbuf, NULL);
  1392. vdev->tx_non_std_data_callback.func(
  1393. vdev->tx_non_std_data_callback.ctxt,
  1394. nbuf, ts.status);
  1395. return;
  1396. } else {
  1397. dp_err_rl("callback func is null");
  1398. }
  1399. error:
  1400. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1401. qdf_nbuf_free(nbuf);
  1402. }
  1403. /**
  1404. * dp_tx_msdu_single_map() - do nbuf map
  1405. * @vdev: DP vdev handle
  1406. * @tx_desc: DP TX descriptor pointer
  1407. * @nbuf: skb pointer
  1408. *
  1409. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1410. * operation done in other component.
  1411. *
  1412. * Return: QDF_STATUS
  1413. */
  1414. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1415. struct dp_tx_desc_s *tx_desc,
  1416. qdf_nbuf_t nbuf)
  1417. {
  1418. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1419. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1420. nbuf,
  1421. QDF_DMA_TO_DEVICE,
  1422. nbuf->len);
  1423. else
  1424. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1425. QDF_DMA_TO_DEVICE);
  1426. }
  1427. #else
  1428. static inline void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1429. {
  1430. }
  1431. static inline void dp_non_std_tx_comp_free_buff(struct dp_soc *soc,
  1432. struct dp_tx_desc_s *tx_desc,
  1433. struct dp_vdev *vdev)
  1434. {
  1435. }
  1436. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1437. struct dp_tx_desc_s *tx_desc,
  1438. qdf_nbuf_t nbuf)
  1439. {
  1440. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1441. nbuf,
  1442. QDF_DMA_TO_DEVICE,
  1443. nbuf->len);
  1444. }
  1445. #endif
  1446. /**
  1447. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1448. * @vdev: DP vdev handle
  1449. * @nbuf: skb
  1450. *
  1451. * Return: 1 if frame needs to be dropped else 0
  1452. */
  1453. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1454. {
  1455. struct dp_pdev *pdev = NULL;
  1456. struct dp_ast_entry *src_ast_entry = NULL;
  1457. struct dp_ast_entry *dst_ast_entry = NULL;
  1458. struct dp_soc *soc = NULL;
  1459. qdf_assert(vdev);
  1460. pdev = vdev->pdev;
  1461. qdf_assert(pdev);
  1462. soc = pdev->soc;
  1463. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1464. (soc, dstmac, vdev->pdev->pdev_id);
  1465. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1466. (soc, srcmac, vdev->pdev->pdev_id);
  1467. if (dst_ast_entry && src_ast_entry) {
  1468. if (dst_ast_entry->peer_id ==
  1469. src_ast_entry->peer_id)
  1470. return 1;
  1471. }
  1472. return 0;
  1473. }
  1474. /**
  1475. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1476. * @vdev: DP vdev handle
  1477. * @nbuf: skb
  1478. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1479. * @meta_data: Metadata to the fw
  1480. * @tx_q: Tx queue to be used for this Tx frame
  1481. * @peer_id: peer_id of the peer in case of NAWDS frames
  1482. * @tx_exc_metadata: Handle that holds exception path metadata
  1483. *
  1484. * Return: NULL on success,
  1485. * nbuf when it fails to send
  1486. */
  1487. qdf_nbuf_t
  1488. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1489. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1490. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1491. {
  1492. struct dp_pdev *pdev = vdev->pdev;
  1493. struct dp_soc *soc = pdev->soc;
  1494. struct dp_tx_desc_s *tx_desc;
  1495. QDF_STATUS status;
  1496. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1497. uint16_t htt_tcl_metadata = 0;
  1498. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  1499. uint8_t tid = msdu_info->tid;
  1500. struct cdp_tid_tx_stats *tid_stats = NULL;
  1501. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1502. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1503. msdu_info, tx_exc_metadata);
  1504. if (!tx_desc) {
  1505. dp_err_rl("Tx_desc prepare Fail vdev %pK queue %d",
  1506. vdev, tx_q->desc_pool_id);
  1507. drop_code = TX_DESC_ERR;
  1508. goto fail_return;
  1509. }
  1510. if (qdf_unlikely(soc->cce_disable)) {
  1511. if (dp_cce_classify(vdev, nbuf) == true) {
  1512. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1513. tid = DP_VO_TID;
  1514. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1515. }
  1516. }
  1517. dp_tx_update_tdls_flags(tx_desc);
  1518. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1519. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1520. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1521. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1522. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1523. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1524. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1525. peer_id);
  1526. } else
  1527. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1528. if (msdu_info->exception_fw)
  1529. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1530. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  1531. !pdev->enhanced_stats_en);
  1532. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  1533. dp_tx_msdu_single_map(vdev, tx_desc, nbuf))) {
  1534. /* Handle failure */
  1535. dp_err("qdf_nbuf_map failed");
  1536. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  1537. drop_code = TX_DMA_MAP_ERR;
  1538. goto release_desc;
  1539. }
  1540. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1541. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1542. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1543. if (status != QDF_STATUS_SUCCESS) {
  1544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1545. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1546. __func__, tx_desc, tx_q->ring_id);
  1547. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  1548. QDF_DMA_TO_DEVICE,
  1549. nbuf->len);
  1550. drop_code = TX_HW_ENQUEUE;
  1551. goto release_desc;
  1552. }
  1553. return NULL;
  1554. release_desc:
  1555. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1556. fail_return:
  1557. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1558. tid_stats = &pdev->stats.tid_stats.
  1559. tid_tx_stats[tx_q->ring_id][tid];
  1560. tid_stats->swdrop_cnt[drop_code]++;
  1561. return nbuf;
  1562. }
  1563. /**
  1564. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1565. * @vdev: DP vdev handle
  1566. * @nbuf: skb
  1567. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1568. *
  1569. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1570. *
  1571. * Return: NULL on success,
  1572. * nbuf when it fails to send
  1573. */
  1574. #if QDF_LOCK_STATS
  1575. noinline
  1576. #else
  1577. #endif
  1578. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1579. struct dp_tx_msdu_info_s *msdu_info)
  1580. {
  1581. uint32_t i;
  1582. struct dp_pdev *pdev = vdev->pdev;
  1583. struct dp_soc *soc = pdev->soc;
  1584. struct dp_tx_desc_s *tx_desc;
  1585. bool is_cce_classified = false;
  1586. QDF_STATUS status;
  1587. uint16_t htt_tcl_metadata = 0;
  1588. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1589. struct cdp_tid_tx_stats *tid_stats = NULL;
  1590. if (qdf_unlikely(soc->cce_disable)) {
  1591. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1592. if (is_cce_classified) {
  1593. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1594. msdu_info->tid = DP_VO_TID;
  1595. }
  1596. }
  1597. if (msdu_info->frm_type == dp_tx_frm_me)
  1598. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1599. i = 0;
  1600. /* Print statement to track i and num_seg */
  1601. /*
  1602. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1603. * descriptors using information in msdu_info
  1604. */
  1605. while (i < msdu_info->num_seg) {
  1606. /*
  1607. * Setup Tx descriptor for an MSDU, and MSDU extension
  1608. * descriptor
  1609. */
  1610. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1611. tx_q->desc_pool_id);
  1612. if (!tx_desc) {
  1613. if (msdu_info->frm_type == dp_tx_frm_me) {
  1614. dp_tx_me_free_buf(pdev,
  1615. (void *)(msdu_info->u.sg_info
  1616. .curr_seg->frags[0].vaddr));
  1617. i++;
  1618. continue;
  1619. }
  1620. goto done;
  1621. }
  1622. if (msdu_info->frm_type == dp_tx_frm_me) {
  1623. tx_desc->me_buffer =
  1624. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1625. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1626. }
  1627. if (is_cce_classified)
  1628. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1629. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1630. if (msdu_info->exception_fw) {
  1631. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1632. }
  1633. /*
  1634. * Enqueue the Tx MSDU descriptor to HW for transmit
  1635. */
  1636. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1637. htt_tcl_metadata, tx_q->ring_id, NULL);
  1638. if (status != QDF_STATUS_SUCCESS) {
  1639. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1640. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d",
  1641. __func__, tx_desc, tx_q->ring_id);
  1642. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1643. tid_stats = &pdev->stats.tid_stats.
  1644. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  1645. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  1646. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1647. if (msdu_info->frm_type == dp_tx_frm_me) {
  1648. i++;
  1649. continue;
  1650. }
  1651. goto done;
  1652. }
  1653. /*
  1654. * TODO
  1655. * if tso_info structure can be modified to have curr_seg
  1656. * as first element, following 2 blocks of code (for TSO and SG)
  1657. * can be combined into 1
  1658. */
  1659. /*
  1660. * For frames with multiple segments (TSO, ME), jump to next
  1661. * segment.
  1662. */
  1663. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1664. if (msdu_info->u.tso_info.curr_seg->next) {
  1665. msdu_info->u.tso_info.curr_seg =
  1666. msdu_info->u.tso_info.curr_seg->next;
  1667. /*
  1668. * If this is a jumbo nbuf, then increment the number of
  1669. * nbuf users for each additional segment of the msdu.
  1670. * This will ensure that the skb is freed only after
  1671. * receiving tx completion for all segments of an nbuf
  1672. */
  1673. qdf_nbuf_inc_users(nbuf);
  1674. /* Check with MCL if this is needed */
  1675. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1676. }
  1677. }
  1678. /*
  1679. * For Multicast-Unicast converted packets,
  1680. * each converted frame (for a client) is represented as
  1681. * 1 segment
  1682. */
  1683. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1684. (msdu_info->frm_type == dp_tx_frm_me)) {
  1685. if (msdu_info->u.sg_info.curr_seg->next) {
  1686. msdu_info->u.sg_info.curr_seg =
  1687. msdu_info->u.sg_info.curr_seg->next;
  1688. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1689. }
  1690. }
  1691. i++;
  1692. }
  1693. nbuf = NULL;
  1694. done:
  1695. return nbuf;
  1696. }
  1697. /**
  1698. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1699. * for SG frames
  1700. * @vdev: DP vdev handle
  1701. * @nbuf: skb
  1702. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1703. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1704. *
  1705. * Return: NULL on success,
  1706. * nbuf when it fails to send
  1707. */
  1708. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1709. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1710. {
  1711. uint32_t cur_frag, nr_frags;
  1712. qdf_dma_addr_t paddr;
  1713. struct dp_tx_sg_info_s *sg_info;
  1714. sg_info = &msdu_info->u.sg_info;
  1715. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1716. if (QDF_STATUS_SUCCESS !=
  1717. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  1718. QDF_DMA_TO_DEVICE, nbuf->len)) {
  1719. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1720. "dma map error");
  1721. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1722. qdf_nbuf_free(nbuf);
  1723. return NULL;
  1724. }
  1725. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  1726. seg_info->frags[0].paddr_lo = paddr;
  1727. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1728. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1729. seg_info->frags[0].vaddr = (void *) nbuf;
  1730. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1731. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1732. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1734. "frag dma map error");
  1735. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1736. qdf_nbuf_free(nbuf);
  1737. return NULL;
  1738. }
  1739. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  1740. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1741. seg_info->frags[cur_frag + 1].paddr_hi =
  1742. ((uint64_t) paddr) >> 32;
  1743. seg_info->frags[cur_frag + 1].len =
  1744. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1745. }
  1746. seg_info->frag_cnt = (cur_frag + 1);
  1747. seg_info->total_len = qdf_nbuf_len(nbuf);
  1748. seg_info->next = NULL;
  1749. sg_info->curr_seg = seg_info;
  1750. msdu_info->frm_type = dp_tx_frm_sg;
  1751. msdu_info->num_seg = 1;
  1752. return nbuf;
  1753. }
  1754. /**
  1755. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  1756. * @vdev: DP vdev handle
  1757. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1758. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  1759. *
  1760. * Return: NULL on failure,
  1761. * nbuf when extracted successfully
  1762. */
  1763. static
  1764. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  1765. struct dp_tx_msdu_info_s *msdu_info,
  1766. uint16_t ppdu_cookie)
  1767. {
  1768. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1769. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1770. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1771. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  1772. (msdu_info->meta_data[5], 1);
  1773. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  1774. (msdu_info->meta_data[5], 1);
  1775. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  1776. (msdu_info->meta_data[6], ppdu_cookie);
  1777. msdu_info->exception_fw = 1;
  1778. msdu_info->is_tx_sniffer = 1;
  1779. }
  1780. #ifdef MESH_MODE_SUPPORT
  1781. /**
  1782. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1783. and prepare msdu_info for mesh frames.
  1784. * @vdev: DP vdev handle
  1785. * @nbuf: skb
  1786. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1787. *
  1788. * Return: NULL on failure,
  1789. * nbuf when extracted successfully
  1790. */
  1791. static
  1792. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1793. struct dp_tx_msdu_info_s *msdu_info)
  1794. {
  1795. struct meta_hdr_s *mhdr;
  1796. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1797. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1798. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1799. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1800. msdu_info->exception_fw = 0;
  1801. goto remove_meta_hdr;
  1802. }
  1803. msdu_info->exception_fw = 1;
  1804. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  1805. meta_data->host_tx_desc_pool = 1;
  1806. meta_data->update_peer_cache = 1;
  1807. meta_data->learning_frame = 1;
  1808. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1809. meta_data->power = mhdr->power;
  1810. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1811. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1812. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1813. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1814. meta_data->dyn_bw = 1;
  1815. meta_data->valid_pwr = 1;
  1816. meta_data->valid_mcs_mask = 1;
  1817. meta_data->valid_nss_mask = 1;
  1818. meta_data->valid_preamble_type = 1;
  1819. meta_data->valid_retries = 1;
  1820. meta_data->valid_bw_info = 1;
  1821. }
  1822. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1823. meta_data->encrypt_type = 0;
  1824. meta_data->valid_encrypt_type = 1;
  1825. meta_data->learning_frame = 0;
  1826. }
  1827. meta_data->valid_key_flags = 1;
  1828. meta_data->key_flags = (mhdr->keyix & 0x3);
  1829. remove_meta_hdr:
  1830. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1831. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1832. "qdf_nbuf_pull_head failed");
  1833. qdf_nbuf_free(nbuf);
  1834. return NULL;
  1835. }
  1836. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1837. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1838. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1839. " tid %d to_fw %d",
  1840. __func__, msdu_info->meta_data[0],
  1841. msdu_info->meta_data[1],
  1842. msdu_info->meta_data[2],
  1843. msdu_info->meta_data[3],
  1844. msdu_info->meta_data[4],
  1845. msdu_info->meta_data[5],
  1846. msdu_info->tid, msdu_info->exception_fw);
  1847. return nbuf;
  1848. }
  1849. #else
  1850. static
  1851. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1852. struct dp_tx_msdu_info_s *msdu_info)
  1853. {
  1854. return nbuf;
  1855. }
  1856. #endif
  1857. /**
  1858. * dp_check_exc_metadata() - Checks if parameters are valid
  1859. * @tx_exc - holds all exception path parameters
  1860. *
  1861. * Returns true when all the parameters are valid else false
  1862. *
  1863. */
  1864. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1865. {
  1866. bool invalid_tid = (tx_exc->tid > DP_MAX_TIDS && tx_exc->tid !=
  1867. HTT_INVALID_TID);
  1868. bool invalid_encap_type =
  1869. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  1870. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  1871. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  1872. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  1873. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  1874. tx_exc->ppdu_cookie == 0);
  1875. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  1876. invalid_cookie) {
  1877. return false;
  1878. }
  1879. return true;
  1880. }
  1881. /**
  1882. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1883. * @soc: DP soc handle
  1884. * @vdev_id: id of DP vdev handle
  1885. * @nbuf: skb
  1886. * @tx_exc_metadata: Handle that holds exception path meta data
  1887. *
  1888. * Entry point for Core Tx layer (DP_TX) invoked from
  1889. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1890. *
  1891. * Return: NULL on success,
  1892. * nbuf when it fails to send
  1893. */
  1894. qdf_nbuf_t
  1895. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1896. qdf_nbuf_t nbuf,
  1897. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1898. {
  1899. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1900. qdf_ether_header_t *eh = NULL;
  1901. struct dp_tx_msdu_info_s msdu_info;
  1902. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id);
  1903. if (qdf_unlikely(!vdev))
  1904. goto fail;
  1905. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  1906. if (!tx_exc_metadata)
  1907. goto fail;
  1908. msdu_info.tid = tx_exc_metadata->tid;
  1909. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  1910. dp_verbose_debug("skb %pM", nbuf->data);
  1911. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1912. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1913. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1914. "Invalid parameters in exception path");
  1915. goto fail;
  1916. }
  1917. /* Basic sanity checks for unsupported packets */
  1918. /* MESH mode */
  1919. if (qdf_unlikely(vdev->mesh_vdev)) {
  1920. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1921. "Mesh mode is not supported in exception path");
  1922. goto fail;
  1923. }
  1924. /* TSO or SG */
  1925. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1926. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1927. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1928. "TSO and SG are not supported in exception path");
  1929. goto fail;
  1930. }
  1931. /* RAW */
  1932. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1933. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1934. "Raw frame is not supported in exception path");
  1935. goto fail;
  1936. }
  1937. /* Mcast enhancement*/
  1938. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1939. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  1940. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  1941. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1942. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW");
  1943. }
  1944. }
  1945. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  1946. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  1947. qdf_nbuf_len(nbuf));
  1948. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  1949. tx_exc_metadata->ppdu_cookie);
  1950. }
  1951. /*
  1952. * Get HW Queue to use for this frame.
  1953. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1954. * dedicated for data and 1 for command.
  1955. * "queue_id" maps to one hardware ring.
  1956. * With each ring, we also associate a unique Tx descriptor pool
  1957. * to minimize lock contention for these resources.
  1958. */
  1959. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1960. /*
  1961. * Check exception descriptors
  1962. */
  1963. if (dp_tx_exception_limit_check(vdev))
  1964. goto fail;
  1965. /* Single linear frame */
  1966. /*
  1967. * If nbuf is a simple linear frame, use send_single function to
  1968. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1969. * SRNG. There is no need to setup a MSDU extension descriptor.
  1970. */
  1971. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1972. tx_exc_metadata->peer_id, tx_exc_metadata);
  1973. dp_vdev_unref_delete(soc, vdev);
  1974. return nbuf;
  1975. fail:
  1976. if (vdev)
  1977. dp_vdev_unref_delete(soc, vdev);
  1978. dp_verbose_debug("pkt send failed");
  1979. return nbuf;
  1980. }
  1981. /**
  1982. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1983. * @soc: DP soc handle
  1984. * @vdev_id: DP vdev handle
  1985. * @nbuf: skb
  1986. *
  1987. * Entry point for Core Tx layer (DP_TX) invoked from
  1988. * hard_start_xmit in OSIF/HDD
  1989. *
  1990. * Return: NULL on success,
  1991. * nbuf when it fails to send
  1992. */
  1993. #ifdef MESH_MODE_SUPPORT
  1994. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  1995. qdf_nbuf_t nbuf)
  1996. {
  1997. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  1998. struct meta_hdr_s *mhdr;
  1999. qdf_nbuf_t nbuf_mesh = NULL;
  2000. qdf_nbuf_t nbuf_clone = NULL;
  2001. struct dp_vdev *vdev;
  2002. uint8_t no_enc_frame = 0;
  2003. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  2004. if (!nbuf_mesh) {
  2005. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2006. "qdf_nbuf_unshare failed");
  2007. return nbuf;
  2008. }
  2009. vdev = dp_vdev_get_ref_by_id(soc, vdev_id);
  2010. if (!vdev) {
  2011. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2012. "vdev is NULL for vdev_id %d", vdev_id);
  2013. return nbuf;
  2014. }
  2015. nbuf = nbuf_mesh;
  2016. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2017. if ((vdev->sec_type != cdp_sec_type_none) &&
  2018. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  2019. no_enc_frame = 1;
  2020. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  2021. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  2022. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  2023. !no_enc_frame) {
  2024. nbuf_clone = qdf_nbuf_clone(nbuf);
  2025. if (!nbuf_clone) {
  2026. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2027. "qdf_nbuf_clone failed");
  2028. dp_vdev_unref_delete(soc, vdev);
  2029. return nbuf;
  2030. }
  2031. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  2032. }
  2033. if (nbuf_clone) {
  2034. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  2035. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2036. } else {
  2037. qdf_nbuf_free(nbuf_clone);
  2038. }
  2039. }
  2040. if (no_enc_frame)
  2041. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  2042. else
  2043. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  2044. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  2045. if ((!nbuf) && no_enc_frame) {
  2046. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  2047. }
  2048. dp_vdev_unref_delete(soc, vdev);
  2049. return nbuf;
  2050. }
  2051. #else
  2052. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  2053. qdf_nbuf_t nbuf)
  2054. {
  2055. return dp_tx_send(soc, vdev_id, nbuf);
  2056. }
  2057. #endif
  2058. /**
  2059. * dp_tx_nawds_handler() - NAWDS handler
  2060. *
  2061. * @soc: DP soc handle
  2062. * @vdev_id: id of DP vdev handle
  2063. * @msdu_info: msdu_info required to create HTT metadata
  2064. * @nbuf: skb
  2065. *
  2066. * This API transfers the multicast frames with the peer id
  2067. * on NAWDS enabled peer.
  2068. * Return: none
  2069. */
  2070. static inline
  2071. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2072. struct dp_tx_msdu_info_s *msdu_info, qdf_nbuf_t nbuf)
  2073. {
  2074. struct dp_peer *peer = NULL;
  2075. qdf_nbuf_t nbuf_clone = NULL;
  2076. uint16_t peer_id = DP_INVALID_PEER;
  2077. uint16_t sa_peer_id = DP_INVALID_PEER;
  2078. struct dp_ast_entry *ast_entry = NULL;
  2079. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2080. if (qdf_nbuf_get_tx_ftype(nbuf) == CB_FTYPE_INTRABSS_FWD) {
  2081. qdf_spin_lock_bh(&soc->ast_lock);
  2082. ast_entry = dp_peer_ast_hash_find_by_pdevid
  2083. (soc,
  2084. (uint8_t *)(eh->ether_shost),
  2085. vdev->pdev->pdev_id);
  2086. if (ast_entry)
  2087. sa_peer_id = ast_entry->peer_id;
  2088. qdf_spin_unlock_bh(&soc->ast_lock);
  2089. }
  2090. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2091. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2092. if (!peer->bss_peer && peer->nawds_enabled) {
  2093. peer_id = peer->peer_id;
  2094. /* Multicast packets needs to be
  2095. * dropped in case of intra bss forwarding
  2096. */
  2097. if (sa_peer_id == peer->peer_id) {
  2098. QDF_TRACE(QDF_MODULE_ID_DP,
  2099. QDF_TRACE_LEVEL_DEBUG,
  2100. " %s: multicast packet", __func__);
  2101. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  2102. continue;
  2103. }
  2104. nbuf_clone = qdf_nbuf_clone(nbuf);
  2105. if (!nbuf_clone) {
  2106. QDF_TRACE(QDF_MODULE_ID_DP,
  2107. QDF_TRACE_LEVEL_ERROR,
  2108. FL("nbuf clone failed"));
  2109. break;
  2110. }
  2111. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2112. msdu_info, peer_id,
  2113. NULL);
  2114. if (nbuf_clone) {
  2115. QDF_TRACE(QDF_MODULE_ID_DP,
  2116. QDF_TRACE_LEVEL_DEBUG,
  2117. FL("pkt send failed"));
  2118. qdf_nbuf_free(nbuf_clone);
  2119. } else {
  2120. if (peer_id != DP_INVALID_PEER)
  2121. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  2122. 1, qdf_nbuf_len(nbuf));
  2123. }
  2124. }
  2125. }
  2126. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2127. }
  2128. /**
  2129. * dp_tx_send() - Transmit a frame on a given VAP
  2130. * @soc: DP soc handle
  2131. * @vdev_id: id of DP vdev handle
  2132. * @nbuf: skb
  2133. *
  2134. * Entry point for Core Tx layer (DP_TX) invoked from
  2135. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  2136. * cases
  2137. *
  2138. * Return: NULL on success,
  2139. * nbuf when it fails to send
  2140. */
  2141. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2142. qdf_nbuf_t nbuf)
  2143. {
  2144. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2145. uint16_t peer_id = HTT_INVALID_PEER;
  2146. /*
  2147. * doing a memzero is causing additional function call overhead
  2148. * so doing static stack clearing
  2149. */
  2150. struct dp_tx_msdu_info_s msdu_info = {0};
  2151. struct dp_vdev *vdev = NULL;
  2152. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  2153. return nbuf;
  2154. /*
  2155. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  2156. * this in per packet path.
  2157. *
  2158. * As in this path vdev memory is already protected with netdev
  2159. * tx lock
  2160. */
  2161. vdev = soc->vdev_id_map[vdev_id];
  2162. if (qdf_unlikely(!vdev))
  2163. return nbuf;
  2164. dp_verbose_debug("skb %pM", nbuf->data);
  2165. /*
  2166. * Set Default Host TID value to invalid TID
  2167. * (TID override disabled)
  2168. */
  2169. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  2170. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2171. if (qdf_unlikely(vdev->mesh_vdev)) {
  2172. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  2173. &msdu_info);
  2174. if (!nbuf_mesh) {
  2175. dp_verbose_debug("Extracting mesh metadata failed");
  2176. return nbuf;
  2177. }
  2178. nbuf = nbuf_mesh;
  2179. }
  2180. /*
  2181. * Get HW Queue to use for this frame.
  2182. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2183. * dedicated for data and 1 for command.
  2184. * "queue_id" maps to one hardware ring.
  2185. * With each ring, we also associate a unique Tx descriptor pool
  2186. * to minimize lock contention for these resources.
  2187. */
  2188. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2189. /*
  2190. * TCL H/W supports 2 DSCP-TID mapping tables.
  2191. * Table 1 - Default DSCP-TID mapping table
  2192. * Table 2 - 1 DSCP-TID override table
  2193. *
  2194. * If we need a different DSCP-TID mapping for this vap,
  2195. * call tid_classify to extract DSCP/ToS from frame and
  2196. * map to a TID and store in msdu_info. This is later used
  2197. * to fill in TCL Input descriptor (per-packet TID override).
  2198. */
  2199. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  2200. /*
  2201. * Classify the frame and call corresponding
  2202. * "prepare" function which extracts the segment (TSO)
  2203. * and fragmentation information (for TSO , SG, ME, or Raw)
  2204. * into MSDU_INFO structure which is later used to fill
  2205. * SW and HW descriptors.
  2206. */
  2207. if (qdf_nbuf_is_tso(nbuf)) {
  2208. dp_verbose_debug("TSO frame %pK", vdev);
  2209. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2210. qdf_nbuf_len(nbuf));
  2211. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2212. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2213. qdf_nbuf_len(nbuf));
  2214. return nbuf;
  2215. }
  2216. goto send_multiple;
  2217. }
  2218. /* SG */
  2219. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2220. struct dp_tx_seg_info_s seg_info = {0};
  2221. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2222. if (!nbuf)
  2223. return NULL;
  2224. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2225. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2226. qdf_nbuf_len(nbuf));
  2227. goto send_multiple;
  2228. }
  2229. #ifdef ATH_SUPPORT_IQUE
  2230. /* Mcast to Ucast Conversion*/
  2231. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  2232. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2233. qdf_nbuf_data(nbuf);
  2234. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2235. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2236. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2237. DP_STATS_INC_PKT(vdev,
  2238. tx_i.mcast_en.mcast_pkt, 1,
  2239. qdf_nbuf_len(nbuf));
  2240. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2241. QDF_STATUS_SUCCESS) {
  2242. return NULL;
  2243. }
  2244. }
  2245. }
  2246. #endif
  2247. /* RAW */
  2248. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  2249. struct dp_tx_seg_info_s seg_info = {0};
  2250. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  2251. if (!nbuf)
  2252. return NULL;
  2253. dp_verbose_debug("Raw frame %pK", vdev);
  2254. goto send_multiple;
  2255. }
  2256. if (qdf_unlikely(vdev->nawds_enabled)) {
  2257. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2258. qdf_nbuf_data(nbuf);
  2259. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost))
  2260. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf);
  2261. peer_id = DP_INVALID_PEER;
  2262. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2263. 1, qdf_nbuf_len(nbuf));
  2264. }
  2265. /* Single linear frame */
  2266. /*
  2267. * If nbuf is a simple linear frame, use send_single function to
  2268. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2269. * SRNG. There is no need to setup a MSDU extension descriptor.
  2270. */
  2271. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  2272. return nbuf;
  2273. send_multiple:
  2274. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2275. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  2276. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  2277. return nbuf;
  2278. }
  2279. /**
  2280. * dp_tx_reinject_handler() - Tx Reinject Handler
  2281. * @tx_desc: software descriptor head pointer
  2282. * @status : Tx completion status from HTT descriptor
  2283. *
  2284. * This function reinjects frames back to Target.
  2285. * Todo - Host queue needs to be added
  2286. *
  2287. * Return: none
  2288. */
  2289. static
  2290. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2291. {
  2292. struct dp_vdev *vdev;
  2293. struct dp_peer *peer = NULL;
  2294. uint32_t peer_id = HTT_INVALID_PEER;
  2295. qdf_nbuf_t nbuf = tx_desc->nbuf;
  2296. qdf_nbuf_t nbuf_copy = NULL;
  2297. struct dp_tx_msdu_info_s msdu_info;
  2298. struct dp_soc *soc = NULL;
  2299. #ifdef WDS_VENDOR_EXTENSION
  2300. int is_mcast = 0, is_ucast = 0;
  2301. int num_peers_3addr = 0;
  2302. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  2303. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  2304. #endif
  2305. vdev = tx_desc->vdev;
  2306. soc = vdev->pdev->soc;
  2307. qdf_assert(vdev);
  2308. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2309. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2310. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2311. "%s Tx reinject path", __func__);
  2312. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  2313. qdf_nbuf_len(tx_desc->nbuf));
  2314. #ifdef WDS_VENDOR_EXTENSION
  2315. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  2316. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  2317. } else {
  2318. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  2319. }
  2320. is_ucast = !is_mcast;
  2321. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2322. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2323. if (peer->bss_peer)
  2324. continue;
  2325. /* Detect wds peers that use 3-addr framing for mcast.
  2326. * if there are any, the bss_peer is used to send the
  2327. * the mcast frame using 3-addr format. all wds enabled
  2328. * peers that use 4-addr framing for mcast frames will
  2329. * be duplicated and sent as 4-addr frames below.
  2330. */
  2331. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  2332. num_peers_3addr = 1;
  2333. break;
  2334. }
  2335. }
  2336. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2337. #endif
  2338. if (qdf_unlikely(vdev->mesh_vdev)) {
  2339. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  2340. } else {
  2341. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2342. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2343. if ((peer->peer_id != HTT_INVALID_PEER) &&
  2344. #ifdef WDS_VENDOR_EXTENSION
  2345. /*
  2346. * . if 3-addr STA, then send on BSS Peer
  2347. * . if Peer WDS enabled and accept 4-addr mcast,
  2348. * send mcast on that peer only
  2349. * . if Peer WDS enabled and accept 4-addr ucast,
  2350. * send ucast on that peer only
  2351. */
  2352. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  2353. (peer->wds_enabled &&
  2354. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  2355. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  2356. #else
  2357. ((peer->bss_peer &&
  2358. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))))) {
  2359. #endif
  2360. peer_id = DP_INVALID_PEER;
  2361. nbuf_copy = qdf_nbuf_copy(nbuf);
  2362. if (!nbuf_copy) {
  2363. QDF_TRACE(QDF_MODULE_ID_DP,
  2364. QDF_TRACE_LEVEL_DEBUG,
  2365. FL("nbuf copy failed"));
  2366. break;
  2367. }
  2368. nbuf_copy = dp_tx_send_msdu_single(vdev,
  2369. nbuf_copy,
  2370. &msdu_info,
  2371. peer_id,
  2372. NULL);
  2373. if (nbuf_copy) {
  2374. QDF_TRACE(QDF_MODULE_ID_DP,
  2375. QDF_TRACE_LEVEL_DEBUG,
  2376. FL("pkt send failed"));
  2377. qdf_nbuf_free(nbuf_copy);
  2378. }
  2379. }
  2380. }
  2381. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2382. }
  2383. qdf_nbuf_free(nbuf);
  2384. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2385. }
  2386. /**
  2387. * dp_tx_inspect_handler() - Tx Inspect Handler
  2388. * @tx_desc: software descriptor head pointer
  2389. * @status : Tx completion status from HTT descriptor
  2390. *
  2391. * Handles Tx frames sent back to Host for inspection
  2392. * (ProxyARP)
  2393. *
  2394. * Return: none
  2395. */
  2396. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2397. {
  2398. struct dp_soc *soc;
  2399. struct dp_pdev *pdev = tx_desc->pdev;
  2400. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2401. "%s Tx inspect path",
  2402. __func__);
  2403. qdf_assert(pdev);
  2404. soc = pdev->soc;
  2405. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  2406. qdf_nbuf_len(tx_desc->nbuf));
  2407. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  2408. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2409. }
  2410. #ifdef FEATURE_PERPKT_INFO
  2411. /**
  2412. * dp_get_completion_indication_for_stack() - send completion to stack
  2413. * @soc : dp_soc handle
  2414. * @pdev: dp_pdev handle
  2415. * @peer: dp peer handle
  2416. * @ts: transmit completion status structure
  2417. * @netbuf: Buffer pointer for free
  2418. *
  2419. * This function is used for indication whether buffer needs to be
  2420. * sent to stack for freeing or not
  2421. */
  2422. QDF_STATUS
  2423. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2424. struct dp_pdev *pdev,
  2425. struct dp_peer *peer,
  2426. struct hal_tx_completion_status *ts,
  2427. qdf_nbuf_t netbuf,
  2428. uint64_t time_latency)
  2429. {
  2430. struct tx_capture_hdr *ppdu_hdr;
  2431. uint16_t peer_id = ts->peer_id;
  2432. uint32_t ppdu_id = ts->ppdu_id;
  2433. uint8_t first_msdu = ts->first_msdu;
  2434. uint8_t last_msdu = ts->last_msdu;
  2435. uint32_t txcap_hdr_size = sizeof(struct tx_capture_hdr);
  2436. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode &&
  2437. !pdev->latency_capture_enable))
  2438. return QDF_STATUS_E_NOSUPPORT;
  2439. if (!peer) {
  2440. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2441. FL("Peer Invalid"));
  2442. return QDF_STATUS_E_INVAL;
  2443. }
  2444. if (pdev->mcopy_mode) {
  2445. /* If mcopy is enabled and mcopy_mode is M_COPY deliver 1st MSDU
  2446. * per PPDU. If mcopy_mode is M_COPY_EXTENDED deliver 1st MSDU
  2447. * for each MPDU
  2448. */
  2449. if (pdev->mcopy_mode == M_COPY) {
  2450. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  2451. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  2452. return QDF_STATUS_E_INVAL;
  2453. }
  2454. }
  2455. if (!first_msdu)
  2456. return QDF_STATUS_E_INVAL;
  2457. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  2458. pdev->m_copy_id.tx_peer_id = peer_id;
  2459. }
  2460. if (qdf_unlikely(qdf_nbuf_headroom(netbuf) < txcap_hdr_size)) {
  2461. netbuf = qdf_nbuf_realloc_headroom(netbuf, txcap_hdr_size);
  2462. if (!netbuf) {
  2463. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2464. FL("No headroom"));
  2465. return QDF_STATUS_E_NOMEM;
  2466. }
  2467. }
  2468. if (!qdf_nbuf_push_head(netbuf, txcap_hdr_size)) {
  2469. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2470. FL("No headroom"));
  2471. return QDF_STATUS_E_NOMEM;
  2472. }
  2473. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  2474. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  2475. QDF_MAC_ADDR_SIZE);
  2476. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  2477. QDF_MAC_ADDR_SIZE);
  2478. ppdu_hdr->ppdu_id = ppdu_id;
  2479. ppdu_hdr->peer_id = peer_id;
  2480. ppdu_hdr->first_msdu = first_msdu;
  2481. ppdu_hdr->last_msdu = last_msdu;
  2482. if (qdf_unlikely(pdev->latency_capture_enable)) {
  2483. ppdu_hdr->tsf = ts->tsf;
  2484. ppdu_hdr->time_latency = time_latency;
  2485. }
  2486. return QDF_STATUS_SUCCESS;
  2487. }
  2488. /**
  2489. * dp_send_completion_to_stack() - send completion to stack
  2490. * @soc : dp_soc handle
  2491. * @pdev: dp_pdev handle
  2492. * @peer_id: peer_id of the peer for which completion came
  2493. * @ppdu_id: ppdu_id
  2494. * @netbuf: Buffer pointer for free
  2495. *
  2496. * This function is used to send completion to stack
  2497. * to free buffer
  2498. */
  2499. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2500. uint16_t peer_id, uint32_t ppdu_id,
  2501. qdf_nbuf_t netbuf)
  2502. {
  2503. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  2504. netbuf, peer_id,
  2505. WDI_NO_VAL, pdev->pdev_id);
  2506. }
  2507. #else
  2508. static QDF_STATUS
  2509. dp_get_completion_indication_for_stack(struct dp_soc *soc,
  2510. struct dp_pdev *pdev,
  2511. struct dp_peer *peer,
  2512. struct hal_tx_completion_status *ts,
  2513. qdf_nbuf_t netbuf,
  2514. uint64_t time_latency)
  2515. {
  2516. return QDF_STATUS_E_NOSUPPORT;
  2517. }
  2518. static void
  2519. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  2520. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  2521. {
  2522. }
  2523. #endif
  2524. /**
  2525. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2526. * @soc: Soc handle
  2527. * @desc: software Tx descriptor to be processed
  2528. *
  2529. * Return: none
  2530. */
  2531. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2532. struct dp_tx_desc_s *desc)
  2533. {
  2534. struct dp_vdev *vdev = desc->vdev;
  2535. qdf_nbuf_t nbuf = desc->nbuf;
  2536. /* nbuf already freed in vdev detach path */
  2537. if (!nbuf)
  2538. return;
  2539. /* If it is TDLS mgmt, don't unmap or free the frame */
  2540. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2541. return dp_non_std_tx_comp_free_buff(soc, desc, vdev);
  2542. /* 0 : MSDU buffer, 1 : MLE */
  2543. if (desc->msdu_ext_desc) {
  2544. /* TSO free */
  2545. if (hal_tx_ext_desc_get_tso_enable(
  2546. desc->msdu_ext_desc->vaddr)) {
  2547. /* unmap eash TSO seg before free the nbuf */
  2548. dp_tx_tso_unmap_segment(soc, desc->tso_desc,
  2549. desc->tso_num_desc);
  2550. qdf_nbuf_free(nbuf);
  2551. return;
  2552. }
  2553. }
  2554. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2555. QDF_DMA_TO_DEVICE, nbuf->len);
  2556. if (qdf_unlikely(!vdev)) {
  2557. qdf_nbuf_free(nbuf);
  2558. return;
  2559. }
  2560. if (qdf_likely(!vdev->mesh_vdev))
  2561. qdf_nbuf_free(nbuf);
  2562. else {
  2563. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2564. qdf_nbuf_free(nbuf);
  2565. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2566. } else
  2567. vdev->osif_tx_free_ext((nbuf));
  2568. }
  2569. }
  2570. #ifdef MESH_MODE_SUPPORT
  2571. /**
  2572. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2573. * in mesh meta header
  2574. * @tx_desc: software descriptor head pointer
  2575. * @ts: pointer to tx completion stats
  2576. * Return: none
  2577. */
  2578. static
  2579. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2580. struct hal_tx_completion_status *ts)
  2581. {
  2582. struct meta_hdr_s *mhdr;
  2583. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2584. if (!tx_desc->msdu_ext_desc) {
  2585. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2586. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2587. "netbuf %pK offset %d",
  2588. netbuf, tx_desc->pkt_offset);
  2589. return;
  2590. }
  2591. }
  2592. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2593. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2594. "netbuf %pK offset %lu", netbuf,
  2595. sizeof(struct meta_hdr_s));
  2596. return;
  2597. }
  2598. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2599. mhdr->rssi = ts->ack_frame_rssi;
  2600. mhdr->band = tx_desc->pdev->operating_channel.band;
  2601. mhdr->channel = tx_desc->pdev->operating_channel.num;
  2602. }
  2603. #else
  2604. static
  2605. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2606. struct hal_tx_completion_status *ts)
  2607. {
  2608. }
  2609. #endif
  2610. #ifdef QCA_PEER_EXT_STATS
  2611. /*
  2612. * dp_tx_compute_tid_delay() - Compute per TID delay
  2613. * @stats: Per TID delay stats
  2614. * @tx_desc: Software Tx descriptor
  2615. *
  2616. * Compute the software enqueue and hw enqueue delays and
  2617. * update the respective histograms
  2618. *
  2619. * Return: void
  2620. */
  2621. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  2622. struct dp_tx_desc_s *tx_desc)
  2623. {
  2624. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  2625. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2626. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  2627. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2628. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2629. timestamp_hw_enqueue = tx_desc->timestamp;
  2630. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2631. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2632. timestamp_hw_enqueue);
  2633. /*
  2634. * Update the Tx software enqueue delay and HW enque-Completion delay.
  2635. */
  2636. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  2637. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  2638. }
  2639. /*
  2640. * dp_tx_update_peer_ext_stats() - Update the peer extended stats
  2641. * @peer: DP peer context
  2642. * @tx_desc: Tx software descriptor
  2643. * @tid: Transmission ID
  2644. * @ring_id: Rx CPU context ID/CPU_ID
  2645. *
  2646. * Update the peer extended stats. These are enhanced other
  2647. * delay stats per msdu level.
  2648. *
  2649. * Return: void
  2650. */
  2651. static void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2652. struct dp_tx_desc_s *tx_desc,
  2653. uint8_t tid, uint8_t ring_id)
  2654. {
  2655. struct dp_pdev *pdev = peer->vdev->pdev;
  2656. struct dp_soc *soc = NULL;
  2657. struct cdp_peer_ext_stats *pext_stats = NULL;
  2658. soc = pdev->soc;
  2659. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  2660. return;
  2661. pext_stats = peer->pext_stats;
  2662. qdf_assert(pext_stats);
  2663. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  2664. /*
  2665. * For non-TID packets use the TID 9
  2666. */
  2667. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2668. tid = CDP_MAX_DATA_TIDS - 1;
  2669. dp_tx_compute_tid_delay(&pext_stats->delay_stats[tid][ring_id],
  2670. tx_desc);
  2671. }
  2672. #else
  2673. static inline void dp_tx_update_peer_ext_stats(struct dp_peer *peer,
  2674. struct dp_tx_desc_s *tx_desc,
  2675. uint8_t tid, uint8_t ring_id)
  2676. {
  2677. }
  2678. #endif
  2679. /**
  2680. * dp_tx_compute_delay() - Compute and fill in all timestamps
  2681. * to pass in correct fields
  2682. *
  2683. * @vdev: pdev handle
  2684. * @tx_desc: tx descriptor
  2685. * @tid: tid value
  2686. * @ring_id: TCL or WBM ring number for transmit path
  2687. * Return: none
  2688. */
  2689. static void dp_tx_compute_delay(struct dp_vdev *vdev,
  2690. struct dp_tx_desc_s *tx_desc,
  2691. uint8_t tid, uint8_t ring_id)
  2692. {
  2693. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  2694. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  2695. if (qdf_likely(!vdev->pdev->delay_stats_flag))
  2696. return;
  2697. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  2698. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  2699. timestamp_hw_enqueue = tx_desc->timestamp;
  2700. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  2701. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  2702. timestamp_hw_enqueue);
  2703. interframe_delay = (uint32_t)(timestamp_ingress -
  2704. vdev->prev_tx_enq_tstamp);
  2705. /*
  2706. * Delay in software enqueue
  2707. */
  2708. dp_update_delay_stats(vdev->pdev, sw_enqueue_delay, tid,
  2709. CDP_DELAY_STATS_SW_ENQ, ring_id);
  2710. /*
  2711. * Delay between packet enqueued to HW and Tx completion
  2712. */
  2713. dp_update_delay_stats(vdev->pdev, fwhw_transmit_delay, tid,
  2714. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id);
  2715. /*
  2716. * Update interframe delay stats calculated at hardstart receive point.
  2717. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  2718. * interframe delay will not be calculate correctly for 1st frame.
  2719. * On the other side, this will help in avoiding extra per packet check
  2720. * of !vdev->prev_tx_enq_tstamp.
  2721. */
  2722. dp_update_delay_stats(vdev->pdev, interframe_delay, tid,
  2723. CDP_DELAY_STATS_TX_INTERFRAME, ring_id);
  2724. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  2725. }
  2726. #ifdef DISABLE_DP_STATS
  2727. static
  2728. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2729. {
  2730. }
  2731. #else
  2732. static
  2733. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_peer *peer)
  2734. {
  2735. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  2736. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  2737. if (subtype != QDF_PROTO_INVALID)
  2738. DP_STATS_INC(peer, tx.no_ack_count[subtype], 1);
  2739. }
  2740. #endif
  2741. /**
  2742. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2743. * per wbm ring
  2744. *
  2745. * @tx_desc: software descriptor head pointer
  2746. * @ts: Tx completion status
  2747. * @peer: peer handle
  2748. * @ring_id: ring number
  2749. *
  2750. * Return: None
  2751. */
  2752. static inline void
  2753. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  2754. struct hal_tx_completion_status *ts,
  2755. struct dp_peer *peer, uint8_t ring_id)
  2756. {
  2757. struct dp_pdev *pdev = peer->vdev->pdev;
  2758. struct dp_soc *soc = NULL;
  2759. uint8_t mcs, pkt_type;
  2760. uint8_t tid = ts->tid;
  2761. uint32_t length;
  2762. struct cdp_tid_tx_stats *tid_stats;
  2763. if (!pdev)
  2764. return;
  2765. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  2766. tid = CDP_MAX_DATA_TIDS - 1;
  2767. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  2768. soc = pdev->soc;
  2769. mcs = ts->mcs;
  2770. pkt_type = ts->pkt_type;
  2771. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  2772. dp_err("Release source is not from TQM");
  2773. return;
  2774. }
  2775. length = qdf_nbuf_len(tx_desc->nbuf);
  2776. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1, length);
  2777. if (qdf_unlikely(pdev->delay_stats_flag))
  2778. dp_tx_compute_delay(peer->vdev, tx_desc, tid, ring_id);
  2779. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2780. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2781. DP_STATS_INCC_PKT(peer, tx.dropped.fw_rem, 1, length,
  2782. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2783. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2784. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2785. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2786. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2787. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2788. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2789. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2790. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2791. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2792. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2793. /*
  2794. * tx_failed is ideally supposed to be updated from HTT ppdu completion
  2795. * stats. But in IPQ807X/IPQ6018 chipsets owing to hw limitation there
  2796. * are no completions for failed cases. Hence updating tx_failed from
  2797. * data path. Please note that if tx_failed is fixed to be from ppdu,
  2798. * then this has to be removed
  2799. */
  2800. peer->stats.tx.tx_failed = peer->stats.tx.dropped.fw_rem.num +
  2801. peer->stats.tx.dropped.fw_rem_notx +
  2802. peer->stats.tx.dropped.fw_rem_tx +
  2803. peer->stats.tx.dropped.age_out +
  2804. peer->stats.tx.dropped.fw_reason1 +
  2805. peer->stats.tx.dropped.fw_reason2 +
  2806. peer->stats.tx.dropped.fw_reason3;
  2807. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  2808. tid_stats->tqm_status_cnt[ts->status]++;
  2809. }
  2810. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  2811. dp_update_no_ack_stats(tx_desc->nbuf, peer);
  2812. return;
  2813. }
  2814. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2815. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2816. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2817. /*
  2818. * Following Rate Statistics are updated from HTT PPDU events from FW.
  2819. * Return from here if HTT PPDU events are enabled.
  2820. */
  2821. if (!(soc->process_tx_status))
  2822. return;
  2823. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2824. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2825. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2826. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2827. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2828. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2829. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2830. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2831. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2832. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2833. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2834. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2835. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2836. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2837. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2838. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2839. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2840. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2841. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2842. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2843. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2844. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2845. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2846. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2847. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2848. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2849. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2850. #if defined(FEATURE_PERPKT_INFO) && WDI_EVENT_ENABLE
  2851. dp_wdi_event_handler(WDI_EVENT_UPDATE_DP_STATS, pdev->soc,
  2852. &peer->stats, ts->peer_id,
  2853. UPDATE_PEER_STATS, pdev->pdev_id);
  2854. #endif
  2855. }
  2856. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2857. /**
  2858. * dp_tx_flow_pool_lock() - take flow pool lock
  2859. * @soc: core txrx main context
  2860. * @tx_desc: tx desc
  2861. *
  2862. * Return: None
  2863. */
  2864. static inline
  2865. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  2866. struct dp_tx_desc_s *tx_desc)
  2867. {
  2868. struct dp_tx_desc_pool_s *pool;
  2869. uint8_t desc_pool_id;
  2870. desc_pool_id = tx_desc->pool_id;
  2871. pool = &soc->tx_desc[desc_pool_id];
  2872. qdf_spin_lock_bh(&pool->flow_pool_lock);
  2873. }
  2874. /**
  2875. * dp_tx_flow_pool_unlock() - release flow pool lock
  2876. * @soc: core txrx main context
  2877. * @tx_desc: tx desc
  2878. *
  2879. * Return: None
  2880. */
  2881. static inline
  2882. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  2883. struct dp_tx_desc_s *tx_desc)
  2884. {
  2885. struct dp_tx_desc_pool_s *pool;
  2886. uint8_t desc_pool_id;
  2887. desc_pool_id = tx_desc->pool_id;
  2888. pool = &soc->tx_desc[desc_pool_id];
  2889. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  2890. }
  2891. #else
  2892. static inline
  2893. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2894. {
  2895. }
  2896. static inline
  2897. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2898. {
  2899. }
  2900. #endif
  2901. /**
  2902. * dp_tx_notify_completion() - Notify tx completion for this desc
  2903. * @soc: core txrx main context
  2904. * @tx_desc: tx desc
  2905. * @netbuf: buffer
  2906. * @status: tx status
  2907. *
  2908. * Return: none
  2909. */
  2910. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  2911. struct dp_tx_desc_s *tx_desc,
  2912. qdf_nbuf_t netbuf,
  2913. uint8_t status)
  2914. {
  2915. void *osif_dev;
  2916. ol_txrx_completion_fp tx_compl_cbk = NULL;
  2917. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  2918. qdf_assert(tx_desc);
  2919. dp_tx_flow_pool_lock(soc, tx_desc);
  2920. if (!tx_desc->vdev ||
  2921. !tx_desc->vdev->osif_vdev) {
  2922. dp_tx_flow_pool_unlock(soc, tx_desc);
  2923. return;
  2924. }
  2925. osif_dev = tx_desc->vdev->osif_vdev;
  2926. tx_compl_cbk = tx_desc->vdev->tx_comp;
  2927. dp_tx_flow_pool_unlock(soc, tx_desc);
  2928. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  2929. flag |= BIT(QDF_TX_RX_STATUS_OK);
  2930. if (tx_compl_cbk)
  2931. tx_compl_cbk(netbuf, osif_dev, flag);
  2932. }
  2933. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  2934. * @pdev: pdev handle
  2935. * @tid: tid value
  2936. * @txdesc_ts: timestamp from txdesc
  2937. * @ppdu_id: ppdu id
  2938. *
  2939. * Return: none
  2940. */
  2941. #ifdef FEATURE_PERPKT_INFO
  2942. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2943. struct dp_peer *peer,
  2944. uint8_t tid,
  2945. uint64_t txdesc_ts,
  2946. uint32_t ppdu_id)
  2947. {
  2948. uint64_t delta_ms;
  2949. struct cdp_tx_sojourn_stats *sojourn_stats;
  2950. if (qdf_unlikely(pdev->enhanced_stats_en == 0))
  2951. return;
  2952. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  2953. tid >= CDP_DATA_TID_MAX))
  2954. return;
  2955. if (qdf_unlikely(!pdev->sojourn_buf))
  2956. return;
  2957. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  2958. qdf_nbuf_data(pdev->sojourn_buf);
  2959. sojourn_stats->cookie = (void *)peer->wlanstats_ctx;
  2960. delta_ms = qdf_ktime_to_ms(qdf_ktime_get()) -
  2961. txdesc_ts;
  2962. qdf_ewma_tx_lag_add(&peer->avg_sojourn_msdu[tid],
  2963. delta_ms);
  2964. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  2965. sojourn_stats->num_msdus[tid] = 1;
  2966. sojourn_stats->avg_sojourn_msdu[tid].internal =
  2967. peer->avg_sojourn_msdu[tid].internal;
  2968. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  2969. pdev->sojourn_buf, HTT_INVALID_PEER,
  2970. WDI_NO_VAL, pdev->pdev_id);
  2971. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  2972. sojourn_stats->num_msdus[tid] = 0;
  2973. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  2974. }
  2975. #else
  2976. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  2977. struct dp_peer *peer,
  2978. uint8_t tid,
  2979. uint64_t txdesc_ts,
  2980. uint32_t ppdu_id)
  2981. {
  2982. }
  2983. #endif
  2984. /**
  2985. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  2986. * @soc: DP Soc handle
  2987. * @tx_desc: software Tx descriptor
  2988. * @ts : Tx completion status from HAL/HTT descriptor
  2989. *
  2990. * Return: none
  2991. */
  2992. static inline void
  2993. dp_tx_comp_process_desc(struct dp_soc *soc,
  2994. struct dp_tx_desc_s *desc,
  2995. struct hal_tx_completion_status *ts,
  2996. struct dp_peer *peer)
  2997. {
  2998. uint64_t time_latency = 0;
  2999. /*
  3000. * m_copy/tx_capture modes are not supported for
  3001. * scatter gather packets
  3002. */
  3003. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  3004. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  3005. desc->timestamp);
  3006. }
  3007. if (!(desc->msdu_ext_desc)) {
  3008. if (QDF_STATUS_SUCCESS ==
  3009. dp_tx_add_to_comp_queue(soc, desc, ts, peer)) {
  3010. return;
  3011. }
  3012. if (QDF_STATUS_SUCCESS ==
  3013. dp_get_completion_indication_for_stack(soc,
  3014. desc->pdev,
  3015. peer, ts,
  3016. desc->nbuf,
  3017. time_latency)) {
  3018. qdf_nbuf_unmap_nbytes_single(soc->osdev, desc->nbuf,
  3019. QDF_DMA_TO_DEVICE,
  3020. desc->nbuf->len);
  3021. dp_send_completion_to_stack(soc,
  3022. desc->pdev,
  3023. ts->peer_id,
  3024. ts->ppdu_id,
  3025. desc->nbuf);
  3026. return;
  3027. }
  3028. }
  3029. dp_tx_comp_free_buf(soc, desc);
  3030. }
  3031. #ifdef DISABLE_DP_STATS
  3032. /**
  3033. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  3034. * @soc: core txrx main context
  3035. * @tx_desc: tx desc
  3036. * @status: tx status
  3037. *
  3038. * Return: none
  3039. */
  3040. static inline
  3041. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3042. struct dp_tx_desc_s *tx_desc,
  3043. uint8_t status)
  3044. {
  3045. }
  3046. #else
  3047. static inline
  3048. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  3049. struct dp_tx_desc_s *tx_desc,
  3050. uint8_t status)
  3051. {
  3052. void *osif_dev;
  3053. ol_txrx_stats_rx_fp stats_cbk;
  3054. uint8_t pkt_type;
  3055. qdf_assert(tx_desc);
  3056. if (!tx_desc->vdev ||
  3057. !tx_desc->vdev->osif_vdev ||
  3058. !tx_desc->vdev->stats_cb)
  3059. return;
  3060. osif_dev = tx_desc->vdev->osif_vdev;
  3061. stats_cbk = tx_desc->vdev->stats_cb;
  3062. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  3063. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  3064. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  3065. &pkt_type);
  3066. }
  3067. #endif
  3068. /**
  3069. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  3070. * @soc: DP soc handle
  3071. * @tx_desc: software descriptor head pointer
  3072. * @ts: Tx completion status
  3073. * @peer: peer handle
  3074. * @ring_id: ring number
  3075. *
  3076. * Return: none
  3077. */
  3078. static inline
  3079. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  3080. struct dp_tx_desc_s *tx_desc,
  3081. struct hal_tx_completion_status *ts,
  3082. struct dp_peer *peer, uint8_t ring_id)
  3083. {
  3084. uint32_t length;
  3085. qdf_ether_header_t *eh;
  3086. struct dp_vdev *vdev = tx_desc->vdev;
  3087. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3088. uint8_t dp_status;
  3089. if (!vdev || !nbuf) {
  3090. dp_info_rl("invalid tx descriptor. vdev or nbuf NULL");
  3091. goto out;
  3092. }
  3093. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  3094. length = qdf_nbuf_len(nbuf);
  3095. dp_status = qdf_dp_get_status_from_htt(ts->status);
  3096. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  3097. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  3098. QDF_TRACE_DEFAULT_PDEV_ID,
  3099. qdf_nbuf_data_addr(nbuf),
  3100. sizeof(qdf_nbuf_data(nbuf)),
  3101. tx_desc->id,
  3102. dp_status));
  3103. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3104. "-------------------- \n"
  3105. "Tx Completion Stats: \n"
  3106. "-------------------- \n"
  3107. "ack_frame_rssi = %d \n"
  3108. "first_msdu = %d \n"
  3109. "last_msdu = %d \n"
  3110. "msdu_part_of_amsdu = %d \n"
  3111. "rate_stats valid = %d \n"
  3112. "bw = %d \n"
  3113. "pkt_type = %d \n"
  3114. "stbc = %d \n"
  3115. "ldpc = %d \n"
  3116. "sgi = %d \n"
  3117. "mcs = %d \n"
  3118. "ofdma = %d \n"
  3119. "tones_in_ru = %d \n"
  3120. "tsf = %d \n"
  3121. "ppdu_id = %d \n"
  3122. "transmit_cnt = %d \n"
  3123. "tid = %d \n"
  3124. "peer_id = %d\n",
  3125. ts->ack_frame_rssi, ts->first_msdu,
  3126. ts->last_msdu, ts->msdu_part_of_amsdu,
  3127. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  3128. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  3129. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  3130. ts->transmit_cnt, ts->tid, ts->peer_id);
  3131. /* Update SoC level stats */
  3132. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  3133. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  3134. if (!peer) {
  3135. dp_err_rl("peer is null or deletion in progress");
  3136. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  3137. goto out;
  3138. }
  3139. dp_tx_update_connectivity_stats(soc, tx_desc, ts->status);
  3140. /* Update per-packet stats for mesh mode */
  3141. if (qdf_unlikely(vdev->mesh_vdev) &&
  3142. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  3143. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  3144. /* Update peer level stats */
  3145. if (qdf_unlikely(peer->bss_peer && vdev->opmode == wlan_op_mode_ap)) {
  3146. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  3147. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  3148. if ((peer->vdev->tx_encap_type ==
  3149. htt_cmn_pkt_type_ethernet) &&
  3150. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  3151. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  3152. }
  3153. }
  3154. } else {
  3155. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  3156. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  3157. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  3158. if (qdf_unlikely(peer->in_twt)) {
  3159. DP_STATS_INC_PKT(peer,
  3160. tx.tx_success_twt,
  3161. 1, length);
  3162. }
  3163. }
  3164. }
  3165. dp_tx_update_peer_stats(tx_desc, ts, peer, ring_id);
  3166. dp_tx_update_peer_ext_stats(peer, tx_desc, ts->tid, ring_id);
  3167. #ifdef QCA_SUPPORT_RDK_STATS
  3168. if (soc->wlanstats_enabled)
  3169. dp_tx_sojourn_stats_process(vdev->pdev, peer, ts->tid,
  3170. tx_desc->timestamp,
  3171. ts->ppdu_id);
  3172. #endif
  3173. out:
  3174. return;
  3175. }
  3176. /**
  3177. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  3178. * @soc: core txrx main context
  3179. * @comp_head: software descriptor head pointer
  3180. * @ring_id: ring number
  3181. *
  3182. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  3183. * and release the software descriptors after processing is complete
  3184. *
  3185. * Return: none
  3186. */
  3187. static void
  3188. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  3189. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  3190. {
  3191. struct dp_tx_desc_s *desc;
  3192. struct dp_tx_desc_s *next;
  3193. struct hal_tx_completion_status ts;
  3194. struct dp_peer *peer;
  3195. qdf_nbuf_t netbuf;
  3196. desc = comp_head;
  3197. while (desc) {
  3198. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  3199. struct dp_pdev *pdev = desc->pdev;
  3200. peer = dp_peer_get_ref_by_id(soc, desc->peer_id,
  3201. DP_MOD_ID_TX_COMP);
  3202. if (qdf_likely(peer)) {
  3203. /*
  3204. * Increment peer statistics
  3205. * Minimal statistics update done here
  3206. */
  3207. DP_STATS_INC_PKT(peer, tx.comp_pkt, 1,
  3208. desc->length);
  3209. if (desc->tx_status !=
  3210. HAL_TX_TQM_RR_FRAME_ACKED)
  3211. peer->stats.tx.tx_failed++;
  3212. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3213. }
  3214. qdf_assert(pdev);
  3215. dp_tx_outstanding_dec(pdev);
  3216. /*
  3217. * Calling a QDF WRAPPER here is creating signifcant
  3218. * performance impact so avoided the wrapper call here
  3219. */
  3220. next = desc->next;
  3221. qdf_mem_unmap_nbytes_single(soc->osdev,
  3222. desc->dma_addr,
  3223. QDF_DMA_TO_DEVICE,
  3224. desc->length);
  3225. qdf_nbuf_free(desc->nbuf);
  3226. dp_tx_desc_free(soc, desc, desc->pool_id);
  3227. desc = next;
  3228. continue;
  3229. }
  3230. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  3231. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3232. DP_MOD_ID_TX_COMP);
  3233. dp_tx_comp_process_tx_status(soc, desc, &ts, peer, ring_id);
  3234. netbuf = desc->nbuf;
  3235. /* check tx complete notification */
  3236. if (QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(netbuf))
  3237. dp_tx_notify_completion(soc, desc, netbuf, ts.status);
  3238. dp_tx_comp_process_desc(soc, desc, &ts, peer);
  3239. if (peer)
  3240. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3241. next = desc->next;
  3242. dp_tx_desc_release(desc, desc->pool_id);
  3243. desc = next;
  3244. }
  3245. }
  3246. /**
  3247. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  3248. * @tx_desc: software descriptor head pointer
  3249. * @status : Tx completion status from HTT descriptor
  3250. * @ring_id: ring number
  3251. *
  3252. * This function will process HTT Tx indication messages from Target
  3253. *
  3254. * Return: none
  3255. */
  3256. static
  3257. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status,
  3258. uint8_t ring_id)
  3259. {
  3260. uint8_t tx_status;
  3261. struct dp_pdev *pdev;
  3262. struct dp_vdev *vdev;
  3263. struct dp_soc *soc;
  3264. struct hal_tx_completion_status ts = {0};
  3265. uint32_t *htt_desc = (uint32_t *)status;
  3266. struct dp_peer *peer;
  3267. struct cdp_tid_tx_stats *tid_stats = NULL;
  3268. struct htt_soc *htt_handle;
  3269. /*
  3270. * If the descriptor is already freed in vdev_detach,
  3271. * continue to next descriptor
  3272. */
  3273. if (!tx_desc->vdev && !tx_desc->flags) {
  3274. QDF_TRACE(QDF_MODULE_ID_DP,
  3275. QDF_TRACE_LEVEL_INFO,
  3276. "Descriptor freed in vdev_detach %d",
  3277. tx_desc->id);
  3278. return;
  3279. }
  3280. pdev = tx_desc->pdev;
  3281. soc = pdev->soc;
  3282. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3283. QDF_TRACE(QDF_MODULE_ID_DP,
  3284. QDF_TRACE_LEVEL_INFO,
  3285. "pdev in down state %d",
  3286. tx_desc->id);
  3287. dp_tx_comp_free_buf(soc, tx_desc);
  3288. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3289. return;
  3290. }
  3291. qdf_assert(tx_desc->pdev);
  3292. vdev = tx_desc->vdev;
  3293. if (!vdev)
  3294. return;
  3295. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  3296. htt_handle = (struct htt_soc *)soc->htt_handle;
  3297. htt_wbm_event_record(htt_handle->htt_logger_handle, tx_status, status);
  3298. switch (tx_status) {
  3299. case HTT_TX_FW2WBM_TX_STATUS_OK:
  3300. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  3301. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  3302. {
  3303. uint8_t tid;
  3304. if (HTT_TX_WBM_COMPLETION_V2_VALID_GET(htt_desc[2])) {
  3305. ts.peer_id =
  3306. HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(
  3307. htt_desc[2]);
  3308. ts.tid =
  3309. HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(
  3310. htt_desc[2]);
  3311. } else {
  3312. ts.peer_id = HTT_INVALID_PEER;
  3313. ts.tid = HTT_INVALID_TID;
  3314. }
  3315. ts.ppdu_id =
  3316. HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(
  3317. htt_desc[1]);
  3318. ts.ack_frame_rssi =
  3319. HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_GET(
  3320. htt_desc[1]);
  3321. ts.tsf = htt_desc[3];
  3322. ts.first_msdu = 1;
  3323. ts.last_msdu = 1;
  3324. tid = ts.tid;
  3325. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3326. tid = CDP_MAX_DATA_TIDS - 1;
  3327. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3328. if (qdf_unlikely(pdev->delay_stats_flag))
  3329. dp_tx_compute_delay(vdev, tx_desc, tid, ring_id);
  3330. if (tx_status < CDP_MAX_TX_HTT_STATUS) {
  3331. tid_stats->htt_status_cnt[tx_status]++;
  3332. }
  3333. peer = dp_peer_get_ref_by_id(soc, ts.peer_id,
  3334. DP_MOD_ID_TX_COMP);
  3335. dp_tx_comp_process_tx_status(soc, tx_desc, &ts, peer, ring_id);
  3336. dp_tx_comp_process_desc(soc, tx_desc, &ts, peer);
  3337. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3338. if (qdf_likely(peer))
  3339. dp_peer_unref_delete(peer, DP_MOD_ID_TX_COMP);
  3340. break;
  3341. }
  3342. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  3343. {
  3344. dp_tx_reinject_handler(tx_desc, status);
  3345. break;
  3346. }
  3347. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  3348. {
  3349. dp_tx_inspect_handler(tx_desc, status);
  3350. break;
  3351. }
  3352. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  3353. {
  3354. dp_tx_mec_handler(vdev, status);
  3355. break;
  3356. }
  3357. default:
  3358. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  3359. "%s Invalid HTT tx_status %d\n",
  3360. __func__, tx_status);
  3361. break;
  3362. }
  3363. }
  3364. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  3365. static inline
  3366. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3367. {
  3368. bool limit_hit = false;
  3369. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  3370. limit_hit =
  3371. (num_reaped >= cfg->tx_comp_loop_pkt_limit) ? true : false;
  3372. if (limit_hit)
  3373. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  3374. return limit_hit;
  3375. }
  3376. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3377. {
  3378. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  3379. }
  3380. #else
  3381. static inline
  3382. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped)
  3383. {
  3384. return false;
  3385. }
  3386. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  3387. {
  3388. return false;
  3389. }
  3390. #endif
  3391. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  3392. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  3393. uint32_t quota)
  3394. {
  3395. void *tx_comp_hal_desc;
  3396. uint8_t buffer_src;
  3397. uint8_t pool_id;
  3398. uint32_t tx_desc_id;
  3399. struct dp_tx_desc_s *tx_desc = NULL;
  3400. struct dp_tx_desc_s *head_desc = NULL;
  3401. struct dp_tx_desc_s *tail_desc = NULL;
  3402. uint32_t num_processed = 0;
  3403. uint32_t count;
  3404. uint32_t num_avail_for_reap = 0;
  3405. bool force_break = false;
  3406. DP_HIST_INIT();
  3407. more_data:
  3408. /* Re-initialize local variables to be re-used */
  3409. head_desc = NULL;
  3410. tail_desc = NULL;
  3411. count = 0;
  3412. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  3413. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  3414. return 0;
  3415. }
  3416. num_avail_for_reap = hal_srng_dst_num_valid(soc->hal_soc, hal_ring_hdl, 0);
  3417. if (num_avail_for_reap >= quota)
  3418. num_avail_for_reap = quota;
  3419. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  3420. /* Find head descriptor from completion ring */
  3421. while (qdf_likely(num_avail_for_reap)) {
  3422. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  3423. if (qdf_unlikely(!tx_comp_hal_desc))
  3424. break;
  3425. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  3426. /* If this buffer was not released by TQM or FW, then it is not
  3427. * Tx completion indication, assert */
  3428. if (qdf_unlikely(buffer_src !=
  3429. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  3430. (qdf_unlikely(buffer_src !=
  3431. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  3432. uint8_t wbm_internal_error;
  3433. dp_err_rl(
  3434. "Tx comp release_src != TQM | FW but from %d",
  3435. buffer_src);
  3436. hal_dump_comp_desc(tx_comp_hal_desc);
  3437. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  3438. /* When WBM sees NULL buffer_addr_info in any of
  3439. * ingress rings it sends an error indication,
  3440. * with wbm_internal_error=1, to a specific ring.
  3441. * The WBM2SW ring used to indicate these errors is
  3442. * fixed in HW, and that ring is being used as Tx
  3443. * completion ring. These errors are not related to
  3444. * Tx completions, and should just be ignored
  3445. */
  3446. wbm_internal_error = hal_get_wbm_internal_error(
  3447. soc->hal_soc,
  3448. tx_comp_hal_desc);
  3449. if (wbm_internal_error) {
  3450. dp_err_rl("Tx comp wbm_internal_error!!");
  3451. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  3452. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  3453. buffer_src)
  3454. dp_handle_wbm_internal_error(
  3455. soc,
  3456. tx_comp_hal_desc,
  3457. hal_tx_comp_get_buffer_type(
  3458. tx_comp_hal_desc));
  3459. } else {
  3460. dp_err_rl("Tx comp wbm_internal_error false");
  3461. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  3462. }
  3463. continue;
  3464. }
  3465. /* Get descriptor id */
  3466. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  3467. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  3468. DP_TX_DESC_ID_POOL_OS;
  3469. /* Find Tx descriptor */
  3470. tx_desc = dp_tx_desc_find(soc, pool_id,
  3471. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  3472. DP_TX_DESC_ID_PAGE_OS,
  3473. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  3474. DP_TX_DESC_ID_OFFSET_OS);
  3475. /*
  3476. * If the release source is FW, process the HTT status
  3477. */
  3478. if (qdf_unlikely(buffer_src ==
  3479. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  3480. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  3481. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  3482. htt_tx_status);
  3483. dp_tx_process_htt_completion(tx_desc,
  3484. htt_tx_status, ring_id);
  3485. } else {
  3486. /*
  3487. * If the fast completion mode is enabled extended
  3488. * metadata from descriptor is not copied
  3489. */
  3490. if (qdf_likely(tx_desc->flags &
  3491. DP_TX_DESC_FLAG_SIMPLE)) {
  3492. tx_desc->peer_id =
  3493. hal_tx_comp_get_peer_id(tx_comp_hal_desc);
  3494. tx_desc->tx_status =
  3495. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  3496. goto add_to_pool;
  3497. }
  3498. /*
  3499. * If the descriptor is already freed in vdev_detach,
  3500. * continue to next descriptor
  3501. */
  3502. if (qdf_unlikely(!tx_desc->vdev) &&
  3503. qdf_unlikely(!tx_desc->flags)) {
  3504. QDF_TRACE(QDF_MODULE_ID_DP,
  3505. QDF_TRACE_LEVEL_INFO,
  3506. "Descriptor freed in vdev_detach %d",
  3507. tx_desc_id);
  3508. continue;
  3509. }
  3510. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  3511. QDF_TRACE(QDF_MODULE_ID_DP,
  3512. QDF_TRACE_LEVEL_INFO,
  3513. "pdev in down state %d",
  3514. tx_desc_id);
  3515. dp_tx_comp_free_buf(soc, tx_desc);
  3516. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3517. goto next_desc;
  3518. }
  3519. /* Pool id is not matching. Error */
  3520. if (tx_desc->pool_id != pool_id) {
  3521. QDF_TRACE(QDF_MODULE_ID_DP,
  3522. QDF_TRACE_LEVEL_FATAL,
  3523. "Tx Comp pool id %d not matched %d",
  3524. pool_id, tx_desc->pool_id);
  3525. qdf_assert_always(0);
  3526. }
  3527. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  3528. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  3529. QDF_TRACE(QDF_MODULE_ID_DP,
  3530. QDF_TRACE_LEVEL_FATAL,
  3531. "Txdesc invalid, flgs = %x,id = %d",
  3532. tx_desc->flags, tx_desc_id);
  3533. qdf_assert_always(0);
  3534. }
  3535. /* Collect hw completion contents */
  3536. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  3537. &tx_desc->comp, 1);
  3538. add_to_pool:
  3539. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  3540. /* First ring descriptor on the cycle */
  3541. if (!head_desc) {
  3542. head_desc = tx_desc;
  3543. tail_desc = tx_desc;
  3544. }
  3545. tail_desc->next = tx_desc;
  3546. tx_desc->next = NULL;
  3547. tail_desc = tx_desc;
  3548. }
  3549. next_desc:
  3550. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  3551. /*
  3552. * Processed packet count is more than given quota
  3553. * stop to processing
  3554. */
  3555. count++;
  3556. if (dp_tx_comp_loop_pkt_limit_hit(soc, count))
  3557. break;
  3558. }
  3559. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  3560. /* Process the reaped descriptors */
  3561. if (head_desc)
  3562. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  3563. if (dp_tx_comp_enable_eol_data_check(soc)) {
  3564. if (num_processed >= quota)
  3565. force_break = true;
  3566. if (!force_break &&
  3567. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  3568. hal_ring_hdl)) {
  3569. DP_STATS_INC(soc, tx.hp_oos2, 1);
  3570. if (!hif_exec_should_yield(soc->hif_handle,
  3571. int_ctx->dp_intr_id))
  3572. goto more_data;
  3573. }
  3574. }
  3575. DP_TX_HIST_STATS_PER_PDEV();
  3576. return num_processed;
  3577. }
  3578. #ifdef FEATURE_WLAN_TDLS
  3579. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3580. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  3581. {
  3582. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3583. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id);
  3584. if (!vdev) {
  3585. dp_err("vdev handle for id %d is NULL", vdev_id);
  3586. return NULL;
  3587. }
  3588. if (tx_spec & OL_TX_SPEC_NO_FREE)
  3589. vdev->is_tdls_frame = true;
  3590. dp_vdev_unref_delete(soc, vdev);
  3591. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  3592. }
  3593. #endif
  3594. static void dp_tx_vdev_update_feature_flags(struct dp_vdev *vdev)
  3595. {
  3596. struct wlan_cfg_dp_soc_ctxt *cfg;
  3597. struct dp_soc *soc;
  3598. soc = vdev->pdev->soc;
  3599. if (!soc)
  3600. return;
  3601. cfg = soc->wlan_cfg_ctx;
  3602. if (!cfg)
  3603. return;
  3604. if (vdev->opmode == wlan_op_mode_ndi)
  3605. vdev->csum_enabled = wlan_cfg_get_nan_checksum_offload(cfg);
  3606. else if ((vdev->subtype == wlan_op_subtype_p2p_device) ||
  3607. (vdev->subtype == wlan_op_subtype_p2p_cli) ||
  3608. (vdev->subtype == wlan_op_subtype_p2p_go))
  3609. vdev->csum_enabled = wlan_cfg_get_p2p_checksum_offload(cfg);
  3610. else
  3611. vdev->csum_enabled = wlan_cfg_get_checksum_offload(cfg);
  3612. }
  3613. /**
  3614. * dp_tx_vdev_attach() - attach vdev to dp tx
  3615. * @vdev: virtual device instance
  3616. *
  3617. * Return: QDF_STATUS_SUCCESS: success
  3618. * QDF_STATUS_E_RESOURCES: Error return
  3619. */
  3620. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  3621. {
  3622. int pdev_id;
  3623. /*
  3624. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  3625. */
  3626. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  3627. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  3628. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  3629. vdev->vdev_id);
  3630. pdev_id =
  3631. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  3632. vdev->pdev->pdev_id);
  3633. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  3634. /*
  3635. * Set HTT Extension Valid bit to 0 by default
  3636. */
  3637. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  3638. dp_tx_vdev_update_search_flags(vdev);
  3639. dp_tx_vdev_update_feature_flags(vdev);
  3640. return QDF_STATUS_SUCCESS;
  3641. }
  3642. #ifndef FEATURE_WDS
  3643. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  3644. {
  3645. return false;
  3646. }
  3647. #endif
  3648. /**
  3649. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  3650. * @vdev: virtual device instance
  3651. *
  3652. * Return: void
  3653. *
  3654. */
  3655. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  3656. {
  3657. struct dp_soc *soc = vdev->pdev->soc;
  3658. /*
  3659. * Enable both AddrY (SA based search) and AddrX (Da based search)
  3660. * for TDLS link
  3661. *
  3662. * Enable AddrY (SA based search) only for non-WDS STA and
  3663. * ProxySTA VAP (in HKv1) modes.
  3664. *
  3665. * In all other VAP modes, only DA based search should be
  3666. * enabled
  3667. */
  3668. if (vdev->opmode == wlan_op_mode_sta &&
  3669. vdev->tdls_link_connected)
  3670. vdev->hal_desc_addr_search_flags =
  3671. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  3672. else if ((vdev->opmode == wlan_op_mode_sta) &&
  3673. !dp_tx_da_search_override(vdev))
  3674. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  3675. else
  3676. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  3677. /* Set search type only when peer map v2 messaging is enabled
  3678. * as we will have the search index (AST hash) only when v2 is
  3679. * enabled
  3680. */
  3681. if (soc->is_peer_map_unmap_v2 && vdev->opmode == wlan_op_mode_sta)
  3682. vdev->search_type = HAL_TX_ADDR_INDEX_SEARCH;
  3683. else
  3684. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  3685. }
  3686. static inline bool
  3687. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  3688. struct dp_vdev *vdev,
  3689. struct dp_tx_desc_s *tx_desc)
  3690. {
  3691. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  3692. return false;
  3693. /*
  3694. * if vdev is given, then only check whether desc
  3695. * vdev match. if vdev is NULL, then check whether
  3696. * desc pdev match.
  3697. */
  3698. return vdev ? (tx_desc->vdev == vdev) : (tx_desc->pdev == pdev);
  3699. }
  3700. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3701. /**
  3702. * dp_tx_desc_flush() - release resources associated
  3703. * to TX Desc
  3704. *
  3705. * @dp_pdev: Handle to DP pdev structure
  3706. * @vdev: virtual device instance
  3707. * NULL: no specific Vdev is required and check all allcated TX desc
  3708. * on this pdev.
  3709. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  3710. *
  3711. * @force_free:
  3712. * true: flush the TX desc.
  3713. * false: only reset the Vdev in each allocated TX desc
  3714. * that associated to current Vdev.
  3715. *
  3716. * This function will go through the TX desc pool to flush
  3717. * the outstanding TX data or reset Vdev to NULL in associated TX
  3718. * Desc.
  3719. */
  3720. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3721. bool force_free)
  3722. {
  3723. uint8_t i;
  3724. uint32_t j;
  3725. uint32_t num_desc, page_id, offset;
  3726. uint16_t num_desc_per_page;
  3727. struct dp_soc *soc = pdev->soc;
  3728. struct dp_tx_desc_s *tx_desc = NULL;
  3729. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3730. if (!vdev && !force_free) {
  3731. dp_err("Reset TX desc vdev, Vdev param is required!");
  3732. return;
  3733. }
  3734. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  3735. tx_desc_pool = &soc->tx_desc[i];
  3736. if (!(tx_desc_pool->pool_size) ||
  3737. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  3738. !(tx_desc_pool->desc_pages.cacheable_pages))
  3739. continue;
  3740. /*
  3741. * Add flow pool lock protection in case pool is freed
  3742. * due to all tx_desc is recycled when handle TX completion.
  3743. * this is not necessary when do force flush as:
  3744. * a. double lock will happen if dp_tx_desc_release is
  3745. * also trying to acquire it.
  3746. * b. dp interrupt has been disabled before do force TX desc
  3747. * flush in dp_pdev_deinit().
  3748. */
  3749. if (!force_free)
  3750. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  3751. num_desc = tx_desc_pool->pool_size;
  3752. num_desc_per_page =
  3753. tx_desc_pool->desc_pages.num_element_per_page;
  3754. for (j = 0; j < num_desc; j++) {
  3755. page_id = j / num_desc_per_page;
  3756. offset = j % num_desc_per_page;
  3757. if (qdf_unlikely(!(tx_desc_pool->
  3758. desc_pages.cacheable_pages)))
  3759. break;
  3760. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3761. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3762. /*
  3763. * Free TX desc if force free is
  3764. * required, otherwise only reset vdev
  3765. * in this TX desc.
  3766. */
  3767. if (force_free) {
  3768. dp_tx_comp_free_buf(soc, tx_desc);
  3769. dp_tx_desc_release(tx_desc, i);
  3770. } else {
  3771. tx_desc->vdev = NULL;
  3772. }
  3773. }
  3774. }
  3775. if (!force_free)
  3776. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  3777. }
  3778. }
  3779. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3780. /**
  3781. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  3782. *
  3783. * @soc: Handle to DP soc structure
  3784. * @tx_desc: pointer of one TX desc
  3785. * @desc_pool_id: TX Desc pool id
  3786. */
  3787. static inline void
  3788. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  3789. uint8_t desc_pool_id)
  3790. {
  3791. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  3792. tx_desc->vdev = NULL;
  3793. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  3794. }
  3795. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  3796. bool force_free)
  3797. {
  3798. uint8_t i, num_pool;
  3799. uint32_t j;
  3800. uint32_t num_desc, page_id, offset;
  3801. uint16_t num_desc_per_page;
  3802. struct dp_soc *soc = pdev->soc;
  3803. struct dp_tx_desc_s *tx_desc = NULL;
  3804. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  3805. if (!vdev && !force_free) {
  3806. dp_err("Reset TX desc vdev, Vdev param is required!");
  3807. return;
  3808. }
  3809. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  3810. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3811. for (i = 0; i < num_pool; i++) {
  3812. tx_desc_pool = &soc->tx_desc[i];
  3813. if (!tx_desc_pool->desc_pages.cacheable_pages)
  3814. continue;
  3815. num_desc_per_page =
  3816. tx_desc_pool->desc_pages.num_element_per_page;
  3817. for (j = 0; j < num_desc; j++) {
  3818. page_id = j / num_desc_per_page;
  3819. offset = j % num_desc_per_page;
  3820. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  3821. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  3822. if (force_free) {
  3823. dp_tx_comp_free_buf(soc, tx_desc);
  3824. dp_tx_desc_release(tx_desc, i);
  3825. } else {
  3826. dp_tx_desc_reset_vdev(soc, tx_desc,
  3827. i);
  3828. }
  3829. }
  3830. }
  3831. }
  3832. }
  3833. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3834. /**
  3835. * dp_tx_vdev_detach() - detach vdev from dp tx
  3836. * @vdev: virtual device instance
  3837. *
  3838. * Return: QDF_STATUS_SUCCESS: success
  3839. * QDF_STATUS_E_RESOURCES: Error return
  3840. */
  3841. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  3842. {
  3843. struct dp_pdev *pdev = vdev->pdev;
  3844. /* Reset TX desc associated to this Vdev as NULL */
  3845. dp_tx_desc_flush(pdev, vdev, false);
  3846. dp_tx_vdev_multipass_deinit(vdev);
  3847. return QDF_STATUS_SUCCESS;
  3848. }
  3849. /**
  3850. * dp_tx_pdev_attach() - attach pdev to dp tx
  3851. * @pdev: physical device instance
  3852. *
  3853. * Return: QDF_STATUS_SUCCESS: success
  3854. * QDF_STATUS_E_RESOURCES: Error return
  3855. */
  3856. QDF_STATUS dp_tx_pdev_init(struct dp_pdev *pdev)
  3857. {
  3858. struct dp_soc *soc = pdev->soc;
  3859. /* Initialize Flow control counters */
  3860. qdf_atomic_init(&pdev->num_tx_outstanding);
  3861. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  3862. /* Initialize descriptors in TCL Ring */
  3863. hal_tx_init_data_ring(soc->hal_soc,
  3864. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  3865. }
  3866. return QDF_STATUS_SUCCESS;
  3867. }
  3868. /**
  3869. * dp_tx_pdev_detach() - detach pdev from dp tx
  3870. * @pdev: physical device instance
  3871. *
  3872. * Return: QDF_STATUS_SUCCESS: success
  3873. * QDF_STATUS_E_RESOURCES: Error return
  3874. */
  3875. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  3876. {
  3877. /* flush TX outstanding data per pdev */
  3878. dp_tx_desc_flush(pdev, NULL, true);
  3879. dp_tx_me_exit(pdev);
  3880. return QDF_STATUS_SUCCESS;
  3881. }
  3882. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  3883. /* Pools will be allocated dynamically */
  3884. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3885. int num_desc)
  3886. {
  3887. uint8_t i;
  3888. for (i = 0; i < num_pool; i++) {
  3889. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  3890. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  3891. }
  3892. return QDF_STATUS_SUCCESS;
  3893. }
  3894. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3895. int num_desc)
  3896. {
  3897. return QDF_STATUS_SUCCESS;
  3898. }
  3899. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  3900. {
  3901. }
  3902. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3903. {
  3904. uint8_t i;
  3905. for (i = 0; i < num_pool; i++)
  3906. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  3907. }
  3908. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  3909. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  3910. int num_desc)
  3911. {
  3912. uint8_t i, count;
  3913. /* Allocate software Tx descriptor pools */
  3914. for (i = 0; i < num_pool; i++) {
  3915. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  3916. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3917. FL("Tx Desc Pool alloc %d failed %pK"),
  3918. i, soc);
  3919. goto fail;
  3920. }
  3921. }
  3922. return QDF_STATUS_SUCCESS;
  3923. fail:
  3924. for (count = 0; count < i; count++)
  3925. dp_tx_desc_pool_free(soc, count);
  3926. return QDF_STATUS_E_NOMEM;
  3927. }
  3928. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  3929. int num_desc)
  3930. {
  3931. uint8_t i;
  3932. for (i = 0; i < num_pool; i++) {
  3933. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  3934. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3935. FL("Tx Desc Pool init %d failed %pK"),
  3936. i, soc);
  3937. return QDF_STATUS_E_NOMEM;
  3938. }
  3939. }
  3940. return QDF_STATUS_SUCCESS;
  3941. }
  3942. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  3943. {
  3944. uint8_t i;
  3945. for (i = 0; i < num_pool; i++)
  3946. dp_tx_desc_pool_deinit(soc, i);
  3947. }
  3948. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  3949. {
  3950. uint8_t i;
  3951. for (i = 0; i < num_pool; i++)
  3952. dp_tx_desc_pool_free(soc, i);
  3953. }
  3954. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  3955. /**
  3956. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  3957. * @soc: core txrx main context
  3958. * @num_pool: number of pools
  3959. *
  3960. */
  3961. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  3962. {
  3963. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  3964. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  3965. }
  3966. /**
  3967. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  3968. * @soc: core txrx main context
  3969. * @num_pool: number of pools
  3970. *
  3971. */
  3972. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  3973. {
  3974. dp_tx_tso_desc_pool_free(soc, num_pool);
  3975. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  3976. }
  3977. /**
  3978. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  3979. * @soc: core txrx main context
  3980. *
  3981. * This function frees all tx related descriptors as below
  3982. * 1. Regular TX descriptors (static pools)
  3983. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  3984. * 3. TSO descriptors
  3985. *
  3986. */
  3987. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  3988. {
  3989. uint8_t num_pool;
  3990. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  3991. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  3992. dp_tx_ext_desc_pool_free(soc, num_pool);
  3993. dp_tx_delete_static_pools(soc, num_pool);
  3994. }
  3995. /**
  3996. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  3997. * @soc: core txrx main context
  3998. *
  3999. * This function de-initializes all tx related descriptors as below
  4000. * 1. Regular TX descriptors (static pools)
  4001. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  4002. * 3. TSO descriptors
  4003. *
  4004. */
  4005. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  4006. {
  4007. uint8_t num_pool;
  4008. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4009. dp_tx_flow_control_deinit(soc);
  4010. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4011. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4012. dp_tx_deinit_static_pools(soc, num_pool);
  4013. }
  4014. /**
  4015. * dp_tso_attach() - TSO attach handler
  4016. * @txrx_soc: Opaque Dp handle
  4017. *
  4018. * Reserve TSO descriptor buffers
  4019. *
  4020. * Return: QDF_STATUS_E_FAILURE on failure or
  4021. * QDF_STATUS_SUCCESS on success
  4022. */
  4023. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  4024. uint8_t num_pool,
  4025. uint16_t num_desc)
  4026. {
  4027. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  4028. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4029. return QDF_STATUS_E_FAILURE;
  4030. }
  4031. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  4032. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4033. num_pool, soc);
  4034. return QDF_STATUS_E_FAILURE;
  4035. }
  4036. return QDF_STATUS_SUCCESS;
  4037. }
  4038. /**
  4039. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  4040. * @soc: DP soc handle
  4041. * @num_pool: Number of pools
  4042. * @num_desc: Number of descriptors
  4043. *
  4044. * Initialize TSO descriptor pools
  4045. *
  4046. * Return: QDF_STATUS_E_FAILURE on failure or
  4047. * QDF_STATUS_SUCCESS on success
  4048. */
  4049. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  4050. uint8_t num_pool,
  4051. uint16_t num_desc)
  4052. {
  4053. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  4054. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  4055. return QDF_STATUS_E_FAILURE;
  4056. }
  4057. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  4058. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  4059. num_pool, soc);
  4060. return QDF_STATUS_E_FAILURE;
  4061. }
  4062. return QDF_STATUS_SUCCESS;
  4063. }
  4064. /**
  4065. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  4066. * @soc: core txrx main context
  4067. *
  4068. * This function allocates memory for following descriptor pools
  4069. * 1. regular sw tx descriptor pools (static pools)
  4070. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4071. * 3. TSO descriptor pools
  4072. *
  4073. * Return: QDF_STATUS_SUCCESS: success
  4074. * QDF_STATUS_E_RESOURCES: Error return
  4075. */
  4076. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  4077. {
  4078. uint8_t num_pool;
  4079. uint32_t num_desc;
  4080. uint32_t num_ext_desc;
  4081. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4082. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4083. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4084. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4085. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  4086. __func__, num_pool, num_desc);
  4087. if ((num_pool > MAX_TXDESC_POOLS) ||
  4088. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  4089. goto fail1;
  4090. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  4091. goto fail1;
  4092. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4093. goto fail2;
  4094. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4095. return QDF_STATUS_SUCCESS;
  4096. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4097. goto fail3;
  4098. return QDF_STATUS_SUCCESS;
  4099. fail3:
  4100. dp_tx_ext_desc_pool_free(soc, num_pool);
  4101. fail2:
  4102. dp_tx_delete_static_pools(soc, num_pool);
  4103. fail1:
  4104. return QDF_STATUS_E_RESOURCES;
  4105. }
  4106. /**
  4107. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  4108. * @soc: core txrx main context
  4109. *
  4110. * This function initializes the following TX descriptor pools
  4111. * 1. regular sw tx descriptor pools (static pools)
  4112. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  4113. * 3. TSO descriptor pools
  4114. *
  4115. * Return: QDF_STATUS_SUCCESS: success
  4116. * QDF_STATUS_E_RESOURCES: Error return
  4117. */
  4118. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  4119. {
  4120. uint8_t num_pool;
  4121. uint32_t num_desc;
  4122. uint32_t num_ext_desc;
  4123. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4124. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4125. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4126. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  4127. goto fail1;
  4128. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  4129. goto fail2;
  4130. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  4131. return QDF_STATUS_SUCCESS;
  4132. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4133. goto fail3;
  4134. dp_tx_flow_control_init(soc);
  4135. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  4136. return QDF_STATUS_SUCCESS;
  4137. fail3:
  4138. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  4139. fail2:
  4140. dp_tx_deinit_static_pools(soc, num_pool);
  4141. fail1:
  4142. return QDF_STATUS_E_RESOURCES;
  4143. }
  4144. /**
  4145. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  4146. * @txrx_soc: dp soc handle
  4147. *
  4148. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4149. * QDF_STATUS_E_FAILURE
  4150. */
  4151. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  4152. {
  4153. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4154. uint8_t num_pool;
  4155. uint32_t num_desc;
  4156. uint32_t num_ext_desc;
  4157. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4158. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  4159. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  4160. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  4161. return QDF_STATUS_E_FAILURE;
  4162. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  4163. return QDF_STATUS_E_FAILURE;
  4164. return QDF_STATUS_SUCCESS;
  4165. }
  4166. /**
  4167. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  4168. * @txrx_soc: dp soc handle
  4169. *
  4170. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  4171. */
  4172. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  4173. {
  4174. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  4175. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  4176. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  4177. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  4178. return QDF_STATUS_SUCCESS;
  4179. }