sde_power_handle.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #define pr_fmt(fmt) "[drm:%s:%d]: " fmt, __func__, __LINE__
  6. #include <linux/clk.h>
  7. #include <linux/kernel.h>
  8. #include <linux/of.h>
  9. #include <linux/string.h>
  10. #include <linux/of_address.h>
  11. #include <linux/slab.h>
  12. #include <linux/mutex.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/sde_io_util.h>
  15. #include <linux/sde_rsc.h>
  16. #include "sde_power_handle.h"
  17. #include "sde_trace.h"
  18. #include "sde_dbg.h"
  19. static const struct sde_power_bus_scaling_data sde_reg_bus_table[] = {
  20. {0, 0},
  21. {0, 76800},
  22. {0, 150000},
  23. {0, 300000},
  24. };
  25. static const char *data_bus_name[SDE_POWER_HANDLE_DBUS_ID_MAX] = {
  26. [SDE_POWER_HANDLE_DBUS_ID_MNOC] = "qcom,sde-data-bus",
  27. [SDE_POWER_HANDLE_DBUS_ID_LLCC] = "qcom,sde-llcc-bus",
  28. [SDE_POWER_HANDLE_DBUS_ID_EBI] = "qcom,sde-ebi-bus",
  29. };
  30. const char *sde_power_handle_get_dbus_name(u32 bus_id)
  31. {
  32. if (bus_id < SDE_POWER_HANDLE_DBUS_ID_MAX)
  33. return data_bus_name[bus_id];
  34. return NULL;
  35. }
  36. static void sde_power_event_trigger_locked(struct sde_power_handle *phandle,
  37. u32 event_type)
  38. {
  39. struct sde_power_event *event;
  40. phandle->last_event_handled = event_type;
  41. list_for_each_entry(event, &phandle->event_list, list) {
  42. if (event->event_type & event_type) {
  43. event->cb_fnc(event_type, event->usr);
  44. }
  45. }
  46. }
  47. static inline void sde_power_rsc_client_init(struct sde_power_handle *phandle)
  48. {
  49. /* creates the rsc client */
  50. if (!phandle->rsc_client_init) {
  51. phandle->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX,
  52. "sde_power_handle", SDE_RSC_CLK_CLIENT, 0);
  53. if (IS_ERR_OR_NULL(phandle->rsc_client)) {
  54. pr_debug("sde rsc client create failed :%ld\n",
  55. PTR_ERR(phandle->rsc_client));
  56. phandle->rsc_client = NULL;
  57. }
  58. phandle->rsc_client_init = true;
  59. }
  60. }
  61. static int sde_power_rsc_update(struct sde_power_handle *phandle, bool enable)
  62. {
  63. u32 rsc_state;
  64. int ret = 0;
  65. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  66. if (phandle->rsc_client)
  67. ret = sde_rsc_client_state_update(phandle->rsc_client,
  68. rsc_state, NULL, SDE_RSC_INVALID_CRTC_ID, NULL);
  69. return ret;
  70. }
  71. static int sde_power_parse_dt_supply(struct platform_device *pdev,
  72. struct dss_module_power *mp)
  73. {
  74. int i = 0, rc = 0;
  75. u32 tmp = 0;
  76. struct device_node *of_node = NULL, *supply_root_node = NULL;
  77. struct device_node *supply_node = NULL;
  78. if (!pdev || !mp) {
  79. pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
  80. return -EINVAL;
  81. }
  82. of_node = pdev->dev.of_node;
  83. mp->num_vreg = 0;
  84. supply_root_node = of_get_child_by_name(of_node,
  85. "qcom,platform-supply-entries");
  86. if (!supply_root_node) {
  87. pr_debug("no supply entry present\n");
  88. return rc;
  89. }
  90. for_each_child_of_node(supply_root_node, supply_node)
  91. mp->num_vreg++;
  92. if (mp->num_vreg == 0) {
  93. pr_debug("no vreg\n");
  94. return rc;
  95. }
  96. pr_debug("vreg found. count=%d\n", mp->num_vreg);
  97. mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) *
  98. mp->num_vreg, GFP_KERNEL);
  99. if (!mp->vreg_config) {
  100. rc = -ENOMEM;
  101. return rc;
  102. }
  103. for_each_child_of_node(supply_root_node, supply_node) {
  104. const char *st = NULL;
  105. rc = of_property_read_string(supply_node,
  106. "qcom,supply-name", &st);
  107. if (rc) {
  108. pr_err("error reading name. rc=%d\n", rc);
  109. goto error;
  110. }
  111. strlcpy(mp->vreg_config[i].vreg_name, st,
  112. sizeof(mp->vreg_config[i].vreg_name));
  113. rc = of_property_read_u32(supply_node,
  114. "qcom,supply-min-voltage", &tmp);
  115. if (rc) {
  116. pr_err("error reading min volt. rc=%d\n", rc);
  117. goto error;
  118. }
  119. mp->vreg_config[i].min_voltage = tmp;
  120. rc = of_property_read_u32(supply_node,
  121. "qcom,supply-max-voltage", &tmp);
  122. if (rc) {
  123. pr_err("error reading max volt. rc=%d\n", rc);
  124. goto error;
  125. }
  126. mp->vreg_config[i].max_voltage = tmp;
  127. rc = of_property_read_u32(supply_node,
  128. "qcom,supply-enable-load", &tmp);
  129. if (rc) {
  130. pr_err("error reading enable load. rc=%d\n", rc);
  131. goto error;
  132. }
  133. mp->vreg_config[i].enable_load = tmp;
  134. rc = of_property_read_u32(supply_node,
  135. "qcom,supply-disable-load", &tmp);
  136. if (rc) {
  137. pr_err("error reading disable load. rc=%d\n", rc);
  138. goto error;
  139. }
  140. mp->vreg_config[i].disable_load = tmp;
  141. rc = of_property_read_u32(supply_node,
  142. "qcom,supply-pre-on-sleep", &tmp);
  143. if (rc)
  144. pr_debug("error reading supply pre sleep value. rc=%d\n",
  145. rc);
  146. mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0);
  147. rc = of_property_read_u32(supply_node,
  148. "qcom,supply-pre-off-sleep", &tmp);
  149. if (rc)
  150. pr_debug("error reading supply pre sleep value. rc=%d\n",
  151. rc);
  152. mp->vreg_config[i].pre_off_sleep = (!rc ? tmp : 0);
  153. rc = of_property_read_u32(supply_node,
  154. "qcom,supply-post-on-sleep", &tmp);
  155. if (rc)
  156. pr_debug("error reading supply post sleep value. rc=%d\n",
  157. rc);
  158. mp->vreg_config[i].post_on_sleep = (!rc ? tmp : 0);
  159. rc = of_property_read_u32(supply_node,
  160. "qcom,supply-post-off-sleep", &tmp);
  161. if (rc)
  162. pr_debug("error reading supply post sleep value. rc=%d\n",
  163. rc);
  164. mp->vreg_config[i].post_off_sleep = (!rc ? tmp : 0);
  165. pr_debug("%s min=%d, max=%d, enable=%d, disable=%d, preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d\n",
  166. mp->vreg_config[i].vreg_name,
  167. mp->vreg_config[i].min_voltage,
  168. mp->vreg_config[i].max_voltage,
  169. mp->vreg_config[i].enable_load,
  170. mp->vreg_config[i].disable_load,
  171. mp->vreg_config[i].pre_on_sleep,
  172. mp->vreg_config[i].post_on_sleep,
  173. mp->vreg_config[i].pre_off_sleep,
  174. mp->vreg_config[i].post_off_sleep);
  175. ++i;
  176. rc = 0;
  177. }
  178. return rc;
  179. error:
  180. if (mp->vreg_config) {
  181. devm_kfree(&pdev->dev, mp->vreg_config);
  182. mp->vreg_config = NULL;
  183. mp->num_vreg = 0;
  184. }
  185. return rc;
  186. }
  187. static int sde_power_parse_dt_clock(struct platform_device *pdev,
  188. struct dss_module_power *mp)
  189. {
  190. u32 i = 0, rc = 0;
  191. const char *clock_name;
  192. u32 clock_rate = 0;
  193. u32 clock_max_rate = 0;
  194. int num_clk = 0;
  195. if (!pdev || !mp) {
  196. pr_err("invalid input param pdev:%pK mp:%pK\n", pdev, mp);
  197. return -EINVAL;
  198. }
  199. mp->num_clk = 0;
  200. num_clk = of_property_count_strings(pdev->dev.of_node,
  201. "clock-names");
  202. if (num_clk <= 0) {
  203. pr_debug("clocks are not defined\n");
  204. goto clk_err;
  205. }
  206. mp->num_clk = num_clk;
  207. mp->clk_config = devm_kzalloc(&pdev->dev,
  208. sizeof(struct dss_clk) * num_clk, GFP_KERNEL);
  209. if (!mp->clk_config) {
  210. rc = -ENOMEM;
  211. mp->num_clk = 0;
  212. goto clk_err;
  213. }
  214. for (i = 0; i < num_clk; i++) {
  215. of_property_read_string_index(pdev->dev.of_node, "clock-names",
  216. i, &clock_name);
  217. strlcpy(mp->clk_config[i].clk_name, clock_name,
  218. sizeof(mp->clk_config[i].clk_name));
  219. of_property_read_u32_index(pdev->dev.of_node, "clock-rate",
  220. i, &clock_rate);
  221. mp->clk_config[i].rate = clock_rate;
  222. if (!clock_rate)
  223. mp->clk_config[i].type = DSS_CLK_AHB;
  224. else
  225. mp->clk_config[i].type = DSS_CLK_PCLK;
  226. clock_max_rate = 0;
  227. of_property_read_u32_index(pdev->dev.of_node, "clock-max-rate",
  228. i, &clock_max_rate);
  229. mp->clk_config[i].max_rate = clock_max_rate;
  230. }
  231. clk_err:
  232. return rc;
  233. }
  234. #define MAX_AXI_PORT_COUNT 3
  235. static int _sde_power_data_bus_set_quota(
  236. struct sde_power_data_bus_handle *pdbus,
  237. u64 in_ab_quota, u64 in_ib_quota)
  238. {
  239. int rc = 0, i = 0;
  240. u32 paths = pdbus->data_paths_cnt;
  241. if (!paths || paths > DATA_BUS_PATH_MAX) {
  242. pr_err("invalid data bus handle, paths %d\n", paths);
  243. return -EINVAL;
  244. }
  245. in_ab_quota = div_u64(in_ab_quota, paths);
  246. SDE_ATRACE_BEGIN("msm_bus_scale_req");
  247. for (i = 0; i < paths; i++) {
  248. if (pdbus->data_bus_hdl[i]) {
  249. rc = icc_set_bw(pdbus->data_bus_hdl[i],
  250. Bps_to_icc(in_ab_quota),
  251. Bps_to_icc(in_ib_quota));
  252. if (rc)
  253. goto err;
  254. }
  255. }
  256. pdbus->curr_val.ab = in_ab_quota;
  257. pdbus->curr_val.ib = in_ib_quota;
  258. SDE_ATRACE_END("msm_bus_scale_req");
  259. return rc;
  260. err:
  261. for (; i >= 0; --i)
  262. if (pdbus->data_bus_hdl[i])
  263. icc_set_bw(pdbus->data_bus_hdl[i],
  264. Bps_to_icc(pdbus->curr_val.ab),
  265. Bps_to_icc(pdbus->curr_val.ib));
  266. SDE_ATRACE_END("msm_bus_scale_req");
  267. pr_err("failed to set data bus vote ab=%llu ib=%llu rc=%d\n",
  268. rc, in_ab_quota, in_ib_quota);
  269. return rc;
  270. }
  271. int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
  272. u32 bus_id, u64 ab_quota, u64 ib_quota)
  273. {
  274. int rc = 0;
  275. u32 paths;
  276. if (!phandle || bus_id >= SDE_POWER_HANDLE_DBUS_ID_MAX) {
  277. pr_err("invalid parameters\n");
  278. return -EINVAL;
  279. }
  280. paths = phandle->data_bus_handle[bus_id].data_paths_cnt;
  281. if (!paths)
  282. goto skip_vote;
  283. trace_sde_perf_update_bus(bus_id, ab_quota, ib_quota, paths);
  284. mutex_lock(&phandle->phandle_lock);
  285. rc = _sde_power_data_bus_set_quota(&phandle->data_bus_handle[bus_id],
  286. ab_quota, ib_quota);
  287. mutex_unlock(&phandle->phandle_lock);
  288. skip_vote:
  289. pr_debug("bus=%d, ab=%llu, ib=%llu, paths=%d\n", bus_id, ab_quota,
  290. ib_quota, paths);
  291. return rc;
  292. }
  293. /**
  294. * sde_power_icc_get - get the interconnect path for the given bus_name
  295. * @pdev - platform device
  296. * @bus_name - bus name for the corresponding interconnect
  297. * @path - the icc_path object we want to obtain for this @bus_name (output)
  298. * @count - if given, incremented only if the path was successfully retrieved
  299. **/
  300. static int sde_power_icc_get(struct platform_device *pdev,
  301. const char *bus_name, struct icc_path **path, u32 *count)
  302. {
  303. int rc = of_property_match_string(pdev->dev.of_node,
  304. "interconnect-names", bus_name);
  305. /* bus_names are optional for any given device node, skip if missing */
  306. if (rc < 0)
  307. goto end;
  308. *path = of_icc_get(&pdev->dev, bus_name);
  309. if (IS_ERR_OR_NULL(*path)) {
  310. rc = PTR_ERR(*path);
  311. pr_err("bus %s parsing failed, rc:%d\n", bus_name, rc);
  312. *path = NULL;
  313. return rc;
  314. }
  315. if (count)
  316. (*count)++;
  317. end:
  318. pr_debug("bus %s dt node %s(%d), icc_path is %s, count:%d\n",
  319. bus_name, rc < 0 ? "missing" : "found", rc,
  320. *path ? "valid" : "NULL", count ? *count : -1);
  321. return 0;
  322. }
  323. static int sde_power_mnoc_bus_parse(struct platform_device *pdev,
  324. struct sde_power_data_bus_handle *pdbus, const char *name)
  325. {
  326. int i, rc = 0;
  327. char bus_name[32];
  328. for (i = 0; i < DATA_BUS_PATH_MAX; ++i) {
  329. snprintf(bus_name, sizeof(bus_name), "%s%d", name, i);
  330. rc = sde_power_icc_get(pdev, bus_name, &pdbus->data_bus_hdl[i],
  331. &pdbus->data_paths_cnt);
  332. if (rc)
  333. break;
  334. }
  335. /* at least one databus path is required */
  336. if (!pdbus->data_paths_cnt) {
  337. pr_err("missing required interconnect:%s, rc:%d\n", name, rc);
  338. return -EINVAL;
  339. } else if (rc) {
  340. pr_info("ignoring error %d for non-primary data path\n", rc);
  341. rc = 0;
  342. }
  343. return rc;
  344. }
  345. static int sde_power_bus_parse(struct platform_device *pdev,
  346. struct sde_power_handle *phandle)
  347. {
  348. int i, j, rc = 0;
  349. bool active_only = false;
  350. const char *bus_name = "qcom,sde-reg-bus";
  351. struct sde_power_data_bus_handle *pdbus = phandle->data_bus_handle;
  352. /* reg bus */
  353. rc = sde_power_icc_get(pdev, bus_name, &phandle->reg_bus_hdl, NULL);
  354. if (rc)
  355. return rc;
  356. /* data buses */
  357. if (of_find_property(pdev->dev.of_node,
  358. "qcom,msm-bus,active-only", NULL))
  359. active_only = true;
  360. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  361. i < SDE_POWER_HANDLE_DBUS_ID_MAX; ++i) {
  362. if (i == SDE_POWER_HANDLE_DBUS_ID_MNOC)
  363. rc = sde_power_mnoc_bus_parse(pdev, &pdbus[i],
  364. data_bus_name[i]);
  365. else
  366. rc = sde_power_icc_get(pdev, data_bus_name[i],
  367. &pdbus[i].data_bus_hdl[0],
  368. &pdbus[i].data_paths_cnt);
  369. if (rc)
  370. break;
  371. if (active_only) {
  372. pdbus[i].bus_active_only = true;
  373. for (j = 0; j < pdbus[i].data_paths_cnt; ++j)
  374. icc_set_tag(pdbus[i].data_bus_hdl[j],
  375. QCOM_ICC_TAG_ACTIVE_ONLY);
  376. }
  377. pr_debug("found %d paths for %s\n", pdbus[i].data_paths_cnt,
  378. data_bus_name[i]);
  379. }
  380. return rc;
  381. }
  382. static void sde_power_bus_unregister(struct sde_power_handle *phandle)
  383. {
  384. int i, j;
  385. struct sde_power_data_bus_handle *pdbus = phandle->data_bus_handle;
  386. icc_put(phandle->reg_bus_hdl);
  387. phandle->reg_bus_hdl = NULL;
  388. for (i = SDE_POWER_HANDLE_DBUS_ID_MAX - 1;
  389. i >= SDE_POWER_HANDLE_DBUS_ID_MNOC; i--) {
  390. for (j = 0; j < pdbus[i].data_paths_cnt; j++) {
  391. if (pdbus[i].data_bus_hdl[j]) {
  392. icc_put(pdbus[i].data_bus_hdl[j]);
  393. pdbus[i].data_bus_hdl[j] = NULL;
  394. }
  395. }
  396. }
  397. }
  398. static int sde_power_reg_bus_update(struct icc_path *reg_bus_hdl,
  399. u32 usecase_ndx)
  400. {
  401. int rc = 0;
  402. if (reg_bus_hdl) {
  403. SDE_ATRACE_BEGIN("msm_bus_scale_req");
  404. rc = icc_set_bw(reg_bus_hdl,
  405. sde_reg_bus_table[usecase_ndx].ab,
  406. sde_reg_bus_table[usecase_ndx].ib);
  407. SDE_ATRACE_END("msm_bus_scale_req");
  408. }
  409. if (rc)
  410. pr_err("failed to set reg bus vote rc=%d\n", rc);
  411. return rc;
  412. }
  413. int sde_power_resource_init(struct platform_device *pdev,
  414. struct sde_power_handle *phandle)
  415. {
  416. int rc = 0;
  417. struct dss_module_power *mp;
  418. if (!phandle || !pdev) {
  419. pr_err("invalid input param\n");
  420. rc = -EINVAL;
  421. goto end;
  422. }
  423. mp = &phandle->mp;
  424. phandle->dev = &pdev->dev;
  425. rc = sde_power_parse_dt_clock(pdev, mp);
  426. if (rc) {
  427. pr_err("device clock parsing failed\n");
  428. goto end;
  429. }
  430. rc = sde_power_parse_dt_supply(pdev, mp);
  431. if (rc) {
  432. pr_err("device vreg supply parsing failed\n");
  433. goto parse_vreg_err;
  434. }
  435. rc = msm_dss_config_vreg(&pdev->dev,
  436. mp->vreg_config, mp->num_vreg, 1);
  437. if (rc) {
  438. pr_err("vreg config failed rc=%d\n", rc);
  439. goto vreg_err;
  440. }
  441. rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
  442. if (rc) {
  443. pr_err("clock get failed rc=%d\n", rc);
  444. goto clkget_err;
  445. }
  446. rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
  447. if (rc) {
  448. pr_err("clock set rate failed rc=%d\n", rc);
  449. goto clkset_err;
  450. }
  451. rc = sde_power_bus_parse(pdev, phandle);
  452. if (rc) {
  453. pr_err("bus parse failed rc=%d\n", rc);
  454. goto bus_err;
  455. }
  456. INIT_LIST_HEAD(&phandle->event_list);
  457. phandle->rsc_client = NULL;
  458. phandle->rsc_client_init = false;
  459. mutex_init(&phandle->phandle_lock);
  460. return rc;
  461. bus_err:
  462. sde_power_bus_unregister(phandle);
  463. clkset_err:
  464. msm_dss_put_clk(mp->clk_config, mp->num_clk);
  465. clkget_err:
  466. msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
  467. vreg_err:
  468. if (mp->vreg_config)
  469. devm_kfree(&pdev->dev, mp->vreg_config);
  470. mp->num_vreg = 0;
  471. parse_vreg_err:
  472. if (mp->clk_config)
  473. devm_kfree(&pdev->dev, mp->clk_config);
  474. mp->num_clk = 0;
  475. end:
  476. return rc;
  477. }
  478. void sde_power_resource_deinit(struct platform_device *pdev,
  479. struct sde_power_handle *phandle)
  480. {
  481. struct dss_module_power *mp;
  482. struct sde_power_event *curr_event, *next_event;
  483. if (!phandle || !pdev) {
  484. pr_err("invalid input param\n");
  485. return;
  486. }
  487. mp = &phandle->mp;
  488. mutex_lock(&phandle->phandle_lock);
  489. list_for_each_entry_safe(curr_event, next_event,
  490. &phandle->event_list, list) {
  491. pr_err("event:%d, client:%s still registered\n",
  492. curr_event->event_type,
  493. curr_event->client_name);
  494. curr_event->active = false;
  495. list_del(&curr_event->list);
  496. }
  497. mutex_unlock(&phandle->phandle_lock);
  498. sde_power_bus_unregister(phandle);
  499. msm_dss_put_clk(mp->clk_config, mp->num_clk);
  500. msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
  501. if (mp->clk_config)
  502. devm_kfree(&pdev->dev, mp->clk_config);
  503. if (mp->vreg_config)
  504. devm_kfree(&pdev->dev, mp->vreg_config);
  505. mp->num_vreg = 0;
  506. mp->num_clk = 0;
  507. if (phandle->rsc_client)
  508. sde_rsc_client_destroy(phandle->rsc_client);
  509. }
  510. int sde_power_scale_reg_bus(struct sde_power_handle *phandle,
  511. u32 usecase_ndx, bool skip_lock)
  512. {
  513. int rc = 0;
  514. if (!skip_lock)
  515. mutex_lock(&phandle->phandle_lock);
  516. pr_debug("%pS: requested:%d\n",
  517. __builtin_return_address(0), usecase_ndx);
  518. rc = sde_power_reg_bus_update(phandle->reg_bus_hdl,
  519. usecase_ndx);
  520. if (rc)
  521. pr_err("failed to set reg bus vote rc=%d\n", rc);
  522. else {
  523. phandle->reg_bus_curr_val.ab =
  524. sde_reg_bus_table[usecase_ndx].ab;
  525. phandle->reg_bus_curr_val.ib =
  526. sde_reg_bus_table[usecase_ndx].ib;
  527. phandle->current_usecase_ndx = usecase_ndx;
  528. }
  529. if (!skip_lock)
  530. mutex_unlock(&phandle->phandle_lock);
  531. return rc;
  532. }
  533. static inline bool _resource_changed(u32 current_usecase_ndx,
  534. u32 max_usecase_ndx)
  535. {
  536. WARN_ON((current_usecase_ndx >= VOTE_INDEX_MAX)
  537. || (max_usecase_ndx >= VOTE_INDEX_MAX));
  538. if (((current_usecase_ndx >= VOTE_INDEX_LOW) && /* enabled */
  539. (max_usecase_ndx == VOTE_INDEX_DISABLE)) || /* max disabled */
  540. ((current_usecase_ndx == VOTE_INDEX_DISABLE) && /* disabled */
  541. (max_usecase_ndx >= VOTE_INDEX_LOW))) /* max enabled */
  542. return true;
  543. return false;
  544. }
  545. int sde_power_resource_enable(struct sde_power_handle *phandle, bool enable)
  546. {
  547. int rc = 0, i = 0;
  548. struct dss_module_power *mp;
  549. if (!phandle) {
  550. pr_err("invalid input argument\n");
  551. return -EINVAL;
  552. }
  553. mp = &phandle->mp;
  554. mutex_lock(&phandle->phandle_lock);
  555. pr_debug("enable:%d\n", enable);
  556. SDE_ATRACE_BEGIN("sde_power_resource_enable");
  557. /* RSC client init */
  558. sde_power_rsc_client_init(phandle);
  559. if (enable) {
  560. sde_power_event_trigger_locked(phandle,
  561. SDE_POWER_EVENT_PRE_ENABLE);
  562. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX &&
  563. phandle->data_bus_handle[i].data_paths_cnt > 0; i++) {
  564. rc = _sde_power_data_bus_set_quota(
  565. &phandle->data_bus_handle[i],
  566. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  567. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  568. if (rc) {
  569. pr_err("failed to set data bus vote id=%d rc=%d\n",
  570. i, rc);
  571. goto vreg_err;
  572. }
  573. }
  574. rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg,
  575. enable);
  576. if (rc) {
  577. pr_err("failed to enable vregs rc=%d\n", rc);
  578. goto vreg_err;
  579. }
  580. rc = sde_power_scale_reg_bus(phandle, VOTE_INDEX_LOW, true);
  581. if (rc) {
  582. pr_err("failed to set reg bus vote rc=%d\n", rc);
  583. goto reg_bus_hdl_err;
  584. }
  585. SDE_EVT32_VERBOSE(enable, SDE_EVTLOG_FUNC_CASE1);
  586. rc = sde_power_rsc_update(phandle, true);
  587. if (rc) {
  588. pr_err("failed to update rsc\n");
  589. goto rsc_err;
  590. }
  591. rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
  592. if (rc) {
  593. pr_err("clock enable failed rc:%d\n", rc);
  594. goto clk_err;
  595. }
  596. sde_power_event_trigger_locked(phandle,
  597. SDE_POWER_EVENT_POST_ENABLE);
  598. } else {
  599. sde_power_event_trigger_locked(phandle,
  600. SDE_POWER_EVENT_PRE_DISABLE);
  601. SDE_EVT32_VERBOSE(enable, SDE_EVTLOG_FUNC_CASE2);
  602. sde_power_rsc_update(phandle, false);
  603. msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
  604. sde_power_scale_reg_bus(phandle, VOTE_INDEX_DISABLE, true);
  605. msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
  606. for (i = SDE_POWER_HANDLE_DBUS_ID_MAX - 1; i >= 0; i--)
  607. if (phandle->data_bus_handle[i].data_paths_cnt > 0)
  608. _sde_power_data_bus_set_quota(
  609. &phandle->data_bus_handle[i],
  610. SDE_POWER_HANDLE_DISABLE_BUS_AB_QUOTA,
  611. SDE_POWER_HANDLE_DISABLE_BUS_IB_QUOTA);
  612. sde_power_event_trigger_locked(phandle,
  613. SDE_POWER_EVENT_POST_DISABLE);
  614. }
  615. SDE_EVT32_VERBOSE(enable, SDE_EVTLOG_FUNC_EXIT);
  616. SDE_ATRACE_END("sde_power_resource_enable");
  617. mutex_unlock(&phandle->phandle_lock);
  618. return rc;
  619. clk_err:
  620. sde_power_rsc_update(phandle, false);
  621. rsc_err:
  622. sde_power_scale_reg_bus(phandle, VOTE_INDEX_DISABLE, true);
  623. reg_bus_hdl_err:
  624. msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0);
  625. vreg_err:
  626. for (i-- ; i >= 0 && phandle->data_bus_handle[i].data_paths_cnt > 0; i--)
  627. _sde_power_data_bus_set_quota(
  628. &phandle->data_bus_handle[i],
  629. SDE_POWER_HANDLE_DISABLE_BUS_AB_QUOTA,
  630. SDE_POWER_HANDLE_DISABLE_BUS_IB_QUOTA);
  631. SDE_ATRACE_END("sde_power_resource_enable");
  632. mutex_unlock(&phandle->phandle_lock);
  633. return rc;
  634. }
  635. int sde_power_clk_set_rate(struct sde_power_handle *phandle, char *clock_name,
  636. u64 rate)
  637. {
  638. int i, rc = -EINVAL;
  639. struct dss_module_power *mp;
  640. if (!phandle) {
  641. pr_err("invalid input power handle\n");
  642. return -EINVAL;
  643. }
  644. mutex_lock(&phandle->phandle_lock);
  645. if (phandle->last_event_handled & SDE_POWER_EVENT_POST_DISABLE) {
  646. pr_debug("invalid power state %u\n",
  647. phandle->last_event_handled);
  648. SDE_EVT32(phandle->last_event_handled, SDE_EVTLOG_ERROR);
  649. mutex_unlock(&phandle->phandle_lock);
  650. return -EINVAL;
  651. }
  652. mp = &phandle->mp;
  653. for (i = 0; i < mp->num_clk; i++) {
  654. if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
  655. if (mp->clk_config[i].max_rate &&
  656. (rate > mp->clk_config[i].max_rate))
  657. rate = mp->clk_config[i].max_rate;
  658. mp->clk_config[i].rate = rate;
  659. rc = msm_dss_single_clk_set_rate(&mp->clk_config[i]);
  660. break;
  661. }
  662. }
  663. mutex_unlock(&phandle->phandle_lock);
  664. return rc;
  665. }
  666. u64 sde_power_clk_get_rate(struct sde_power_handle *phandle, char *clock_name)
  667. {
  668. int i;
  669. struct dss_module_power *mp;
  670. u64 rate = -EINVAL;
  671. if (!phandle) {
  672. pr_err("invalid input power handle\n");
  673. return -EINVAL;
  674. }
  675. mp = &phandle->mp;
  676. for (i = 0; i < mp->num_clk; i++) {
  677. if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
  678. rate = clk_get_rate(mp->clk_config[i].clk);
  679. break;
  680. }
  681. }
  682. return rate;
  683. }
  684. u64 sde_power_clk_get_max_rate(struct sde_power_handle *phandle,
  685. char *clock_name)
  686. {
  687. int i;
  688. struct dss_module_power *mp;
  689. u64 rate = 0;
  690. if (!phandle) {
  691. pr_err("invalid input power handle\n");
  692. return 0;
  693. }
  694. mp = &phandle->mp;
  695. for (i = 0; i < mp->num_clk; i++) {
  696. if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
  697. rate = mp->clk_config[i].max_rate;
  698. break;
  699. }
  700. }
  701. return rate;
  702. }
  703. struct clk *sde_power_clk_get_clk(struct sde_power_handle *phandle,
  704. char *clock_name)
  705. {
  706. int i;
  707. struct dss_module_power *mp;
  708. struct clk *clk = NULL;
  709. if (!phandle) {
  710. pr_err("invalid input power handle\n");
  711. return 0;
  712. }
  713. mp = &phandle->mp;
  714. for (i = 0; i < mp->num_clk; i++) {
  715. if (!strcmp(mp->clk_config[i].clk_name, clock_name)) {
  716. clk = mp->clk_config[i].clk;
  717. break;
  718. }
  719. }
  720. return clk;
  721. }
  722. struct sde_power_event *sde_power_handle_register_event(
  723. struct sde_power_handle *phandle,
  724. u32 event_type, void (*cb_fnc)(u32 event_type, void *usr),
  725. void *usr, char *client_name)
  726. {
  727. struct sde_power_event *event;
  728. if (!phandle) {
  729. pr_err("invalid power handle\n");
  730. return ERR_PTR(-EINVAL);
  731. } else if (!cb_fnc || !event_type) {
  732. pr_err("no callback fnc or event type\n");
  733. return ERR_PTR(-EINVAL);
  734. }
  735. event = kzalloc(sizeof(struct sde_power_event), GFP_KERNEL);
  736. if (!event)
  737. return ERR_PTR(-ENOMEM);
  738. event->event_type = event_type;
  739. event->cb_fnc = cb_fnc;
  740. event->usr = usr;
  741. strlcpy(event->client_name, client_name, MAX_CLIENT_NAME_LEN);
  742. event->active = true;
  743. mutex_lock(&phandle->phandle_lock);
  744. list_add(&event->list, &phandle->event_list);
  745. mutex_unlock(&phandle->phandle_lock);
  746. return event;
  747. }
  748. void sde_power_handle_unregister_event(
  749. struct sde_power_handle *phandle,
  750. struct sde_power_event *event)
  751. {
  752. if (!phandle || !event) {
  753. pr_err("invalid phandle or event\n");
  754. } else if (!event->active) {
  755. pr_err("power handle deinit already done\n");
  756. kfree(event);
  757. } else {
  758. mutex_lock(&phandle->phandle_lock);
  759. list_del_init(&event->list);
  760. mutex_unlock(&phandle->phandle_lock);
  761. kfree(event);
  762. }
  763. }