dsi_phy_timing_v4_0.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include "dsi_phy_timing_calc.h"
  6. void dsi_phy_hw_v4_0_get_default_phy_params(
  7. struct phy_clk_params *params)
  8. {
  9. params->clk_prep_buf = 50;
  10. params->clk_zero_buf = 2;
  11. params->clk_trail_buf = 30;
  12. params->hs_prep_buf = 50;
  13. params->hs_zero_buf = 10;
  14. params->hs_trail_buf = 30;
  15. params->hs_rqst_buf = 0;
  16. params->hs_exit_buf = 10;
  17. /* 1.25 is used in code for precision */
  18. params->clk_pre_buf = 1;
  19. params->clk_post_buf = 5;
  20. }
  21. int32_t dsi_phy_hw_v4_0_calc_clk_zero(s64 rec_temp1, s64 mult)
  22. {
  23. s64 rec_temp2, rec_temp3;
  24. rec_temp2 = rec_temp1;
  25. rec_temp3 = roundup(div_s64(rec_temp2, 8), mult);
  26. return (div_s64(rec_temp3, mult) - 1);
  27. }
  28. int32_t dsi_phy_hw_v4_0_calc_clk_trail_rec_min(s64 temp_mul,
  29. s64 frac, s64 mult)
  30. {
  31. s64 rec_temp1, rec_temp2, rec_temp3;
  32. rec_temp1 = temp_mul;
  33. rec_temp2 = div_s64(rec_temp1, 8);
  34. rec_temp3 = roundup(rec_temp2, mult);
  35. return (div_s64(rec_temp3, mult) - 1);
  36. }
  37. int32_t dsi_phy_hw_v4_0_calc_clk_trail_rec_max(s64 temp1, s64 mult)
  38. {
  39. s64 rec_temp2;
  40. rec_temp2 = temp1 / 8;
  41. return (div_s64(rec_temp2, mult) - 1);
  42. }
  43. int32_t dsi_phy_hw_v4_0_calc_hs_zero(s64 temp1, s64 mult)
  44. {
  45. s64 rec_temp2, rec_min;
  46. rec_temp2 = roundup((temp1 / 8), mult);
  47. rec_min = rec_temp2 - (1 * mult);
  48. return div_s64(rec_min, mult);
  49. }
  50. void dsi_phy_hw_v4_0_calc_hs_trail(struct phy_clk_params *clk_params,
  51. struct phy_timing_desc *desc)
  52. {
  53. s64 rec_temp1;
  54. struct timing_entry *t = &desc->hs_trail;
  55. t->rec_min = DIV_ROUND_UP(
  56. (t->mipi_min * clk_params->bitclk_mbps),
  57. (8 * clk_params->tlpx_numer_ns)) - 1;
  58. rec_temp1 = (t->mipi_max * clk_params->bitclk_mbps);
  59. t->rec_max =
  60. (div_s64(rec_temp1, (8 * clk_params->tlpx_numer_ns))) - 1;
  61. }
  62. void dsi_phy_hw_v4_0_update_timing_params(
  63. struct dsi_phy_per_lane_cfgs *timing,
  64. struct phy_timing_desc *desc)
  65. {
  66. timing->lane_v4[0] = 0x00;
  67. timing->lane_v4[1] = desc->clk_zero.reg_value;
  68. timing->lane_v4[2] = desc->clk_prepare.reg_value;
  69. timing->lane_v4[3] = desc->clk_trail.reg_value;
  70. timing->lane_v4[4] = desc->hs_exit.reg_value;
  71. timing->lane_v4[5] = desc->hs_zero.reg_value;
  72. timing->lane_v4[6] = desc->hs_prepare.reg_value;
  73. timing->lane_v4[7] = desc->hs_trail.reg_value;
  74. timing->lane_v4[8] = desc->hs_rqst.reg_value;
  75. timing->lane_v4[9] = 0x02;
  76. timing->lane_v4[10] = 0x04;
  77. timing->lane_v4[11] = 0x00;
  78. timing->lane_v4[12] = desc->clk_pre.reg_value;
  79. timing->lane_v4[13] = desc->clk_post.reg_value;
  80. DSI_DEBUG("[%d %d %d %d]\n", timing->lane_v4[0],
  81. timing->lane_v4[1], timing->lane_v4[2], timing->lane_v4[3]);
  82. DSI_DEBUG("[%d %d %d %d]\n", timing->lane_v4[4],
  83. timing->lane_v4[5], timing->lane_v4[6], timing->lane_v4[7]);
  84. DSI_DEBUG("[%d %d %d %d]\n", timing->lane_v4[8],
  85. timing->lane_v4[9], timing->lane_v4[10], timing->lane_v4[11]);
  86. DSI_DEBUG("[%d %d]\n", timing->lane_v4[12], timing->lane_v4[13]);
  87. timing->count_per_lane = 14;
  88. }