dsi_phy_hw_v2_0.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/math64.h>
  6. #include <linux/delay.h>
  7. #include "dsi_hw.h"
  8. #include "dsi_phy_hw.h"
  9. #define DSIPHY_CMN_REVISION_ID0 0x0000
  10. #define DSIPHY_CMN_REVISION_ID1 0x0004
  11. #define DSIPHY_CMN_REVISION_ID2 0x0008
  12. #define DSIPHY_CMN_REVISION_ID3 0x000C
  13. #define DSIPHY_CMN_CLK_CFG0 0x0010
  14. #define DSIPHY_CMN_CLK_CFG1 0x0014
  15. #define DSIPHY_CMN_GLBL_TEST_CTRL 0x0018
  16. #define DSIPHY_CMN_CTRL_0 0x001C
  17. #define DSIPHY_CMN_CTRL_1 0x0020
  18. #define DSIPHY_CMN_CAL_HW_TRIGGER 0x0024
  19. #define DSIPHY_CMN_CAL_SW_CFG0 0x0028
  20. #define DSIPHY_CMN_CAL_SW_CFG1 0x002C
  21. #define DSIPHY_CMN_CAL_SW_CFG2 0x0030
  22. #define DSIPHY_CMN_CAL_HW_CFG0 0x0034
  23. #define DSIPHY_CMN_CAL_HW_CFG1 0x0038
  24. #define DSIPHY_CMN_CAL_HW_CFG2 0x003C
  25. #define DSIPHY_CMN_CAL_HW_CFG3 0x0040
  26. #define DSIPHY_CMN_CAL_HW_CFG4 0x0044
  27. #define DSIPHY_CMN_PLL_CNTRL 0x0048
  28. #define DSIPHY_CMN_LDO_CNTRL 0x004C
  29. #define DSIPHY_CMN_REGULATOR_CAL_STATUS0 0x0064
  30. #define DSIPHY_CMN_REGULATOR_CAL_STATUS1 0x0068
  31. #define DSI_MDP_ULPS_CLAMP_ENABLE_OFF 0x0054
  32. /* n = 0..3 for data lanes and n = 4 for clock lane
  33. * t for count per lane
  34. */
  35. #define DSIPHY_DLNX_CFG(n, t) \
  36. (0x100 + ((t) * 0x04) + ((n) * 0x80))
  37. #define DSIPHY_DLNX_TIMING_CTRL(n, t) \
  38. (0x118 + ((t) * 0x04) + ((n) * 0x80))
  39. #define DSIPHY_DLNX_STRENGTH_CTRL(n, t) \
  40. (0x138 + ((t) * 0x04) + ((n) * 0x80))
  41. #define DSIPHY_DLNX_TEST_DATAPATH(n) (0x110 + ((n) * 0x80))
  42. #define DSIPHY_DLNX_TEST_STR(n) (0x114 + ((n) * 0x80))
  43. #define DSIPHY_DLNX_BIST_POLY(n) (0x140 + ((n) * 0x80))
  44. #define DSIPHY_DLNX_BIST_SEED0(n) (0x144 + ((n) * 0x80))
  45. #define DSIPHY_DLNX_BIST_SEED1(n) (0x148 + ((n) * 0x80))
  46. #define DSIPHY_DLNX_BIST_HEAD(n) (0x14C + ((n) * 0x80))
  47. #define DSIPHY_DLNX_BIST_SOT(n) (0x150 + ((n) * 0x80))
  48. #define DSIPHY_DLNX_BIST_CTRL0(n) (0x154 + ((n) * 0x80))
  49. #define DSIPHY_DLNX_BIST_CTRL1(n) (0x158 + ((n) * 0x80))
  50. #define DSIPHY_DLNX_BIST_CTRL2(n) (0x15C + ((n) * 0x80))
  51. #define DSIPHY_DLNX_BIST_CTRL3(n) (0x160 + ((n) * 0x80))
  52. #define DSIPHY_DLNX_VREG_CNTRL(n) (0x164 + ((n) * 0x80))
  53. #define DSIPHY_DLNX_HSTX_STR_STATUS(n) (0x168 + ((n) * 0x80))
  54. #define DSIPHY_DLNX_BIST_STATUS0(n) (0x16C + ((n) * 0x80))
  55. #define DSIPHY_DLNX_BIST_STATUS1(n) (0x170 + ((n) * 0x80))
  56. #define DSIPHY_DLNX_BIST_STATUS2(n) (0x174 + ((n) * 0x80))
  57. #define DSIPHY_DLNX_BIST_STATUS3(n) (0x178 + ((n) * 0x80))
  58. #define DSIPHY_DLNX_MISR_STATUS(n) (0x17C + ((n) * 0x80))
  59. #define DSIPHY_PLL_CLKBUFLR_EN 0x041C
  60. #define DSIPHY_PLL_PLL_BANDGAP 0x0508
  61. /**
  62. * regulator_enable() - enable regulators for DSI PHY
  63. * @phy: Pointer to DSI PHY hardware object.
  64. * @reg_cfg: Regulator configuration for all DSI lanes.
  65. */
  66. void dsi_phy_hw_v2_0_regulator_enable(struct dsi_phy_hw *phy,
  67. struct dsi_phy_per_lane_cfgs *reg_cfg)
  68. {
  69. int i;
  70. bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map);
  71. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++)
  72. DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(i), reg_cfg->lane[i][0]);
  73. if (is_split_link)
  74. DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(DSI_LOGICAL_CLOCK_LANE+1),
  75. reg_cfg->lane[DSI_LOGICAL_CLOCK_LANE][0]);
  76. /* make sure all values are written to hardware */
  77. wmb();
  78. DSI_PHY_DBG(phy, "Phy regulators enabled\n");
  79. }
  80. /**
  81. * regulator_disable() - disable regulators
  82. * @phy: Pointer to DSI PHY hardware object.
  83. */
  84. void dsi_phy_hw_v2_0_regulator_disable(struct dsi_phy_hw *phy)
  85. {
  86. DSI_PHY_DBG(phy, "Phy regulators disabled\n");
  87. }
  88. /**
  89. * enable() - Enable PHY hardware
  90. * @phy: Pointer to DSI PHY hardware object.
  91. * @cfg: Per lane configurations for timing, strength and lane
  92. * configurations.
  93. */
  94. void dsi_phy_hw_v2_0_enable(struct dsi_phy_hw *phy,
  95. struct dsi_phy_cfg *cfg)
  96. {
  97. int i, j;
  98. struct dsi_phy_per_lane_cfgs *lanecfg = &cfg->lanecfg;
  99. struct dsi_phy_per_lane_cfgs *timing = &cfg->timing;
  100. struct dsi_phy_per_lane_cfgs *strength = &cfg->strength;
  101. u32 data;
  102. bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map);
  103. DSI_W32(phy, DSIPHY_CMN_LDO_CNTRL, 0x1C);
  104. DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, 0x1);
  105. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
  106. for (j = 0; j < lanecfg->count_per_lane; j++)
  107. DSI_W32(phy, DSIPHY_DLNX_CFG(i, j),
  108. lanecfg->lane[i][j]);
  109. DSI_W32(phy, DSIPHY_DLNX_TEST_STR(i), 0x88);
  110. for (j = 0; j < timing->count_per_lane; j++)
  111. DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL(i, j),
  112. timing->lane[i][j]);
  113. for (j = 0; j < strength->count_per_lane; j++)
  114. DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i, j),
  115. strength->lane[i][j]);
  116. }
  117. if (is_split_link) {
  118. i = DSI_LOGICAL_CLOCK_LANE;
  119. for (j = 0; j < lanecfg->count_per_lane; j++)
  120. DSI_W32(phy, DSIPHY_DLNX_CFG(i+1, j),
  121. lanecfg->lane[i][j]);
  122. DSI_W32(phy, DSIPHY_DLNX_TEST_STR(i+1), 0x0);
  123. DSI_W32(phy, DSIPHY_DLNX_TEST_DATAPATH(i+1), 0x88);
  124. for (j = 0; j < timing->count_per_lane; j++)
  125. DSI_W32(phy, DSIPHY_DLNX_TIMING_CTRL(i+1, j),
  126. timing->lane[i][j]);
  127. for (j = 0; j < strength->count_per_lane; j++)
  128. DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i+1, j),
  129. strength->lane[i][j]);
  130. /* enable split link for cmn clk cfg1 */
  131. data = DSI_R32(phy, DSIPHY_CMN_CLK_CFG1);
  132. data |= BIT(1);
  133. DSI_W32(phy, DSIPHY_CMN_CLK_CFG1, data);
  134. }
  135. /* make sure all values are written to hardware before enabling phy */
  136. wmb();
  137. DSI_W32(phy, DSIPHY_CMN_CTRL_1, 0x80);
  138. udelay(100);
  139. DSI_W32(phy, DSIPHY_CMN_CTRL_1, 0x00);
  140. data = DSI_R32(phy, DSIPHY_CMN_GLBL_TEST_CTRL);
  141. switch (cfg->pll_source) {
  142. case DSI_PLL_SOURCE_STANDALONE:
  143. DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x01);
  144. data &= ~BIT(2);
  145. break;
  146. case DSI_PLL_SOURCE_NATIVE:
  147. DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x03);
  148. data &= ~BIT(2);
  149. break;
  150. case DSI_PLL_SOURCE_NON_NATIVE:
  151. DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0x00);
  152. data |= BIT(2);
  153. break;
  154. default:
  155. break;
  156. }
  157. DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, data);
  158. /* Enable bias current for pll1 during split display case */
  159. if (cfg->pll_source == DSI_PLL_SOURCE_NON_NATIVE)
  160. DSI_W32(phy, DSIPHY_PLL_PLL_BANDGAP, 0x3);
  161. DSI_PHY_DBG(phy, "Phy enabled\n");
  162. }
  163. /**
  164. * disable() - Disable PHY hardware
  165. * @phy: Pointer to DSI PHY hardware object.
  166. */
  167. void dsi_phy_hw_v2_0_disable(struct dsi_phy_hw *phy,
  168. struct dsi_phy_cfg *cfg)
  169. {
  170. DSI_W32(phy, DSIPHY_PLL_CLKBUFLR_EN, 0);
  171. DSI_W32(phy, DSIPHY_CMN_GLBL_TEST_CTRL, 0);
  172. DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0);
  173. DSI_PHY_DBG(phy, "Phy disabled\n");
  174. }
  175. /**
  176. * dsi_phy_hw_v2_0_idle_on() - Enable DSI PHY hardware during idle screen
  177. * @phy: Pointer to DSI PHY hardware object.
  178. */
  179. void dsi_phy_hw_v2_0_idle_on(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg)
  180. {
  181. int i = 0, j;
  182. struct dsi_phy_per_lane_cfgs *strength = &cfg->strength;
  183. bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map);
  184. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
  185. for (j = 0; j < strength->count_per_lane; j++)
  186. DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i, j),
  187. strength->lane[i][j]);
  188. }
  189. if (is_split_link) {
  190. i = DSI_LOGICAL_CLOCK_LANE;
  191. for (j = 0; j < strength->count_per_lane; j++)
  192. DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i+1, j),
  193. strength->lane[i][j]);
  194. }
  195. wmb(); /* make sure write happens */
  196. DSI_PHY_DBG(phy, "Phy enabled out of idle screen\n");
  197. }
  198. /**
  199. * dsi_phy_hw_v2_0_idle_off() - Disable DSI PHY hardware during idle screen
  200. * @phy: Pointer to DSI PHY hardware object.
  201. */
  202. void dsi_phy_hw_v2_0_idle_off(struct dsi_phy_hw *phy)
  203. {
  204. int i = 0;
  205. bool is_split_link = test_bit(DSI_PHY_SPLIT_LINK, phy->feature_map);
  206. DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0x7f);
  207. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++)
  208. DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(i), 0x1c);
  209. if (is_split_link)
  210. DSI_W32(phy, DSIPHY_DLNX_VREG_CNTRL(DSI_LOGICAL_CLOCK_LANE+1),
  211. 0x1c);
  212. DSI_W32(phy, DSIPHY_CMN_LDO_CNTRL, 0x1C);
  213. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++)
  214. DSI_W32(phy, DSIPHY_DLNX_STRENGTH_CTRL(i, 1), 0x0);
  215. if (is_split_link)
  216. DSI_W32(phy,
  217. DSIPHY_DLNX_STRENGTH_CTRL(DSI_LOGICAL_CLOCK_LANE+1, 1), 0x0);
  218. wmb(); /* make sure write happens */
  219. DSI_PHY_DBG(phy, "Phy disabled during idle screen\n");
  220. }
  221. int dsi_phy_hw_timing_val_v2_0(struct dsi_phy_per_lane_cfgs *timing_cfg,
  222. u32 *timing_val, u32 size)
  223. {
  224. int i = 0, j = 0;
  225. if (size != (DSI_LANE_MAX * DSI_MAX_SETTINGS)) {
  226. DSI_ERR("Unexpected timing array size %d\n", size);
  227. return -EINVAL;
  228. }
  229. for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++) {
  230. for (j = 0; j < DSI_MAX_SETTINGS; j++) {
  231. timing_cfg->lane[i][j] = *timing_val;
  232. timing_val++;
  233. }
  234. }
  235. return 0;
  236. }
  237. void dsi_phy_hw_v2_0_clamp_ctrl(struct dsi_phy_hw *phy, bool enable)
  238. {
  239. u32 clamp_reg = 0;
  240. if (!phy->phy_clamp_base) {
  241. DSI_PHY_DBG(phy, "phy_clamp_base NULL\n");
  242. return;
  243. }
  244. if (enable) {
  245. clamp_reg |= BIT(0);
  246. DSI_MISC_W32(phy, DSI_MDP_ULPS_CLAMP_ENABLE_OFF,
  247. clamp_reg);
  248. DSI_PHY_DBG(phy, "clamp enabled\n");
  249. } else {
  250. clamp_reg &= ~BIT(0);
  251. DSI_MISC_W32(phy, DSI_MDP_ULPS_CLAMP_ENABLE_OFF,
  252. clamp_reg);
  253. DSI_PHY_DBG(phy, "clamp disabled\n");
  254. }
  255. }