dsi_drm.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/drm_atomic_helper.h>
  6. #include <drm/drm_atomic.h>
  7. #include "msm_kms.h"
  8. #include "sde_connector.h"
  9. #include "dsi_drm.h"
  10. #include "sde_trace.h"
  11. #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base)
  12. #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base)
  13. #define DEFAULT_PANEL_JITTER_NUMERATOR 2
  14. #define DEFAULT_PANEL_JITTER_DENOMINATOR 1
  15. #define DEFAULT_PANEL_JITTER_ARRAY_SIZE 2
  16. #define DEFAULT_PANEL_PREFILL_LINES 25
  17. static struct dsi_display_mode_priv_info default_priv_info = {
  18. .panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR,
  19. .panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR,
  20. .panel_prefill_lines = DEFAULT_PANEL_PREFILL_LINES,
  21. .dsc_enabled = false,
  22. };
  23. static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
  24. struct dsi_display_mode *dsi_mode)
  25. {
  26. memset(dsi_mode, 0, sizeof(*dsi_mode));
  27. dsi_mode->timing.h_active = drm_mode->hdisplay;
  28. dsi_mode->timing.h_back_porch = drm_mode->htotal - drm_mode->hsync_end;
  29. dsi_mode->timing.h_sync_width = drm_mode->htotal -
  30. (drm_mode->hsync_start + dsi_mode->timing.h_back_porch);
  31. dsi_mode->timing.h_front_porch = drm_mode->hsync_start -
  32. drm_mode->hdisplay;
  33. dsi_mode->timing.h_skew = drm_mode->hskew;
  34. dsi_mode->timing.v_active = drm_mode->vdisplay;
  35. dsi_mode->timing.v_back_porch = drm_mode->vtotal - drm_mode->vsync_end;
  36. dsi_mode->timing.v_sync_width = drm_mode->vtotal -
  37. (drm_mode->vsync_start + dsi_mode->timing.v_back_porch);
  38. dsi_mode->timing.v_front_porch = drm_mode->vsync_start -
  39. drm_mode->vdisplay;
  40. dsi_mode->timing.refresh_rate = drm_mode->vrefresh;
  41. dsi_mode->pixel_clk_khz = drm_mode->clock;
  42. dsi_mode->priv_info =
  43. (struct dsi_display_mode_priv_info *)drm_mode->private;
  44. if (dsi_mode->priv_info) {
  45. dsi_mode->timing.dsc_enabled = dsi_mode->priv_info->dsc_enabled;
  46. dsi_mode->timing.dsc = &dsi_mode->priv_info->dsc;
  47. }
  48. if (msm_is_mode_seamless(drm_mode))
  49. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_SEAMLESS;
  50. if (msm_is_mode_dynamic_fps(drm_mode))
  51. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DFPS;
  52. if (msm_needs_vblank_pre_modeset(drm_mode))
  53. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
  54. if (msm_is_mode_seamless_dms(drm_mode))
  55. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  56. if (msm_is_mode_seamless_vrr(drm_mode))
  57. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR;
  58. if (msm_is_mode_seamless_poms(drm_mode))
  59. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  60. if (msm_is_mode_seamless_dyn_clk(drm_mode))
  61. dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK;
  62. dsi_mode->timing.h_sync_polarity =
  63. !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC);
  64. dsi_mode->timing.v_sync_polarity =
  65. !!(drm_mode->flags & DRM_MODE_FLAG_PVSYNC);
  66. if (drm_mode->flags & DRM_MODE_FLAG_VID_MODE_PANEL)
  67. dsi_mode->panel_mode = DSI_OP_VIDEO_MODE;
  68. if (drm_mode->flags & DRM_MODE_FLAG_CMD_MODE_PANEL)
  69. dsi_mode->panel_mode = DSI_OP_CMD_MODE;
  70. }
  71. void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
  72. struct drm_display_mode *drm_mode)
  73. {
  74. bool video_mode = (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE);
  75. memset(drm_mode, 0, sizeof(*drm_mode));
  76. drm_mode->hdisplay = dsi_mode->timing.h_active;
  77. drm_mode->hsync_start = drm_mode->hdisplay +
  78. dsi_mode->timing.h_front_porch;
  79. drm_mode->hsync_end = drm_mode->hsync_start +
  80. dsi_mode->timing.h_sync_width;
  81. drm_mode->htotal = drm_mode->hsync_end + dsi_mode->timing.h_back_porch;
  82. drm_mode->hskew = dsi_mode->timing.h_skew;
  83. drm_mode->vdisplay = dsi_mode->timing.v_active;
  84. drm_mode->vsync_start = drm_mode->vdisplay +
  85. dsi_mode->timing.v_front_porch;
  86. drm_mode->vsync_end = drm_mode->vsync_start +
  87. dsi_mode->timing.v_sync_width;
  88. drm_mode->vtotal = drm_mode->vsync_end + dsi_mode->timing.v_back_porch;
  89. drm_mode->vrefresh = dsi_mode->timing.refresh_rate;
  90. drm_mode->clock = dsi_mode->pixel_clk_khz;
  91. drm_mode->private = (int *)dsi_mode->priv_info;
  92. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_SEAMLESS)
  93. drm_mode->flags |= DRM_MODE_FLAG_SEAMLESS;
  94. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DFPS)
  95. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
  96. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
  97. drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
  98. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
  99. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS;
  100. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR)
  101. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR;
  102. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_POMS)
  103. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_POMS;
  104. if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)
  105. drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK;
  106. if (dsi_mode->timing.h_sync_polarity)
  107. drm_mode->flags |= DRM_MODE_FLAG_PHSYNC;
  108. if (dsi_mode->timing.v_sync_polarity)
  109. drm_mode->flags |= DRM_MODE_FLAG_PVSYNC;
  110. if (dsi_mode->panel_mode == DSI_OP_VIDEO_MODE)
  111. drm_mode->flags |= DRM_MODE_FLAG_VID_MODE_PANEL;
  112. if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
  113. drm_mode->flags |= DRM_MODE_FLAG_CMD_MODE_PANEL;
  114. /* set mode name */
  115. snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%d%s",
  116. drm_mode->hdisplay, drm_mode->vdisplay,
  117. drm_mode->vrefresh, drm_mode->clock,
  118. video_mode ? "vid" : "cmd");
  119. }
  120. static int dsi_bridge_attach(struct drm_bridge *bridge)
  121. {
  122. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  123. if (!bridge) {
  124. DSI_ERR("Invalid params\n");
  125. return -EINVAL;
  126. }
  127. DSI_DEBUG("[%d] attached\n", c_bridge->id);
  128. return 0;
  129. }
  130. static void dsi_bridge_pre_enable(struct drm_bridge *bridge)
  131. {
  132. int rc = 0;
  133. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  134. if (!bridge) {
  135. DSI_ERR("Invalid params\n");
  136. return;
  137. }
  138. if (!c_bridge || !c_bridge->display || !c_bridge->display->panel) {
  139. DSI_ERR("Incorrect bridge details\n");
  140. return;
  141. }
  142. atomic_set(&c_bridge->display->panel->esd_recovery_pending, 0);
  143. /* By this point mode should have been validated through mode_fixup */
  144. rc = dsi_display_set_mode(c_bridge->display,
  145. &(c_bridge->dsi_mode), 0x0);
  146. if (rc) {
  147. DSI_ERR("[%d] failed to perform a mode set, rc=%d\n",
  148. c_bridge->id, rc);
  149. return;
  150. }
  151. if (c_bridge->dsi_mode.dsi_mode_flags &
  152. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  153. DSI_MODE_FLAG_DYN_CLK)) {
  154. DSI_DEBUG("[%d] seamless pre-enable\n", c_bridge->id);
  155. return;
  156. }
  157. SDE_ATRACE_BEGIN("dsi_display_prepare");
  158. rc = dsi_display_prepare(c_bridge->display);
  159. if (rc) {
  160. DSI_ERR("[%d] DSI display prepare failed, rc=%d\n",
  161. c_bridge->id, rc);
  162. SDE_ATRACE_END("dsi_display_prepare");
  163. return;
  164. }
  165. SDE_ATRACE_END("dsi_display_prepare");
  166. SDE_ATRACE_BEGIN("dsi_display_enable");
  167. rc = dsi_display_enable(c_bridge->display);
  168. if (rc) {
  169. DSI_ERR("[%d] DSI display enable failed, rc=%d\n",
  170. c_bridge->id, rc);
  171. (void)dsi_display_unprepare(c_bridge->display);
  172. }
  173. SDE_ATRACE_END("dsi_display_enable");
  174. rc = dsi_display_splash_res_cleanup(c_bridge->display);
  175. if (rc)
  176. DSI_ERR("Continuous splash pipeline cleanup failed, rc=%d\n",
  177. rc);
  178. }
  179. static void dsi_bridge_enable(struct drm_bridge *bridge)
  180. {
  181. int rc = 0;
  182. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  183. struct dsi_display *display;
  184. if (!bridge) {
  185. DSI_ERR("Invalid params\n");
  186. return;
  187. }
  188. if (c_bridge->dsi_mode.dsi_mode_flags &
  189. (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR |
  190. DSI_MODE_FLAG_DYN_CLK)) {
  191. DSI_DEBUG("[%d] seamless enable\n", c_bridge->id);
  192. return;
  193. }
  194. display = c_bridge->display;
  195. rc = dsi_display_post_enable(display);
  196. if (rc)
  197. DSI_ERR("[%d] DSI display post enabled failed, rc=%d\n",
  198. c_bridge->id, rc);
  199. if (display && display->drm_conn)
  200. sde_connector_helper_bridge_enable(display->drm_conn);
  201. }
  202. static void dsi_bridge_disable(struct drm_bridge *bridge)
  203. {
  204. int rc = 0;
  205. struct dsi_display *display;
  206. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  207. if (!bridge) {
  208. DSI_ERR("Invalid params\n");
  209. return;
  210. }
  211. display = c_bridge->display;
  212. if (display && display->drm_conn) {
  213. if (bridge->encoder->crtc->state->adjusted_mode.private_flags &
  214. MSM_MODE_FLAG_SEAMLESS_POMS) {
  215. display->poms_pending = true;
  216. /* Disable ESD thread, during panel mode switch */
  217. sde_connector_schedule_status_work(display->drm_conn,
  218. false);
  219. } else {
  220. display->poms_pending = false;
  221. sde_connector_helper_bridge_disable(display->drm_conn);
  222. }
  223. }
  224. rc = dsi_display_pre_disable(c_bridge->display);
  225. if (rc) {
  226. DSI_ERR("[%d] DSI display pre disable failed, rc=%d\n",
  227. c_bridge->id, rc);
  228. }
  229. }
  230. static void dsi_bridge_post_disable(struct drm_bridge *bridge)
  231. {
  232. int rc = 0;
  233. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  234. if (!bridge) {
  235. DSI_ERR("Invalid params\n");
  236. return;
  237. }
  238. SDE_ATRACE_BEGIN("dsi_bridge_post_disable");
  239. SDE_ATRACE_BEGIN("dsi_display_disable");
  240. rc = dsi_display_disable(c_bridge->display);
  241. if (rc) {
  242. DSI_ERR("[%d] DSI display disable failed, rc=%d\n",
  243. c_bridge->id, rc);
  244. SDE_ATRACE_END("dsi_display_disable");
  245. return;
  246. }
  247. SDE_ATRACE_END("dsi_display_disable");
  248. rc = dsi_display_unprepare(c_bridge->display);
  249. if (rc) {
  250. DSI_ERR("[%d] DSI display unprepare failed, rc=%d\n",
  251. c_bridge->id, rc);
  252. SDE_ATRACE_END("dsi_bridge_post_disable");
  253. return;
  254. }
  255. SDE_ATRACE_END("dsi_bridge_post_disable");
  256. }
  257. static void dsi_bridge_mode_set(struct drm_bridge *bridge,
  258. struct drm_display_mode *mode,
  259. struct drm_display_mode *adjusted_mode)
  260. {
  261. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  262. if (!bridge || !mode || !adjusted_mode) {
  263. DSI_ERR("Invalid params\n");
  264. return;
  265. }
  266. memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode));
  267. convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode));
  268. /* restore bit_clk_rate also for dynamic clk use cases */
  269. c_bridge->dsi_mode.timing.clk_rate_hz =
  270. dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode);
  271. DSI_DEBUG("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz);
  272. }
  273. static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge,
  274. const struct drm_display_mode *mode,
  275. struct drm_display_mode *adjusted_mode)
  276. {
  277. int rc = 0;
  278. struct dsi_bridge *c_bridge = to_dsi_bridge(bridge);
  279. struct dsi_display *display;
  280. struct dsi_display_mode dsi_mode, cur_dsi_mode, *panel_dsi_mode;
  281. struct drm_display_mode cur_mode;
  282. struct drm_crtc_state *crtc_state;
  283. crtc_state = container_of(mode, struct drm_crtc_state, mode);
  284. if (!bridge || !mode || !adjusted_mode) {
  285. DSI_ERR("Invalid params\n");
  286. return false;
  287. }
  288. display = c_bridge->display;
  289. if (!display) {
  290. DSI_ERR("Invalid params\n");
  291. return false;
  292. }
  293. /*
  294. * if no timing defined in panel, it must be external mode
  295. * and we'll use empty priv info to populate the mode
  296. */
  297. if (display->panel && !display->panel->num_timing_nodes) {
  298. *adjusted_mode = *mode;
  299. adjusted_mode->private = (int *)&default_priv_info;
  300. adjusted_mode->private_flags = 0;
  301. return true;
  302. }
  303. convert_to_dsi_mode(mode, &dsi_mode);
  304. /*
  305. * retrieve dsi mode from dsi driver's cache since not safe to take
  306. * the drm mode config mutex in all paths
  307. */
  308. rc = dsi_display_find_mode(display, &dsi_mode, &panel_dsi_mode);
  309. if (rc)
  310. return rc;
  311. /* propagate the private info to the adjusted_mode derived dsi mode */
  312. dsi_mode.priv_info = panel_dsi_mode->priv_info;
  313. dsi_mode.dsi_mode_flags = panel_dsi_mode->dsi_mode_flags;
  314. dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled;
  315. dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  316. rc = dsi_display_validate_mode(c_bridge->display, &dsi_mode,
  317. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  318. if (rc) {
  319. DSI_ERR("[%d] mode is not valid, rc=%d\n", c_bridge->id, rc);
  320. return false;
  321. }
  322. if (bridge->encoder && bridge->encoder->crtc &&
  323. crtc_state->crtc) {
  324. convert_to_dsi_mode(&crtc_state->crtc->state->mode,
  325. &cur_dsi_mode);
  326. cur_dsi_mode.timing.dsc_enabled =
  327. dsi_mode.priv_info->dsc_enabled;
  328. cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc;
  329. rc = dsi_display_validate_mode_change(c_bridge->display,
  330. &cur_dsi_mode, &dsi_mode);
  331. if (rc) {
  332. DSI_ERR("[%s] seamless mode mismatch failure rc=%d\n",
  333. c_bridge->display->name, rc);
  334. return false;
  335. }
  336. cur_mode = crtc_state->crtc->mode;
  337. /* No panel mode switch when drm pipeline is changing */
  338. if ((dsi_mode.panel_mode != cur_dsi_mode.panel_mode) &&
  339. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  340. (crtc_state->enable ==
  341. crtc_state->crtc->state->enable))
  342. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_POMS;
  343. /* No DMS/VRR when drm pipeline is changing */
  344. if (!drm_mode_equal(&cur_mode, adjusted_mode) &&
  345. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) &&
  346. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_POMS)) &&
  347. (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) &&
  348. (!crtc_state->active_changed ||
  349. display->is_cont_splash_enabled))
  350. dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS;
  351. }
  352. /* convert back to drm mode, propagating the private info & flags */
  353. dsi_convert_to_drm_mode(&dsi_mode, adjusted_mode);
  354. return true;
  355. }
  356. u64 dsi_drm_find_bit_clk_rate(void *display,
  357. const struct drm_display_mode *drm_mode)
  358. {
  359. int i = 0, count = 0;
  360. struct dsi_display *dsi_display = display;
  361. struct dsi_display_mode *dsi_mode;
  362. u64 bit_clk_rate = 0;
  363. if (!dsi_display || !drm_mode)
  364. return 0;
  365. dsi_display_get_mode_count(dsi_display, &count);
  366. for (i = 0; i < count; i++) {
  367. dsi_mode = &dsi_display->modes[i];
  368. if ((dsi_mode->timing.v_active == drm_mode->vdisplay) &&
  369. (dsi_mode->timing.h_active == drm_mode->hdisplay) &&
  370. (dsi_mode->pixel_clk_khz == drm_mode->clock) &&
  371. (dsi_mode->timing.refresh_rate == drm_mode->vrefresh)) {
  372. bit_clk_rate = dsi_mode->timing.clk_rate_hz;
  373. break;
  374. }
  375. }
  376. return bit_clk_rate;
  377. }
  378. int dsi_conn_get_mode_info(struct drm_connector *connector,
  379. const struct drm_display_mode *drm_mode,
  380. struct msm_mode_info *mode_info,
  381. void *display, const struct msm_resource_caps_info *avail_res)
  382. {
  383. struct dsi_display_mode dsi_mode;
  384. struct dsi_mode_info *timing;
  385. if (!drm_mode || !mode_info)
  386. return -EINVAL;
  387. convert_to_dsi_mode(drm_mode, &dsi_mode);
  388. if (!dsi_mode.priv_info)
  389. return -EINVAL;
  390. memset(mode_info, 0, sizeof(*mode_info));
  391. timing = &dsi_mode.timing;
  392. mode_info->frame_rate = dsi_mode.timing.refresh_rate;
  393. mode_info->vtotal = DSI_V_TOTAL(timing);
  394. mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines;
  395. mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer;
  396. mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom;
  397. mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode);
  398. mode_info->mdp_transfer_time_us =
  399. dsi_mode.priv_info->mdp_transfer_time_us;
  400. memcpy(&mode_info->topology, &dsi_mode.priv_info->topology,
  401. sizeof(struct msm_display_topology));
  402. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_NONE;
  403. if (dsi_mode.priv_info->dsc_enabled) {
  404. mode_info->comp_info.comp_type = MSM_DISPLAY_COMPRESSION_DSC;
  405. memcpy(&mode_info->comp_info.dsc_info, &dsi_mode.priv_info->dsc,
  406. sizeof(dsi_mode.priv_info->dsc));
  407. mode_info->comp_info.comp_ratio =
  408. MSM_DISPLAY_COMPRESSION_RATIO_3_TO_1;
  409. }
  410. if (dsi_mode.priv_info->roi_caps.enabled) {
  411. memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps,
  412. sizeof(dsi_mode.priv_info->roi_caps));
  413. }
  414. return 0;
  415. }
  416. static const struct drm_bridge_funcs dsi_bridge_ops = {
  417. .attach = dsi_bridge_attach,
  418. .mode_fixup = dsi_bridge_mode_fixup,
  419. .pre_enable = dsi_bridge_pre_enable,
  420. .enable = dsi_bridge_enable,
  421. .disable = dsi_bridge_disable,
  422. .post_disable = dsi_bridge_post_disable,
  423. .mode_set = dsi_bridge_mode_set,
  424. };
  425. int dsi_conn_set_info_blob(struct drm_connector *connector,
  426. void *info, void *display, struct msm_mode_info *mode_info)
  427. {
  428. struct dsi_display *dsi_display = display;
  429. struct dsi_panel *panel;
  430. enum dsi_pixel_format fmt;
  431. u32 bpp;
  432. if (!info || !dsi_display)
  433. return -EINVAL;
  434. dsi_display->drm_conn = connector;
  435. sde_kms_info_add_keystr(info,
  436. "display type", dsi_display->display_type);
  437. switch (dsi_display->type) {
  438. case DSI_DISPLAY_SINGLE:
  439. sde_kms_info_add_keystr(info, "display config",
  440. "single display");
  441. break;
  442. case DSI_DISPLAY_EXT_BRIDGE:
  443. sde_kms_info_add_keystr(info, "display config", "ext bridge");
  444. break;
  445. case DSI_DISPLAY_SPLIT:
  446. sde_kms_info_add_keystr(info, "display config",
  447. "split display");
  448. break;
  449. case DSI_DISPLAY_SPLIT_EXT_BRIDGE:
  450. sde_kms_info_add_keystr(info, "display config",
  451. "split ext bridge");
  452. break;
  453. default:
  454. DSI_DEBUG("invalid display type:%d\n", dsi_display->type);
  455. break;
  456. }
  457. if (!dsi_display->panel) {
  458. DSI_DEBUG("invalid panel data\n");
  459. goto end;
  460. }
  461. panel = dsi_display->panel;
  462. sde_kms_info_add_keystr(info, "panel name", panel->name);
  463. switch (panel->panel_mode) {
  464. case DSI_OP_VIDEO_MODE:
  465. sde_kms_info_add_keystr(info, "panel mode", "video");
  466. sde_kms_info_add_keystr(info, "qsync support",
  467. panel->qsync_min_fps ? "true" : "false");
  468. break;
  469. case DSI_OP_CMD_MODE:
  470. sde_kms_info_add_keystr(info, "panel mode", "command");
  471. sde_kms_info_add_keyint(info, "mdp_transfer_time_us",
  472. mode_info->mdp_transfer_time_us);
  473. sde_kms_info_add_keystr(info, "qsync support",
  474. panel->qsync_min_fps ? "true" : "false");
  475. break;
  476. default:
  477. DSI_DEBUG("invalid panel type:%d\n", panel->panel_mode);
  478. break;
  479. }
  480. sde_kms_info_add_keystr(info, "dfps support",
  481. panel->dfps_caps.dfps_support ? "true" : "false");
  482. if (panel->dfps_caps.dfps_support) {
  483. sde_kms_info_add_keyint(info, "min_fps",
  484. panel->dfps_caps.min_refresh_rate);
  485. sde_kms_info_add_keyint(info, "max_fps",
  486. panel->dfps_caps.max_refresh_rate);
  487. }
  488. sde_kms_info_add_keystr(info, "dyn bitclk support",
  489. panel->dyn_clk_caps.dyn_clk_support ? "true" : "false");
  490. switch (panel->phy_props.rotation) {
  491. case DSI_PANEL_ROTATE_NONE:
  492. sde_kms_info_add_keystr(info, "panel orientation", "none");
  493. break;
  494. case DSI_PANEL_ROTATE_H_FLIP:
  495. sde_kms_info_add_keystr(info, "panel orientation", "horz flip");
  496. break;
  497. case DSI_PANEL_ROTATE_V_FLIP:
  498. sde_kms_info_add_keystr(info, "panel orientation", "vert flip");
  499. break;
  500. case DSI_PANEL_ROTATE_HV_FLIP:
  501. sde_kms_info_add_keystr(info, "panel orientation",
  502. "horz & vert flip");
  503. break;
  504. default:
  505. DSI_DEBUG("invalid panel rotation:%d\n",
  506. panel->phy_props.rotation);
  507. break;
  508. }
  509. switch (panel->bl_config.type) {
  510. case DSI_BACKLIGHT_PWM:
  511. sde_kms_info_add_keystr(info, "backlight type", "pwm");
  512. break;
  513. case DSI_BACKLIGHT_WLED:
  514. sde_kms_info_add_keystr(info, "backlight type", "wled");
  515. break;
  516. case DSI_BACKLIGHT_DCS:
  517. sde_kms_info_add_keystr(info, "backlight type", "dcs");
  518. break;
  519. default:
  520. DSI_DEBUG("invalid panel backlight type:%d\n",
  521. panel->bl_config.type);
  522. break;
  523. }
  524. if (mode_info && mode_info->roi_caps.enabled) {
  525. sde_kms_info_add_keyint(info, "partial_update_num_roi",
  526. mode_info->roi_caps.num_roi);
  527. sde_kms_info_add_keyint(info, "partial_update_xstart",
  528. mode_info->roi_caps.align.xstart_pix_align);
  529. sde_kms_info_add_keyint(info, "partial_update_walign",
  530. mode_info->roi_caps.align.width_pix_align);
  531. sde_kms_info_add_keyint(info, "partial_update_wmin",
  532. mode_info->roi_caps.align.min_width);
  533. sde_kms_info_add_keyint(info, "partial_update_ystart",
  534. mode_info->roi_caps.align.ystart_pix_align);
  535. sde_kms_info_add_keyint(info, "partial_update_halign",
  536. mode_info->roi_caps.align.height_pix_align);
  537. sde_kms_info_add_keyint(info, "partial_update_hmin",
  538. mode_info->roi_caps.align.min_height);
  539. sde_kms_info_add_keyint(info, "partial_update_roimerge",
  540. mode_info->roi_caps.merge_rois);
  541. }
  542. fmt = dsi_display->config.common_config.dst_format;
  543. bpp = dsi_ctrl_pixel_format_to_bpp(fmt);
  544. sde_kms_info_add_keyint(info, "bit_depth", bpp);
  545. end:
  546. return 0;
  547. }
  548. enum drm_connector_status dsi_conn_detect(struct drm_connector *conn,
  549. bool force,
  550. void *display)
  551. {
  552. enum drm_connector_status status = connector_status_unknown;
  553. struct msm_display_info info;
  554. int rc;
  555. if (!conn || !display)
  556. return status;
  557. /* get display dsi_info */
  558. memset(&info, 0x0, sizeof(info));
  559. rc = dsi_display_get_info(conn, &info, display);
  560. if (rc) {
  561. DSI_ERR("failed to get display info, rc=%d\n", rc);
  562. return connector_status_disconnected;
  563. }
  564. if (info.capabilities & MSM_DISPLAY_CAP_HOT_PLUG)
  565. status = (info.is_connected ? connector_status_connected :
  566. connector_status_disconnected);
  567. else
  568. status = connector_status_connected;
  569. conn->display_info.width_mm = info.width_mm;
  570. conn->display_info.height_mm = info.height_mm;
  571. return status;
  572. }
  573. void dsi_connector_put_modes(struct drm_connector *connector,
  574. void *display)
  575. {
  576. struct drm_display_mode *drm_mode;
  577. struct dsi_display_mode dsi_mode;
  578. struct dsi_display *dsi_display;
  579. if (!connector || !display)
  580. return;
  581. list_for_each_entry(drm_mode, &connector->modes, head) {
  582. convert_to_dsi_mode(drm_mode, &dsi_mode);
  583. dsi_display_put_mode(display, &dsi_mode);
  584. }
  585. /* free the display structure modes also */
  586. dsi_display = display;
  587. kfree(dsi_display->modes);
  588. dsi_display->modes = NULL;
  589. }
  590. static int dsi_drm_update_edid_name(struct edid *edid, const char *name)
  591. {
  592. u8 *dtd = (u8 *)&edid->detailed_timings[3];
  593. u8 standard_header[] = {0x00, 0x00, 0x00, 0xFE, 0x00};
  594. u32 dtd_size = 18;
  595. u32 header_size = sizeof(standard_header);
  596. if (!name)
  597. return -EINVAL;
  598. /* Fill standard header */
  599. memcpy(dtd, standard_header, header_size);
  600. dtd_size -= header_size;
  601. dtd_size = min_t(u32, dtd_size, strlen(name));
  602. memcpy(dtd + header_size, name, dtd_size);
  603. return 0;
  604. }
  605. static void dsi_drm_update_dtd(struct edid *edid,
  606. struct dsi_display_mode *modes, u32 modes_count)
  607. {
  608. u32 i;
  609. u32 count = min_t(u32, modes_count, 3);
  610. for (i = 0; i < count; i++) {
  611. struct detailed_timing *dtd = &edid->detailed_timings[i];
  612. struct dsi_display_mode *mode = &modes[i];
  613. struct dsi_mode_info *timing = &mode->timing;
  614. struct detailed_pixel_timing *pd = &dtd->data.pixel_data;
  615. u32 h_blank = timing->h_front_porch + timing->h_sync_width +
  616. timing->h_back_porch;
  617. u32 v_blank = timing->v_front_porch + timing->v_sync_width +
  618. timing->v_back_porch;
  619. u32 h_img = 0, v_img = 0;
  620. dtd->pixel_clock = mode->pixel_clk_khz / 10;
  621. pd->hactive_lo = timing->h_active & 0xFF;
  622. pd->hblank_lo = h_blank & 0xFF;
  623. pd->hactive_hblank_hi = ((h_blank >> 8) & 0xF) |
  624. ((timing->h_active >> 8) & 0xF) << 4;
  625. pd->vactive_lo = timing->v_active & 0xFF;
  626. pd->vblank_lo = v_blank & 0xFF;
  627. pd->vactive_vblank_hi = ((v_blank >> 8) & 0xF) |
  628. ((timing->v_active >> 8) & 0xF) << 4;
  629. pd->hsync_offset_lo = timing->h_front_porch & 0xFF;
  630. pd->hsync_pulse_width_lo = timing->h_sync_width & 0xFF;
  631. pd->vsync_offset_pulse_width_lo =
  632. ((timing->v_front_porch & 0xF) << 4) |
  633. (timing->v_sync_width & 0xF);
  634. pd->hsync_vsync_offset_pulse_width_hi =
  635. (((timing->h_front_porch >> 8) & 0x3) << 6) |
  636. (((timing->h_sync_width >> 8) & 0x3) << 4) |
  637. (((timing->v_front_porch >> 4) & 0x3) << 2) |
  638. (((timing->v_sync_width >> 4) & 0x3) << 0);
  639. pd->width_mm_lo = h_img & 0xFF;
  640. pd->height_mm_lo = v_img & 0xFF;
  641. pd->width_height_mm_hi = (((h_img >> 8) & 0xF) << 4) |
  642. ((v_img >> 8) & 0xF);
  643. pd->hborder = 0;
  644. pd->vborder = 0;
  645. pd->misc = 0;
  646. }
  647. }
  648. static void dsi_drm_update_checksum(struct edid *edid)
  649. {
  650. u8 *data = (u8 *)edid;
  651. u32 i, sum = 0;
  652. for (i = 0; i < EDID_LENGTH - 1; i++)
  653. sum += data[i];
  654. edid->checksum = 0x100 - (sum & 0xFF);
  655. }
  656. int dsi_connector_get_modes(struct drm_connector *connector, void *data,
  657. const struct msm_resource_caps_info *avail_res)
  658. {
  659. int rc, i;
  660. u32 count = 0, edid_size;
  661. struct dsi_display_mode *modes = NULL;
  662. struct drm_display_mode drm_mode;
  663. struct dsi_display *display = data;
  664. struct edid edid;
  665. const u8 edid_buf[EDID_LENGTH] = {
  666. 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x44, 0x6D,
  667. 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x1B, 0x10, 0x01, 0x03,
  668. 0x80, 0x00, 0x00, 0x78, 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47,
  669. 0x98, 0x27, 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
  670. 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
  671. 0x01, 0x01, 0x01, 0x01,
  672. };
  673. edid_size = min_t(u32, sizeof(edid), EDID_LENGTH);
  674. memcpy(&edid, edid_buf, edid_size);
  675. rc = dsi_display_get_mode_count(display, &count);
  676. if (rc) {
  677. DSI_ERR("failed to get num of modes, rc=%d\n", rc);
  678. goto end;
  679. }
  680. rc = dsi_display_get_modes(display, &modes);
  681. if (rc) {
  682. DSI_ERR("failed to get modes, rc=%d\n", rc);
  683. count = 0;
  684. goto end;
  685. }
  686. for (i = 0; i < count; i++) {
  687. struct drm_display_mode *m;
  688. memset(&drm_mode, 0x0, sizeof(drm_mode));
  689. dsi_convert_to_drm_mode(&modes[i], &drm_mode);
  690. m = drm_mode_duplicate(connector->dev, &drm_mode);
  691. if (!m) {
  692. DSI_ERR("failed to add mode %ux%u\n",
  693. drm_mode.hdisplay,
  694. drm_mode.vdisplay);
  695. count = -ENOMEM;
  696. goto end;
  697. }
  698. m->width_mm = connector->display_info.width_mm;
  699. m->height_mm = connector->display_info.height_mm;
  700. /* set the first mode in list as preferred */
  701. if (i == 0)
  702. m->type |= DRM_MODE_TYPE_PREFERRED;
  703. drm_mode_probed_add(connector, m);
  704. }
  705. rc = dsi_drm_update_edid_name(&edid, display->panel->name);
  706. if (rc) {
  707. count = 0;
  708. goto end;
  709. }
  710. edid.width_cm = (connector->display_info.width_mm) / 10;
  711. edid.height_cm = (connector->display_info.height_mm) / 10;
  712. dsi_drm_update_dtd(&edid, modes, count);
  713. dsi_drm_update_checksum(&edid);
  714. rc = drm_connector_update_edid_property(connector, &edid);
  715. if (rc)
  716. count = 0;
  717. end:
  718. DSI_DEBUG("MODE COUNT =%d\n\n", count);
  719. return count;
  720. }
  721. enum drm_mode_status dsi_conn_mode_valid(struct drm_connector *connector,
  722. struct drm_display_mode *mode,
  723. void *display, const struct msm_resource_caps_info *avail_res)
  724. {
  725. struct dsi_display_mode dsi_mode;
  726. int rc;
  727. if (!connector || !mode) {
  728. DSI_ERR("Invalid params\n");
  729. return MODE_ERROR;
  730. }
  731. convert_to_dsi_mode(mode, &dsi_mode);
  732. rc = dsi_display_validate_mode(display, &dsi_mode,
  733. DSI_VALIDATE_FLAG_ALLOW_ADJUST);
  734. if (rc) {
  735. DSI_ERR("mode not supported, rc=%d\n", rc);
  736. return MODE_BAD;
  737. }
  738. return MODE_OK;
  739. }
  740. int dsi_conn_pre_kickoff(struct drm_connector *connector,
  741. void *display,
  742. struct msm_display_kickoff_params *params)
  743. {
  744. if (!connector || !display || !params) {
  745. DSI_ERR("Invalid params\n");
  746. return -EINVAL;
  747. }
  748. return dsi_display_pre_kickoff(connector, display, params);
  749. }
  750. void dsi_conn_enable_event(struct drm_connector *connector,
  751. uint32_t event_idx, bool enable, void *display)
  752. {
  753. struct dsi_event_cb_info event_info;
  754. memset(&event_info, 0, sizeof(event_info));
  755. event_info.event_cb = sde_connector_trigger_event;
  756. event_info.event_usr_ptr = connector;
  757. dsi_display_enable_event(connector, display,
  758. event_idx, &event_info, enable);
  759. }
  760. int dsi_conn_post_kickoff(struct drm_connector *connector)
  761. {
  762. struct drm_encoder *encoder;
  763. struct dsi_bridge *c_bridge;
  764. struct dsi_display_mode adj_mode;
  765. struct dsi_display *display;
  766. struct dsi_display_ctrl *m_ctrl, *ctrl;
  767. int i, rc = 0;
  768. if (!connector || !connector->state) {
  769. DSI_ERR("invalid connector or connector state\n");
  770. return -EINVAL;
  771. }
  772. encoder = connector->state->best_encoder;
  773. if (!encoder) {
  774. DSI_DEBUG("best encoder is not available\n");
  775. return 0;
  776. }
  777. c_bridge = to_dsi_bridge(encoder->bridge);
  778. adj_mode = c_bridge->dsi_mode;
  779. display = c_bridge->display;
  780. if (adj_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR) {
  781. m_ctrl = &display->ctrl[display->clk_master_idx];
  782. rc = dsi_ctrl_timing_db_update(m_ctrl->ctrl, false);
  783. if (rc) {
  784. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  785. display->name, rc);
  786. return -EINVAL;
  787. }
  788. /* Update the rest of the controllers */
  789. display_for_each_ctrl(i, display) {
  790. ctrl = &display->ctrl[i];
  791. if (!ctrl->ctrl || (ctrl == m_ctrl))
  792. continue;
  793. rc = dsi_ctrl_timing_db_update(ctrl->ctrl, false);
  794. if (rc) {
  795. DSI_ERR("[%s] failed to dfps update rc=%d\n",
  796. display->name, rc);
  797. return -EINVAL;
  798. }
  799. }
  800. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR;
  801. }
  802. /* ensure dynamic clk switch flag is reset */
  803. c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK;
  804. return 0;
  805. }
  806. struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display *display,
  807. struct drm_device *dev,
  808. struct drm_encoder *encoder)
  809. {
  810. int rc = 0;
  811. struct dsi_bridge *bridge;
  812. bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
  813. if (!bridge) {
  814. rc = -ENOMEM;
  815. goto error;
  816. }
  817. bridge->display = display;
  818. bridge->base.funcs = &dsi_bridge_ops;
  819. bridge->base.encoder = encoder;
  820. rc = drm_bridge_attach(encoder, &bridge->base, NULL);
  821. if (rc) {
  822. DSI_ERR("failed to attach bridge, rc=%d\n", rc);
  823. goto error_free_bridge;
  824. }
  825. encoder->bridge = &bridge->base;
  826. return bridge;
  827. error_free_bridge:
  828. kfree(bridge);
  829. error:
  830. return ERR_PTR(rc);
  831. }
  832. void dsi_drm_bridge_cleanup(struct dsi_bridge *bridge)
  833. {
  834. if (bridge && bridge->base.encoder)
  835. bridge->base.encoder->bridge = NULL;
  836. kfree(bridge);
  837. }