dp_tx.c 95 KB

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  1. /*
  2. * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "htt.h"
  19. #include "dp_tx.h"
  20. #include "dp_tx_desc.h"
  21. #include "dp_peer.h"
  22. #include "dp_types.h"
  23. #include "hal_tx.h"
  24. #include "qdf_mem.h"
  25. #include "qdf_nbuf.h"
  26. #include "qdf_net_types.h"
  27. #include <wlan_cfg.h>
  28. #ifdef MESH_MODE_SUPPORT
  29. #include "if_meta_hdr.h"
  30. #endif
  31. #define DP_TX_QUEUE_MASK 0x3
  32. /* TODO Add support in TSO */
  33. #define DP_DESC_NUM_FRAG(x) 0
  34. /* disable TQM_BYPASS */
  35. #define TQM_BYPASS_WAR 0
  36. /* invalid peer id for reinject*/
  37. #define DP_INVALID_PEER 0XFFFE
  38. /*mapping between hal encrypt type and cdp_sec_type*/
  39. #define MAX_CDP_SEC_TYPE 12
  40. static const uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {
  41. HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  42. HAL_TX_ENCRYPT_TYPE_WEP_128,
  43. HAL_TX_ENCRYPT_TYPE_WEP_104,
  44. HAL_TX_ENCRYPT_TYPE_WEP_40,
  45. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  46. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  47. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  48. HAL_TX_ENCRYPT_TYPE_WAPI,
  49. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  50. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  51. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  52. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  53. /**
  54. * dp_tx_get_queue() - Returns Tx queue IDs to be used for this Tx frame
  55. * @vdev: DP Virtual device handle
  56. * @nbuf: Buffer pointer
  57. * @queue: queue ids container for nbuf
  58. *
  59. * TX packet queue has 2 instances, software descriptors id and dma ring id
  60. * Based on tx feature and hardware configuration queue id combination could be
  61. * different.
  62. * For example -
  63. * With XPS enabled,all TX descriptor pools and dma ring are assigned per cpu id
  64. * With no XPS,lock based resource protection, Descriptor pool ids are different
  65. * for each vdev, dma ring id will be same as single pdev id
  66. *
  67. * Return: None
  68. */
  69. #ifdef QCA_OL_TX_MULTIQ_SUPPORT
  70. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  71. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  72. {
  73. uint16_t queue_offset = qdf_nbuf_get_queue_mapping(nbuf) & DP_TX_QUEUE_MASK;
  74. queue->desc_pool_id = queue_offset;
  75. queue->ring_id = vdev->pdev->soc->tx_ring_map[queue_offset];
  76. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  77. "%s, pool_id:%d ring_id: %d",
  78. __func__, queue->desc_pool_id, queue->ring_id);
  79. return;
  80. }
  81. #else /* QCA_OL_TX_MULTIQ_SUPPORT */
  82. static inline void dp_tx_get_queue(struct dp_vdev *vdev,
  83. qdf_nbuf_t nbuf, struct dp_tx_queue *queue)
  84. {
  85. /* get flow id */
  86. queue->desc_pool_id = DP_TX_GET_DESC_POOL_ID(vdev);
  87. queue->ring_id = DP_TX_GET_RING_ID(vdev);
  88. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  89. "%s, pool_id:%d ring_id: %d",
  90. __func__, queue->desc_pool_id, queue->ring_id);
  91. return;
  92. }
  93. #endif
  94. #if defined(FEATURE_TSO)
  95. /**
  96. * dp_tx_tso_desc_release() - Release the tso segment
  97. * after unmapping all the fragments
  98. *
  99. * @pdev - physical device handle
  100. * @tx_desc - Tx software descriptor
  101. */
  102. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  103. struct dp_tx_desc_s *tx_desc)
  104. {
  105. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  106. if (qdf_unlikely(tx_desc->tso_desc == NULL)) {
  107. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  108. "%s %d TSO desc is NULL!",
  109. __func__, __LINE__);
  110. qdf_assert(0);
  111. } else if (qdf_unlikely(tx_desc->tso_num_desc == NULL)) {
  112. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  113. "%s %d TSO common info is NULL!",
  114. __func__, __LINE__);
  115. qdf_assert(0);
  116. } else {
  117. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  118. (struct qdf_tso_num_seg_elem_t *) tx_desc->tso_num_desc;
  119. if (tso_num_desc->num_seg.tso_cmn_num_seg > 1) {
  120. tso_num_desc->num_seg.tso_cmn_num_seg--;
  121. qdf_nbuf_unmap_tso_segment(soc->osdev,
  122. tx_desc->tso_desc, false);
  123. } else {
  124. tso_num_desc->num_seg.tso_cmn_num_seg--;
  125. qdf_assert(tso_num_desc->num_seg.tso_cmn_num_seg == 0);
  126. qdf_nbuf_unmap_tso_segment(soc->osdev,
  127. tx_desc->tso_desc, true);
  128. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  129. tx_desc->tso_num_desc);
  130. tx_desc->tso_num_desc = NULL;
  131. }
  132. dp_tx_tso_desc_free(soc,
  133. tx_desc->pool_id, tx_desc->tso_desc);
  134. tx_desc->tso_desc = NULL;
  135. }
  136. }
  137. #else
  138. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  139. struct dp_tx_desc_s *tx_desc)
  140. {
  141. return;
  142. }
  143. #endif
  144. /**
  145. * dp_tx_desc_release() - Release Tx Descriptor
  146. * @tx_desc : Tx Descriptor
  147. * @desc_pool_id: Descriptor Pool ID
  148. *
  149. * Deallocate all resources attached to Tx descriptor and free the Tx
  150. * descriptor.
  151. *
  152. * Return:
  153. */
  154. static void
  155. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  156. {
  157. struct dp_pdev *pdev = tx_desc->pdev;
  158. struct dp_soc *soc;
  159. uint8_t comp_status = 0;
  160. qdf_assert(pdev);
  161. soc = pdev->soc;
  162. if (tx_desc->frm_type == dp_tx_frm_tso)
  163. dp_tx_tso_desc_release(soc, tx_desc);
  164. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
  165. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  166. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  167. dp_tx_me_free_buf(tx_desc->pdev, tx_desc->me_buffer);
  168. qdf_atomic_dec(&pdev->num_tx_outstanding);
  169. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  170. qdf_atomic_dec(&pdev->num_tx_exception);
  171. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  172. hal_tx_comp_get_buffer_source(&tx_desc->comp))
  173. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp);
  174. else
  175. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  176. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  177. "Tx Completion Release desc %d status %d outstanding %d",
  178. tx_desc->id, comp_status,
  179. qdf_atomic_read(&pdev->num_tx_outstanding));
  180. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  181. return;
  182. }
  183. /**
  184. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  185. * @vdev: DP vdev Handle
  186. * @nbuf: skb
  187. *
  188. * Prepares and fills HTT metadata in the frame pre-header for special frames
  189. * that should be transmitted using varying transmit parameters.
  190. * There are 2 VDEV modes that currently needs this special metadata -
  191. * 1) Mesh Mode
  192. * 2) DSRC Mode
  193. *
  194. * Return: HTT metadata size
  195. *
  196. */
  197. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  198. uint32_t *meta_data)
  199. {
  200. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  201. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  202. uint8_t htt_desc_size;
  203. /* Size rounded of multiple of 8 bytes */
  204. uint8_t htt_desc_size_aligned;
  205. uint8_t *hdr = NULL;
  206. /*
  207. * Metadata - HTT MSDU Extension header
  208. */
  209. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  210. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  211. if (vdev->mesh_vdev) {
  212. /* Fill and add HTT metaheader */
  213. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  214. if (hdr == NULL) {
  215. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  216. "Error in filling HTT metadata\n");
  217. return 0;
  218. }
  219. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  220. } else if (vdev->opmode == wlan_op_mode_ocb) {
  221. /* Todo - Add support for DSRC */
  222. }
  223. return htt_desc_size_aligned;
  224. }
  225. /**
  226. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  227. * @tso_seg: TSO segment to process
  228. * @ext_desc: Pointer to MSDU extension descriptor
  229. *
  230. * Return: void
  231. */
  232. #if defined(FEATURE_TSO)
  233. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  234. void *ext_desc)
  235. {
  236. uint8_t num_frag;
  237. uint32_t tso_flags;
  238. /*
  239. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  240. * tcp_flag_mask
  241. *
  242. * Checksum enable flags are set in TCL descriptor and not in Extension
  243. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  244. */
  245. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  246. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  247. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  248. tso_seg->tso_flags.ip_len);
  249. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  250. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  251. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  252. uint32_t lo = 0;
  253. uint32_t hi = 0;
  254. qdf_dmaaddr_to_32s(
  255. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  256. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  257. tso_seg->tso_frags[num_frag].length);
  258. }
  259. return;
  260. }
  261. #else
  262. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  263. void *ext_desc)
  264. {
  265. return;
  266. }
  267. #endif
  268. #if defined(FEATURE_TSO)
  269. /**
  270. * dp_tx_free_tso_seg() - Loop through the tso segments
  271. * allocated and free them
  272. *
  273. * @soc: soc handle
  274. * @free_seg: list of tso segments
  275. * @msdu_info: msdu descriptor
  276. *
  277. * Return - void
  278. */
  279. static void dp_tx_free_tso_seg(struct dp_soc *soc,
  280. struct qdf_tso_seg_elem_t *free_seg,
  281. struct dp_tx_msdu_info_s *msdu_info)
  282. {
  283. struct qdf_tso_seg_elem_t *next_seg;
  284. while (free_seg) {
  285. next_seg = free_seg->next;
  286. dp_tx_tso_desc_free(soc,
  287. msdu_info->tx_queue.desc_pool_id,
  288. free_seg);
  289. free_seg = next_seg;
  290. }
  291. }
  292. /**
  293. * dp_tx_free_tso_num_seg() - Loop through the tso num segments
  294. * allocated and free them
  295. *
  296. * @soc: soc handle
  297. * @free_seg: list of tso segments
  298. * @msdu_info: msdu descriptor
  299. * Return - void
  300. */
  301. static void dp_tx_free_tso_num_seg(struct dp_soc *soc,
  302. struct qdf_tso_num_seg_elem_t *free_seg,
  303. struct dp_tx_msdu_info_s *msdu_info)
  304. {
  305. struct qdf_tso_num_seg_elem_t *next_seg;
  306. while (free_seg) {
  307. next_seg = free_seg->next;
  308. dp_tso_num_seg_free(soc,
  309. msdu_info->tx_queue.desc_pool_id,
  310. free_seg);
  311. free_seg = next_seg;
  312. }
  313. }
  314. /**
  315. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  316. * @vdev: virtual device handle
  317. * @msdu: network buffer
  318. * @msdu_info: meta data associated with the msdu
  319. *
  320. * Return: QDF_STATUS_SUCCESS success
  321. */
  322. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  323. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  324. {
  325. struct qdf_tso_seg_elem_t *tso_seg;
  326. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  327. struct dp_soc *soc = vdev->pdev->soc;
  328. struct qdf_tso_info_t *tso_info;
  329. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  330. tso_info = &msdu_info->u.tso_info;
  331. tso_info->curr_seg = NULL;
  332. tso_info->tso_seg_list = NULL;
  333. tso_info->num_segs = num_seg;
  334. msdu_info->frm_type = dp_tx_frm_tso;
  335. tso_info->tso_num_seg_list = NULL;
  336. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  337. while (num_seg) {
  338. tso_seg = dp_tx_tso_desc_alloc(
  339. soc, msdu_info->tx_queue.desc_pool_id);
  340. if (tso_seg) {
  341. tso_seg->next = tso_info->tso_seg_list;
  342. tso_info->tso_seg_list = tso_seg;
  343. num_seg--;
  344. } else {
  345. struct qdf_tso_seg_elem_t *free_seg =
  346. tso_info->tso_seg_list;
  347. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  348. return QDF_STATUS_E_NOMEM;
  349. }
  350. }
  351. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  352. tso_num_seg = dp_tso_num_seg_alloc(soc,
  353. msdu_info->tx_queue.desc_pool_id);
  354. if (tso_num_seg) {
  355. tso_num_seg->next = tso_info->tso_num_seg_list;
  356. tso_info->tso_num_seg_list = tso_num_seg;
  357. } else {
  358. /* Bug: free tso_num_seg and tso_seg */
  359. /* Free the already allocated num of segments */
  360. struct qdf_tso_seg_elem_t *free_seg =
  361. tso_info->tso_seg_list;
  362. TSO_DEBUG(" %s: Failed alloc - Number of segs for a TSO packet",
  363. __func__);
  364. dp_tx_free_tso_seg(soc, free_seg, msdu_info);
  365. return QDF_STATUS_E_NOMEM;
  366. }
  367. msdu_info->num_seg =
  368. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  369. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  370. msdu_info->num_seg);
  371. if (!(msdu_info->num_seg)) {
  372. dp_tx_free_tso_seg(soc, tso_info->tso_seg_list, msdu_info);
  373. dp_tx_free_tso_num_seg(soc, tso_info->tso_num_seg_list,
  374. msdu_info);
  375. return QDF_STATUS_E_INVAL;
  376. }
  377. tso_info->curr_seg = tso_info->tso_seg_list;
  378. return QDF_STATUS_SUCCESS;
  379. }
  380. #else
  381. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  382. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  383. {
  384. return QDF_STATUS_E_NOMEM;
  385. }
  386. #endif
  387. /**
  388. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  389. * @vdev: DP Vdev handle
  390. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  391. * @desc_pool_id: Descriptor Pool ID
  392. *
  393. * Return:
  394. */
  395. static
  396. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  397. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  398. {
  399. uint8_t i;
  400. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  401. struct dp_tx_seg_info_s *seg_info;
  402. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  403. struct dp_soc *soc = vdev->pdev->soc;
  404. /* Allocate an extension descriptor */
  405. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  406. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  407. if (!msdu_ext_desc) {
  408. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  409. return NULL;
  410. }
  411. if (msdu_info->exception_fw &&
  412. qdf_unlikely(vdev->mesh_vdev)) {
  413. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  414. &msdu_info->meta_data[0],
  415. sizeof(struct htt_tx_msdu_desc_ext2_t));
  416. qdf_atomic_inc(&vdev->pdev->num_tx_exception);
  417. }
  418. switch (msdu_info->frm_type) {
  419. case dp_tx_frm_sg:
  420. case dp_tx_frm_me:
  421. case dp_tx_frm_raw:
  422. seg_info = msdu_info->u.sg_info.curr_seg;
  423. /* Update the buffer pointers in MSDU Extension Descriptor */
  424. for (i = 0; i < seg_info->frag_cnt; i++) {
  425. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  426. seg_info->frags[i].paddr_lo,
  427. seg_info->frags[i].paddr_hi,
  428. seg_info->frags[i].len);
  429. }
  430. break;
  431. case dp_tx_frm_tso:
  432. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  433. &cached_ext_desc[0]);
  434. break;
  435. default:
  436. break;
  437. }
  438. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  439. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  440. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  441. msdu_ext_desc->vaddr);
  442. return msdu_ext_desc;
  443. }
  444. /**
  445. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  446. * @vdev: DP vdev handle
  447. * @nbuf: skb
  448. * @desc_pool_id: Descriptor pool ID
  449. * @meta_data: Metadata to the fw
  450. * @tx_exc_metadata: Handle that holds exception path metadata
  451. * Allocate and prepare Tx descriptor with msdu information.
  452. *
  453. * Return: Pointer to Tx Descriptor on success,
  454. * NULL on failure
  455. */
  456. static
  457. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  458. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  459. struct dp_tx_msdu_info_s *msdu_info,
  460. struct cdp_tx_exception_metadata *tx_exc_metadata)
  461. {
  462. uint8_t align_pad;
  463. uint8_t is_exception = 0;
  464. uint8_t htt_hdr_size;
  465. struct ether_header *eh;
  466. struct dp_tx_desc_s *tx_desc;
  467. struct dp_pdev *pdev = vdev->pdev;
  468. struct dp_soc *soc = pdev->soc;
  469. /* Allocate software Tx descriptor */
  470. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  471. if (qdf_unlikely(!tx_desc)) {
  472. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  473. return NULL;
  474. }
  475. /* Flow control/Congestion Control counters */
  476. qdf_atomic_inc(&pdev->num_tx_outstanding);
  477. /* Initialize the SW tx descriptor */
  478. tx_desc->nbuf = nbuf;
  479. tx_desc->frm_type = dp_tx_frm_std;
  480. tx_desc->tx_encap_type = (tx_exc_metadata ?
  481. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  482. tx_desc->vdev = vdev;
  483. tx_desc->pdev = pdev;
  484. tx_desc->msdu_ext_desc = NULL;
  485. tx_desc->pkt_offset = 0;
  486. /*
  487. * For special modes (vdev_type == ocb or mesh), data frames should be
  488. * transmitted using varying transmit parameters (tx spec) which include
  489. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  490. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  491. * These frames are sent as exception packets to firmware.
  492. *
  493. * HW requirement is that metadata should always point to a
  494. * 8-byte aligned address. So we add alignment pad to start of buffer.
  495. * HTT Metadata should be ensured to be multiple of 8-bytes,
  496. * to get 8-byte aligned start address along with align_pad added
  497. *
  498. * |-----------------------------|
  499. * | |
  500. * |-----------------------------| <-----Buffer Pointer Address given
  501. * | | ^ in HW descriptor (aligned)
  502. * | HTT Metadata | |
  503. * | | |
  504. * | | | Packet Offset given in descriptor
  505. * | | |
  506. * |-----------------------------| |
  507. * | Alignment Pad | v
  508. * |-----------------------------| <----- Actual buffer start address
  509. * | SKB Data | (Unaligned)
  510. * | |
  511. * | |
  512. * | |
  513. * | |
  514. * | |
  515. * |-----------------------------|
  516. */
  517. if (qdf_unlikely((msdu_info->exception_fw)) ||
  518. (vdev->opmode == wlan_op_mode_ocb)) {
  519. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  520. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  521. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  522. "qdf_nbuf_push_head failed\n");
  523. goto failure;
  524. }
  525. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  526. msdu_info->meta_data);
  527. if (htt_hdr_size == 0)
  528. goto failure;
  529. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  530. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  531. is_exception = 1;
  532. }
  533. if (qdf_unlikely(QDF_STATUS_SUCCESS !=
  534. qdf_nbuf_map(soc->osdev, nbuf,
  535. QDF_DMA_TO_DEVICE))) {
  536. /* Handle failure */
  537. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  538. "qdf_nbuf_map failed\n");
  539. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  540. goto failure;
  541. }
  542. if (qdf_unlikely(vdev->nawds_enabled)) {
  543. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  544. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  545. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  546. is_exception = 1;
  547. }
  548. }
  549. #if !TQM_BYPASS_WAR
  550. if (is_exception || tx_exc_metadata)
  551. #endif
  552. {
  553. /* Temporary WAR due to TQM VP issues */
  554. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  555. qdf_atomic_inc(&pdev->num_tx_exception);
  556. }
  557. return tx_desc;
  558. failure:
  559. dp_tx_desc_release(tx_desc, desc_pool_id);
  560. return NULL;
  561. }
  562. /**
  563. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  564. * @vdev: DP vdev handle
  565. * @nbuf: skb
  566. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  567. * @desc_pool_id : Descriptor Pool ID
  568. *
  569. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  570. * information. For frames wth fragments, allocate and prepare
  571. * an MSDU extension descriptor
  572. *
  573. * Return: Pointer to Tx Descriptor on success,
  574. * NULL on failure
  575. */
  576. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  577. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  578. uint8_t desc_pool_id)
  579. {
  580. struct dp_tx_desc_s *tx_desc;
  581. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  582. struct dp_pdev *pdev = vdev->pdev;
  583. struct dp_soc *soc = pdev->soc;
  584. /* Allocate software Tx descriptor */
  585. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  586. if (!tx_desc) {
  587. DP_STATS_INC(vdev, tx_i.dropped.desc_na, 1);
  588. return NULL;
  589. }
  590. /* Flow control/Congestion Control counters */
  591. qdf_atomic_inc(&pdev->num_tx_outstanding);
  592. /* Initialize the SW tx descriptor */
  593. tx_desc->nbuf = nbuf;
  594. tx_desc->frm_type = msdu_info->frm_type;
  595. tx_desc->tx_encap_type = vdev->tx_encap_type;
  596. tx_desc->vdev = vdev;
  597. tx_desc->pdev = pdev;
  598. tx_desc->pkt_offset = 0;
  599. tx_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  600. tx_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  601. /* Handle scattered frames - TSO/SG/ME */
  602. /* Allocate and prepare an extension descriptor for scattered frames */
  603. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  604. if (!msdu_ext_desc) {
  605. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  606. "%s Tx Extension Descriptor Alloc Fail\n",
  607. __func__);
  608. goto failure;
  609. }
  610. #if TQM_BYPASS_WAR
  611. /* Temporary WAR due to TQM VP issues */
  612. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  613. qdf_atomic_inc(&pdev->num_tx_exception);
  614. #endif
  615. if (qdf_unlikely(msdu_info->exception_fw))
  616. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  617. tx_desc->msdu_ext_desc = msdu_ext_desc;
  618. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  619. return tx_desc;
  620. failure:
  621. dp_tx_desc_release(tx_desc, desc_pool_id);
  622. return NULL;
  623. }
  624. /**
  625. * dp_tx_prepare_raw() - Prepare RAW packet TX
  626. * @vdev: DP vdev handle
  627. * @nbuf: buffer pointer
  628. * @seg_info: Pointer to Segment info Descriptor to be prepared
  629. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  630. * descriptor
  631. *
  632. * Return:
  633. */
  634. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  635. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  636. {
  637. qdf_nbuf_t curr_nbuf = NULL;
  638. uint16_t total_len = 0;
  639. qdf_dma_addr_t paddr;
  640. int32_t i;
  641. int32_t mapped_buf_num = 0;
  642. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  643. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  644. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  645. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  646. if (qos_wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
  647. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  648. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  649. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  650. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, curr_nbuf,
  651. QDF_DMA_TO_DEVICE)) {
  652. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  653. "%s dma map error \n", __func__);
  654. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  655. mapped_buf_num = i;
  656. goto error;
  657. }
  658. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  659. seg_info->frags[i].paddr_lo = paddr;
  660. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  661. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  662. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  663. total_len += qdf_nbuf_len(curr_nbuf);
  664. }
  665. seg_info->frag_cnt = i;
  666. seg_info->total_len = total_len;
  667. seg_info->next = NULL;
  668. sg_info->curr_seg = seg_info;
  669. msdu_info->frm_type = dp_tx_frm_raw;
  670. msdu_info->num_seg = 1;
  671. return nbuf;
  672. error:
  673. i = 0;
  674. while (nbuf) {
  675. curr_nbuf = nbuf;
  676. if (i < mapped_buf_num) {
  677. qdf_nbuf_unmap(vdev->osdev, curr_nbuf, QDF_DMA_TO_DEVICE);
  678. i++;
  679. }
  680. nbuf = qdf_nbuf_next(nbuf);
  681. qdf_nbuf_free(curr_nbuf);
  682. }
  683. return NULL;
  684. }
  685. /**
  686. * dp_tx_hw_enqueue() - Enqueue to TCL HW for transmit
  687. * @soc: DP Soc Handle
  688. * @vdev: DP vdev handle
  689. * @tx_desc: Tx Descriptor Handle
  690. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  691. * @fw_metadata: Metadata to send to Target Firmware along with frame
  692. * @ring_id: Ring ID of H/W ring to which we enqueue the packet
  693. * @tx_exc_metadata: Handle that holds exception path meta data
  694. *
  695. * Gets the next free TCL HW DMA descriptor and sets up required parameters
  696. * from software Tx descriptor
  697. *
  698. * Return:
  699. */
  700. static QDF_STATUS dp_tx_hw_enqueue(struct dp_soc *soc, struct dp_vdev *vdev,
  701. struct dp_tx_desc_s *tx_desc, uint8_t tid,
  702. uint16_t fw_metadata, uint8_t ring_id,
  703. struct cdp_tx_exception_metadata
  704. *tx_exc_metadata)
  705. {
  706. uint8_t type;
  707. uint16_t length;
  708. void *hal_tx_desc, *hal_tx_desc_cached;
  709. qdf_dma_addr_t dma_addr;
  710. uint8_t cached_desc[HAL_TX_DESC_LEN_BYTES];
  711. enum cdp_sec_type sec_type = (tx_exc_metadata ?
  712. tx_exc_metadata->sec_type : vdev->sec_type);
  713. /* Return Buffer Manager ID */
  714. uint8_t bm_id = ring_id;
  715. void *hal_srng = soc->tcl_data_ring[ring_id].hal_srng;
  716. hal_tx_desc_cached = (void *) cached_desc;
  717. qdf_mem_zero_outline(hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  718. if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG) {
  719. length = HAL_TX_EXT_DESC_WITH_META_DATA;
  720. type = HAL_TX_BUF_TYPE_EXT_DESC;
  721. dma_addr = tx_desc->msdu_ext_desc->paddr;
  722. } else {
  723. length = qdf_nbuf_len(tx_desc->nbuf) - tx_desc->pkt_offset;
  724. type = HAL_TX_BUF_TYPE_BUFFER;
  725. dma_addr = qdf_nbuf_mapped_paddr_get(tx_desc->nbuf);
  726. }
  727. hal_tx_desc_set_fw_metadata(hal_tx_desc_cached, fw_metadata);
  728. hal_tx_desc_set_buf_addr(hal_tx_desc_cached,
  729. dma_addr , bm_id, tx_desc->id, type);
  730. hal_tx_desc_set_buf_length(hal_tx_desc_cached, length);
  731. hal_tx_desc_set_buf_offset(hal_tx_desc_cached, tx_desc->pkt_offset);
  732. hal_tx_desc_set_encap_type(hal_tx_desc_cached, tx_desc->tx_encap_type);
  733. hal_tx_desc_set_lmac_id(hal_tx_desc_cached,
  734. HAL_TX_DESC_DEFAULT_LMAC_ID);
  735. hal_tx_desc_set_dscp_tid_table_id(hal_tx_desc_cached,
  736. vdev->dscp_tid_map_id);
  737. hal_tx_desc_set_encrypt_type(hal_tx_desc_cached,
  738. sec_type_map[sec_type]);
  739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  740. "%s length:%d , type = %d, dma_addr %llx, offset %d desc id %u",
  741. __func__, length, type, (uint64_t)dma_addr,
  742. tx_desc->pkt_offset, tx_desc->id);
  743. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  744. hal_tx_desc_set_to_fw(hal_tx_desc_cached, 1);
  745. hal_tx_desc_set_addr_search_flags(hal_tx_desc_cached,
  746. vdev->hal_desc_addr_search_flags);
  747. /* verify checksum offload configuration*/
  748. if ((wlan_cfg_get_checksum_offload(soc->wlan_cfg_ctx)) &&
  749. ((qdf_nbuf_get_tx_cksum(tx_desc->nbuf) == QDF_NBUF_TX_CKSUM_TCP_UDP)
  750. || qdf_nbuf_is_tso(tx_desc->nbuf))) {
  751. hal_tx_desc_set_l3_checksum_en(hal_tx_desc_cached, 1);
  752. hal_tx_desc_set_l4_checksum_en(hal_tx_desc_cached, 1);
  753. }
  754. if (tid != HTT_TX_EXT_TID_INVALID)
  755. hal_tx_desc_set_hlos_tid(hal_tx_desc_cached, tid);
  756. if (tx_desc->flags & DP_TX_DESC_FLAG_MESH)
  757. hal_tx_desc_set_mesh_en(hal_tx_desc_cached, 1);
  758. /* Sync cached descriptor with HW */
  759. hal_tx_desc = hal_srng_src_get_next(soc->hal_soc, hal_srng);
  760. if (!hal_tx_desc) {
  761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  762. "%s TCL ring full ring_id:%d\n", __func__, ring_id);
  763. DP_STATS_INC(soc, tx.tcl_ring_full[ring_id], 1);
  764. DP_STATS_INC(vdev, tx_i.dropped.enqueue_fail, 1);
  765. return QDF_STATUS_E_RESOURCES;
  766. }
  767. tx_desc->flags |= DP_TX_DESC_FLAG_QUEUED_TX;
  768. hal_tx_desc_sync(hal_tx_desc_cached, hal_tx_desc);
  769. DP_STATS_INC_PKT(vdev, tx_i.processed, 1, length);
  770. /*
  771. * If one packet is enqueued in HW, PM usage count needs to be
  772. * incremented by one to prevent future runtime suspend. This
  773. * should be tied with the success of enqueuing. It will be
  774. * decremented after the packet has been sent.
  775. */
  776. hif_pm_runtime_get_noresume(soc->hif_handle);
  777. return QDF_STATUS_SUCCESS;
  778. }
  779. /**
  780. * dp_cce_classify() - Classify the frame based on CCE rules
  781. * @vdev: DP vdev handle
  782. * @nbuf: skb
  783. *
  784. * Classify frames based on CCE rules
  785. * Return: bool( true if classified,
  786. * else false)
  787. */
  788. static bool dp_cce_classify(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  789. {
  790. struct ether_header *eh = NULL;
  791. uint16_t ether_type;
  792. qdf_llc_t *llcHdr;
  793. qdf_nbuf_t nbuf_clone = NULL;
  794. qdf_dot3_qosframe_t *qos_wh = NULL;
  795. /* for mesh packets don't do any classification */
  796. if (qdf_unlikely(vdev->mesh_vdev))
  797. return false;
  798. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  799. eh = (struct ether_header *) qdf_nbuf_data(nbuf);
  800. ether_type = eh->ether_type;
  801. llcHdr = (qdf_llc_t *)(nbuf->data +
  802. sizeof(struct ether_header));
  803. } else {
  804. qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  805. /* For encrypted packets don't do any classification */
  806. if (qdf_unlikely(qos_wh->i_fc[1] & IEEE80211_FC1_WEP))
  807. return false;
  808. if (qdf_unlikely(qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS)) {
  809. if (qdf_unlikely(
  810. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_TODS &&
  811. qos_wh->i_fc[1] & QDF_IEEE80211_FC1_FROMDS)) {
  812. ether_type = *(uint16_t *)(nbuf->data
  813. + QDF_IEEE80211_4ADDR_HDR_LEN
  814. + sizeof(qdf_llc_t)
  815. - sizeof(ether_type));
  816. llcHdr = (qdf_llc_t *)(nbuf->data +
  817. QDF_IEEE80211_4ADDR_HDR_LEN);
  818. } else {
  819. ether_type = *(uint16_t *)(nbuf->data
  820. + QDF_IEEE80211_3ADDR_HDR_LEN
  821. + sizeof(qdf_llc_t)
  822. - sizeof(ether_type));
  823. llcHdr = (qdf_llc_t *)(nbuf->data +
  824. QDF_IEEE80211_3ADDR_HDR_LEN);
  825. }
  826. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr)
  827. && (ether_type ==
  828. qdf_htons(QDF_NBUF_TRAC_EAPOL_ETH_TYPE)))) {
  829. DP_STATS_INC(vdev, tx_i.cce_classified_raw, 1);
  830. return true;
  831. }
  832. }
  833. return false;
  834. }
  835. if (qdf_unlikely(DP_FRAME_IS_SNAP(llcHdr))) {
  836. ether_type = *(uint16_t *)(nbuf->data + 2*ETHER_ADDR_LEN +
  837. sizeof(*llcHdr));
  838. nbuf_clone = qdf_nbuf_clone(nbuf);
  839. if (qdf_unlikely(nbuf_clone)) {
  840. qdf_nbuf_pull_head(nbuf_clone, sizeof(*llcHdr));
  841. if (ether_type == htons(ETHERTYPE_8021Q)) {
  842. qdf_nbuf_pull_head(nbuf_clone,
  843. sizeof(qdf_net_vlanhdr_t));
  844. }
  845. }
  846. } else {
  847. if (ether_type == htons(ETHERTYPE_8021Q)) {
  848. nbuf_clone = qdf_nbuf_clone(nbuf);
  849. if (qdf_unlikely(nbuf_clone)) {
  850. qdf_nbuf_pull_head(nbuf_clone,
  851. sizeof(qdf_net_vlanhdr_t));
  852. }
  853. }
  854. }
  855. if (qdf_unlikely(nbuf_clone))
  856. nbuf = nbuf_clone;
  857. if (qdf_unlikely(qdf_nbuf_is_ipv4_eapol_pkt(nbuf)
  858. || qdf_nbuf_is_ipv4_arp_pkt(nbuf)
  859. || qdf_nbuf_is_ipv4_wapi_pkt(nbuf)
  860. || qdf_nbuf_is_ipv4_tdls_pkt(nbuf)
  861. || (qdf_nbuf_is_ipv4_pkt(nbuf)
  862. && qdf_nbuf_is_ipv4_dhcp_pkt(nbuf))
  863. || (qdf_nbuf_is_ipv6_pkt(nbuf) &&
  864. qdf_nbuf_is_ipv6_dhcp_pkt(nbuf)))) {
  865. if (qdf_unlikely(nbuf_clone != NULL))
  866. qdf_nbuf_free(nbuf_clone);
  867. return true;
  868. }
  869. if (qdf_unlikely(nbuf_clone != NULL))
  870. qdf_nbuf_free(nbuf_clone);
  871. return false;
  872. }
  873. /**
  874. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  875. * @vdev: DP vdev handle
  876. * @nbuf: skb
  877. *
  878. * Extract the DSCP or PCP information from frame and map into TID value.
  879. * Software based TID classification is required when more than 2 DSCP-TID
  880. * mapping tables are needed.
  881. * Hardware supports 2 DSCP-TID mapping tables
  882. *
  883. * Return: void
  884. */
  885. static void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  886. struct dp_tx_msdu_info_s *msdu_info)
  887. {
  888. uint8_t tos = 0, dscp_tid_override = 0;
  889. uint8_t *hdr_ptr, *L3datap;
  890. uint8_t is_mcast = 0;
  891. struct ether_header *eh = NULL;
  892. qdf_ethervlan_header_t *evh = NULL;
  893. uint16_t ether_type;
  894. qdf_llc_t *llcHdr;
  895. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  896. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  897. if (vdev->dscp_tid_map_id <= 1)
  898. return;
  899. /* for mesh packets don't do any classification */
  900. if (qdf_unlikely(vdev->mesh_vdev))
  901. return;
  902. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  903. eh = (struct ether_header *) nbuf->data;
  904. hdr_ptr = eh->ether_dhost;
  905. L3datap = hdr_ptr + sizeof(struct ether_header);
  906. } else {
  907. qdf_dot3_qosframe_t *qos_wh =
  908. (qdf_dot3_qosframe_t *) nbuf->data;
  909. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  910. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  911. return;
  912. }
  913. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  914. ether_type = eh->ether_type;
  915. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(struct ether_header));
  916. /*
  917. * Check if packet is dot3 or eth2 type.
  918. */
  919. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  920. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN +
  921. sizeof(*llcHdr));
  922. if (ether_type == htons(ETHERTYPE_8021Q)) {
  923. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  924. sizeof(*llcHdr);
  925. ether_type = (uint16_t)*(nbuf->data + 2*ETHER_ADDR_LEN
  926. + sizeof(*llcHdr) +
  927. sizeof(qdf_net_vlanhdr_t));
  928. } else {
  929. L3datap = hdr_ptr + sizeof(struct ether_header) +
  930. sizeof(*llcHdr);
  931. }
  932. } else {
  933. if (ether_type == htons(ETHERTYPE_8021Q)) {
  934. evh = (qdf_ethervlan_header_t *) eh;
  935. ether_type = evh->ether_type;
  936. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  937. }
  938. }
  939. /*
  940. * Find priority from IP TOS DSCP field
  941. */
  942. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  943. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  944. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  945. /* Only for unicast frames */
  946. if (!is_mcast) {
  947. /* send it on VO queue */
  948. msdu_info->tid = DP_VO_TID;
  949. }
  950. } else {
  951. /*
  952. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  953. * from TOS byte.
  954. */
  955. tos = ip->ip_tos;
  956. dscp_tid_override = 1;
  957. }
  958. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  959. /* TODO
  960. * use flowlabel
  961. *igmpmld cases to be handled in phase 2
  962. */
  963. unsigned long ver_pri_flowlabel;
  964. unsigned long pri;
  965. ver_pri_flowlabel = *(unsigned long *) L3datap;
  966. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  967. DP_IPV6_PRIORITY_SHIFT;
  968. tos = pri;
  969. dscp_tid_override = 1;
  970. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  971. msdu_info->tid = DP_VO_TID;
  972. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  973. /* Only for unicast frames */
  974. if (!is_mcast) {
  975. /* send ucast arp on VO queue */
  976. msdu_info->tid = DP_VO_TID;
  977. }
  978. }
  979. /*
  980. * Assign all MCAST packets to BE
  981. */
  982. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  983. if (is_mcast) {
  984. tos = 0;
  985. dscp_tid_override = 1;
  986. }
  987. }
  988. if (dscp_tid_override == 1) {
  989. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  990. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  991. }
  992. return;
  993. }
  994. #ifdef CONVERGED_TDLS_ENABLE
  995. /**
  996. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  997. * @tx_desc: TX descriptor
  998. *
  999. * Return: None
  1000. */
  1001. static void dp_tx_update_tdls_flags(struct dp_tx_desc_s *tx_desc)
  1002. {
  1003. if (tx_desc->vdev) {
  1004. if (tx_desc->vdev->is_tdls_frame)
  1005. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1006. tx_desc->vdev->is_tdls_frame = false;
  1007. }
  1008. }
  1009. /**
  1010. * dp_non_std_tx_comp_free_buff() - Free the non std tx packet buffer
  1011. * @tx_desc: TX descriptor
  1012. * @vdev: datapath vdev handle
  1013. *
  1014. * Return: None
  1015. */
  1016. static void dp_non_std_tx_comp_free_buff(struct dp_tx_desc_s *tx_desc,
  1017. struct dp_vdev *vdev)
  1018. {
  1019. struct hal_tx_completion_status ts = {0};
  1020. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1021. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  1022. if (vdev->tx_non_std_data_callback.func) {
  1023. qdf_nbuf_set_next(tx_desc->nbuf, NULL);
  1024. vdev->tx_non_std_data_callback.func(
  1025. vdev->tx_non_std_data_callback.ctxt,
  1026. nbuf, ts.status);
  1027. return;
  1028. }
  1029. }
  1030. #endif
  1031. /**
  1032. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  1033. * @vdev: DP vdev handle
  1034. * @nbuf: skb
  1035. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1036. * @meta_data: Metadata to the fw
  1037. * @tx_q: Tx queue to be used for this Tx frame
  1038. * @peer_id: peer_id of the peer in case of NAWDS frames
  1039. * @tx_exc_metadata: Handle that holds exception path metadata
  1040. *
  1041. * Return: NULL on success,
  1042. * nbuf when it fails to send
  1043. */
  1044. static qdf_nbuf_t dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1045. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  1046. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1047. {
  1048. struct dp_pdev *pdev = vdev->pdev;
  1049. struct dp_soc *soc = pdev->soc;
  1050. struct dp_tx_desc_s *tx_desc;
  1051. QDF_STATUS status;
  1052. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  1053. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1054. uint16_t htt_tcl_metadata = 0;
  1055. uint8_t tid = msdu_info->tid;
  1056. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  1057. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  1058. msdu_info, tx_exc_metadata);
  1059. if (!tx_desc) {
  1060. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1061. "%s Tx_desc prepare Fail vdev %pK queue %d\n",
  1062. __func__, vdev, tx_q->desc_pool_id);
  1063. return nbuf;
  1064. }
  1065. if (qdf_unlikely(soc->cce_disable)) {
  1066. if (dp_cce_classify(vdev, nbuf) == true) {
  1067. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1068. tid = DP_VO_TID;
  1069. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1070. }
  1071. }
  1072. dp_tx_update_tdls_flags(tx_desc);
  1073. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1074. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1075. "%s %d : HAL RING Access Failed -- %pK\n",
  1076. __func__, __LINE__, hal_srng);
  1077. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1078. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1079. goto fail_return;
  1080. }
  1081. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  1082. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1083. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  1084. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  1085. HTT_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  1086. HTT_TCL_METADATA_TYPE_PEER_BASED);
  1087. HTT_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  1088. peer_id);
  1089. } else
  1090. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1091. if (msdu_info->exception_fw) {
  1092. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1093. }
  1094. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  1095. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, tid,
  1096. htt_tcl_metadata, tx_q->ring_id, tx_exc_metadata);
  1097. if (status != QDF_STATUS_SUCCESS) {
  1098. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1099. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1100. __func__, tx_desc, tx_q->ring_id);
  1101. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1102. goto fail_return;
  1103. }
  1104. nbuf = NULL;
  1105. fail_return:
  1106. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1107. hal_srng_access_end(soc->hal_soc, hal_srng);
  1108. hif_pm_runtime_put(soc->hif_handle);
  1109. } else {
  1110. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1111. }
  1112. return nbuf;
  1113. }
  1114. /**
  1115. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  1116. * @vdev: DP vdev handle
  1117. * @nbuf: skb
  1118. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  1119. *
  1120. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  1121. *
  1122. * Return: NULL on success,
  1123. * nbuf when it fails to send
  1124. */
  1125. #if QDF_LOCK_STATS
  1126. static noinline
  1127. #else
  1128. static
  1129. #endif
  1130. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1131. struct dp_tx_msdu_info_s *msdu_info)
  1132. {
  1133. uint8_t i;
  1134. struct dp_pdev *pdev = vdev->pdev;
  1135. struct dp_soc *soc = pdev->soc;
  1136. struct dp_tx_desc_s *tx_desc;
  1137. bool is_cce_classified = false;
  1138. QDF_STATUS status;
  1139. uint16_t htt_tcl_metadata = 0;
  1140. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  1141. void *hal_srng = soc->tcl_data_ring[tx_q->ring_id].hal_srng;
  1142. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  1143. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1144. "%s %d : HAL RING Access Failed -- %pK\n",
  1145. __func__, __LINE__, hal_srng);
  1146. DP_STATS_INC(vdev, tx_i.dropped.ring_full, 1);
  1147. return nbuf;
  1148. }
  1149. if (qdf_unlikely(soc->cce_disable)) {
  1150. is_cce_classified = dp_cce_classify(vdev, nbuf);
  1151. if (is_cce_classified) {
  1152. DP_STATS_INC(vdev, tx_i.cce_classified, 1);
  1153. msdu_info->tid = DP_VO_TID;
  1154. }
  1155. }
  1156. if (msdu_info->frm_type == dp_tx_frm_me)
  1157. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1158. i = 0;
  1159. /* Print statement to track i and num_seg */
  1160. /*
  1161. * For each segment (maps to 1 MSDU) , prepare software and hardware
  1162. * descriptors using information in msdu_info
  1163. */
  1164. while (i < msdu_info->num_seg) {
  1165. /*
  1166. * Setup Tx descriptor for an MSDU, and MSDU extension
  1167. * descriptor
  1168. */
  1169. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  1170. tx_q->desc_pool_id);
  1171. if (!tx_desc) {
  1172. if (msdu_info->frm_type == dp_tx_frm_me) {
  1173. dp_tx_me_free_buf(pdev,
  1174. (void *)(msdu_info->u.sg_info
  1175. .curr_seg->frags[0].vaddr));
  1176. }
  1177. goto done;
  1178. }
  1179. if (msdu_info->frm_type == dp_tx_frm_me) {
  1180. tx_desc->me_buffer =
  1181. msdu_info->u.sg_info.curr_seg->frags[0].vaddr;
  1182. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  1183. }
  1184. if (is_cce_classified)
  1185. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1186. htt_tcl_metadata = vdev->htt_tcl_metadata;
  1187. if (msdu_info->exception_fw) {
  1188. HTT_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  1189. }
  1190. /*
  1191. * Enqueue the Tx MSDU descriptor to HW for transmit
  1192. */
  1193. status = dp_tx_hw_enqueue(soc, vdev, tx_desc, msdu_info->tid,
  1194. htt_tcl_metadata, tx_q->ring_id, NULL);
  1195. if (status != QDF_STATUS_SUCCESS) {
  1196. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1197. "%s Tx_hw_enqueue Fail tx_desc %pK queue %d\n",
  1198. __func__, tx_desc, tx_q->ring_id);
  1199. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  1200. dp_tx_me_free_buf(pdev, tx_desc->me_buffer);
  1201. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  1202. goto done;
  1203. }
  1204. /*
  1205. * TODO
  1206. * if tso_info structure can be modified to have curr_seg
  1207. * as first element, following 2 blocks of code (for TSO and SG)
  1208. * can be combined into 1
  1209. */
  1210. /*
  1211. * For frames with multiple segments (TSO, ME), jump to next
  1212. * segment.
  1213. */
  1214. if (msdu_info->frm_type == dp_tx_frm_tso) {
  1215. if (msdu_info->u.tso_info.curr_seg->next) {
  1216. msdu_info->u.tso_info.curr_seg =
  1217. msdu_info->u.tso_info.curr_seg->next;
  1218. /*
  1219. * If this is a jumbo nbuf, then increment the number of
  1220. * nbuf users for each additional segment of the msdu.
  1221. * This will ensure that the skb is freed only after
  1222. * receiving tx completion for all segments of an nbuf
  1223. */
  1224. qdf_nbuf_inc_users(nbuf);
  1225. /* Check with MCL if this is needed */
  1226. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf; */
  1227. }
  1228. }
  1229. /*
  1230. * For Multicast-Unicast converted packets,
  1231. * each converted frame (for a client) is represented as
  1232. * 1 segment
  1233. */
  1234. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  1235. (msdu_info->frm_type == dp_tx_frm_me)) {
  1236. if (msdu_info->u.sg_info.curr_seg->next) {
  1237. msdu_info->u.sg_info.curr_seg =
  1238. msdu_info->u.sg_info.curr_seg->next;
  1239. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  1240. }
  1241. }
  1242. i++;
  1243. }
  1244. nbuf = NULL;
  1245. done:
  1246. if (hif_pm_runtime_get(soc->hif_handle) == 0) {
  1247. hal_srng_access_end(soc->hal_soc, hal_srng);
  1248. hif_pm_runtime_put(soc->hif_handle);
  1249. } else {
  1250. hal_srng_access_end_reap(soc->hal_soc, hal_srng);
  1251. }
  1252. return nbuf;
  1253. }
  1254. /**
  1255. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  1256. * for SG frames
  1257. * @vdev: DP vdev handle
  1258. * @nbuf: skb
  1259. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1260. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1261. *
  1262. * Return: NULL on success,
  1263. * nbuf when it fails to send
  1264. */
  1265. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1266. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1267. {
  1268. uint32_t cur_frag, nr_frags;
  1269. qdf_dma_addr_t paddr;
  1270. struct dp_tx_sg_info_s *sg_info;
  1271. sg_info = &msdu_info->u.sg_info;
  1272. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  1273. if (QDF_STATUS_SUCCESS != qdf_nbuf_map(vdev->osdev, nbuf,
  1274. QDF_DMA_TO_DEVICE)) {
  1275. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1276. "dma map error\n");
  1277. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1278. qdf_nbuf_free(nbuf);
  1279. return NULL;
  1280. }
  1281. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1282. seg_info->frags[0].paddr_lo = paddr;
  1283. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  1284. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  1285. seg_info->frags[0].vaddr = (void *) nbuf;
  1286. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  1287. if (QDF_STATUS_E_FAILURE == qdf_nbuf_frag_map(vdev->osdev,
  1288. nbuf, 0, QDF_DMA_TO_DEVICE, cur_frag)) {
  1289. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1290. "frag dma map error\n");
  1291. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  1292. qdf_nbuf_free(nbuf);
  1293. return NULL;
  1294. }
  1295. paddr = qdf_nbuf_get_frag_paddr(nbuf, 0);
  1296. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  1297. seg_info->frags[cur_frag + 1].paddr_hi =
  1298. ((uint64_t) paddr) >> 32;
  1299. seg_info->frags[cur_frag + 1].len =
  1300. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  1301. }
  1302. seg_info->frag_cnt = (cur_frag + 1);
  1303. seg_info->total_len = qdf_nbuf_len(nbuf);
  1304. seg_info->next = NULL;
  1305. sg_info->curr_seg = seg_info;
  1306. msdu_info->frm_type = dp_tx_frm_sg;
  1307. msdu_info->num_seg = 1;
  1308. return nbuf;
  1309. }
  1310. #ifdef MESH_MODE_SUPPORT
  1311. /**
  1312. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  1313. and prepare msdu_info for mesh frames.
  1314. * @vdev: DP vdev handle
  1315. * @nbuf: skb
  1316. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  1317. *
  1318. * Return: NULL on failure,
  1319. * nbuf when extracted successfully
  1320. */
  1321. static
  1322. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1323. struct dp_tx_msdu_info_s *msdu_info)
  1324. {
  1325. struct meta_hdr_s *mhdr;
  1326. struct htt_tx_msdu_desc_ext2_t *meta_data =
  1327. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  1328. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1329. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  1330. msdu_info->exception_fw = 0;
  1331. goto remove_meta_hdr;
  1332. }
  1333. msdu_info->exception_fw = 1;
  1334. qdf_mem_set(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t), 0);
  1335. meta_data->host_tx_desc_pool = 1;
  1336. meta_data->update_peer_cache = 1;
  1337. meta_data->learning_frame = 1;
  1338. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  1339. meta_data->power = mhdr->power;
  1340. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  1341. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  1342. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  1343. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  1344. meta_data->dyn_bw = 1;
  1345. meta_data->valid_pwr = 1;
  1346. meta_data->valid_mcs_mask = 1;
  1347. meta_data->valid_nss_mask = 1;
  1348. meta_data->valid_preamble_type = 1;
  1349. meta_data->valid_retries = 1;
  1350. meta_data->valid_bw_info = 1;
  1351. }
  1352. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  1353. meta_data->encrypt_type = 0;
  1354. meta_data->valid_encrypt_type = 1;
  1355. meta_data->learning_frame = 0;
  1356. }
  1357. meta_data->valid_key_flags = 1;
  1358. meta_data->key_flags = (mhdr->keyix & 0x3);
  1359. remove_meta_hdr:
  1360. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  1361. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1362. "qdf_nbuf_pull_head failed\n");
  1363. qdf_nbuf_free(nbuf);
  1364. return NULL;
  1365. }
  1366. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  1367. msdu_info->tid = HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST;
  1368. else
  1369. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  1370. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1371. "%s , Meta hdr %0x %0x %0x %0x %0x %0x"
  1372. " tid %d to_fw %d\n",
  1373. __func__, msdu_info->meta_data[0],
  1374. msdu_info->meta_data[1],
  1375. msdu_info->meta_data[2],
  1376. msdu_info->meta_data[3],
  1377. msdu_info->meta_data[4],
  1378. msdu_info->meta_data[5],
  1379. msdu_info->tid, msdu_info->exception_fw);
  1380. return nbuf;
  1381. }
  1382. #else
  1383. static
  1384. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1385. struct dp_tx_msdu_info_s *msdu_info)
  1386. {
  1387. return nbuf;
  1388. }
  1389. #endif
  1390. #ifdef DP_FEATURE_NAWDS_TX
  1391. /**
  1392. * dp_tx_prepare_nawds(): Tramit NAWDS frames
  1393. * @vdev: dp_vdev handle
  1394. * @nbuf: skb
  1395. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  1396. * @tx_q: Tx queue to be used for this Tx frame
  1397. * @meta_data: Meta date for mesh
  1398. * @peer_id: peer_id of the peer in case of NAWDS frames
  1399. *
  1400. * return: NULL on success nbuf on failure
  1401. */
  1402. static qdf_nbuf_t dp_tx_prepare_nawds(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1403. struct dp_tx_msdu_info_s *msdu_info)
  1404. {
  1405. struct dp_peer *peer = NULL;
  1406. struct dp_soc *soc = vdev->pdev->soc;
  1407. struct dp_ast_entry *ast_entry = NULL;
  1408. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1409. uint16_t peer_id = HTT_INVALID_PEER;
  1410. struct dp_peer *sa_peer = NULL;
  1411. qdf_nbuf_t nbuf_copy;
  1412. qdf_spin_lock_bh(&(soc->ast_lock));
  1413. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1414. if (ast_entry)
  1415. sa_peer = ast_entry->peer;
  1416. qdf_spin_unlock_bh(&(soc->ast_lock));
  1417. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1418. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1419. (peer->nawds_enabled)) {
  1420. if (sa_peer == peer) {
  1421. QDF_TRACE(QDF_MODULE_ID_DP,
  1422. QDF_TRACE_LEVEL_DEBUG,
  1423. " %s: broadcast multicast packet",
  1424. __func__);
  1425. DP_STATS_INC(peer, tx.nawds_mcast_drop, 1);
  1426. continue;
  1427. }
  1428. nbuf_copy = qdf_nbuf_copy(nbuf);
  1429. if (!nbuf_copy) {
  1430. QDF_TRACE(QDF_MODULE_ID_DP,
  1431. QDF_TRACE_LEVEL_ERROR,
  1432. "nbuf copy failed");
  1433. }
  1434. peer_id = peer->peer_ids[0];
  1435. nbuf_copy = dp_tx_send_msdu_single(vdev, nbuf_copy,
  1436. msdu_info, peer_id, NULL);
  1437. if (nbuf_copy != NULL) {
  1438. qdf_nbuf_free(nbuf_copy);
  1439. continue;
  1440. }
  1441. DP_STATS_INC_PKT(peer, tx.nawds_mcast,
  1442. 1, qdf_nbuf_len(nbuf));
  1443. }
  1444. }
  1445. if (peer_id == HTT_INVALID_PEER)
  1446. return nbuf;
  1447. return NULL;
  1448. }
  1449. #endif
  1450. /**
  1451. * dp_check_exc_metadata() - Checks if parameters are valid
  1452. * @tx_exc - holds all exception path parameters
  1453. *
  1454. * Returns true when all the parameters are valid else false
  1455. *
  1456. */
  1457. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  1458. {
  1459. if ((tx_exc->tid > DP_MAX_TIDS && tx_exc->tid != HTT_INVALID_TID) ||
  1460. tx_exc->tx_encap_type > htt_cmn_pkt_num_types ||
  1461. tx_exc->sec_type > cdp_num_sec_types) {
  1462. return false;
  1463. }
  1464. return true;
  1465. }
  1466. /**
  1467. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  1468. * @vap_dev: DP vdev handle
  1469. * @nbuf: skb
  1470. * @tx_exc_metadata: Handle that holds exception path meta data
  1471. *
  1472. * Entry point for Core Tx layer (DP_TX) invoked from
  1473. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  1474. *
  1475. * Return: NULL on success,
  1476. * nbuf when it fails to send
  1477. */
  1478. qdf_nbuf_t dp_tx_send_exception(void *vap_dev, qdf_nbuf_t nbuf,
  1479. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1480. {
  1481. struct ether_header *eh = NULL;
  1482. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1483. struct dp_tx_msdu_info_s msdu_info;
  1484. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1485. msdu_info.tid = tx_exc_metadata->tid;
  1486. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1487. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1488. "%s , skb %pM",
  1489. __func__, nbuf->data);
  1490. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1491. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  1492. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1493. "Invalid parameters in exception path");
  1494. goto fail;
  1495. }
  1496. /* Basic sanity checks for unsupported packets */
  1497. /* MESH mode */
  1498. if (qdf_unlikely(vdev->mesh_vdev)) {
  1499. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1500. "Mesh mode is not supported in exception path");
  1501. goto fail;
  1502. }
  1503. /* TSO or SG */
  1504. if (qdf_unlikely(qdf_nbuf_is_tso(nbuf)) ||
  1505. qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1506. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1507. "TSO and SG are not supported in exception path");
  1508. goto fail;
  1509. }
  1510. /* RAW */
  1511. if (qdf_unlikely(tx_exc_metadata->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1512. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1513. "Raw frame is not supported in exception path");
  1514. goto fail;
  1515. }
  1516. /* Mcast enhancement*/
  1517. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1518. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1519. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1520. "Ignoring mcast_enhancement_en which is set and sending the mcast packet to the FW\n");
  1521. }
  1522. }
  1523. /*
  1524. * Get HW Queue to use for this frame.
  1525. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1526. * dedicated for data and 1 for command.
  1527. * "queue_id" maps to one hardware ring.
  1528. * With each ring, we also associate a unique Tx descriptor pool
  1529. * to minimize lock contention for these resources.
  1530. */
  1531. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1532. /* Reset the control block */
  1533. qdf_nbuf_reset_ctxt(nbuf);
  1534. /* Single linear frame */
  1535. /*
  1536. * If nbuf is a simple linear frame, use send_single function to
  1537. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1538. * SRNG. There is no need to setup a MSDU extension descriptor.
  1539. */
  1540. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  1541. tx_exc_metadata->peer_id, tx_exc_metadata);
  1542. return nbuf;
  1543. fail:
  1544. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1545. "pkt send failed");
  1546. return nbuf;
  1547. }
  1548. /**
  1549. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  1550. * @vap_dev: DP vdev handle
  1551. * @nbuf: skb
  1552. *
  1553. * Entry point for Core Tx layer (DP_TX) invoked from
  1554. * hard_start_xmit in OSIF/HDD
  1555. *
  1556. * Return: NULL on success,
  1557. * nbuf when it fails to send
  1558. */
  1559. #ifdef MESH_MODE_SUPPORT
  1560. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1561. {
  1562. struct meta_hdr_s *mhdr;
  1563. qdf_nbuf_t nbuf_mesh = NULL;
  1564. qdf_nbuf_t nbuf_clone = NULL;
  1565. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1566. uint8_t no_enc_frame = 0;
  1567. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  1568. if (nbuf_mesh == NULL) {
  1569. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1570. "qdf_nbuf_unshare failed\n");
  1571. return nbuf;
  1572. }
  1573. nbuf = nbuf_mesh;
  1574. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  1575. if ((vdev->sec_type != cdp_sec_type_none) &&
  1576. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  1577. no_enc_frame = 1;
  1578. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  1579. !no_enc_frame) {
  1580. nbuf_clone = qdf_nbuf_clone(nbuf);
  1581. if (nbuf_clone == NULL) {
  1582. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1583. "qdf_nbuf_clone failed\n");
  1584. return nbuf;
  1585. }
  1586. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  1587. }
  1588. if (nbuf_clone) {
  1589. if (!dp_tx_send(vap_dev, nbuf_clone)) {
  1590. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1591. } else
  1592. qdf_nbuf_free(nbuf_clone);
  1593. }
  1594. if (no_enc_frame)
  1595. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  1596. else
  1597. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  1598. nbuf = dp_tx_send(vap_dev, nbuf);
  1599. if ((nbuf == NULL) && no_enc_frame) {
  1600. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  1601. }
  1602. return nbuf;
  1603. }
  1604. #else
  1605. qdf_nbuf_t dp_tx_send_mesh(void *vap_dev, qdf_nbuf_t nbuf)
  1606. {
  1607. return dp_tx_send(vap_dev, nbuf);
  1608. }
  1609. #endif
  1610. /**
  1611. * dp_tx_send() - Transmit a frame on a given VAP
  1612. * @vap_dev: DP vdev handle
  1613. * @nbuf: skb
  1614. *
  1615. * Entry point for Core Tx layer (DP_TX) invoked from
  1616. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  1617. * cases
  1618. *
  1619. * Return: NULL on success,
  1620. * nbuf when it fails to send
  1621. */
  1622. qdf_nbuf_t dp_tx_send(void *vap_dev, qdf_nbuf_t nbuf)
  1623. {
  1624. struct ether_header *eh = NULL;
  1625. struct dp_tx_msdu_info_s msdu_info;
  1626. struct dp_tx_seg_info_s seg_info;
  1627. struct dp_vdev *vdev = (struct dp_vdev *) vap_dev;
  1628. uint16_t peer_id = HTT_INVALID_PEER;
  1629. qdf_nbuf_t nbuf_mesh = NULL;
  1630. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1631. qdf_mem_set(&seg_info, sizeof(seg_info), 0x0);
  1632. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1633. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1634. "%s , skb %pM",
  1635. __func__, nbuf->data);
  1636. /*
  1637. * Set Default Host TID value to invalid TID
  1638. * (TID override disabled)
  1639. */
  1640. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  1641. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  1642. if (qdf_unlikely(vdev->mesh_vdev)) {
  1643. nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  1644. &msdu_info);
  1645. if (nbuf_mesh == NULL) {
  1646. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1647. "Extracting mesh metadata failed\n");
  1648. return nbuf;
  1649. }
  1650. nbuf = nbuf_mesh;
  1651. }
  1652. /*
  1653. * Get HW Queue to use for this frame.
  1654. * TCL supports upto 4 DMA rings, out of which 3 rings are
  1655. * dedicated for data and 1 for command.
  1656. * "queue_id" maps to one hardware ring.
  1657. * With each ring, we also associate a unique Tx descriptor pool
  1658. * to minimize lock contention for these resources.
  1659. */
  1660. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1661. /*
  1662. * TCL H/W supports 2 DSCP-TID mapping tables.
  1663. * Table 1 - Default DSCP-TID mapping table
  1664. * Table 2 - 1 DSCP-TID override table
  1665. *
  1666. * If we need a different DSCP-TID mapping for this vap,
  1667. * call tid_classify to extract DSCP/ToS from frame and
  1668. * map to a TID and store in msdu_info. This is later used
  1669. * to fill in TCL Input descriptor (per-packet TID override).
  1670. */
  1671. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  1672. /* Reset the control block */
  1673. qdf_nbuf_reset_ctxt(nbuf);
  1674. /*
  1675. * Classify the frame and call corresponding
  1676. * "prepare" function which extracts the segment (TSO)
  1677. * and fragmentation information (for TSO , SG, ME, or Raw)
  1678. * into MSDU_INFO structure which is later used to fill
  1679. * SW and HW descriptors.
  1680. */
  1681. if (qdf_nbuf_is_tso(nbuf)) {
  1682. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1683. "%s TSO frame %pK\n", __func__, vdev);
  1684. DP_STATS_INC_PKT(vdev, tx_i.tso.tso_pkt, 1,
  1685. qdf_nbuf_len(nbuf));
  1686. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  1687. DP_STATS_INC(vdev, tx_i.tso.dropped_host, 1);
  1688. return nbuf;
  1689. }
  1690. goto send_multiple;
  1691. }
  1692. /* SG */
  1693. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  1694. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  1695. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1696. "%s non-TSO SG frame %pK\n", __func__, vdev);
  1697. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  1698. qdf_nbuf_len(nbuf));
  1699. goto send_multiple;
  1700. }
  1701. #ifdef ATH_SUPPORT_IQUE
  1702. /* Mcast to Ucast Conversion*/
  1703. if (qdf_unlikely(vdev->mcast_enhancement_en > 0)) {
  1704. eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1705. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  1706. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1707. "%s Mcast frm for ME %pK\n", __func__, vdev);
  1708. DP_STATS_INC_PKT(vdev,
  1709. tx_i.mcast_en.mcast_pkt, 1,
  1710. qdf_nbuf_len(nbuf));
  1711. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  1712. QDF_STATUS_SUCCESS) {
  1713. return NULL;
  1714. }
  1715. }
  1716. }
  1717. #endif
  1718. /* RAW */
  1719. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  1720. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  1721. if (nbuf == NULL)
  1722. return NULL;
  1723. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1724. "%s Raw frame %pK\n", __func__, vdev);
  1725. goto send_multiple;
  1726. }
  1727. /* Single linear frame */
  1728. /*
  1729. * If nbuf is a simple linear frame, use send_single function to
  1730. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  1731. * SRNG. There is no need to setup a MSDU extension descriptor.
  1732. */
  1733. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info, peer_id, NULL);
  1734. return nbuf;
  1735. send_multiple:
  1736. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  1737. return nbuf;
  1738. }
  1739. /**
  1740. * dp_tx_reinject_handler() - Tx Reinject Handler
  1741. * @tx_desc: software descriptor head pointer
  1742. * @status : Tx completion status from HTT descriptor
  1743. *
  1744. * This function reinjects frames back to Target.
  1745. * Todo - Host queue needs to be added
  1746. *
  1747. * Return: none
  1748. */
  1749. static
  1750. void dp_tx_reinject_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1751. {
  1752. struct dp_vdev *vdev;
  1753. struct dp_peer *peer = NULL;
  1754. uint32_t peer_id = HTT_INVALID_PEER;
  1755. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1756. qdf_nbuf_t nbuf_copy = NULL;
  1757. struct dp_tx_msdu_info_s msdu_info;
  1758. struct dp_peer *sa_peer = NULL;
  1759. struct dp_ast_entry *ast_entry = NULL;
  1760. struct dp_soc *soc = NULL;
  1761. struct ether_header *eh = (struct ether_header *)qdf_nbuf_data(nbuf);
  1762. #ifdef WDS_VENDOR_EXTENSION
  1763. int is_mcast = 0, is_ucast = 0;
  1764. int num_peers_3addr = 0;
  1765. struct ether_header *eth_hdr = (struct ether_header *)(qdf_nbuf_data(nbuf));
  1766. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  1767. #endif
  1768. vdev = tx_desc->vdev;
  1769. soc = vdev->pdev->soc;
  1770. qdf_assert(vdev);
  1771. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  1772. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  1773. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1774. "%s Tx reinject path\n", __func__);
  1775. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  1776. qdf_nbuf_len(tx_desc->nbuf));
  1777. qdf_spin_lock_bh(&(soc->ast_lock));
  1778. ast_entry = dp_peer_ast_hash_find(soc, (uint8_t *)(eh->ether_shost));
  1779. if (ast_entry)
  1780. sa_peer = ast_entry->peer;
  1781. qdf_spin_unlock_bh(&(soc->ast_lock));
  1782. #ifdef WDS_VENDOR_EXTENSION
  1783. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1784. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  1785. } else {
  1786. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  1787. }
  1788. is_ucast = !is_mcast;
  1789. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1790. if (peer->bss_peer)
  1791. continue;
  1792. /* Detect wds peers that use 3-addr framing for mcast.
  1793. * if there are any, the bss_peer is used to send the
  1794. * the mcast frame using 3-addr format. all wds enabled
  1795. * peers that use 4-addr framing for mcast frames will
  1796. * be duplicated and sent as 4-addr frames below.
  1797. */
  1798. if (!peer->wds_enabled || !peer->wds_ecm.wds_tx_mcast_4addr) {
  1799. num_peers_3addr = 1;
  1800. break;
  1801. }
  1802. }
  1803. #endif
  1804. if (qdf_unlikely(vdev->mesh_vdev)) {
  1805. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  1806. } else {
  1807. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  1808. if ((peer->peer_ids[0] != HTT_INVALID_PEER) &&
  1809. #ifdef WDS_VENDOR_EXTENSION
  1810. /*
  1811. * . if 3-addr STA, then send on BSS Peer
  1812. * . if Peer WDS enabled and accept 4-addr mcast,
  1813. * send mcast on that peer only
  1814. * . if Peer WDS enabled and accept 4-addr ucast,
  1815. * send ucast on that peer only
  1816. */
  1817. ((peer->bss_peer && num_peers_3addr && is_mcast) ||
  1818. (peer->wds_enabled &&
  1819. ((is_mcast && peer->wds_ecm.wds_tx_mcast_4addr) ||
  1820. (is_ucast && peer->wds_ecm.wds_tx_ucast_4addr))))) {
  1821. #else
  1822. ((peer->bss_peer &&
  1823. !(vdev->osif_proxy_arp(vdev->osif_vdev, nbuf))) ||
  1824. peer->nawds_enabled)) {
  1825. #endif
  1826. peer_id = DP_INVALID_PEER;
  1827. if (peer->nawds_enabled) {
  1828. peer_id = peer->peer_ids[0];
  1829. if (sa_peer == peer) {
  1830. QDF_TRACE(
  1831. QDF_MODULE_ID_DP,
  1832. QDF_TRACE_LEVEL_DEBUG,
  1833. " %s: multicast packet",
  1834. __func__);
  1835. DP_STATS_INC(peer,
  1836. tx.nawds_mcast_drop, 1);
  1837. continue;
  1838. }
  1839. }
  1840. nbuf_copy = qdf_nbuf_copy(nbuf);
  1841. if (!nbuf_copy) {
  1842. QDF_TRACE(QDF_MODULE_ID_DP,
  1843. QDF_TRACE_LEVEL_DEBUG,
  1844. FL("nbuf copy failed"));
  1845. break;
  1846. }
  1847. nbuf_copy = dp_tx_send_msdu_single(vdev,
  1848. nbuf_copy,
  1849. &msdu_info,
  1850. peer_id,
  1851. NULL);
  1852. if (nbuf_copy) {
  1853. QDF_TRACE(QDF_MODULE_ID_DP,
  1854. QDF_TRACE_LEVEL_DEBUG,
  1855. FL("pkt send failed"));
  1856. qdf_nbuf_free(nbuf_copy);
  1857. } else {
  1858. if (peer_id != DP_INVALID_PEER)
  1859. DP_STATS_INC_PKT(peer,
  1860. tx.nawds_mcast,
  1861. 1, qdf_nbuf_len(nbuf));
  1862. }
  1863. }
  1864. }
  1865. }
  1866. if (vdev->nawds_enabled) {
  1867. peer_id = DP_INVALID_PEER;
  1868. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  1869. 1, qdf_nbuf_len(nbuf));
  1870. nbuf = dp_tx_send_msdu_single(vdev,
  1871. nbuf,
  1872. &msdu_info,
  1873. peer_id, NULL);
  1874. if (nbuf) {
  1875. QDF_TRACE(QDF_MODULE_ID_DP,
  1876. QDF_TRACE_LEVEL_DEBUG,
  1877. FL("pkt send failed"));
  1878. qdf_nbuf_free(nbuf);
  1879. }
  1880. } else
  1881. qdf_nbuf_free(nbuf);
  1882. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1883. }
  1884. /**
  1885. * dp_tx_inspect_handler() - Tx Inspect Handler
  1886. * @tx_desc: software descriptor head pointer
  1887. * @status : Tx completion status from HTT descriptor
  1888. *
  1889. * Handles Tx frames sent back to Host for inspection
  1890. * (ProxyARP)
  1891. *
  1892. * Return: none
  1893. */
  1894. static void dp_tx_inspect_handler(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  1895. {
  1896. struct dp_soc *soc;
  1897. struct dp_pdev *pdev = tx_desc->pdev;
  1898. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  1899. "%s Tx inspect path\n",
  1900. __func__);
  1901. qdf_assert(pdev);
  1902. soc = pdev->soc;
  1903. DP_STATS_INC_PKT(tx_desc->vdev, tx_i.inspect_pkts, 1,
  1904. qdf_nbuf_len(tx_desc->nbuf));
  1905. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  1906. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  1907. }
  1908. #ifdef FEATURE_PERPKT_INFO
  1909. /**
  1910. * dp_get_completion_indication_for_stack() - send completion to stack
  1911. * @soc : dp_soc handle
  1912. * @pdev: dp_pdev handle
  1913. * @peer_id: peer_id of the peer for which completion came
  1914. * @ppdu_id: ppdu_id
  1915. * @first_msdu: first msdu
  1916. * @last_msdu: last msdu
  1917. * @netbuf: Buffer pointer for free
  1918. *
  1919. * This function is used for indication whether buffer needs to be
  1920. * send to stack for free or not
  1921. */
  1922. QDF_STATUS
  1923. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1924. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1925. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1926. {
  1927. struct tx_capture_hdr *ppdu_hdr;
  1928. struct dp_peer *peer = NULL;
  1929. if (qdf_unlikely(!pdev->tx_sniffer_enable && !pdev->mcopy_mode))
  1930. return QDF_STATUS_E_NOSUPPORT;
  1931. peer = (peer_id == HTT_INVALID_PEER) ? NULL :
  1932. dp_peer_find_by_id(soc, peer_id);
  1933. if (!peer) {
  1934. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1935. FL("Peer Invalid"));
  1936. return QDF_STATUS_E_INVAL;
  1937. }
  1938. if (pdev->mcopy_mode) {
  1939. if ((pdev->m_copy_id.tx_ppdu_id == ppdu_id) &&
  1940. (pdev->m_copy_id.tx_peer_id == peer_id)) {
  1941. return QDF_STATUS_E_INVAL;
  1942. }
  1943. pdev->m_copy_id.tx_ppdu_id = ppdu_id;
  1944. pdev->m_copy_id.tx_peer_id = peer_id;
  1945. }
  1946. if (!qdf_nbuf_push_head(netbuf, sizeof(struct tx_capture_hdr))) {
  1947. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1948. FL("No headroom"));
  1949. return QDF_STATUS_E_NOMEM;
  1950. }
  1951. ppdu_hdr = (struct tx_capture_hdr *)qdf_nbuf_data(netbuf);
  1952. qdf_mem_copy(ppdu_hdr->ta, peer->vdev->mac_addr.raw,
  1953. IEEE80211_ADDR_LEN);
  1954. ppdu_hdr->ppdu_id = ppdu_id;
  1955. qdf_mem_copy(ppdu_hdr->ra, peer->mac_addr.raw,
  1956. IEEE80211_ADDR_LEN);
  1957. ppdu_hdr->peer_id = peer_id;
  1958. ppdu_hdr->first_msdu = first_msdu;
  1959. ppdu_hdr->last_msdu = last_msdu;
  1960. return QDF_STATUS_SUCCESS;
  1961. }
  1962. /**
  1963. * dp_send_completion_to_stack() - send completion to stack
  1964. * @soc : dp_soc handle
  1965. * @pdev: dp_pdev handle
  1966. * @peer_id: peer_id of the peer for which completion came
  1967. * @ppdu_id: ppdu_id
  1968. * @netbuf: Buffer pointer for free
  1969. *
  1970. * This function is used to send completion to stack
  1971. * to free buffer
  1972. */
  1973. void dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1974. uint16_t peer_id, uint32_t ppdu_id,
  1975. qdf_nbuf_t netbuf)
  1976. {
  1977. dp_wdi_event_handler(WDI_EVENT_TX_DATA, soc,
  1978. netbuf, peer_id,
  1979. WDI_NO_VAL, pdev->pdev_id);
  1980. }
  1981. #else
  1982. static QDF_STATUS
  1983. dp_get_completion_indication_for_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1984. uint16_t peer_id, uint32_t ppdu_id, uint8_t first_msdu,
  1985. uint8_t last_msdu, qdf_nbuf_t netbuf)
  1986. {
  1987. return QDF_STATUS_E_NOSUPPORT;
  1988. }
  1989. static void
  1990. dp_send_completion_to_stack(struct dp_soc *soc, struct dp_pdev *pdev,
  1991. uint16_t peer_id, uint32_t ppdu_id, qdf_nbuf_t netbuf)
  1992. {
  1993. }
  1994. #endif
  1995. /**
  1996. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  1997. * @soc: Soc handle
  1998. * @desc: software Tx descriptor to be processed
  1999. *
  2000. * Return: none
  2001. */
  2002. static inline void dp_tx_comp_free_buf(struct dp_soc *soc,
  2003. struct dp_tx_desc_s *desc)
  2004. {
  2005. struct dp_vdev *vdev = desc->vdev;
  2006. qdf_nbuf_t nbuf = desc->nbuf;
  2007. /* If it is TDLS mgmt, don't unmap or free the frame */
  2008. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)
  2009. return dp_non_std_tx_comp_free_buff(desc, vdev);
  2010. /* 0 : MSDU buffer, 1 : MLE */
  2011. if (desc->msdu_ext_desc) {
  2012. /* TSO free */
  2013. if (hal_tx_ext_desc_get_tso_enable(
  2014. desc->msdu_ext_desc->vaddr)) {
  2015. /* If remaining number of segment is 0
  2016. * actual TSO may unmap and free */
  2017. if (qdf_nbuf_get_users(nbuf) == 1)
  2018. __qdf_nbuf_unmap_single(soc->osdev,
  2019. nbuf,
  2020. QDF_DMA_TO_DEVICE);
  2021. qdf_nbuf_free(nbuf);
  2022. return;
  2023. }
  2024. }
  2025. qdf_nbuf_unmap(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2026. if (qdf_likely(!vdev->mesh_vdev))
  2027. qdf_nbuf_free(nbuf);
  2028. else {
  2029. if (desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  2030. qdf_nbuf_free(nbuf);
  2031. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  2032. } else
  2033. vdev->osif_tx_free_ext((nbuf));
  2034. }
  2035. }
  2036. /**
  2037. * dp_tx_mec_handler() - Tx MEC Notify Handler
  2038. * @vdev: pointer to dp dev handler
  2039. * @status : Tx completion status from HTT descriptor
  2040. *
  2041. * Handles MEC notify event sent from fw to Host
  2042. *
  2043. * Return: none
  2044. */
  2045. #ifdef FEATURE_WDS
  2046. void dp_tx_mec_handler(struct dp_vdev *vdev, uint8_t *status)
  2047. {
  2048. struct dp_soc *soc;
  2049. uint32_t flags = IEEE80211_NODE_F_WDS_HM;
  2050. struct dp_peer *peer;
  2051. uint8_t mac_addr[DP_MAC_ADDR_LEN], i;
  2052. if (!vdev->wds_enabled)
  2053. return;
  2054. soc = vdev->pdev->soc;
  2055. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2056. peer = TAILQ_FIRST(&vdev->peer_list);
  2057. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2058. if (!peer) {
  2059. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2060. FL("peer is NULL"));
  2061. return;
  2062. }
  2063. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2064. "%s Tx MEC Handler\n",
  2065. __func__);
  2066. for (i = 0; i < DP_MAC_ADDR_LEN; i++)
  2067. mac_addr[(DP_MAC_ADDR_LEN - 1) - i] =
  2068. status[(DP_MAC_ADDR_LEN - 2) + i];
  2069. if (qdf_mem_cmp(mac_addr, vdev->mac_addr.raw, DP_MAC_ADDR_LEN))
  2070. dp_peer_add_ast(soc,
  2071. peer,
  2072. mac_addr,
  2073. CDP_TXRX_AST_TYPE_MEC,
  2074. flags);
  2075. }
  2076. #endif
  2077. /**
  2078. * dp_tx_process_htt_completion() - Tx HTT Completion Indication Handler
  2079. * @tx_desc: software descriptor head pointer
  2080. * @status : Tx completion status from HTT descriptor
  2081. *
  2082. * This function will process HTT Tx indication messages from Target
  2083. *
  2084. * Return: none
  2085. */
  2086. static
  2087. void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
  2088. {
  2089. uint8_t tx_status;
  2090. struct dp_pdev *pdev;
  2091. struct dp_vdev *vdev;
  2092. struct dp_soc *soc;
  2093. uint32_t *htt_status_word = (uint32_t *) status;
  2094. qdf_assert(tx_desc->pdev);
  2095. pdev = tx_desc->pdev;
  2096. vdev = tx_desc->vdev;
  2097. soc = pdev->soc;
  2098. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_status_word[0]);
  2099. switch (tx_status) {
  2100. case HTT_TX_FW2WBM_TX_STATUS_OK:
  2101. case HTT_TX_FW2WBM_TX_STATUS_DROP:
  2102. case HTT_TX_FW2WBM_TX_STATUS_TTL:
  2103. {
  2104. dp_tx_comp_free_buf(soc, tx_desc);
  2105. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  2106. break;
  2107. }
  2108. case HTT_TX_FW2WBM_TX_STATUS_REINJECT:
  2109. {
  2110. dp_tx_reinject_handler(tx_desc, status);
  2111. break;
  2112. }
  2113. case HTT_TX_FW2WBM_TX_STATUS_INSPECT:
  2114. {
  2115. dp_tx_inspect_handler(tx_desc, status);
  2116. break;
  2117. }
  2118. case HTT_TX_FW2WBM_TX_STATUS_MEC_NOTIFY:
  2119. {
  2120. dp_tx_mec_handler(vdev, status);
  2121. break;
  2122. }
  2123. default:
  2124. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2125. "%s Invalid HTT tx_status %d\n",
  2126. __func__, tx_status);
  2127. break;
  2128. }
  2129. }
  2130. #ifdef MESH_MODE_SUPPORT
  2131. /**
  2132. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  2133. * in mesh meta header
  2134. * @tx_desc: software descriptor head pointer
  2135. * @ts: pointer to tx completion stats
  2136. * Return: none
  2137. */
  2138. static
  2139. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2140. struct hal_tx_completion_status *ts)
  2141. {
  2142. struct meta_hdr_s *mhdr;
  2143. qdf_nbuf_t netbuf = tx_desc->nbuf;
  2144. if (!tx_desc->msdu_ext_desc) {
  2145. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  2146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2147. "netbuf %pK offset %d\n",
  2148. netbuf, tx_desc->pkt_offset);
  2149. return;
  2150. }
  2151. }
  2152. if (qdf_nbuf_push_head(netbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2153. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2154. "netbuf %pK offset %d\n", netbuf,
  2155. sizeof(struct meta_hdr_s));
  2156. return;
  2157. }
  2158. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(netbuf);
  2159. mhdr->rssi = ts->ack_frame_rssi;
  2160. mhdr->channel = tx_desc->pdev->operating_channel;
  2161. }
  2162. #else
  2163. static
  2164. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  2165. struct hal_tx_completion_status *ts)
  2166. {
  2167. }
  2168. #endif
  2169. /**
  2170. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  2171. * @peer: Handle to DP peer
  2172. * @ts: pointer to HAL Tx completion stats
  2173. * @length: MSDU length
  2174. *
  2175. * Return: None
  2176. */
  2177. static void dp_tx_update_peer_stats(struct dp_peer *peer,
  2178. struct hal_tx_completion_status *ts, uint32_t length)
  2179. {
  2180. struct dp_pdev *pdev = peer->vdev->pdev;
  2181. struct dp_soc *soc = pdev->soc;
  2182. uint8_t mcs, pkt_type;
  2183. mcs = ts->mcs;
  2184. pkt_type = ts->pkt_type;
  2185. if (!ts->release_src == HAL_TX_COMP_RELEASE_SOURCE_TQM)
  2186. return;
  2187. if (peer->bss_peer) {
  2188. DP_STATS_INC_PKT(peer, tx.mcast, 1, length);
  2189. } else {
  2190. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  2191. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2192. }
  2193. DP_STATS_INC_PKT(peer, tx.ucast, 1, length);
  2194. }
  2195. DP_STATS_INCC(peer, tx.dropped.age_out, 1,
  2196. (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED));
  2197. DP_STATS_INCC(peer, tx.dropped.fw_rem, 1,
  2198. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  2199. DP_STATS_INCC(peer, tx.dropped.fw_rem_notx, 1,
  2200. (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX));
  2201. DP_STATS_INCC(peer, tx.dropped.fw_rem_tx, 1,
  2202. (ts->status == HAL_TX_TQM_RR_REM_CMD_TX));
  2203. DP_STATS_INCC(peer, tx.dropped.fw_reason1, 1,
  2204. (ts->status == HAL_TX_TQM_RR_FW_REASON1));
  2205. DP_STATS_INCC(peer, tx.dropped.fw_reason2, 1,
  2206. (ts->status == HAL_TX_TQM_RR_FW_REASON2));
  2207. DP_STATS_INCC(peer, tx.dropped.fw_reason3, 1,
  2208. (ts->status == HAL_TX_TQM_RR_FW_REASON3));
  2209. if (!ts->status == HAL_TX_TQM_RR_FRAME_ACKED)
  2210. return;
  2211. DP_STATS_INCC(peer, tx.ofdma, 1, ts->ofdma);
  2212. DP_STATS_INCC(peer, tx.amsdu_cnt, 1, ts->msdu_part_of_amsdu);
  2213. DP_STATS_INCC(peer, tx.non_amsdu_cnt, 1, !ts->msdu_part_of_amsdu);
  2214. if (!(soc->process_tx_status))
  2215. return;
  2216. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2217. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_A)));
  2218. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2219. ((mcs < (MAX_MCS_11A)) && (pkt_type == DOT11_A)));
  2220. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2221. ((mcs >= MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2222. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2223. ((mcs < MAX_MCS_11B) && (pkt_type == DOT11_B)));
  2224. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2225. ((mcs >= MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2226. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2227. ((mcs < MAX_MCS_11A) && (pkt_type == DOT11_N)));
  2228. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2229. ((mcs >= MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2230. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2231. ((mcs < MAX_MCS_11AC) && (pkt_type == DOT11_AC)));
  2232. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[MAX_MCS - 1], 1,
  2233. ((mcs >= (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2234. DP_STATS_INCC(peer, tx.pkt_type[pkt_type].mcs_count[mcs], 1,
  2235. ((mcs < (MAX_MCS - 1)) && (pkt_type == DOT11_AX)));
  2236. DP_STATS_INC(peer, tx.sgi_count[ts->sgi], 1);
  2237. DP_STATS_INC(peer, tx.bw[ts->bw], 1);
  2238. DP_STATS_UPD(peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  2239. DP_STATS_INC(peer, tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  2240. DP_STATS_INCC(peer, tx.stbc, 1, ts->stbc);
  2241. DP_STATS_INCC(peer, tx.ldpc, 1, ts->ldpc);
  2242. DP_STATS_INC_PKT(peer, tx.tx_success, 1, length);
  2243. DP_STATS_INCC(peer, tx.retries, 1, ts->transmit_cnt > 1);
  2244. if (soc->cdp_soc.ol_ops->update_dp_stats) {
  2245. soc->cdp_soc.ol_ops->update_dp_stats(pdev->osif_pdev,
  2246. &peer->stats, ts->peer_id,
  2247. UPDATE_PEER_STATS);
  2248. }
  2249. }
  2250. /**
  2251. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  2252. * @tx_desc: software descriptor head pointer
  2253. * @length: packet length
  2254. *
  2255. * Return: none
  2256. */
  2257. static inline void dp_tx_comp_process_tx_status(struct dp_tx_desc_s *tx_desc,
  2258. uint32_t length)
  2259. {
  2260. struct hal_tx_completion_status ts;
  2261. struct dp_soc *soc = NULL;
  2262. struct dp_vdev *vdev = tx_desc->vdev;
  2263. struct dp_peer *peer = NULL;
  2264. struct ether_header *eh =
  2265. (struct ether_header *)qdf_nbuf_data(tx_desc->nbuf);
  2266. hal_tx_comp_get_status(&tx_desc->comp, &ts);
  2267. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2268. "-------------------- \n"
  2269. "Tx Completion Stats: \n"
  2270. "-------------------- \n"
  2271. "ack_frame_rssi = %d \n"
  2272. "first_msdu = %d \n"
  2273. "last_msdu = %d \n"
  2274. "msdu_part_of_amsdu = %d \n"
  2275. "rate_stats valid = %d \n"
  2276. "bw = %d \n"
  2277. "pkt_type = %d \n"
  2278. "stbc = %d \n"
  2279. "ldpc = %d \n"
  2280. "sgi = %d \n"
  2281. "mcs = %d \n"
  2282. "ofdma = %d \n"
  2283. "tones_in_ru = %d \n"
  2284. "tsf = %d \n"
  2285. "ppdu_id = %d \n"
  2286. "transmit_cnt = %d \n"
  2287. "tid = %d \n"
  2288. "peer_id = %d \n",
  2289. ts.ack_frame_rssi, ts.first_msdu, ts.last_msdu,
  2290. ts.msdu_part_of_amsdu, ts.valid, ts.bw,
  2291. ts.pkt_type, ts.stbc, ts.ldpc, ts.sgi,
  2292. ts.mcs, ts.ofdma, ts.tones_in_ru, ts.tsf,
  2293. ts.ppdu_id, ts.transmit_cnt, ts.tid,
  2294. ts.peer_id);
  2295. if (!vdev) {
  2296. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2297. "invalid vdev");
  2298. goto out;
  2299. }
  2300. soc = vdev->pdev->soc;
  2301. /* Update SoC level stats */
  2302. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  2303. (ts.status == HAL_TX_TQM_RR_REM_CMD_REM));
  2304. /* Update per-packet stats */
  2305. if (qdf_unlikely(vdev->mesh_vdev) &&
  2306. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  2307. dp_tx_comp_fill_tx_completion_stats(tx_desc, &ts);
  2308. /* Update peer level stats */
  2309. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2310. if (!peer) {
  2311. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2312. "invalid peer");
  2313. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  2314. goto out;
  2315. }
  2316. if (qdf_likely(peer->vdev->tx_encap_type ==
  2317. htt_cmn_pkt_type_ethernet)) {
  2318. if (peer->bss_peer && IEEE80211_IS_BROADCAST(eh->ether_dhost))
  2319. DP_STATS_INC_PKT(peer, tx.bcast, 1, length);
  2320. }
  2321. dp_tx_update_peer_stats(peer, &ts, length);
  2322. out:
  2323. return;
  2324. }
  2325. /**
  2326. * dp_tx_comp_process_desc() - Tx complete software descriptor handler
  2327. * @soc: core txrx main context
  2328. * @comp_head: software descriptor head pointer
  2329. *
  2330. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  2331. * and release the software descriptors after processing is complete
  2332. *
  2333. * Return: none
  2334. */
  2335. static void dp_tx_comp_process_desc(struct dp_soc *soc,
  2336. struct dp_tx_desc_s *comp_head)
  2337. {
  2338. struct dp_tx_desc_s *desc;
  2339. struct dp_tx_desc_s *next;
  2340. struct hal_tx_completion_status ts = {0};
  2341. uint32_t length;
  2342. struct dp_peer *peer;
  2343. DP_HIST_INIT();
  2344. desc = comp_head;
  2345. while (desc) {
  2346. hal_tx_comp_get_status(&desc->comp, &ts);
  2347. peer = dp_peer_find_by_id(soc, ts.peer_id);
  2348. length = qdf_nbuf_len(desc->nbuf);
  2349. dp_tx_comp_process_tx_status(desc, length);
  2350. /*currently m_copy/tx_capture is not supported for scatter gather packets*/
  2351. if (!(desc->msdu_ext_desc) && (dp_get_completion_indication_for_stack(soc,
  2352. desc->pdev, ts.peer_id, ts.ppdu_id,
  2353. ts.first_msdu, ts.last_msdu,
  2354. desc->nbuf) == QDF_STATUS_SUCCESS)) {
  2355. qdf_nbuf_unmap(soc->osdev, desc->nbuf,
  2356. QDF_DMA_TO_DEVICE);
  2357. dp_send_completion_to_stack(soc, desc->pdev, ts.peer_id,
  2358. ts.ppdu_id, desc->nbuf);
  2359. } else {
  2360. dp_tx_comp_free_buf(soc, desc);
  2361. }
  2362. DP_HIST_PACKET_COUNT_INC(desc->pdev->pdev_id);
  2363. next = desc->next;
  2364. dp_tx_desc_release(desc, desc->pool_id);
  2365. desc = next;
  2366. }
  2367. DP_TX_HIST_STATS_PER_PDEV();
  2368. }
  2369. /**
  2370. * dp_tx_comp_handler() - Tx completion handler
  2371. * @soc: core txrx main context
  2372. * @ring_id: completion ring id
  2373. * @quota: No. of packets/descriptors that can be serviced in one loop
  2374. *
  2375. * This function will collect hardware release ring element contents and
  2376. * handle descriptor contents. Based on contents, free packet or handle error
  2377. * conditions
  2378. *
  2379. * Return: none
  2380. */
  2381. uint32_t dp_tx_comp_handler(struct dp_soc *soc, void *hal_srng, uint32_t quota)
  2382. {
  2383. void *tx_comp_hal_desc;
  2384. uint8_t buffer_src;
  2385. uint8_t pool_id;
  2386. uint32_t tx_desc_id;
  2387. struct dp_tx_desc_s *tx_desc = NULL;
  2388. struct dp_tx_desc_s *head_desc = NULL;
  2389. struct dp_tx_desc_s *tail_desc = NULL;
  2390. uint32_t num_processed;
  2391. uint32_t count;
  2392. if (qdf_unlikely(hal_srng_access_start(soc->hal_soc, hal_srng))) {
  2393. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2394. "%s %d : HAL RING Access Failed -- %pK\n",
  2395. __func__, __LINE__, hal_srng);
  2396. return 0;
  2397. }
  2398. num_processed = 0;
  2399. count = 0;
  2400. /* Find head descriptor from completion ring */
  2401. while (qdf_likely(tx_comp_hal_desc =
  2402. hal_srng_dst_get_next(soc->hal_soc, hal_srng))) {
  2403. buffer_src = hal_tx_comp_get_buffer_source(tx_comp_hal_desc);
  2404. /* If this buffer was not released by TQM or FW, then it is not
  2405. * Tx completion indication, assert */
  2406. if ((buffer_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  2407. (buffer_src != HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2408. QDF_TRACE(QDF_MODULE_ID_DP,
  2409. QDF_TRACE_LEVEL_FATAL,
  2410. "Tx comp release_src != TQM | FW");
  2411. qdf_assert_always(0);
  2412. }
  2413. /* Get descriptor id */
  2414. tx_desc_id = hal_tx_comp_get_desc_id(tx_comp_hal_desc);
  2415. pool_id = (tx_desc_id & DP_TX_DESC_ID_POOL_MASK) >>
  2416. DP_TX_DESC_ID_POOL_OS;
  2417. /* Pool ID is out of limit. Error */
  2418. if (pool_id > wlan_cfg_get_num_tx_desc_pool(
  2419. soc->wlan_cfg_ctx)) {
  2420. QDF_TRACE(QDF_MODULE_ID_DP,
  2421. QDF_TRACE_LEVEL_FATAL,
  2422. "Tx Comp pool id %d not valid",
  2423. pool_id);
  2424. qdf_assert_always(0);
  2425. }
  2426. /* Find Tx descriptor */
  2427. tx_desc = dp_tx_desc_find(soc, pool_id,
  2428. (tx_desc_id & DP_TX_DESC_ID_PAGE_MASK) >>
  2429. DP_TX_DESC_ID_PAGE_OS,
  2430. (tx_desc_id & DP_TX_DESC_ID_OFFSET_MASK) >>
  2431. DP_TX_DESC_ID_OFFSET_OS);
  2432. /*
  2433. * If the release source is FW, process the HTT status
  2434. */
  2435. if (qdf_unlikely(buffer_src ==
  2436. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  2437. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  2438. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  2439. htt_tx_status);
  2440. dp_tx_process_htt_completion(tx_desc,
  2441. htt_tx_status);
  2442. } else {
  2443. /* Pool id is not matching. Error */
  2444. if (tx_desc->pool_id != pool_id) {
  2445. QDF_TRACE(QDF_MODULE_ID_DP,
  2446. QDF_TRACE_LEVEL_FATAL,
  2447. "Tx Comp pool id %d not matched %d",
  2448. pool_id, tx_desc->pool_id);
  2449. qdf_assert_always(0);
  2450. }
  2451. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  2452. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  2453. QDF_TRACE(QDF_MODULE_ID_DP,
  2454. QDF_TRACE_LEVEL_FATAL,
  2455. "Txdesc invalid, flgs = %x,id = %d",
  2456. tx_desc->flags, tx_desc_id);
  2457. qdf_assert_always(0);
  2458. }
  2459. /* First ring descriptor on the cycle */
  2460. if (!head_desc) {
  2461. head_desc = tx_desc;
  2462. tail_desc = tx_desc;
  2463. }
  2464. tail_desc->next = tx_desc;
  2465. tx_desc->next = NULL;
  2466. tail_desc = tx_desc;
  2467. /* Collect hw completion contents */
  2468. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  2469. &tx_desc->comp, 1);
  2470. }
  2471. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  2472. /* Decrement PM usage count if the packet has been sent.*/
  2473. hif_pm_runtime_put(soc->hif_handle);
  2474. /*
  2475. * Processed packet count is more than given quota
  2476. * stop to processing
  2477. */
  2478. if ((num_processed >= quota))
  2479. break;
  2480. count++;
  2481. }
  2482. hal_srng_access_end(soc->hal_soc, hal_srng);
  2483. /* Process the reaped descriptors */
  2484. if (head_desc)
  2485. dp_tx_comp_process_desc(soc, head_desc);
  2486. return num_processed;
  2487. }
  2488. #ifdef CONVERGED_TDLS_ENABLE
  2489. /**
  2490. * dp_tx_non_std() - Allow the control-path SW to send data frames
  2491. *
  2492. * @data_vdev - which vdev should transmit the tx data frames
  2493. * @tx_spec - what non-standard handling to apply to the tx data frames
  2494. * @msdu_list - NULL-terminated list of tx MSDUs
  2495. *
  2496. * Return: NULL on success,
  2497. * nbuf when it fails to send
  2498. */
  2499. qdf_nbuf_t dp_tx_non_std(struct cdp_vdev *vdev_handle,
  2500. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  2501. {
  2502. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2503. if (tx_spec & OL_TX_SPEC_NO_FREE)
  2504. vdev->is_tdls_frame = true;
  2505. return dp_tx_send(vdev_handle, msdu_list);
  2506. }
  2507. #endif
  2508. /**
  2509. * dp_tx_vdev_attach() - attach vdev to dp tx
  2510. * @vdev: virtual device instance
  2511. *
  2512. * Return: QDF_STATUS_SUCCESS: success
  2513. * QDF_STATUS_E_RESOURCES: Error return
  2514. */
  2515. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  2516. {
  2517. /*
  2518. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  2519. */
  2520. HTT_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  2521. HTT_TCL_METADATA_TYPE_VDEV_BASED);
  2522. HTT_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  2523. vdev->vdev_id);
  2524. HTT_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata,
  2525. DP_SW2HW_MACID(vdev->pdev->pdev_id));
  2526. /*
  2527. * Set HTT Extension Valid bit to 0 by default
  2528. */
  2529. HTT_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  2530. dp_tx_vdev_update_search_flags(vdev);
  2531. return QDF_STATUS_SUCCESS;
  2532. }
  2533. /**
  2534. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  2535. * @vdev: virtual device instance
  2536. *
  2537. * Return: void
  2538. *
  2539. */
  2540. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  2541. {
  2542. /*
  2543. * Enable both AddrY (SA based search) and AddrX (Da based search)
  2544. * for TDLS link
  2545. *
  2546. * Enable AddrY (SA based search) only for non-WDS STA and
  2547. * ProxySTA VAP modes.
  2548. *
  2549. * In all other VAP modes, only DA based search should be
  2550. * enabled
  2551. */
  2552. if (vdev->opmode == wlan_op_mode_sta &&
  2553. vdev->tdls_link_connected)
  2554. vdev->hal_desc_addr_search_flags =
  2555. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  2556. else if ((vdev->opmode == wlan_op_mode_sta &&
  2557. (!vdev->wds_enabled || vdev->proxysta_vdev)))
  2558. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  2559. else
  2560. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  2561. }
  2562. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2563. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2564. {
  2565. }
  2566. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2567. /* dp_tx_desc_flush() - release resources associated
  2568. * to tx_desc
  2569. * @vdev: virtual device instance
  2570. *
  2571. * This function will free all outstanding Tx buffers,
  2572. * including ME buffer for which either free during
  2573. * completion didn't happened or completion is not
  2574. * received.
  2575. */
  2576. static void dp_tx_desc_flush(struct dp_vdev *vdev)
  2577. {
  2578. uint8_t i, num_pool;
  2579. uint32_t j;
  2580. uint32_t num_desc;
  2581. struct dp_soc *soc = vdev->pdev->soc;
  2582. struct dp_tx_desc_s *tx_desc = NULL;
  2583. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  2584. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2585. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2586. for (i = 0; i < num_pool; i++) {
  2587. for (j = 0; j < num_desc; j++) {
  2588. tx_desc_pool = &((soc)->tx_desc[(i)]);
  2589. if (tx_desc_pool &&
  2590. tx_desc_pool->desc_pages.cacheable_pages) {
  2591. tx_desc = dp_tx_desc_find(soc, i,
  2592. (j & DP_TX_DESC_ID_PAGE_MASK) >>
  2593. DP_TX_DESC_ID_PAGE_OS,
  2594. (j & DP_TX_DESC_ID_OFFSET_MASK) >>
  2595. DP_TX_DESC_ID_OFFSET_OS);
  2596. if (tx_desc && (tx_desc->vdev == vdev) &&
  2597. (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)) {
  2598. dp_tx_comp_free_buf(soc, tx_desc);
  2599. dp_tx_desc_release(tx_desc, i);
  2600. }
  2601. }
  2602. }
  2603. }
  2604. }
  2605. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2606. /**
  2607. * dp_tx_vdev_detach() - detach vdev from dp tx
  2608. * @vdev: virtual device instance
  2609. *
  2610. * Return: QDF_STATUS_SUCCESS: success
  2611. * QDF_STATUS_E_RESOURCES: Error return
  2612. */
  2613. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  2614. {
  2615. dp_tx_desc_flush(vdev);
  2616. return QDF_STATUS_SUCCESS;
  2617. }
  2618. /**
  2619. * dp_tx_pdev_attach() - attach pdev to dp tx
  2620. * @pdev: physical device instance
  2621. *
  2622. * Return: QDF_STATUS_SUCCESS: success
  2623. * QDF_STATUS_E_RESOURCES: Error return
  2624. */
  2625. QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
  2626. {
  2627. struct dp_soc *soc = pdev->soc;
  2628. /* Initialize Flow control counters */
  2629. qdf_atomic_init(&pdev->num_tx_exception);
  2630. qdf_atomic_init(&pdev->num_tx_outstanding);
  2631. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2632. /* Initialize descriptors in TCL Ring */
  2633. hal_tx_init_data_ring(soc->hal_soc,
  2634. soc->tcl_data_ring[pdev->pdev_id].hal_srng);
  2635. }
  2636. return QDF_STATUS_SUCCESS;
  2637. }
  2638. /**
  2639. * dp_tx_pdev_detach() - detach pdev from dp tx
  2640. * @pdev: physical device instance
  2641. *
  2642. * Return: QDF_STATUS_SUCCESS: success
  2643. * QDF_STATUS_E_RESOURCES: Error return
  2644. */
  2645. QDF_STATUS dp_tx_pdev_detach(struct dp_pdev *pdev)
  2646. {
  2647. dp_tx_me_exit(pdev);
  2648. return QDF_STATUS_SUCCESS;
  2649. }
  2650. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  2651. /* Pools will be allocated dynamically */
  2652. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2653. int num_desc)
  2654. {
  2655. uint8_t i;
  2656. for (i = 0; i < num_pool; i++) {
  2657. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  2658. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  2659. }
  2660. return 0;
  2661. }
  2662. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2663. {
  2664. uint8_t i;
  2665. for (i = 0; i < num_pool; i++)
  2666. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  2667. }
  2668. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  2669. static int dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  2670. int num_desc)
  2671. {
  2672. uint8_t i;
  2673. /* Allocate software Tx descriptor pools */
  2674. for (i = 0; i < num_pool; i++) {
  2675. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  2676. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2677. "%s Tx Desc Pool alloc %d failed %pK\n",
  2678. __func__, i, soc);
  2679. return ENOMEM;
  2680. }
  2681. }
  2682. return 0;
  2683. }
  2684. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  2685. {
  2686. uint8_t i;
  2687. for (i = 0; i < num_pool; i++) {
  2688. qdf_assert_always(!soc->tx_desc[i].num_allocated);
  2689. if (dp_tx_desc_pool_free(soc, i)) {
  2690. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2691. "%s Tx Desc Pool Free failed\n", __func__);
  2692. }
  2693. }
  2694. }
  2695. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  2696. /**
  2697. * dp_tx_soc_detach() - detach soc from dp tx
  2698. * @soc: core txrx main context
  2699. *
  2700. * This function will detach dp tx into main device context
  2701. * will free dp tx resource and initialize resources
  2702. *
  2703. * Return: QDF_STATUS_SUCCESS: success
  2704. * QDF_STATUS_E_RESOURCES: Error return
  2705. */
  2706. QDF_STATUS dp_tx_soc_detach(struct dp_soc *soc)
  2707. {
  2708. uint8_t num_pool;
  2709. uint16_t num_desc;
  2710. uint16_t num_ext_desc;
  2711. uint8_t i;
  2712. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2713. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2714. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2715. dp_tx_flow_control_deinit(soc);
  2716. dp_tx_delete_static_pools(soc, num_pool);
  2717. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2718. "%s Tx Desc Pool Free num_pool = %d, descs = %d\n",
  2719. __func__, num_pool, num_desc);
  2720. for (i = 0; i < num_pool; i++) {
  2721. if (dp_tx_ext_desc_pool_free(soc, i)) {
  2722. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2723. "%s Tx Ext Desc Pool Free failed\n",
  2724. __func__);
  2725. return QDF_STATUS_E_RESOURCES;
  2726. }
  2727. }
  2728. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2729. "%s MSDU Ext Desc Pool %d Free descs = %d\n",
  2730. __func__, num_pool, num_ext_desc);
  2731. for (i = 0; i < num_pool; i++) {
  2732. dp_tx_tso_desc_pool_free(soc, i);
  2733. }
  2734. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2735. "%s TSO Desc Pool %d Free descs = %d\n",
  2736. __func__, num_pool, num_desc);
  2737. for (i = 0; i < num_pool; i++)
  2738. dp_tx_tso_num_seg_pool_free(soc, i);
  2739. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2740. "%s TSO Num of seg Desc Pool %d Free descs = %d\n",
  2741. __func__, num_pool, num_desc);
  2742. return QDF_STATUS_SUCCESS;
  2743. }
  2744. /**
  2745. * dp_tx_soc_attach() - attach soc to dp tx
  2746. * @soc: core txrx main context
  2747. *
  2748. * This function will attach dp tx into main device context
  2749. * will allocate dp tx resource and initialize resources
  2750. *
  2751. * Return: QDF_STATUS_SUCCESS: success
  2752. * QDF_STATUS_E_RESOURCES: Error return
  2753. */
  2754. QDF_STATUS dp_tx_soc_attach(struct dp_soc *soc)
  2755. {
  2756. uint8_t i;
  2757. uint8_t num_pool;
  2758. uint32_t num_desc;
  2759. uint32_t num_ext_desc;
  2760. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  2761. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  2762. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  2763. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  2764. goto fail;
  2765. dp_tx_flow_control_init(soc);
  2766. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2767. "%s Tx Desc Alloc num_pool = %d, descs = %d\n",
  2768. __func__, num_pool, num_desc);
  2769. /* Allocate extension tx descriptor pools */
  2770. for (i = 0; i < num_pool; i++) {
  2771. if (dp_tx_ext_desc_pool_alloc(soc, i, num_ext_desc)) {
  2772. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2773. "MSDU Ext Desc Pool alloc %d failed %pK\n",
  2774. i, soc);
  2775. goto fail;
  2776. }
  2777. }
  2778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2779. "%s MSDU Ext Desc Alloc %d, descs = %d\n",
  2780. __func__, num_pool, num_ext_desc);
  2781. for (i = 0; i < num_pool; i++) {
  2782. if (dp_tx_tso_desc_pool_alloc(soc, i, num_desc)) {
  2783. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2784. "TSO Desc Pool alloc %d failed %pK\n",
  2785. i, soc);
  2786. goto fail;
  2787. }
  2788. }
  2789. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2790. "%s TSO Desc Alloc %d, descs = %d\n",
  2791. __func__, num_pool, num_desc);
  2792. for (i = 0; i < num_pool; i++) {
  2793. if (dp_tx_tso_num_seg_pool_alloc(soc, i, num_desc)) {
  2794. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2795. "TSO Num of seg Pool alloc %d failed %pK\n",
  2796. i, soc);
  2797. goto fail;
  2798. }
  2799. }
  2800. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2801. "%s TSO Num of seg pool Alloc %d, descs = %d\n",
  2802. __func__, num_pool, num_desc);
  2803. /* Initialize descriptors in TCL Rings */
  2804. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2805. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2806. hal_tx_init_data_ring(soc->hal_soc,
  2807. soc->tcl_data_ring[i].hal_srng);
  2808. }
  2809. }
  2810. /*
  2811. * todo - Add a runtime config option to enable this.
  2812. */
  2813. /*
  2814. * Due to multiple issues on NPR EMU, enable it selectively
  2815. * only for NPR EMU, should be removed, once NPR platforms
  2816. * are stable.
  2817. */
  2818. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  2819. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2820. "%s HAL Tx init Success\n", __func__);
  2821. return QDF_STATUS_SUCCESS;
  2822. fail:
  2823. /* Detach will take care of freeing only allocated resources */
  2824. dp_tx_soc_detach(soc);
  2825. return QDF_STATUS_E_RESOURCES;
  2826. }
  2827. /*
  2828. * dp_tx_me_mem_free(): Function to free allocated memory in mcast enahncement
  2829. * pdev: pointer to DP PDEV structure
  2830. * seg_info_head: Pointer to the head of list
  2831. *
  2832. * return: void
  2833. */
  2834. static void dp_tx_me_mem_free(struct dp_pdev *pdev,
  2835. struct dp_tx_seg_info_s *seg_info_head)
  2836. {
  2837. struct dp_tx_me_buf_t *mc_uc_buf;
  2838. struct dp_tx_seg_info_s *seg_info_new = NULL;
  2839. qdf_nbuf_t nbuf = NULL;
  2840. uint64_t phy_addr;
  2841. while (seg_info_head) {
  2842. nbuf = seg_info_head->nbuf;
  2843. mc_uc_buf = (struct dp_tx_me_buf_t *)
  2844. seg_info_head->frags[0].vaddr;
  2845. phy_addr = seg_info_head->frags[0].paddr_hi;
  2846. phy_addr = (phy_addr << 32) | seg_info_head->frags[0].paddr_lo;
  2847. qdf_mem_unmap_nbytes_single(pdev->soc->osdev,
  2848. phy_addr,
  2849. QDF_DMA_TO_DEVICE , DP_MAC_ADDR_LEN);
  2850. dp_tx_me_free_buf(pdev, mc_uc_buf);
  2851. qdf_nbuf_free(nbuf);
  2852. seg_info_new = seg_info_head;
  2853. seg_info_head = seg_info_head->next;
  2854. qdf_mem_free(seg_info_new);
  2855. }
  2856. }
  2857. /**
  2858. * dp_tx_me_send_convert_ucast(): function to convert multicast to unicast
  2859. * @vdev: DP VDEV handle
  2860. * @nbuf: Multicast nbuf
  2861. * @newmac: Table of the clients to which packets have to be sent
  2862. * @new_mac_cnt: No of clients
  2863. *
  2864. * return: no of converted packets
  2865. */
  2866. uint16_t
  2867. dp_tx_me_send_convert_ucast(struct cdp_vdev *vdev_handle, qdf_nbuf_t nbuf,
  2868. uint8_t newmac[][DP_MAC_ADDR_LEN], uint8_t new_mac_cnt)
  2869. {
  2870. struct dp_vdev *vdev = (struct dp_vdev *) vdev_handle;
  2871. struct dp_pdev *pdev = vdev->pdev;
  2872. struct ether_header *eh;
  2873. uint8_t *data;
  2874. uint16_t len;
  2875. /* reference to frame dst addr */
  2876. uint8_t *dstmac;
  2877. /* copy of original frame src addr */
  2878. uint8_t srcmac[DP_MAC_ADDR_LEN];
  2879. /* local index into newmac */
  2880. uint8_t new_mac_idx = 0;
  2881. struct dp_tx_me_buf_t *mc_uc_buf;
  2882. qdf_nbuf_t nbuf_clone;
  2883. struct dp_tx_msdu_info_s msdu_info;
  2884. struct dp_tx_seg_info_s *seg_info_head = NULL;
  2885. struct dp_tx_seg_info_s *seg_info_tail = NULL;
  2886. struct dp_tx_seg_info_s *seg_info_new;
  2887. struct dp_tx_frag_info_s data_frag;
  2888. qdf_dma_addr_t paddr_data;
  2889. qdf_dma_addr_t paddr_mcbuf = 0;
  2890. uint8_t empty_entry_mac[DP_MAC_ADDR_LEN] = {0};
  2891. QDF_STATUS status;
  2892. qdf_mem_set(&msdu_info, sizeof(msdu_info), 0x0);
  2893. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2894. eh = (struct ether_header *) nbuf;
  2895. qdf_mem_copy(srcmac, eh->ether_shost, DP_MAC_ADDR_LEN);
  2896. len = qdf_nbuf_len(nbuf);
  2897. data = qdf_nbuf_data(nbuf);
  2898. status = qdf_nbuf_map(vdev->osdev, nbuf,
  2899. QDF_DMA_TO_DEVICE);
  2900. if (status) {
  2901. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2902. "Mapping failure Error:%d", status);
  2903. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2904. qdf_nbuf_free(nbuf);
  2905. return 1;
  2906. }
  2907. paddr_data = qdf_nbuf_get_frag_paddr(nbuf, 0) + IEEE80211_ADDR_LEN;
  2908. /*preparing data fragment*/
  2909. data_frag.vaddr = qdf_nbuf_data(nbuf) + IEEE80211_ADDR_LEN;
  2910. data_frag.paddr_lo = (uint32_t)paddr_data;
  2911. data_frag.paddr_hi = (((uint64_t) paddr_data) >> 32);
  2912. data_frag.len = len - DP_MAC_ADDR_LEN;
  2913. for (new_mac_idx = 0; new_mac_idx < new_mac_cnt; new_mac_idx++) {
  2914. dstmac = newmac[new_mac_idx];
  2915. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2916. "added mac addr (%pM)", dstmac);
  2917. /* Check for NULL Mac Address */
  2918. if (!qdf_mem_cmp(dstmac, empty_entry_mac, DP_MAC_ADDR_LEN))
  2919. continue;
  2920. /* frame to self mac. skip */
  2921. if (!qdf_mem_cmp(dstmac, srcmac, DP_MAC_ADDR_LEN))
  2922. continue;
  2923. /*
  2924. * TODO: optimize to avoid malloc in per-packet path
  2925. * For eg. seg_pool can be made part of vdev structure
  2926. */
  2927. seg_info_new = qdf_mem_malloc(sizeof(*seg_info_new));
  2928. if (!seg_info_new) {
  2929. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2930. "alloc failed");
  2931. DP_STATS_INC(vdev, tx_i.mcast_en.fail_seg_alloc, 1);
  2932. goto fail_seg_alloc;
  2933. }
  2934. mc_uc_buf = dp_tx_me_alloc_buf(pdev);
  2935. if (mc_uc_buf == NULL)
  2936. goto fail_buf_alloc;
  2937. /*
  2938. * TODO: Check if we need to clone the nbuf
  2939. * Or can we just use the reference for all cases
  2940. */
  2941. if (new_mac_idx < (new_mac_cnt - 1)) {
  2942. nbuf_clone = qdf_nbuf_clone((qdf_nbuf_t)nbuf);
  2943. if (nbuf_clone == NULL) {
  2944. DP_STATS_INC(vdev, tx_i.mcast_en.clone_fail, 1);
  2945. goto fail_clone;
  2946. }
  2947. } else {
  2948. /*
  2949. * Update the ref
  2950. * to account for frame sent without cloning
  2951. */
  2952. qdf_nbuf_ref(nbuf);
  2953. nbuf_clone = nbuf;
  2954. }
  2955. qdf_mem_copy(mc_uc_buf->data, dstmac, DP_MAC_ADDR_LEN);
  2956. status = qdf_mem_map_nbytes_single(vdev->osdev, mc_uc_buf->data,
  2957. QDF_DMA_TO_DEVICE, DP_MAC_ADDR_LEN,
  2958. &paddr_mcbuf);
  2959. if (status) {
  2960. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2961. "Mapping failure Error:%d", status);
  2962. DP_STATS_INC(vdev, tx_i.mcast_en.dropped_map_error, 1);
  2963. goto fail_map;
  2964. }
  2965. seg_info_new->frags[0].vaddr = (uint8_t *)mc_uc_buf;
  2966. seg_info_new->frags[0].paddr_lo = (uint32_t) paddr_mcbuf;
  2967. seg_info_new->frags[0].paddr_hi =
  2968. ((uint64_t) paddr_mcbuf >> 32);
  2969. seg_info_new->frags[0].len = DP_MAC_ADDR_LEN;
  2970. seg_info_new->frags[1] = data_frag;
  2971. seg_info_new->nbuf = nbuf_clone;
  2972. seg_info_new->frag_cnt = 2;
  2973. seg_info_new->total_len = len;
  2974. seg_info_new->next = NULL;
  2975. if (seg_info_head == NULL)
  2976. seg_info_head = seg_info_new;
  2977. else
  2978. seg_info_tail->next = seg_info_new;
  2979. seg_info_tail = seg_info_new;
  2980. }
  2981. if (!seg_info_head) {
  2982. goto free_return;
  2983. }
  2984. msdu_info.u.sg_info.curr_seg = seg_info_head;
  2985. msdu_info.num_seg = new_mac_cnt;
  2986. msdu_info.frm_type = dp_tx_frm_me;
  2987. DP_STATS_INC(vdev, tx_i.mcast_en.ucast, new_mac_cnt);
  2988. dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2989. while (seg_info_head->next) {
  2990. seg_info_new = seg_info_head;
  2991. seg_info_head = seg_info_head->next;
  2992. qdf_mem_free(seg_info_new);
  2993. }
  2994. qdf_mem_free(seg_info_head);
  2995. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  2996. qdf_nbuf_free(nbuf);
  2997. return new_mac_cnt;
  2998. fail_map:
  2999. qdf_nbuf_free(nbuf_clone);
  3000. fail_clone:
  3001. dp_tx_me_free_buf(pdev, mc_uc_buf);
  3002. fail_buf_alloc:
  3003. qdf_mem_free(seg_info_new);
  3004. fail_seg_alloc:
  3005. dp_tx_me_mem_free(pdev, seg_info_head);
  3006. free_return:
  3007. qdf_nbuf_unmap(pdev->soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  3008. qdf_nbuf_free(nbuf);
  3009. return 1;
  3010. }