2c06a656a5
Add the PPE related DP APIs Change-Id: I25aeff73fef21a7a8ad0f0e6e8aa6c537a233029 CRs-Fixed: 3045340
458 行
13 KiB
C
458 行
13 KiB
C
/*
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* Copyright (c) 2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_9224_TX_H_
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#define _HAL_9224_TX_H_
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#include "tcl_data_cmd.h"
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#include "phyrx_rssi_legacy.h"
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#include "hal_internal.h"
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#include "qdf_trace.h"
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#include "hal_rx.h"
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#include "hal_tx.h"
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#include "hal_api_mon.h"
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#include <hal_be_tx.h>
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#define DSCP_TID_TABLE_SIZE 24
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#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
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#define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
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/**
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* hal_tx_set_dscp_tid_map_9224() - Configure default DSCP to TID map table
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id: mapping table ID - 0-31
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*
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* DSCP are mapped to 8 TID values using TID values programmed
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* in any of the 32 DSCP_TID_MAPS (id = 0-31).
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*
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* Return: none
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*/
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static void hal_tx_set_dscp_tid_map_9224(struct hal_soc *hal_soc, uint8_t *map,
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uint8_t id)
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{
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int i;
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uint32_t addr, cmn_reg_addr;
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uint32_t value = 0, regval;
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uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS)
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return;
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cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
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MAC_TCL_REG_REG_BASE);
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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MAC_TCL_REG_REG_BASE,
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id * NUM_WORDS_PER_DSCP_TID_TABLE);
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/* Enable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval |=
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(1 <<
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HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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/* Write 8 (24 bits) DSCP-TID mappings in each interation */
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for (i = 0; i < 64; i += 8) {
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value = (map[i] |
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(map[i + 1] << 0x3) |
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(map[i + 2] << 0x6) |
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(map[i + 3] << 0x9) |
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(map[i + 4] << 0xc) |
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(map[i + 5] << 0xf) |
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(map[i + 6] << 0x12) |
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(map[i + 7] << 0x15));
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qdf_mem_copy(&val[cnt], (void *)&value, 3);
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cnt += 3;
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}
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for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
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regval = *(uint32_t *)(val + i);
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HAL_REG_WRITE(soc, addr,
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(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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addr += 4;
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}
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/* Diasble read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval &=
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~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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}
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/**
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* hal_tx_update_dscp_tid_9224() - Update the dscp tid map table as updated
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* by the user
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id : MAP ID
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* @dscp: DSCP_TID map index
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*
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* Return: void
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*/
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static void hal_tx_update_dscp_tid_9224(struct hal_soc *soc, uint8_t tid,
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uint8_t id, uint8_t dscp)
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{
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uint32_t addr, addr1, cmn_reg_addr;
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uint32_t start_value = 0, end_value = 0;
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uint32_t regval;
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uint8_t end_bits = 0;
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uint8_t start_bits = 0;
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uint32_t start_index, end_index;
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cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
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MAC_TCL_REG_REG_BASE);
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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MAC_TCL_REG_REG_BASE,
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id * NUM_WORDS_PER_DSCP_TID_TABLE);
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start_index = dscp * HAL_TX_BITS_PER_TID;
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end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
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% HAL_TX_NUM_DSCP_REGISTER_SIZE;
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start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
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addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
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HAL_TX_NUM_DSCP_REGISTER_SIZE));
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if (end_index < start_index) {
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end_bits = end_index + 1;
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start_bits = HAL_TX_BITS_PER_TID - end_bits;
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start_value = tid << start_index;
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end_value = tid >> start_bits;
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addr1 = addr + 4;
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} else {
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start_bits = HAL_TX_BITS_PER_TID - end_bits;
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start_value = tid << start_index;
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addr1 = 0;
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}
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/* Enable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval |=
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(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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regval = HAL_REG_READ(soc, addr);
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if (end_index < start_index)
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regval &= (~0) >> start_bits;
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else
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regval &= ~(7 << start_index);
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regval |= start_value;
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HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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if (addr1) {
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regval = HAL_REG_READ(soc, addr1);
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regval &= (~0) << end_bits;
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regval |= end_value;
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HAL_REG_WRITE(soc, addr1, (regval &
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HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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}
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/* Diasble read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval &=
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~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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}
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/**
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* hal_tx_init_cmd_credit_ring_9224() - Initialize command/credit SRNG
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* @hal_soc_hdl: Handle to HAL SoC structure
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* @hal_srng: Handle to HAL SRNG structure
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*
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* Return: none
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*/
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static inline void
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hal_tx_init_cmd_credit_ring_9224(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl)
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{
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}
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/* TX MONITOR */
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#ifdef QCA_MONITOR_2_0_SUPPORT
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#if defined(TX_MONITOR_WORD_MASK)
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typedef struct tx_fes_setup_compact_9224 hal_tx_fes_setup_t;
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struct tx_fes_setup_compact_9224 {
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/* DWORD - 0 */
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uint32_t schedule_id;
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/* DWORD - 1 */
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uint32_t reserved_1a : 7, // [0: 6]
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transmit_start_reason : 3, // [7: 9]
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reserved_1b : 13, // [10: 22]
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number_of_users : 6, // [28: 23]
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MU_type : 1, // [29]
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reserved_1c : 2; // [30]
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/* DWORD - 2 */
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uint32_t reserved_2a : 4, // [0: 3]
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ndp_frame : 2, // [4: 5]
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txbf : 1, // [6]
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reserved_2b : 3, // [7: 9]
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static_bandwidth : 3, // [12: 10]
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reserved_2c : 1, // [13]
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transmission_contains_MU_RTS : 1, // [14]
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reserved_2d : 17; // [15: 31]
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/* DWORD - 3 */
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uint32_t reserved_3a : 15, // [0: 14]
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mu_ndp : 1, // [15]
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reserved_3b : 11, // [16: 26]
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ndpa : 1, // [27]
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reserved_3c : 4; // [28: 31]
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};
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#endif
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#endif /* QCA_MONITOR_2_0_SUPPORT */
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/**
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* hal_tx_set_ppe_cmn_config_9224() - Set the PPE common config register
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* @hal_soc_hdl: HAL SoC handle
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* @cmn_cfg: Common PPE config
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*
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* Based on the PPE2TCL descriptor below errors, if the below register
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* values are set then the packets are forward to Tx rule handler if 1'0b
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* or to TCL exit base if 1'1b.
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*
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* Return: void
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*/
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static inline
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void hal_tx_set_ppe_cmn_config_9224(hal_soc_handle_t hal_soc_hdl,
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union hal_tx_cmn_config_ppe *cmn_cfg)
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{
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struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
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union hal_tx_cmn_config_ppe *cfg =
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(union hal_tx_cmn_config_ppe *)cmn_cfg;
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uint32_t reg_addr, reg_val = 0;
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reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE);
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reg_val = HAL_REG_READ(soc, reg_addr);
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reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK;
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reg_val |=
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(cfg->drop_prec_err &
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HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) <<
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HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT;
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reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK;
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reg_val |=
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(cfg->fake_mac_hdr &
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HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) <<
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HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT;
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reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK;
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reg_val |=
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(cfg->cpu_code_inv &
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HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) <<
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HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT;
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reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK;
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reg_val |=
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(cfg->l3_l4_err &
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HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) <<
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HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT;
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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}
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/**
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* hal_tx_set_ppe_vp_entry_9224() - Set the PPE VP entry
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* @hal_soc_hdl: HAL SoC handle
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* @vp_cfg: PPE VP config
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* @ppe_vp_idx : PPE VP index to the table
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*
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* Return: void
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*/
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static inline
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void hal_tx_set_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl,
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union hal_tx_ppe_vp_config *cfg,
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int ppe_vp_idx)
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{
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struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
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uint32_t reg_addr, reg_val = 0;
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reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
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ppe_vp_idx);
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/*
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* Drop precedence is enabled by default.
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*/
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reg_val = HAL_REG_READ(soc, reg_addr);
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reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK;
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reg_val |= (cfg->vp_num &
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK) <<
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_SHFT;
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reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK;
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reg_val |= (cfg->pmac_id &
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK) <<
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_SHFT;
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reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK;
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reg_val |= (cfg->bank_id &
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK) <<
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_SHFT;
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reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK;
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reg_val |= (cfg->vdev_id &
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK) <<
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_SHFT;
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reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK;
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reg_val |=
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(cfg->search_idx_reg_num &
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK) <<
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_SHFT;
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reg_val &=
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~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
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reg_val |=
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(cfg->use_ppe_int_pri &
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
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reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK;
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reg_val |= (cfg->to_fw &
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK) <<
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_SHFT;
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reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK;
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reg_val |= (cfg->drop_prec_enable &
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK) <<
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_SHFT;
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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}
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/**
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* hal_tx_set_ppe_pri2tid_map1_9224()
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* @hal_soc_hdl: HAL SoC handle
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* @val : PRI to TID value
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* @map_no: Map number
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*
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* Return: void
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*/
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static inline
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void hal_tx_set_ppe_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl,
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uint32_t val, uint8_t map_no)
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{
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struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
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uint32_t reg_addr, reg_val = 0;
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if (map_no == 0)
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reg_addr =
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HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
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else
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reg_addr =
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HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
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reg_val |= val;
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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}
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/**
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* hal_tx_set_ppe_pri2tid_map1_9224()
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* @hal_soc_hdl: HAL SoC handle
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* @val : PRI to TID value
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* @map_no: Map number
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*
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* Return: void
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*/
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static inline
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void hal_tx_enable_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl,
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bool val, uint8_t ppe_vp_idx)
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{
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struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
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uint32_t reg_addr, reg_val = 0;
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reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
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ppe_vp_idx);
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/*
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* Drop precedence is enabled by default.
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*/
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reg_val = HAL_REG_READ(soc, reg_addr);
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reg_val &=
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~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
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reg_val |=
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(val &
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
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HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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}
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/**
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* hal_tx_update_ppe_pri2tid_9224()
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* @hal_soc_hdl: HAL SoC handle
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* @pri: INT_PRI
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* @tid: Wi-Fi TID
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*
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* Return: void
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*/
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static inline
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void hal_tx_update_ppe_pri2tid_9224(hal_soc_handle_t hal_soc_hdl,
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uint8_t pri, uint8_t tid)
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{
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struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
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uint32_t reg_addr, reg_val = 0, mask, shift;
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/*
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* INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15
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* is in MAP1 register.
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*/
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switch (pri) {
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case 0 ... 9:
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reg_addr =
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HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
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mask =
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(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri));
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shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3);
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break;
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case 10 ... 15:
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pri = pri - 10;
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reg_addr =
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HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
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mask =
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(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri));
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shift =
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HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3);
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break;
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default:
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return;
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}
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reg_val = HAL_REG_READ(soc, reg_addr);
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reg_val &= ~mask;
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reg_val |= (pri << shift) & mask;
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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}
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#endif /* _HAL_9224_TX_H_ */
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