dp_li_rx.c 24 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include "cdp_txrx_cmn_struct.h"
  19. #include "hal_hw_headers.h"
  20. #include "dp_types.h"
  21. #include "dp_rx.h"
  22. #include "dp_li_rx.h"
  23. #include "dp_peer.h"
  24. #include "hal_rx.h"
  25. #include "hal_li_rx.h"
  26. #include "hal_api.h"
  27. #include "hal_li_api.h"
  28. #include "qdf_nbuf.h"
  29. #ifdef MESH_MODE_SUPPORT
  30. #include "if_meta_hdr.h"
  31. #endif
  32. #include "dp_internal.h"
  33. #include "dp_rx_mon.h"
  34. #include "dp_ipa.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #include "dp_hist.h"
  39. #include "dp_rx_buffer_pool.h"
  40. static inline
  41. bool is_sa_da_idx_valid(struct dp_soc *soc, uint8_t *rx_tlv_hdr,
  42. qdf_nbuf_t nbuf, struct hal_rx_msdu_metadata msdu_info)
  43. {
  44. if ((qdf_nbuf_is_sa_valid(nbuf) &&
  45. (msdu_info.sa_idx > wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx))) ||
  46. (!qdf_nbuf_is_da_mcbc(nbuf) && qdf_nbuf_is_da_valid(nbuf) &&
  47. (msdu_info.da_idx > wlan_cfg_get_max_ast_idx(soc->wlan_cfg_ctx))))
  48. return false;
  49. return true;
  50. }
  51. /**
  52. * dp_rx_process_li() - Brain of the Rx processing functionality
  53. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  54. * @int_ctx: per interrupt context
  55. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  56. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  57. * @quota: No. of units (packets) that can be serviced in one shot.
  58. *
  59. * This function implements the core of Rx functionality. This is
  60. * expected to handle only non-error frames.
  61. *
  62. * Return: uint32_t: No. of elements processed
  63. */
  64. uint32_t dp_rx_process_li(struct dp_intr *int_ctx,
  65. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  66. uint32_t quota)
  67. {
  68. hal_ring_desc_t ring_desc;
  69. hal_soc_handle_t hal_soc;
  70. struct dp_rx_desc *rx_desc = NULL;
  71. qdf_nbuf_t nbuf, next;
  72. bool near_full;
  73. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  74. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  75. uint32_t num_pending;
  76. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  77. uint16_t msdu_len = 0;
  78. uint16_t peer_id;
  79. uint8_t vdev_id;
  80. struct dp_peer *peer;
  81. struct dp_vdev *vdev;
  82. uint32_t pkt_len = 0;
  83. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  84. struct hal_rx_msdu_desc_info msdu_desc_info;
  85. enum hal_reo_error_status error;
  86. uint32_t peer_mdata;
  87. uint8_t *rx_tlv_hdr;
  88. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  89. uint8_t mac_id = 0;
  90. struct dp_pdev *rx_pdev;
  91. struct dp_srng *dp_rxdma_srng;
  92. struct rx_desc_pool *rx_desc_pool;
  93. struct dp_soc *soc = int_ctx->soc;
  94. uint8_t core_id = 0;
  95. struct cdp_tid_rx_stats *tid_stats;
  96. qdf_nbuf_t nbuf_head;
  97. qdf_nbuf_t nbuf_tail;
  98. qdf_nbuf_t deliver_list_head;
  99. qdf_nbuf_t deliver_list_tail;
  100. uint32_t num_rx_bufs_reaped = 0;
  101. uint32_t intr_id;
  102. struct hif_opaque_softc *scn;
  103. int32_t tid = 0;
  104. bool is_prev_msdu_last = true;
  105. uint32_t num_entries_avail = 0;
  106. uint32_t rx_ol_pkt_cnt = 0;
  107. uint32_t num_entries = 0;
  108. struct hal_rx_msdu_metadata msdu_metadata;
  109. QDF_STATUS status;
  110. qdf_nbuf_t ebuf_head;
  111. qdf_nbuf_t ebuf_tail;
  112. uint8_t pkt_capture_offload = 0;
  113. int max_reap_limit;
  114. DP_HIST_INIT();
  115. qdf_assert_always(soc && hal_ring_hdl);
  116. hal_soc = soc->hal_soc;
  117. qdf_assert_always(hal_soc);
  118. scn = soc->hif_handle;
  119. hif_pm_runtime_mark_dp_rx_busy(scn);
  120. intr_id = int_ctx->dp_intr_id;
  121. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  122. more_data:
  123. /* reset local variables here to be re-used in the function */
  124. nbuf_head = NULL;
  125. nbuf_tail = NULL;
  126. deliver_list_head = NULL;
  127. deliver_list_tail = NULL;
  128. peer = NULL;
  129. vdev = NULL;
  130. num_rx_bufs_reaped = 0;
  131. ebuf_head = NULL;
  132. ebuf_tail = NULL;
  133. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  134. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  135. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  136. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  137. qdf_mem_zero(head, sizeof(head));
  138. qdf_mem_zero(tail, sizeof(tail));
  139. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  140. /*
  141. * Need API to convert from hal_ring pointer to
  142. * Ring Type / Ring Id combo
  143. */
  144. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  145. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  146. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  147. goto done;
  148. }
  149. /*
  150. * start reaping the buffers from reo ring and queue
  151. * them in per vdev queue.
  152. * Process the received pkts in a different per vdev loop.
  153. */
  154. while (qdf_likely(quota &&
  155. (ring_desc = hal_srng_dst_peek(hal_soc,
  156. hal_ring_hdl)))) {
  157. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  158. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  159. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  160. soc, hal_ring_hdl, error);
  161. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  162. 1);
  163. /* Don't know how to deal with this -- assert */
  164. qdf_assert(0);
  165. }
  166. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  167. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  168. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  169. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  170. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  171. break;
  172. }
  173. rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, rx_buf_cookie);
  174. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  175. ring_desc, rx_desc);
  176. if (QDF_IS_STATUS_ERROR(status)) {
  177. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  178. qdf_assert_always(!rx_desc->unmapped);
  179. dp_ipa_reo_ctx_buf_mapping_lock(soc,
  180. reo_ring_num);
  181. dp_ipa_handle_rx_buf_smmu_mapping(
  182. soc,
  183. rx_desc->nbuf,
  184. RX_DATA_BUFFER_SIZE,
  185. false);
  186. qdf_nbuf_unmap_nbytes_single(
  187. soc->osdev,
  188. rx_desc->nbuf,
  189. QDF_DMA_FROM_DEVICE,
  190. RX_DATA_BUFFER_SIZE);
  191. rx_desc->unmapped = 1;
  192. dp_ipa_reo_ctx_buf_mapping_unlock(soc,
  193. reo_ring_num);
  194. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  195. rx_desc->pool_id);
  196. dp_rx_add_to_free_desc_list(
  197. &head[rx_desc->pool_id],
  198. &tail[rx_desc->pool_id],
  199. rx_desc);
  200. }
  201. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  202. continue;
  203. }
  204. /*
  205. * this is a unlikely scenario where the host is reaping
  206. * a descriptor which it already reaped just a while ago
  207. * but is yet to replenish it back to HW.
  208. * In this case host will dump the last 128 descriptors
  209. * including the software descriptor rx_desc and assert.
  210. */
  211. if (qdf_unlikely(!rx_desc->in_use)) {
  212. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  213. dp_info_rl("Reaping rx_desc not in use!");
  214. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  215. ring_desc, rx_desc);
  216. /* ignore duplicate RX desc and continue to process */
  217. /* Pop out the descriptor */
  218. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  219. continue;
  220. }
  221. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  222. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  223. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  224. dp_info_rl("Nbuf sanity check failure!");
  225. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  226. ring_desc, rx_desc);
  227. rx_desc->in_err_state = 1;
  228. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  229. continue;
  230. }
  231. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  232. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  233. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  234. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  235. ring_desc, rx_desc);
  236. }
  237. /* Get MPDU DESC info */
  238. hal_rx_mpdu_desc_info_get_li(ring_desc, &mpdu_desc_info);
  239. /* Get MSDU DESC info */
  240. hal_rx_msdu_desc_info_get_li(ring_desc, &msdu_desc_info);
  241. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  242. HAL_MSDU_F_MSDU_CONTINUATION)) {
  243. /* previous msdu has end bit set, so current one is
  244. * the new MPDU
  245. */
  246. if (is_prev_msdu_last) {
  247. /* Get number of entries available in HW ring */
  248. num_entries_avail =
  249. hal_srng_dst_num_valid(hal_soc,
  250. hal_ring_hdl, 1);
  251. /* For new MPDU check if we can read complete
  252. * MPDU by comparing the number of buffers
  253. * available and number of buffers needed to
  254. * reap this MPDU
  255. */
  256. if ((msdu_desc_info.msdu_len /
  257. (RX_DATA_BUFFER_SIZE -
  258. soc->rx_pkt_tlv_size) + 1) >
  259. num_entries_avail) {
  260. DP_STATS_INC(soc,
  261. rx.msdu_scatter_wait_break,
  262. 1);
  263. dp_rx_cookie_reset_invalid_bit(
  264. ring_desc);
  265. break;
  266. }
  267. is_prev_msdu_last = false;
  268. }
  269. }
  270. core_id = smp_processor_id();
  271. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  272. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  273. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  274. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  275. HAL_MPDU_F_RAW_AMPDU))
  276. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  277. if (!is_prev_msdu_last &&
  278. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  279. is_prev_msdu_last = true;
  280. /* Pop out the descriptor*/
  281. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  282. rx_bufs_reaped[rx_desc->pool_id]++;
  283. peer_mdata = mpdu_desc_info.peer_meta_data;
  284. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  285. DP_PEER_METADATA_PEER_ID_GET(peer_mdata);
  286. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  287. DP_PEER_METADATA_VDEV_ID_GET(peer_mdata);
  288. /* to indicate whether this msdu is rx offload */
  289. pkt_capture_offload =
  290. DP_PEER_METADATA_OFFLOAD_GET(peer_mdata);
  291. /*
  292. * save msdu flags first, last and continuation msdu in
  293. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  294. * length to nbuf->cb. This ensures the info required for
  295. * per pkt processing is always in the same cache line.
  296. * This helps in improving throughput for smaller pkt
  297. * sizes.
  298. */
  299. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  300. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  301. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  302. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  303. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  304. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  305. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  306. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  307. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  308. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  309. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  310. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  311. qdf_nbuf_set_tid_val(rx_desc->nbuf,
  312. HAL_RX_REO_QUEUE_NUMBER_GET(ring_desc));
  313. qdf_nbuf_set_rx_reo_dest_ind(
  314. rx_desc->nbuf,
  315. HAL_RX_REO_MSDU_REO_DST_IND_GET(ring_desc));
  316. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  317. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  318. /*
  319. * move unmap after scattered msdu waiting break logic
  320. * in case double skb unmap happened.
  321. */
  322. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  323. dp_ipa_reo_ctx_buf_mapping_lock(soc, reo_ring_num);
  324. dp_ipa_handle_rx_buf_smmu_mapping(soc, rx_desc->nbuf,
  325. rx_desc_pool->buf_size,
  326. false);
  327. qdf_nbuf_unmap_nbytes_single(soc->osdev, rx_desc->nbuf,
  328. QDF_DMA_FROM_DEVICE,
  329. rx_desc_pool->buf_size);
  330. rx_desc->unmapped = 1;
  331. dp_ipa_reo_ctx_buf_mapping_unlock(soc, reo_ring_num);
  332. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  333. ebuf_tail, rx_desc);
  334. /*
  335. * if continuation bit is set then we have MSDU spread
  336. * across multiple buffers, let us not decrement quota
  337. * till we reap all buffers of that MSDU.
  338. */
  339. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  340. quota -= 1;
  341. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  342. &tail[rx_desc->pool_id], rx_desc);
  343. num_rx_bufs_reaped++;
  344. /*
  345. * only if complete msdu is received for scatter case,
  346. * then allow break.
  347. */
  348. if (is_prev_msdu_last &&
  349. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  350. max_reap_limit))
  351. break;
  352. }
  353. done:
  354. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  355. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  356. /*
  357. * continue with next mac_id if no pkts were reaped
  358. * from that pool
  359. */
  360. if (!rx_bufs_reaped[mac_id])
  361. continue;
  362. dp_rxdma_srng = &soc->rx_refill_buf_ring[mac_id];
  363. rx_desc_pool = &soc->rx_desc_buf[mac_id];
  364. dp_rx_buffers_replenish(soc, mac_id, dp_rxdma_srng,
  365. rx_desc_pool, rx_bufs_reaped[mac_id],
  366. &head[mac_id], &tail[mac_id]);
  367. }
  368. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  369. /* Peer can be NULL is case of LFR */
  370. if (qdf_likely(peer))
  371. vdev = NULL;
  372. /*
  373. * BIG loop where each nbuf is dequeued from global queue,
  374. * processed and queued back on a per vdev basis. These nbufs
  375. * are sent to stack as and when we run out of nbufs
  376. * or a new nbuf dequeued from global queue has a different
  377. * vdev when compared to previous nbuf.
  378. */
  379. nbuf = nbuf_head;
  380. while (nbuf) {
  381. next = nbuf->next;
  382. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  383. nbuf = next;
  384. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  385. continue;
  386. }
  387. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  388. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  389. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  390. if (dp_rx_is_list_ready(deliver_list_head, vdev, peer,
  391. peer_id, vdev_id)) {
  392. dp_rx_deliver_to_stack(soc, vdev, peer,
  393. deliver_list_head,
  394. deliver_list_tail);
  395. deliver_list_head = NULL;
  396. deliver_list_tail = NULL;
  397. }
  398. /* Get TID from struct cb->tid_val, save to tid */
  399. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  400. tid = qdf_nbuf_get_tid_val(nbuf);
  401. if (qdf_unlikely(!peer)) {
  402. peer = dp_peer_get_ref_by_id(soc, peer_id,
  403. DP_MOD_ID_RX);
  404. } else if (peer && peer->peer_id != peer_id) {
  405. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  406. peer = dp_peer_get_ref_by_id(soc, peer_id,
  407. DP_MOD_ID_RX);
  408. }
  409. if (peer) {
  410. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  411. qdf_dp_trace_set_track(nbuf, QDF_RX);
  412. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  413. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  414. QDF_NBUF_RX_PKT_DATA_TRACK;
  415. }
  416. rx_bufs_used++;
  417. if (qdf_likely(peer)) {
  418. vdev = peer->vdev;
  419. } else {
  420. nbuf->next = NULL;
  421. dp_rx_deliver_to_pkt_capture_no_peer(
  422. soc, nbuf, pkt_capture_offload);
  423. if (!pkt_capture_offload)
  424. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  425. nbuf = next;
  426. continue;
  427. }
  428. if (qdf_unlikely(!vdev)) {
  429. qdf_nbuf_free(nbuf);
  430. nbuf = next;
  431. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  432. continue;
  433. }
  434. /* when hlos tid override is enabled, save tid in
  435. * skb->priority
  436. */
  437. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  438. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  439. qdf_nbuf_set_priority(nbuf, tid);
  440. rx_pdev = vdev->pdev;
  441. DP_RX_TID_SAVE(nbuf, tid);
  442. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  443. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  444. soc->wlan_cfg_ctx)))
  445. qdf_nbuf_set_timestamp(nbuf);
  446. tid_stats =
  447. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  448. /*
  449. * Check if DMA completed -- msdu_done is the last bit
  450. * to be written
  451. */
  452. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(nbuf))) {
  453. if (qdf_unlikely(!hal_rx_attn_msdu_done_get_li(
  454. rx_tlv_hdr))) {
  455. dp_err_rl("MSDU DONE failure");
  456. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  457. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  458. QDF_TRACE_LEVEL_INFO);
  459. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  460. qdf_assert(0);
  461. qdf_nbuf_free(nbuf);
  462. nbuf = next;
  463. continue;
  464. } else if (qdf_unlikely(hal_rx_attn_msdu_len_err_get_li(
  465. rx_tlv_hdr))) {
  466. DP_STATS_INC(soc, rx.err.msdu_len_err, 1);
  467. qdf_nbuf_free(nbuf);
  468. nbuf = next;
  469. continue;
  470. }
  471. }
  472. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  473. /*
  474. * First IF condition:
  475. * 802.11 Fragmented pkts are reinjected to REO
  476. * HW block as SG pkts and for these pkts we only
  477. * need to pull the RX TLVS header length.
  478. * Second IF condition:
  479. * The below condition happens when an MSDU is spread
  480. * across multiple buffers. This can happen in two cases
  481. * 1. The nbuf size is smaller then the received msdu.
  482. * ex: we have set the nbuf size to 2048 during
  483. * nbuf_alloc. but we received an msdu which is
  484. * 2304 bytes in size then this msdu is spread
  485. * across 2 nbufs.
  486. *
  487. * 2. AMSDUs when RAW mode is enabled.
  488. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  489. * across 1st nbuf and 2nd nbuf and last MSDU is
  490. * spread across 2nd nbuf and 3rd nbuf.
  491. *
  492. * for these scenarios let us create a skb frag_list and
  493. * append these buffers till the last MSDU of the AMSDU
  494. * Third condition:
  495. * This is the most likely case, we receive 802.3 pkts
  496. * decapsulated by HW, here we need to set the pkt length.
  497. */
  498. hal_rx_msdu_metadata_get(hal_soc, rx_tlv_hdr, &msdu_metadata);
  499. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  500. bool is_mcbc, is_sa_vld, is_da_vld;
  501. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  502. rx_tlv_hdr);
  503. is_sa_vld =
  504. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  505. rx_tlv_hdr);
  506. is_da_vld =
  507. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  508. rx_tlv_hdr);
  509. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  510. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  511. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  512. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  513. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  514. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  515. nbuf = dp_rx_sg_create(soc, nbuf);
  516. next = nbuf->next;
  517. if (qdf_nbuf_is_raw_frame(nbuf)) {
  518. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  519. DP_STATS_INC_PKT(peer, rx.raw, 1, msdu_len);
  520. } else {
  521. qdf_nbuf_free(nbuf);
  522. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  523. dp_info_rl("scatter msdu len %d, dropped",
  524. msdu_len);
  525. nbuf = next;
  526. continue;
  527. }
  528. } else {
  529. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  530. pkt_len = msdu_len +
  531. msdu_metadata.l3_hdr_pad +
  532. soc->rx_pkt_tlv_size;
  533. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  534. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  535. }
  536. /*
  537. * process frame for mulitpass phrase processing
  538. */
  539. if (qdf_unlikely(vdev->multipass_en)) {
  540. if (dp_rx_multipass_process(peer, nbuf, tid) == false) {
  541. DP_STATS_INC(peer, rx.multipass_rx_pkt_drop, 1);
  542. qdf_nbuf_free(nbuf);
  543. nbuf = next;
  544. continue;
  545. }
  546. }
  547. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, peer)) {
  548. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  549. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  550. /* Drop & free packet */
  551. qdf_nbuf_free(nbuf);
  552. /* Statistics */
  553. nbuf = next;
  554. continue;
  555. }
  556. if (qdf_unlikely(peer && (peer->nawds_enabled) &&
  557. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  558. (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc,
  559. rx_tlv_hdr) ==
  560. false))) {
  561. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  562. DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
  563. qdf_nbuf_free(nbuf);
  564. nbuf = next;
  565. continue;
  566. }
  567. /*
  568. * Drop non-EAPOL frames from unauthorized peer.
  569. */
  570. if (qdf_likely(peer) && qdf_unlikely(!peer->authorize)) {
  571. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  572. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  573. if (!is_eapol) {
  574. DP_STATS_INC(soc,
  575. rx.err.peer_unauth_rx_pkt_drop,
  576. 1);
  577. qdf_nbuf_free(nbuf);
  578. nbuf = next;
  579. continue;
  580. }
  581. }
  582. if (soc->process_rx_status)
  583. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  584. /* Update the protocol tag in SKB based on CCE metadata */
  585. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  586. reo_ring_num, false, true);
  587. /* Update the flow tag in SKB based on FSE metadata */
  588. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  589. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, peer,
  590. reo_ring_num, tid_stats);
  591. if (qdf_unlikely(vdev->mesh_vdev)) {
  592. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  593. == QDF_STATUS_SUCCESS) {
  594. dp_rx_info("%pK: mesh pkt filtered", soc);
  595. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  596. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  597. 1);
  598. qdf_nbuf_free(nbuf);
  599. nbuf = next;
  600. continue;
  601. }
  602. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
  603. }
  604. if (qdf_likely(vdev->rx_decap_type ==
  605. htt_cmn_pkt_type_ethernet) &&
  606. qdf_likely(!vdev->mesh_vdev)) {
  607. /* WDS Destination Address Learning */
  608. dp_rx_da_learn(soc, rx_tlv_hdr, peer, nbuf);
  609. /* Due to HW issue, sometimes we see that the sa_idx
  610. * and da_idx are invalid with sa_valid and da_valid
  611. * bits set
  612. *
  613. * in this case we also see that value of
  614. * sa_sw_peer_id is set as 0
  615. *
  616. * Drop the packet if sa_idx and da_idx OOB or
  617. * sa_sw_peerid is 0
  618. */
  619. if (!is_sa_da_idx_valid(soc, rx_tlv_hdr, nbuf,
  620. msdu_metadata)) {
  621. qdf_nbuf_free(nbuf);
  622. nbuf = next;
  623. DP_STATS_INC(soc, rx.err.invalid_sa_da_idx, 1);
  624. continue;
  625. }
  626. /* WDS Source Port Learning */
  627. if (qdf_likely(vdev->wds_enabled))
  628. dp_rx_wds_srcport_learn(soc,
  629. rx_tlv_hdr,
  630. peer,
  631. nbuf,
  632. msdu_metadata);
  633. /* Intrabss-fwd */
  634. if (dp_rx_check_ap_bridge(vdev))
  635. if (DP_RX_INTRABSS_FWD(soc, peer, rx_tlv_hdr,
  636. nbuf, msdu_metadata)) {
  637. nbuf = next;
  638. tid_stats->intrabss_cnt++;
  639. continue; /* Get next desc */
  640. }
  641. }
  642. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  643. dp_rx_update_stats(soc, nbuf);
  644. DP_RX_LIST_APPEND(deliver_list_head,
  645. deliver_list_tail,
  646. nbuf);
  647. DP_STATS_INC_PKT(peer, rx.to_stack, 1,
  648. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  649. if (qdf_unlikely(peer->in_twt))
  650. DP_STATS_INC_PKT(peer, rx.to_stack_twt, 1,
  651. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  652. tid_stats->delivered_to_stack++;
  653. nbuf = next;
  654. }
  655. if (qdf_likely(deliver_list_head)) {
  656. if (qdf_likely(peer)) {
  657. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  658. pkt_capture_offload,
  659. deliver_list_head);
  660. if (!pkt_capture_offload)
  661. dp_rx_deliver_to_stack(soc, vdev, peer,
  662. deliver_list_head,
  663. deliver_list_tail);
  664. } else {
  665. nbuf = deliver_list_head;
  666. while (nbuf) {
  667. next = nbuf->next;
  668. nbuf->next = NULL;
  669. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  670. nbuf = next;
  671. }
  672. }
  673. }
  674. if (qdf_likely(peer))
  675. dp_peer_unref_delete(peer, DP_MOD_ID_RX);
  676. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  677. if (quota) {
  678. num_pending =
  679. dp_rx_srng_get_num_pending(hal_soc,
  680. hal_ring_hdl,
  681. num_entries,
  682. &near_full);
  683. if (num_pending) {
  684. DP_STATS_INC(soc, rx.hp_oos2, 1);
  685. if (!hif_exec_should_yield(scn, intr_id))
  686. goto more_data;
  687. if (qdf_unlikely(near_full)) {
  688. DP_STATS_INC(soc, rx.near_full, 1);
  689. goto more_data;
  690. }
  691. }
  692. }
  693. if (vdev && vdev->osif_fisa_flush)
  694. vdev->osif_fisa_flush(soc, reo_ring_num);
  695. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  696. vdev->osif_gro_flush(vdev->osif_vdev,
  697. reo_ring_num);
  698. }
  699. }
  700. /* Update histogram statistics by looping through pdev's */
  701. DP_RX_HIST_STATS_PER_PDEV();
  702. return rx_bufs_used; /* Assume no scale factor for now */
  703. }
  704. QDF_STATUS dp_rx_desc_pool_init_li(struct dp_soc *soc,
  705. struct rx_desc_pool *rx_desc_pool,
  706. uint32_t pool_id)
  707. {
  708. return dp_rx_desc_pool_init_generic(soc, rx_desc_pool, pool_id);
  709. }
  710. void dp_rx_desc_pool_deinit_li(struct dp_soc *soc,
  711. struct rx_desc_pool *rx_desc_pool,
  712. uint32_t pool_id)
  713. {
  714. }
  715. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_li(
  716. struct dp_soc *soc,
  717. void *ring_desc,
  718. struct dp_rx_desc **r_rx_desc)
  719. {
  720. struct hal_buf_info buf_info = {0};
  721. hal_soc_handle_t hal_soc = soc->hal_soc;
  722. /* only cookie and rbm will be valid in buf_info */
  723. hal_rx_buf_cookie_rbm_get(hal_soc, (uint32_t *)ring_desc,
  724. &buf_info);
  725. if (qdf_unlikely(buf_info.rbm !=
  726. HAL_RX_BUF_RBM_SW3_BM(soc->wbm_sw0_bm_id))) {
  727. /* TODO */
  728. /* Call appropriate handler */
  729. DP_STATS_INC(soc, rx.err.invalid_rbm, 1);
  730. dp_rx_err("%pK: Invalid RBM %d", soc, buf_info.rbm);
  731. return QDF_STATUS_E_INVAL;
  732. }
  733. *r_rx_desc = dp_rx_cookie_2_va_rxdma_buf(soc, buf_info.sw_cookie);
  734. return QDF_STATUS_SUCCESS;
  735. }