dp_tx.c 175 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. #define DP_RETRY_COUNT 7
  63. #ifdef WLAN_PEER_JITTER
  64. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  65. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  66. #endif
  67. #ifdef QCA_DP_TX_FW_METADATA_V2
  68. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  69. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  70. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  71. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  80. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  81. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  82. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  84. #else
  85. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  86. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  87. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  88. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  97. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  98. HTT_TCL_METADATA_TYPE_PEER_BASED
  99. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  100. HTT_TCL_METADATA_TYPE_VDEV_BASED
  101. #endif
  102. #define DP_GET_HW_LINK_ID_FRM_PPDU_ID(PPDU_ID, LINK_ID_OFFSET, LINK_ID_BITS) \
  103. (((PPDU_ID) >> (LINK_ID_OFFSET)) & ((1 << (LINK_ID_BITS)) - 1))
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. /**
  232. * dp_is_tput_high() - Check if throughput is high
  233. *
  234. * @soc: core txrx main context
  235. *
  236. * The current function is based of the RTPM tput policy variable where RTPM is
  237. * avoided based on throughput.
  238. */
  239. static inline int dp_is_tput_high(struct dp_soc *soc)
  240. {
  241. return dp_get_rtpm_tput_policy_requirement(soc);
  242. }
  243. #if defined(FEATURE_TSO)
  244. /**
  245. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  246. *
  247. * @soc: core txrx main context
  248. * @seg_desc: tso segment descriptor
  249. * @num_seg_desc: tso number segment descriptor
  250. */
  251. static void dp_tx_tso_unmap_segment(
  252. struct dp_soc *soc,
  253. struct qdf_tso_seg_elem_t *seg_desc,
  254. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  255. {
  256. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  257. if (qdf_unlikely(!seg_desc)) {
  258. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  259. __func__, __LINE__);
  260. qdf_assert(0);
  261. } else if (qdf_unlikely(!num_seg_desc)) {
  262. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  263. __func__, __LINE__);
  264. qdf_assert(0);
  265. } else {
  266. bool is_last_seg;
  267. /* no tso segment left to do dma unmap */
  268. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  269. return;
  270. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  271. true : false;
  272. qdf_nbuf_unmap_tso_segment(soc->osdev,
  273. seg_desc, is_last_seg);
  274. num_seg_desc->num_seg.tso_cmn_num_seg--;
  275. }
  276. }
  277. /**
  278. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  279. * back to the freelist
  280. *
  281. * @soc: soc device handle
  282. * @tx_desc: Tx software descriptor
  283. */
  284. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  285. struct dp_tx_desc_s *tx_desc)
  286. {
  287. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  288. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  289. dp_tx_err("SO desc is NULL!");
  290. qdf_assert(0);
  291. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  292. dp_tx_err("TSO num desc is NULL!");
  293. qdf_assert(0);
  294. } else {
  295. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  296. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  297. msdu_ext_desc->tso_num_desc;
  298. /* Add the tso num segment into the free list */
  299. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  300. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  301. tx_desc->msdu_ext_desc->
  302. tso_num_desc);
  303. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  304. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  305. }
  306. /* Add the tso segment into the free list*/
  307. dp_tx_tso_desc_free(soc,
  308. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  309. tso_desc);
  310. tx_desc->msdu_ext_desc->tso_desc = NULL;
  311. }
  312. }
  313. #else
  314. static void dp_tx_tso_unmap_segment(
  315. struct dp_soc *soc,
  316. struct qdf_tso_seg_elem_t *seg_desc,
  317. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  318. {
  319. }
  320. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  321. struct dp_tx_desc_s *tx_desc)
  322. {
  323. }
  324. #endif
  325. void
  326. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  327. {
  328. struct dp_pdev *pdev = tx_desc->pdev;
  329. struct dp_soc *soc;
  330. uint8_t comp_status = 0;
  331. qdf_assert(pdev);
  332. soc = pdev->soc;
  333. dp_tx_outstanding_dec(pdev);
  334. if (tx_desc->msdu_ext_desc) {
  335. if (tx_desc->frm_type == dp_tx_frm_tso)
  336. dp_tx_tso_desc_release(soc, tx_desc);
  337. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  338. dp_tx_me_free_buf(tx_desc->pdev,
  339. tx_desc->msdu_ext_desc->me_buffer);
  340. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  341. }
  342. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  343. qdf_atomic_dec(&soc->num_tx_exception);
  344. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  345. tx_desc->buffer_src)
  346. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  347. soc->hal_soc);
  348. else
  349. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  350. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  351. tx_desc->id, comp_status,
  352. qdf_atomic_read(&pdev->num_tx_outstanding));
  353. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  354. return;
  355. }
  356. /**
  357. * dp_tx_prepare_htt_metadata() - Prepare HTT metadata for special frames
  358. * @vdev: DP vdev Handle
  359. * @nbuf: skb
  360. * @msdu_info: msdu_info required to create HTT metadata
  361. *
  362. * Prepares and fills HTT metadata in the frame pre-header for special frames
  363. * that should be transmitted using varying transmit parameters.
  364. * There are 2 VDEV modes that currently needs this special metadata -
  365. * 1) Mesh Mode
  366. * 2) DSRC Mode
  367. *
  368. * Return: HTT metadata size
  369. *
  370. */
  371. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  372. struct dp_tx_msdu_info_s *msdu_info)
  373. {
  374. uint32_t *meta_data = msdu_info->meta_data;
  375. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  376. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  377. uint8_t htt_desc_size;
  378. /* Size rounded of multiple of 8 bytes */
  379. uint8_t htt_desc_size_aligned;
  380. uint8_t *hdr = NULL;
  381. /*
  382. * Metadata - HTT MSDU Extension header
  383. */
  384. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  385. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  386. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  387. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  388. meta_data[0]) ||
  389. msdu_info->exception_fw) {
  390. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  391. htt_desc_size_aligned)) {
  392. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  393. htt_desc_size_aligned);
  394. if (!nbuf) {
  395. /*
  396. * qdf_nbuf_realloc_headroom won't do skb_clone
  397. * as skb_realloc_headroom does. so, no free is
  398. * needed here.
  399. */
  400. DP_STATS_INC(vdev,
  401. tx_i.dropped.headroom_insufficient,
  402. 1);
  403. qdf_print(" %s[%d] skb_realloc_headroom failed",
  404. __func__, __LINE__);
  405. return 0;
  406. }
  407. }
  408. /* Fill and add HTT metaheader */
  409. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  410. if (!hdr) {
  411. dp_tx_err("Error in filling HTT metadata");
  412. return 0;
  413. }
  414. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  415. } else if (vdev->opmode == wlan_op_mode_ocb) {
  416. /* Todo - Add support for DSRC */
  417. }
  418. return htt_desc_size_aligned;
  419. }
  420. /**
  421. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  422. * @tso_seg: TSO segment to process
  423. * @ext_desc: Pointer to MSDU extension descriptor
  424. *
  425. * Return: void
  426. */
  427. #if defined(FEATURE_TSO)
  428. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  429. void *ext_desc)
  430. {
  431. uint8_t num_frag;
  432. uint32_t tso_flags;
  433. /*
  434. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  435. * tcp_flag_mask
  436. *
  437. * Checksum enable flags are set in TCL descriptor and not in Extension
  438. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  439. */
  440. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  441. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  442. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  443. tso_seg->tso_flags.ip_len);
  444. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  445. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  446. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  447. uint32_t lo = 0;
  448. uint32_t hi = 0;
  449. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  450. (tso_seg->tso_frags[num_frag].length));
  451. qdf_dmaaddr_to_32s(
  452. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  453. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  454. tso_seg->tso_frags[num_frag].length);
  455. }
  456. return;
  457. }
  458. #else
  459. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  460. void *ext_desc)
  461. {
  462. return;
  463. }
  464. #endif
  465. #if defined(FEATURE_TSO)
  466. /**
  467. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  468. * allocated and free them
  469. * @soc: soc handle
  470. * @free_seg: list of tso segments
  471. * @msdu_info: msdu descriptor
  472. *
  473. * Return: void
  474. */
  475. static void dp_tx_free_tso_seg_list(
  476. struct dp_soc *soc,
  477. struct qdf_tso_seg_elem_t *free_seg,
  478. struct dp_tx_msdu_info_s *msdu_info)
  479. {
  480. struct qdf_tso_seg_elem_t *next_seg;
  481. while (free_seg) {
  482. next_seg = free_seg->next;
  483. dp_tx_tso_desc_free(soc,
  484. msdu_info->tx_queue.desc_pool_id,
  485. free_seg);
  486. free_seg = next_seg;
  487. }
  488. }
  489. /**
  490. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  491. * allocated and free them
  492. * @soc: soc handle
  493. * @free_num_seg: list of tso number segments
  494. * @msdu_info: msdu descriptor
  495. *
  496. * Return: void
  497. */
  498. static void dp_tx_free_tso_num_seg_list(
  499. struct dp_soc *soc,
  500. struct qdf_tso_num_seg_elem_t *free_num_seg,
  501. struct dp_tx_msdu_info_s *msdu_info)
  502. {
  503. struct qdf_tso_num_seg_elem_t *next_num_seg;
  504. while (free_num_seg) {
  505. next_num_seg = free_num_seg->next;
  506. dp_tso_num_seg_free(soc,
  507. msdu_info->tx_queue.desc_pool_id,
  508. free_num_seg);
  509. free_num_seg = next_num_seg;
  510. }
  511. }
  512. /**
  513. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  514. * do dma unmap for each segment
  515. * @soc: soc handle
  516. * @free_seg: list of tso segments
  517. * @num_seg_desc: tso number segment descriptor
  518. *
  519. * Return: void
  520. */
  521. static void dp_tx_unmap_tso_seg_list(
  522. struct dp_soc *soc,
  523. struct qdf_tso_seg_elem_t *free_seg,
  524. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  525. {
  526. struct qdf_tso_seg_elem_t *next_seg;
  527. if (qdf_unlikely(!num_seg_desc)) {
  528. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  529. return;
  530. }
  531. while (free_seg) {
  532. next_seg = free_seg->next;
  533. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  534. free_seg = next_seg;
  535. }
  536. }
  537. #ifdef FEATURE_TSO_STATS
  538. /**
  539. * dp_tso_get_stats_idx() - Retrieve the tso packet id
  540. * @pdev: pdev handle
  541. *
  542. * Return: id
  543. */
  544. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  545. {
  546. uint32_t stats_idx;
  547. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  548. % CDP_MAX_TSO_PACKETS);
  549. return stats_idx;
  550. }
  551. #else
  552. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  553. {
  554. return 0;
  555. }
  556. #endif /* FEATURE_TSO_STATS */
  557. /**
  558. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  559. * free the tso segments descriptor and
  560. * tso num segments descriptor
  561. * @soc: soc handle
  562. * @msdu_info: msdu descriptor
  563. * @tso_seg_unmap: flag to show if dma unmap is necessary
  564. *
  565. * Return: void
  566. */
  567. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  568. struct dp_tx_msdu_info_s *msdu_info,
  569. bool tso_seg_unmap)
  570. {
  571. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  572. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  573. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  574. tso_info->tso_num_seg_list;
  575. /* do dma unmap for each segment */
  576. if (tso_seg_unmap)
  577. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  578. /* free all tso number segment descriptor though looks only have 1 */
  579. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  580. /* free all tso segment descriptor */
  581. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  582. }
  583. /**
  584. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  585. * @vdev: virtual device handle
  586. * @msdu: network buffer
  587. * @msdu_info: meta data associated with the msdu
  588. *
  589. * Return: QDF_STATUS_SUCCESS success
  590. */
  591. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  592. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  593. {
  594. struct qdf_tso_seg_elem_t *tso_seg;
  595. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  596. struct dp_soc *soc = vdev->pdev->soc;
  597. struct dp_pdev *pdev = vdev->pdev;
  598. struct qdf_tso_info_t *tso_info;
  599. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  600. tso_info = &msdu_info->u.tso_info;
  601. tso_info->curr_seg = NULL;
  602. tso_info->tso_seg_list = NULL;
  603. tso_info->num_segs = num_seg;
  604. msdu_info->frm_type = dp_tx_frm_tso;
  605. tso_info->tso_num_seg_list = NULL;
  606. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  607. while (num_seg) {
  608. tso_seg = dp_tx_tso_desc_alloc(
  609. soc, msdu_info->tx_queue.desc_pool_id);
  610. if (tso_seg) {
  611. tso_seg->next = tso_info->tso_seg_list;
  612. tso_info->tso_seg_list = tso_seg;
  613. num_seg--;
  614. } else {
  615. dp_err_rl("Failed to alloc tso seg desc");
  616. DP_STATS_INC_PKT(vdev->pdev,
  617. tso_stats.tso_no_mem_dropped, 1,
  618. qdf_nbuf_len(msdu));
  619. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  620. return QDF_STATUS_E_NOMEM;
  621. }
  622. }
  623. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  624. tso_num_seg = dp_tso_num_seg_alloc(soc,
  625. msdu_info->tx_queue.desc_pool_id);
  626. if (tso_num_seg) {
  627. tso_num_seg->next = tso_info->tso_num_seg_list;
  628. tso_info->tso_num_seg_list = tso_num_seg;
  629. } else {
  630. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  631. __func__);
  632. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  633. return QDF_STATUS_E_NOMEM;
  634. }
  635. msdu_info->num_seg =
  636. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  637. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  638. msdu_info->num_seg);
  639. if (!(msdu_info->num_seg)) {
  640. /*
  641. * Free allocated TSO seg desc and number seg desc,
  642. * do unmap for segments if dma map has done.
  643. */
  644. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  645. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  646. return QDF_STATUS_E_INVAL;
  647. }
  648. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  649. msdu, 0, DP_TX_DESC_MAP);
  650. tso_info->curr_seg = tso_info->tso_seg_list;
  651. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  652. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  653. msdu, msdu_info->num_seg);
  654. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  655. tso_info->msdu_stats_idx);
  656. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  657. return QDF_STATUS_SUCCESS;
  658. }
  659. #else
  660. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  661. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  662. {
  663. return QDF_STATUS_E_NOMEM;
  664. }
  665. #endif
  666. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  667. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  668. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  669. /**
  670. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  671. * @vdev: DP Vdev handle
  672. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  673. * @desc_pool_id: Descriptor Pool ID
  674. *
  675. * Return:
  676. */
  677. static
  678. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  679. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  680. {
  681. uint8_t i;
  682. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  683. struct dp_tx_seg_info_s *seg_info;
  684. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  685. struct dp_soc *soc = vdev->pdev->soc;
  686. /* Allocate an extension descriptor */
  687. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  688. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  689. if (!msdu_ext_desc) {
  690. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  691. return NULL;
  692. }
  693. if (msdu_info->exception_fw &&
  694. qdf_unlikely(vdev->mesh_vdev)) {
  695. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  696. &msdu_info->meta_data[0],
  697. sizeof(struct htt_tx_msdu_desc_ext2_t));
  698. qdf_atomic_inc(&soc->num_tx_exception);
  699. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  700. }
  701. switch (msdu_info->frm_type) {
  702. case dp_tx_frm_sg:
  703. case dp_tx_frm_me:
  704. case dp_tx_frm_raw:
  705. seg_info = msdu_info->u.sg_info.curr_seg;
  706. /* Update the buffer pointers in MSDU Extension Descriptor */
  707. for (i = 0; i < seg_info->frag_cnt; i++) {
  708. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  709. seg_info->frags[i].paddr_lo,
  710. seg_info->frags[i].paddr_hi,
  711. seg_info->frags[i].len);
  712. }
  713. break;
  714. case dp_tx_frm_tso:
  715. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  716. &cached_ext_desc[0]);
  717. break;
  718. default:
  719. break;
  720. }
  721. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  722. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  723. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  724. msdu_ext_desc->vaddr);
  725. return msdu_ext_desc;
  726. }
  727. /**
  728. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  729. * @soc: datapath SOC
  730. * @skb: skb to be traced
  731. * @msdu_id: msdu_id of the packet
  732. * @vdev_id: vdev_id of the packet
  733. *
  734. * Return: None
  735. */
  736. #ifdef DP_DISABLE_TX_PKT_TRACE
  737. static void dp_tx_trace_pkt(struct dp_soc *soc,
  738. qdf_nbuf_t skb, uint16_t msdu_id,
  739. uint8_t vdev_id)
  740. {
  741. }
  742. #else
  743. static void dp_tx_trace_pkt(struct dp_soc *soc,
  744. qdf_nbuf_t skb, uint16_t msdu_id,
  745. uint8_t vdev_id)
  746. {
  747. if (dp_is_tput_high(soc))
  748. return;
  749. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  750. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  751. DPTRACE(qdf_dp_trace_ptr(skb,
  752. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  753. QDF_TRACE_DEFAULT_PDEV_ID,
  754. qdf_nbuf_data_addr(skb),
  755. sizeof(qdf_nbuf_data(skb)),
  756. msdu_id, vdev_id, 0));
  757. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  758. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  759. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  760. msdu_id, QDF_TX));
  761. }
  762. #endif
  763. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  764. /**
  765. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  766. * exception by the upper layer (OS_IF)
  767. * @soc: DP soc handle
  768. * @nbuf: packet to be transmitted
  769. *
  770. * Return: 1 if the packet is marked as exception,
  771. * 0, if the packet is not marked as exception.
  772. */
  773. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  774. qdf_nbuf_t nbuf)
  775. {
  776. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  777. }
  778. #else
  779. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  780. qdf_nbuf_t nbuf)
  781. {
  782. return 0;
  783. }
  784. #endif
  785. #ifdef DP_TRAFFIC_END_INDICATION
  786. /**
  787. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  788. * as indication to fw to inform that
  789. * data stream has ended
  790. * @vdev: DP vdev handle
  791. * @nbuf: original buffer from network stack
  792. *
  793. * Return: NULL on failure,
  794. * nbuf on success
  795. */
  796. static inline qdf_nbuf_t
  797. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  798. qdf_nbuf_t nbuf)
  799. {
  800. /* Packet length should be enough to copy upto L3 header */
  801. uint8_t end_nbuf_len = 64;
  802. uint8_t htt_desc_size_aligned;
  803. uint8_t htt_desc_size;
  804. qdf_nbuf_t end_nbuf;
  805. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  806. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  807. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  808. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  809. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  810. if (!end_nbuf) {
  811. end_nbuf = qdf_nbuf_alloc(NULL,
  812. (htt_desc_size_aligned +
  813. end_nbuf_len),
  814. htt_desc_size_aligned,
  815. 8, false);
  816. if (!end_nbuf) {
  817. dp_err("Packet allocation failed");
  818. goto out;
  819. }
  820. } else {
  821. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  822. }
  823. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  824. end_nbuf_len);
  825. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  826. return end_nbuf;
  827. }
  828. out:
  829. return NULL;
  830. }
  831. /**
  832. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  833. * via exception path.
  834. * @vdev: DP vdev handle
  835. * @end_nbuf: skb to send as indication
  836. * @msdu_info: msdu_info of original nbuf
  837. * @peer_id: peer id
  838. *
  839. * Return: None
  840. */
  841. static inline void
  842. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  843. qdf_nbuf_t end_nbuf,
  844. struct dp_tx_msdu_info_s *msdu_info,
  845. uint16_t peer_id)
  846. {
  847. struct dp_tx_msdu_info_s e_msdu_info = {0};
  848. qdf_nbuf_t nbuf;
  849. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  850. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  851. e_msdu_info.tx_queue = msdu_info->tx_queue;
  852. e_msdu_info.tid = msdu_info->tid;
  853. e_msdu_info.exception_fw = 1;
  854. desc_ext->host_tx_desc_pool = 1;
  855. desc_ext->traffic_end_indication = 1;
  856. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  857. peer_id, NULL);
  858. if (nbuf) {
  859. dp_err("Traffic end indication packet tx failed");
  860. qdf_nbuf_free(nbuf);
  861. }
  862. }
  863. /**
  864. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  865. * mark it traffic end indication
  866. * packet.
  867. * @tx_desc: Tx descriptor pointer
  868. * @msdu_info: msdu_info structure pointer
  869. *
  870. * Return: None
  871. */
  872. static inline void
  873. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  874. struct dp_tx_msdu_info_s *msdu_info)
  875. {
  876. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  877. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  878. if (qdf_unlikely(desc_ext->traffic_end_indication))
  879. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  880. }
  881. /**
  882. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  883. * freeing which are associated
  884. * with traffic end indication
  885. * flagged descriptor.
  886. * @soc: dp soc handle
  887. * @desc: Tx descriptor pointer
  888. * @nbuf: buffer pointer
  889. *
  890. * Return: True if packet gets enqueued else false
  891. */
  892. static bool
  893. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  894. struct dp_tx_desc_s *desc,
  895. qdf_nbuf_t nbuf)
  896. {
  897. struct dp_vdev *vdev = NULL;
  898. if (qdf_unlikely((desc->flags &
  899. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  900. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  901. DP_MOD_ID_TX_COMP);
  902. if (vdev) {
  903. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  904. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  905. return true;
  906. }
  907. }
  908. return false;
  909. }
  910. /**
  911. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  912. * enable/disable status
  913. * @vdev: dp vdev handle
  914. *
  915. * Return: True if feature is enable else false
  916. */
  917. static inline bool
  918. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  919. {
  920. return qdf_unlikely(vdev->traffic_end_ind_en);
  921. }
  922. static inline qdf_nbuf_t
  923. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  924. struct dp_tx_msdu_info_s *msdu_info,
  925. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  926. {
  927. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  928. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  929. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  930. if (qdf_unlikely(end_nbuf))
  931. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  932. msdu_info, peer_id);
  933. return nbuf;
  934. }
  935. #else
  936. static inline qdf_nbuf_t
  937. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  938. qdf_nbuf_t nbuf)
  939. {
  940. return NULL;
  941. }
  942. static inline void
  943. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  944. qdf_nbuf_t end_nbuf,
  945. struct dp_tx_msdu_info_s *msdu_info,
  946. uint16_t peer_id)
  947. {}
  948. static inline void
  949. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  950. struct dp_tx_msdu_info_s *msdu_info)
  951. {}
  952. static inline bool
  953. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  954. struct dp_tx_desc_s *desc,
  955. qdf_nbuf_t nbuf)
  956. {
  957. return false;
  958. }
  959. static inline bool
  960. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  961. {
  962. return false;
  963. }
  964. static inline qdf_nbuf_t
  965. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  966. struct dp_tx_msdu_info_s *msdu_info,
  967. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  968. {
  969. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  970. }
  971. #endif
  972. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  973. static bool
  974. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  975. struct cdp_tx_exception_metadata *tx_exc_metadata)
  976. {
  977. if (soc->features.wds_ext_ast_override_enable &&
  978. tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  979. return true;
  980. return false;
  981. }
  982. #else
  983. static bool
  984. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  985. struct cdp_tx_exception_metadata *tx_exc_metadata)
  986. {
  987. return false;
  988. }
  989. #endif
  990. /**
  991. * dp_tx_prepare_desc_single() - Allocate and prepare Tx descriptor
  992. * @vdev: DP vdev handle
  993. * @nbuf: skb
  994. * @desc_pool_id: Descriptor pool ID
  995. * @msdu_info: Metadata to the fw
  996. * @tx_exc_metadata: Handle that holds exception path metadata
  997. *
  998. * Allocate and prepare Tx descriptor with msdu information.
  999. *
  1000. * Return: Pointer to Tx Descriptor on success,
  1001. * NULL on failure
  1002. */
  1003. static
  1004. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1005. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1006. struct dp_tx_msdu_info_s *msdu_info,
  1007. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1008. {
  1009. uint8_t align_pad;
  1010. uint8_t is_exception = 0;
  1011. uint8_t htt_hdr_size;
  1012. struct dp_tx_desc_s *tx_desc;
  1013. struct dp_pdev *pdev = vdev->pdev;
  1014. struct dp_soc *soc = pdev->soc;
  1015. if (dp_tx_limit_check(vdev, nbuf))
  1016. return NULL;
  1017. /* Allocate software Tx descriptor */
  1018. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1019. if (qdf_unlikely(!tx_desc)) {
  1020. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1021. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1022. return NULL;
  1023. }
  1024. dp_tx_outstanding_inc(pdev);
  1025. /* Initialize the SW tx descriptor */
  1026. tx_desc->nbuf = nbuf;
  1027. tx_desc->frm_type = dp_tx_frm_std;
  1028. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1029. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1030. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1031. tx_desc->vdev_id = vdev->vdev_id;
  1032. tx_desc->pdev = pdev;
  1033. tx_desc->msdu_ext_desc = NULL;
  1034. tx_desc->pkt_offset = 0;
  1035. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1036. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1037. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1038. if (qdf_unlikely(vdev->multipass_en)) {
  1039. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1040. goto failure;
  1041. }
  1042. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1043. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1044. is_exception = 1;
  1045. /* for BE chipsets if wds extension was enbled will not mark FW
  1046. * in desc will mark ast index based search for ast index.
  1047. */
  1048. if (dp_tx_is_wds_ast_override_en(soc, tx_exc_metadata))
  1049. return tx_desc;
  1050. /*
  1051. * For special modes (vdev_type == ocb or mesh), data frames should be
  1052. * transmitted using varying transmit parameters (tx spec) which include
  1053. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1054. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1055. * These frames are sent as exception packets to firmware.
  1056. *
  1057. * HW requirement is that metadata should always point to a
  1058. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1059. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1060. * to get 8-byte aligned start address along with align_pad added
  1061. *
  1062. * |-----------------------------|
  1063. * | |
  1064. * |-----------------------------| <-----Buffer Pointer Address given
  1065. * | | ^ in HW descriptor (aligned)
  1066. * | HTT Metadata | |
  1067. * | | |
  1068. * | | | Packet Offset given in descriptor
  1069. * | | |
  1070. * |-----------------------------| |
  1071. * | Alignment Pad | v
  1072. * |-----------------------------| <----- Actual buffer start address
  1073. * | SKB Data | (Unaligned)
  1074. * | |
  1075. * | |
  1076. * | |
  1077. * | |
  1078. * | |
  1079. * |-----------------------------|
  1080. */
  1081. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1082. (vdev->opmode == wlan_op_mode_ocb) ||
  1083. (tx_exc_metadata &&
  1084. tx_exc_metadata->is_tx_sniffer)) {
  1085. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1086. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1087. DP_STATS_INC(vdev,
  1088. tx_i.dropped.headroom_insufficient, 1);
  1089. goto failure;
  1090. }
  1091. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1092. dp_tx_err("qdf_nbuf_push_head failed");
  1093. goto failure;
  1094. }
  1095. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1096. msdu_info);
  1097. if (htt_hdr_size == 0)
  1098. goto failure;
  1099. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1100. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1101. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1102. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1103. msdu_info);
  1104. is_exception = 1;
  1105. tx_desc->length -= tx_desc->pkt_offset;
  1106. }
  1107. #if !TQM_BYPASS_WAR
  1108. if (is_exception || tx_exc_metadata)
  1109. #endif
  1110. {
  1111. /* Temporary WAR due to TQM VP issues */
  1112. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1113. qdf_atomic_inc(&soc->num_tx_exception);
  1114. }
  1115. return tx_desc;
  1116. failure:
  1117. dp_tx_desc_release(tx_desc, desc_pool_id);
  1118. return NULL;
  1119. }
  1120. /**
  1121. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment
  1122. * frame
  1123. * @vdev: DP vdev handle
  1124. * @nbuf: skb
  1125. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1126. * @desc_pool_id : Descriptor Pool ID
  1127. *
  1128. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1129. * information. For frames with fragments, allocate and prepare
  1130. * an MSDU extension descriptor
  1131. *
  1132. * Return: Pointer to Tx Descriptor on success,
  1133. * NULL on failure
  1134. */
  1135. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1136. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1137. uint8_t desc_pool_id)
  1138. {
  1139. struct dp_tx_desc_s *tx_desc;
  1140. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1141. struct dp_pdev *pdev = vdev->pdev;
  1142. struct dp_soc *soc = pdev->soc;
  1143. if (dp_tx_limit_check(vdev, nbuf))
  1144. return NULL;
  1145. /* Allocate software Tx descriptor */
  1146. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1147. if (!tx_desc) {
  1148. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1149. return NULL;
  1150. }
  1151. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1152. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1153. dp_tx_outstanding_inc(pdev);
  1154. /* Initialize the SW tx descriptor */
  1155. tx_desc->nbuf = nbuf;
  1156. tx_desc->frm_type = msdu_info->frm_type;
  1157. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1158. tx_desc->vdev_id = vdev->vdev_id;
  1159. tx_desc->pdev = pdev;
  1160. tx_desc->pkt_offset = 0;
  1161. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1162. /* Handle scattered frames - TSO/SG/ME */
  1163. /* Allocate and prepare an extension descriptor for scattered frames */
  1164. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1165. if (!msdu_ext_desc) {
  1166. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1167. goto failure;
  1168. }
  1169. #if TQM_BYPASS_WAR
  1170. /* Temporary WAR due to TQM VP issues */
  1171. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1172. qdf_atomic_inc(&soc->num_tx_exception);
  1173. #endif
  1174. if (qdf_unlikely(msdu_info->exception_fw))
  1175. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1176. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1177. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1178. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1179. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1180. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1181. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1182. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1183. else
  1184. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1185. return tx_desc;
  1186. failure:
  1187. dp_tx_desc_release(tx_desc, desc_pool_id);
  1188. return NULL;
  1189. }
  1190. /**
  1191. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1192. * @vdev: DP vdev handle
  1193. * @nbuf: buffer pointer
  1194. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1195. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1196. * descriptor
  1197. *
  1198. * Return:
  1199. */
  1200. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1201. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1202. {
  1203. qdf_nbuf_t curr_nbuf = NULL;
  1204. uint16_t total_len = 0;
  1205. qdf_dma_addr_t paddr;
  1206. int32_t i;
  1207. int32_t mapped_buf_num = 0;
  1208. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1209. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1210. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1211. /* Continue only if frames are of DATA type */
  1212. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1213. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1214. dp_tx_debug("Pkt. recd is of not data type");
  1215. goto error;
  1216. }
  1217. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1218. if (vdev->raw_mode_war &&
  1219. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1220. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1221. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1222. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1223. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1224. /*
  1225. * Number of nbuf's must not exceed the size of the frags
  1226. * array in seg_info.
  1227. */
  1228. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1229. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1230. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1231. goto error;
  1232. }
  1233. if (QDF_STATUS_SUCCESS !=
  1234. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1235. curr_nbuf,
  1236. QDF_DMA_TO_DEVICE,
  1237. curr_nbuf->len)) {
  1238. dp_tx_err("%s dma map error ", __func__);
  1239. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1240. goto error;
  1241. }
  1242. /* Update the count of mapped nbuf's */
  1243. mapped_buf_num++;
  1244. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1245. seg_info->frags[i].paddr_lo = paddr;
  1246. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1247. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1248. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1249. total_len += qdf_nbuf_len(curr_nbuf);
  1250. }
  1251. seg_info->frag_cnt = i;
  1252. seg_info->total_len = total_len;
  1253. seg_info->next = NULL;
  1254. sg_info->curr_seg = seg_info;
  1255. msdu_info->frm_type = dp_tx_frm_raw;
  1256. msdu_info->num_seg = 1;
  1257. return nbuf;
  1258. error:
  1259. i = 0;
  1260. while (nbuf) {
  1261. curr_nbuf = nbuf;
  1262. if (i < mapped_buf_num) {
  1263. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1264. QDF_DMA_TO_DEVICE,
  1265. curr_nbuf->len);
  1266. i++;
  1267. }
  1268. nbuf = qdf_nbuf_next(nbuf);
  1269. qdf_nbuf_free(curr_nbuf);
  1270. }
  1271. return NULL;
  1272. }
  1273. /**
  1274. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1275. * @soc: DP soc handle
  1276. * @nbuf: Buffer pointer
  1277. *
  1278. * unmap the chain of nbufs that belong to this RAW frame.
  1279. *
  1280. * Return: None
  1281. */
  1282. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1283. qdf_nbuf_t nbuf)
  1284. {
  1285. qdf_nbuf_t cur_nbuf = nbuf;
  1286. do {
  1287. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1288. QDF_DMA_TO_DEVICE,
  1289. cur_nbuf->len);
  1290. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1291. } while (cur_nbuf);
  1292. }
  1293. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1294. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1295. qdf_nbuf_t nbuf)
  1296. {
  1297. qdf_nbuf_t nbuf_local;
  1298. struct dp_vdev *vdev_local = vdev_hdl;
  1299. do {
  1300. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1301. break;
  1302. nbuf_local = nbuf;
  1303. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1304. htt_cmn_pkt_type_raw))
  1305. break;
  1306. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1307. break;
  1308. else if (qdf_nbuf_is_tso((nbuf_local)))
  1309. break;
  1310. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1311. (nbuf_local),
  1312. NULL, 1, 0);
  1313. } while (0);
  1314. }
  1315. #endif
  1316. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1317. void dp_tx_update_stats(struct dp_soc *soc,
  1318. struct dp_tx_desc_s *tx_desc,
  1319. uint8_t ring_id)
  1320. {
  1321. uint32_t stats_len = dp_tx_get_pkt_len(tx_desc);
  1322. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1323. }
  1324. int
  1325. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1326. struct dp_tx_desc_s *tx_desc,
  1327. uint8_t tid,
  1328. struct dp_tx_msdu_info_s *msdu_info,
  1329. uint8_t ring_id)
  1330. {
  1331. struct dp_swlm *swlm = &soc->swlm;
  1332. union swlm_data swlm_query_data;
  1333. struct dp_swlm_tcl_data tcl_data;
  1334. QDF_STATUS status;
  1335. int ret;
  1336. if (!swlm->is_enabled)
  1337. return msdu_info->skip_hp_update;
  1338. tcl_data.nbuf = tx_desc->nbuf;
  1339. tcl_data.tid = tid;
  1340. tcl_data.ring_id = ring_id;
  1341. tcl_data.pkt_len = dp_tx_get_pkt_len(tx_desc);
  1342. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1343. swlm_query_data.tcl_data = &tcl_data;
  1344. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1345. if (QDF_IS_STATUS_ERROR(status)) {
  1346. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1347. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1348. return 0;
  1349. }
  1350. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1351. if (ret) {
  1352. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1353. } else {
  1354. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1355. }
  1356. return ret;
  1357. }
  1358. void
  1359. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1360. int coalesce)
  1361. {
  1362. if (coalesce)
  1363. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1364. else
  1365. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1366. }
  1367. static inline void
  1368. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1369. {
  1370. if (((i + 1) < msdu_info->num_seg))
  1371. msdu_info->skip_hp_update = 1;
  1372. else
  1373. msdu_info->skip_hp_update = 0;
  1374. }
  1375. static inline void
  1376. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1377. {
  1378. hal_ring_handle_t hal_ring_hdl =
  1379. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1380. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1381. dp_err("Fillmore: SRNG access start failed");
  1382. return;
  1383. }
  1384. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1385. }
  1386. static inline void
  1387. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1388. QDF_STATUS status,
  1389. struct dp_tx_msdu_info_s *msdu_info)
  1390. {
  1391. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1392. dp_flush_tcp_hp(soc,
  1393. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1394. }
  1395. }
  1396. #else
  1397. static inline void
  1398. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1399. {
  1400. }
  1401. static inline void
  1402. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1403. QDF_STATUS status,
  1404. struct dp_tx_msdu_info_s *msdu_info)
  1405. {
  1406. }
  1407. #endif
  1408. #ifdef FEATURE_RUNTIME_PM
  1409. void
  1410. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1411. hal_ring_handle_t hal_ring_hdl,
  1412. int coalesce)
  1413. {
  1414. int ret;
  1415. /*
  1416. * Avoid runtime get and put APIs under high throughput scenarios.
  1417. */
  1418. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1419. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1420. return;
  1421. }
  1422. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1423. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1424. if (hif_system_pm_state_check(soc->hif_handle)) {
  1425. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1426. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1427. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1428. } else {
  1429. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1430. }
  1431. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1432. } else {
  1433. dp_runtime_get(soc);
  1434. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1435. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1436. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1437. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1438. dp_runtime_put(soc);
  1439. }
  1440. }
  1441. #else
  1442. #ifdef DP_POWER_SAVE
  1443. void
  1444. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1445. hal_ring_handle_t hal_ring_hdl,
  1446. int coalesce)
  1447. {
  1448. if (hif_system_pm_state_check(soc->hif_handle)) {
  1449. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1450. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1451. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1452. } else {
  1453. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1454. }
  1455. }
  1456. #endif
  1457. #endif
  1458. /**
  1459. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1460. * @vdev: DP vdev handle
  1461. * @nbuf: skb
  1462. * @msdu_info: msdu descriptor
  1463. *
  1464. * Extract the DSCP or PCP information from frame and map into TID value.
  1465. *
  1466. * Return: void
  1467. */
  1468. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1469. struct dp_tx_msdu_info_s *msdu_info)
  1470. {
  1471. uint8_t tos = 0, dscp_tid_override = 0;
  1472. uint8_t *hdr_ptr, *L3datap;
  1473. uint8_t is_mcast = 0;
  1474. qdf_ether_header_t *eh = NULL;
  1475. qdf_ethervlan_header_t *evh = NULL;
  1476. uint16_t ether_type;
  1477. qdf_llc_t *llcHdr;
  1478. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1479. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1480. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1481. eh = (qdf_ether_header_t *)nbuf->data;
  1482. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1483. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1484. } else {
  1485. qdf_dot3_qosframe_t *qos_wh =
  1486. (qdf_dot3_qosframe_t *) nbuf->data;
  1487. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1488. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1489. return;
  1490. }
  1491. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1492. ether_type = eh->ether_type;
  1493. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1494. /*
  1495. * Check if packet is dot3 or eth2 type.
  1496. */
  1497. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1498. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1499. sizeof(*llcHdr));
  1500. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1501. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1502. sizeof(*llcHdr);
  1503. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1504. + sizeof(*llcHdr) +
  1505. sizeof(qdf_net_vlanhdr_t));
  1506. } else {
  1507. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1508. sizeof(*llcHdr);
  1509. }
  1510. } else {
  1511. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1512. evh = (qdf_ethervlan_header_t *) eh;
  1513. ether_type = evh->ether_type;
  1514. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1515. }
  1516. }
  1517. /*
  1518. * Find priority from IP TOS DSCP field
  1519. */
  1520. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1521. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1522. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1523. /* Only for unicast frames */
  1524. if (!is_mcast) {
  1525. /* send it on VO queue */
  1526. msdu_info->tid = DP_VO_TID;
  1527. }
  1528. } else {
  1529. /*
  1530. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1531. * from TOS byte.
  1532. */
  1533. tos = ip->ip_tos;
  1534. dscp_tid_override = 1;
  1535. }
  1536. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1537. /* TODO
  1538. * use flowlabel
  1539. *igmpmld cases to be handled in phase 2
  1540. */
  1541. unsigned long ver_pri_flowlabel;
  1542. unsigned long pri;
  1543. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1544. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1545. DP_IPV6_PRIORITY_SHIFT;
  1546. tos = pri;
  1547. dscp_tid_override = 1;
  1548. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1549. msdu_info->tid = DP_VO_TID;
  1550. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1551. /* Only for unicast frames */
  1552. if (!is_mcast) {
  1553. /* send ucast arp on VO queue */
  1554. msdu_info->tid = DP_VO_TID;
  1555. }
  1556. }
  1557. /*
  1558. * Assign all MCAST packets to BE
  1559. */
  1560. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1561. if (is_mcast) {
  1562. tos = 0;
  1563. dscp_tid_override = 1;
  1564. }
  1565. }
  1566. if (dscp_tid_override == 1) {
  1567. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1568. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1569. }
  1570. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1571. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1572. return;
  1573. }
  1574. /**
  1575. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1576. * @vdev: DP vdev handle
  1577. * @nbuf: skb
  1578. * @msdu_info: msdu descriptor
  1579. *
  1580. * Software based TID classification is required when more than 2 DSCP-TID
  1581. * mapping tables are needed.
  1582. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1583. *
  1584. * Return: void
  1585. */
  1586. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1587. struct dp_tx_msdu_info_s *msdu_info)
  1588. {
  1589. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1590. /*
  1591. * skip_sw_tid_classification flag will set in below cases-
  1592. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1593. * 2. hlos_tid_override enabled for vdev
  1594. * 3. mesh mode enabled for vdev
  1595. */
  1596. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1597. /* Update tid in msdu_info from skb priority */
  1598. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1599. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1600. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1601. if (tid == DP_TX_INVALID_QOS_TAG)
  1602. return;
  1603. msdu_info->tid = tid;
  1604. return;
  1605. }
  1606. return;
  1607. }
  1608. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1609. }
  1610. #ifdef FEATURE_WLAN_TDLS
  1611. /**
  1612. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1613. * @soc: datapath SOC
  1614. * @vdev: datapath vdev
  1615. * @tx_desc: TX descriptor
  1616. *
  1617. * Return: None
  1618. */
  1619. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1620. struct dp_vdev *vdev,
  1621. struct dp_tx_desc_s *tx_desc)
  1622. {
  1623. if (vdev) {
  1624. if (vdev->is_tdls_frame) {
  1625. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1626. vdev->is_tdls_frame = false;
  1627. }
  1628. }
  1629. }
  1630. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1631. {
  1632. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1633. switch (soc->arch_id) {
  1634. case CDP_ARCH_TYPE_LI:
  1635. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1636. break;
  1637. case CDP_ARCH_TYPE_BE:
  1638. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1639. break;
  1640. case CDP_ARCH_TYPE_RH:
  1641. {
  1642. uint32_t *msg_word = (uint32_t *)htt_desc;
  1643. tx_status = HTT_TX_MSDU_INFO_RELEASE_REASON_GET(
  1644. *(msg_word + 3));
  1645. }
  1646. break;
  1647. default:
  1648. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1649. QDF_BUG(0);
  1650. }
  1651. return tx_status;
  1652. }
  1653. /**
  1654. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1655. * @soc: dp_soc handle
  1656. * @tx_desc: TX descriptor
  1657. *
  1658. * Return: None
  1659. */
  1660. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1661. struct dp_tx_desc_s *tx_desc)
  1662. {
  1663. uint8_t tx_status = 0;
  1664. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1665. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1666. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1667. DP_MOD_ID_TDLS);
  1668. if (qdf_unlikely(!vdev)) {
  1669. dp_err_rl("vdev is null!");
  1670. goto error;
  1671. }
  1672. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1673. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1674. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1675. if (vdev->tx_non_std_data_callback.func) {
  1676. qdf_nbuf_set_next(nbuf, NULL);
  1677. vdev->tx_non_std_data_callback.func(
  1678. vdev->tx_non_std_data_callback.ctxt,
  1679. nbuf, tx_status);
  1680. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1681. return;
  1682. } else {
  1683. dp_err_rl("callback func is null");
  1684. }
  1685. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1686. error:
  1687. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1688. qdf_nbuf_free(nbuf);
  1689. }
  1690. /**
  1691. * dp_tx_msdu_single_map() - do nbuf map
  1692. * @vdev: DP vdev handle
  1693. * @tx_desc: DP TX descriptor pointer
  1694. * @nbuf: skb pointer
  1695. *
  1696. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1697. * operation done in other component.
  1698. *
  1699. * Return: QDF_STATUS
  1700. */
  1701. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1702. struct dp_tx_desc_s *tx_desc,
  1703. qdf_nbuf_t nbuf)
  1704. {
  1705. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1706. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1707. nbuf,
  1708. QDF_DMA_TO_DEVICE,
  1709. nbuf->len);
  1710. else
  1711. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1712. QDF_DMA_TO_DEVICE);
  1713. }
  1714. #else
  1715. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1716. struct dp_vdev *vdev,
  1717. struct dp_tx_desc_s *tx_desc)
  1718. {
  1719. }
  1720. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1721. struct dp_tx_desc_s *tx_desc)
  1722. {
  1723. }
  1724. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1725. struct dp_tx_desc_s *tx_desc,
  1726. qdf_nbuf_t nbuf)
  1727. {
  1728. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1729. nbuf,
  1730. QDF_DMA_TO_DEVICE,
  1731. nbuf->len);
  1732. }
  1733. #endif
  1734. static inline
  1735. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1736. struct dp_tx_desc_s *tx_desc,
  1737. qdf_nbuf_t nbuf)
  1738. {
  1739. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1740. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1741. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1742. return 0;
  1743. return qdf_nbuf_mapped_paddr_get(nbuf);
  1744. }
  1745. static inline
  1746. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1747. {
  1748. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1749. desc->nbuf,
  1750. desc->dma_addr,
  1751. QDF_DMA_TO_DEVICE,
  1752. desc->length);
  1753. }
  1754. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1755. static inline bool
  1756. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1757. {
  1758. struct net_device *ingress_dev;
  1759. skb_frag_t *frag;
  1760. uint16_t buf_len = 0;
  1761. uint16_t linear_data_len = 0;
  1762. uint8_t *payload_addr = NULL;
  1763. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1764. if (!ingress_dev)
  1765. return false;
  1766. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1767. dev_put(ingress_dev);
  1768. frag = &(skb_shinfo(nbuf)->frags[0]);
  1769. buf_len = skb_frag_size(frag);
  1770. payload_addr = (uint8_t *)skb_frag_address(frag);
  1771. linear_data_len = skb_headlen(nbuf);
  1772. buf_len += linear_data_len;
  1773. payload_addr = payload_addr - linear_data_len;
  1774. memcpy(payload_addr, nbuf->data, linear_data_len);
  1775. msdu_info->frm_type = dp_tx_frm_rmnet;
  1776. msdu_info->buf_len = buf_len;
  1777. msdu_info->payload_addr = payload_addr;
  1778. return true;
  1779. }
  1780. dev_put(ingress_dev);
  1781. return false;
  1782. }
  1783. static inline
  1784. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1785. struct dp_tx_desc_s *tx_desc)
  1786. {
  1787. qdf_dma_addr_t paddr;
  1788. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1789. tx_desc->length = msdu_info->buf_len;
  1790. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1791. (void *)(msdu_info->payload_addr +
  1792. msdu_info->buf_len));
  1793. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1794. return paddr;
  1795. }
  1796. #else
  1797. static inline bool
  1798. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1799. {
  1800. return false;
  1801. }
  1802. static inline
  1803. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1804. struct dp_tx_desc_s *tx_desc)
  1805. {
  1806. return 0;
  1807. }
  1808. #endif
  1809. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1810. static inline
  1811. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1812. struct dp_tx_desc_s *tx_desc,
  1813. qdf_nbuf_t nbuf)
  1814. {
  1815. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1816. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1817. (void *)(nbuf->data + nbuf->len));
  1818. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1819. } else {
  1820. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1821. }
  1822. }
  1823. static inline
  1824. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1825. struct dp_tx_desc_s *desc)
  1826. {
  1827. if (qdf_unlikely(!(desc->flags &
  1828. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1829. return dp_tx_nbuf_unmap_regular(soc, desc);
  1830. }
  1831. #else
  1832. static inline
  1833. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1834. struct dp_tx_desc_s *tx_desc,
  1835. qdf_nbuf_t nbuf)
  1836. {
  1837. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1838. }
  1839. static inline
  1840. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1841. struct dp_tx_desc_s *desc)
  1842. {
  1843. return dp_tx_nbuf_unmap_regular(soc, desc);
  1844. }
  1845. #endif
  1846. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1847. static inline
  1848. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1849. {
  1850. dp_tx_nbuf_unmap(soc, desc);
  1851. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1852. }
  1853. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1854. {
  1855. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1856. dp_tx_nbuf_unmap(soc, desc);
  1857. }
  1858. #else
  1859. static inline
  1860. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1861. {
  1862. }
  1863. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1864. {
  1865. dp_tx_nbuf_unmap(soc, desc);
  1866. }
  1867. #endif
  1868. #ifdef MESH_MODE_SUPPORT
  1869. /**
  1870. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1871. * @soc: datapath SOC
  1872. * @vdev: datapath vdev
  1873. * @tx_desc: TX descriptor
  1874. *
  1875. * Return: None
  1876. */
  1877. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1878. struct dp_vdev *vdev,
  1879. struct dp_tx_desc_s *tx_desc)
  1880. {
  1881. if (qdf_unlikely(vdev->mesh_vdev))
  1882. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1883. }
  1884. /**
  1885. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1886. * @soc: dp_soc handle
  1887. * @tx_desc: TX descriptor
  1888. * @delayed_free: delay the nbuf free
  1889. *
  1890. * Return: nbuf to be freed late
  1891. */
  1892. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1893. struct dp_tx_desc_s *tx_desc,
  1894. bool delayed_free)
  1895. {
  1896. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1897. struct dp_vdev *vdev = NULL;
  1898. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1899. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1900. if (vdev)
  1901. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1902. if (delayed_free)
  1903. return nbuf;
  1904. qdf_nbuf_free(nbuf);
  1905. } else {
  1906. if (vdev && vdev->osif_tx_free_ext) {
  1907. vdev->osif_tx_free_ext((nbuf));
  1908. } else {
  1909. if (delayed_free)
  1910. return nbuf;
  1911. qdf_nbuf_free(nbuf);
  1912. }
  1913. }
  1914. if (vdev)
  1915. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1916. return NULL;
  1917. }
  1918. #else
  1919. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1920. struct dp_vdev *vdev,
  1921. struct dp_tx_desc_s *tx_desc)
  1922. {
  1923. }
  1924. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1925. struct dp_tx_desc_s *tx_desc,
  1926. bool delayed_free)
  1927. {
  1928. return NULL;
  1929. }
  1930. #endif
  1931. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1932. {
  1933. struct dp_pdev *pdev = NULL;
  1934. struct dp_ast_entry *src_ast_entry = NULL;
  1935. struct dp_ast_entry *dst_ast_entry = NULL;
  1936. struct dp_soc *soc = NULL;
  1937. qdf_assert(vdev);
  1938. pdev = vdev->pdev;
  1939. qdf_assert(pdev);
  1940. soc = pdev->soc;
  1941. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1942. (soc, dstmac, vdev->pdev->pdev_id);
  1943. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1944. (soc, srcmac, vdev->pdev->pdev_id);
  1945. if (dst_ast_entry && src_ast_entry) {
  1946. if (dst_ast_entry->peer_id ==
  1947. src_ast_entry->peer_id)
  1948. return 1;
  1949. }
  1950. return 0;
  1951. }
  1952. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  1953. defined(WLAN_MCAST_MLO)
  1954. /* MLO peer id for reinject*/
  1955. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  1956. /* MLO vdev id inc offset */
  1957. #define DP_MLO_VDEV_ID_OFFSET 0x80
  1958. #ifdef QCA_SUPPORT_WDS_EXTENDED
  1959. static inline bool
  1960. dp_tx_wds_ext_check(struct cdp_tx_exception_metadata *tx_exc_metadata)
  1961. {
  1962. if (tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  1963. return true;
  1964. return false;
  1965. }
  1966. #else
  1967. static inline bool
  1968. dp_tx_wds_ext_check(struct cdp_tx_exception_metadata *tx_exc_metadata)
  1969. {
  1970. return false;
  1971. }
  1972. #endif
  1973. static inline void
  1974. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  1975. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1976. {
  1977. /* wds ext enabled will not set the TO_FW bit */
  1978. if (dp_tx_wds_ext_check(tx_exc_metadata))
  1979. return;
  1980. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  1981. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1982. qdf_atomic_inc(&soc->num_tx_exception);
  1983. }
  1984. }
  1985. static inline void
  1986. dp_tx_update_mcast_param(uint16_t peer_id,
  1987. uint16_t *htt_tcl_metadata,
  1988. struct dp_vdev *vdev,
  1989. struct dp_tx_msdu_info_s *msdu_info)
  1990. {
  1991. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  1992. *htt_tcl_metadata = 0;
  1993. DP_TX_TCL_METADATA_TYPE_SET(
  1994. *htt_tcl_metadata,
  1995. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  1996. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  1997. msdu_info->gsn);
  1998. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  1999. if (qdf_unlikely(vdev->nawds_enabled ||
  2000. dp_vdev_is_wds_ext_enabled(vdev)))
  2001. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2002. *htt_tcl_metadata, 1);
  2003. } else {
  2004. msdu_info->vdev_id = vdev->vdev_id;
  2005. }
  2006. }
  2007. #else
  2008. static inline void
  2009. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  2010. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2011. {
  2012. }
  2013. static inline void
  2014. dp_tx_update_mcast_param(uint16_t peer_id,
  2015. uint16_t *htt_tcl_metadata,
  2016. struct dp_vdev *vdev,
  2017. struct dp_tx_msdu_info_s *msdu_info)
  2018. {
  2019. }
  2020. #endif
  2021. #ifdef DP_TX_SW_DROP_STATS_INC
  2022. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2023. qdf_nbuf_t nbuf,
  2024. enum cdp_tx_sw_drop drop_code)
  2025. {
  2026. /* EAPOL Drop stats */
  2027. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2028. switch (drop_code) {
  2029. case TX_DESC_ERR:
  2030. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2031. break;
  2032. case TX_HAL_RING_ACCESS_ERR:
  2033. DP_STATS_INC(pdev,
  2034. eap_drop_stats.tx_hal_ring_access_err, 1);
  2035. break;
  2036. case TX_DMA_MAP_ERR:
  2037. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2038. break;
  2039. case TX_HW_ENQUEUE:
  2040. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2041. break;
  2042. case TX_SW_ENQUEUE:
  2043. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2044. break;
  2045. default:
  2046. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2047. break;
  2048. }
  2049. }
  2050. }
  2051. #else
  2052. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2053. qdf_nbuf_t nbuf,
  2054. enum cdp_tx_sw_drop drop_code)
  2055. {
  2056. }
  2057. #endif
  2058. qdf_nbuf_t
  2059. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2060. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2061. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2062. {
  2063. struct dp_pdev *pdev = vdev->pdev;
  2064. struct dp_soc *soc = pdev->soc;
  2065. struct dp_tx_desc_s *tx_desc;
  2066. QDF_STATUS status;
  2067. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2068. uint16_t htt_tcl_metadata = 0;
  2069. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2070. uint8_t tid = msdu_info->tid;
  2071. struct cdp_tid_tx_stats *tid_stats = NULL;
  2072. qdf_dma_addr_t paddr;
  2073. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2074. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2075. msdu_info, tx_exc_metadata);
  2076. if (!tx_desc) {
  2077. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2078. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2079. drop_code = TX_DESC_ERR;
  2080. goto fail_return;
  2081. }
  2082. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2083. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2084. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2085. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2086. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2087. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2088. DP_TCL_METADATA_TYPE_PEER_BASED);
  2089. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2090. peer_id);
  2091. dp_tx_bypass_reinjection(soc, tx_desc, tx_exc_metadata);
  2092. } else
  2093. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2094. if (msdu_info->exception_fw)
  2095. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2096. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2097. !pdev->enhanced_stats_en);
  2098. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2099. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2100. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2101. else
  2102. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2103. if (!paddr) {
  2104. /* Handle failure */
  2105. dp_err("qdf_nbuf_map failed");
  2106. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2107. drop_code = TX_DMA_MAP_ERR;
  2108. goto release_desc;
  2109. }
  2110. tx_desc->dma_addr = paddr;
  2111. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2112. tx_desc->id, DP_TX_DESC_MAP);
  2113. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2114. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2115. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2116. htt_tcl_metadata,
  2117. tx_exc_metadata, msdu_info);
  2118. if (status != QDF_STATUS_SUCCESS) {
  2119. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2120. tx_desc, tx_q->ring_id);
  2121. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2122. tx_desc->id, DP_TX_DESC_UNMAP);
  2123. dp_tx_nbuf_unmap(soc, tx_desc);
  2124. drop_code = TX_HW_ENQUEUE;
  2125. goto release_desc;
  2126. }
  2127. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2128. return NULL;
  2129. release_desc:
  2130. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2131. fail_return:
  2132. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2133. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2134. tid_stats = &pdev->stats.tid_stats.
  2135. tid_tx_stats[tx_q->ring_id][tid];
  2136. tid_stats->swdrop_cnt[drop_code]++;
  2137. return nbuf;
  2138. }
  2139. /**
  2140. * dp_tdls_tx_comp_free_buff() - Free non std buffer when TDLS flag is set
  2141. * @soc: Soc handle
  2142. * @desc: software Tx descriptor to be processed
  2143. *
  2144. * Return: 0 if Success
  2145. */
  2146. #ifdef FEATURE_WLAN_TDLS
  2147. static inline int
  2148. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2149. {
  2150. /* If it is TDLS mgmt, don't unmap or free the frame */
  2151. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2152. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2153. return 0;
  2154. }
  2155. return 1;
  2156. }
  2157. #else
  2158. static inline int
  2159. dp_tdls_tx_comp_free_buff(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  2160. {
  2161. return 1;
  2162. }
  2163. #endif
  2164. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2165. bool delayed_free)
  2166. {
  2167. qdf_nbuf_t nbuf = desc->nbuf;
  2168. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2169. /* nbuf already freed in vdev detach path */
  2170. if (!nbuf)
  2171. return NULL;
  2172. if (!dp_tdls_tx_comp_free_buff(soc, desc))
  2173. return NULL;
  2174. /* 0 : MSDU buffer, 1 : MLE */
  2175. if (desc->msdu_ext_desc) {
  2176. /* TSO free */
  2177. if (hal_tx_ext_desc_get_tso_enable(
  2178. desc->msdu_ext_desc->vaddr)) {
  2179. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2180. desc->id, DP_TX_COMP_MSDU_EXT);
  2181. dp_tx_tso_seg_history_add(soc,
  2182. desc->msdu_ext_desc->tso_desc,
  2183. desc->nbuf, desc->id, type);
  2184. /* unmap eash TSO seg before free the nbuf */
  2185. dp_tx_tso_unmap_segment(soc,
  2186. desc->msdu_ext_desc->tso_desc,
  2187. desc->msdu_ext_desc->
  2188. tso_num_desc);
  2189. goto nbuf_free;
  2190. }
  2191. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2192. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2193. qdf_dma_addr_t iova;
  2194. uint32_t frag_len;
  2195. uint32_t i;
  2196. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2197. QDF_DMA_TO_DEVICE,
  2198. qdf_nbuf_headlen(nbuf));
  2199. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2200. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2201. &iova,
  2202. &frag_len);
  2203. if (!iova || !frag_len)
  2204. break;
  2205. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2206. QDF_DMA_TO_DEVICE);
  2207. }
  2208. goto nbuf_free;
  2209. }
  2210. }
  2211. /* If it's ME frame, dont unmap the cloned nbuf's */
  2212. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2213. goto nbuf_free;
  2214. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2215. dp_tx_unmap(soc, desc);
  2216. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2217. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2218. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2219. return NULL;
  2220. nbuf_free:
  2221. if (delayed_free)
  2222. return nbuf;
  2223. qdf_nbuf_free(nbuf);
  2224. return NULL;
  2225. }
  2226. /**
  2227. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2228. * @soc: DP soc handle
  2229. * @nbuf: skb
  2230. * @msdu_info: MSDU info
  2231. *
  2232. * Return: None
  2233. */
  2234. static inline void
  2235. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2236. struct dp_tx_msdu_info_s *msdu_info)
  2237. {
  2238. uint32_t cur_idx;
  2239. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2240. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2241. qdf_nbuf_headlen(nbuf));
  2242. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2243. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2244. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2245. seg->frags[cur_idx].paddr_hi) << 32),
  2246. seg->frags[cur_idx].len,
  2247. QDF_DMA_TO_DEVICE);
  2248. }
  2249. #if QDF_LOCK_STATS
  2250. noinline
  2251. #else
  2252. #endif
  2253. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2254. struct dp_tx_msdu_info_s *msdu_info)
  2255. {
  2256. uint32_t i;
  2257. struct dp_pdev *pdev = vdev->pdev;
  2258. struct dp_soc *soc = pdev->soc;
  2259. struct dp_tx_desc_s *tx_desc;
  2260. bool is_cce_classified = false;
  2261. QDF_STATUS status;
  2262. uint16_t htt_tcl_metadata = 0;
  2263. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2264. struct cdp_tid_tx_stats *tid_stats = NULL;
  2265. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2266. if (msdu_info->frm_type == dp_tx_frm_me)
  2267. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2268. i = 0;
  2269. /* Print statement to track i and num_seg */
  2270. /*
  2271. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2272. * descriptors using information in msdu_info
  2273. */
  2274. while (i < msdu_info->num_seg) {
  2275. /*
  2276. * Setup Tx descriptor for an MSDU, and MSDU extension
  2277. * descriptor
  2278. */
  2279. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2280. tx_q->desc_pool_id);
  2281. if (!tx_desc) {
  2282. if (msdu_info->frm_type == dp_tx_frm_me) {
  2283. prep_desc_fail++;
  2284. dp_tx_me_free_buf(pdev,
  2285. (void *)(msdu_info->u.sg_info
  2286. .curr_seg->frags[0].vaddr));
  2287. if (prep_desc_fail == msdu_info->num_seg) {
  2288. /*
  2289. * Unmap is needed only if descriptor
  2290. * preparation failed for all segments.
  2291. */
  2292. qdf_nbuf_unmap(soc->osdev,
  2293. msdu_info->u.sg_info.
  2294. curr_seg->nbuf,
  2295. QDF_DMA_TO_DEVICE);
  2296. }
  2297. /*
  2298. * Free the nbuf for the current segment
  2299. * and make it point to the next in the list.
  2300. * For me, there are as many segments as there
  2301. * are no of clients.
  2302. */
  2303. qdf_nbuf_free(msdu_info->u.sg_info
  2304. .curr_seg->nbuf);
  2305. if (msdu_info->u.sg_info.curr_seg->next) {
  2306. msdu_info->u.sg_info.curr_seg =
  2307. msdu_info->u.sg_info
  2308. .curr_seg->next;
  2309. nbuf = msdu_info->u.sg_info
  2310. .curr_seg->nbuf;
  2311. }
  2312. i++;
  2313. continue;
  2314. }
  2315. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2316. dp_tx_tso_seg_history_add(
  2317. soc,
  2318. msdu_info->u.tso_info.curr_seg,
  2319. nbuf, 0, DP_TX_DESC_UNMAP);
  2320. dp_tx_tso_unmap_segment(soc,
  2321. msdu_info->u.tso_info.
  2322. curr_seg,
  2323. msdu_info->u.tso_info.
  2324. tso_num_seg_list);
  2325. if (msdu_info->u.tso_info.curr_seg->next) {
  2326. msdu_info->u.tso_info.curr_seg =
  2327. msdu_info->u.tso_info.curr_seg->next;
  2328. i++;
  2329. continue;
  2330. }
  2331. }
  2332. if (msdu_info->frm_type == dp_tx_frm_sg)
  2333. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2334. goto done;
  2335. }
  2336. if (msdu_info->frm_type == dp_tx_frm_me) {
  2337. tx_desc->msdu_ext_desc->me_buffer =
  2338. (struct dp_tx_me_buf_t *)msdu_info->
  2339. u.sg_info.curr_seg->frags[0].vaddr;
  2340. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2341. }
  2342. if (is_cce_classified)
  2343. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2344. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2345. if (msdu_info->exception_fw) {
  2346. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2347. }
  2348. dp_tx_is_hp_update_required(i, msdu_info);
  2349. /*
  2350. * For frames with multiple segments (TSO, ME), jump to next
  2351. * segment.
  2352. */
  2353. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2354. if (msdu_info->u.tso_info.curr_seg->next) {
  2355. msdu_info->u.tso_info.curr_seg =
  2356. msdu_info->u.tso_info.curr_seg->next;
  2357. /*
  2358. * If this is a jumbo nbuf, then increment the
  2359. * number of nbuf users for each additional
  2360. * segment of the msdu. This will ensure that
  2361. * the skb is freed only after receiving tx
  2362. * completion for all segments of an nbuf
  2363. */
  2364. qdf_nbuf_inc_users(nbuf);
  2365. /* Check with MCL if this is needed */
  2366. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2367. */
  2368. }
  2369. }
  2370. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2371. &htt_tcl_metadata,
  2372. vdev,
  2373. msdu_info);
  2374. /*
  2375. * Enqueue the Tx MSDU descriptor to HW for transmit
  2376. */
  2377. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2378. htt_tcl_metadata,
  2379. NULL, msdu_info);
  2380. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2381. if (status != QDF_STATUS_SUCCESS) {
  2382. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2383. tx_desc, tx_q->ring_id);
  2384. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2385. tid_stats = &pdev->stats.tid_stats.
  2386. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2387. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2388. if (msdu_info->frm_type == dp_tx_frm_me) {
  2389. hw_enq_fail++;
  2390. if (hw_enq_fail == msdu_info->num_seg) {
  2391. /*
  2392. * Unmap is needed only if enqueue
  2393. * failed for all segments.
  2394. */
  2395. qdf_nbuf_unmap(soc->osdev,
  2396. msdu_info->u.sg_info.
  2397. curr_seg->nbuf,
  2398. QDF_DMA_TO_DEVICE);
  2399. }
  2400. /*
  2401. * Free the nbuf for the current segment
  2402. * and make it point to the next in the list.
  2403. * For me, there are as many segments as there
  2404. * are no of clients.
  2405. */
  2406. qdf_nbuf_free(msdu_info->u.sg_info
  2407. .curr_seg->nbuf);
  2408. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2409. if (msdu_info->u.sg_info.curr_seg->next) {
  2410. msdu_info->u.sg_info.curr_seg =
  2411. msdu_info->u.sg_info
  2412. .curr_seg->next;
  2413. nbuf = msdu_info->u.sg_info
  2414. .curr_seg->nbuf;
  2415. } else
  2416. break;
  2417. i++;
  2418. continue;
  2419. }
  2420. /*
  2421. * For TSO frames, the nbuf users increment done for
  2422. * the current segment has to be reverted, since the
  2423. * hw enqueue for this segment failed
  2424. */
  2425. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2426. msdu_info->u.tso_info.curr_seg) {
  2427. /*
  2428. * unmap and free current,
  2429. * retransmit remaining segments
  2430. */
  2431. dp_tx_comp_free_buf(soc, tx_desc, false);
  2432. i++;
  2433. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2434. continue;
  2435. }
  2436. if (msdu_info->frm_type == dp_tx_frm_sg)
  2437. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2438. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2439. goto done;
  2440. }
  2441. /*
  2442. * TODO
  2443. * if tso_info structure can be modified to have curr_seg
  2444. * as first element, following 2 blocks of code (for TSO and SG)
  2445. * can be combined into 1
  2446. */
  2447. /*
  2448. * For Multicast-Unicast converted packets,
  2449. * each converted frame (for a client) is represented as
  2450. * 1 segment
  2451. */
  2452. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2453. (msdu_info->frm_type == dp_tx_frm_me)) {
  2454. if (msdu_info->u.sg_info.curr_seg->next) {
  2455. msdu_info->u.sg_info.curr_seg =
  2456. msdu_info->u.sg_info.curr_seg->next;
  2457. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2458. } else
  2459. break;
  2460. }
  2461. i++;
  2462. }
  2463. nbuf = NULL;
  2464. done:
  2465. return nbuf;
  2466. }
  2467. /**
  2468. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2469. * for SG frames
  2470. * @vdev: DP vdev handle
  2471. * @nbuf: skb
  2472. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2473. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2474. *
  2475. * Return: NULL on success,
  2476. * nbuf when it fails to send
  2477. */
  2478. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2479. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2480. {
  2481. uint32_t cur_frag, nr_frags, i;
  2482. qdf_dma_addr_t paddr;
  2483. struct dp_tx_sg_info_s *sg_info;
  2484. sg_info = &msdu_info->u.sg_info;
  2485. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2486. if (QDF_STATUS_SUCCESS !=
  2487. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2488. QDF_DMA_TO_DEVICE,
  2489. qdf_nbuf_headlen(nbuf))) {
  2490. dp_tx_err("dma map error");
  2491. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2492. qdf_nbuf_free(nbuf);
  2493. return NULL;
  2494. }
  2495. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2496. seg_info->frags[0].paddr_lo = paddr;
  2497. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2498. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2499. seg_info->frags[0].vaddr = (void *) nbuf;
  2500. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2501. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2502. nbuf, 0,
  2503. QDF_DMA_TO_DEVICE,
  2504. cur_frag)) {
  2505. dp_tx_err("frag dma map error");
  2506. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2507. goto map_err;
  2508. }
  2509. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2510. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2511. seg_info->frags[cur_frag + 1].paddr_hi =
  2512. ((uint64_t) paddr) >> 32;
  2513. seg_info->frags[cur_frag + 1].len =
  2514. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2515. }
  2516. seg_info->frag_cnt = (cur_frag + 1);
  2517. seg_info->total_len = qdf_nbuf_len(nbuf);
  2518. seg_info->next = NULL;
  2519. sg_info->curr_seg = seg_info;
  2520. msdu_info->frm_type = dp_tx_frm_sg;
  2521. msdu_info->num_seg = 1;
  2522. return nbuf;
  2523. map_err:
  2524. /* restore paddr into nbuf before calling unmap */
  2525. qdf_nbuf_mapped_paddr_set(nbuf,
  2526. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2527. ((uint64_t)
  2528. seg_info->frags[0].paddr_hi) << 32));
  2529. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2530. QDF_DMA_TO_DEVICE,
  2531. seg_info->frags[0].len);
  2532. for (i = 1; i <= cur_frag; i++) {
  2533. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2534. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2535. seg_info->frags[i].paddr_hi) << 32),
  2536. seg_info->frags[i].len,
  2537. QDF_DMA_TO_DEVICE);
  2538. }
  2539. qdf_nbuf_free(nbuf);
  2540. return NULL;
  2541. }
  2542. /**
  2543. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2544. * @vdev: DP vdev handle
  2545. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2546. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2547. *
  2548. * Return: NULL on failure,
  2549. * nbuf when extracted successfully
  2550. */
  2551. static
  2552. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2553. struct dp_tx_msdu_info_s *msdu_info,
  2554. uint16_t ppdu_cookie)
  2555. {
  2556. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2557. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2558. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2559. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2560. (msdu_info->meta_data[5], 1);
  2561. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2562. (msdu_info->meta_data[5], 1);
  2563. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2564. (msdu_info->meta_data[6], ppdu_cookie);
  2565. msdu_info->exception_fw = 1;
  2566. msdu_info->is_tx_sniffer = 1;
  2567. }
  2568. #ifdef MESH_MODE_SUPPORT
  2569. /**
  2570. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2571. * and prepare msdu_info for mesh frames.
  2572. * @vdev: DP vdev handle
  2573. * @nbuf: skb
  2574. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2575. *
  2576. * Return: NULL on failure,
  2577. * nbuf when extracted successfully
  2578. */
  2579. static
  2580. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2581. struct dp_tx_msdu_info_s *msdu_info)
  2582. {
  2583. struct meta_hdr_s *mhdr;
  2584. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2585. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2586. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2587. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2588. msdu_info->exception_fw = 0;
  2589. goto remove_meta_hdr;
  2590. }
  2591. msdu_info->exception_fw = 1;
  2592. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2593. meta_data->host_tx_desc_pool = 1;
  2594. meta_data->update_peer_cache = 1;
  2595. meta_data->learning_frame = 1;
  2596. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2597. meta_data->power = mhdr->power;
  2598. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2599. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2600. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2601. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2602. meta_data->dyn_bw = 1;
  2603. meta_data->valid_pwr = 1;
  2604. meta_data->valid_mcs_mask = 1;
  2605. meta_data->valid_nss_mask = 1;
  2606. meta_data->valid_preamble_type = 1;
  2607. meta_data->valid_retries = 1;
  2608. meta_data->valid_bw_info = 1;
  2609. }
  2610. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2611. meta_data->encrypt_type = 0;
  2612. meta_data->valid_encrypt_type = 1;
  2613. meta_data->learning_frame = 0;
  2614. }
  2615. meta_data->valid_key_flags = 1;
  2616. meta_data->key_flags = (mhdr->keyix & 0x3);
  2617. remove_meta_hdr:
  2618. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2619. dp_tx_err("qdf_nbuf_pull_head failed");
  2620. qdf_nbuf_free(nbuf);
  2621. return NULL;
  2622. }
  2623. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2624. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2625. " tid %d to_fw %d",
  2626. msdu_info->meta_data[0],
  2627. msdu_info->meta_data[1],
  2628. msdu_info->meta_data[2],
  2629. msdu_info->meta_data[3],
  2630. msdu_info->meta_data[4],
  2631. msdu_info->meta_data[5],
  2632. msdu_info->tid, msdu_info->exception_fw);
  2633. return nbuf;
  2634. }
  2635. #else
  2636. static
  2637. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2638. struct dp_tx_msdu_info_s *msdu_info)
  2639. {
  2640. return nbuf;
  2641. }
  2642. #endif
  2643. /**
  2644. * dp_check_exc_metadata() - Checks if parameters are valid
  2645. * @tx_exc: holds all exception path parameters
  2646. *
  2647. * Return: true when all the parameters are valid else false
  2648. *
  2649. */
  2650. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2651. {
  2652. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2653. HTT_INVALID_TID);
  2654. bool invalid_encap_type =
  2655. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2656. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2657. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2658. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2659. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2660. tx_exc->ppdu_cookie == 0);
  2661. if (tx_exc->is_intrabss_fwd)
  2662. return true;
  2663. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2664. invalid_cookie) {
  2665. return false;
  2666. }
  2667. return true;
  2668. }
  2669. #ifdef ATH_SUPPORT_IQUE
  2670. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2671. {
  2672. qdf_ether_header_t *eh;
  2673. /* Mcast to Ucast Conversion*/
  2674. if (qdf_likely(!vdev->mcast_enhancement_en))
  2675. return true;
  2676. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2677. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2678. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2679. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2680. qdf_nbuf_set_next(nbuf, NULL);
  2681. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2682. qdf_nbuf_len(nbuf));
  2683. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2684. QDF_STATUS_SUCCESS) {
  2685. return false;
  2686. }
  2687. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2688. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2689. QDF_STATUS_SUCCESS) {
  2690. return false;
  2691. }
  2692. }
  2693. }
  2694. return true;
  2695. }
  2696. #else
  2697. bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2698. {
  2699. return true;
  2700. }
  2701. #endif
  2702. #ifdef QCA_SUPPORT_WDS_EXTENDED
  2703. /**
  2704. * dp_tx_mcast_drop() - Drop mcast frame if drop_tx_mcast is set in WDS_EXT
  2705. * @vdev: vdev handle
  2706. * @nbuf: skb
  2707. *
  2708. * Return: true if frame is dropped, false otherwise
  2709. */
  2710. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2711. {
  2712. /* Drop tx mcast and WDS Extended feature check */
  2713. if (qdf_unlikely((vdev->drop_tx_mcast) && (vdev->wds_ext_enabled))) {
  2714. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2715. qdf_nbuf_data(nbuf);
  2716. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  2717. DP_STATS_INC(vdev, tx_i.dropped.tx_mcast_drop, 1);
  2718. return true;
  2719. }
  2720. }
  2721. return false;
  2722. }
  2723. #else
  2724. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2725. {
  2726. return false;
  2727. }
  2728. #endif
  2729. /**
  2730. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2731. * @nbuf: qdf_nbuf_t
  2732. * @vdev: struct dp_vdev *
  2733. *
  2734. * Allow packet for processing only if it is for peer client which is
  2735. * connected with same vap. Drop packet if client is connected to
  2736. * different vap.
  2737. *
  2738. * Return: QDF_STATUS
  2739. */
  2740. static inline QDF_STATUS
  2741. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2742. {
  2743. struct dp_ast_entry *dst_ast_entry = NULL;
  2744. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2745. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2746. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2747. return QDF_STATUS_SUCCESS;
  2748. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2749. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2750. eh->ether_dhost,
  2751. vdev->vdev_id);
  2752. /* If there is no ast entry, return failure */
  2753. if (qdf_unlikely(!dst_ast_entry)) {
  2754. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2755. return QDF_STATUS_E_FAILURE;
  2756. }
  2757. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2758. return QDF_STATUS_SUCCESS;
  2759. }
  2760. /**
  2761. * dp_tx_nawds_handler() - NAWDS handler
  2762. *
  2763. * @soc: DP soc handle
  2764. * @vdev: DP vdev handle
  2765. * @msdu_info: msdu_info required to create HTT metadata
  2766. * @nbuf: skb
  2767. * @sa_peer_id:
  2768. *
  2769. * This API transfers the multicast frames with the peer id
  2770. * on NAWDS enabled peer.
  2771. *
  2772. * Return: none
  2773. */
  2774. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2775. struct dp_tx_msdu_info_s *msdu_info,
  2776. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2777. {
  2778. struct dp_peer *peer = NULL;
  2779. qdf_nbuf_t nbuf_clone = NULL;
  2780. uint16_t peer_id = DP_INVALID_PEER;
  2781. struct dp_txrx_peer *txrx_peer;
  2782. uint8_t link_id = 0;
  2783. /* This check avoids pkt forwarding which is entered
  2784. * in the ast table but still doesn't have valid peerid.
  2785. */
  2786. if (sa_peer_id == HTT_INVALID_PEER)
  2787. return;
  2788. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2789. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2790. txrx_peer = dp_get_txrx_peer(peer);
  2791. if (!txrx_peer)
  2792. continue;
  2793. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2794. peer_id = peer->peer_id;
  2795. if (!dp_peer_is_primary_link_peer(peer))
  2796. continue;
  2797. /* In the case of wds ext peer mcast traffic will be
  2798. * sent as part of VLAN interface
  2799. */
  2800. if (dp_peer_is_wds_ext_peer(txrx_peer))
  2801. continue;
  2802. /* Multicast packets needs to be
  2803. * dropped in case of intra bss forwarding
  2804. */
  2805. if (sa_peer_id == txrx_peer->peer_id) {
  2806. dp_tx_debug("multicast packet");
  2807. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2808. tx.nawds_mcast_drop,
  2809. 1, link_id);
  2810. continue;
  2811. }
  2812. nbuf_clone = qdf_nbuf_clone(nbuf);
  2813. if (!nbuf_clone) {
  2814. QDF_TRACE(QDF_MODULE_ID_DP,
  2815. QDF_TRACE_LEVEL_ERROR,
  2816. FL("nbuf clone failed"));
  2817. break;
  2818. }
  2819. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2820. msdu_info, peer_id,
  2821. NULL);
  2822. if (nbuf_clone) {
  2823. dp_tx_debug("pkt send failed");
  2824. qdf_nbuf_free(nbuf_clone);
  2825. } else {
  2826. if (peer_id != DP_INVALID_PEER)
  2827. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2828. tx.nawds_mcast,
  2829. 1, qdf_nbuf_len(nbuf), link_id);
  2830. }
  2831. }
  2832. }
  2833. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2834. }
  2835. #ifdef WLAN_MCAST_MLO
  2836. static inline bool
  2837. dp_tx_check_mesh_vdev(struct dp_vdev *vdev,
  2838. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2839. {
  2840. if (!tx_exc_metadata->is_mlo_mcast && qdf_unlikely(vdev->mesh_vdev))
  2841. return true;
  2842. return false;
  2843. }
  2844. #else
  2845. static inline bool
  2846. dp_tx_check_mesh_vdev(struct dp_vdev *vdev,
  2847. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2848. {
  2849. if (qdf_unlikely(vdev->mesh_vdev))
  2850. return true;
  2851. return false;
  2852. }
  2853. #endif
  2854. qdf_nbuf_t
  2855. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2856. qdf_nbuf_t nbuf,
  2857. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2858. {
  2859. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2860. struct dp_tx_msdu_info_s msdu_info;
  2861. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2862. DP_MOD_ID_TX_EXCEPTION);
  2863. if (qdf_unlikely(!vdev))
  2864. goto fail;
  2865. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2866. if (!tx_exc_metadata)
  2867. goto fail;
  2868. msdu_info.tid = tx_exc_metadata->tid;
  2869. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2870. QDF_MAC_ADDR_REF(nbuf->data));
  2871. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2872. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2873. dp_tx_err("Invalid parameters in exception path");
  2874. goto fail;
  2875. }
  2876. /* for peer based metadata check if peer is valid */
  2877. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2878. struct dp_peer *peer = NULL;
  2879. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2880. tx_exc_metadata->peer_id,
  2881. DP_MOD_ID_TX_EXCEPTION);
  2882. if (qdf_unlikely(!peer)) {
  2883. DP_STATS_INC(vdev,
  2884. tx_i.dropped.invalid_peer_id_in_exc_path,
  2885. 1);
  2886. goto fail;
  2887. }
  2888. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2889. }
  2890. /* Basic sanity checks for unsupported packets */
  2891. /* MESH mode */
  2892. if (dp_tx_check_mesh_vdev(vdev, tx_exc_metadata)) {
  2893. dp_tx_err("Mesh mode is not supported in exception path");
  2894. goto fail;
  2895. }
  2896. /*
  2897. * Classify the frame and call corresponding
  2898. * "prepare" function which extracts the segment (TSO)
  2899. * and fragmentation information (for TSO , SG, ME, or Raw)
  2900. * into MSDU_INFO structure which is later used to fill
  2901. * SW and HW descriptors.
  2902. */
  2903. if (qdf_nbuf_is_tso(nbuf)) {
  2904. dp_verbose_debug("TSO frame %pK", vdev);
  2905. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2906. qdf_nbuf_len(nbuf));
  2907. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2908. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2909. qdf_nbuf_len(nbuf));
  2910. goto fail;
  2911. }
  2912. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  2913. goto send_multiple;
  2914. }
  2915. /* SG */
  2916. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2917. struct dp_tx_seg_info_s seg_info = {0};
  2918. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2919. if (!nbuf)
  2920. goto fail;
  2921. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2922. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2923. qdf_nbuf_len(nbuf));
  2924. goto send_multiple;
  2925. }
  2926. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2927. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2928. qdf_nbuf_len(nbuf));
  2929. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2930. tx_exc_metadata->ppdu_cookie);
  2931. }
  2932. /*
  2933. * Get HW Queue to use for this frame.
  2934. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2935. * dedicated for data and 1 for command.
  2936. * "queue_id" maps to one hardware ring.
  2937. * With each ring, we also associate a unique Tx descriptor pool
  2938. * to minimize lock contention for these resources.
  2939. */
  2940. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2941. /*
  2942. * if the packet is mcast packet send through mlo_macst handler
  2943. * for all prnt_vdevs
  2944. */
  2945. if (soc->arch_ops.dp_tx_mlo_mcast_send) {
  2946. nbuf = soc->arch_ops.dp_tx_mlo_mcast_send(soc, vdev,
  2947. nbuf,
  2948. tx_exc_metadata);
  2949. if (!nbuf)
  2950. goto fail;
  2951. }
  2952. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2953. if (qdf_unlikely(vdev->nawds_enabled)) {
  2954. /*
  2955. * This is a multicast packet
  2956. */
  2957. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2958. tx_exc_metadata->peer_id);
  2959. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2960. 1, qdf_nbuf_len(nbuf));
  2961. }
  2962. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2963. DP_INVALID_PEER, NULL);
  2964. } else {
  2965. /*
  2966. * Check exception descriptors
  2967. */
  2968. if (dp_tx_exception_limit_check(vdev))
  2969. goto fail;
  2970. /* Single linear frame */
  2971. /*
  2972. * If nbuf is a simple linear frame, use send_single function to
  2973. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2974. * SRNG. There is no need to setup a MSDU extension descriptor.
  2975. */
  2976. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2977. tx_exc_metadata->peer_id,
  2978. tx_exc_metadata);
  2979. }
  2980. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2981. return nbuf;
  2982. send_multiple:
  2983. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  2984. fail:
  2985. if (vdev)
  2986. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  2987. dp_verbose_debug("pkt send failed");
  2988. return nbuf;
  2989. }
  2990. qdf_nbuf_t
  2991. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  2992. uint8_t vdev_id, qdf_nbuf_t nbuf,
  2993. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2994. {
  2995. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2996. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2997. DP_MOD_ID_TX_EXCEPTION);
  2998. if (qdf_unlikely(!vdev))
  2999. goto fail;
  3000. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3001. == QDF_STATUS_E_FAILURE)) {
  3002. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3003. goto fail;
  3004. }
  3005. /* Unref count as it will again be taken inside dp_tx_exception */
  3006. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3007. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  3008. fail:
  3009. if (vdev)
  3010. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3011. dp_verbose_debug("pkt send failed");
  3012. return nbuf;
  3013. }
  3014. #ifdef MESH_MODE_SUPPORT
  3015. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3016. qdf_nbuf_t nbuf)
  3017. {
  3018. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3019. struct meta_hdr_s *mhdr;
  3020. qdf_nbuf_t nbuf_mesh = NULL;
  3021. qdf_nbuf_t nbuf_clone = NULL;
  3022. struct dp_vdev *vdev;
  3023. uint8_t no_enc_frame = 0;
  3024. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3025. if (!nbuf_mesh) {
  3026. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3027. "qdf_nbuf_unshare failed");
  3028. return nbuf;
  3029. }
  3030. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3031. if (!vdev) {
  3032. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3033. "vdev is NULL for vdev_id %d", vdev_id);
  3034. return nbuf;
  3035. }
  3036. nbuf = nbuf_mesh;
  3037. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3038. if ((vdev->sec_type != cdp_sec_type_none) &&
  3039. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3040. no_enc_frame = 1;
  3041. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3042. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3043. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3044. !no_enc_frame) {
  3045. nbuf_clone = qdf_nbuf_clone(nbuf);
  3046. if (!nbuf_clone) {
  3047. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3048. "qdf_nbuf_clone failed");
  3049. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3050. return nbuf;
  3051. }
  3052. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3053. }
  3054. if (nbuf_clone) {
  3055. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3056. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3057. } else {
  3058. qdf_nbuf_free(nbuf_clone);
  3059. }
  3060. }
  3061. if (no_enc_frame)
  3062. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3063. else
  3064. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3065. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3066. if ((!nbuf) && no_enc_frame) {
  3067. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3068. }
  3069. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3070. return nbuf;
  3071. }
  3072. #else
  3073. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3074. qdf_nbuf_t nbuf)
  3075. {
  3076. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3077. }
  3078. #endif
  3079. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3080. static inline
  3081. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3082. {
  3083. if (nbuf) {
  3084. qdf_prefetch(&nbuf->len);
  3085. qdf_prefetch(&nbuf->data);
  3086. }
  3087. }
  3088. #else
  3089. static inline
  3090. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3091. {
  3092. }
  3093. #endif
  3094. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3095. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3096. qdf_nbuf_t nbuf)
  3097. {
  3098. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3099. struct dp_vdev *vdev = NULL;
  3100. vdev = soc->vdev_id_map[vdev_id];
  3101. if (qdf_unlikely(!vdev))
  3102. return nbuf;
  3103. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3104. return nbuf;
  3105. }
  3106. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3107. qdf_nbuf_t nbuf,
  3108. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3109. {
  3110. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3111. }
  3112. #endif
  3113. #ifdef FEATURE_DIRECT_LINK
  3114. /**
  3115. * dp_vdev_tx_mark_to_fw() - Mark to_fw bit for the tx packet
  3116. * @nbuf: skb
  3117. * @vdev: DP vdev handle
  3118. *
  3119. * Return: None
  3120. */
  3121. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3122. {
  3123. if (qdf_unlikely(vdev->to_fw))
  3124. QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf) = 1;
  3125. }
  3126. #else
  3127. static inline void dp_vdev_tx_mark_to_fw(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  3128. {
  3129. }
  3130. #endif
  3131. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3132. qdf_nbuf_t nbuf)
  3133. {
  3134. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3135. uint16_t peer_id = HTT_INVALID_PEER;
  3136. /*
  3137. * doing a memzero is causing additional function call overhead
  3138. * so doing static stack clearing
  3139. */
  3140. struct dp_tx_msdu_info_s msdu_info = {0};
  3141. struct dp_vdev *vdev = NULL;
  3142. qdf_nbuf_t end_nbuf = NULL;
  3143. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3144. return nbuf;
  3145. /*
  3146. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3147. * this in per packet path.
  3148. *
  3149. * As in this path vdev memory is already protected with netdev
  3150. * tx lock
  3151. */
  3152. vdev = soc->vdev_id_map[vdev_id];
  3153. if (qdf_unlikely(!vdev))
  3154. return nbuf;
  3155. dp_vdev_tx_mark_to_fw(nbuf, vdev);
  3156. /*
  3157. * Set Default Host TID value to invalid TID
  3158. * (TID override disabled)
  3159. */
  3160. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3161. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  3162. if (qdf_unlikely(vdev->mesh_vdev)) {
  3163. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3164. &msdu_info);
  3165. if (!nbuf_mesh) {
  3166. dp_verbose_debug("Extracting mesh metadata failed");
  3167. return nbuf;
  3168. }
  3169. nbuf = nbuf_mesh;
  3170. }
  3171. /*
  3172. * Get HW Queue to use for this frame.
  3173. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3174. * dedicated for data and 1 for command.
  3175. * "queue_id" maps to one hardware ring.
  3176. * With each ring, we also associate a unique Tx descriptor pool
  3177. * to minimize lock contention for these resources.
  3178. */
  3179. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3180. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3181. 1);
  3182. /*
  3183. * TCL H/W supports 2 DSCP-TID mapping tables.
  3184. * Table 1 - Default DSCP-TID mapping table
  3185. * Table 2 - 1 DSCP-TID override table
  3186. *
  3187. * If we need a different DSCP-TID mapping for this vap,
  3188. * call tid_classify to extract DSCP/ToS from frame and
  3189. * map to a TID and store in msdu_info. This is later used
  3190. * to fill in TCL Input descriptor (per-packet TID override).
  3191. */
  3192. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3193. /*
  3194. * Classify the frame and call corresponding
  3195. * "prepare" function which extracts the segment (TSO)
  3196. * and fragmentation information (for TSO , SG, ME, or Raw)
  3197. * into MSDU_INFO structure which is later used to fill
  3198. * SW and HW descriptors.
  3199. */
  3200. if (qdf_nbuf_is_tso(nbuf)) {
  3201. dp_verbose_debug("TSO frame %pK", vdev);
  3202. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3203. qdf_nbuf_len(nbuf));
  3204. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3205. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3206. qdf_nbuf_len(nbuf));
  3207. return nbuf;
  3208. }
  3209. DP_STATS_INC(vdev, tx_i.rcvd.num, msdu_info.num_seg - 1);
  3210. goto send_multiple;
  3211. }
  3212. /* SG */
  3213. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3214. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3215. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3216. return nbuf;
  3217. } else {
  3218. struct dp_tx_seg_info_s seg_info = {0};
  3219. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3220. goto send_single;
  3221. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3222. &msdu_info);
  3223. if (!nbuf)
  3224. return NULL;
  3225. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3226. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3227. qdf_nbuf_len(nbuf));
  3228. goto send_multiple;
  3229. }
  3230. }
  3231. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3232. return NULL;
  3233. if (qdf_unlikely(dp_tx_mcast_drop(vdev, nbuf)))
  3234. return nbuf;
  3235. /* RAW */
  3236. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3237. struct dp_tx_seg_info_s seg_info = {0};
  3238. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3239. if (!nbuf)
  3240. return NULL;
  3241. dp_verbose_debug("Raw frame %pK", vdev);
  3242. goto send_multiple;
  3243. }
  3244. if (qdf_unlikely(vdev->nawds_enabled)) {
  3245. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3246. qdf_nbuf_data(nbuf);
  3247. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3248. uint16_t sa_peer_id = DP_INVALID_PEER;
  3249. if (!soc->ast_offload_support) {
  3250. struct dp_ast_entry *ast_entry = NULL;
  3251. qdf_spin_lock_bh(&soc->ast_lock);
  3252. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3253. (soc,
  3254. (uint8_t *)(eh->ether_shost),
  3255. vdev->pdev->pdev_id);
  3256. if (ast_entry)
  3257. sa_peer_id = ast_entry->peer_id;
  3258. qdf_spin_unlock_bh(&soc->ast_lock);
  3259. }
  3260. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3261. sa_peer_id);
  3262. }
  3263. peer_id = DP_INVALID_PEER;
  3264. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3265. 1, qdf_nbuf_len(nbuf));
  3266. }
  3267. send_single:
  3268. /* Single linear frame */
  3269. /*
  3270. * If nbuf is a simple linear frame, use send_single function to
  3271. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3272. * SRNG. There is no need to setup a MSDU extension descriptor.
  3273. */
  3274. dp_tx_prefetch_nbuf_data(nbuf);
  3275. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3276. peer_id, end_nbuf);
  3277. return nbuf;
  3278. send_multiple:
  3279. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3280. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3281. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3282. return nbuf;
  3283. }
  3284. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3285. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3286. {
  3287. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3288. struct dp_vdev *vdev = NULL;
  3289. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3290. return nbuf;
  3291. /*
  3292. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3293. * this in per packet path.
  3294. *
  3295. * As in this path vdev memory is already protected with netdev
  3296. * tx lock
  3297. */
  3298. vdev = soc->vdev_id_map[vdev_id];
  3299. if (qdf_unlikely(!vdev))
  3300. return nbuf;
  3301. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3302. == QDF_STATUS_E_FAILURE)) {
  3303. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3304. return nbuf;
  3305. }
  3306. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3307. }
  3308. #ifdef UMAC_SUPPORT_PROXY_ARP
  3309. /**
  3310. * dp_tx_proxy_arp() - Tx proxy arp handler
  3311. * @vdev: datapath vdev handle
  3312. * @nbuf: sk buffer
  3313. *
  3314. * Return: status
  3315. */
  3316. static inline
  3317. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3318. {
  3319. if (vdev->osif_proxy_arp)
  3320. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3321. /*
  3322. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3323. * osif_proxy_arp has a valid function pointer assigned
  3324. * to it
  3325. */
  3326. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3327. return QDF_STATUS_NOT_INITIALIZED;
  3328. }
  3329. #else
  3330. static inline
  3331. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3332. {
  3333. return QDF_STATUS_SUCCESS;
  3334. }
  3335. #endif
  3336. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  3337. !defined(CONFIG_MLO_SINGLE_DEV)
  3338. #ifdef WLAN_MCAST_MLO
  3339. static bool
  3340. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3341. struct dp_tx_desc_s *tx_desc,
  3342. qdf_nbuf_t nbuf,
  3343. uint8_t reinject_reason)
  3344. {
  3345. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3346. if (soc->arch_ops.dp_tx_mcast_handler)
  3347. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3348. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3349. return true;
  3350. }
  3351. return false;
  3352. }
  3353. #else /* WLAN_MCAST_MLO */
  3354. static inline bool
  3355. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3356. struct dp_tx_desc_s *tx_desc,
  3357. qdf_nbuf_t nbuf,
  3358. uint8_t reinject_reason)
  3359. {
  3360. return false;
  3361. }
  3362. #endif /* WLAN_MCAST_MLO */
  3363. #else
  3364. static inline bool
  3365. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3366. struct dp_tx_desc_s *tx_desc,
  3367. qdf_nbuf_t nbuf,
  3368. uint8_t reinject_reason)
  3369. {
  3370. return false;
  3371. }
  3372. #endif
  3373. void dp_tx_reinject_handler(struct dp_soc *soc,
  3374. struct dp_vdev *vdev,
  3375. struct dp_tx_desc_s *tx_desc,
  3376. uint8_t *status,
  3377. uint8_t reinject_reason)
  3378. {
  3379. struct dp_peer *peer = NULL;
  3380. uint32_t peer_id = HTT_INVALID_PEER;
  3381. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3382. qdf_nbuf_t nbuf_copy = NULL;
  3383. struct dp_tx_msdu_info_s msdu_info;
  3384. #ifdef WDS_VENDOR_EXTENSION
  3385. int is_mcast = 0, is_ucast = 0;
  3386. int num_peers_3addr = 0;
  3387. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3388. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3389. #endif
  3390. struct dp_txrx_peer *txrx_peer;
  3391. qdf_assert(vdev);
  3392. dp_tx_debug("Tx reinject path");
  3393. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3394. qdf_nbuf_len(tx_desc->nbuf));
  3395. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3396. return;
  3397. #ifdef WDS_VENDOR_EXTENSION
  3398. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3399. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3400. } else {
  3401. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3402. }
  3403. is_ucast = !is_mcast;
  3404. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3405. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3406. txrx_peer = dp_get_txrx_peer(peer);
  3407. if (!txrx_peer || txrx_peer->bss_peer)
  3408. continue;
  3409. /* Detect wds peers that use 3-addr framing for mcast.
  3410. * if there are any, the bss_peer is used to send the
  3411. * the mcast frame using 3-addr format. all wds enabled
  3412. * peers that use 4-addr framing for mcast frames will
  3413. * be duplicated and sent as 4-addr frames below.
  3414. */
  3415. if (!txrx_peer->wds_enabled ||
  3416. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3417. num_peers_3addr = 1;
  3418. break;
  3419. }
  3420. }
  3421. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3422. #endif
  3423. if (qdf_unlikely(vdev->mesh_vdev)) {
  3424. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3425. } else {
  3426. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3427. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3428. txrx_peer = dp_get_txrx_peer(peer);
  3429. if (!txrx_peer)
  3430. continue;
  3431. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3432. #ifdef WDS_VENDOR_EXTENSION
  3433. /*
  3434. * . if 3-addr STA, then send on BSS Peer
  3435. * . if Peer WDS enabled and accept 4-addr mcast,
  3436. * send mcast on that peer only
  3437. * . if Peer WDS enabled and accept 4-addr ucast,
  3438. * send ucast on that peer only
  3439. */
  3440. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3441. (txrx_peer->wds_enabled &&
  3442. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3443. (is_ucast &&
  3444. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3445. #else
  3446. (txrx_peer->bss_peer &&
  3447. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3448. #endif
  3449. peer_id = DP_INVALID_PEER;
  3450. nbuf_copy = qdf_nbuf_copy(nbuf);
  3451. if (!nbuf_copy) {
  3452. dp_tx_debug("nbuf copy failed");
  3453. break;
  3454. }
  3455. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3456. dp_tx_get_queue(vdev, nbuf,
  3457. &msdu_info.tx_queue);
  3458. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3459. nbuf_copy,
  3460. &msdu_info,
  3461. peer_id,
  3462. NULL);
  3463. if (nbuf_copy) {
  3464. dp_tx_debug("pkt send failed");
  3465. qdf_nbuf_free(nbuf_copy);
  3466. }
  3467. }
  3468. }
  3469. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3470. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3471. QDF_DMA_TO_DEVICE, nbuf->len);
  3472. qdf_nbuf_free(nbuf);
  3473. }
  3474. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3475. }
  3476. void dp_tx_inspect_handler(struct dp_soc *soc,
  3477. struct dp_vdev *vdev,
  3478. struct dp_tx_desc_s *tx_desc,
  3479. uint8_t *status)
  3480. {
  3481. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3482. "%s Tx inspect path",
  3483. __func__);
  3484. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3485. qdf_nbuf_len(tx_desc->nbuf));
  3486. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3487. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3488. }
  3489. #ifdef MESH_MODE_SUPPORT
  3490. /**
  3491. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3492. * in mesh meta header
  3493. * @tx_desc: software descriptor head pointer
  3494. * @ts: pointer to tx completion stats
  3495. * Return: none
  3496. */
  3497. static
  3498. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3499. struct hal_tx_completion_status *ts)
  3500. {
  3501. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3502. if (!tx_desc->msdu_ext_desc) {
  3503. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3504. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3505. "netbuf %pK offset %d",
  3506. netbuf, tx_desc->pkt_offset);
  3507. return;
  3508. }
  3509. }
  3510. }
  3511. #else
  3512. static
  3513. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3514. struct hal_tx_completion_status *ts)
  3515. {
  3516. }
  3517. #endif
  3518. #ifdef CONFIG_SAWF
  3519. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3520. struct dp_vdev *vdev,
  3521. struct dp_txrx_peer *txrx_peer,
  3522. struct dp_tx_desc_s *tx_desc,
  3523. struct hal_tx_completion_status *ts,
  3524. uint8_t tid)
  3525. {
  3526. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3527. ts, tid);
  3528. }
  3529. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3530. uint32_t nw_delay,
  3531. uint32_t sw_delay,
  3532. uint32_t hw_delay)
  3533. {
  3534. dp_peer_tid_delay_avg(tx_delay,
  3535. nw_delay,
  3536. sw_delay,
  3537. hw_delay);
  3538. }
  3539. #else
  3540. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3541. struct dp_vdev *vdev,
  3542. struct dp_txrx_peer *txrx_peer,
  3543. struct dp_tx_desc_s *tx_desc,
  3544. struct hal_tx_completion_status *ts,
  3545. uint8_t tid)
  3546. {
  3547. }
  3548. static inline void
  3549. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3550. uint32_t nw_delay, uint32_t sw_delay,
  3551. uint32_t hw_delay)
  3552. {
  3553. }
  3554. #endif
  3555. #ifdef QCA_PEER_EXT_STATS
  3556. #ifdef WLAN_CONFIG_TX_DELAY
  3557. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3558. struct dp_tx_desc_s *tx_desc,
  3559. struct hal_tx_completion_status *ts,
  3560. struct dp_vdev *vdev)
  3561. {
  3562. struct dp_soc *soc = vdev->pdev->soc;
  3563. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3564. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3565. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3566. if (!ts->valid)
  3567. return;
  3568. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3569. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3570. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3571. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3572. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3573. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3574. &fwhw_transmit_delay))
  3575. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3576. fwhw_transmit_delay);
  3577. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3578. fwhw_transmit_delay);
  3579. }
  3580. #else
  3581. /**
  3582. * dp_tx_compute_tid_delay() - Compute per TID delay
  3583. * @stats: Per TID delay stats
  3584. * @tx_desc: Software Tx descriptor
  3585. * @ts: Tx completion status
  3586. * @vdev: vdev
  3587. *
  3588. * Compute the software enqueue and hw enqueue delays and
  3589. * update the respective histograms
  3590. *
  3591. * Return: void
  3592. */
  3593. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3594. struct dp_tx_desc_s *tx_desc,
  3595. struct hal_tx_completion_status *ts,
  3596. struct dp_vdev *vdev)
  3597. {
  3598. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3599. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3600. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3601. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3602. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3603. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3604. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3605. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3606. timestamp_hw_enqueue);
  3607. /*
  3608. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3609. */
  3610. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3611. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3612. }
  3613. #endif
  3614. /**
  3615. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3616. * @txrx_peer: DP peer context
  3617. * @tx_desc: Tx software descriptor
  3618. * @ts: Tx completion status
  3619. * @ring_id: Rx CPU context ID/CPU_ID
  3620. *
  3621. * Update the peer extended stats. These are enhanced other
  3622. * delay stats per msdu level.
  3623. *
  3624. * Return: void
  3625. */
  3626. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3627. struct dp_tx_desc_s *tx_desc,
  3628. struct hal_tx_completion_status *ts,
  3629. uint8_t ring_id)
  3630. {
  3631. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3632. struct dp_soc *soc = NULL;
  3633. struct dp_peer_delay_stats *delay_stats = NULL;
  3634. uint8_t tid;
  3635. soc = pdev->soc;
  3636. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3637. return;
  3638. if (!txrx_peer->delay_stats)
  3639. return;
  3640. tid = ts->tid;
  3641. delay_stats = txrx_peer->delay_stats;
  3642. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3643. /*
  3644. * For non-TID packets use the TID 9
  3645. */
  3646. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3647. tid = CDP_MAX_DATA_TIDS - 1;
  3648. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3649. tx_desc, ts, txrx_peer->vdev);
  3650. }
  3651. #else
  3652. static inline
  3653. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3654. struct dp_tx_desc_s *tx_desc,
  3655. struct hal_tx_completion_status *ts,
  3656. uint8_t ring_id)
  3657. {
  3658. }
  3659. #endif
  3660. #ifdef WLAN_PEER_JITTER
  3661. /**
  3662. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3663. * @curr_delay: Current delay
  3664. * @prev_delay: Previous delay
  3665. * @avg_jitter: Average Jitter
  3666. * Return: Newly Computed Average Jitter
  3667. */
  3668. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3669. uint32_t prev_delay,
  3670. uint32_t avg_jitter)
  3671. {
  3672. uint32_t curr_jitter;
  3673. int32_t jitter_diff;
  3674. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3675. if (!avg_jitter)
  3676. return curr_jitter;
  3677. jitter_diff = curr_jitter - avg_jitter;
  3678. if (jitter_diff < 0)
  3679. avg_jitter = avg_jitter -
  3680. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3681. else
  3682. avg_jitter = avg_jitter +
  3683. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3684. return avg_jitter;
  3685. }
  3686. /**
  3687. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3688. * @curr_delay: Current delay
  3689. * @avg_delay: Average delay
  3690. * Return: Newly Computed Average Delay
  3691. */
  3692. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3693. uint32_t avg_delay)
  3694. {
  3695. int32_t delay_diff;
  3696. if (!avg_delay)
  3697. return curr_delay;
  3698. delay_diff = curr_delay - avg_delay;
  3699. if (delay_diff < 0)
  3700. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3701. DP_AVG_DELAY_WEIGHT_DENOM);
  3702. else
  3703. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3704. DP_AVG_DELAY_WEIGHT_DENOM);
  3705. return avg_delay;
  3706. }
  3707. #ifdef WLAN_CONFIG_TX_DELAY
  3708. /**
  3709. * dp_tx_compute_cur_delay() - get the current delay
  3710. * @soc: soc handle
  3711. * @vdev: vdev structure for data path state
  3712. * @ts: Tx completion status
  3713. * @curr_delay: current delay
  3714. * @tx_desc: tx descriptor
  3715. * Return: void
  3716. */
  3717. static
  3718. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3719. struct dp_vdev *vdev,
  3720. struct hal_tx_completion_status *ts,
  3721. uint32_t *curr_delay,
  3722. struct dp_tx_desc_s *tx_desc)
  3723. {
  3724. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3725. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3726. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3727. curr_delay);
  3728. return status;
  3729. }
  3730. #else
  3731. static
  3732. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3733. struct dp_vdev *vdev,
  3734. struct hal_tx_completion_status *ts,
  3735. uint32_t *curr_delay,
  3736. struct dp_tx_desc_s *tx_desc)
  3737. {
  3738. int64_t current_timestamp, timestamp_hw_enqueue;
  3739. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3740. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3741. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3742. return QDF_STATUS_SUCCESS;
  3743. }
  3744. #endif
  3745. /**
  3746. * dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3747. * @jitter: per tid per ring jitter stats
  3748. * @ts: Tx completion status
  3749. * @vdev: vdev structure for data path state
  3750. * @tx_desc: tx descriptor
  3751. * Return: void
  3752. */
  3753. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3754. struct hal_tx_completion_status *ts,
  3755. struct dp_vdev *vdev,
  3756. struct dp_tx_desc_s *tx_desc)
  3757. {
  3758. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3759. struct dp_soc *soc = vdev->pdev->soc;
  3760. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3761. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3762. jitter->tx_drop += 1;
  3763. return;
  3764. }
  3765. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3766. tx_desc);
  3767. if (QDF_IS_STATUS_SUCCESS(status)) {
  3768. avg_delay = jitter->tx_avg_delay;
  3769. avg_jitter = jitter->tx_avg_jitter;
  3770. prev_delay = jitter->tx_prev_delay;
  3771. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3772. prev_delay,
  3773. avg_jitter);
  3774. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3775. jitter->tx_avg_delay = avg_delay;
  3776. jitter->tx_avg_jitter = avg_jitter;
  3777. jitter->tx_prev_delay = curr_delay;
  3778. jitter->tx_total_success += 1;
  3779. } else if (status == QDF_STATUS_E_FAILURE) {
  3780. jitter->tx_avg_err += 1;
  3781. }
  3782. }
  3783. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3784. * @txrx_peer: DP peer context
  3785. * @tx_desc: Tx software descriptor
  3786. * @ts: Tx completion status
  3787. * @ring_id: Rx CPU context ID/CPU_ID
  3788. * Return: void
  3789. */
  3790. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3791. struct dp_tx_desc_s *tx_desc,
  3792. struct hal_tx_completion_status *ts,
  3793. uint8_t ring_id)
  3794. {
  3795. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3796. struct dp_soc *soc = pdev->soc;
  3797. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3798. uint8_t tid;
  3799. struct cdp_peer_tid_stats *rx_tid = NULL;
  3800. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3801. return;
  3802. tid = ts->tid;
  3803. jitter_stats = txrx_peer->jitter_stats;
  3804. qdf_assert_always(jitter_stats);
  3805. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3806. /*
  3807. * For non-TID packets use the TID 9
  3808. */
  3809. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3810. tid = CDP_MAX_DATA_TIDS - 1;
  3811. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3812. dp_tx_compute_tid_jitter(rx_tid,
  3813. ts, txrx_peer->vdev, tx_desc);
  3814. }
  3815. #else
  3816. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3817. struct dp_tx_desc_s *tx_desc,
  3818. struct hal_tx_completion_status *ts,
  3819. uint8_t ring_id)
  3820. {
  3821. }
  3822. #endif
  3823. #ifdef HW_TX_DELAY_STATS_ENABLE
  3824. /**
  3825. * dp_update_tx_delay_stats() - update the delay stats
  3826. * @vdev: vdev handle
  3827. * @delay: delay in ms or us based on the flag delay_in_us
  3828. * @tid: tid value
  3829. * @mode: type of tx delay mode
  3830. * @ring_id: ring number
  3831. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3832. *
  3833. * Return: none
  3834. */
  3835. static inline
  3836. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3837. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3838. {
  3839. struct cdp_tid_tx_stats *tstats =
  3840. &vdev->stats.tid_tx_stats[ring_id][tid];
  3841. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3842. delay_in_us);
  3843. }
  3844. #else
  3845. static inline
  3846. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3847. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3848. {
  3849. struct cdp_tid_tx_stats *tstats =
  3850. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3851. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3852. delay_in_us);
  3853. }
  3854. #endif
  3855. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3856. uint8_t tid, uint8_t ring_id)
  3857. {
  3858. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3859. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3860. uint32_t fwhw_transmit_delay_us;
  3861. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3862. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3863. return;
  3864. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3865. fwhw_transmit_delay_us =
  3866. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3867. qdf_ktime_to_us(tx_desc->timestamp);
  3868. /*
  3869. * Delay between packet enqueued to HW and Tx completion in us
  3870. */
  3871. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3872. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3873. ring_id, true);
  3874. /*
  3875. * For MCL, only enqueue to completion delay is required
  3876. * so return if the vdev flag is enabled.
  3877. */
  3878. return;
  3879. }
  3880. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3881. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3882. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3883. timestamp_hw_enqueue);
  3884. if (!timestamp_hw_enqueue)
  3885. return;
  3886. /*
  3887. * Delay between packet enqueued to HW and Tx completion in ms
  3888. */
  3889. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  3890. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  3891. false);
  3892. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3893. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3894. interframe_delay = (uint32_t)(timestamp_ingress -
  3895. vdev->prev_tx_enq_tstamp);
  3896. /*
  3897. * Delay in software enqueue
  3898. */
  3899. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  3900. CDP_DELAY_STATS_SW_ENQ, ring_id,
  3901. false);
  3902. /*
  3903. * Update interframe delay stats calculated at hardstart receive point.
  3904. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  3905. * interframe delay will not be calculate correctly for 1st frame.
  3906. * On the other side, this will help in avoiding extra per packet check
  3907. * of !vdev->prev_tx_enq_tstamp.
  3908. */
  3909. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  3910. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  3911. false);
  3912. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  3913. }
  3914. #ifdef DISABLE_DP_STATS
  3915. static
  3916. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  3917. struct dp_txrx_peer *txrx_peer,
  3918. uint8_t link_id)
  3919. {
  3920. }
  3921. #else
  3922. static inline void
  3923. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer,
  3924. uint8_t link_id)
  3925. {
  3926. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  3927. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  3928. if (subtype != QDF_PROTO_INVALID)
  3929. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  3930. 1, link_id);
  3931. }
  3932. #endif
  3933. #ifndef QCA_ENHANCED_STATS_SUPPORT
  3934. #ifdef DP_PEER_EXTENDED_API
  3935. static inline uint8_t
  3936. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3937. {
  3938. return txrx_peer->mpdu_retry_threshold;
  3939. }
  3940. #else
  3941. static inline uint8_t
  3942. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  3943. {
  3944. return 0;
  3945. }
  3946. #endif
  3947. /**
  3948. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  3949. *
  3950. * @ts: Tx compltion status
  3951. * @txrx_peer: datapath txrx_peer handle
  3952. * @link_id: Link id
  3953. *
  3954. * Return: void
  3955. */
  3956. static inline void
  3957. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3958. struct dp_txrx_peer *txrx_peer, uint8_t link_id)
  3959. {
  3960. uint8_t mcs, pkt_type, dst_mcs_idx;
  3961. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  3962. mcs = ts->mcs;
  3963. pkt_type = ts->pkt_type;
  3964. /* do HW to SW pkt type conversion */
  3965. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  3966. hal_2_dp_pkt_type_map[pkt_type]);
  3967. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  3968. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  3969. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3970. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  3971. 1, link_id);
  3972. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1, link_id);
  3973. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1, link_id);
  3974. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi,
  3975. link_id);
  3976. DP_PEER_EXTD_STATS_INC(txrx_peer,
  3977. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1,
  3978. link_id);
  3979. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc, link_id);
  3980. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc, link_id);
  3981. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1,
  3982. link_id);
  3983. if (ts->first_msdu) {
  3984. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  3985. ts->transmit_cnt > 1, link_id);
  3986. if (!retry_threshold)
  3987. return;
  3988. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  3989. qdf_do_div(ts->transmit_cnt,
  3990. retry_threshold),
  3991. ts->transmit_cnt > retry_threshold,
  3992. link_id);
  3993. }
  3994. }
  3995. #else
  3996. static inline void
  3997. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  3998. struct dp_txrx_peer *txrx_peer, uint8_t link_id)
  3999. {
  4000. }
  4001. #endif
  4002. #if defined(WLAN_FEATURE_11BE_MLO) && defined(QCA_ENHANCED_STATS_SUPPORT)
  4003. static inline uint8_t
  4004. dp_tx_get_link_id_from_ppdu_id(struct dp_soc *soc,
  4005. struct hal_tx_completion_status *ts,
  4006. struct dp_txrx_peer *txrx_peer,
  4007. struct dp_vdev *vdev)
  4008. {
  4009. uint8_t hw_link_id = 0;
  4010. uint32_t ppdu_id;
  4011. uint8_t link_id_offset, link_id_bits;
  4012. if (!txrx_peer->is_mld_peer || !vdev->pdev->link_peer_stats)
  4013. return 0;
  4014. link_id_offset = soc->link_id_offset;
  4015. link_id_bits = soc->link_id_bits;
  4016. ppdu_id = ts->ppdu_id;
  4017. hw_link_id = ((DP_GET_HW_LINK_ID_FRM_PPDU_ID(ppdu_id, link_id_offset,
  4018. link_id_bits)) + 1);
  4019. if (hw_link_id > DP_MAX_MLO_LINKS) {
  4020. hw_link_id = 0;
  4021. DP_PEER_PER_PKT_STATS_INC(
  4022. txrx_peer,
  4023. tx.inval_link_id_pkt_cnt, 1, hw_link_id);
  4024. }
  4025. return hw_link_id;
  4026. }
  4027. #else
  4028. static inline uint8_t
  4029. dp_tx_get_link_id_from_ppdu_id(struct dp_soc *soc,
  4030. struct hal_tx_completion_status *ts,
  4031. struct dp_txrx_peer *txrx_peer,
  4032. struct dp_vdev *vdev)
  4033. {
  4034. return 0;
  4035. }
  4036. #endif
  4037. /**
  4038. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4039. * per wbm ring
  4040. *
  4041. * @tx_desc: software descriptor head pointer
  4042. * @ts: Tx completion status
  4043. * @txrx_peer: peer handle
  4044. * @ring_id: ring number
  4045. * @link_id: Link id
  4046. *
  4047. * Return: None
  4048. */
  4049. static inline void
  4050. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4051. struct hal_tx_completion_status *ts,
  4052. struct dp_txrx_peer *txrx_peer, uint8_t ring_id,
  4053. uint8_t link_id)
  4054. {
  4055. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4056. uint8_t tid = ts->tid;
  4057. uint32_t length;
  4058. struct cdp_tid_tx_stats *tid_stats;
  4059. if (!pdev)
  4060. return;
  4061. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4062. tid = CDP_MAX_DATA_TIDS - 1;
  4063. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4064. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4065. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4066. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1,
  4067. link_id);
  4068. return;
  4069. }
  4070. length = qdf_nbuf_len(tx_desc->nbuf);
  4071. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4072. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4073. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4074. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4075. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4076. tid_stats->tqm_status_cnt[ts->status]++;
  4077. }
  4078. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4079. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4080. ts->transmit_cnt > 1, link_id);
  4081. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4082. 1, ts->transmit_cnt > 2, link_id);
  4083. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma,
  4084. link_id);
  4085. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4086. ts->msdu_part_of_amsdu, link_id);
  4087. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4088. !ts->msdu_part_of_amsdu, link_id);
  4089. txrx_peer->stats[link_id].per_pkt_stats.tx.last_tx_ts =
  4090. qdf_system_ticks();
  4091. dp_tx_update_peer_extd_stats(ts, txrx_peer, link_id);
  4092. return;
  4093. }
  4094. /*
  4095. * tx_failed is ideally supposed to be updated from HTT ppdu
  4096. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4097. * hw limitation there are no completions for failed cases.
  4098. * Hence updating tx_failed from data path. Please note that
  4099. * if tx_failed is fixed to be from ppdu, then this has to be
  4100. * removed
  4101. */
  4102. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4103. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4104. ts->transmit_cnt > DP_RETRY_COUNT,
  4105. link_id);
  4106. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer, link_id);
  4107. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4108. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1,
  4109. link_id);
  4110. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4111. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4112. length, link_id);
  4113. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4114. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1,
  4115. link_id);
  4116. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4117. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1,
  4118. link_id);
  4119. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4120. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1,
  4121. link_id);
  4122. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4123. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1,
  4124. link_id);
  4125. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4126. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1,
  4127. link_id);
  4128. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4129. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4130. tx.dropped.fw_rem_queue_disable, 1,
  4131. link_id);
  4132. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4133. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4134. tx.dropped.fw_rem_no_match, 1,
  4135. link_id);
  4136. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4137. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4138. tx.dropped.drop_threshold, 1,
  4139. link_id);
  4140. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4141. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4142. tx.dropped.drop_link_desc_na, 1,
  4143. link_id);
  4144. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4145. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4146. tx.dropped.invalid_drop, 1,
  4147. link_id);
  4148. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4149. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4150. tx.dropped.mcast_vdev_drop, 1,
  4151. link_id);
  4152. } else {
  4153. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1,
  4154. link_id);
  4155. }
  4156. }
  4157. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4158. /**
  4159. * dp_tx_flow_pool_lock() - take flow pool lock
  4160. * @soc: core txrx main context
  4161. * @tx_desc: tx desc
  4162. *
  4163. * Return: None
  4164. */
  4165. static inline
  4166. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4167. struct dp_tx_desc_s *tx_desc)
  4168. {
  4169. struct dp_tx_desc_pool_s *pool;
  4170. uint8_t desc_pool_id;
  4171. desc_pool_id = tx_desc->pool_id;
  4172. pool = &soc->tx_desc[desc_pool_id];
  4173. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4174. }
  4175. /**
  4176. * dp_tx_flow_pool_unlock() - release flow pool lock
  4177. * @soc: core txrx main context
  4178. * @tx_desc: tx desc
  4179. *
  4180. * Return: None
  4181. */
  4182. static inline
  4183. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4184. struct dp_tx_desc_s *tx_desc)
  4185. {
  4186. struct dp_tx_desc_pool_s *pool;
  4187. uint8_t desc_pool_id;
  4188. desc_pool_id = tx_desc->pool_id;
  4189. pool = &soc->tx_desc[desc_pool_id];
  4190. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4191. }
  4192. #else
  4193. static inline
  4194. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4195. {
  4196. }
  4197. static inline
  4198. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4199. {
  4200. }
  4201. #endif
  4202. /**
  4203. * dp_tx_notify_completion() - Notify tx completion for this desc
  4204. * @soc: core txrx main context
  4205. * @vdev: datapath vdev handle
  4206. * @tx_desc: tx desc
  4207. * @netbuf: buffer
  4208. * @status: tx status
  4209. *
  4210. * Return: none
  4211. */
  4212. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4213. struct dp_vdev *vdev,
  4214. struct dp_tx_desc_s *tx_desc,
  4215. qdf_nbuf_t netbuf,
  4216. uint8_t status)
  4217. {
  4218. void *osif_dev;
  4219. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4220. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4221. qdf_assert(tx_desc);
  4222. if (!vdev ||
  4223. !vdev->osif_vdev) {
  4224. return;
  4225. }
  4226. osif_dev = vdev->osif_vdev;
  4227. tx_compl_cbk = vdev->tx_comp;
  4228. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4229. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4230. if (tx_compl_cbk)
  4231. tx_compl_cbk(netbuf, osif_dev, flag);
  4232. }
  4233. /**
  4234. * dp_tx_sojourn_stats_process() - Collect sojourn stats
  4235. * @pdev: pdev handle
  4236. * @txrx_peer: DP peer context
  4237. * @tid: tid value
  4238. * @txdesc_ts: timestamp from txdesc
  4239. * @ppdu_id: ppdu id
  4240. * @link_id: link id
  4241. *
  4242. * Return: none
  4243. */
  4244. #ifdef FEATURE_PERPKT_INFO
  4245. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4246. struct dp_txrx_peer *txrx_peer,
  4247. uint8_t tid,
  4248. uint64_t txdesc_ts,
  4249. uint32_t ppdu_id,
  4250. uint8_t link_id)
  4251. {
  4252. uint64_t delta_ms;
  4253. struct cdp_tx_sojourn_stats *sojourn_stats;
  4254. struct dp_peer *primary_link_peer = NULL;
  4255. struct dp_soc *link_peer_soc = NULL;
  4256. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4257. return;
  4258. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4259. tid >= CDP_DATA_TID_MAX))
  4260. return;
  4261. if (qdf_unlikely(!pdev->sojourn_buf))
  4262. return;
  4263. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4264. txrx_peer->peer_id,
  4265. DP_MOD_ID_TX_COMP);
  4266. if (qdf_unlikely(!primary_link_peer))
  4267. return;
  4268. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4269. qdf_nbuf_data(pdev->sojourn_buf);
  4270. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4271. sojourn_stats->cookie = (void *)
  4272. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4273. primary_link_peer);
  4274. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4275. txdesc_ts;
  4276. qdf_ewma_tx_lag_add(&txrx_peer->stats[link_id].per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4277. delta_ms);
  4278. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4279. sojourn_stats->num_msdus[tid] = 1;
  4280. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4281. txrx_peer->stats[link_id].
  4282. per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4283. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4284. pdev->sojourn_buf, HTT_INVALID_PEER,
  4285. WDI_NO_VAL, pdev->pdev_id);
  4286. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4287. sojourn_stats->num_msdus[tid] = 0;
  4288. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4289. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4290. }
  4291. #else
  4292. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4293. struct dp_txrx_peer *txrx_peer,
  4294. uint8_t tid,
  4295. uint64_t txdesc_ts,
  4296. uint32_t ppdu_id)
  4297. {
  4298. }
  4299. #endif
  4300. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4301. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4302. struct dp_tx_desc_s *desc,
  4303. struct hal_tx_completion_status *ts)
  4304. {
  4305. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4306. desc, ts->peer_id,
  4307. WDI_NO_VAL, desc->pdev->pdev_id);
  4308. }
  4309. #endif
  4310. void
  4311. dp_tx_comp_process_desc(struct dp_soc *soc,
  4312. struct dp_tx_desc_s *desc,
  4313. struct hal_tx_completion_status *ts,
  4314. struct dp_txrx_peer *txrx_peer)
  4315. {
  4316. uint64_t time_latency = 0;
  4317. uint16_t peer_id = DP_INVALID_PEER_ID;
  4318. /*
  4319. * m_copy/tx_capture modes are not supported for
  4320. * scatter gather packets
  4321. */
  4322. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4323. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4324. qdf_ktime_to_ms(desc->timestamp));
  4325. }
  4326. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4327. if (dp_tx_pkt_tracepoints_enabled())
  4328. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4329. desc->msdu_ext_desc ?
  4330. desc->msdu_ext_desc->tso_desc : NULL,
  4331. qdf_ktime_to_ms(desc->timestamp));
  4332. if (!(desc->msdu_ext_desc)) {
  4333. dp_tx_enh_unmap(soc, desc);
  4334. if (txrx_peer)
  4335. peer_id = txrx_peer->peer_id;
  4336. if (QDF_STATUS_SUCCESS ==
  4337. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4338. return;
  4339. }
  4340. if (QDF_STATUS_SUCCESS ==
  4341. dp_get_completion_indication_for_stack(soc,
  4342. desc->pdev,
  4343. txrx_peer, ts,
  4344. desc->nbuf,
  4345. time_latency)) {
  4346. dp_send_completion_to_stack(soc,
  4347. desc->pdev,
  4348. ts->peer_id,
  4349. ts->ppdu_id,
  4350. desc->nbuf);
  4351. return;
  4352. }
  4353. }
  4354. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4355. dp_tx_comp_free_buf(soc, desc, false);
  4356. }
  4357. #ifdef DISABLE_DP_STATS
  4358. /**
  4359. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4360. * @soc: core txrx main context
  4361. * @vdev: virtual device instance
  4362. * @tx_desc: tx desc
  4363. * @status: tx status
  4364. *
  4365. * Return: none
  4366. */
  4367. static inline
  4368. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4369. struct dp_vdev *vdev,
  4370. struct dp_tx_desc_s *tx_desc,
  4371. uint8_t status)
  4372. {
  4373. }
  4374. #else
  4375. static inline
  4376. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4377. struct dp_vdev *vdev,
  4378. struct dp_tx_desc_s *tx_desc,
  4379. uint8_t status)
  4380. {
  4381. void *osif_dev;
  4382. ol_txrx_stats_rx_fp stats_cbk;
  4383. uint8_t pkt_type;
  4384. qdf_assert(tx_desc);
  4385. if (!vdev ||
  4386. !vdev->osif_vdev ||
  4387. !vdev->stats_cb)
  4388. return;
  4389. osif_dev = vdev->osif_vdev;
  4390. stats_cbk = vdev->stats_cb;
  4391. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4392. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4393. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4394. &pkt_type);
  4395. }
  4396. #endif
  4397. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4398. /* Mask for bit29 ~ bit31 */
  4399. #define DP_TX_TS_BIT29_31_MASK 0xE0000000
  4400. /* Timestamp value (unit us) if bit29 is set */
  4401. #define DP_TX_TS_BIT29_SET_VALUE BIT(29)
  4402. /**
  4403. * dp_tx_adjust_enqueue_buffer_ts() - adjust the enqueue buffer_timestamp
  4404. * @ack_ts: OTA ack timestamp, unit us.
  4405. * @enqueue_ts: TCL enqueue TX data to TQM timestamp, unit us.
  4406. * @base_delta_ts: base timestamp delta for ack_ts and enqueue_ts
  4407. *
  4408. * this function will restore the bit29 ~ bit31 3 bits value for
  4409. * buffer_timestamp in wbm2sw ring entry, currently buffer_timestamp only
  4410. * can support 0x7FFF * 1024 us (29 bits), but if the timestamp is >
  4411. * 0x7FFF * 1024 us, bit29~ bit31 will be lost.
  4412. *
  4413. * Return: the adjusted buffer_timestamp value
  4414. */
  4415. static inline
  4416. uint32_t dp_tx_adjust_enqueue_buffer_ts(uint32_t ack_ts,
  4417. uint32_t enqueue_ts,
  4418. uint32_t base_delta_ts)
  4419. {
  4420. uint32_t ack_buffer_ts;
  4421. uint32_t ack_buffer_ts_bit29_31;
  4422. uint32_t adjusted_enqueue_ts;
  4423. /* corresponding buffer_timestamp value when receive OTA Ack */
  4424. ack_buffer_ts = ack_ts - base_delta_ts;
  4425. ack_buffer_ts_bit29_31 = ack_buffer_ts & DP_TX_TS_BIT29_31_MASK;
  4426. /* restore the bit29 ~ bit31 value */
  4427. adjusted_enqueue_ts = ack_buffer_ts_bit29_31 | enqueue_ts;
  4428. /*
  4429. * if actual enqueue_ts value occupied 29 bits only, this enqueue_ts
  4430. * value + real UL delay overflow 29 bits, then 30th bit (bit-29)
  4431. * should not be marked, otherwise extra 0x20000000 us is added to
  4432. * enqueue_ts.
  4433. */
  4434. if (qdf_unlikely(adjusted_enqueue_ts > ack_buffer_ts))
  4435. adjusted_enqueue_ts -= DP_TX_TS_BIT29_SET_VALUE;
  4436. return adjusted_enqueue_ts;
  4437. }
  4438. QDF_STATUS
  4439. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4440. uint32_t delta_tsf,
  4441. uint32_t *delay_us)
  4442. {
  4443. uint32_t buffer_ts;
  4444. uint32_t delay;
  4445. if (!delay_us)
  4446. return QDF_STATUS_E_INVAL;
  4447. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4448. if (!ts->valid)
  4449. return QDF_STATUS_E_INVAL;
  4450. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4451. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4452. * valid up to 29 bits.
  4453. */
  4454. buffer_ts = ts->buffer_timestamp << 10;
  4455. buffer_ts = dp_tx_adjust_enqueue_buffer_ts(ts->tsf,
  4456. buffer_ts, delta_tsf);
  4457. delay = ts->tsf - buffer_ts - delta_tsf;
  4458. if (qdf_unlikely(delay & 0x80000000)) {
  4459. dp_err_rl("delay = 0x%x (-ve)\n"
  4460. "release_src = %d\n"
  4461. "ppdu_id = 0x%x\n"
  4462. "peer_id = 0x%x\n"
  4463. "tid = 0x%x\n"
  4464. "release_reason = %d\n"
  4465. "tsf = %u (0x%x)\n"
  4466. "buffer_timestamp = %u (0x%x)\n"
  4467. "delta_tsf = %u (0x%x)\n",
  4468. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4469. ts->tid, ts->status, ts->tsf, ts->tsf,
  4470. ts->buffer_timestamp, ts->buffer_timestamp,
  4471. delta_tsf, delta_tsf);
  4472. delay = 0;
  4473. goto end;
  4474. }
  4475. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4476. if (delay > 0x1000000) {
  4477. dp_info_rl("----------------------\n"
  4478. "Tx completion status:\n"
  4479. "----------------------\n"
  4480. "release_src = %d\n"
  4481. "ppdu_id = 0x%x\n"
  4482. "release_reason = %d\n"
  4483. "tsf = %u (0x%x)\n"
  4484. "buffer_timestamp = %u (0x%x)\n"
  4485. "delta_tsf = %u (0x%x)\n",
  4486. ts->release_src, ts->ppdu_id, ts->status,
  4487. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4488. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4489. return QDF_STATUS_E_FAILURE;
  4490. }
  4491. end:
  4492. *delay_us = delay;
  4493. return QDF_STATUS_SUCCESS;
  4494. }
  4495. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4496. uint32_t delta_tsf)
  4497. {
  4498. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4499. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4500. DP_MOD_ID_CDP);
  4501. if (!vdev) {
  4502. dp_err_rl("vdev %d does not exist", vdev_id);
  4503. return;
  4504. }
  4505. vdev->delta_tsf = delta_tsf;
  4506. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4507. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4508. }
  4509. #endif
  4510. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4511. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4512. uint8_t vdev_id, bool enable)
  4513. {
  4514. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4515. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4516. DP_MOD_ID_CDP);
  4517. if (!vdev) {
  4518. dp_err_rl("vdev %d does not exist", vdev_id);
  4519. return QDF_STATUS_E_FAILURE;
  4520. }
  4521. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4522. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4523. return QDF_STATUS_SUCCESS;
  4524. }
  4525. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4526. uint32_t *val)
  4527. {
  4528. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4529. struct dp_vdev *vdev;
  4530. uint32_t delay_accum;
  4531. uint32_t pkts_accum;
  4532. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4533. if (!vdev) {
  4534. dp_err_rl("vdev %d does not exist", vdev_id);
  4535. return QDF_STATUS_E_FAILURE;
  4536. }
  4537. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4538. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4539. return QDF_STATUS_E_FAILURE;
  4540. }
  4541. /* Average uplink delay based on current accumulated values */
  4542. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4543. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4544. *val = delay_accum / pkts_accum;
  4545. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4546. delay_accum, pkts_accum);
  4547. /* Reset accumulated values to 0 */
  4548. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4549. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4550. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4551. return QDF_STATUS_SUCCESS;
  4552. }
  4553. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4554. struct hal_tx_completion_status *ts)
  4555. {
  4556. uint32_t ul_delay;
  4557. if (qdf_unlikely(!vdev)) {
  4558. dp_info_rl("vdev is null or delete in progress");
  4559. return;
  4560. }
  4561. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4562. return;
  4563. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4564. vdev->delta_tsf,
  4565. &ul_delay)))
  4566. return;
  4567. ul_delay /= 1000; /* in unit of ms */
  4568. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4569. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4570. }
  4571. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4572. static inline
  4573. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4574. struct hal_tx_completion_status *ts)
  4575. {
  4576. }
  4577. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4578. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4579. struct dp_tx_desc_s *tx_desc,
  4580. struct hal_tx_completion_status *ts,
  4581. struct dp_txrx_peer *txrx_peer,
  4582. uint8_t ring_id)
  4583. {
  4584. uint32_t length;
  4585. qdf_ether_header_t *eh;
  4586. struct dp_vdev *vdev = NULL;
  4587. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4588. enum qdf_dp_tx_rx_status dp_status;
  4589. uint8_t link_id = 0;
  4590. if (!nbuf) {
  4591. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4592. goto out;
  4593. }
  4594. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4595. length = dp_tx_get_pkt_len(tx_desc);
  4596. dp_status = dp_tx_hw_to_qdf(ts->status);
  4597. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4598. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4599. QDF_TRACE_DEFAULT_PDEV_ID,
  4600. qdf_nbuf_data_addr(nbuf),
  4601. sizeof(qdf_nbuf_data(nbuf)),
  4602. tx_desc->id, ts->status, dp_status));
  4603. dp_tx_comp_debug("-------------------- \n"
  4604. "Tx Completion Stats: \n"
  4605. "-------------------- \n"
  4606. "ack_frame_rssi = %d \n"
  4607. "first_msdu = %d \n"
  4608. "last_msdu = %d \n"
  4609. "msdu_part_of_amsdu = %d \n"
  4610. "rate_stats valid = %d \n"
  4611. "bw = %d \n"
  4612. "pkt_type = %d \n"
  4613. "stbc = %d \n"
  4614. "ldpc = %d \n"
  4615. "sgi = %d \n"
  4616. "mcs = %d \n"
  4617. "ofdma = %d \n"
  4618. "tones_in_ru = %d \n"
  4619. "tsf = %d \n"
  4620. "ppdu_id = %d \n"
  4621. "transmit_cnt = %d \n"
  4622. "tid = %d \n"
  4623. "peer_id = %d\n"
  4624. "tx_status = %d\n",
  4625. ts->ack_frame_rssi, ts->first_msdu,
  4626. ts->last_msdu, ts->msdu_part_of_amsdu,
  4627. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4628. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4629. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4630. ts->transmit_cnt, ts->tid, ts->peer_id,
  4631. ts->status);
  4632. /* Update SoC level stats */
  4633. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4634. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4635. if (!txrx_peer) {
  4636. dp_info_rl("peer is null or deletion in progress");
  4637. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4638. goto out;
  4639. }
  4640. vdev = txrx_peer->vdev;
  4641. link_id = dp_tx_get_link_id_from_ppdu_id(soc, ts, txrx_peer, vdev);
  4642. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4643. dp_tx_update_uplink_delay(soc, vdev, ts);
  4644. /* check tx complete notification */
  4645. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4646. dp_tx_notify_completion(soc, vdev, tx_desc,
  4647. nbuf, ts->status);
  4648. /* Update per-packet stats for mesh mode */
  4649. if (qdf_unlikely(vdev->mesh_vdev) &&
  4650. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4651. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4652. /* Update peer level stats */
  4653. if (qdf_unlikely(txrx_peer->bss_peer &&
  4654. vdev->opmode == wlan_op_mode_ap)) {
  4655. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4656. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4657. length, link_id);
  4658. if (txrx_peer->vdev->tx_encap_type ==
  4659. htt_cmn_pkt_type_ethernet &&
  4660. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4661. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4662. tx.bcast, 1,
  4663. length, link_id);
  4664. }
  4665. }
  4666. } else {
  4667. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length,
  4668. link_id);
  4669. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4670. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4671. 1, length, link_id);
  4672. if (qdf_unlikely(txrx_peer->in_twt)) {
  4673. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4674. tx.tx_success_twt,
  4675. 1, length,
  4676. link_id);
  4677. }
  4678. }
  4679. }
  4680. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id, link_id);
  4681. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4682. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4683. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4684. ts, ts->tid);
  4685. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4686. #ifdef QCA_SUPPORT_RDK_STATS
  4687. if (soc->peerstats_enabled)
  4688. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4689. qdf_ktime_to_ms(tx_desc->timestamp),
  4690. ts->ppdu_id, link_id);
  4691. #endif
  4692. out:
  4693. return;
  4694. }
  4695. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4696. defined(QCA_ENHANCED_STATS_SUPPORT)
  4697. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4698. uint32_t length, uint8_t tx_status,
  4699. bool update)
  4700. {
  4701. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4702. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4703. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4704. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4705. }
  4706. }
  4707. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4708. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4709. uint32_t length, uint8_t tx_status,
  4710. bool update)
  4711. {
  4712. if (!txrx_peer->hw_txrx_stats_en) {
  4713. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4714. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4715. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4716. }
  4717. }
  4718. #else
  4719. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4720. uint32_t length, uint8_t tx_status,
  4721. bool update)
  4722. {
  4723. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4724. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4725. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4726. }
  4727. #endif
  4728. /**
  4729. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4730. * @next: descriptor of the nrxt buffer
  4731. *
  4732. * Return: none
  4733. */
  4734. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4735. static inline
  4736. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4737. {
  4738. qdf_nbuf_t nbuf = NULL;
  4739. if (next)
  4740. nbuf = next->nbuf;
  4741. if (nbuf)
  4742. qdf_prefetch(nbuf);
  4743. }
  4744. #else
  4745. static inline
  4746. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4747. {
  4748. }
  4749. #endif
  4750. /**
  4751. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4752. * @soc: core txrx main context
  4753. * @desc: software descriptor
  4754. *
  4755. * Return: true when packet is reinjected
  4756. */
  4757. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4758. defined(WLAN_MCAST_MLO) && !defined(CONFIG_MLO_SINGLE_DEV)
  4759. static inline bool
  4760. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4761. {
  4762. struct dp_vdev *vdev = NULL;
  4763. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4764. if (!soc->arch_ops.dp_tx_mcast_handler ||
  4765. !soc->arch_ops.dp_tx_is_mcast_primary)
  4766. return false;
  4767. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4768. DP_MOD_ID_REINJECT);
  4769. if (qdf_unlikely(!vdev)) {
  4770. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4771. desc->id);
  4772. return false;
  4773. }
  4774. if (!(soc->arch_ops.dp_tx_is_mcast_primary(soc, vdev))) {
  4775. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4776. return false;
  4777. }
  4778. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4779. qdf_nbuf_len(desc->nbuf));
  4780. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4781. dp_tx_desc_release(desc, desc->pool_id);
  4782. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4783. return true;
  4784. }
  4785. return false;
  4786. }
  4787. #else
  4788. static inline bool
  4789. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4790. {
  4791. return false;
  4792. }
  4793. #endif
  4794. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  4795. static inline void
  4796. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4797. {
  4798. qdf_nbuf_queue_head_init(nbuf_queue_head);
  4799. }
  4800. static inline void
  4801. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4802. struct dp_tx_desc_s *desc)
  4803. {
  4804. qdf_nbuf_t nbuf = NULL;
  4805. nbuf = desc->nbuf;
  4806. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_FAST))
  4807. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4808. else
  4809. qdf_nbuf_free(nbuf);
  4810. }
  4811. static inline void
  4812. dp_tx_nbuf_dev_queue_free_no_flag(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4813. qdf_nbuf_t nbuf)
  4814. {
  4815. if (!nbuf)
  4816. return;
  4817. if (nbuf->is_from_recycler)
  4818. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4819. else
  4820. qdf_nbuf_free(nbuf);
  4821. }
  4822. static inline void
  4823. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4824. {
  4825. qdf_nbuf_dev_kfree_list(nbuf_queue_head);
  4826. }
  4827. #else
  4828. static inline void
  4829. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4830. {
  4831. }
  4832. static inline void
  4833. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4834. struct dp_tx_desc_s *desc)
  4835. {
  4836. qdf_nbuf_free(desc->nbuf);
  4837. }
  4838. static inline void
  4839. dp_tx_nbuf_dev_queue_free_no_flag(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4840. qdf_nbuf_t nbuf)
  4841. {
  4842. qdf_nbuf_free(nbuf);
  4843. }
  4844. static inline void
  4845. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4846. {
  4847. }
  4848. #endif
  4849. #ifdef WLAN_SUPPORT_PPEDS
  4850. static inline void
  4851. dp_tx_update_ppeds_tx_comp_stats(struct dp_soc *soc,
  4852. struct dp_txrx_peer *txrx_peer,
  4853. struct hal_tx_completion_status *ts,
  4854. struct dp_tx_desc_s *desc,
  4855. uint8_t ring_id)
  4856. {
  4857. uint8_t link_id = 0;
  4858. struct dp_vdev *vdev = NULL;
  4859. if (qdf_likely(txrx_peer)) {
  4860. dp_tx_update_peer_basic_stats(txrx_peer,
  4861. desc->length,
  4862. desc->tx_status,
  4863. false);
  4864. if (!(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4865. hal_tx_comp_get_status(&desc->comp,
  4866. ts,
  4867. soc->hal_soc);
  4868. vdev = txrx_peer->vdev;
  4869. link_id = dp_tx_get_link_id_from_ppdu_id(soc,
  4870. ts,
  4871. txrx_peer,
  4872. vdev);
  4873. if (link_id < 1 || link_id > DP_MAX_MLO_LINKS)
  4874. link_id = 0;
  4875. dp_tx_update_peer_stats(desc, ts,
  4876. txrx_peer,
  4877. ring_id,
  4878. link_id);
  4879. }
  4880. }
  4881. }
  4882. #else
  4883. static inline void
  4884. dp_tx_update_ppeds_tx_comp_stats(struct dp_soc *soc,
  4885. struct dp_txrx_peer *txrx_peer,
  4886. struct hal_tx_completion_status *ts,
  4887. struct dp_tx_desc_s *desc,
  4888. uint8_t ring_id)
  4889. {
  4890. }
  4891. #endif
  4892. void
  4893. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4894. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4895. {
  4896. struct dp_tx_desc_s *desc;
  4897. struct dp_tx_desc_s *next;
  4898. struct hal_tx_completion_status ts;
  4899. struct dp_txrx_peer *txrx_peer = NULL;
  4900. uint16_t peer_id = DP_INVALID_PEER;
  4901. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4902. qdf_nbuf_queue_head_t h;
  4903. desc = comp_head;
  4904. dp_tx_nbuf_queue_head_init(&h);
  4905. while (desc) {
  4906. next = desc->next;
  4907. dp_tx_prefetch_next_nbuf_data(next);
  4908. if (peer_id != desc->peer_id) {
  4909. if (txrx_peer)
  4910. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4911. DP_MOD_ID_TX_COMP);
  4912. peer_id = desc->peer_id;
  4913. txrx_peer =
  4914. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4915. &txrx_ref_handle,
  4916. DP_MOD_ID_TX_COMP);
  4917. }
  4918. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4919. desc = next;
  4920. continue;
  4921. }
  4922. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4923. qdf_nbuf_t nbuf;
  4924. dp_tx_update_ppeds_tx_comp_stats(soc, txrx_peer, &ts,
  4925. desc, ring_id);
  4926. if (desc->pool_id != DP_TX_PPEDS_POOL_ID) {
  4927. nbuf = desc->nbuf;
  4928. dp_tx_nbuf_dev_queue_free_no_flag(&h, nbuf);
  4929. dp_tx_desc_free(soc, desc, desc->pool_id);
  4930. } else {
  4931. nbuf = dp_ppeds_tx_desc_free(soc, desc);
  4932. dp_tx_nbuf_dev_queue_free_no_flag(&h, nbuf);
  4933. }
  4934. desc = next;
  4935. continue;
  4936. }
  4937. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4938. struct dp_pdev *pdev = desc->pdev;
  4939. if (qdf_likely(txrx_peer))
  4940. dp_tx_update_peer_basic_stats(txrx_peer,
  4941. desc->length,
  4942. desc->tx_status,
  4943. false);
  4944. qdf_assert(pdev);
  4945. dp_tx_outstanding_dec(pdev);
  4946. /*
  4947. * Calling a QDF WRAPPER here is creating significant
  4948. * performance impact so avoided the wrapper call here
  4949. */
  4950. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4951. desc->id, DP_TX_COMP_UNMAP);
  4952. dp_tx_nbuf_unmap(soc, desc);
  4953. dp_tx_nbuf_dev_queue_free(&h, desc);
  4954. dp_tx_desc_free(soc, desc, desc->pool_id);
  4955. desc = next;
  4956. continue;
  4957. }
  4958. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4959. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4960. ring_id);
  4961. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4962. dp_tx_desc_release(desc, desc->pool_id);
  4963. desc = next;
  4964. }
  4965. dp_tx_nbuf_dev_kfree_list(&h);
  4966. if (txrx_peer)
  4967. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4968. }
  4969. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  4970. static inline
  4971. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4972. int max_reap_limit)
  4973. {
  4974. bool limit_hit = false;
  4975. limit_hit =
  4976. (num_reaped >= max_reap_limit) ? true : false;
  4977. if (limit_hit)
  4978. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  4979. return limit_hit;
  4980. }
  4981. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4982. {
  4983. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  4984. }
  4985. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  4986. {
  4987. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  4988. return cfg->tx_comp_loop_pkt_limit;
  4989. }
  4990. #else
  4991. static inline
  4992. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  4993. int max_reap_limit)
  4994. {
  4995. return false;
  4996. }
  4997. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  4998. {
  4999. return false;
  5000. }
  5001. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5002. {
  5003. return 0;
  5004. }
  5005. #endif
  5006. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  5007. static inline int
  5008. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5009. int *max_reap_limit)
  5010. {
  5011. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  5012. max_reap_limit);
  5013. }
  5014. #else
  5015. static inline int
  5016. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5017. int *max_reap_limit)
  5018. {
  5019. return 0;
  5020. }
  5021. #endif
  5022. #ifdef DP_TX_TRACKING
  5023. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  5024. {
  5025. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  5026. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  5027. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  5028. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  5029. }
  5030. }
  5031. #endif
  5032. #ifndef WLAN_SOFTUMAC_SUPPORT
  5033. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  5034. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  5035. uint32_t quota)
  5036. {
  5037. void *tx_comp_hal_desc;
  5038. void *last_prefetched_hw_desc = NULL;
  5039. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  5040. hal_soc_handle_t hal_soc;
  5041. uint8_t buffer_src;
  5042. struct dp_tx_desc_s *tx_desc = NULL;
  5043. struct dp_tx_desc_s *head_desc = NULL;
  5044. struct dp_tx_desc_s *tail_desc = NULL;
  5045. uint32_t num_processed = 0;
  5046. uint32_t count;
  5047. uint32_t num_avail_for_reap = 0;
  5048. bool force_break = false;
  5049. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  5050. int max_reap_limit, ring_near_full;
  5051. uint32_t num_entries;
  5052. DP_HIST_INIT();
  5053. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  5054. more_data:
  5055. hal_soc = soc->hal_soc;
  5056. /* Re-initialize local variables to be re-used */
  5057. head_desc = NULL;
  5058. tail_desc = NULL;
  5059. count = 0;
  5060. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  5061. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  5062. &max_reap_limit);
  5063. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  5064. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  5065. return 0;
  5066. }
  5067. if (!num_avail_for_reap)
  5068. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  5069. hal_ring_hdl, 0);
  5070. if (num_avail_for_reap >= quota)
  5071. num_avail_for_reap = quota;
  5072. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  5073. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  5074. hal_ring_hdl,
  5075. num_avail_for_reap);
  5076. /* Find head descriptor from completion ring */
  5077. while (qdf_likely(num_avail_for_reap--)) {
  5078. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  5079. if (qdf_unlikely(!tx_comp_hal_desc))
  5080. break;
  5081. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  5082. tx_comp_hal_desc);
  5083. /* If this buffer was not released by TQM or FW, then it is not
  5084. * Tx completion indication, assert */
  5085. if (qdf_unlikely(buffer_src !=
  5086. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  5087. (qdf_unlikely(buffer_src !=
  5088. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  5089. uint8_t wbm_internal_error;
  5090. dp_err_rl(
  5091. "Tx comp release_src != TQM | FW but from %d",
  5092. buffer_src);
  5093. hal_dump_comp_desc(tx_comp_hal_desc);
  5094. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  5095. /* When WBM sees NULL buffer_addr_info in any of
  5096. * ingress rings it sends an error indication,
  5097. * with wbm_internal_error=1, to a specific ring.
  5098. * The WBM2SW ring used to indicate these errors is
  5099. * fixed in HW, and that ring is being used as Tx
  5100. * completion ring. These errors are not related to
  5101. * Tx completions, and should just be ignored
  5102. */
  5103. wbm_internal_error = hal_get_wbm_internal_error(
  5104. hal_soc,
  5105. tx_comp_hal_desc);
  5106. if (wbm_internal_error) {
  5107. dp_err_rl("Tx comp wbm_internal_error!!");
  5108. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  5109. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  5110. buffer_src)
  5111. dp_handle_wbm_internal_error(
  5112. soc,
  5113. tx_comp_hal_desc,
  5114. hal_tx_comp_get_buffer_type(
  5115. tx_comp_hal_desc));
  5116. } else {
  5117. dp_err_rl("Tx comp wbm_internal_error false");
  5118. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  5119. }
  5120. continue;
  5121. }
  5122. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  5123. tx_comp_hal_desc,
  5124. &tx_desc);
  5125. if (qdf_unlikely(!tx_desc)) {
  5126. dp_err("unable to retrieve tx_desc!");
  5127. hal_dump_comp_desc(tx_comp_hal_desc);
  5128. DP_STATS_INC(soc, tx.invalid_tx_comp_desc, 1);
  5129. QDF_BUG(0);
  5130. continue;
  5131. }
  5132. tx_desc->buffer_src = buffer_src;
  5133. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5134. goto add_to_pool2;
  5135. /*
  5136. * If the release source is FW, process the HTT status
  5137. */
  5138. if (qdf_unlikely(buffer_src ==
  5139. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5140. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5141. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5142. htt_tx_status);
  5143. /* Collect hw completion contents */
  5144. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5145. &tx_desc->comp, 1);
  5146. soc->arch_ops.dp_tx_process_htt_completion(
  5147. soc,
  5148. tx_desc,
  5149. htt_tx_status,
  5150. ring_id);
  5151. } else {
  5152. tx_desc->tx_status =
  5153. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5154. tx_desc->buffer_src = buffer_src;
  5155. /*
  5156. * If the fast completion mode is enabled extended
  5157. * metadata from descriptor is not copied
  5158. */
  5159. if (qdf_likely(tx_desc->flags &
  5160. DP_TX_DESC_FLAG_SIMPLE))
  5161. goto add_to_pool;
  5162. /*
  5163. * If the descriptor is already freed in vdev_detach,
  5164. * continue to next descriptor
  5165. */
  5166. if (qdf_unlikely
  5167. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5168. !tx_desc->flags)) {
  5169. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5170. tx_desc->id);
  5171. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5172. dp_tx_desc_check_corruption(tx_desc);
  5173. continue;
  5174. }
  5175. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5176. dp_tx_comp_info_rl("pdev in down state %d",
  5177. tx_desc->id);
  5178. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5179. dp_tx_comp_free_buf(soc, tx_desc, false);
  5180. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5181. goto next_desc;
  5182. }
  5183. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5184. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5185. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5186. tx_desc->flags, tx_desc->id);
  5187. qdf_assert_always(0);
  5188. }
  5189. /* Collect hw completion contents */
  5190. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5191. &tx_desc->comp, 1);
  5192. add_to_pool:
  5193. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5194. add_to_pool2:
  5195. /* First ring descriptor on the cycle */
  5196. if (!head_desc) {
  5197. head_desc = tx_desc;
  5198. tail_desc = tx_desc;
  5199. }
  5200. tail_desc->next = tx_desc;
  5201. tx_desc->next = NULL;
  5202. tail_desc = tx_desc;
  5203. }
  5204. next_desc:
  5205. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5206. /*
  5207. * Processed packet count is more than given quota
  5208. * stop to processing
  5209. */
  5210. count++;
  5211. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5212. num_avail_for_reap,
  5213. hal_ring_hdl,
  5214. &last_prefetched_hw_desc,
  5215. &last_prefetched_sw_desc);
  5216. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5217. break;
  5218. }
  5219. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5220. /* Process the reaped descriptors */
  5221. if (head_desc)
  5222. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5223. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5224. /*
  5225. * If we are processing in near-full condition, there are 3 scenario
  5226. * 1) Ring entries has reached critical state
  5227. * 2) Ring entries are still near high threshold
  5228. * 3) Ring entries are below the safe level
  5229. *
  5230. * One more loop will move the state to normal processing and yield
  5231. */
  5232. if (ring_near_full)
  5233. goto more_data;
  5234. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5235. if (num_processed >= quota)
  5236. force_break = true;
  5237. if (!force_break &&
  5238. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5239. hal_ring_hdl)) {
  5240. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5241. if (!hif_exec_should_yield(soc->hif_handle,
  5242. int_ctx->dp_intr_id))
  5243. goto more_data;
  5244. num_avail_for_reap =
  5245. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5246. hal_ring_hdl,
  5247. true);
  5248. if (qdf_unlikely(num_entries &&
  5249. (num_avail_for_reap >=
  5250. num_entries >> 1))) {
  5251. DP_STATS_INC(soc, tx.near_full, 1);
  5252. goto more_data;
  5253. }
  5254. }
  5255. }
  5256. DP_TX_HIST_STATS_PER_PDEV();
  5257. return num_processed;
  5258. }
  5259. #endif
  5260. #ifdef FEATURE_WLAN_TDLS
  5261. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5262. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5263. {
  5264. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5265. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5266. DP_MOD_ID_TDLS);
  5267. if (!vdev) {
  5268. dp_err("vdev handle for id %d is NULL", vdev_id);
  5269. return NULL;
  5270. }
  5271. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5272. vdev->is_tdls_frame = true;
  5273. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5274. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5275. }
  5276. #endif
  5277. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5278. {
  5279. int pdev_id;
  5280. /*
  5281. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5282. */
  5283. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5284. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5285. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5286. vdev->vdev_id);
  5287. pdev_id =
  5288. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5289. vdev->pdev->pdev_id);
  5290. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5291. /*
  5292. * Set HTT Extension Valid bit to 0 by default
  5293. */
  5294. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5295. dp_tx_vdev_update_search_flags(vdev);
  5296. return QDF_STATUS_SUCCESS;
  5297. }
  5298. #ifndef FEATURE_WDS
  5299. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5300. {
  5301. return false;
  5302. }
  5303. #endif
  5304. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5305. {
  5306. struct dp_soc *soc = vdev->pdev->soc;
  5307. /*
  5308. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5309. * for TDLS link
  5310. *
  5311. * Enable AddrY (SA based search) only for non-WDS STA and
  5312. * ProxySTA VAP (in HKv1) modes.
  5313. *
  5314. * In all other VAP modes, only DA based search should be
  5315. * enabled
  5316. */
  5317. if (vdev->opmode == wlan_op_mode_sta &&
  5318. vdev->tdls_link_connected)
  5319. vdev->hal_desc_addr_search_flags =
  5320. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5321. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5322. !dp_tx_da_search_override(vdev))
  5323. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5324. else
  5325. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5326. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5327. vdev->search_type = soc->sta_mode_search_policy;
  5328. else
  5329. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5330. }
  5331. static inline bool
  5332. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5333. struct dp_vdev *vdev,
  5334. struct dp_tx_desc_s *tx_desc)
  5335. {
  5336. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5337. return false;
  5338. /*
  5339. * if vdev is given, then only check whether desc
  5340. * vdev match. if vdev is NULL, then check whether
  5341. * desc pdev match.
  5342. */
  5343. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5344. (tx_desc->pdev == pdev);
  5345. }
  5346. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5347. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5348. bool force_free)
  5349. {
  5350. uint8_t i;
  5351. uint32_t j;
  5352. uint32_t num_desc, page_id, offset;
  5353. uint16_t num_desc_per_page;
  5354. struct dp_soc *soc = pdev->soc;
  5355. struct dp_tx_desc_s *tx_desc = NULL;
  5356. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5357. if (!vdev && !force_free) {
  5358. dp_err("Reset TX desc vdev, Vdev param is required!");
  5359. return;
  5360. }
  5361. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5362. tx_desc_pool = &soc->tx_desc[i];
  5363. if (!(tx_desc_pool->pool_size) ||
  5364. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5365. !(tx_desc_pool->desc_pages.cacheable_pages))
  5366. continue;
  5367. /*
  5368. * Add flow pool lock protection in case pool is freed
  5369. * due to all tx_desc is recycled when handle TX completion.
  5370. * this is not necessary when do force flush as:
  5371. * a. double lock will happen if dp_tx_desc_release is
  5372. * also trying to acquire it.
  5373. * b. dp interrupt has been disabled before do force TX desc
  5374. * flush in dp_pdev_deinit().
  5375. */
  5376. if (!force_free)
  5377. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5378. num_desc = tx_desc_pool->pool_size;
  5379. num_desc_per_page =
  5380. tx_desc_pool->desc_pages.num_element_per_page;
  5381. for (j = 0; j < num_desc; j++) {
  5382. page_id = j / num_desc_per_page;
  5383. offset = j % num_desc_per_page;
  5384. if (qdf_unlikely(!(tx_desc_pool->
  5385. desc_pages.cacheable_pages)))
  5386. break;
  5387. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5388. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5389. /*
  5390. * Free TX desc if force free is
  5391. * required, otherwise only reset vdev
  5392. * in this TX desc.
  5393. */
  5394. if (force_free) {
  5395. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5396. dp_tx_comp_free_buf(soc, tx_desc,
  5397. false);
  5398. dp_tx_desc_release(tx_desc, i);
  5399. } else {
  5400. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5401. }
  5402. }
  5403. }
  5404. if (!force_free)
  5405. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5406. }
  5407. }
  5408. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5409. /**
  5410. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5411. *
  5412. * @soc: Handle to DP soc structure
  5413. * @tx_desc: pointer of one TX desc
  5414. * @desc_pool_id: TX Desc pool id
  5415. */
  5416. static inline void
  5417. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5418. uint8_t desc_pool_id)
  5419. {
  5420. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5421. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5422. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5423. }
  5424. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5425. bool force_free)
  5426. {
  5427. uint8_t i, num_pool;
  5428. uint32_t j;
  5429. uint32_t num_desc, page_id, offset;
  5430. uint16_t num_desc_per_page;
  5431. struct dp_soc *soc = pdev->soc;
  5432. struct dp_tx_desc_s *tx_desc = NULL;
  5433. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5434. if (!vdev && !force_free) {
  5435. dp_err("Reset TX desc vdev, Vdev param is required!");
  5436. return;
  5437. }
  5438. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5439. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5440. for (i = 0; i < num_pool; i++) {
  5441. tx_desc_pool = &soc->tx_desc[i];
  5442. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5443. continue;
  5444. num_desc_per_page =
  5445. tx_desc_pool->desc_pages.num_element_per_page;
  5446. for (j = 0; j < num_desc; j++) {
  5447. page_id = j / num_desc_per_page;
  5448. offset = j % num_desc_per_page;
  5449. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5450. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5451. if (force_free) {
  5452. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5453. dp_tx_comp_free_buf(soc, tx_desc,
  5454. false);
  5455. dp_tx_desc_release(tx_desc, i);
  5456. } else {
  5457. dp_tx_desc_reset_vdev(soc, tx_desc,
  5458. i);
  5459. }
  5460. }
  5461. }
  5462. }
  5463. }
  5464. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5465. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5466. {
  5467. struct dp_pdev *pdev = vdev->pdev;
  5468. /* Reset TX desc associated to this Vdev as NULL */
  5469. dp_tx_desc_flush(pdev, vdev, false);
  5470. return QDF_STATUS_SUCCESS;
  5471. }
  5472. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5473. /* Pools will be allocated dynamically */
  5474. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5475. int num_desc)
  5476. {
  5477. uint8_t i;
  5478. for (i = 0; i < num_pool; i++) {
  5479. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5480. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5481. }
  5482. return QDF_STATUS_SUCCESS;
  5483. }
  5484. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5485. uint32_t num_desc)
  5486. {
  5487. return QDF_STATUS_SUCCESS;
  5488. }
  5489. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5490. {
  5491. }
  5492. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5493. {
  5494. uint8_t i;
  5495. for (i = 0; i < num_pool; i++)
  5496. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5497. }
  5498. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5499. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5500. uint32_t num_desc)
  5501. {
  5502. uint8_t i, count;
  5503. /* Allocate software Tx descriptor pools */
  5504. for (i = 0; i < num_pool; i++) {
  5505. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5506. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5507. FL("Tx Desc Pool alloc %d failed %pK"),
  5508. i, soc);
  5509. goto fail;
  5510. }
  5511. }
  5512. return QDF_STATUS_SUCCESS;
  5513. fail:
  5514. for (count = 0; count < i; count++)
  5515. dp_tx_desc_pool_free(soc, count);
  5516. return QDF_STATUS_E_NOMEM;
  5517. }
  5518. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5519. uint32_t num_desc)
  5520. {
  5521. uint8_t i;
  5522. for (i = 0; i < num_pool; i++) {
  5523. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5524. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5525. FL("Tx Desc Pool init %d failed %pK"),
  5526. i, soc);
  5527. return QDF_STATUS_E_NOMEM;
  5528. }
  5529. }
  5530. return QDF_STATUS_SUCCESS;
  5531. }
  5532. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5533. {
  5534. uint8_t i;
  5535. for (i = 0; i < num_pool; i++)
  5536. dp_tx_desc_pool_deinit(soc, i);
  5537. }
  5538. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5539. {
  5540. uint8_t i;
  5541. for (i = 0; i < num_pool; i++)
  5542. dp_tx_desc_pool_free(soc, i);
  5543. }
  5544. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5545. /**
  5546. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5547. * @soc: core txrx main context
  5548. * @num_pool: number of pools
  5549. *
  5550. */
  5551. static void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5552. {
  5553. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5554. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5555. }
  5556. /**
  5557. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5558. * @soc: core txrx main context
  5559. * @num_pool: number of pools
  5560. *
  5561. */
  5562. static void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5563. {
  5564. dp_tx_tso_desc_pool_free(soc, num_pool);
  5565. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5566. }
  5567. #ifndef WLAN_SOFTUMAC_SUPPORT
  5568. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5569. {
  5570. uint8_t num_pool;
  5571. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5572. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5573. dp_tx_ext_desc_pool_free(soc, num_pool);
  5574. dp_tx_delete_static_pools(soc, num_pool);
  5575. }
  5576. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5577. {
  5578. uint8_t num_pool;
  5579. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5580. dp_tx_flow_control_deinit(soc);
  5581. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5582. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5583. dp_tx_deinit_static_pools(soc, num_pool);
  5584. }
  5585. #else
  5586. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5587. {
  5588. uint8_t num_pool;
  5589. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5590. dp_tx_delete_static_pools(soc, num_pool);
  5591. }
  5592. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5593. {
  5594. uint8_t num_pool;
  5595. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5596. dp_tx_flow_control_deinit(soc);
  5597. dp_tx_deinit_static_pools(soc, num_pool);
  5598. }
  5599. #endif /*WLAN_SOFTUMAC_SUPPORT*/
  5600. /**
  5601. * dp_tx_tso_cmn_desc_pool_alloc() - TSO cmn desc pool allocator
  5602. * @soc: DP soc handle
  5603. * @num_pool: Number of pools
  5604. * @num_desc: Number of descriptors
  5605. *
  5606. * Reserve TSO descriptor buffers
  5607. *
  5608. * Return: QDF_STATUS_E_FAILURE on failure or
  5609. * QDF_STATUS_SUCCESS on success
  5610. */
  5611. static QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5612. uint8_t num_pool,
  5613. uint32_t num_desc)
  5614. {
  5615. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5616. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5617. return QDF_STATUS_E_FAILURE;
  5618. }
  5619. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5620. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5621. num_pool, soc);
  5622. return QDF_STATUS_E_FAILURE;
  5623. }
  5624. return QDF_STATUS_SUCCESS;
  5625. }
  5626. /**
  5627. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5628. * @soc: DP soc handle
  5629. * @num_pool: Number of pools
  5630. * @num_desc: Number of descriptors
  5631. *
  5632. * Initialize TSO descriptor pools
  5633. *
  5634. * Return: QDF_STATUS_E_FAILURE on failure or
  5635. * QDF_STATUS_SUCCESS on success
  5636. */
  5637. static QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5638. uint8_t num_pool,
  5639. uint32_t num_desc)
  5640. {
  5641. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5642. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5643. return QDF_STATUS_E_FAILURE;
  5644. }
  5645. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5646. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5647. num_pool, soc);
  5648. return QDF_STATUS_E_FAILURE;
  5649. }
  5650. return QDF_STATUS_SUCCESS;
  5651. }
  5652. #ifndef WLAN_SOFTUMAC_SUPPORT
  5653. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5654. {
  5655. uint8_t num_pool;
  5656. uint32_t num_desc;
  5657. uint32_t num_ext_desc;
  5658. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5659. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5660. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5661. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5662. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5663. __func__, num_pool, num_desc);
  5664. if ((num_pool > MAX_TXDESC_POOLS) ||
  5665. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5666. goto fail1;
  5667. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5668. goto fail1;
  5669. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5670. goto fail2;
  5671. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5672. return QDF_STATUS_SUCCESS;
  5673. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5674. goto fail3;
  5675. return QDF_STATUS_SUCCESS;
  5676. fail3:
  5677. dp_tx_ext_desc_pool_free(soc, num_pool);
  5678. fail2:
  5679. dp_tx_delete_static_pools(soc, num_pool);
  5680. fail1:
  5681. return QDF_STATUS_E_RESOURCES;
  5682. }
  5683. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5684. {
  5685. uint8_t num_pool;
  5686. uint32_t num_desc;
  5687. uint32_t num_ext_desc;
  5688. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5689. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5690. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5691. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5692. goto fail1;
  5693. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5694. goto fail2;
  5695. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5696. return QDF_STATUS_SUCCESS;
  5697. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5698. goto fail3;
  5699. dp_tx_flow_control_init(soc);
  5700. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5701. return QDF_STATUS_SUCCESS;
  5702. fail3:
  5703. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5704. fail2:
  5705. dp_tx_deinit_static_pools(soc, num_pool);
  5706. fail1:
  5707. return QDF_STATUS_E_RESOURCES;
  5708. }
  5709. #else
  5710. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5711. {
  5712. uint8_t num_pool;
  5713. uint32_t num_desc;
  5714. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5715. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5716. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5717. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5718. __func__, num_pool, num_desc);
  5719. if ((num_pool > MAX_TXDESC_POOLS) ||
  5720. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5721. return QDF_STATUS_E_RESOURCES;
  5722. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5723. return QDF_STATUS_E_RESOURCES;
  5724. return QDF_STATUS_SUCCESS;
  5725. }
  5726. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5727. {
  5728. uint8_t num_pool;
  5729. uint32_t num_desc;
  5730. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5731. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5732. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5733. return QDF_STATUS_E_RESOURCES;
  5734. dp_tx_flow_control_init(soc);
  5735. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5736. return QDF_STATUS_SUCCESS;
  5737. }
  5738. #endif
  5739. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5740. {
  5741. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5742. uint8_t num_pool;
  5743. uint32_t num_ext_desc;
  5744. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5745. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5746. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5747. return QDF_STATUS_E_FAILURE;
  5748. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5749. return QDF_STATUS_E_FAILURE;
  5750. return QDF_STATUS_SUCCESS;
  5751. }
  5752. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5753. {
  5754. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5755. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5756. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5757. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5758. return QDF_STATUS_SUCCESS;
  5759. }
  5760. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5761. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5762. enum qdf_pkt_timestamp_index index, uint64_t time,
  5763. qdf_nbuf_t nbuf)
  5764. {
  5765. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5766. uint64_t tsf_time;
  5767. if (vdev->get_tsf_time) {
  5768. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5769. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5770. }
  5771. }
  5772. }
  5773. void dp_pkt_get_timestamp(uint64_t *time)
  5774. {
  5775. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5776. *time = qdf_get_log_timestamp();
  5777. }
  5778. #endif