sde_encoder.c 142 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/kthread.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/input.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sde_rsc.h>
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "sde_hwio.h"
  29. #include "sde_hw_catalog.h"
  30. #include "sde_hw_intf.h"
  31. #include "sde_hw_ctl.h"
  32. #include "sde_formats.h"
  33. #include "sde_encoder.h"
  34. #include "sde_encoder_phys.h"
  35. #include "sde_hw_dsc.h"
  36. #include "sde_crtc.h"
  37. #include "sde_trace.h"
  38. #include "sde_core_irq.h"
  39. #include "sde_hw_top.h"
  40. #include "sde_hw_qdss.h"
  41. #include "sde_encoder_dce.h"
  42. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  43. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  44. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  45. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  46. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  47. (p) ? (p)->parent->base.id : -1, \
  48. (p) ? (p)->intf_idx - INTF_0 : -1, \
  49. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  50. ##__VA_ARGS__)
  51. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  52. (p) ? (p)->parent->base.id : -1, \
  53. (p) ? (p)->intf_idx - INTF_0 : -1, \
  54. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  55. ##__VA_ARGS__)
  56. #define MISR_BUFF_SIZE 256
  57. #define IDLE_SHORT_TIMEOUT 1
  58. #define EVT_TIME_OUT_SPLIT 2
  59. /* Maximum number of VSYNC wait attempts for RSC state transition */
  60. #define MAX_RSC_WAIT 5
  61. #define TOPOLOGY_DUALPIPE_MERGE_MODE(x) \
  62. (((x) == SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE) || \
  63. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE) || \
  64. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC) || \
  65. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC))
  66. /**
  67. * enum sde_enc_rc_events - events for resource control state machine
  68. * @SDE_ENC_RC_EVENT_KICKOFF:
  69. * This event happens at NORMAL priority.
  70. * Event that signals the start of the transfer. When this event is
  71. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  72. * Regardless of the previous state, the resource should be in ON state
  73. * at the end of this event. At the end of this event, a delayed work is
  74. * scheduled to go to IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION
  75. * ktime.
  76. * @SDE_ENC_RC_EVENT_PRE_STOP:
  77. * This event happens at NORMAL priority.
  78. * This event, when received during the ON state, set RSC to IDLE, and
  79. * and leave the RC STATE in the PRE_OFF state.
  80. * It should be followed by the STOP event as part of encoder disable.
  81. * If received during IDLE or OFF states, it will do nothing.
  82. * @SDE_ENC_RC_EVENT_STOP:
  83. * This event happens at NORMAL priority.
  84. * When this event is received, disable all the MDP/DSI core clocks, and
  85. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  86. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  87. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  88. * Resource state should be in OFF at the end of the event.
  89. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  90. * This event happens at NORMAL priority from a work item.
  91. * Event signals that there is a seamless mode switch is in prgoress. A
  92. * client needs to turn of only irq - leave clocks ON to reduce the mode
  93. * switch latency.
  94. * @SDE_ENC_RC_EVENT_POST_MODESET:
  95. * This event happens at NORMAL priority from a work item.
  96. * Event signals that seamless mode switch is complete and resources are
  97. * acquired. Clients wants to turn on the irq again and update the rsc
  98. * with new vtotal.
  99. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  100. * This event happens at NORMAL priority from a work item.
  101. * Event signals that there were no frame updates for
  102. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  103. * and request RSC with IDLE state and change the resource state to IDLE.
  104. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  105. * This event is triggered from the input event thread when touch event is
  106. * received from the input device. On receiving this event,
  107. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  108. clocks and enable RSC.
  109. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  110. * off work since a new commit is imminent.
  111. */
  112. enum sde_enc_rc_events {
  113. SDE_ENC_RC_EVENT_KICKOFF = 1,
  114. SDE_ENC_RC_EVENT_PRE_STOP,
  115. SDE_ENC_RC_EVENT_STOP,
  116. SDE_ENC_RC_EVENT_PRE_MODESET,
  117. SDE_ENC_RC_EVENT_POST_MODESET,
  118. SDE_ENC_RC_EVENT_ENTER_IDLE,
  119. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  120. };
  121. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  122. {
  123. struct sde_encoder_virt *sde_enc;
  124. int i;
  125. sde_enc = to_sde_encoder_virt(drm_enc);
  126. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  127. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  128. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  129. SDE_EVT32(DRMID(drm_enc), enable);
  130. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  131. }
  132. }
  133. }
  134. static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc)
  135. {
  136. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  137. struct msm_drm_private *priv;
  138. struct sde_kms *sde_kms;
  139. struct device *cpu_dev;
  140. struct cpumask *cpu_mask = NULL;
  141. int cpu = 0;
  142. u32 cpu_dma_latency;
  143. priv = drm_enc->dev->dev_private;
  144. sde_kms = to_sde_kms(priv->kms);
  145. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  146. return;
  147. cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;
  148. cpumask_clear(&sde_enc->valid_cpu_mask);
  149. if (sde_enc->mode_info.frame_rate > FPS60)
  150. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask_perf);
  151. if (!cpu_mask &&
  152. sde_encoder_check_curr_mode(drm_enc,
  153. MSM_DISPLAY_CMD_MODE))
  154. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask);
  155. if (!cpu_mask)
  156. return;
  157. for_each_cpu(cpu, cpu_mask) {
  158. cpu_dev = get_cpu_device(cpu);
  159. if (!cpu_dev) {
  160. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  161. cpu);
  162. return;
  163. }
  164. cpumask_set_cpu(cpu, &sde_enc->valid_cpu_mask);
  165. dev_pm_qos_add_request(cpu_dev,
  166. &sde_enc->pm_qos_cpu_req[cpu],
  167. DEV_PM_QOS_RESUME_LATENCY, cpu_dma_latency);
  168. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_dma_latency, cpu);
  169. }
  170. }
  171. static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc)
  172. {
  173. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  174. struct device *cpu_dev;
  175. int cpu = 0;
  176. for_each_cpu(cpu, &sde_enc->valid_cpu_mask) {
  177. cpu_dev = get_cpu_device(cpu);
  178. if (!cpu_dev) {
  179. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  180. cpu);
  181. continue;
  182. }
  183. dev_pm_qos_remove_request(&sde_enc->pm_qos_cpu_req[cpu]);
  184. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu);
  185. }
  186. cpumask_clear(&sde_enc->valid_cpu_mask);
  187. }
  188. static bool _sde_encoder_is_autorefresh_enabled(
  189. struct sde_encoder_virt *sde_enc)
  190. {
  191. struct drm_connector *drm_conn;
  192. if (!sde_enc->cur_master ||
  193. !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
  194. return false;
  195. drm_conn = sde_enc->cur_master->connector;
  196. if (!drm_conn || !drm_conn->state)
  197. return false;
  198. return sde_connector_get_property(drm_conn->state,
  199. CONNECTOR_PROP_AUTOREFRESH) ? true : false;
  200. }
  201. static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,
  202. struct sde_hw_qdss *hw_qdss,
  203. struct sde_encoder_phys *phys, bool enable)
  204. {
  205. if (sde_enc->qdss_status == enable)
  206. return;
  207. sde_enc->qdss_status = enable;
  208. phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,
  209. sde_enc->qdss_status);
  210. hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);
  211. }
  212. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  213. s64 timeout_ms, struct sde_encoder_wait_info *info)
  214. {
  215. int rc = 0;
  216. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  217. ktime_t cur_ktime;
  218. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  219. do {
  220. rc = wait_event_timeout(*(info->wq),
  221. atomic_read(info->atomic_cnt) == info->count_check,
  222. wait_time_jiffies);
  223. cur_ktime = ktime_get();
  224. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  225. timeout_ms, atomic_read(info->atomic_cnt),
  226. info->count_check);
  227. /* If we timed out, counter is valid and time is less, wait again */
  228. } while ((atomic_read(info->atomic_cnt) != info->count_check) &&
  229. (rc == 0) &&
  230. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  231. return rc;
  232. }
  233. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  234. {
  235. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  236. return sde_enc &&
  237. (sde_enc->disp_info.display_type ==
  238. SDE_CONNECTOR_PRIMARY);
  239. }
  240. bool sde_encoder_is_dsi_display(struct drm_encoder *drm_enc)
  241. {
  242. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  243. return sde_enc &&
  244. (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI);
  245. }
  246. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  247. {
  248. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  249. return sde_enc && sde_enc->cur_master &&
  250. sde_enc->cur_master->cont_splash_enabled;
  251. }
  252. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  253. enum sde_intr_idx intr_idx)
  254. {
  255. SDE_EVT32(DRMID(phys_enc->parent),
  256. phys_enc->intf_idx - INTF_0,
  257. phys_enc->hw_pp->idx - PINGPONG_0,
  258. intr_idx);
  259. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  260. if (phys_enc->parent_ops.handle_frame_done)
  261. phys_enc->parent_ops.handle_frame_done(
  262. phys_enc->parent, phys_enc,
  263. SDE_ENCODER_FRAME_EVENT_ERROR);
  264. }
  265. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  266. enum sde_intr_idx intr_idx,
  267. struct sde_encoder_wait_info *wait_info)
  268. {
  269. struct sde_encoder_irq *irq;
  270. u32 irq_status;
  271. int ret, i;
  272. if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
  273. SDE_ERROR("invalid params\n");
  274. return -EINVAL;
  275. }
  276. irq = &phys_enc->irq[intr_idx];
  277. /* note: do master / slave checking outside */
  278. /* return EWOULDBLOCK since we know the wait isn't necessary */
  279. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  280. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  281. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  282. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  283. return -EWOULDBLOCK;
  284. }
  285. if (irq->irq_idx < 0) {
  286. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  287. irq->name, irq->hw_idx);
  288. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  289. irq->irq_idx);
  290. return 0;
  291. }
  292. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  293. atomic_read(wait_info->atomic_cnt));
  294. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  295. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  296. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  297. /*
  298. * Some module X may disable interrupt for longer duration
  299. * and it may trigger all interrupts including timer interrupt
  300. * when module X again enable the interrupt.
  301. * That may cause interrupt wait timeout API in this API.
  302. * It is handled by split the wait timer in two halves.
  303. */
  304. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  305. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  306. irq->hw_idx,
  307. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  308. wait_info);
  309. if (ret)
  310. break;
  311. }
  312. if (ret <= 0) {
  313. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  314. irq->irq_idx, true);
  315. if (irq_status) {
  316. unsigned long flags;
  317. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  318. irq->hw_idx, irq->irq_idx,
  319. phys_enc->hw_pp->idx - PINGPONG_0,
  320. atomic_read(wait_info->atomic_cnt));
  321. SDE_DEBUG_PHYS(phys_enc,
  322. "done but irq %d not triggered\n",
  323. irq->irq_idx);
  324. local_irq_save(flags);
  325. irq->cb.func(phys_enc, irq->irq_idx);
  326. local_irq_restore(flags);
  327. ret = 0;
  328. } else {
  329. ret = -ETIMEDOUT;
  330. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  331. irq->hw_idx, irq->irq_idx,
  332. phys_enc->hw_pp->idx - PINGPONG_0,
  333. atomic_read(wait_info->atomic_cnt), irq_status,
  334. SDE_EVTLOG_ERROR);
  335. }
  336. } else {
  337. ret = 0;
  338. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  339. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  340. atomic_read(wait_info->atomic_cnt));
  341. }
  342. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  343. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  344. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  345. return ret;
  346. }
  347. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  348. enum sde_intr_idx intr_idx)
  349. {
  350. struct sde_encoder_irq *irq;
  351. int ret = 0;
  352. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  353. SDE_ERROR("invalid params\n");
  354. return -EINVAL;
  355. }
  356. irq = &phys_enc->irq[intr_idx];
  357. if (irq->irq_idx >= 0) {
  358. SDE_DEBUG_PHYS(phys_enc,
  359. "skipping already registered irq %s type %d\n",
  360. irq->name, irq->intr_type);
  361. return 0;
  362. }
  363. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  364. irq->intr_type, irq->hw_idx);
  365. if (irq->irq_idx < 0) {
  366. SDE_ERROR_PHYS(phys_enc,
  367. "failed to lookup IRQ index for %s type:%d\n",
  368. irq->name, irq->intr_type);
  369. return -EINVAL;
  370. }
  371. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  372. &irq->cb);
  373. if (ret) {
  374. SDE_ERROR_PHYS(phys_enc,
  375. "failed to register IRQ callback for %s\n",
  376. irq->name);
  377. irq->irq_idx = -EINVAL;
  378. return ret;
  379. }
  380. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  381. if (ret) {
  382. SDE_ERROR_PHYS(phys_enc,
  383. "enable IRQ for intr:%s failed, irq_idx %d\n",
  384. irq->name, irq->irq_idx);
  385. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  386. irq->irq_idx, &irq->cb);
  387. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  388. irq->irq_idx, SDE_EVTLOG_ERROR);
  389. irq->irq_idx = -EINVAL;
  390. return ret;
  391. }
  392. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  393. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  394. irq->name, irq->irq_idx);
  395. return ret;
  396. }
  397. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  398. enum sde_intr_idx intr_idx)
  399. {
  400. struct sde_encoder_irq *irq;
  401. int ret;
  402. if (!phys_enc) {
  403. SDE_ERROR("invalid encoder\n");
  404. return -EINVAL;
  405. }
  406. irq = &phys_enc->irq[intr_idx];
  407. /* silently skip irqs that weren't registered */
  408. if (irq->irq_idx < 0) {
  409. SDE_ERROR(
  410. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  411. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  412. irq->irq_idx);
  413. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  414. irq->irq_idx, SDE_EVTLOG_ERROR);
  415. return 0;
  416. }
  417. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  418. if (ret)
  419. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  420. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  421. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  422. &irq->cb);
  423. if (ret)
  424. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  425. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  426. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  427. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  428. irq->irq_idx = -EINVAL;
  429. return 0;
  430. }
  431. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  432. struct sde_encoder_hw_resources *hw_res,
  433. struct drm_connector_state *conn_state)
  434. {
  435. struct sde_encoder_virt *sde_enc = NULL;
  436. struct msm_mode_info mode_info;
  437. int i = 0;
  438. if (!hw_res || !drm_enc || !conn_state) {
  439. SDE_ERROR("invalid argument(s), drm_enc %d, res %d, state %d\n",
  440. !drm_enc, !hw_res, !conn_state);
  441. return;
  442. }
  443. sde_enc = to_sde_encoder_virt(drm_enc);
  444. SDE_DEBUG_ENC(sde_enc, "\n");
  445. /* Query resources used by phys encs, expected to be without overlap */
  446. memset(hw_res, 0, sizeof(*hw_res));
  447. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  448. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  449. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  450. if (phys && phys->ops.get_hw_resources)
  451. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  452. }
  453. /*
  454. * NOTE: Do not use sde_encoder_get_mode_info here as this function is
  455. * called from atomic_check phase. Use the below API to get mode
  456. * information of the temporary conn_state passed
  457. */
  458. sde_connector_state_get_mode_info(conn_state, &mode_info);
  459. hw_res->topology = mode_info.topology;
  460. hw_res->comp_info = &sde_enc->mode_info.comp_info;
  461. hw_res->display_type = sde_enc->disp_info.display_type;
  462. }
  463. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  464. {
  465. struct sde_encoder_virt *sde_enc = NULL;
  466. int i = 0;
  467. if (!drm_enc) {
  468. SDE_ERROR("invalid encoder\n");
  469. return;
  470. }
  471. sde_enc = to_sde_encoder_virt(drm_enc);
  472. SDE_DEBUG_ENC(sde_enc, "\n");
  473. mutex_lock(&sde_enc->enc_lock);
  474. sde_rsc_client_destroy(sde_enc->rsc_client);
  475. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  476. struct sde_encoder_phys *phys;
  477. phys = sde_enc->phys_vid_encs[i];
  478. if (phys && phys->ops.destroy) {
  479. phys->ops.destroy(phys);
  480. --sde_enc->num_phys_encs;
  481. sde_enc->phys_encs[i] = NULL;
  482. }
  483. phys = sde_enc->phys_cmd_encs[i];
  484. if (phys && phys->ops.destroy) {
  485. phys->ops.destroy(phys);
  486. --sde_enc->num_phys_encs;
  487. sde_enc->phys_encs[i] = NULL;
  488. }
  489. }
  490. if (sde_enc->num_phys_encs)
  491. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  492. sde_enc->num_phys_encs);
  493. sde_enc->num_phys_encs = 0;
  494. mutex_unlock(&sde_enc->enc_lock);
  495. drm_encoder_cleanup(drm_enc);
  496. mutex_destroy(&sde_enc->enc_lock);
  497. kfree(sde_enc->input_handler);
  498. sde_enc->input_handler = NULL;
  499. kfree(sde_enc);
  500. }
  501. void sde_encoder_helper_update_intf_cfg(
  502. struct sde_encoder_phys *phys_enc)
  503. {
  504. struct sde_encoder_virt *sde_enc;
  505. struct sde_hw_intf_cfg_v1 *intf_cfg;
  506. enum sde_3d_blend_mode mode_3d;
  507. if (!phys_enc || !phys_enc->hw_pp) {
  508. SDE_ERROR("invalid args, encoder %d\n", !phys_enc);
  509. return;
  510. }
  511. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  512. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  513. SDE_DEBUG_ENC(sde_enc,
  514. "intf_cfg updated for %d at idx %d\n",
  515. phys_enc->intf_idx,
  516. intf_cfg->intf_count);
  517. /* setup interface configuration */
  518. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  519. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  520. return;
  521. }
  522. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  523. if (phys_enc == sde_enc->cur_master) {
  524. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  525. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  526. else
  527. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  528. }
  529. /* configure this interface as master for split display */
  530. if (phys_enc->split_role == ENC_ROLE_MASTER)
  531. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  532. /* setup which pp blk will connect to this intf */
  533. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  534. phys_enc->hw_intf->ops.bind_pingpong_blk(
  535. phys_enc->hw_intf,
  536. true,
  537. phys_enc->hw_pp->idx);
  538. /*setup merge_3d configuration */
  539. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  540. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  541. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  542. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  543. phys_enc->hw_pp->merge_3d->idx;
  544. if (phys_enc->hw_pp->ops.setup_3d_mode)
  545. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  546. mode_3d);
  547. }
  548. void sde_encoder_helper_split_config(
  549. struct sde_encoder_phys *phys_enc,
  550. enum sde_intf interface)
  551. {
  552. struct sde_encoder_virt *sde_enc;
  553. struct split_pipe_cfg *cfg;
  554. struct sde_hw_mdp *hw_mdptop;
  555. enum sde_rm_topology_name topology;
  556. struct msm_display_info *disp_info;
  557. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  558. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  559. return;
  560. }
  561. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  562. hw_mdptop = phys_enc->hw_mdptop;
  563. disp_info = &sde_enc->disp_info;
  564. cfg = &phys_enc->hw_intf->cfg;
  565. memset(cfg, 0, sizeof(*cfg));
  566. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  567. return;
  568. if (disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK)
  569. cfg->split_link_en = true;
  570. /**
  571. * disable split modes since encoder will be operating in as the only
  572. * encoder, either for the entire use case in the case of, for example,
  573. * single DSI, or for this frame in the case of left/right only partial
  574. * update.
  575. */
  576. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  577. if (hw_mdptop->ops.setup_split_pipe)
  578. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  579. if (hw_mdptop->ops.setup_pp_split)
  580. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  581. return;
  582. }
  583. cfg->en = true;
  584. cfg->mode = phys_enc->intf_mode;
  585. cfg->intf = interface;
  586. if (cfg->en && phys_enc->ops.needs_single_flush &&
  587. phys_enc->ops.needs_single_flush(phys_enc))
  588. cfg->split_flush_en = true;
  589. topology = sde_connector_get_topology_name(phys_enc->connector);
  590. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  591. cfg->pp_split_slave = cfg->intf;
  592. else
  593. cfg->pp_split_slave = INTF_MAX;
  594. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  595. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg->en);
  596. if (hw_mdptop->ops.setup_split_pipe)
  597. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  598. } else if (sde_enc->hw_pp[0]) {
  599. /*
  600. * slave encoder
  601. * - determine split index from master index,
  602. * assume master is first pp
  603. */
  604. cfg->pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  605. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  606. cfg->pp_split_index);
  607. if (hw_mdptop->ops.setup_pp_split)
  608. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  609. }
  610. }
  611. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  612. {
  613. struct sde_encoder_virt *sde_enc;
  614. int i = 0;
  615. if (!drm_enc)
  616. return false;
  617. sde_enc = to_sde_encoder_virt(drm_enc);
  618. if (!sde_enc)
  619. return false;
  620. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  621. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  622. if (phys && phys->in_clone_mode)
  623. return true;
  624. }
  625. return false;
  626. }
  627. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  628. struct drm_crtc_state *crtc_state,
  629. struct drm_connector_state *conn_state)
  630. {
  631. const struct drm_display_mode *mode;
  632. struct drm_display_mode *adj_mode;
  633. int i = 0;
  634. int ret = 0;
  635. mode = &crtc_state->mode;
  636. adj_mode = &crtc_state->adjusted_mode;
  637. /* perform atomic check on the first physical encoder (master) */
  638. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  639. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  640. if (phys && phys->ops.atomic_check)
  641. ret = phys->ops.atomic_check(phys, crtc_state,
  642. conn_state);
  643. else if (phys && phys->ops.mode_fixup)
  644. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  645. ret = -EINVAL;
  646. if (ret) {
  647. SDE_ERROR_ENC(sde_enc,
  648. "mode unsupported, phys idx %d\n", i);
  649. break;
  650. }
  651. }
  652. return ret;
  653. }
  654. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  655. struct drm_crtc_state *crtc_state,
  656. struct drm_connector_state *conn_state,
  657. struct sde_connector_state *sde_conn_state,
  658. struct sde_crtc_state *sde_crtc_state)
  659. {
  660. int ret = 0;
  661. if (crtc_state->mode_changed || crtc_state->active_changed) {
  662. struct sde_rect mode_roi, roi;
  663. mode_roi.x = 0;
  664. mode_roi.y = 0;
  665. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  666. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  667. if (sde_conn_state->rois.num_rects) {
  668. sde_kms_rect_merge_rectangles(
  669. &sde_conn_state->rois, &roi);
  670. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  671. SDE_ERROR_ENC(sde_enc,
  672. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  673. roi.x, roi.y, roi.w, roi.h);
  674. ret = -EINVAL;
  675. }
  676. }
  677. if (sde_crtc_state->user_roi_list.num_rects) {
  678. sde_kms_rect_merge_rectangles(
  679. &sde_crtc_state->user_roi_list, &roi);
  680. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  681. SDE_ERROR_ENC(sde_enc,
  682. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  683. roi.x, roi.y, roi.w, roi.h);
  684. ret = -EINVAL;
  685. }
  686. }
  687. }
  688. return ret;
  689. }
  690. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  691. struct drm_crtc_state *crtc_state,
  692. struct drm_connector_state *conn_state,
  693. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  694. struct sde_connector *sde_conn,
  695. struct sde_connector_state *sde_conn_state)
  696. {
  697. int ret = 0;
  698. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  699. if (sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {
  700. struct msm_display_topology *topology = NULL;
  701. ret = sde_connector_get_mode_info(&sde_conn->base,
  702. adj_mode, &sde_conn_state->mode_info);
  703. if (ret) {
  704. SDE_ERROR_ENC(sde_enc,
  705. "failed to get mode info, rc = %d\n", ret);
  706. return ret;
  707. }
  708. if (sde_conn_state->mode_info.comp_info.comp_type &&
  709. sde_conn_state->mode_info.comp_info.comp_ratio >=
  710. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  711. SDE_ERROR_ENC(sde_enc,
  712. "invalid compression ratio: %d\n",
  713. sde_conn_state->mode_info.comp_info.comp_ratio);
  714. ret = -EINVAL;
  715. return ret;
  716. }
  717. /* Reserve dynamic resources, indicating atomic_check phase */
  718. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  719. conn_state, true);
  720. if (ret) {
  721. SDE_ERROR_ENC(sde_enc,
  722. "RM failed to reserve resources, rc = %d\n",
  723. ret);
  724. return ret;
  725. }
  726. /**
  727. * Update connector state with the topology selected for the
  728. * resource set validated. Reset the topology if we are
  729. * de-activating crtc.
  730. */
  731. if (crtc_state->active)
  732. topology = &sde_conn_state->mode_info.topology;
  733. ret = sde_rm_update_topology(conn_state, topology);
  734. if (ret) {
  735. SDE_ERROR_ENC(sde_enc,
  736. "RM failed to update topology, rc: %d\n", ret);
  737. return ret;
  738. }
  739. ret = sde_connector_set_blob_data(conn_state->connector,
  740. conn_state,
  741. CONNECTOR_PROP_SDE_INFO);
  742. if (ret) {
  743. SDE_ERROR_ENC(sde_enc,
  744. "connector failed to update info, rc: %d\n",
  745. ret);
  746. return ret;
  747. }
  748. }
  749. return ret;
  750. }
  751. static int sde_encoder_virt_atomic_check(
  752. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  753. struct drm_connector_state *conn_state)
  754. {
  755. struct sde_encoder_virt *sde_enc;
  756. struct sde_kms *sde_kms;
  757. const struct drm_display_mode *mode;
  758. struct drm_display_mode *adj_mode;
  759. struct sde_connector *sde_conn = NULL;
  760. struct sde_connector_state *sde_conn_state = NULL;
  761. struct sde_crtc_state *sde_crtc_state = NULL;
  762. enum sde_rm_topology_name old_top;
  763. int ret = 0;
  764. if (!drm_enc || !crtc_state || !conn_state) {
  765. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  766. !drm_enc, !crtc_state, !conn_state);
  767. return -EINVAL;
  768. }
  769. sde_enc = to_sde_encoder_virt(drm_enc);
  770. SDE_DEBUG_ENC(sde_enc, "\n");
  771. sde_kms = sde_encoder_get_kms(drm_enc);
  772. if (!sde_kms)
  773. return -EINVAL;
  774. mode = &crtc_state->mode;
  775. adj_mode = &crtc_state->adjusted_mode;
  776. sde_conn = to_sde_connector(conn_state->connector);
  777. sde_conn_state = to_sde_connector_state(conn_state);
  778. sde_crtc_state = to_sde_crtc_state(crtc_state);
  779. SDE_EVT32(DRMID(drm_enc), crtc_state->mode_changed,
  780. crtc_state->active_changed, crtc_state->connectors_changed);
  781. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  782. conn_state);
  783. if (ret)
  784. return ret;
  785. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  786. conn_state, sde_conn_state, sde_crtc_state);
  787. if (ret)
  788. return ret;
  789. /**
  790. * record topology in previous atomic state to be able to handle
  791. * topology transitions correctly.
  792. */
  793. old_top = sde_connector_get_property(conn_state,
  794. CONNECTOR_PROP_TOPOLOGY_NAME);
  795. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  796. if (ret)
  797. return ret;
  798. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  799. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  800. if (ret)
  801. return ret;
  802. ret = sde_connector_roi_v1_check_roi(conn_state);
  803. if (ret) {
  804. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  805. ret);
  806. return ret;
  807. }
  808. drm_mode_set_crtcinfo(adj_mode, 0);
  809. SDE_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
  810. return ret;
  811. }
  812. static void _sde_encoder_get_connector_roi(
  813. struct sde_encoder_virt *sde_enc,
  814. struct sde_rect *merged_conn_roi)
  815. {
  816. struct drm_connector *drm_conn;
  817. struct sde_connector_state *c_state;
  818. if (!sde_enc || !merged_conn_roi)
  819. return;
  820. drm_conn = sde_enc->phys_encs[0]->connector;
  821. if (!drm_conn || !drm_conn->state)
  822. return;
  823. c_state = to_sde_connector_state(drm_conn->state);
  824. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  825. }
  826. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  827. {
  828. struct sde_encoder_virt *sde_enc;
  829. struct drm_connector *drm_conn;
  830. struct drm_display_mode *adj_mode;
  831. struct sde_rect roi;
  832. if (!drm_enc) {
  833. SDE_ERROR("invalid encoder parameter\n");
  834. return -EINVAL;
  835. }
  836. sde_enc = to_sde_encoder_virt(drm_enc);
  837. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  838. SDE_ERROR("invalid crtc parameter\n");
  839. return -EINVAL;
  840. }
  841. if (!sde_enc->cur_master) {
  842. SDE_ERROR("invalid cur_master parameter\n");
  843. return -EINVAL;
  844. }
  845. adj_mode = &sde_enc->cur_master->cached_mode;
  846. drm_conn = sde_enc->cur_master->connector;
  847. _sde_encoder_get_connector_roi(sde_enc, &roi);
  848. if (sde_kms_rect_is_null(&roi)) {
  849. roi.w = adj_mode->hdisplay;
  850. roi.h = adj_mode->vdisplay;
  851. }
  852. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  853. sizeof(sde_enc->prv_conn_roi));
  854. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  855. return 0;
  856. }
  857. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc,
  858. u32 vsync_source, bool is_dummy)
  859. {
  860. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  861. struct sde_kms *sde_kms;
  862. struct sde_hw_mdp *hw_mdptop;
  863. struct sde_encoder_virt *sde_enc;
  864. int i;
  865. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  866. if (!sde_enc) {
  867. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  868. return;
  869. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  870. SDE_ERROR("invalid num phys enc %d/%d\n",
  871. sde_enc->num_phys_encs,
  872. (int) ARRAY_SIZE(sde_enc->hw_pp));
  873. return;
  874. }
  875. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  876. if (!sde_kms) {
  877. SDE_ERROR("invalid sde_kms\n");
  878. return;
  879. }
  880. hw_mdptop = sde_kms->hw_mdp;
  881. if (!hw_mdptop) {
  882. SDE_ERROR("invalid mdptop\n");
  883. return;
  884. }
  885. if (hw_mdptop->ops.setup_vsync_source) {
  886. for (i = 0; i < sde_enc->num_phys_encs; i++)
  887. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  888. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  889. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  890. vsync_cfg.vsync_source = vsync_source;
  891. vsync_cfg.is_dummy = is_dummy;
  892. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  893. }
  894. }
  895. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  896. struct msm_display_info *disp_info, bool is_dummy)
  897. {
  898. struct sde_encoder_phys *phys;
  899. int i;
  900. u32 vsync_source;
  901. if (!sde_enc || !disp_info) {
  902. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  903. sde_enc != NULL, disp_info != NULL);
  904. return;
  905. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  906. SDE_ERROR("invalid num phys enc %d/%d\n",
  907. sde_enc->num_phys_encs,
  908. (int) ARRAY_SIZE(sde_enc->hw_pp));
  909. return;
  910. }
  911. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  912. if (is_dummy)
  913. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_0 -
  914. sde_enc->te_source;
  915. else if (disp_info->is_te_using_watchdog_timer)
  916. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4;
  917. else
  918. vsync_source = sde_enc->te_source;
  919. SDE_EVT32(DRMID(&sde_enc->base), vsync_source, is_dummy,
  920. disp_info->is_te_using_watchdog_timer);
  921. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  922. phys = sde_enc->phys_encs[i];
  923. if (phys && phys->ops.setup_vsync_source)
  924. phys->ops.setup_vsync_source(phys,
  925. vsync_source, is_dummy);
  926. }
  927. }
  928. }
  929. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  930. bool watchdog_te)
  931. {
  932. struct sde_encoder_virt *sde_enc;
  933. struct msm_display_info disp_info;
  934. if (!drm_enc) {
  935. pr_err("invalid drm encoder\n");
  936. return -EINVAL;
  937. }
  938. sde_enc = to_sde_encoder_virt(drm_enc);
  939. sde_encoder_control_te(drm_enc, false);
  940. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  941. disp_info.is_te_using_watchdog_timer = watchdog_te;
  942. _sde_encoder_update_vsync_source(sde_enc, &disp_info, false);
  943. sde_encoder_control_te(drm_enc, true);
  944. return 0;
  945. }
  946. static int _sde_encoder_rsc_client_update_vsync_wait(
  947. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  948. int wait_vblank_crtc_id)
  949. {
  950. int wait_refcount = 0, ret = 0;
  951. int pipe = -1;
  952. int wait_count = 0;
  953. struct drm_crtc *primary_crtc;
  954. struct drm_crtc *crtc;
  955. crtc = sde_enc->crtc;
  956. if (wait_vblank_crtc_id)
  957. wait_refcount =
  958. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  959. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  960. SDE_EVTLOG_FUNC_ENTRY);
  961. if (crtc->base.id != wait_vblank_crtc_id) {
  962. primary_crtc = drm_crtc_find(drm_enc->dev,
  963. NULL, wait_vblank_crtc_id);
  964. if (!primary_crtc) {
  965. SDE_ERROR_ENC(sde_enc,
  966. "failed to find primary crtc id %d\n",
  967. wait_vblank_crtc_id);
  968. return -EINVAL;
  969. }
  970. pipe = drm_crtc_index(primary_crtc);
  971. }
  972. /**
  973. * note: VBLANK is expected to be enabled at this point in
  974. * resource control state machine if on primary CRTC
  975. */
  976. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  977. if (sde_rsc_client_is_state_update_complete(
  978. sde_enc->rsc_client))
  979. break;
  980. if (crtc->base.id == wait_vblank_crtc_id)
  981. ret = sde_encoder_wait_for_event(drm_enc,
  982. MSM_ENC_VBLANK);
  983. else
  984. drm_wait_one_vblank(drm_enc->dev, pipe);
  985. if (ret) {
  986. SDE_ERROR_ENC(sde_enc,
  987. "wait for vblank failed ret:%d\n", ret);
  988. /**
  989. * rsc hardware may hang without vsync. avoid rsc hang
  990. * by generating the vsync from watchdog timer.
  991. */
  992. if (crtc->base.id == wait_vblank_crtc_id)
  993. sde_encoder_helper_switch_vsync(drm_enc, true);
  994. }
  995. }
  996. if (wait_count >= MAX_RSC_WAIT)
  997. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  998. SDE_EVTLOG_ERROR);
  999. if (wait_refcount)
  1000. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  1001. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1002. SDE_EVTLOG_FUNC_EXIT);
  1003. return ret;
  1004. }
  1005. static int _sde_encoder_update_rsc_client(
  1006. struct drm_encoder *drm_enc, bool enable)
  1007. {
  1008. struct sde_encoder_virt *sde_enc;
  1009. struct drm_crtc *crtc;
  1010. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  1011. struct sde_rsc_cmd_config *rsc_config;
  1012. int ret;
  1013. struct msm_display_info *disp_info;
  1014. struct msm_mode_info *mode_info;
  1015. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  1016. u32 qsync_mode = 0, v_front_porch;
  1017. struct drm_display_mode *mode;
  1018. bool is_vid_mode;
  1019. struct drm_encoder *enc;
  1020. if (!drm_enc || !drm_enc->dev) {
  1021. SDE_ERROR("invalid encoder arguments\n");
  1022. return -EINVAL;
  1023. }
  1024. sde_enc = to_sde_encoder_virt(drm_enc);
  1025. mode_info = &sde_enc->mode_info;
  1026. crtc = sde_enc->crtc;
  1027. if (!sde_enc->crtc) {
  1028. SDE_ERROR("invalid crtc parameter\n");
  1029. return -EINVAL;
  1030. }
  1031. disp_info = &sde_enc->disp_info;
  1032. rsc_config = &sde_enc->rsc_config;
  1033. if (!sde_enc->rsc_client) {
  1034. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  1035. return 0;
  1036. }
  1037. /**
  1038. * only primary command mode panel without Qsync can request CMD state.
  1039. * all other panels/displays can request for VID state including
  1040. * secondary command mode panel.
  1041. * Clone mode encoder can request CLK STATE only.
  1042. */
  1043. if (sde_enc->cur_master)
  1044. qsync_mode = sde_connector_get_qsync_mode(
  1045. sde_enc->cur_master->connector);
  1046. if (sde_encoder_in_clone_mode(drm_enc) ||
  1047. (disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  1048. (disp_info->display_type && qsync_mode))
  1049. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1050. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1051. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1052. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1053. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1054. drm_for_each_encoder(enc, drm_enc->dev) {
  1055. if (enc->base.id != drm_enc->base.id &&
  1056. sde_encoder_in_cont_splash(enc))
  1057. rsc_state = SDE_RSC_CLK_STATE;
  1058. }
  1059. SDE_EVT32(rsc_state, qsync_mode);
  1060. is_vid_mode = sde_encoder_check_curr_mode(&sde_enc->base,
  1061. MSM_DISPLAY_VIDEO_MODE);
  1062. mode = &sde_enc->crtc->state->mode;
  1063. v_front_porch = mode->vsync_start - mode->vdisplay;
  1064. /* compare specific items and reconfigure the rsc */
  1065. if ((rsc_config->fps != mode_info->frame_rate) ||
  1066. (rsc_config->vtotal != mode_info->vtotal) ||
  1067. (rsc_config->prefill_lines != mode_info->prefill_lines) ||
  1068. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1069. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1070. rsc_config->fps = mode_info->frame_rate;
  1071. rsc_config->vtotal = mode_info->vtotal;
  1072. /*
  1073. * for video mode, prefill lines should not go beyond vertical
  1074. * front porch for RSCC configuration. This will ensure bw
  1075. * downvotes are not sent within the active region. Additional
  1076. * -1 is to give one line time for rscc mode min_threshold.
  1077. */
  1078. if (is_vid_mode && (mode_info->prefill_lines >= v_front_porch))
  1079. rsc_config->prefill_lines = v_front_porch - 1;
  1080. else
  1081. rsc_config->prefill_lines = mode_info->prefill_lines;
  1082. rsc_config->jitter_numer = mode_info->jitter_numer;
  1083. rsc_config->jitter_denom = mode_info->jitter_denom;
  1084. sde_enc->rsc_state_init = false;
  1085. }
  1086. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1087. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1088. /* update it only once */
  1089. sde_enc->rsc_state_init = true;
  1090. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1091. rsc_state, rsc_config, crtc->base.id,
  1092. &wait_vblank_crtc_id);
  1093. } else {
  1094. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1095. rsc_state, NULL, crtc->base.id,
  1096. &wait_vblank_crtc_id);
  1097. }
  1098. /**
  1099. * if RSC performed a state change that requires a VBLANK wait, it will
  1100. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1101. *
  1102. * if we are the primary display, we will need to enable and wait
  1103. * locally since we hold the commit thread
  1104. *
  1105. * if we are an external display, we must send a signal to the primary
  1106. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1107. * by the primary panel's VBLANK signals
  1108. */
  1109. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1110. if (ret) {
  1111. SDE_ERROR_ENC(sde_enc,
  1112. "sde rsc client update failed ret:%d\n", ret);
  1113. return ret;
  1114. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1115. return ret;
  1116. }
  1117. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1118. sde_enc, wait_vblank_crtc_id);
  1119. return ret;
  1120. }
  1121. static void _sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1122. {
  1123. struct sde_encoder_virt *sde_enc;
  1124. int i;
  1125. if (!drm_enc) {
  1126. SDE_ERROR("invalid encoder\n");
  1127. return;
  1128. }
  1129. sde_enc = to_sde_encoder_virt(drm_enc);
  1130. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1131. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1132. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1133. if (phys && phys->ops.irq_control)
  1134. phys->ops.irq_control(phys, enable);
  1135. }
  1136. }
  1137. /* keep track of the userspace vblank during modeset */
  1138. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1139. u32 sw_event)
  1140. {
  1141. struct sde_encoder_virt *sde_enc;
  1142. bool enable;
  1143. int i;
  1144. if (!drm_enc) {
  1145. SDE_ERROR("invalid encoder\n");
  1146. return;
  1147. }
  1148. sde_enc = to_sde_encoder_virt(drm_enc);
  1149. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1150. sw_event, sde_enc->vblank_enabled);
  1151. /* nothing to do if vblank not enabled by userspace */
  1152. if (!sde_enc->vblank_enabled)
  1153. return;
  1154. /* disable vblank on pre_modeset */
  1155. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1156. enable = false;
  1157. /* enable vblank on post_modeset */
  1158. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1159. enable = true;
  1160. else
  1161. return;
  1162. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1163. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1164. if (phys && phys->ops.control_vblank_irq)
  1165. phys->ops.control_vblank_irq(phys, enable);
  1166. }
  1167. }
  1168. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1169. {
  1170. struct sde_encoder_virt *sde_enc;
  1171. if (!drm_enc)
  1172. return NULL;
  1173. sde_enc = to_sde_encoder_virt(drm_enc);
  1174. return sde_enc->rsc_client;
  1175. }
  1176. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1177. bool enable)
  1178. {
  1179. struct sde_kms *sde_kms;
  1180. struct sde_encoder_virt *sde_enc;
  1181. int rc;
  1182. sde_enc = to_sde_encoder_virt(drm_enc);
  1183. sde_kms = sde_encoder_get_kms(drm_enc);
  1184. if (!sde_kms)
  1185. return -EINVAL;
  1186. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1187. SDE_EVT32(DRMID(drm_enc), enable);
  1188. if (!sde_enc->cur_master) {
  1189. SDE_ERROR("encoder master not set\n");
  1190. return -EINVAL;
  1191. }
  1192. if (enable) {
  1193. /* enable SDE core clks */
  1194. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1195. if (rc < 0) {
  1196. SDE_ERROR("failed to enable power resource %d\n", rc);
  1197. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1198. return rc;
  1199. }
  1200. sde_enc->elevated_ahb_vote = true;
  1201. /* enable DSI clks */
  1202. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1203. true);
  1204. if (rc) {
  1205. SDE_ERROR("failed to enable clk control %d\n", rc);
  1206. pm_runtime_put_sync(drm_enc->dev->dev);
  1207. return rc;
  1208. }
  1209. /* enable all the irq */
  1210. _sde_encoder_irq_control(drm_enc, true);
  1211. _sde_encoder_pm_qos_add_request(drm_enc);
  1212. } else {
  1213. _sde_encoder_pm_qos_remove_request(drm_enc);
  1214. /* disable all the irq */
  1215. _sde_encoder_irq_control(drm_enc, false);
  1216. /* disable DSI clks */
  1217. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1218. /* disable SDE core clks */
  1219. pm_runtime_put_sync(drm_enc->dev->dev);
  1220. }
  1221. return 0;
  1222. }
  1223. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1224. bool enable, u32 frame_count)
  1225. {
  1226. struct sde_encoder_virt *sde_enc;
  1227. int i;
  1228. if (!drm_enc) {
  1229. SDE_ERROR("invalid encoder\n");
  1230. return;
  1231. }
  1232. sde_enc = to_sde_encoder_virt(drm_enc);
  1233. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1234. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1235. if (!phys || !phys->ops.setup_misr)
  1236. continue;
  1237. phys->ops.setup_misr(phys, enable, frame_count);
  1238. }
  1239. }
  1240. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1241. unsigned int type, unsigned int code, int value)
  1242. {
  1243. struct drm_encoder *drm_enc = NULL;
  1244. struct sde_encoder_virt *sde_enc = NULL;
  1245. struct msm_drm_thread *disp_thread = NULL;
  1246. struct msm_drm_private *priv = NULL;
  1247. if (!handle || !handle->handler || !handle->handler->private) {
  1248. SDE_ERROR("invalid encoder for the input event\n");
  1249. return;
  1250. }
  1251. drm_enc = (struct drm_encoder *)handle->handler->private;
  1252. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1253. SDE_ERROR("invalid parameters\n");
  1254. return;
  1255. }
  1256. priv = drm_enc->dev->dev_private;
  1257. sde_enc = to_sde_encoder_virt(drm_enc);
  1258. if (!sde_enc->crtc || (sde_enc->crtc->index
  1259. >= ARRAY_SIZE(priv->disp_thread))) {
  1260. SDE_DEBUG_ENC(sde_enc,
  1261. "invalid cached CRTC: %d or crtc index: %d\n",
  1262. sde_enc->crtc == NULL,
  1263. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1264. return;
  1265. }
  1266. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1267. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1268. kthread_queue_work(&disp_thread->worker,
  1269. &sde_enc->input_event_work);
  1270. }
  1271. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1272. {
  1273. struct sde_encoder_virt *sde_enc;
  1274. if (!drm_enc) {
  1275. SDE_ERROR("invalid encoder\n");
  1276. return;
  1277. }
  1278. sde_enc = to_sde_encoder_virt(drm_enc);
  1279. /* return early if there is no state change */
  1280. if (sde_enc->idle_pc_enabled == enable)
  1281. return;
  1282. sde_enc->idle_pc_enabled = enable;
  1283. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1284. SDE_EVT32(sde_enc->idle_pc_enabled);
  1285. }
  1286. static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
  1287. u32 sw_event)
  1288. {
  1289. struct drm_encoder *drm_enc = &sde_enc->base;
  1290. struct msm_drm_private *priv;
  1291. unsigned int lp, idle_pc_duration;
  1292. struct msm_drm_thread *disp_thread;
  1293. bool autorefresh_enabled = false;
  1294. autorefresh_enabled = _sde_encoder_is_autorefresh_enabled(sde_enc);
  1295. if (autorefresh_enabled)
  1296. return;
  1297. /* set idle timeout based on master connector's lp value */
  1298. if (sde_enc->cur_master)
  1299. lp = sde_connector_get_lp(
  1300. sde_enc->cur_master->connector);
  1301. else
  1302. lp = SDE_MODE_DPMS_ON;
  1303. if (lp == SDE_MODE_DPMS_LP2)
  1304. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1305. else
  1306. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1307. priv = drm_enc->dev->dev_private;
  1308. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1309. kthread_mod_delayed_work(
  1310. &disp_thread->worker,
  1311. &sde_enc->delayed_off_work,
  1312. msecs_to_jiffies(idle_pc_duration));
  1313. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1314. autorefresh_enabled,
  1315. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1316. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1317. sw_event);
  1318. }
  1319. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1320. u32 sw_event)
  1321. {
  1322. if (kthread_cancel_delayed_work_sync(
  1323. &sde_enc->delayed_off_work))
  1324. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1325. sw_event);
  1326. }
  1327. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1328. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1329. {
  1330. int ret = 0;
  1331. mutex_lock(&sde_enc->rc_lock);
  1332. /* return if the resource control is already in ON state */
  1333. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1334. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1335. sw_event);
  1336. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1337. SDE_EVTLOG_FUNC_CASE1);
  1338. goto end;
  1339. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1340. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1341. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1342. sw_event, sde_enc->rc_state);
  1343. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1344. SDE_EVTLOG_ERROR);
  1345. goto end;
  1346. }
  1347. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1348. _sde_encoder_irq_control(drm_enc, true);
  1349. } else {
  1350. /* enable all the clks and resources */
  1351. ret = _sde_encoder_resource_control_helper(drm_enc,
  1352. true);
  1353. if (ret) {
  1354. SDE_ERROR_ENC(sde_enc,
  1355. "sw_event:%d, rc in state %d\n",
  1356. sw_event, sde_enc->rc_state);
  1357. SDE_EVT32(DRMID(drm_enc), sw_event,
  1358. sde_enc->rc_state,
  1359. SDE_EVTLOG_ERROR);
  1360. goto end;
  1361. }
  1362. _sde_encoder_update_rsc_client(drm_enc, true);
  1363. }
  1364. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1365. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1366. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1367. end:
  1368. /* restart delayed off work, if required */
  1369. _sde_encoder_rc_restart_delayed(sde_enc, sw_event);
  1370. mutex_unlock(&sde_enc->rc_lock);
  1371. return ret;
  1372. }
  1373. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1374. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1375. {
  1376. /* cancel delayed off work, if any */
  1377. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1378. mutex_lock(&sde_enc->rc_lock);
  1379. if (is_vid_mode &&
  1380. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1381. _sde_encoder_irq_control(drm_enc, true);
  1382. }
  1383. /* skip if is already OFF or IDLE, resources are off already */
  1384. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1385. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1386. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1387. sw_event, sde_enc->rc_state);
  1388. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1389. SDE_EVTLOG_FUNC_CASE3);
  1390. goto end;
  1391. }
  1392. /**
  1393. * IRQs are still enabled currently, which allows wait for
  1394. * VBLANK which RSC may require to correctly transition to OFF
  1395. */
  1396. _sde_encoder_update_rsc_client(drm_enc, false);
  1397. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1398. SDE_ENC_RC_STATE_PRE_OFF,
  1399. SDE_EVTLOG_FUNC_CASE3);
  1400. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1401. end:
  1402. mutex_unlock(&sde_enc->rc_lock);
  1403. return 0;
  1404. }
  1405. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1406. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1407. {
  1408. int ret = 0;
  1409. /* cancel vsync event work and timer */
  1410. kthread_cancel_work_sync(&sde_enc->vsync_event_work);
  1411. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI)
  1412. del_timer_sync(&sde_enc->vsync_event_timer);
  1413. mutex_lock(&sde_enc->rc_lock);
  1414. /* return if the resource control is already in OFF state */
  1415. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1416. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1417. sw_event);
  1418. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1419. SDE_EVTLOG_FUNC_CASE4);
  1420. goto end;
  1421. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1422. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1423. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1424. sw_event, sde_enc->rc_state);
  1425. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1426. SDE_EVTLOG_ERROR);
  1427. ret = -EINVAL;
  1428. goto end;
  1429. }
  1430. /**
  1431. * expect to arrive here only if in either idle state or pre-off
  1432. * and in IDLE state the resources are already disabled
  1433. */
  1434. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  1435. _sde_encoder_resource_control_helper(drm_enc, false);
  1436. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1437. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  1438. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  1439. end:
  1440. mutex_unlock(&sde_enc->rc_lock);
  1441. return ret;
  1442. }
  1443. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  1444. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1445. {
  1446. int ret = 0;
  1447. /* cancel delayed off work, if any */
  1448. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1449. mutex_lock(&sde_enc->rc_lock);
  1450. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1451. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1452. sw_event);
  1453. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1454. SDE_EVTLOG_FUNC_CASE5);
  1455. goto end;
  1456. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1457. /* enable all the clks and resources */
  1458. ret = _sde_encoder_resource_control_helper(drm_enc,
  1459. true);
  1460. if (ret) {
  1461. SDE_ERROR_ENC(sde_enc,
  1462. "sw_event:%d, rc in state %d\n",
  1463. sw_event, sde_enc->rc_state);
  1464. SDE_EVT32(DRMID(drm_enc), sw_event,
  1465. sde_enc->rc_state,
  1466. SDE_EVTLOG_ERROR);
  1467. goto end;
  1468. }
  1469. _sde_encoder_update_rsc_client(drm_enc, true);
  1470. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1471. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  1472. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1473. }
  1474. ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  1475. if (ret && ret != -EWOULDBLOCK) {
  1476. SDE_ERROR_ENC(sde_enc,
  1477. "wait for commit done returned %d\n",
  1478. ret);
  1479. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1480. ret, SDE_EVTLOG_ERROR);
  1481. ret = -EINVAL;
  1482. goto end;
  1483. }
  1484. _sde_encoder_irq_control(drm_enc, false);
  1485. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1486. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1487. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  1488. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  1489. _sde_encoder_pm_qos_remove_request(drm_enc);
  1490. end:
  1491. mutex_unlock(&sde_enc->rc_lock);
  1492. return ret;
  1493. }
  1494. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  1495. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1496. {
  1497. int ret = 0;
  1498. mutex_lock(&sde_enc->rc_lock);
  1499. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1500. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1501. sw_event);
  1502. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1503. SDE_EVTLOG_FUNC_CASE5);
  1504. goto end;
  1505. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  1506. SDE_ERROR_ENC(sde_enc,
  1507. "sw_event:%d, rc:%d !MODESET state\n",
  1508. sw_event, sde_enc->rc_state);
  1509. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1510. SDE_EVTLOG_ERROR);
  1511. ret = -EINVAL;
  1512. goto end;
  1513. }
  1514. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1515. _sde_encoder_irq_control(drm_enc, true);
  1516. _sde_encoder_update_rsc_client(drm_enc, true);
  1517. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1518. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  1519. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1520. _sde_encoder_pm_qos_add_request(drm_enc);
  1521. end:
  1522. mutex_unlock(&sde_enc->rc_lock);
  1523. return ret;
  1524. }
  1525. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  1526. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1527. {
  1528. struct msm_drm_private *priv;
  1529. struct sde_kms *sde_kms;
  1530. struct drm_crtc *crtc = drm_enc->crtc;
  1531. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1532. priv = drm_enc->dev->dev_private;
  1533. sde_kms = to_sde_kms(priv->kms);
  1534. mutex_lock(&sde_enc->rc_lock);
  1535. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1536. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  1537. sw_event, sde_enc->rc_state);
  1538. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1539. SDE_EVTLOG_ERROR);
  1540. goto end;
  1541. } else if (sde_crtc_frame_pending(sde_enc->crtc)) {
  1542. SDE_DEBUG_ENC(sde_enc, "skip idle entry");
  1543. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1544. sde_crtc_frame_pending(sde_enc->crtc),
  1545. SDE_EVTLOG_ERROR);
  1546. _sde_encoder_rc_restart_delayed(sde_enc,
  1547. SDE_ENC_RC_EVENT_ENTER_IDLE);
  1548. goto end;
  1549. }
  1550. if (is_vid_mode) {
  1551. _sde_encoder_irq_control(drm_enc, false);
  1552. } else {
  1553. /* disable all the clks and resources */
  1554. _sde_encoder_update_rsc_client(drm_enc, false);
  1555. _sde_encoder_resource_control_helper(drm_enc, false);
  1556. if (!sde_kms->perf.bw_vote_mode)
  1557. memset(&sde_crtc->cur_perf, 0,
  1558. sizeof(struct sde_core_perf_params));
  1559. }
  1560. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1561. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  1562. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  1563. end:
  1564. mutex_unlock(&sde_enc->rc_lock);
  1565. return 0;
  1566. }
  1567. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  1568. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1569. struct msm_drm_private *priv, bool is_vid_mode)
  1570. {
  1571. bool autorefresh_enabled = false;
  1572. struct msm_drm_thread *disp_thread;
  1573. int ret = 0;
  1574. if (!sde_enc->crtc ||
  1575. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1576. SDE_DEBUG_ENC(sde_enc,
  1577. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  1578. sde_enc->crtc == NULL,
  1579. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  1580. sw_event);
  1581. return -EINVAL;
  1582. }
  1583. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1584. mutex_lock(&sde_enc->rc_lock);
  1585. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1586. if (sde_enc->cur_master &&
  1587. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1588. autorefresh_enabled =
  1589. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1590. sde_enc->cur_master);
  1591. if (autorefresh_enabled) {
  1592. SDE_DEBUG_ENC(sde_enc,
  1593. "not handling early wakeup since auto refresh is enabled\n");
  1594. goto end;
  1595. }
  1596. if (!sde_crtc_frame_pending(sde_enc->crtc))
  1597. kthread_mod_delayed_work(&disp_thread->worker,
  1598. &sde_enc->delayed_off_work,
  1599. msecs_to_jiffies(
  1600. IDLE_POWERCOLLAPSE_DURATION));
  1601. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1602. /* enable all the clks and resources */
  1603. ret = _sde_encoder_resource_control_helper(drm_enc,
  1604. true);
  1605. if (ret) {
  1606. SDE_ERROR_ENC(sde_enc,
  1607. "sw_event:%d, rc in state %d\n",
  1608. sw_event, sde_enc->rc_state);
  1609. SDE_EVT32(DRMID(drm_enc), sw_event,
  1610. sde_enc->rc_state,
  1611. SDE_EVTLOG_ERROR);
  1612. goto end;
  1613. }
  1614. _sde_encoder_update_rsc_client(drm_enc, true);
  1615. /*
  1616. * In some cases, commit comes with slight delay
  1617. * (> 80 ms)after early wake up, prevent clock switch
  1618. * off to avoid jank in next update. So, increase the
  1619. * command mode idle timeout sufficiently to prevent
  1620. * such case.
  1621. */
  1622. kthread_mod_delayed_work(&disp_thread->worker,
  1623. &sde_enc->delayed_off_work,
  1624. msecs_to_jiffies(
  1625. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  1626. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1627. }
  1628. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1629. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  1630. end:
  1631. mutex_unlock(&sde_enc->rc_lock);
  1632. return ret;
  1633. }
  1634. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  1635. u32 sw_event)
  1636. {
  1637. struct sde_encoder_virt *sde_enc;
  1638. struct msm_drm_private *priv;
  1639. int ret = 0;
  1640. bool is_vid_mode = false;
  1641. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1642. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  1643. sw_event);
  1644. return -EINVAL;
  1645. }
  1646. sde_enc = to_sde_encoder_virt(drm_enc);
  1647. priv = drm_enc->dev->dev_private;
  1648. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  1649. is_vid_mode = true;
  1650. /*
  1651. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  1652. * events and return early for other events (ie wb display).
  1653. */
  1654. if (!sde_enc->idle_pc_enabled &&
  1655. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  1656. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  1657. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  1658. sw_event != SDE_ENC_RC_EVENT_STOP &&
  1659. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  1660. return 0;
  1661. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  1662. sw_event, sde_enc->idle_pc_enabled);
  1663. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1664. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  1665. switch (sw_event) {
  1666. case SDE_ENC_RC_EVENT_KICKOFF:
  1667. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  1668. is_vid_mode);
  1669. break;
  1670. case SDE_ENC_RC_EVENT_PRE_STOP:
  1671. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  1672. is_vid_mode);
  1673. break;
  1674. case SDE_ENC_RC_EVENT_STOP:
  1675. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  1676. break;
  1677. case SDE_ENC_RC_EVENT_PRE_MODESET:
  1678. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  1679. break;
  1680. case SDE_ENC_RC_EVENT_POST_MODESET:
  1681. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  1682. break;
  1683. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  1684. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  1685. is_vid_mode);
  1686. break;
  1687. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  1688. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  1689. priv, is_vid_mode);
  1690. break;
  1691. default:
  1692. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  1693. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  1694. break;
  1695. }
  1696. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1697. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  1698. return ret;
  1699. }
  1700. static void sde_encoder_virt_mode_switch(struct drm_encoder *drm_enc,
  1701. enum sde_intf_mode intf_mode, struct drm_display_mode *adj_mode)
  1702. {
  1703. int i = 0;
  1704. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1705. if (intf_mode == INTF_MODE_CMD)
  1706. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  1707. else if (intf_mode == INTF_MODE_VIDEO)
  1708. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  1709. _sde_encoder_update_rsc_client(drm_enc, true);
  1710. if (intf_mode == INTF_MODE_CMD) {
  1711. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1712. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  1713. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  1714. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1715. msm_is_mode_seamless_poms(adj_mode),
  1716. SDE_EVTLOG_FUNC_CASE1);
  1717. } else if (intf_mode == INTF_MODE_VIDEO) {
  1718. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1719. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  1720. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1721. msm_is_mode_seamless_poms(adj_mode),
  1722. SDE_EVTLOG_FUNC_CASE2);
  1723. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  1724. }
  1725. }
  1726. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  1727. struct drm_display_mode *mode,
  1728. struct drm_display_mode *adj_mode)
  1729. {
  1730. struct sde_encoder_virt *sde_enc;
  1731. struct sde_kms *sde_kms;
  1732. struct drm_connector_list_iter conn_iter;
  1733. struct drm_connector *conn = NULL, *conn_search;
  1734. struct sde_rm_hw_iter dsc_iter, pp_iter, qdss_iter;
  1735. struct sde_rm_hw_iter vdc_iter;
  1736. struct sde_rm_hw_request request_hw;
  1737. enum sde_intf_mode intf_mode;
  1738. bool is_cmd_mode = false;
  1739. int i = 0, ret;
  1740. if (!drm_enc) {
  1741. SDE_ERROR("invalid encoder\n");
  1742. return;
  1743. }
  1744. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  1745. SDE_ERROR("power resource is not enabled\n");
  1746. return;
  1747. }
  1748. sde_enc = to_sde_encoder_virt(drm_enc);
  1749. SDE_DEBUG_ENC(sde_enc, "\n");
  1750. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1751. is_cmd_mode = true;
  1752. sde_kms = sde_encoder_get_kms(drm_enc);
  1753. if (!sde_kms)
  1754. return;
  1755. SDE_EVT32(DRMID(drm_enc));
  1756. /*
  1757. * cache the crtc in sde_enc on enable for duration of use case
  1758. * for correctly servicing asynchronous irq events and timers
  1759. */
  1760. if (!drm_enc->crtc) {
  1761. SDE_ERROR("invalid crtc\n");
  1762. return;
  1763. }
  1764. sde_enc->crtc = drm_enc->crtc;
  1765. drm_connector_list_iter_begin(sde_kms->dev, &conn_iter);
  1766. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1767. if (conn_search->encoder == drm_enc) {
  1768. conn = conn_search;
  1769. break;
  1770. }
  1771. }
  1772. drm_connector_list_iter_end(&conn_iter);
  1773. sde_crtc_set_qos_dirty(sde_enc->crtc);
  1774. if (!conn) {
  1775. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  1776. return;
  1777. } else if (!conn->state) {
  1778. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  1779. return;
  1780. }
  1781. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  1782. /* store the mode_info */
  1783. sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);
  1784. sde_encoder_dce_set_bpp(sde_enc->mode_info, sde_enc->crtc);
  1785. /* release resources before seamless mode change */
  1786. if (msm_is_mode_seamless_dms(adj_mode) ||
  1787. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1788. is_cmd_mode)) {
  1789. /* restore resource state before releasing them */
  1790. ret = sde_encoder_resource_control(drm_enc,
  1791. SDE_ENC_RC_EVENT_PRE_MODESET);
  1792. if (ret) {
  1793. SDE_ERROR_ENC(sde_enc,
  1794. "sde resource control failed: %d\n",
  1795. ret);
  1796. return;
  1797. }
  1798. /*
  1799. * Disable dce before switch the mode and after pre_modeset,
  1800. * to guarantee that previous kickoff finished.
  1801. */
  1802. sde_encoder_dce_disable(sde_enc);
  1803. } else if (msm_is_mode_seamless_poms(adj_mode)) {
  1804. _sde_encoder_modeset_helper_locked(drm_enc,
  1805. SDE_ENC_RC_EVENT_PRE_MODESET);
  1806. sde_encoder_virt_mode_switch(drm_enc, intf_mode, adj_mode);
  1807. }
  1808. /* Reserve dynamic resources now. Indicating non-AtomicTest phase */
  1809. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
  1810. conn->state, false);
  1811. if (ret) {
  1812. SDE_ERROR_ENC(sde_enc,
  1813. "failed to reserve hw resources, %d\n", ret);
  1814. return;
  1815. }
  1816. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  1817. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1818. sde_enc->hw_pp[i] = NULL;
  1819. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  1820. break;
  1821. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  1822. }
  1823. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1824. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1825. if (phys) {
  1826. sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
  1827. SDE_HW_BLK_QDSS);
  1828. for (i = 0; i < QDSS_MAX; i++) {
  1829. if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
  1830. phys->hw_qdss =
  1831. (struct sde_hw_qdss *)qdss_iter.hw;
  1832. break;
  1833. }
  1834. }
  1835. }
  1836. }
  1837. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  1838. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1839. sde_enc->hw_dsc[i] = NULL;
  1840. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  1841. break;
  1842. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  1843. }
  1844. sde_rm_init_hw_iter(&vdc_iter, drm_enc->base.id, SDE_HW_BLK_VDC);
  1845. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1846. sde_enc->hw_vdc[i] = NULL;
  1847. if (!sde_rm_get_hw(&sde_kms->rm, &vdc_iter))
  1848. break;
  1849. sde_enc->hw_vdc[i] = (struct sde_hw_vdc *) vdc_iter.hw;
  1850. }
  1851. /* Get PP for DSC configuration */
  1852. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1853. struct sde_hw_pingpong *pp = NULL;
  1854. unsigned long features = 0;
  1855. if (!sde_enc->hw_dsc[i])
  1856. continue;
  1857. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  1858. request_hw.type = SDE_HW_BLK_PINGPONG;
  1859. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  1860. break;
  1861. pp = (struct sde_hw_pingpong *) request_hw.hw;
  1862. features = pp->ops.get_hw_caps(pp);
  1863. if (test_bit(SDE_PINGPONG_DSC, &features))
  1864. sde_enc->hw_dsc_pp[i] = pp;
  1865. else
  1866. sde_enc->hw_dsc_pp[i] = NULL;
  1867. }
  1868. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1869. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1870. if (phys) {
  1871. if (!sde_enc->hw_pp[i] && sde_enc->topology.num_intf) {
  1872. SDE_ERROR_ENC(sde_enc,
  1873. "invalid pingpong block for the encoder\n");
  1874. return;
  1875. }
  1876. phys->hw_pp = sde_enc->hw_pp[i];
  1877. phys->connector = conn->state->connector;
  1878. if (phys->ops.mode_set)
  1879. phys->ops.mode_set(phys, mode, adj_mode);
  1880. }
  1881. }
  1882. /* update resources after seamless mode change */
  1883. if (msm_is_mode_seamless_dms(adj_mode) ||
  1884. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1885. is_cmd_mode))
  1886. sde_encoder_resource_control(&sde_enc->base,
  1887. SDE_ENC_RC_EVENT_POST_MODESET);
  1888. else if (msm_is_mode_seamless_poms(adj_mode))
  1889. _sde_encoder_modeset_helper_locked(drm_enc,
  1890. SDE_ENC_RC_EVENT_POST_MODESET);
  1891. }
  1892. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  1893. {
  1894. struct sde_encoder_virt *sde_enc;
  1895. struct sde_encoder_phys *phys;
  1896. int i;
  1897. if (!drm_enc) {
  1898. SDE_ERROR("invalid parameters\n");
  1899. return;
  1900. }
  1901. sde_enc = to_sde_encoder_virt(drm_enc);
  1902. if (!sde_enc) {
  1903. SDE_ERROR("invalid sde encoder\n");
  1904. return;
  1905. }
  1906. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1907. phys = sde_enc->phys_encs[i];
  1908. if (phys && phys->ops.control_te)
  1909. phys->ops.control_te(phys, enable);
  1910. }
  1911. }
  1912. static int _sde_encoder_input_connect(struct input_handler *handler,
  1913. struct input_dev *dev, const struct input_device_id *id)
  1914. {
  1915. struct input_handle *handle;
  1916. int rc = 0;
  1917. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  1918. if (!handle)
  1919. return -ENOMEM;
  1920. handle->dev = dev;
  1921. handle->handler = handler;
  1922. handle->name = handler->name;
  1923. rc = input_register_handle(handle);
  1924. if (rc) {
  1925. pr_err("failed to register input handle\n");
  1926. goto error;
  1927. }
  1928. rc = input_open_device(handle);
  1929. if (rc) {
  1930. pr_err("failed to open input device\n");
  1931. goto error_unregister;
  1932. }
  1933. return 0;
  1934. error_unregister:
  1935. input_unregister_handle(handle);
  1936. error:
  1937. kfree(handle);
  1938. return rc;
  1939. }
  1940. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  1941. {
  1942. input_close_device(handle);
  1943. input_unregister_handle(handle);
  1944. kfree(handle);
  1945. }
  1946. /**
  1947. * Structure for specifying event parameters on which to receive callbacks.
  1948. * This structure will trigger a callback in case of a touch event (specified by
  1949. * EV_ABS) where there is a change in X and Y coordinates,
  1950. */
  1951. static const struct input_device_id sde_input_ids[] = {
  1952. {
  1953. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  1954. .evbit = { BIT_MASK(EV_ABS) },
  1955. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  1956. BIT_MASK(ABS_MT_POSITION_X) |
  1957. BIT_MASK(ABS_MT_POSITION_Y) },
  1958. },
  1959. { },
  1960. };
  1961. static void _sde_encoder_input_handler_register(
  1962. struct drm_encoder *drm_enc)
  1963. {
  1964. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1965. int rc;
  1966. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1967. return;
  1968. if (sde_enc->input_handler && !sde_enc->input_handler->private) {
  1969. sde_enc->input_handler->private = sde_enc;
  1970. /* register input handler if not already registered */
  1971. rc = input_register_handler(sde_enc->input_handler);
  1972. if (rc) {
  1973. SDE_ERROR("input_handler_register failed, rc= %d\n",
  1974. rc);
  1975. kfree(sde_enc->input_handler);
  1976. }
  1977. }
  1978. }
  1979. static void _sde_encoder_input_handler_unregister(
  1980. struct drm_encoder *drm_enc)
  1981. {
  1982. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1983. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1984. return;
  1985. if (sde_enc->input_handler && sde_enc->input_handler->private) {
  1986. input_unregister_handler(sde_enc->input_handler);
  1987. sde_enc->input_handler->private = NULL;
  1988. }
  1989. }
  1990. static int _sde_encoder_input_handler(
  1991. struct sde_encoder_virt *sde_enc)
  1992. {
  1993. struct input_handler *input_handler = NULL;
  1994. int rc = 0;
  1995. if (sde_enc->input_handler) {
  1996. SDE_ERROR_ENC(sde_enc,
  1997. "input_handle is active. unexpected\n");
  1998. return -EINVAL;
  1999. }
  2000. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  2001. if (!input_handler)
  2002. return -ENOMEM;
  2003. input_handler->event = sde_encoder_input_event_handler;
  2004. input_handler->connect = _sde_encoder_input_connect;
  2005. input_handler->disconnect = _sde_encoder_input_disconnect;
  2006. input_handler->name = "sde";
  2007. input_handler->id_table = sde_input_ids;
  2008. sde_enc->input_handler = input_handler;
  2009. return rc;
  2010. }
  2011. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  2012. {
  2013. struct sde_encoder_virt *sde_enc = NULL;
  2014. struct sde_kms *sde_kms;
  2015. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2016. SDE_ERROR("invalid parameters\n");
  2017. return;
  2018. }
  2019. sde_kms = sde_encoder_get_kms(drm_enc);
  2020. if (!sde_kms)
  2021. return;
  2022. sde_enc = to_sde_encoder_virt(drm_enc);
  2023. if (!sde_enc || !sde_enc->cur_master) {
  2024. SDE_DEBUG("invalid sde encoder/master\n");
  2025. return;
  2026. }
  2027. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  2028. sde_enc->cur_master->hw_mdptop &&
  2029. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  2030. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  2031. sde_enc->cur_master->hw_mdptop);
  2032. if (sde_enc->cur_master->hw_mdptop &&
  2033. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
  2034. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  2035. sde_enc->cur_master->hw_mdptop,
  2036. sde_kms->catalog);
  2037. if (sde_enc->cur_master->hw_ctl &&
  2038. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  2039. !sde_enc->cur_master->cont_splash_enabled)
  2040. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  2041. sde_enc->cur_master->hw_ctl,
  2042. &sde_enc->cur_master->intf_cfg_v1);
  2043. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info, false);
  2044. sde_encoder_control_te(drm_enc, true);
  2045. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  2046. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  2047. }
  2048. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  2049. {
  2050. void *dither_cfg = NULL;
  2051. int ret = 0, i = 0;
  2052. size_t len = 0;
  2053. enum sde_rm_topology_name topology;
  2054. struct drm_encoder *drm_enc;
  2055. struct msm_display_dsc_info *dsc = NULL;
  2056. struct sde_encoder_virt *sde_enc;
  2057. struct sde_hw_pingpong *hw_pp;
  2058. u32 bpp, bpc;
  2059. if (!phys || !phys->connector || !phys->hw_pp ||
  2060. !phys->hw_pp->ops.setup_dither || !phys->parent)
  2061. return;
  2062. topology = sde_connector_get_topology_name(phys->connector);
  2063. if ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  2064. (phys->split_role == ENC_ROLE_SLAVE))
  2065. return;
  2066. drm_enc = phys->parent;
  2067. sde_enc = to_sde_encoder_virt(drm_enc);
  2068. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  2069. bpc = dsc->config.bits_per_component;
  2070. bpp = dsc->config.bits_per_pixel;
  2071. /* disable dither for 10 bpp or 10bpc dsc config */
  2072. if (bpp == 10 || bpc == 10) {
  2073. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  2074. return;
  2075. }
  2076. ret = sde_connector_get_dither_cfg(phys->connector,
  2077. phys->connector->state, &dither_cfg,
  2078. &len, sde_enc->idle_pc_restore);
  2079. /* skip reg writes when return values are invalid or no data */
  2080. if (ret && ret == -ENODATA)
  2081. return;
  2082. if (TOPOLOGY_DUALPIPE_MERGE_MODE(topology)) {
  2083. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2084. hw_pp = sde_enc->hw_pp[i];
  2085. phys->hw_pp->ops.setup_dither(hw_pp,
  2086. dither_cfg, len);
  2087. }
  2088. } else {
  2089. phys->hw_pp->ops.setup_dither(phys->hw_pp,
  2090. dither_cfg, len);
  2091. }
  2092. }
  2093. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  2094. {
  2095. struct sde_encoder_virt *sde_enc = NULL;
  2096. int i;
  2097. if (!drm_enc) {
  2098. SDE_ERROR("invalid encoder\n");
  2099. return;
  2100. }
  2101. sde_enc = to_sde_encoder_virt(drm_enc);
  2102. if (!sde_enc->cur_master) {
  2103. SDE_DEBUG("virt encoder has no master\n");
  2104. return;
  2105. }
  2106. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2107. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2108. sde_enc->idle_pc_restore = true;
  2109. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2110. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2111. if (!phys)
  2112. continue;
  2113. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2114. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2115. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2116. phys->ops.restore(phys);
  2117. _sde_encoder_setup_dither(phys);
  2118. }
  2119. if (sde_enc->cur_master->ops.restore)
  2120. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2121. _sde_encoder_virt_enable_helper(drm_enc);
  2122. }
  2123. static void sde_encoder_off_work(struct kthread_work *work)
  2124. {
  2125. struct sde_encoder_virt *sde_enc = container_of(work,
  2126. struct sde_encoder_virt, delayed_off_work.work);
  2127. struct drm_encoder *drm_enc;
  2128. if (!sde_enc) {
  2129. SDE_ERROR("invalid sde encoder\n");
  2130. return;
  2131. }
  2132. drm_enc = &sde_enc->base;
  2133. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2134. sde_encoder_idle_request(drm_enc);
  2135. SDE_ATRACE_END("sde_encoder_off_work");
  2136. }
  2137. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2138. {
  2139. struct sde_encoder_virt *sde_enc = NULL;
  2140. int i, ret = 0;
  2141. struct msm_compression_info *comp_info = NULL;
  2142. struct drm_display_mode *cur_mode = NULL;
  2143. struct msm_display_info *disp_info;
  2144. if (!drm_enc) {
  2145. SDE_ERROR("invalid encoder\n");
  2146. return;
  2147. }
  2148. sde_enc = to_sde_encoder_virt(drm_enc);
  2149. disp_info = &sde_enc->disp_info;
  2150. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2151. SDE_ERROR("power resource is not enabled\n");
  2152. return;
  2153. }
  2154. if (drm_enc->crtc && !sde_enc->crtc)
  2155. sde_enc->crtc = drm_enc->crtc;
  2156. comp_info = &sde_enc->mode_info.comp_info;
  2157. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2158. SDE_DEBUG_ENC(sde_enc, "\n");
  2159. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2160. sde_enc->cur_master = NULL;
  2161. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2162. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2163. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2164. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2165. sde_enc->cur_master = phys;
  2166. break;
  2167. }
  2168. }
  2169. if (!sde_enc->cur_master) {
  2170. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2171. return;
  2172. }
  2173. _sde_encoder_input_handler_register(drm_enc);
  2174. if (!(msm_is_mode_seamless_vrr(cur_mode)
  2175. || msm_is_mode_seamless_dms(cur_mode)
  2176. || msm_is_mode_seamless_dyn_clk(cur_mode)))
  2177. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2178. sde_encoder_off_work);
  2179. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2180. if (ret) {
  2181. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2182. ret);
  2183. return;
  2184. }
  2185. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2186. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2187. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2188. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2189. if (!phys)
  2190. continue;
  2191. phys->comp_type = comp_info->comp_type;
  2192. phys->comp_ratio = comp_info->comp_ratio;
  2193. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2194. phys->poms_align_vsync = disp_info->poms_align_vsync;
  2195. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2196. phys->dsc_extra_pclk_cycle_cnt =
  2197. comp_info->dsc_info.pclk_per_line;
  2198. phys->dsc_extra_disp_width =
  2199. comp_info->dsc_info.extra_width;
  2200. phys->dce_bytes_per_line =
  2201. comp_info->dsc_info.bytes_per_pkt *
  2202. comp_info->dsc_info.pkt_per_line;
  2203. } else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
  2204. phys->dce_bytes_per_line =
  2205. comp_info->vdc_info.bytes_per_pkt *
  2206. comp_info->vdc_info.pkt_per_line;
  2207. }
  2208. if (phys != sde_enc->cur_master) {
  2209. /**
  2210. * on DMS request, the encoder will be enabled
  2211. * already. Invoke restore to reconfigure the
  2212. * new mode.
  2213. */
  2214. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2215. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2216. phys->ops.restore)
  2217. phys->ops.restore(phys);
  2218. else if (phys->ops.enable)
  2219. phys->ops.enable(phys);
  2220. }
  2221. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2222. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2223. phys->ops.setup_misr(phys, true,
  2224. sde_enc->misr_frame_count);
  2225. }
  2226. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2227. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2228. sde_enc->cur_master->ops.restore)
  2229. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2230. else if (sde_enc->cur_master->ops.enable)
  2231. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2232. _sde_encoder_virt_enable_helper(drm_enc);
  2233. }
  2234. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2235. {
  2236. struct sde_encoder_virt *sde_enc = NULL;
  2237. struct sde_kms *sde_kms;
  2238. enum sde_intf_mode intf_mode;
  2239. int i = 0;
  2240. if (!drm_enc) {
  2241. SDE_ERROR("invalid encoder\n");
  2242. return;
  2243. } else if (!drm_enc->dev) {
  2244. SDE_ERROR("invalid dev\n");
  2245. return;
  2246. } else if (!drm_enc->dev->dev_private) {
  2247. SDE_ERROR("invalid dev_private\n");
  2248. return;
  2249. }
  2250. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2251. SDE_ERROR("power resource is not enabled\n");
  2252. return;
  2253. }
  2254. sde_enc = to_sde_encoder_virt(drm_enc);
  2255. SDE_DEBUG_ENC(sde_enc, "\n");
  2256. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2257. if (!sde_kms)
  2258. return;
  2259. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2260. SDE_EVT32(DRMID(drm_enc));
  2261. /* wait for idle */
  2262. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2263. _sde_encoder_input_handler_unregister(drm_enc);
  2264. /*
  2265. * For primary command mode and video mode encoders, execute the
  2266. * resource control pre-stop operations before the physical encoders
  2267. * are disabled, to allow the rsc to transition its states properly.
  2268. *
  2269. * For other encoder types, rsc should not be enabled until after
  2270. * they have been fully disabled, so delay the pre-stop operations
  2271. * until after the physical disable calls have returned.
  2272. */
  2273. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2274. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2275. sde_encoder_resource_control(drm_enc,
  2276. SDE_ENC_RC_EVENT_PRE_STOP);
  2277. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2278. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2279. if (phys && phys->ops.disable)
  2280. phys->ops.disable(phys);
  2281. }
  2282. } else {
  2283. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2284. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2285. if (phys && phys->ops.disable)
  2286. phys->ops.disable(phys);
  2287. }
  2288. sde_encoder_resource_control(drm_enc,
  2289. SDE_ENC_RC_EVENT_PRE_STOP);
  2290. }
  2291. /*
  2292. * disable dce after the transfer is complete (for command mode)
  2293. * and after physical encoder is disabled, to make sure timing
  2294. * engine is already disabled (for video mode).
  2295. */
  2296. sde_encoder_dce_disable(sde_enc);
  2297. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2298. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2299. if (sde_enc->phys_encs[i]) {
  2300. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2301. sde_enc->phys_encs[i]->connector = NULL;
  2302. }
  2303. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2304. }
  2305. sde_enc->cur_master = NULL;
  2306. /*
  2307. * clear the cached crtc in sde_enc on use case finish, after all the
  2308. * outstanding events and timers have been completed
  2309. */
  2310. sde_enc->crtc = NULL;
  2311. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2312. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2313. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2314. }
  2315. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2316. struct sde_encoder_phys_wb *wb_enc)
  2317. {
  2318. struct sde_encoder_virt *sde_enc;
  2319. phys_enc->hw_ctl->ops.reset(phys_enc->hw_ctl);
  2320. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2321. if (wb_enc) {
  2322. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2323. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2324. false, phys_enc->hw_pp->idx);
  2325. if (phys_enc->hw_ctl->ops.update_bitmask)
  2326. phys_enc->hw_ctl->ops.update_bitmask(
  2327. phys_enc->hw_ctl,
  2328. SDE_HW_FLUSH_WB,
  2329. wb_enc->hw_wb->idx, true);
  2330. }
  2331. } else {
  2332. if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2333. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2334. phys_enc->hw_intf, false,
  2335. phys_enc->hw_pp->idx);
  2336. if (phys_enc->hw_ctl->ops.update_bitmask)
  2337. phys_enc->hw_ctl->ops.update_bitmask(
  2338. phys_enc->hw_ctl,
  2339. SDE_HW_FLUSH_INTF,
  2340. phys_enc->hw_intf->idx, true);
  2341. }
  2342. }
  2343. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2344. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2345. if (phys_enc->hw_ctl->ops.update_bitmask &&
  2346. phys_enc->hw_pp->merge_3d)
  2347. phys_enc->hw_ctl->ops.update_bitmask(
  2348. phys_enc->hw_ctl, SDE_HW_FLUSH_MERGE_3D,
  2349. phys_enc->hw_pp->merge_3d->idx, true);
  2350. }
  2351. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2352. phys_enc->hw_pp) {
  2353. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2354. false, phys_enc->hw_pp->idx);
  2355. if (phys_enc->hw_ctl->ops.update_bitmask)
  2356. phys_enc->hw_ctl->ops.update_bitmask(
  2357. phys_enc->hw_ctl, SDE_HW_FLUSH_CDM,
  2358. phys_enc->hw_cdm->idx, true);
  2359. }
  2360. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2361. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2362. phys_enc->hw_ctl->ops.reset_post_disable)
  2363. phys_enc->hw_ctl->ops.reset_post_disable(
  2364. phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,
  2365. phys_enc->hw_pp->merge_3d ?
  2366. phys_enc->hw_pp->merge_3d->idx : 0);
  2367. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  2368. phys_enc->hw_ctl->ops.trigger_start(phys_enc->hw_ctl);
  2369. }
  2370. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2371. enum sde_intf_type type, u32 controller_id)
  2372. {
  2373. int i = 0;
  2374. for (i = 0; i < catalog->intf_count; i++) {
  2375. if (catalog->intf[i].type == type
  2376. && catalog->intf[i].controller_id == controller_id) {
  2377. return catalog->intf[i].id;
  2378. }
  2379. }
  2380. return INTF_MAX;
  2381. }
  2382. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2383. enum sde_intf_type type, u32 controller_id)
  2384. {
  2385. if (controller_id < catalog->wb_count)
  2386. return catalog->wb[controller_id].id;
  2387. return WB_MAX;
  2388. }
  2389. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2390. struct drm_crtc *crtc)
  2391. {
  2392. struct sde_hw_uidle *uidle;
  2393. struct sde_uidle_cntr cntr;
  2394. struct sde_uidle_status status;
  2395. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2396. pr_err("invalid params %d %d\n",
  2397. !sde_kms, !crtc);
  2398. return;
  2399. }
  2400. /* check if perf counters are enabled and setup */
  2401. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2402. return;
  2403. uidle = sde_kms->hw_uidle;
  2404. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2405. && uidle->ops.uidle_get_status) {
  2406. uidle->ops.uidle_get_status(uidle, &status);
  2407. trace_sde_perf_uidle_status(
  2408. crtc->base.id,
  2409. status.uidle_danger_status_0,
  2410. status.uidle_danger_status_1,
  2411. status.uidle_safe_status_0,
  2412. status.uidle_safe_status_1,
  2413. status.uidle_idle_status_0,
  2414. status.uidle_idle_status_1,
  2415. status.uidle_fal_status_0,
  2416. status.uidle_fal_status_1,
  2417. status.uidle_status,
  2418. status.uidle_en_fal10);
  2419. }
  2420. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2421. && uidle->ops.uidle_get_cntr) {
  2422. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2423. trace_sde_perf_uidle_cntr(
  2424. crtc->base.id,
  2425. cntr.fal1_gate_cntr,
  2426. cntr.fal10_gate_cntr,
  2427. cntr.fal_wait_gate_cntr,
  2428. cntr.fal1_num_transitions_cntr,
  2429. cntr.fal10_num_transitions_cntr,
  2430. cntr.min_gate_cntr,
  2431. cntr.max_gate_cntr);
  2432. }
  2433. }
  2434. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2435. struct sde_encoder_phys *phy_enc)
  2436. {
  2437. struct sde_encoder_virt *sde_enc = NULL;
  2438. unsigned long lock_flags;
  2439. if (!drm_enc || !phy_enc)
  2440. return;
  2441. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2442. sde_enc = to_sde_encoder_virt(drm_enc);
  2443. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2444. if (sde_enc->crtc_vblank_cb)
  2445. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data);
  2446. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2447. if (phy_enc->sde_kms &&
  2448. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2449. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2450. atomic_inc(&phy_enc->vsync_cnt);
  2451. SDE_ATRACE_END("encoder_vblank_callback");
  2452. }
  2453. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2454. struct sde_encoder_phys *phy_enc)
  2455. {
  2456. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2457. if (!phy_enc)
  2458. return;
  2459. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2460. atomic_inc(&phy_enc->underrun_cnt);
  2461. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2462. if (sde_enc->cur_master->ops.get_underrun_line_count)
  2463. sde_enc->cur_master->ops.get_underrun_line_count(
  2464. sde_enc->cur_master);
  2465. trace_sde_encoder_underrun(DRMID(drm_enc),
  2466. atomic_read(&phy_enc->underrun_cnt));
  2467. SDE_DBG_CTRL("stop_ftrace");
  2468. SDE_DBG_CTRL("panic_underrun");
  2469. SDE_ATRACE_END("encoder_underrun_callback");
  2470. }
  2471. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2472. void (*vbl_cb)(void *), void *vbl_data)
  2473. {
  2474. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2475. unsigned long lock_flags;
  2476. bool enable;
  2477. int i;
  2478. enable = vbl_cb ? true : false;
  2479. if (!drm_enc) {
  2480. SDE_ERROR("invalid encoder\n");
  2481. return;
  2482. }
  2483. SDE_DEBUG_ENC(sde_enc, "\n");
  2484. SDE_EVT32(DRMID(drm_enc), enable);
  2485. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2486. sde_enc->crtc_vblank_cb = vbl_cb;
  2487. sde_enc->crtc_vblank_cb_data = vbl_data;
  2488. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2489. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2490. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2491. if (phys && phys->ops.control_vblank_irq)
  2492. phys->ops.control_vblank_irq(phys, enable);
  2493. }
  2494. sde_enc->vblank_enabled = enable;
  2495. }
  2496. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2497. void (*frame_event_cb)(void *, u32 event),
  2498. struct drm_crtc *crtc)
  2499. {
  2500. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2501. unsigned long lock_flags;
  2502. bool enable;
  2503. enable = frame_event_cb ? true : false;
  2504. if (!drm_enc) {
  2505. SDE_ERROR("invalid encoder\n");
  2506. return;
  2507. }
  2508. SDE_DEBUG_ENC(sde_enc, "\n");
  2509. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2510. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2511. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2512. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2513. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2514. }
  2515. static void sde_encoder_frame_done_callback(
  2516. struct drm_encoder *drm_enc,
  2517. struct sde_encoder_phys *ready_phys, u32 event)
  2518. {
  2519. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2520. unsigned int i;
  2521. bool trigger = true;
  2522. bool is_cmd_mode = false;
  2523. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2524. if (!drm_enc || !sde_enc->cur_master) {
  2525. SDE_ERROR("invalid param: drm_enc %pK, cur_master %pK\n",
  2526. drm_enc, drm_enc ? sde_enc->cur_master : 0);
  2527. return;
  2528. }
  2529. sde_enc->crtc_frame_event_cb_data.connector =
  2530. sde_enc->cur_master->connector;
  2531. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2532. is_cmd_mode = true;
  2533. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2534. | SDE_ENCODER_FRAME_EVENT_ERROR
  2535. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2536. if (ready_phys->connector)
  2537. topology = sde_connector_get_topology_name(
  2538. ready_phys->connector);
  2539. /* One of the physical encoders has become idle */
  2540. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2541. if (sde_enc->phys_encs[i] == ready_phys) {
  2542. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2543. atomic_read(&sde_enc->frame_done_cnt[i]));
  2544. if (!atomic_add_unless(
  2545. &sde_enc->frame_done_cnt[i], 1, 1)) {
  2546. SDE_EVT32(DRMID(drm_enc), event,
  2547. ready_phys->intf_idx,
  2548. SDE_EVTLOG_ERROR);
  2549. SDE_ERROR_ENC(sde_enc,
  2550. "intf idx:%d, event:%d\n",
  2551. ready_phys->intf_idx, event);
  2552. return;
  2553. }
  2554. }
  2555. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  2556. atomic_read(&sde_enc->frame_done_cnt[i]) != 1)
  2557. trigger = false;
  2558. }
  2559. if (trigger) {
  2560. if (sde_enc->crtc_frame_event_cb)
  2561. sde_enc->crtc_frame_event_cb(
  2562. &sde_enc->crtc_frame_event_cb_data,
  2563. event);
  2564. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2565. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2566. }
  2567. } else if (sde_enc->crtc_frame_event_cb) {
  2568. sde_enc->crtc_frame_event_cb(
  2569. &sde_enc->crtc_frame_event_cb_data, event);
  2570. }
  2571. }
  2572. static void sde_encoder_get_qsync_fps_callback(
  2573. struct drm_encoder *drm_enc,
  2574. u32 *qsync_fps)
  2575. {
  2576. struct msm_display_info *disp_info;
  2577. struct sde_encoder_virt *sde_enc;
  2578. if (!qsync_fps)
  2579. return;
  2580. *qsync_fps = 0;
  2581. if (!drm_enc) {
  2582. SDE_ERROR("invalid drm encoder\n");
  2583. return;
  2584. }
  2585. sde_enc = to_sde_encoder_virt(drm_enc);
  2586. disp_info = &sde_enc->disp_info;
  2587. *qsync_fps = disp_info->qsync_min_fps;
  2588. }
  2589. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  2590. {
  2591. struct sde_encoder_virt *sde_enc;
  2592. if (!drm_enc) {
  2593. SDE_ERROR("invalid drm encoder\n");
  2594. return -EINVAL;
  2595. }
  2596. sde_enc = to_sde_encoder_virt(drm_enc);
  2597. sde_encoder_resource_control(&sde_enc->base,
  2598. SDE_ENC_RC_EVENT_ENTER_IDLE);
  2599. return 0;
  2600. }
  2601. /**
  2602. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  2603. * drm_enc: Pointer to drm encoder structure
  2604. * phys: Pointer to physical encoder structure
  2605. * extra_flush: Additional bit mask to include in flush trigger
  2606. */
  2607. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  2608. struct sde_encoder_phys *phys,
  2609. struct sde_ctl_flush_cfg *extra_flush)
  2610. {
  2611. struct sde_hw_ctl *ctl;
  2612. unsigned long lock_flags;
  2613. struct sde_encoder_virt *sde_enc;
  2614. int pend_ret_fence_cnt;
  2615. struct sde_connector *c_conn;
  2616. if (!drm_enc || !phys) {
  2617. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  2618. !drm_enc, !phys);
  2619. return;
  2620. }
  2621. sde_enc = to_sde_encoder_virt(drm_enc);
  2622. c_conn = to_sde_connector(phys->connector);
  2623. if (!phys->hw_pp) {
  2624. SDE_ERROR("invalid pingpong hw\n");
  2625. return;
  2626. }
  2627. ctl = phys->hw_ctl;
  2628. if (!ctl || !phys->ops.trigger_flush) {
  2629. SDE_ERROR("missing ctl/trigger cb\n");
  2630. return;
  2631. }
  2632. if (phys->split_role == ENC_ROLE_SKIP) {
  2633. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  2634. "skip flush pp%d ctl%d\n",
  2635. phys->hw_pp->idx - PINGPONG_0,
  2636. ctl->idx - CTL_0);
  2637. return;
  2638. }
  2639. /* update pending counts and trigger kickoff ctl flush atomically */
  2640. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2641. if (phys->ops.is_master && phys->ops.is_master(phys))
  2642. atomic_inc(&phys->pending_retire_fence_cnt);
  2643. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  2644. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  2645. ctl->ops.update_bitmask) {
  2646. /* perform peripheral flush on every frame update for dp dsc */
  2647. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  2648. phys->comp_ratio && c_conn->ops.update_pps) {
  2649. c_conn->ops.update_pps(phys->connector, NULL,
  2650. c_conn->display);
  2651. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2652. phys->hw_intf->idx, 1);
  2653. }
  2654. if (sde_enc->dynamic_hdr_updated)
  2655. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2656. phys->hw_intf->idx, 1);
  2657. }
  2658. if ((extra_flush && extra_flush->pending_flush_mask)
  2659. && ctl->ops.update_pending_flush)
  2660. ctl->ops.update_pending_flush(ctl, extra_flush);
  2661. phys->ops.trigger_flush(phys);
  2662. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2663. if (ctl->ops.get_pending_flush) {
  2664. struct sde_ctl_flush_cfg pending_flush = {0,};
  2665. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2666. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2667. ctl->idx - CTL_0,
  2668. pending_flush.pending_flush_mask,
  2669. pend_ret_fence_cnt);
  2670. } else {
  2671. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2672. ctl->idx - CTL_0,
  2673. pend_ret_fence_cnt);
  2674. }
  2675. }
  2676. /**
  2677. * _sde_encoder_trigger_start - trigger start for a physical encoder
  2678. * phys: Pointer to physical encoder structure
  2679. */
  2680. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  2681. {
  2682. struct sde_hw_ctl *ctl;
  2683. struct sde_encoder_virt *sde_enc;
  2684. if (!phys) {
  2685. SDE_ERROR("invalid argument(s)\n");
  2686. return;
  2687. }
  2688. if (!phys->hw_pp) {
  2689. SDE_ERROR("invalid pingpong hw\n");
  2690. return;
  2691. }
  2692. if (!phys->parent) {
  2693. SDE_ERROR("invalid parent\n");
  2694. return;
  2695. }
  2696. /* avoid ctrl start for encoder in clone mode */
  2697. if (phys->in_clone_mode)
  2698. return;
  2699. ctl = phys->hw_ctl;
  2700. sde_enc = to_sde_encoder_virt(phys->parent);
  2701. if (phys->split_role == ENC_ROLE_SKIP) {
  2702. SDE_DEBUG_ENC(sde_enc,
  2703. "skip start pp%d ctl%d\n",
  2704. phys->hw_pp->idx - PINGPONG_0,
  2705. ctl->idx - CTL_0);
  2706. return;
  2707. }
  2708. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  2709. phys->ops.trigger_start(phys);
  2710. }
  2711. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  2712. {
  2713. struct sde_hw_ctl *ctl;
  2714. if (!phys_enc) {
  2715. SDE_ERROR("invalid encoder\n");
  2716. return;
  2717. }
  2718. ctl = phys_enc->hw_ctl;
  2719. if (ctl && ctl->ops.trigger_flush)
  2720. ctl->ops.trigger_flush(ctl);
  2721. }
  2722. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  2723. {
  2724. struct sde_hw_ctl *ctl;
  2725. if (!phys_enc) {
  2726. SDE_ERROR("invalid encoder\n");
  2727. return;
  2728. }
  2729. ctl = phys_enc->hw_ctl;
  2730. if (ctl && ctl->ops.trigger_start) {
  2731. ctl->ops.trigger_start(ctl);
  2732. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  2733. }
  2734. }
  2735. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  2736. {
  2737. struct sde_encoder_virt *sde_enc;
  2738. struct sde_connector *sde_con;
  2739. void *sde_con_disp;
  2740. struct sde_hw_ctl *ctl;
  2741. int rc;
  2742. if (!phys_enc) {
  2743. SDE_ERROR("invalid encoder\n");
  2744. return;
  2745. }
  2746. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2747. ctl = phys_enc->hw_ctl;
  2748. if (!ctl || !ctl->ops.reset)
  2749. return;
  2750. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  2751. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  2752. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  2753. phys_enc->connector) {
  2754. sde_con = to_sde_connector(phys_enc->connector);
  2755. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  2756. if (sde_con->ops.soft_reset) {
  2757. rc = sde_con->ops.soft_reset(sde_con_disp);
  2758. if (rc) {
  2759. SDE_ERROR_ENC(sde_enc,
  2760. "connector soft reset failure\n");
  2761. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus",
  2762. "panic");
  2763. }
  2764. }
  2765. }
  2766. phys_enc->enable_state = SDE_ENC_ENABLED;
  2767. }
  2768. /**
  2769. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  2770. * Iterate through the physical encoders and perform consolidated flush
  2771. * and/or control start triggering as needed. This is done in the virtual
  2772. * encoder rather than the individual physical ones in order to handle
  2773. * use cases that require visibility into multiple physical encoders at
  2774. * a time.
  2775. * sde_enc: Pointer to virtual encoder structure
  2776. */
  2777. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
  2778. {
  2779. struct sde_hw_ctl *ctl;
  2780. uint32_t i;
  2781. struct sde_ctl_flush_cfg pending_flush = {0,};
  2782. u32 pending_kickoff_cnt;
  2783. struct msm_drm_private *priv = NULL;
  2784. struct sde_kms *sde_kms = NULL;
  2785. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  2786. bool is_regdma_blocking = false, is_vid_mode = false;
  2787. if (!sde_enc) {
  2788. SDE_ERROR("invalid encoder\n");
  2789. return;
  2790. }
  2791. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  2792. is_vid_mode = true;
  2793. is_regdma_blocking = (is_vid_mode ||
  2794. _sde_encoder_is_autorefresh_enabled(sde_enc));
  2795. /* don't perform flush/start operations for slave encoders */
  2796. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2797. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2798. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2799. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2800. continue;
  2801. ctl = phys->hw_ctl;
  2802. if (!ctl)
  2803. continue;
  2804. if (phys->connector)
  2805. topology = sde_connector_get_topology_name(
  2806. phys->connector);
  2807. if (!phys->ops.needs_single_flush ||
  2808. !phys->ops.needs_single_flush(phys)) {
  2809. if (ctl->ops.reg_dma_flush)
  2810. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2811. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
  2812. } else if (ctl->ops.get_pending_flush) {
  2813. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2814. }
  2815. }
  2816. /* for split flush, combine pending flush masks and send to master */
  2817. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  2818. ctl = sde_enc->cur_master->hw_ctl;
  2819. if (ctl->ops.reg_dma_flush)
  2820. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2821. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  2822. &pending_flush);
  2823. }
  2824. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  2825. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2826. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2827. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2828. continue;
  2829. if (!phys->ops.needs_single_flush ||
  2830. !phys->ops.needs_single_flush(phys)) {
  2831. pending_kickoff_cnt =
  2832. sde_encoder_phys_inc_pending(phys);
  2833. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  2834. } else {
  2835. pending_kickoff_cnt =
  2836. sde_encoder_phys_inc_pending(phys);
  2837. SDE_EVT32(pending_kickoff_cnt,
  2838. pending_flush.pending_flush_mask,
  2839. SDE_EVTLOG_FUNC_CASE2);
  2840. }
  2841. }
  2842. if (sde_enc->misr_enable)
  2843. sde_encoder_misr_configure(&sde_enc->base, true,
  2844. sde_enc->misr_frame_count);
  2845. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  2846. if (crtc_misr_info.misr_enable)
  2847. sde_crtc_misr_setup(sde_enc->crtc, true,
  2848. crtc_misr_info.misr_frame_count);
  2849. _sde_encoder_trigger_start(sde_enc->cur_master);
  2850. if (sde_enc->elevated_ahb_vote) {
  2851. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2852. priv = sde_enc->base.dev->dev_private;
  2853. if (sde_kms != NULL) {
  2854. sde_power_scale_reg_bus(&priv->phandle,
  2855. VOTE_INDEX_LOW,
  2856. false);
  2857. }
  2858. sde_enc->elevated_ahb_vote = false;
  2859. }
  2860. }
  2861. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  2862. struct drm_encoder *drm_enc,
  2863. unsigned long *affected_displays,
  2864. int num_active_phys)
  2865. {
  2866. struct sde_encoder_virt *sde_enc;
  2867. struct sde_encoder_phys *master;
  2868. enum sde_rm_topology_name topology;
  2869. bool is_right_only;
  2870. if (!drm_enc || !affected_displays)
  2871. return;
  2872. sde_enc = to_sde_encoder_virt(drm_enc);
  2873. master = sde_enc->cur_master;
  2874. if (!master || !master->connector)
  2875. return;
  2876. topology = sde_connector_get_topology_name(master->connector);
  2877. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  2878. return;
  2879. /*
  2880. * For pingpong split, the slave pingpong won't generate IRQs. For
  2881. * right-only updates, we can't swap pingpongs, or simply swap the
  2882. * master/slave assignment, we actually have to swap the interfaces
  2883. * so that the master physical encoder will use a pingpong/interface
  2884. * that generates irqs on which to wait.
  2885. */
  2886. is_right_only = !test_bit(0, affected_displays) &&
  2887. test_bit(1, affected_displays);
  2888. if (is_right_only && !sde_enc->intfs_swapped) {
  2889. /* right-only update swap interfaces */
  2890. swap(sde_enc->phys_encs[0]->intf_idx,
  2891. sde_enc->phys_encs[1]->intf_idx);
  2892. sde_enc->intfs_swapped = true;
  2893. } else if (!is_right_only && sde_enc->intfs_swapped) {
  2894. /* left-only or full update, swap back */
  2895. swap(sde_enc->phys_encs[0]->intf_idx,
  2896. sde_enc->phys_encs[1]->intf_idx);
  2897. sde_enc->intfs_swapped = false;
  2898. }
  2899. SDE_DEBUG_ENC(sde_enc,
  2900. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  2901. is_right_only, sde_enc->intfs_swapped,
  2902. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2903. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  2904. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  2905. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2906. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  2907. *affected_displays);
  2908. /* ppsplit always uses master since ppslave invalid for irqs*/
  2909. if (num_active_phys == 1)
  2910. *affected_displays = BIT(0);
  2911. }
  2912. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  2913. struct sde_encoder_kickoff_params *params)
  2914. {
  2915. struct sde_encoder_virt *sde_enc;
  2916. struct sde_encoder_phys *phys;
  2917. int i, num_active_phys;
  2918. bool master_assigned = false;
  2919. if (!drm_enc || !params)
  2920. return;
  2921. sde_enc = to_sde_encoder_virt(drm_enc);
  2922. if (sde_enc->num_phys_encs <= 1)
  2923. return;
  2924. /* count bits set */
  2925. num_active_phys = hweight_long(params->affected_displays);
  2926. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  2927. params->affected_displays, num_active_phys);
  2928. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  2929. num_active_phys);
  2930. /* for left/right only update, ppsplit master switches interface */
  2931. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  2932. &params->affected_displays, num_active_phys);
  2933. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2934. enum sde_enc_split_role prv_role, new_role;
  2935. bool active = false;
  2936. phys = sde_enc->phys_encs[i];
  2937. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  2938. continue;
  2939. active = test_bit(i, &params->affected_displays);
  2940. prv_role = phys->split_role;
  2941. if (active && num_active_phys == 1)
  2942. new_role = ENC_ROLE_SOLO;
  2943. else if (active && !master_assigned)
  2944. new_role = ENC_ROLE_MASTER;
  2945. else if (active)
  2946. new_role = ENC_ROLE_SLAVE;
  2947. else
  2948. new_role = ENC_ROLE_SKIP;
  2949. phys->ops.update_split_role(phys, new_role);
  2950. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  2951. sde_enc->cur_master = phys;
  2952. master_assigned = true;
  2953. }
  2954. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  2955. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2956. phys->split_role, active);
  2957. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  2958. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2959. phys->split_role, active, num_active_phys);
  2960. }
  2961. }
  2962. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  2963. {
  2964. struct sde_encoder_virt *sde_enc;
  2965. struct msm_display_info *disp_info;
  2966. if (!drm_enc) {
  2967. SDE_ERROR("invalid encoder\n");
  2968. return false;
  2969. }
  2970. sde_enc = to_sde_encoder_virt(drm_enc);
  2971. disp_info = &sde_enc->disp_info;
  2972. return (disp_info->curr_panel_mode == mode);
  2973. }
  2974. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  2975. {
  2976. struct sde_encoder_virt *sde_enc;
  2977. struct sde_encoder_phys *phys;
  2978. unsigned int i;
  2979. struct sde_hw_ctl *ctl;
  2980. if (!drm_enc) {
  2981. SDE_ERROR("invalid encoder\n");
  2982. return;
  2983. }
  2984. sde_enc = to_sde_encoder_virt(drm_enc);
  2985. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2986. phys = sde_enc->phys_encs[i];
  2987. if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
  2988. sde_encoder_check_curr_mode(drm_enc,
  2989. MSM_DISPLAY_CMD_MODE)) {
  2990. ctl = phys->hw_ctl;
  2991. if (ctl->ops.trigger_pending)
  2992. /* update only for command mode primary ctl */
  2993. ctl->ops.trigger_pending(ctl);
  2994. }
  2995. }
  2996. sde_enc->idle_pc_restore = false;
  2997. }
  2998. static int _sde_encoder_wakeup_time(struct drm_encoder *drm_enc,
  2999. ktime_t *wakeup_time)
  3000. {
  3001. struct drm_display_mode *mode;
  3002. struct sde_encoder_virt *sde_enc;
  3003. u32 cur_line, lines_left;
  3004. u32 line_time, mdp_transfer_time_us;
  3005. u32 vtotal, time_to_vsync_us, threshold_time_us = 0;
  3006. ktime_t cur_time;
  3007. sde_enc = to_sde_encoder_virt(drm_enc);
  3008. if (!sde_enc || !sde_enc->cur_master) {
  3009. SDE_ERROR("invalid sde encoder/master\n");
  3010. return -EINVAL;
  3011. }
  3012. mode = &sde_enc->cur_master->cached_mode;
  3013. mdp_transfer_time_us = sde_enc->mode_info.mdp_transfer_time_us;
  3014. vtotal = mode->vtotal;
  3015. if (!mdp_transfer_time_us) {
  3016. /* mdp_transfer_time set to 0 for video mode */
  3017. line_time = (1000000 / sde_enc->mode_info.frame_rate) / vtotal;
  3018. } else {
  3019. line_time = mdp_transfer_time_us / vtotal;
  3020. threshold_time_us = ((1000000 / sde_enc->mode_info.frame_rate)
  3021. - mdp_transfer_time_us);
  3022. }
  3023. if (!sde_enc->cur_master->ops.get_line_count) {
  3024. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3025. return -EINVAL;
  3026. }
  3027. cur_line = sde_enc->cur_master->ops.get_line_count(sde_enc->cur_master);
  3028. lines_left = (cur_line >= vtotal) ? vtotal : (vtotal - cur_line);
  3029. time_to_vsync_us = line_time * lines_left;
  3030. if (!time_to_vsync_us) {
  3031. SDE_ERROR("time to vsync should not be zero, vtotal=%d\n",
  3032. vtotal);
  3033. return -EINVAL;
  3034. }
  3035. cur_time = ktime_get();
  3036. *wakeup_time = ktime_add_us(cur_time, time_to_vsync_us);
  3037. if (threshold_time_us)
  3038. *wakeup_time = ktime_add_us(*wakeup_time, threshold_time_us);
  3039. SDE_DEBUG_ENC(sde_enc,
  3040. "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
  3041. cur_line, vtotal, time_to_vsync_us,
  3042. ktime_to_ms(cur_time),
  3043. ktime_to_ms(*wakeup_time));
  3044. return 0;
  3045. }
  3046. static void sde_encoder_vsync_event_handler(struct timer_list *t)
  3047. {
  3048. struct drm_encoder *drm_enc;
  3049. struct sde_encoder_virt *sde_enc =
  3050. from_timer(sde_enc, t, vsync_event_timer);
  3051. struct msm_drm_private *priv;
  3052. struct msm_drm_thread *event_thread;
  3053. if (!sde_enc || !sde_enc->crtc) {
  3054. SDE_ERROR("invalid encoder parameters %d\n", !sde_enc);
  3055. return;
  3056. }
  3057. drm_enc = &sde_enc->base;
  3058. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  3059. SDE_ERROR("invalid encoder parameters\n");
  3060. return;
  3061. }
  3062. priv = drm_enc->dev->dev_private;
  3063. if (sde_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
  3064. SDE_ERROR("invalid crtc index:%u\n",
  3065. sde_enc->crtc->index);
  3066. return;
  3067. }
  3068. event_thread = &priv->event_thread[sde_enc->crtc->index];
  3069. if (!event_thread) {
  3070. SDE_ERROR("event_thread not found for crtc:%d\n",
  3071. sde_enc->crtc->index);
  3072. return;
  3073. }
  3074. kthread_queue_work(&event_thread->worker,
  3075. &sde_enc->vsync_event_work);
  3076. }
  3077. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3078. {
  3079. struct sde_encoder_virt *sde_enc = container_of(work,
  3080. struct sde_encoder_virt, esd_trigger_work);
  3081. if (!sde_enc) {
  3082. SDE_ERROR("invalid sde encoder\n");
  3083. return;
  3084. }
  3085. sde_encoder_resource_control(&sde_enc->base,
  3086. SDE_ENC_RC_EVENT_KICKOFF);
  3087. }
  3088. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3089. {
  3090. struct sde_encoder_virt *sde_enc = container_of(work,
  3091. struct sde_encoder_virt, input_event_work);
  3092. if (!sde_enc) {
  3093. SDE_ERROR("invalid sde encoder\n");
  3094. return;
  3095. }
  3096. sde_encoder_resource_control(&sde_enc->base,
  3097. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3098. }
  3099. static void sde_encoder_vsync_event_work_handler(struct kthread_work *work)
  3100. {
  3101. struct sde_encoder_virt *sde_enc = container_of(work,
  3102. struct sde_encoder_virt, vsync_event_work);
  3103. bool autorefresh_enabled = false;
  3104. int rc = 0;
  3105. ktime_t wakeup_time;
  3106. struct drm_encoder *drm_enc;
  3107. if (!sde_enc) {
  3108. SDE_ERROR("invalid sde encoder\n");
  3109. return;
  3110. }
  3111. drm_enc = &sde_enc->base;
  3112. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3113. if (rc < 0) {
  3114. SDE_ERROR_ENC(sde_enc, "sde enc power enabled failed:%d\n", rc);
  3115. return;
  3116. }
  3117. if (sde_enc->cur_master &&
  3118. sde_enc->cur_master->ops.is_autorefresh_enabled)
  3119. autorefresh_enabled =
  3120. sde_enc->cur_master->ops.is_autorefresh_enabled(
  3121. sde_enc->cur_master);
  3122. /* Update timer if autorefresh is enabled else return */
  3123. if (!autorefresh_enabled)
  3124. goto exit;
  3125. rc = _sde_encoder_wakeup_time(&sde_enc->base, &wakeup_time);
  3126. if (rc)
  3127. goto exit;
  3128. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3129. mod_timer(&sde_enc->vsync_event_timer,
  3130. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3131. exit:
  3132. pm_runtime_put_sync(drm_enc->dev->dev);
  3133. }
  3134. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3135. {
  3136. static const uint64_t timeout_us = 50000;
  3137. static const uint64_t sleep_us = 20;
  3138. struct sde_encoder_virt *sde_enc;
  3139. ktime_t cur_ktime, exp_ktime;
  3140. uint32_t line_count, tmp, i;
  3141. if (!drm_enc) {
  3142. SDE_ERROR("invalid encoder\n");
  3143. return -EINVAL;
  3144. }
  3145. sde_enc = to_sde_encoder_virt(drm_enc);
  3146. if (!sde_enc->cur_master ||
  3147. !sde_enc->cur_master->ops.get_line_count) {
  3148. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3149. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3150. return -EINVAL;
  3151. }
  3152. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3153. line_count = sde_enc->cur_master->ops.get_line_count(
  3154. sde_enc->cur_master);
  3155. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3156. tmp = line_count;
  3157. line_count = sde_enc->cur_master->ops.get_line_count(
  3158. sde_enc->cur_master);
  3159. if (line_count < tmp) {
  3160. SDE_EVT32(DRMID(drm_enc), line_count);
  3161. return 0;
  3162. }
  3163. cur_ktime = ktime_get();
  3164. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3165. break;
  3166. usleep_range(sleep_us / 2, sleep_us);
  3167. }
  3168. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3169. return -ETIMEDOUT;
  3170. }
  3171. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3172. {
  3173. struct drm_encoder *drm_enc;
  3174. struct sde_rm_hw_iter rm_iter;
  3175. bool lm_valid = false;
  3176. bool intf_valid = false;
  3177. if (!phys_enc || !phys_enc->parent) {
  3178. SDE_ERROR("invalid encoder\n");
  3179. return -EINVAL;
  3180. }
  3181. drm_enc = phys_enc->parent;
  3182. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3183. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3184. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3185. phys_enc->has_intf_te)) {
  3186. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3187. SDE_HW_BLK_INTF);
  3188. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3189. struct sde_hw_intf *hw_intf =
  3190. (struct sde_hw_intf *)rm_iter.hw;
  3191. if (!hw_intf)
  3192. continue;
  3193. if (phys_enc->hw_ctl->ops.update_bitmask)
  3194. phys_enc->hw_ctl->ops.update_bitmask(
  3195. phys_enc->hw_ctl,
  3196. SDE_HW_FLUSH_INTF,
  3197. hw_intf->idx, 1);
  3198. intf_valid = true;
  3199. }
  3200. if (!intf_valid) {
  3201. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3202. "intf not found to flush\n");
  3203. return -EFAULT;
  3204. }
  3205. } else {
  3206. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3207. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3208. struct sde_hw_mixer *hw_lm =
  3209. (struct sde_hw_mixer *)rm_iter.hw;
  3210. if (!hw_lm)
  3211. continue;
  3212. /* update LM flush for HW without INTF TE */
  3213. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3214. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3215. phys_enc->hw_ctl,
  3216. hw_lm->idx, 1);
  3217. lm_valid = true;
  3218. }
  3219. if (!lm_valid) {
  3220. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3221. "lm not found to flush\n");
  3222. return -EFAULT;
  3223. }
  3224. }
  3225. return 0;
  3226. }
  3227. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3228. struct sde_encoder_virt *sde_enc)
  3229. {
  3230. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3231. struct sde_hw_mdp *mdptop = NULL;
  3232. sde_enc->dynamic_hdr_updated = false;
  3233. if (sde_enc->cur_master) {
  3234. mdptop = sde_enc->cur_master->hw_mdptop;
  3235. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3236. sde_enc->cur_master->connector);
  3237. }
  3238. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3239. return;
  3240. if (mdptop->ops.set_hdr_plus_metadata) {
  3241. sde_enc->dynamic_hdr_updated = true;
  3242. mdptop->ops.set_hdr_plus_metadata(
  3243. mdptop, dhdr_meta->dynamic_hdr_payload,
  3244. dhdr_meta->dynamic_hdr_payload_size,
  3245. sde_enc->cur_master->intf_idx == INTF_0 ?
  3246. 0 : 1);
  3247. }
  3248. }
  3249. void sde_encoder_needs_hw_reset(struct drm_encoder *drm_enc)
  3250. {
  3251. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3252. struct sde_encoder_phys *phys;
  3253. int i;
  3254. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3255. phys = sde_enc->phys_encs[i];
  3256. if (phys && phys->ops.hw_reset)
  3257. phys->ops.hw_reset(phys);
  3258. }
  3259. }
  3260. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3261. struct sde_encoder_kickoff_params *params)
  3262. {
  3263. struct sde_encoder_virt *sde_enc;
  3264. struct sde_encoder_phys *phys;
  3265. struct sde_kms *sde_kms = NULL;
  3266. struct sde_crtc *sde_crtc;
  3267. bool needs_hw_reset = false, is_cmd_mode;
  3268. int i, rc, ret = 0;
  3269. struct msm_display_info *disp_info;
  3270. if (!drm_enc || !params || !drm_enc->dev ||
  3271. !drm_enc->dev->dev_private) {
  3272. SDE_ERROR("invalid args\n");
  3273. return -EINVAL;
  3274. }
  3275. sde_enc = to_sde_encoder_virt(drm_enc);
  3276. sde_kms = sde_encoder_get_kms(drm_enc);
  3277. if (!sde_kms)
  3278. return -EINVAL;
  3279. disp_info = &sde_enc->disp_info;
  3280. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3281. SDE_DEBUG_ENC(sde_enc, "\n");
  3282. SDE_EVT32(DRMID(drm_enc));
  3283. is_cmd_mode = sde_encoder_check_curr_mode(drm_enc,
  3284. MSM_DISPLAY_CMD_MODE);
  3285. if (sde_enc->cur_master && sde_enc->cur_master->connector
  3286. && is_cmd_mode)
  3287. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3288. sde_enc->cur_master->connector->state,
  3289. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3290. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3291. /* prepare for next kickoff, may include waiting on previous kickoff */
  3292. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3293. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3294. phys = sde_enc->phys_encs[i];
  3295. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3296. params->recovery_events_enabled =
  3297. sde_enc->recovery_events_enabled;
  3298. if (phys) {
  3299. if (phys->ops.prepare_for_kickoff) {
  3300. rc = phys->ops.prepare_for_kickoff(
  3301. phys, params);
  3302. if (rc)
  3303. ret = rc;
  3304. }
  3305. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3306. needs_hw_reset = true;
  3307. _sde_encoder_setup_dither(phys);
  3308. if (sde_enc->cur_master &&
  3309. sde_connector_is_qsync_updated(
  3310. sde_enc->cur_master->connector)) {
  3311. _helper_flush_qsync(phys);
  3312. }
  3313. }
  3314. }
  3315. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3316. if (rc) {
  3317. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3318. ret = rc;
  3319. goto end;
  3320. }
  3321. /* if any phys needs reset, reset all phys, in-order */
  3322. if (needs_hw_reset)
  3323. sde_encoder_needs_hw_reset(drm_enc);
  3324. _sde_encoder_update_master(drm_enc, params);
  3325. _sde_encoder_update_roi(drm_enc);
  3326. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3327. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3328. if (rc) {
  3329. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3330. sde_enc->cur_master->connector->base.id,
  3331. rc);
  3332. ret = rc;
  3333. }
  3334. }
  3335. if (sde_enc->cur_master &&
  3336. ((is_cmd_mode && sde_enc->cur_master->cont_splash_enabled) ||
  3337. !sde_enc->cur_master->cont_splash_enabled)) {
  3338. rc = sde_encoder_dce_setup(sde_enc, params);
  3339. if (rc) {
  3340. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3341. ret = rc;
  3342. }
  3343. }
  3344. sde_encoder_dce_flush(sde_enc);
  3345. if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)
  3346. sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,
  3347. sde_enc->cur_master, sde_kms->qdss_enabled);
  3348. end:
  3349. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3350. return ret;
  3351. }
  3352. /**
  3353. * _sde_encoder_reset_ctl_hw - reset h/w configuration for all ctl's associated
  3354. * with the specified encoder, and unstage all pipes from it
  3355. * @encoder: encoder pointer
  3356. * Returns: 0 on success
  3357. */
  3358. static int _sde_encoder_reset_ctl_hw(struct drm_encoder *drm_enc)
  3359. {
  3360. struct sde_encoder_virt *sde_enc;
  3361. struct sde_encoder_phys *phys;
  3362. unsigned int i;
  3363. int rc = 0;
  3364. if (!drm_enc) {
  3365. SDE_ERROR("invalid encoder\n");
  3366. return -EINVAL;
  3367. }
  3368. sde_enc = to_sde_encoder_virt(drm_enc);
  3369. SDE_ATRACE_BEGIN("encoder_release_lm");
  3370. SDE_DEBUG_ENC(sde_enc, "\n");
  3371. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3372. phys = sde_enc->phys_encs[i];
  3373. if (!phys)
  3374. continue;
  3375. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0);
  3376. rc = sde_encoder_helper_reset_mixers(phys, NULL);
  3377. if (rc)
  3378. SDE_EVT32(DRMID(drm_enc), rc, SDE_EVTLOG_ERROR);
  3379. }
  3380. SDE_ATRACE_END("encoder_release_lm");
  3381. return rc;
  3382. }
  3383. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error)
  3384. {
  3385. struct sde_encoder_virt *sde_enc;
  3386. struct sde_encoder_phys *phys;
  3387. ktime_t wakeup_time;
  3388. unsigned int i;
  3389. if (!drm_enc) {
  3390. SDE_ERROR("invalid encoder\n");
  3391. return;
  3392. }
  3393. SDE_ATRACE_BEGIN("encoder_kickoff");
  3394. sde_enc = to_sde_encoder_virt(drm_enc);
  3395. SDE_DEBUG_ENC(sde_enc, "\n");
  3396. /* create a 'no pipes' commit to release buffers on errors */
  3397. if (is_error)
  3398. _sde_encoder_reset_ctl_hw(drm_enc);
  3399. /* All phys encs are ready to go, trigger the kickoff */
  3400. _sde_encoder_kickoff_phys(sde_enc);
  3401. /* allow phys encs to handle any post-kickoff business */
  3402. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3403. phys = sde_enc->phys_encs[i];
  3404. if (phys && phys->ops.handle_post_kickoff)
  3405. phys->ops.handle_post_kickoff(phys);
  3406. }
  3407. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI &&
  3408. !_sde_encoder_wakeup_time(drm_enc, &wakeup_time)) {
  3409. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3410. mod_timer(&sde_enc->vsync_event_timer,
  3411. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3412. }
  3413. SDE_ATRACE_END("encoder_kickoff");
  3414. }
  3415. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3416. struct sde_hw_pp_vsync_info *info)
  3417. {
  3418. struct sde_encoder_virt *sde_enc;
  3419. struct sde_encoder_phys *phys;
  3420. int i, ret;
  3421. if (!drm_enc || !info)
  3422. return;
  3423. sde_enc = to_sde_encoder_virt(drm_enc);
  3424. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3425. phys = sde_enc->phys_encs[i];
  3426. if (phys && phys->hw_intf && phys->hw_pp
  3427. && phys->hw_intf->ops.get_vsync_info) {
  3428. ret = phys->hw_intf->ops.get_vsync_info(
  3429. phys->hw_intf, &info[i]);
  3430. if (!ret) {
  3431. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  3432. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  3433. }
  3434. }
  3435. }
  3436. }
  3437. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  3438. struct drm_framebuffer *fb)
  3439. {
  3440. struct drm_encoder *drm_enc;
  3441. struct sde_hw_mixer_cfg mixer;
  3442. struct sde_rm_hw_iter lm_iter;
  3443. bool lm_valid = false;
  3444. if (!phys_enc || !phys_enc->parent) {
  3445. SDE_ERROR("invalid encoder\n");
  3446. return -EINVAL;
  3447. }
  3448. drm_enc = phys_enc->parent;
  3449. memset(&mixer, 0, sizeof(mixer));
  3450. /* reset associated CTL/LMs */
  3451. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  3452. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  3453. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3454. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  3455. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  3456. if (!hw_lm)
  3457. continue;
  3458. /* need to flush LM to remove it */
  3459. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3460. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3461. phys_enc->hw_ctl,
  3462. hw_lm->idx, 1);
  3463. if (fb) {
  3464. /* assume a single LM if targeting a frame buffer */
  3465. if (lm_valid)
  3466. continue;
  3467. mixer.out_height = fb->height;
  3468. mixer.out_width = fb->width;
  3469. if (hw_lm->ops.setup_mixer_out)
  3470. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  3471. }
  3472. lm_valid = true;
  3473. /* only enable border color on LM */
  3474. if (phys_enc->hw_ctl->ops.setup_blendstage)
  3475. phys_enc->hw_ctl->ops.setup_blendstage(
  3476. phys_enc->hw_ctl, hw_lm->idx, NULL, NULL);
  3477. }
  3478. if (!lm_valid) {
  3479. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  3480. return -EFAULT;
  3481. }
  3482. return 0;
  3483. }
  3484. int sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  3485. {
  3486. struct sde_encoder_virt *sde_enc;
  3487. struct sde_encoder_phys *phys;
  3488. int i, rc = 0, ret = 0;
  3489. struct sde_hw_ctl *ctl;
  3490. if (!drm_enc) {
  3491. SDE_ERROR("invalid encoder\n");
  3492. return -EINVAL;
  3493. }
  3494. sde_enc = to_sde_encoder_virt(drm_enc);
  3495. /* update the qsync parameters for the current frame */
  3496. if (sde_enc->cur_master)
  3497. sde_connector_set_qsync_params(
  3498. sde_enc->cur_master->connector);
  3499. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3500. phys = sde_enc->phys_encs[i];
  3501. if (phys && phys->ops.prepare_commit)
  3502. phys->ops.prepare_commit(phys);
  3503. if (phys && phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3504. ret = -ETIMEDOUT;
  3505. if (phys && phys->hw_ctl) {
  3506. ctl = phys->hw_ctl;
  3507. /*
  3508. * avoid clearing the pending flush during the first
  3509. * frame update after idle power collpase as the
  3510. * restore path would have updated the pending flush
  3511. */
  3512. if (!sde_enc->idle_pc_restore &&
  3513. ctl->ops.clear_pending_flush)
  3514. ctl->ops.clear_pending_flush(ctl);
  3515. }
  3516. }
  3517. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3518. rc = sde_connector_prepare_commit(
  3519. sde_enc->cur_master->connector);
  3520. if (rc)
  3521. SDE_ERROR_ENC(sde_enc,
  3522. "prepare commit failed conn %d rc %d\n",
  3523. sde_enc->cur_master->connector->base.id,
  3524. rc);
  3525. }
  3526. return ret;
  3527. }
  3528. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  3529. bool enable, u32 frame_count)
  3530. {
  3531. if (!phys_enc)
  3532. return;
  3533. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  3534. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  3535. enable, frame_count);
  3536. }
  3537. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  3538. bool nonblock, u32 *misr_value)
  3539. {
  3540. if (!phys_enc)
  3541. return -EINVAL;
  3542. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  3543. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  3544. nonblock, misr_value) : -ENOTSUPP;
  3545. }
  3546. #ifdef CONFIG_DEBUG_FS
  3547. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  3548. {
  3549. struct sde_encoder_virt *sde_enc;
  3550. int i;
  3551. if (!s || !s->private)
  3552. return -EINVAL;
  3553. sde_enc = s->private;
  3554. mutex_lock(&sde_enc->enc_lock);
  3555. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3556. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3557. if (!phys)
  3558. continue;
  3559. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  3560. phys->intf_idx - INTF_0,
  3561. atomic_read(&phys->vsync_cnt),
  3562. atomic_read(&phys->underrun_cnt));
  3563. switch (phys->intf_mode) {
  3564. case INTF_MODE_VIDEO:
  3565. seq_puts(s, "mode: video\n");
  3566. break;
  3567. case INTF_MODE_CMD:
  3568. seq_puts(s, "mode: command\n");
  3569. break;
  3570. case INTF_MODE_WB_BLOCK:
  3571. seq_puts(s, "mode: wb block\n");
  3572. break;
  3573. case INTF_MODE_WB_LINE:
  3574. seq_puts(s, "mode: wb line\n");
  3575. break;
  3576. default:
  3577. seq_puts(s, "mode: ???\n");
  3578. break;
  3579. }
  3580. }
  3581. mutex_unlock(&sde_enc->enc_lock);
  3582. return 0;
  3583. }
  3584. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  3585. struct file *file)
  3586. {
  3587. return single_open(file, _sde_encoder_status_show, inode->i_private);
  3588. }
  3589. static ssize_t _sde_encoder_misr_setup(struct file *file,
  3590. const char __user *user_buf, size_t count, loff_t *ppos)
  3591. {
  3592. struct sde_encoder_virt *sde_enc;
  3593. int rc;
  3594. char buf[MISR_BUFF_SIZE + 1];
  3595. size_t buff_copy;
  3596. u32 frame_count, enable;
  3597. struct sde_kms *sde_kms = NULL;
  3598. struct drm_encoder *drm_enc;
  3599. if (!file || !file->private_data)
  3600. return -EINVAL;
  3601. sde_enc = file->private_data;
  3602. if (!sde_enc)
  3603. return -EINVAL;
  3604. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3605. if (!sde_kms)
  3606. return -EINVAL;
  3607. drm_enc = &sde_enc->base;
  3608. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3609. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  3610. return -ENOTSUPP;
  3611. }
  3612. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  3613. if (copy_from_user(buf, user_buf, buff_copy))
  3614. return -EINVAL;
  3615. buf[buff_copy] = 0; /* end of string */
  3616. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  3617. return -EINVAL;
  3618. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3619. if (rc < 0)
  3620. return rc;
  3621. sde_enc->misr_enable = enable;
  3622. sde_enc->misr_frame_count = frame_count;
  3623. sde_encoder_misr_configure(&sde_enc->base, enable, frame_count);
  3624. pm_runtime_put_sync(drm_enc->dev->dev);
  3625. return count;
  3626. }
  3627. static ssize_t _sde_encoder_misr_read(struct file *file,
  3628. char __user *user_buff, size_t count, loff_t *ppos)
  3629. {
  3630. struct sde_encoder_virt *sde_enc;
  3631. struct sde_kms *sde_kms = NULL;
  3632. struct drm_encoder *drm_enc;
  3633. int i = 0, len = 0;
  3634. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  3635. int rc;
  3636. if (*ppos)
  3637. return 0;
  3638. if (!file || !file->private_data)
  3639. return -EINVAL;
  3640. sde_enc = file->private_data;
  3641. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3642. if (!sde_kms)
  3643. return -EINVAL;
  3644. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3645. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  3646. return -ENOTSUPP;
  3647. }
  3648. drm_enc = &sde_enc->base;
  3649. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3650. if (rc < 0)
  3651. return rc;
  3652. if (!sde_enc->misr_enable) {
  3653. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3654. "disabled\n");
  3655. goto buff_check;
  3656. }
  3657. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3658. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3659. u32 misr_value = 0;
  3660. if (!phys || !phys->ops.collect_misr) {
  3661. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3662. "invalid\n");
  3663. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  3664. continue;
  3665. }
  3666. rc = phys->ops.collect_misr(phys, false, &misr_value);
  3667. if (rc) {
  3668. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3669. "invalid\n");
  3670. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  3671. rc);
  3672. continue;
  3673. } else {
  3674. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3675. "Intf idx:%d\n",
  3676. phys->intf_idx - INTF_0);
  3677. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3678. "0x%x\n", misr_value);
  3679. }
  3680. }
  3681. buff_check:
  3682. if (count <= len) {
  3683. len = 0;
  3684. goto end;
  3685. }
  3686. if (copy_to_user(user_buff, buf, len)) {
  3687. len = -EFAULT;
  3688. goto end;
  3689. }
  3690. *ppos += len; /* increase offset */
  3691. end:
  3692. pm_runtime_put_sync(drm_enc->dev->dev);
  3693. return len;
  3694. }
  3695. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3696. {
  3697. struct sde_encoder_virt *sde_enc;
  3698. struct sde_kms *sde_kms;
  3699. int i;
  3700. static const struct file_operations debugfs_status_fops = {
  3701. .open = _sde_encoder_debugfs_status_open,
  3702. .read = seq_read,
  3703. .llseek = seq_lseek,
  3704. .release = single_release,
  3705. };
  3706. static const struct file_operations debugfs_misr_fops = {
  3707. .open = simple_open,
  3708. .read = _sde_encoder_misr_read,
  3709. .write = _sde_encoder_misr_setup,
  3710. };
  3711. char name[SDE_NAME_SIZE];
  3712. if (!drm_enc) {
  3713. SDE_ERROR("invalid encoder\n");
  3714. return -EINVAL;
  3715. }
  3716. sde_enc = to_sde_encoder_virt(drm_enc);
  3717. sde_kms = sde_encoder_get_kms(drm_enc);
  3718. if (!sde_kms) {
  3719. SDE_ERROR("invalid sde_kms\n");
  3720. return -EINVAL;
  3721. }
  3722. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  3723. /* create overall sub-directory for the encoder */
  3724. sde_enc->debugfs_root = debugfs_create_dir(name,
  3725. drm_enc->dev->primary->debugfs_root);
  3726. if (!sde_enc->debugfs_root)
  3727. return -ENOMEM;
  3728. /* don't error check these */
  3729. debugfs_create_file("status", 0400,
  3730. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  3731. debugfs_create_file("misr_data", 0600,
  3732. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  3733. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  3734. &sde_enc->idle_pc_enabled);
  3735. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  3736. &sde_enc->frame_trigger_mode);
  3737. for (i = 0; i < sde_enc->num_phys_encs; i++)
  3738. if (sde_enc->phys_encs[i] &&
  3739. sde_enc->phys_encs[i]->ops.late_register)
  3740. sde_enc->phys_encs[i]->ops.late_register(
  3741. sde_enc->phys_encs[i],
  3742. sde_enc->debugfs_root);
  3743. return 0;
  3744. }
  3745. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3746. {
  3747. struct sde_encoder_virt *sde_enc;
  3748. if (!drm_enc)
  3749. return;
  3750. sde_enc = to_sde_encoder_virt(drm_enc);
  3751. debugfs_remove_recursive(sde_enc->debugfs_root);
  3752. }
  3753. #else
  3754. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3755. {
  3756. return 0;
  3757. }
  3758. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3759. {
  3760. }
  3761. #endif
  3762. static int sde_encoder_late_register(struct drm_encoder *encoder)
  3763. {
  3764. return _sde_encoder_init_debugfs(encoder);
  3765. }
  3766. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  3767. {
  3768. _sde_encoder_destroy_debugfs(encoder);
  3769. }
  3770. static int sde_encoder_virt_add_phys_encs(
  3771. struct msm_display_info *disp_info,
  3772. struct sde_encoder_virt *sde_enc,
  3773. struct sde_enc_phys_init_params *params)
  3774. {
  3775. struct sde_encoder_phys *enc = NULL;
  3776. u32 display_caps = disp_info->capabilities;
  3777. SDE_DEBUG_ENC(sde_enc, "\n");
  3778. /*
  3779. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  3780. * in this function, check up-front.
  3781. */
  3782. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  3783. ARRAY_SIZE(sde_enc->phys_encs)) {
  3784. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3785. sde_enc->num_phys_encs);
  3786. return -EINVAL;
  3787. }
  3788. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  3789. enc = sde_encoder_phys_vid_init(params);
  3790. if (IS_ERR_OR_NULL(enc)) {
  3791. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  3792. PTR_ERR(enc));
  3793. return !enc ? -EINVAL : PTR_ERR(enc);
  3794. }
  3795. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  3796. }
  3797. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  3798. enc = sde_encoder_phys_cmd_init(params);
  3799. if (IS_ERR_OR_NULL(enc)) {
  3800. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  3801. PTR_ERR(enc));
  3802. return !enc ? -EINVAL : PTR_ERR(enc);
  3803. }
  3804. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  3805. }
  3806. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  3807. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3808. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  3809. else
  3810. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3811. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  3812. ++sde_enc->num_phys_encs;
  3813. return 0;
  3814. }
  3815. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  3816. struct sde_enc_phys_init_params *params)
  3817. {
  3818. struct sde_encoder_phys *enc = NULL;
  3819. if (!sde_enc) {
  3820. SDE_ERROR("invalid encoder\n");
  3821. return -EINVAL;
  3822. }
  3823. SDE_DEBUG_ENC(sde_enc, "\n");
  3824. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  3825. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3826. sde_enc->num_phys_encs);
  3827. return -EINVAL;
  3828. }
  3829. enc = sde_encoder_phys_wb_init(params);
  3830. if (IS_ERR_OR_NULL(enc)) {
  3831. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  3832. PTR_ERR(enc));
  3833. return !enc ? -EINVAL : PTR_ERR(enc);
  3834. }
  3835. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  3836. ++sde_enc->num_phys_encs;
  3837. return 0;
  3838. }
  3839. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  3840. struct sde_kms *sde_kms,
  3841. struct msm_display_info *disp_info,
  3842. int *drm_enc_mode)
  3843. {
  3844. int ret = 0;
  3845. int i = 0;
  3846. enum sde_intf_type intf_type;
  3847. struct sde_encoder_virt_ops parent_ops = {
  3848. sde_encoder_vblank_callback,
  3849. sde_encoder_underrun_callback,
  3850. sde_encoder_frame_done_callback,
  3851. sde_encoder_get_qsync_fps_callback,
  3852. };
  3853. struct sde_enc_phys_init_params phys_params;
  3854. if (!sde_enc || !sde_kms) {
  3855. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  3856. !sde_enc, !sde_kms);
  3857. return -EINVAL;
  3858. }
  3859. memset(&phys_params, 0, sizeof(phys_params));
  3860. phys_params.sde_kms = sde_kms;
  3861. phys_params.parent = &sde_enc->base;
  3862. phys_params.parent_ops = parent_ops;
  3863. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  3864. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  3865. SDE_DEBUG("\n");
  3866. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  3867. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  3868. intf_type = INTF_DSI;
  3869. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  3870. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3871. intf_type = INTF_HDMI;
  3872. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  3873. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  3874. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  3875. else
  3876. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3877. intf_type = INTF_DP;
  3878. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  3879. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  3880. intf_type = INTF_WB;
  3881. } else {
  3882. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  3883. return -EINVAL;
  3884. }
  3885. WARN_ON(disp_info->num_of_h_tiles < 1);
  3886. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  3887. sde_enc->te_source = disp_info->te_source;
  3888. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  3889. if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
  3890. (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
  3891. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  3892. mutex_lock(&sde_enc->enc_lock);
  3893. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  3894. /*
  3895. * Left-most tile is at index 0, content is controller id
  3896. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  3897. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  3898. */
  3899. u32 controller_id = disp_info->h_tile_instance[i];
  3900. if (disp_info->num_of_h_tiles > 1) {
  3901. if (i == 0)
  3902. phys_params.split_role = ENC_ROLE_MASTER;
  3903. else
  3904. phys_params.split_role = ENC_ROLE_SLAVE;
  3905. } else {
  3906. phys_params.split_role = ENC_ROLE_SOLO;
  3907. }
  3908. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  3909. i, controller_id, phys_params.split_role);
  3910. if (sde_enc->ops.phys_init) {
  3911. struct sde_encoder_phys *enc;
  3912. enc = sde_enc->ops.phys_init(intf_type,
  3913. controller_id,
  3914. &phys_params);
  3915. if (enc) {
  3916. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3917. enc;
  3918. ++sde_enc->num_phys_encs;
  3919. } else
  3920. SDE_ERROR_ENC(sde_enc,
  3921. "failed to add phys encs\n");
  3922. continue;
  3923. }
  3924. if (intf_type == INTF_WB) {
  3925. phys_params.intf_idx = INTF_MAX;
  3926. phys_params.wb_idx = sde_encoder_get_wb(
  3927. sde_kms->catalog,
  3928. intf_type, controller_id);
  3929. if (phys_params.wb_idx == WB_MAX) {
  3930. SDE_ERROR_ENC(sde_enc,
  3931. "could not get wb: type %d, id %d\n",
  3932. intf_type, controller_id);
  3933. ret = -EINVAL;
  3934. }
  3935. } else {
  3936. phys_params.wb_idx = WB_MAX;
  3937. phys_params.intf_idx = sde_encoder_get_intf(
  3938. sde_kms->catalog, intf_type,
  3939. controller_id);
  3940. if (phys_params.intf_idx == INTF_MAX) {
  3941. SDE_ERROR_ENC(sde_enc,
  3942. "could not get wb: type %d, id %d\n",
  3943. intf_type, controller_id);
  3944. ret = -EINVAL;
  3945. }
  3946. }
  3947. if (!ret) {
  3948. if (intf_type == INTF_WB)
  3949. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  3950. &phys_params);
  3951. else
  3952. ret = sde_encoder_virt_add_phys_encs(
  3953. disp_info,
  3954. sde_enc,
  3955. &phys_params);
  3956. if (ret)
  3957. SDE_ERROR_ENC(sde_enc,
  3958. "failed to add phys encs\n");
  3959. }
  3960. }
  3961. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3962. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  3963. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  3964. if (vid_phys) {
  3965. atomic_set(&vid_phys->vsync_cnt, 0);
  3966. atomic_set(&vid_phys->underrun_cnt, 0);
  3967. }
  3968. if (cmd_phys) {
  3969. atomic_set(&cmd_phys->vsync_cnt, 0);
  3970. atomic_set(&cmd_phys->underrun_cnt, 0);
  3971. }
  3972. }
  3973. mutex_unlock(&sde_enc->enc_lock);
  3974. return ret;
  3975. }
  3976. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  3977. .mode_set = sde_encoder_virt_mode_set,
  3978. .disable = sde_encoder_virt_disable,
  3979. .enable = sde_encoder_virt_enable,
  3980. .atomic_check = sde_encoder_virt_atomic_check,
  3981. };
  3982. static const struct drm_encoder_funcs sde_encoder_funcs = {
  3983. .destroy = sde_encoder_destroy,
  3984. .late_register = sde_encoder_late_register,
  3985. .early_unregister = sde_encoder_early_unregister,
  3986. };
  3987. struct drm_encoder *sde_encoder_init_with_ops(
  3988. struct drm_device *dev,
  3989. struct msm_display_info *disp_info,
  3990. const struct sde_encoder_ops *ops)
  3991. {
  3992. struct msm_drm_private *priv = dev->dev_private;
  3993. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  3994. struct drm_encoder *drm_enc = NULL;
  3995. struct sde_encoder_virt *sde_enc = NULL;
  3996. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  3997. char name[SDE_NAME_SIZE];
  3998. int ret = 0, i, intf_index = INTF_MAX;
  3999. struct sde_encoder_phys *phys = NULL;
  4000. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  4001. if (!sde_enc) {
  4002. ret = -ENOMEM;
  4003. goto fail;
  4004. }
  4005. if (ops)
  4006. sde_enc->ops = *ops;
  4007. mutex_init(&sde_enc->enc_lock);
  4008. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  4009. &drm_enc_mode);
  4010. if (ret)
  4011. goto fail;
  4012. sde_enc->cur_master = NULL;
  4013. spin_lock_init(&sde_enc->enc_spinlock);
  4014. mutex_init(&sde_enc->vblank_ctl_lock);
  4015. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  4016. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  4017. drm_enc = &sde_enc->base;
  4018. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  4019. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  4020. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI)
  4021. timer_setup(&sde_enc->vsync_event_timer,
  4022. sde_encoder_vsync_event_handler, 0);
  4023. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4024. phys = sde_enc->phys_encs[i];
  4025. if (!phys)
  4026. continue;
  4027. if (phys->ops.is_master && phys->ops.is_master(phys))
  4028. intf_index = phys->intf_idx - INTF_0;
  4029. }
  4030. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  4031. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  4032. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  4033. SDE_RSC_PRIMARY_DISP_CLIENT :
  4034. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  4035. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  4036. SDE_DEBUG("sde rsc client create failed :%ld\n",
  4037. PTR_ERR(sde_enc->rsc_client));
  4038. sde_enc->rsc_client = NULL;
  4039. }
  4040. if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
  4041. ret = _sde_encoder_input_handler(sde_enc);
  4042. if (ret)
  4043. SDE_ERROR(
  4044. "input handler registration failed, rc = %d\n", ret);
  4045. }
  4046. mutex_init(&sde_enc->rc_lock);
  4047. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  4048. sde_encoder_off_work);
  4049. sde_enc->vblank_enabled = false;
  4050. sde_enc->qdss_status = false;
  4051. kthread_init_work(&sde_enc->vsync_event_work,
  4052. sde_encoder_vsync_event_work_handler);
  4053. kthread_init_work(&sde_enc->input_event_work,
  4054. sde_encoder_input_event_work_handler);
  4055. kthread_init_work(&sde_enc->esd_trigger_work,
  4056. sde_encoder_esd_trigger_work_handler);
  4057. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  4058. SDE_DEBUG_ENC(sde_enc, "created\n");
  4059. return drm_enc;
  4060. fail:
  4061. SDE_ERROR("failed to create encoder\n");
  4062. if (drm_enc)
  4063. sde_encoder_destroy(drm_enc);
  4064. return ERR_PTR(ret);
  4065. }
  4066. struct drm_encoder *sde_encoder_init(
  4067. struct drm_device *dev,
  4068. struct msm_display_info *disp_info)
  4069. {
  4070. return sde_encoder_init_with_ops(dev, disp_info, NULL);
  4071. }
  4072. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  4073. enum msm_event_wait event)
  4074. {
  4075. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  4076. struct sde_encoder_virt *sde_enc = NULL;
  4077. int i, ret = 0;
  4078. char atrace_buf[32];
  4079. if (!drm_enc) {
  4080. SDE_ERROR("invalid encoder\n");
  4081. return -EINVAL;
  4082. }
  4083. sde_enc = to_sde_encoder_virt(drm_enc);
  4084. SDE_DEBUG_ENC(sde_enc, "\n");
  4085. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4086. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4087. switch (event) {
  4088. case MSM_ENC_COMMIT_DONE:
  4089. fn_wait = phys->ops.wait_for_commit_done;
  4090. break;
  4091. case MSM_ENC_TX_COMPLETE:
  4092. fn_wait = phys->ops.wait_for_tx_complete;
  4093. break;
  4094. case MSM_ENC_VBLANK:
  4095. fn_wait = phys->ops.wait_for_vblank;
  4096. break;
  4097. case MSM_ENC_ACTIVE_REGION:
  4098. fn_wait = phys->ops.wait_for_active;
  4099. break;
  4100. default:
  4101. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4102. event);
  4103. return -EINVAL;
  4104. }
  4105. if (phys && fn_wait) {
  4106. snprintf(atrace_buf, sizeof(atrace_buf),
  4107. "wait_completion_event_%d", event);
  4108. SDE_ATRACE_BEGIN(atrace_buf);
  4109. ret = fn_wait(phys);
  4110. SDE_ATRACE_END(atrace_buf);
  4111. if (ret)
  4112. return ret;
  4113. }
  4114. }
  4115. return ret;
  4116. }
  4117. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *drm_enc,
  4118. u64 *l_bound, u64 *u_bound)
  4119. {
  4120. struct sde_encoder_virt *sde_enc;
  4121. u64 jitter_ns, frametime_ns;
  4122. struct msm_mode_info *info;
  4123. if (!drm_enc) {
  4124. SDE_ERROR("invalid encoder\n");
  4125. return;
  4126. }
  4127. sde_enc = to_sde_encoder_virt(drm_enc);
  4128. info = &sde_enc->mode_info;
  4129. frametime_ns = (1 * 1000000000) / info->frame_rate;
  4130. jitter_ns = info->jitter_numer * frametime_ns;
  4131. do_div(jitter_ns, info->jitter_denom * 100);
  4132. *l_bound = frametime_ns - jitter_ns;
  4133. *u_bound = frametime_ns + jitter_ns;
  4134. }
  4135. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4136. {
  4137. struct sde_encoder_virt *sde_enc;
  4138. if (!drm_enc) {
  4139. SDE_ERROR("invalid encoder\n");
  4140. return 0;
  4141. }
  4142. sde_enc = to_sde_encoder_virt(drm_enc);
  4143. return sde_enc->mode_info.frame_rate;
  4144. }
  4145. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4146. {
  4147. struct sde_encoder_virt *sde_enc = NULL;
  4148. int i;
  4149. if (!encoder) {
  4150. SDE_ERROR("invalid encoder\n");
  4151. return INTF_MODE_NONE;
  4152. }
  4153. sde_enc = to_sde_encoder_virt(encoder);
  4154. if (sde_enc->cur_master)
  4155. return sde_enc->cur_master->intf_mode;
  4156. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4157. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4158. if (phys)
  4159. return phys->intf_mode;
  4160. }
  4161. return INTF_MODE_NONE;
  4162. }
  4163. static void _sde_encoder_cache_hw_res_cont_splash(
  4164. struct drm_encoder *encoder,
  4165. struct sde_kms *sde_kms)
  4166. {
  4167. int i, idx;
  4168. struct sde_encoder_virt *sde_enc;
  4169. struct sde_encoder_phys *phys_enc;
  4170. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4171. sde_enc = to_sde_encoder_virt(encoder);
  4172. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4173. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4174. sde_enc->hw_pp[i] = NULL;
  4175. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4176. break;
  4177. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4178. }
  4179. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4180. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4181. sde_enc->hw_dsc[i] = NULL;
  4182. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4183. break;
  4184. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4185. }
  4186. /*
  4187. * If we have multiple phys encoders with one controller, make
  4188. * sure to populate the controller pointer in both phys encoders.
  4189. */
  4190. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4191. phys_enc = sde_enc->phys_encs[idx];
  4192. phys_enc->hw_ctl = NULL;
  4193. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4194. SDE_HW_BLK_CTL);
  4195. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4196. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4197. phys_enc->hw_ctl =
  4198. (struct sde_hw_ctl *) ctl_iter.hw;
  4199. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4200. phys_enc->intf_idx, phys_enc->hw_ctl);
  4201. }
  4202. }
  4203. }
  4204. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4205. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4206. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4207. phys->hw_intf = NULL;
  4208. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4209. break;
  4210. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4211. }
  4212. }
  4213. /**
  4214. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4215. * device bootup when cont_splash is enabled
  4216. * @drm_enc: Pointer to drm encoder structure
  4217. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4218. * @enable: boolean indicates enable or displae state of splash
  4219. * @Return: true if successful in updating the encoder structure
  4220. */
  4221. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4222. struct sde_splash_display *splash_display, bool enable)
  4223. {
  4224. struct sde_encoder_virt *sde_enc;
  4225. struct msm_drm_private *priv;
  4226. struct sde_kms *sde_kms;
  4227. struct drm_connector *conn = NULL;
  4228. struct sde_connector *sde_conn = NULL;
  4229. struct sde_connector_state *sde_conn_state = NULL;
  4230. struct drm_display_mode *drm_mode = NULL;
  4231. struct sde_encoder_phys *phys_enc;
  4232. int ret = 0, i;
  4233. if (!encoder) {
  4234. SDE_ERROR("invalid drm enc\n");
  4235. return -EINVAL;
  4236. }
  4237. sde_enc = to_sde_encoder_virt(encoder);
  4238. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  4239. if (!sde_kms) {
  4240. SDE_ERROR("invalid sde_kms\n");
  4241. return -EINVAL;
  4242. }
  4243. priv = encoder->dev->dev_private;
  4244. if (!priv->num_connectors) {
  4245. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4246. return -EINVAL;
  4247. }
  4248. SDE_DEBUG_ENC(sde_enc,
  4249. "num of connectors: %d\n", priv->num_connectors);
  4250. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4251. if (!enable) {
  4252. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4253. phys_enc = sde_enc->phys_encs[i];
  4254. if (phys_enc)
  4255. phys_enc->cont_splash_enabled = false;
  4256. }
  4257. return ret;
  4258. }
  4259. if (!splash_display) {
  4260. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4261. return -EINVAL;
  4262. }
  4263. for (i = 0; i < priv->num_connectors; i++) {
  4264. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4265. priv->connectors[i]->base.id);
  4266. sde_conn = to_sde_connector(priv->connectors[i]);
  4267. if (!sde_conn->encoder) {
  4268. SDE_DEBUG_ENC(sde_enc,
  4269. "encoder not attached to connector\n");
  4270. continue;
  4271. }
  4272. if (sde_conn->encoder->base.id
  4273. == encoder->base.id) {
  4274. conn = (priv->connectors[i]);
  4275. break;
  4276. }
  4277. }
  4278. if (!conn || !conn->state) {
  4279. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4280. return -EINVAL;
  4281. }
  4282. sde_conn_state = to_sde_connector_state(conn->state);
  4283. if (!sde_conn->ops.get_mode_info) {
  4284. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4285. return -EINVAL;
  4286. }
  4287. ret = sde_connector_get_mode_info(&sde_conn->base,
  4288. &encoder->crtc->state->adjusted_mode,
  4289. &sde_conn_state->mode_info);
  4290. if (ret) {
  4291. SDE_ERROR_ENC(sde_enc,
  4292. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4293. return ret;
  4294. }
  4295. if (sde_conn->encoder) {
  4296. conn->state->best_encoder = sde_conn->encoder;
  4297. SDE_DEBUG_ENC(sde_enc,
  4298. "configured cstate->best_encoder to ID = %d\n",
  4299. conn->state->best_encoder->base.id);
  4300. } else {
  4301. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4302. conn->base.id);
  4303. }
  4304. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4305. conn->state, false);
  4306. if (ret) {
  4307. SDE_ERROR_ENC(sde_enc,
  4308. "failed to reserve hw resources, %d\n", ret);
  4309. return ret;
  4310. }
  4311. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4312. sde_connector_get_topology_name(conn));
  4313. drm_mode = &encoder->crtc->state->adjusted_mode;
  4314. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4315. drm_mode->hdisplay, drm_mode->vdisplay);
  4316. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4317. if (encoder->bridge) {
  4318. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4319. /*
  4320. * For cont-splash use case, we update the mode
  4321. * configurations manually. This will skip the
  4322. * usually mode set call when actual frame is
  4323. * pushed from framework. The bridge needs to
  4324. * be updated with the current drm mode by
  4325. * calling the bridge mode set ops.
  4326. */
  4327. if (encoder->bridge->funcs) {
  4328. SDE_DEBUG_ENC(sde_enc, "calling mode_set\n");
  4329. encoder->bridge->funcs->mode_set(encoder->bridge,
  4330. drm_mode, drm_mode);
  4331. }
  4332. } else {
  4333. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4334. }
  4335. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4336. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4337. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4338. if (!phys) {
  4339. SDE_ERROR_ENC(sde_enc,
  4340. "phys encoders not initialized\n");
  4341. return -EINVAL;
  4342. }
  4343. /* update connector for master and slave phys encoders */
  4344. phys->connector = conn;
  4345. phys->cont_splash_enabled = true;
  4346. phys->hw_pp = sde_enc->hw_pp[i];
  4347. if (phys->ops.cont_splash_mode_set)
  4348. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4349. if (phys->ops.is_master && phys->ops.is_master(phys))
  4350. sde_enc->cur_master = phys;
  4351. }
  4352. return ret;
  4353. }
  4354. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4355. bool skip_pre_kickoff)
  4356. {
  4357. struct msm_drm_thread *event_thread = NULL;
  4358. struct msm_drm_private *priv = NULL;
  4359. struct sde_encoder_virt *sde_enc = NULL;
  4360. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4361. SDE_ERROR("invalid parameters\n");
  4362. return -EINVAL;
  4363. }
  4364. priv = enc->dev->dev_private;
  4365. sde_enc = to_sde_encoder_virt(enc);
  4366. if (!sde_enc->crtc || (sde_enc->crtc->index
  4367. >= ARRAY_SIZE(priv->event_thread))) {
  4368. SDE_DEBUG_ENC(sde_enc,
  4369. "invalid cached CRTC: %d or crtc index: %d\n",
  4370. sde_enc->crtc == NULL,
  4371. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4372. return -EINVAL;
  4373. }
  4374. SDE_EVT32_VERBOSE(DRMID(enc));
  4375. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4376. if (!skip_pre_kickoff) {
  4377. kthread_queue_work(&event_thread->worker,
  4378. &sde_enc->esd_trigger_work);
  4379. kthread_flush_work(&sde_enc->esd_trigger_work);
  4380. }
  4381. /*
  4382. * panel may stop generating te signal (vsync) during esd failure. rsc
  4383. * hardware may hang without vsync. Avoid rsc hang by generating the
  4384. * vsync from watchdog timer instead of panel.
  4385. */
  4386. sde_encoder_helper_switch_vsync(enc, true);
  4387. if (!skip_pre_kickoff)
  4388. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4389. return 0;
  4390. }
  4391. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4392. {
  4393. struct sde_encoder_virt *sde_enc;
  4394. if (!encoder) {
  4395. SDE_ERROR("invalid drm enc\n");
  4396. return false;
  4397. }
  4398. sde_enc = to_sde_encoder_virt(encoder);
  4399. return sde_enc->recovery_events_enabled;
  4400. }
  4401. void sde_encoder_recovery_events_handler(struct drm_encoder *encoder,
  4402. bool enabled)
  4403. {
  4404. struct sde_encoder_virt *sde_enc;
  4405. if (!encoder) {
  4406. SDE_ERROR("invalid drm enc\n");
  4407. return;
  4408. }
  4409. sde_enc = to_sde_encoder_virt(encoder);
  4410. sde_enc->recovery_events_enabled = enabled;
  4411. }