sde_crtc.c 173 KB

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  1. /*
  2. * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/sort.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/ktime.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/drm_mode.h>
  24. #include <drm/drm_crtc.h>
  25. #include <drm/drm_probe_helper.h>
  26. #include <drm/drm_flip_work.h>
  27. #include "sde_kms.h"
  28. #include "sde_hw_lm.h"
  29. #include "sde_hw_ctl.h"
  30. #include "sde_crtc.h"
  31. #include "sde_plane.h"
  32. #include "sde_hw_util.h"
  33. #include "sde_hw_catalog.h"
  34. #include "sde_color_processing.h"
  35. #include "sde_encoder.h"
  36. #include "sde_connector.h"
  37. #include "sde_vbif.h"
  38. #include "sde_power_handle.h"
  39. #include "sde_core_perf.h"
  40. #include "sde_trace.h"
  41. #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4)
  42. #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2)
  43. struct sde_crtc_custom_events {
  44. u32 event;
  45. int (*func)(struct drm_crtc *crtc, bool en,
  46. struct sde_irq_callback *irq);
  47. };
  48. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  49. bool en, struct sde_irq_callback *ad_irq);
  50. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  51. bool en, struct sde_irq_callback *idle_irq);
  52. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  53. struct sde_irq_callback *noirq);
  54. static struct sde_crtc_custom_events custom_events[] = {
  55. {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt},
  56. {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler},
  57. {DRM_EVENT_IDLE_NOTIFY, sde_crtc_idle_interrupt_handler},
  58. {DRM_EVENT_HISTOGRAM, sde_cp_hist_interrupt},
  59. {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler},
  60. {DRM_EVENT_LTM_HIST, sde_cp_ltm_hist_interrupt},
  61. {DRM_EVENT_LTM_WB_PB, sde_cp_ltm_wb_pb_interrupt},
  62. {DRM_EVENT_LTM_OFF, sde_cp_ltm_off_event_handler},
  63. };
  64. /* default input fence timeout, in ms */
  65. #define SDE_CRTC_INPUT_FENCE_TIMEOUT 10000
  66. /*
  67. * The default input fence timeout is 2 seconds while max allowed
  68. * range is 10 seconds. Any value above 10 seconds adds glitches beyond
  69. * tolerance limit.
  70. */
  71. #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
  72. /* layer mixer index on sde_crtc */
  73. #define LEFT_MIXER 0
  74. #define RIGHT_MIXER 1
  75. #define MISR_BUFF_SIZE 256
  76. /*
  77. * Time period for fps calculation in micro seconds.
  78. * Default value is set to 1 sec.
  79. */
  80. #define DEFAULT_FPS_PERIOD_1_SEC 1000000
  81. #define MAX_FPS_PERIOD_5_SECONDS 5000000
  82. #define MAX_FRAME_COUNT 1000
  83. #define MILI_TO_MICRO 1000
  84. #define SKIP_STAGING_PIPE_ZPOS 255
  85. static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
  86. {
  87. struct msm_drm_private *priv;
  88. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  89. SDE_ERROR("invalid crtc\n");
  90. return NULL;
  91. }
  92. priv = crtc->dev->dev_private;
  93. if (!priv || !priv->kms) {
  94. SDE_ERROR("invalid kms\n");
  95. return NULL;
  96. }
  97. return to_sde_kms(priv->kms);
  98. }
  99. /**
  100. * sde_crtc_calc_fps() - Calculates fps value.
  101. * @sde_crtc : CRTC structure
  102. *
  103. * This function is called at frame done. It counts the number
  104. * of frames done for every 1 sec. Stores the value in measured_fps.
  105. * measured_fps value is 10 times the calculated fps value.
  106. * For example, measured_fps= 594 for calculated fps of 59.4
  107. */
  108. static void sde_crtc_calc_fps(struct sde_crtc *sde_crtc)
  109. {
  110. ktime_t current_time_us;
  111. u64 fps, diff_us;
  112. current_time_us = ktime_get();
  113. diff_us = (u64)ktime_us_delta(current_time_us,
  114. sde_crtc->fps_info.last_sampled_time_us);
  115. sde_crtc->fps_info.frame_count++;
  116. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  117. /* Multiplying with 10 to get fps in floating point */
  118. fps = ((u64)sde_crtc->fps_info.frame_count)
  119. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  120. do_div(fps, diff_us);
  121. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  122. SDE_DEBUG(" FPS for crtc%d is %d.%d\n",
  123. sde_crtc->base.base.id, (unsigned int)fps/10,
  124. (unsigned int)fps%10);
  125. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  126. sde_crtc->fps_info.frame_count = 0;
  127. }
  128. if (!sde_crtc->fps_info.time_buf)
  129. return;
  130. /**
  131. * Array indexing is based on sliding window algorithm.
  132. * sde_crtc->time_buf has a maximum capacity of MAX_FRAME_COUNT
  133. * time slots. As the count increases to MAX_FRAME_COUNT + 1, the
  134. * counter loops around and comes back to the first index to store
  135. * the next ktime.
  136. */
  137. sde_crtc->fps_info.time_buf[sde_crtc->fps_info.next_time_index++] =
  138. ktime_get();
  139. sde_crtc->fps_info.next_time_index %= MAX_FRAME_COUNT;
  140. }
  141. static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc)
  142. {
  143. if (!sde_crtc)
  144. return;
  145. }
  146. #ifdef CONFIG_DEBUG_FS
  147. static int _sde_debugfs_fps_status_show(struct seq_file *s, void *data)
  148. {
  149. struct sde_crtc *sde_crtc;
  150. u64 fps_int, fps_float;
  151. ktime_t current_time_us;
  152. u64 fps, diff_us;
  153. if (!s || !s->private) {
  154. SDE_ERROR("invalid input param(s)\n");
  155. return -EAGAIN;
  156. }
  157. sde_crtc = s->private;
  158. current_time_us = ktime_get();
  159. diff_us = (u64)ktime_us_delta(current_time_us,
  160. sde_crtc->fps_info.last_sampled_time_us);
  161. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  162. /* Multiplying with 10 to get fps in floating point */
  163. fps = ((u64)sde_crtc->fps_info.frame_count)
  164. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  165. do_div(fps, diff_us);
  166. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  167. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  168. sde_crtc->fps_info.frame_count = 0;
  169. SDE_DEBUG("Measured FPS for crtc%d is %d.%d\n",
  170. sde_crtc->base.base.id, (unsigned int)fps/10,
  171. (unsigned int)fps%10);
  172. }
  173. fps_int = (unsigned int) sde_crtc->fps_info.measured_fps;
  174. fps_float = do_div(fps_int, 10);
  175. seq_printf(s, "fps: %llu.%llu\n", fps_int, fps_float);
  176. return 0;
  177. }
  178. static int _sde_debugfs_fps_status(struct inode *inode, struct file *file)
  179. {
  180. return single_open(file, _sde_debugfs_fps_status_show,
  181. inode->i_private);
  182. }
  183. #endif
  184. static ssize_t fps_periodicity_ms_store(struct device *device,
  185. struct device_attribute *attr, const char *buf, size_t count)
  186. {
  187. struct drm_crtc *crtc;
  188. struct sde_crtc *sde_crtc;
  189. int res;
  190. /* Base of the input */
  191. int cnt = 10;
  192. if (!device || !buf) {
  193. SDE_ERROR("invalid input param(s)\n");
  194. return -EAGAIN;
  195. }
  196. crtc = dev_get_drvdata(device);
  197. if (!crtc)
  198. return -EINVAL;
  199. sde_crtc = to_sde_crtc(crtc);
  200. res = kstrtou32(buf, cnt, &sde_crtc->fps_info.fps_periodic_duration);
  201. if (res < 0)
  202. return res;
  203. if (sde_crtc->fps_info.fps_periodic_duration <= 0)
  204. sde_crtc->fps_info.fps_periodic_duration =
  205. DEFAULT_FPS_PERIOD_1_SEC;
  206. else if ((sde_crtc->fps_info.fps_periodic_duration) * MILI_TO_MICRO >
  207. MAX_FPS_PERIOD_5_SECONDS)
  208. sde_crtc->fps_info.fps_periodic_duration =
  209. MAX_FPS_PERIOD_5_SECONDS;
  210. else
  211. sde_crtc->fps_info.fps_periodic_duration *= MILI_TO_MICRO;
  212. return count;
  213. }
  214. static ssize_t fps_periodicity_ms_show(struct device *device,
  215. struct device_attribute *attr, char *buf)
  216. {
  217. struct drm_crtc *crtc;
  218. struct sde_crtc *sde_crtc;
  219. if (!device || !buf) {
  220. SDE_ERROR("invalid input param(s)\n");
  221. return -EAGAIN;
  222. }
  223. crtc = dev_get_drvdata(device);
  224. if (!crtc)
  225. return -EINVAL;
  226. sde_crtc = to_sde_crtc(crtc);
  227. return scnprintf(buf, PAGE_SIZE, "%d\n",
  228. (sde_crtc->fps_info.fps_periodic_duration)/MILI_TO_MICRO);
  229. }
  230. static ssize_t measured_fps_show(struct device *device,
  231. struct device_attribute *attr, char *buf)
  232. {
  233. struct drm_crtc *crtc;
  234. struct sde_crtc *sde_crtc;
  235. uint64_t fps_int, fps_decimal;
  236. u64 fps = 0, frame_count = 0;
  237. ktime_t current_time;
  238. int i = 0, current_time_index;
  239. u64 diff_us;
  240. if (!device || !buf) {
  241. SDE_ERROR("invalid input param(s)\n");
  242. return -EAGAIN;
  243. }
  244. crtc = dev_get_drvdata(device);
  245. if (!crtc) {
  246. scnprintf(buf, PAGE_SIZE, "fps information not available");
  247. return -EINVAL;
  248. }
  249. sde_crtc = to_sde_crtc(crtc);
  250. if (!sde_crtc->fps_info.time_buf) {
  251. scnprintf(buf, PAGE_SIZE,
  252. "timebuf null - fps information not available");
  253. return -EINVAL;
  254. }
  255. /**
  256. * Whenever the time_index counter comes to zero upon decrementing,
  257. * it is set to the last index since it is the next index that we
  258. * should check for calculating the buftime.
  259. */
  260. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  261. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  262. current_time = ktime_get();
  263. for (i = 0; i < MAX_FRAME_COUNT; i++) {
  264. u64 ptime = (u64)ktime_to_us(current_time);
  265. u64 buftime = (u64)ktime_to_us(
  266. sde_crtc->fps_info.time_buf[current_time_index]);
  267. diff_us = (u64)ktime_us_delta(current_time,
  268. sde_crtc->fps_info.time_buf[current_time_index]);
  269. if (ptime > buftime && diff_us >= (u64)
  270. sde_crtc->fps_info.fps_periodic_duration) {
  271. /* Multiplying with 10 to get fps in floating point */
  272. fps = frame_count * DEFAULT_FPS_PERIOD_1_SEC * 10;
  273. do_div(fps, diff_us);
  274. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  275. SDE_DEBUG("measured fps: %d\n",
  276. sde_crtc->fps_info.measured_fps);
  277. break;
  278. }
  279. current_time_index = (current_time_index == 0) ?
  280. (MAX_FRAME_COUNT - 1) : (current_time_index - 1);
  281. SDE_DEBUG("current time index: %d\n", current_time_index);
  282. frame_count++;
  283. }
  284. if (i == MAX_FRAME_COUNT) {
  285. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  286. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  287. diff_us = (u64)ktime_us_delta(current_time,
  288. sde_crtc->fps_info.time_buf[current_time_index]);
  289. if (diff_us >= sde_crtc->fps_info.fps_periodic_duration) {
  290. /* Multiplying with 10 to get fps in floating point */
  291. fps = (frame_count) * DEFAULT_FPS_PERIOD_1_SEC * 10;
  292. do_div(fps, diff_us);
  293. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  294. }
  295. }
  296. fps_int = (uint64_t) sde_crtc->fps_info.measured_fps;
  297. fps_decimal = do_div(fps_int, 10);
  298. return scnprintf(buf, PAGE_SIZE,
  299. "fps: %d.%d duration:%d frame_count:%lld\n", fps_int, fps_decimal,
  300. sde_crtc->fps_info.fps_periodic_duration, frame_count);
  301. }
  302. static ssize_t vsync_event_show(struct device *device,
  303. struct device_attribute *attr, char *buf)
  304. {
  305. struct drm_crtc *crtc;
  306. struct sde_crtc *sde_crtc;
  307. if (!device || !buf) {
  308. SDE_ERROR("invalid input param(s)\n");
  309. return -EAGAIN;
  310. }
  311. crtc = dev_get_drvdata(device);
  312. sde_crtc = to_sde_crtc(crtc);
  313. return scnprintf(buf, PAGE_SIZE, "VSYNC=%llu\n",
  314. ktime_to_ns(sde_crtc->vblank_last_cb_time));
  315. }
  316. static DEVICE_ATTR_RO(vsync_event);
  317. static DEVICE_ATTR_RO(measured_fps);
  318. static DEVICE_ATTR_RW(fps_periodicity_ms);
  319. static struct attribute *sde_crtc_dev_attrs[] = {
  320. &dev_attr_vsync_event.attr,
  321. &dev_attr_measured_fps.attr,
  322. &dev_attr_fps_periodicity_ms.attr,
  323. NULL
  324. };
  325. static const struct attribute_group sde_crtc_attr_group = {
  326. .attrs = sde_crtc_dev_attrs,
  327. };
  328. static const struct attribute_group *sde_crtc_attr_groups[] = {
  329. &sde_crtc_attr_group,
  330. NULL,
  331. };
  332. static void sde_crtc_destroy(struct drm_crtc *crtc)
  333. {
  334. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  335. SDE_DEBUG("\n");
  336. if (!crtc)
  337. return;
  338. if (sde_crtc->vsync_event_sf)
  339. sysfs_put(sde_crtc->vsync_event_sf);
  340. if (sde_crtc->sysfs_dev)
  341. device_unregister(sde_crtc->sysfs_dev);
  342. if (sde_crtc->blob_info)
  343. drm_property_blob_put(sde_crtc->blob_info);
  344. msm_property_destroy(&sde_crtc->property_info);
  345. sde_cp_crtc_destroy_properties(crtc);
  346. sde_fence_deinit(sde_crtc->output_fence);
  347. _sde_crtc_deinit_events(sde_crtc);
  348. drm_crtc_cleanup(crtc);
  349. mutex_destroy(&sde_crtc->crtc_lock);
  350. kfree(sde_crtc);
  351. }
  352. static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
  353. const struct drm_display_mode *mode,
  354. struct drm_display_mode *adjusted_mode)
  355. {
  356. SDE_DEBUG("\n");
  357. sde_cp_mode_switch_prop_dirty(crtc);
  358. if ((msm_is_mode_seamless(adjusted_mode) ||
  359. (msm_is_mode_seamless_vrr(adjusted_mode) ||
  360. msm_is_mode_seamless_dyn_clk(adjusted_mode))) &&
  361. (!crtc->enabled)) {
  362. SDE_ERROR("crtc state prevents seamless transition\n");
  363. return false;
  364. }
  365. return true;
  366. }
  367. static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
  368. struct sde_plane_state *pstate, struct sde_format *format)
  369. {
  370. uint32_t blend_op, fg_alpha, bg_alpha;
  371. uint32_t blend_type;
  372. struct sde_hw_mixer *lm = mixer->hw_lm;
  373. /* default to opaque blending */
  374. fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
  375. bg_alpha = 0xFF - fg_alpha;
  376. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
  377. blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
  378. SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
  379. switch (blend_type) {
  380. case SDE_DRM_BLEND_OP_OPAQUE:
  381. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  382. SDE_BLEND_BG_ALPHA_BG_CONST;
  383. break;
  384. case SDE_DRM_BLEND_OP_PREMULTIPLIED:
  385. if (format->alpha_enable) {
  386. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  387. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  388. if (fg_alpha != 0xff) {
  389. bg_alpha = fg_alpha;
  390. blend_op |= SDE_BLEND_BG_MOD_ALPHA |
  391. SDE_BLEND_BG_INV_MOD_ALPHA;
  392. } else {
  393. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  394. }
  395. }
  396. break;
  397. case SDE_DRM_BLEND_OP_COVERAGE:
  398. if (format->alpha_enable) {
  399. blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
  400. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  401. if (fg_alpha != 0xff) {
  402. bg_alpha = fg_alpha;
  403. blend_op |= SDE_BLEND_FG_MOD_ALPHA |
  404. SDE_BLEND_BG_MOD_ALPHA |
  405. SDE_BLEND_BG_INV_MOD_ALPHA;
  406. } else {
  407. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  408. }
  409. }
  410. break;
  411. case SDE_DRM_BLEND_OP_SKIP:
  412. SDE_ERROR("skip the blending for plane\n");
  413. return;
  414. default:
  415. /* do nothing */
  416. break;
  417. }
  418. lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
  419. bg_alpha, blend_op);
  420. SDE_DEBUG(
  421. "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
  422. (char *) &format->base.pixel_format,
  423. format->alpha_enable, fg_alpha, bg_alpha, blend_op);
  424. }
  425. static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
  426. struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer,
  427. struct sde_hw_dim_layer *dim_layer)
  428. {
  429. struct sde_crtc_state *cstate;
  430. struct sde_hw_mixer *lm;
  431. struct sde_hw_dim_layer split_dim_layer;
  432. int i;
  433. if (!dim_layer->rect.w || !dim_layer->rect.h) {
  434. SDE_DEBUG("empty dim_layer\n");
  435. return;
  436. }
  437. cstate = to_sde_crtc_state(crtc->state);
  438. SDE_DEBUG("dim_layer - flags:%d, stage:%d\n",
  439. dim_layer->flags, dim_layer->stage);
  440. split_dim_layer.stage = dim_layer->stage;
  441. split_dim_layer.color_fill = dim_layer->color_fill;
  442. /*
  443. * traverse through the layer mixers attached to crtc and find the
  444. * intersecting dim layer rect in each LM and program accordingly.
  445. */
  446. for (i = 0; i < sde_crtc->num_mixers; i++) {
  447. split_dim_layer.flags = dim_layer->flags;
  448. sde_kms_rect_intersect(&cstate->lm_roi[i], &dim_layer->rect,
  449. &split_dim_layer.rect);
  450. if (sde_kms_rect_is_null(&split_dim_layer.rect)) {
  451. /*
  452. * no extra programming required for non-intersecting
  453. * layer mixers with INCLUSIVE dim layer
  454. */
  455. if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE)
  456. continue;
  457. /*
  458. * program the other non-intersecting layer mixers with
  459. * INCLUSIVE dim layer of full size for uniformity
  460. * with EXCLUSIVE dim layer config.
  461. */
  462. split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE;
  463. split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE;
  464. memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i],
  465. sizeof(split_dim_layer.rect));
  466. } else {
  467. split_dim_layer.rect.x =
  468. split_dim_layer.rect.x -
  469. cstate->lm_roi[i].x;
  470. split_dim_layer.rect.y =
  471. split_dim_layer.rect.y -
  472. cstate->lm_roi[i].y;
  473. }
  474. SDE_EVT32_VERBOSE(DRMID(crtc),
  475. cstate->lm_roi[i].x,
  476. cstate->lm_roi[i].y,
  477. cstate->lm_roi[i].w,
  478. cstate->lm_roi[i].h,
  479. dim_layer->rect.x,
  480. dim_layer->rect.y,
  481. dim_layer->rect.w,
  482. dim_layer->rect.h,
  483. split_dim_layer.rect.x,
  484. split_dim_layer.rect.y,
  485. split_dim_layer.rect.w,
  486. split_dim_layer.rect.h);
  487. SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n",
  488. i, split_dim_layer.rect.x, split_dim_layer.rect.y,
  489. split_dim_layer.rect.w, split_dim_layer.rect.h);
  490. lm = mixer[i].hw_lm;
  491. mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
  492. lm->ops.setup_dim_layer(lm, &split_dim_layer);
  493. }
  494. }
  495. void sde_crtc_get_crtc_roi(struct drm_crtc_state *state,
  496. const struct sde_rect **crtc_roi)
  497. {
  498. struct sde_crtc_state *crtc_state;
  499. if (!state || !crtc_roi)
  500. return;
  501. crtc_state = to_sde_crtc_state(state);
  502. *crtc_roi = &crtc_state->crtc_roi;
  503. }
  504. bool sde_crtc_is_crtc_roi_dirty(struct drm_crtc_state *state)
  505. {
  506. struct sde_crtc_state *cstate;
  507. struct sde_crtc *sde_crtc;
  508. if (!state || !state->crtc)
  509. return false;
  510. sde_crtc = to_sde_crtc(state->crtc);
  511. cstate = to_sde_crtc_state(state);
  512. return msm_property_is_dirty(&sde_crtc->property_info,
  513. &cstate->property_state, CRTC_PROP_ROI_V1);
  514. }
  515. static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state,
  516. void __user *usr_ptr)
  517. {
  518. struct drm_crtc *crtc;
  519. struct sde_crtc_state *cstate;
  520. struct sde_drm_roi_v1 roi_v1;
  521. int i;
  522. if (!state) {
  523. SDE_ERROR("invalid args\n");
  524. return -EINVAL;
  525. }
  526. cstate = to_sde_crtc_state(state);
  527. crtc = cstate->base.crtc;
  528. memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list));
  529. if (!usr_ptr) {
  530. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  531. return 0;
  532. }
  533. if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) {
  534. SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc));
  535. return -EINVAL;
  536. }
  537. SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects);
  538. if (roi_v1.num_rects == 0) {
  539. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  540. return 0;
  541. }
  542. if (roi_v1.num_rects > SDE_MAX_ROI_V1) {
  543. SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc),
  544. roi_v1.num_rects);
  545. return -EINVAL;
  546. }
  547. cstate->user_roi_list.num_rects = roi_v1.num_rects;
  548. for (i = 0; i < roi_v1.num_rects; ++i) {
  549. cstate->user_roi_list.roi[i] = roi_v1.roi[i];
  550. SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n",
  551. DRMID(crtc), i,
  552. cstate->user_roi_list.roi[i].x1,
  553. cstate->user_roi_list.roi[i].y1,
  554. cstate->user_roi_list.roi[i].x2,
  555. cstate->user_roi_list.roi[i].y2);
  556. SDE_EVT32_VERBOSE(DRMID(crtc),
  557. cstate->user_roi_list.roi[i].x1,
  558. cstate->user_roi_list.roi[i].y1,
  559. cstate->user_roi_list.roi[i].x2,
  560. cstate->user_roi_list.roi[i].y2);
  561. }
  562. return 0;
  563. }
  564. static bool _sde_crtc_setup_is_3dmux_dsc(struct drm_crtc_state *state)
  565. {
  566. int i;
  567. struct sde_crtc_state *cstate;
  568. bool is_3dmux_dsc = false;
  569. cstate = to_sde_crtc_state(state);
  570. for (i = 0; i < cstate->num_connectors; i++) {
  571. struct drm_connector *conn = cstate->connectors[i];
  572. if (sde_connector_get_topology_name(conn) ==
  573. SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC)
  574. is_3dmux_dsc = true;
  575. }
  576. return is_3dmux_dsc;
  577. }
  578. static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc,
  579. struct drm_crtc_state *state)
  580. {
  581. struct drm_connector *conn;
  582. struct drm_connector_state *conn_state;
  583. struct sde_crtc *sde_crtc;
  584. struct sde_crtc_state *crtc_state;
  585. struct sde_rect *crtc_roi;
  586. struct msm_mode_info mode_info;
  587. int i = 0;
  588. int rc;
  589. bool is_crtc_roi_dirty;
  590. bool is_any_conn_roi_dirty;
  591. if (!crtc || !state)
  592. return -EINVAL;
  593. sde_crtc = to_sde_crtc(crtc);
  594. crtc_state = to_sde_crtc_state(state);
  595. crtc_roi = &crtc_state->crtc_roi;
  596. is_crtc_roi_dirty = sde_crtc_is_crtc_roi_dirty(state);
  597. is_any_conn_roi_dirty = false;
  598. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  599. struct sde_connector *sde_conn;
  600. struct sde_connector_state *sde_conn_state;
  601. struct sde_rect conn_roi;
  602. if (!conn_state || conn_state->crtc != crtc)
  603. continue;
  604. rc = sde_connector_state_get_mode_info(conn_state, &mode_info);
  605. if (rc) {
  606. SDE_ERROR("failed to get mode info\n");
  607. return -EINVAL;
  608. }
  609. sde_conn = to_sde_connector(conn_state->connector);
  610. sde_conn_state = to_sde_connector_state(conn_state);
  611. is_any_conn_roi_dirty = is_any_conn_roi_dirty ||
  612. msm_property_is_dirty(
  613. &sde_conn->property_info,
  614. &sde_conn_state->property_state,
  615. CONNECTOR_PROP_ROI_V1);
  616. if (!mode_info.roi_caps.enabled)
  617. continue;
  618. /*
  619. * current driver only supports same connector and crtc size,
  620. * but if support for different sizes is added, driver needs
  621. * to check the connector roi here to make sure is full screen
  622. * for dsc 3d-mux topology that doesn't support partial update.
  623. */
  624. if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list,
  625. sizeof(crtc_state->user_roi_list))) {
  626. SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n",
  627. sde_crtc->name);
  628. return -EINVAL;
  629. }
  630. sde_kms_rect_merge_rectangles(&sde_conn_state->rois, &conn_roi);
  631. SDE_DEBUG("conn_roi x:%u, y:%u, w:%u, h:%u\n",
  632. conn_roi.x, conn_roi.y,
  633. conn_roi.w, conn_roi.h);
  634. SDE_EVT32_VERBOSE(DRMID(crtc), DRMID(conn),
  635. conn_roi.x, conn_roi.y,
  636. conn_roi.w, conn_roi.h);
  637. }
  638. /*
  639. * Check against CRTC ROI and Connector ROI not being updated together.
  640. * This restriction should be relaxed when Connector ROI scaling is
  641. * supported.
  642. */
  643. if (is_any_conn_roi_dirty != is_crtc_roi_dirty) {
  644. SDE_ERROR("connector/crtc rois not updated together\n");
  645. return -EINVAL;
  646. }
  647. sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi);
  648. /* clear the ROI to null if it matches full screen anyways */
  649. if (crtc_roi->x == 0 && crtc_roi->y == 0 &&
  650. crtc_roi->w == state->adjusted_mode.hdisplay &&
  651. crtc_roi->h == state->adjusted_mode.vdisplay)
  652. memset(crtc_roi, 0, sizeof(*crtc_roi));
  653. SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name,
  654. crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
  655. SDE_EVT32_VERBOSE(DRMID(crtc), crtc_roi->x, crtc_roi->y, crtc_roi->w,
  656. crtc_roi->h);
  657. return 0;
  658. }
  659. static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc,
  660. struct drm_crtc_state *state)
  661. {
  662. struct sde_crtc *sde_crtc;
  663. struct sde_crtc_state *crtc_state;
  664. struct drm_connector *conn;
  665. struct drm_connector_state *conn_state;
  666. int i;
  667. if (!crtc || !state)
  668. return -EINVAL;
  669. sde_crtc = to_sde_crtc(crtc);
  670. crtc_state = to_sde_crtc_state(state);
  671. if (sde_kms_rect_is_null(&crtc_state->crtc_roi))
  672. return 0;
  673. /* partial update active, check if autorefresh is also requested */
  674. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  675. uint64_t autorefresh;
  676. if (!conn_state || conn_state->crtc != crtc)
  677. continue;
  678. autorefresh = sde_connector_get_property(conn_state,
  679. CONNECTOR_PROP_AUTOREFRESH);
  680. if (autorefresh) {
  681. SDE_ERROR(
  682. "%s: autorefresh & partial crtc roi incompatible %llu\n",
  683. sde_crtc->name, autorefresh);
  684. return -EINVAL;
  685. }
  686. }
  687. return 0;
  688. }
  689. static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc,
  690. struct drm_crtc_state *state, int lm_idx)
  691. {
  692. struct sde_crtc *sde_crtc;
  693. struct sde_crtc_state *crtc_state;
  694. const struct sde_rect *crtc_roi;
  695. const struct sde_rect *lm_bounds;
  696. struct sde_rect *lm_roi;
  697. if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds))
  698. return -EINVAL;
  699. sde_crtc = to_sde_crtc(crtc);
  700. crtc_state = to_sde_crtc_state(state);
  701. crtc_roi = &crtc_state->crtc_roi;
  702. lm_bounds = &crtc_state->lm_bounds[lm_idx];
  703. lm_roi = &crtc_state->lm_roi[lm_idx];
  704. if (sde_kms_rect_is_null(crtc_roi))
  705. memcpy(lm_roi, lm_bounds, sizeof(*lm_roi));
  706. else
  707. sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
  708. SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx,
  709. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  710. /*
  711. * partial update is not supported with 3dmux dsc or dest scaler.
  712. * hence, crtc roi must match the mixer dimensions.
  713. */
  714. if (crtc_state->num_ds_enabled ||
  715. _sde_crtc_setup_is_3dmux_dsc(state)) {
  716. if (memcmp(lm_roi, lm_bounds, sizeof(struct sde_rect))) {
  717. SDE_ERROR("Unsupported: Dest scaler/3d mux DSC + PU\n");
  718. return -EINVAL;
  719. }
  720. }
  721. /* if any dimension is zero, clear all dimensions for clarity */
  722. if (sde_kms_rect_is_null(lm_roi))
  723. memset(lm_roi, 0, sizeof(*lm_roi));
  724. return 0;
  725. }
  726. static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
  727. struct drm_crtc_state *state)
  728. {
  729. struct sde_crtc *sde_crtc;
  730. struct sde_crtc_state *crtc_state;
  731. u32 disp_bitmask = 0;
  732. int i;
  733. if (!crtc || !state) {
  734. pr_err("Invalid crtc or state\n");
  735. return 0;
  736. }
  737. sde_crtc = to_sde_crtc(crtc);
  738. crtc_state = to_sde_crtc_state(state);
  739. /* pingpong split: one ROI, one LM, two physical displays */
  740. if (crtc_state->is_ppsplit) {
  741. u32 lm_split_width = crtc_state->lm_bounds[0].w / 2;
  742. struct sde_rect *roi = &crtc_state->lm_roi[0];
  743. if (sde_kms_rect_is_null(roi))
  744. disp_bitmask = 0;
  745. else if ((u32)roi->x + (u32)roi->w <= lm_split_width)
  746. disp_bitmask = BIT(0); /* left only */
  747. else if (roi->x >= lm_split_width)
  748. disp_bitmask = BIT(1); /* right only */
  749. else
  750. disp_bitmask = BIT(0) | BIT(1); /* left and right */
  751. } else {
  752. for (i = 0; i < sde_crtc->num_mixers; i++) {
  753. if (!sde_kms_rect_is_null(&crtc_state->lm_roi[i]))
  754. disp_bitmask |= BIT(i);
  755. }
  756. }
  757. SDE_DEBUG("affected displays 0x%x\n", disp_bitmask);
  758. return disp_bitmask;
  759. }
  760. static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc,
  761. struct drm_crtc_state *state)
  762. {
  763. struct sde_crtc *sde_crtc;
  764. struct sde_crtc_state *crtc_state;
  765. const struct sde_rect *roi[CRTC_DUAL_MIXERS];
  766. if (!crtc || !state)
  767. return -EINVAL;
  768. sde_crtc = to_sde_crtc(crtc);
  769. crtc_state = to_sde_crtc_state(state);
  770. if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  771. SDE_ERROR("%s: unsupported number of mixers: %d\n",
  772. sde_crtc->name, sde_crtc->num_mixers);
  773. return -EINVAL;
  774. }
  775. /*
  776. * If using pingpong split: one ROI, one LM, two physical displays
  777. * then the ROI must be centered on the panel split boundary and
  778. * be of equal width across the split.
  779. */
  780. if (crtc_state->is_ppsplit) {
  781. u16 panel_split_width;
  782. u32 display_mask;
  783. roi[0] = &crtc_state->lm_roi[0];
  784. if (sde_kms_rect_is_null(roi[0]))
  785. return 0;
  786. display_mask = _sde_crtc_get_displays_affected(crtc, state);
  787. if (display_mask != (BIT(0) | BIT(1)))
  788. return 0;
  789. panel_split_width = crtc_state->lm_bounds[0].w / 2;
  790. if (roi[0]->x + roi[0]->w / 2 != panel_split_width) {
  791. SDE_ERROR("%s: roi x %d w %d split %d\n",
  792. sde_crtc->name, roi[0]->x, roi[0]->w,
  793. panel_split_width);
  794. return -EINVAL;
  795. }
  796. return 0;
  797. }
  798. /*
  799. * On certain HW, if using 2 LM, ROIs must be split evenly between the
  800. * LMs and be of equal width.
  801. */
  802. if (sde_crtc->num_mixers < 2)
  803. return 0;
  804. roi[0] = &crtc_state->lm_roi[0];
  805. roi[1] = &crtc_state->lm_roi[1];
  806. /* if one of the roi is null it's a left/right-only update */
  807. if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1]))
  808. return 0;
  809. /* check lm rois are equal width & first roi ends at 2nd roi */
  810. if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) {
  811. SDE_ERROR(
  812. "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n",
  813. sde_crtc->name, roi[0]->x, roi[0]->w,
  814. roi[1]->x, roi[1]->w);
  815. return -EINVAL;
  816. }
  817. return 0;
  818. }
  819. static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc,
  820. struct drm_crtc_state *state)
  821. {
  822. struct sde_crtc *sde_crtc;
  823. struct sde_crtc_state *crtc_state;
  824. const struct sde_rect *crtc_roi;
  825. const struct drm_plane_state *pstate;
  826. struct drm_plane *plane;
  827. if (!crtc || !state)
  828. return -EINVAL;
  829. /*
  830. * Reject commit if a Plane CRTC destination coordinates fall outside
  831. * the partial CRTC ROI. LM output is determined via connector ROIs,
  832. * if they are specified, not Plane CRTC ROIs.
  833. */
  834. sde_crtc = to_sde_crtc(crtc);
  835. crtc_state = to_sde_crtc_state(state);
  836. crtc_roi = &crtc_state->crtc_roi;
  837. if (sde_kms_rect_is_null(crtc_roi))
  838. return 0;
  839. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  840. struct sde_rect plane_roi, intersection;
  841. if (IS_ERR_OR_NULL(pstate)) {
  842. int rc = PTR_ERR(pstate);
  843. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  844. sde_crtc->name, plane->base.id, rc);
  845. return rc;
  846. }
  847. plane_roi.x = pstate->crtc_x;
  848. plane_roi.y = pstate->crtc_y;
  849. plane_roi.w = pstate->crtc_w;
  850. plane_roi.h = pstate->crtc_h;
  851. sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection);
  852. if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) {
  853. SDE_ERROR(
  854. "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n",
  855. sde_crtc->name, plane->base.id,
  856. plane_roi.x, plane_roi.y,
  857. plane_roi.w, plane_roi.h,
  858. crtc_roi->x, crtc_roi->y,
  859. crtc_roi->w, crtc_roi->h);
  860. return -E2BIG;
  861. }
  862. }
  863. return 0;
  864. }
  865. static int _sde_crtc_check_rois(struct drm_crtc *crtc,
  866. struct drm_crtc_state *state)
  867. {
  868. struct sde_crtc *sde_crtc;
  869. struct sde_crtc_state *sde_crtc_state;
  870. struct msm_mode_info mode_info;
  871. int rc, lm_idx, i;
  872. if (!crtc || !state)
  873. return -EINVAL;
  874. memset(&mode_info, 0, sizeof(mode_info));
  875. sde_crtc = to_sde_crtc(crtc);
  876. sde_crtc_state = to_sde_crtc_state(state);
  877. /*
  878. * check connector array cached at modeset time since incoming atomic
  879. * state may not include any connectors if they aren't modified
  880. */
  881. for (i = 0; i < sde_crtc_state->num_connectors; i++) {
  882. struct drm_connector *conn = sde_crtc_state->connectors[i];
  883. if (!conn || !conn->state)
  884. continue;
  885. rc = sde_connector_state_get_mode_info(conn->state, &mode_info);
  886. if (rc) {
  887. SDE_ERROR("failed to get mode info\n");
  888. return -EINVAL;
  889. }
  890. if (!mode_info.roi_caps.enabled)
  891. continue;
  892. if (sde_crtc_state->user_roi_list.num_rects >
  893. mode_info.roi_caps.num_roi) {
  894. SDE_ERROR("roi count is exceeding limit, %d > %d\n",
  895. sde_crtc_state->user_roi_list.num_rects,
  896. mode_info.roi_caps.num_roi);
  897. return -E2BIG;
  898. }
  899. rc = _sde_crtc_set_crtc_roi(crtc, state);
  900. if (rc)
  901. return rc;
  902. rc = _sde_crtc_check_autorefresh(crtc, state);
  903. if (rc)
  904. return rc;
  905. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  906. rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx);
  907. if (rc)
  908. return rc;
  909. }
  910. rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state);
  911. if (rc)
  912. return rc;
  913. rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state);
  914. if (rc)
  915. return rc;
  916. }
  917. return 0;
  918. }
  919. static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc)
  920. {
  921. struct sde_crtc *sde_crtc;
  922. struct sde_crtc_state *crtc_state;
  923. const struct sde_rect *lm_roi;
  924. struct sde_hw_mixer *hw_lm;
  925. int lm_idx, lm_horiz_position;
  926. if (!crtc)
  927. return;
  928. sde_crtc = to_sde_crtc(crtc);
  929. crtc_state = to_sde_crtc_state(crtc->state);
  930. lm_horiz_position = 0;
  931. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  932. struct sde_hw_mixer_cfg cfg;
  933. lm_roi = &crtc_state->lm_roi[lm_idx];
  934. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  935. SDE_EVT32(DRMID(crtc_state->base.crtc), lm_idx,
  936. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  937. if (sde_kms_rect_is_null(lm_roi))
  938. continue;
  939. hw_lm->cfg.out_width = lm_roi->w;
  940. hw_lm->cfg.out_height = lm_roi->h;
  941. hw_lm->cfg.right_mixer = lm_horiz_position;
  942. cfg.out_width = lm_roi->w;
  943. cfg.out_height = lm_roi->h;
  944. cfg.right_mixer = lm_horiz_position++;
  945. cfg.flags = 0;
  946. hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
  947. }
  948. }
  949. struct plane_state {
  950. struct sde_plane_state *sde_pstate;
  951. const struct drm_plane_state *drm_pstate;
  952. int stage;
  953. u32 pipe_id;
  954. };
  955. static int pstate_cmp(const void *a, const void *b)
  956. {
  957. struct plane_state *pa = (struct plane_state *)a;
  958. struct plane_state *pb = (struct plane_state *)b;
  959. int rc = 0;
  960. int pa_zpos, pb_zpos;
  961. pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
  962. pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
  963. if (pa_zpos != pb_zpos)
  964. rc = pa_zpos - pb_zpos;
  965. else
  966. rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
  967. return rc;
  968. }
  969. /*
  970. * validate and set source split:
  971. * use pstates sorted by stage to check planes on same stage
  972. * we assume that all pipes are in source split so its valid to compare
  973. * without taking into account left/right mixer placement
  974. */
  975. static int _sde_crtc_validate_src_split_order(struct drm_crtc *crtc,
  976. struct plane_state *pstates, int cnt)
  977. {
  978. struct plane_state *prv_pstate, *cur_pstate;
  979. struct sde_rect left_rect, right_rect;
  980. struct sde_kms *sde_kms;
  981. int32_t left_pid, right_pid;
  982. int32_t stage;
  983. int i, rc = 0;
  984. sde_kms = _sde_crtc_get_kms(crtc);
  985. if (!sde_kms || !sde_kms->catalog) {
  986. SDE_ERROR("invalid parameters\n");
  987. return -EINVAL;
  988. }
  989. for (i = 1; i < cnt; i++) {
  990. prv_pstate = &pstates[i - 1];
  991. cur_pstate = &pstates[i];
  992. if (prv_pstate->stage != cur_pstate->stage)
  993. continue;
  994. stage = cur_pstate->stage;
  995. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  996. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  997. prv_pstate->drm_pstate->crtc_y,
  998. prv_pstate->drm_pstate->crtc_w,
  999. prv_pstate->drm_pstate->crtc_h, false);
  1000. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1001. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1002. cur_pstate->drm_pstate->crtc_y,
  1003. cur_pstate->drm_pstate->crtc_w,
  1004. cur_pstate->drm_pstate->crtc_h, false);
  1005. if (right_rect.x < left_rect.x) {
  1006. swap(left_pid, right_pid);
  1007. swap(left_rect, right_rect);
  1008. swap(prv_pstate, cur_pstate);
  1009. }
  1010. /*
  1011. * - planes are enumerated in pipe-priority order such that
  1012. * planes with lower drm_id must be left-most in a shared
  1013. * blend-stage when using source split.
  1014. * - planes in source split must be contiguous in width
  1015. * - planes in source split must have same dest yoff and height
  1016. */
  1017. if ((right_pid < left_pid) &&
  1018. !sde_kms->catalog->pipe_order_type) {
  1019. SDE_ERROR(
  1020. "invalid src split cfg, stage:%d left:%d right:%d\n",
  1021. stage, left_pid, right_pid);
  1022. return -EINVAL;
  1023. } else if (right_rect.x != (left_rect.x + left_rect.w)) {
  1024. SDE_ERROR(
  1025. "invalid coordinates, stage:%d l:%d-%d r:%d-%d\n",
  1026. stage, left_rect.x, left_rect.w,
  1027. right_rect.x, right_rect.w);
  1028. return -EINVAL;
  1029. } else if ((left_rect.y != right_rect.y) ||
  1030. (left_rect.h != right_rect.h)) {
  1031. SDE_ERROR(
  1032. "stage:%d invalid yoff/ht: l_yxh:%dx%d r_yxh:%dx%d\n",
  1033. stage, left_rect.y, left_rect.h,
  1034. right_rect.y, right_rect.h);
  1035. return -EINVAL;
  1036. }
  1037. }
  1038. return rc;
  1039. }
  1040. static void _sde_crtc_set_src_split_order(struct drm_crtc *crtc,
  1041. struct plane_state *pstates, int cnt)
  1042. {
  1043. struct plane_state *prv_pstate, *cur_pstate, *nxt_pstate;
  1044. struct sde_kms *sde_kms;
  1045. struct sde_rect left_rect, right_rect;
  1046. int32_t left_pid, right_pid;
  1047. int32_t stage;
  1048. int i;
  1049. sde_kms = _sde_crtc_get_kms(crtc);
  1050. if (!sde_kms || !sde_kms->catalog) {
  1051. SDE_ERROR("invalid parameters\n");
  1052. return;
  1053. }
  1054. if (!sde_kms->catalog->pipe_order_type)
  1055. return;
  1056. for (i = 0; i < cnt; i++) {
  1057. prv_pstate = (i > 0) ? &pstates[i - 1] : NULL;
  1058. cur_pstate = &pstates[i];
  1059. nxt_pstate = ((i + 1) < cnt) ? &pstates[i + 1] : NULL;
  1060. if ((!prv_pstate) || (prv_pstate->stage != cur_pstate->stage)) {
  1061. /*
  1062. * reset if prv or nxt pipes are not in the same stage
  1063. * as the cur pipe
  1064. */
  1065. if ((!nxt_pstate)
  1066. || (nxt_pstate->stage != cur_pstate->stage))
  1067. cur_pstate->sde_pstate->pipe_order_flags = 0;
  1068. continue;
  1069. }
  1070. stage = cur_pstate->stage;
  1071. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1072. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1073. prv_pstate->drm_pstate->crtc_y,
  1074. prv_pstate->drm_pstate->crtc_w,
  1075. prv_pstate->drm_pstate->crtc_h, false);
  1076. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1077. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1078. cur_pstate->drm_pstate->crtc_y,
  1079. cur_pstate->drm_pstate->crtc_w,
  1080. cur_pstate->drm_pstate->crtc_h, false);
  1081. if (right_rect.x < left_rect.x) {
  1082. swap(left_pid, right_pid);
  1083. swap(left_rect, right_rect);
  1084. swap(prv_pstate, cur_pstate);
  1085. }
  1086. cur_pstate->sde_pstate->pipe_order_flags = SDE_SSPP_RIGHT;
  1087. prv_pstate->sde_pstate->pipe_order_flags = 0;
  1088. }
  1089. for (i = 0; i < cnt; i++) {
  1090. cur_pstate = &pstates[i];
  1091. sde_plane_setup_src_split_order(
  1092. cur_pstate->drm_pstate->plane,
  1093. cur_pstate->sde_pstate->multirect_index,
  1094. cur_pstate->sde_pstate->pipe_order_flags);
  1095. }
  1096. }
  1097. static void __sde_crtc_assign_active_cfg(struct sde_crtc *sdecrtc,
  1098. struct drm_plane *plane)
  1099. {
  1100. u8 found = 0;
  1101. int i;
  1102. for (i = 0; i < SDE_STAGE_MAX; i++) {
  1103. if (sdecrtc->active_cfg.stage[i][0] == SSPP_NONE) {
  1104. found = 1;
  1105. break;
  1106. }
  1107. }
  1108. if (!found) {
  1109. SDE_ERROR("All active configs are allocated\n");
  1110. return;
  1111. }
  1112. sdecrtc->active_cfg.stage[i][0] = sde_plane_pipe(plane);
  1113. }
  1114. static void _sde_crtc_setup_blend_cfg_by_stage(struct sde_crtc_mixer *mixer,
  1115. int num_mixers, struct plane_state *pstates, int cnt)
  1116. {
  1117. int i, lm_idx;
  1118. struct sde_format *format;
  1119. bool blend_stage[SDE_STAGE_MAX] = { false };
  1120. u32 blend_type;
  1121. for (i = cnt - 1; i >= 0; i--) {
  1122. blend_type = sde_plane_get_property(pstates[i].sde_pstate,
  1123. PLANE_PROP_BLEND_OP);
  1124. /* stage has already been programmed or BLEND_OP_SKIP type */
  1125. if (blend_stage[pstates[i].sde_pstate->stage] ||
  1126. blend_type == SDE_DRM_BLEND_OP_SKIP)
  1127. continue;
  1128. for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) {
  1129. format = to_sde_format(msm_framebuffer_format(
  1130. pstates[i].sde_pstate->base.fb));
  1131. if (!format) {
  1132. SDE_ERROR("invalid format\n");
  1133. return;
  1134. }
  1135. _sde_crtc_setup_blend_cfg(mixer + lm_idx,
  1136. pstates[i].sde_pstate, format);
  1137. blend_stage[pstates[i].sde_pstate->stage] = true;
  1138. }
  1139. }
  1140. }
  1141. static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
  1142. struct drm_crtc_state *old_state, struct sde_crtc *sde_crtc,
  1143. struct sde_crtc_mixer *mixer)
  1144. {
  1145. struct drm_plane *plane;
  1146. struct drm_framebuffer *fb;
  1147. struct drm_plane_state *state;
  1148. struct sde_crtc_state *cstate;
  1149. struct sde_plane_state *pstate = NULL;
  1150. struct plane_state *pstates = NULL;
  1151. struct sde_format *format;
  1152. struct sde_hw_ctl *ctl;
  1153. struct sde_hw_mixer *lm;
  1154. struct sde_hw_stage_cfg *stage_cfg;
  1155. struct sde_rect plane_crtc_roi;
  1156. uint32_t stage_idx, lm_idx;
  1157. int zpos_cnt[SDE_STAGE_MAX + 1] = { 0 };
  1158. int i, mode, cnt = 0;
  1159. bool bg_alpha_enable = false, is_secure = false;
  1160. u32 blend_type;
  1161. if (!sde_crtc || !crtc->state || !mixer) {
  1162. SDE_ERROR("invalid sde_crtc or mixer\n");
  1163. return;
  1164. }
  1165. ctl = mixer->hw_ctl;
  1166. lm = mixer->hw_lm;
  1167. stage_cfg = &sde_crtc->stage_cfg;
  1168. cstate = to_sde_crtc_state(crtc->state);
  1169. pstates = kcalloc(SDE_PSTATES_MAX,
  1170. sizeof(struct plane_state), GFP_KERNEL);
  1171. if (!pstates)
  1172. return;
  1173. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1174. state = plane->state;
  1175. if (!state)
  1176. continue;
  1177. plane_crtc_roi.x = state->crtc_x;
  1178. plane_crtc_roi.y = state->crtc_y;
  1179. plane_crtc_roi.w = state->crtc_w;
  1180. plane_crtc_roi.h = state->crtc_h;
  1181. pstate = to_sde_plane_state(state);
  1182. fb = state->fb;
  1183. mode = sde_plane_get_property(pstate,
  1184. PLANE_PROP_FB_TRANSLATION_MODE);
  1185. is_secure = ((mode == SDE_DRM_FB_SEC) ||
  1186. (mode == SDE_DRM_FB_SEC_DIR_TRANS)) ?
  1187. true : false;
  1188. sde_plane_ctl_flush(plane, ctl, true);
  1189. SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
  1190. crtc->base.id,
  1191. pstate->stage,
  1192. plane->base.id,
  1193. sde_plane_pipe(plane) - SSPP_VIG0,
  1194. state->fb ? state->fb->base.id : -1);
  1195. format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
  1196. if (!format) {
  1197. SDE_ERROR("invalid format\n");
  1198. goto end;
  1199. }
  1200. blend_type = sde_plane_get_property(pstate,
  1201. PLANE_PROP_BLEND_OP);
  1202. if (blend_type == SDE_DRM_BLEND_OP_SKIP) {
  1203. __sde_crtc_assign_active_cfg(sde_crtc, plane);
  1204. } else {
  1205. if (pstate->stage == SDE_STAGE_BASE &&
  1206. format->alpha_enable)
  1207. bg_alpha_enable = true;
  1208. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1209. state->fb ? state->fb->base.id : -1,
  1210. state->src_x >> 16, state->src_y >> 16,
  1211. state->src_w >> 16, state->src_h >> 16,
  1212. state->crtc_x, state->crtc_y,
  1213. state->crtc_w, state->crtc_h,
  1214. pstate->rotation, is_secure);
  1215. stage_idx = zpos_cnt[pstate->stage]++;
  1216. stage_cfg->stage[pstate->stage][stage_idx] =
  1217. sde_plane_pipe(plane);
  1218. stage_cfg->multirect_index[pstate->stage][stage_idx] =
  1219. pstate->multirect_index;
  1220. SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
  1221. sde_plane_pipe(plane) - SSPP_VIG0,
  1222. pstate->stage,
  1223. pstate->multirect_index,
  1224. pstate->multirect_mode,
  1225. format->base.pixel_format,
  1226. fb ? fb->modifier : 0);
  1227. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers;
  1228. lm_idx++) {
  1229. if (bg_alpha_enable && !format->alpha_enable)
  1230. mixer[lm_idx].mixer_op_mode = 0;
  1231. else
  1232. mixer[lm_idx].mixer_op_mode |=
  1233. 1 << pstate->stage;
  1234. }
  1235. }
  1236. if (cnt >= SDE_PSTATES_MAX)
  1237. continue;
  1238. pstates[cnt].sde_pstate = pstate;
  1239. pstates[cnt].drm_pstate = state;
  1240. if (blend_type == SDE_DRM_BLEND_OP_SKIP)
  1241. pstates[cnt].stage = SKIP_STAGING_PIPE_ZPOS;
  1242. else
  1243. pstates[cnt].stage = sde_plane_get_property(
  1244. pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
  1245. pstates[cnt].pipe_id = sde_plane_pipe(plane);
  1246. cnt++;
  1247. }
  1248. /* blend config update */
  1249. _sde_crtc_setup_blend_cfg_by_stage(mixer, sde_crtc->num_mixers,
  1250. pstates, cnt);
  1251. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  1252. _sde_crtc_set_src_split_order(crtc, pstates, cnt);
  1253. if (lm && lm->ops.setup_dim_layer) {
  1254. cstate = to_sde_crtc_state(crtc->state);
  1255. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty)) {
  1256. for (i = 0; i < cstate->num_dim_layers; i++)
  1257. _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc,
  1258. mixer, &cstate->dim_layer[i]);
  1259. clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  1260. }
  1261. }
  1262. _sde_crtc_program_lm_output_roi(crtc);
  1263. end:
  1264. kfree(pstates);
  1265. }
  1266. static void _sde_crtc_swap_mixers_for_right_partial_update(
  1267. struct drm_crtc *crtc)
  1268. {
  1269. struct sde_crtc *sde_crtc;
  1270. struct sde_crtc_state *cstate;
  1271. struct drm_encoder *drm_enc;
  1272. bool is_right_only;
  1273. bool encoder_in_dsc_merge = false;
  1274. if (!crtc || !crtc->state)
  1275. return;
  1276. sde_crtc = to_sde_crtc(crtc);
  1277. cstate = to_sde_crtc_state(crtc->state);
  1278. if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS)
  1279. return;
  1280. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  1281. crtc->state->encoder_mask) {
  1282. if (sde_encoder_is_dsc_merge(drm_enc)) {
  1283. encoder_in_dsc_merge = true;
  1284. break;
  1285. }
  1286. }
  1287. /**
  1288. * For right-only partial update with DSC merge, we swap LM0 & LM1.
  1289. * This is due to two reasons:
  1290. * - On 8996, there is a DSC HW requirement that in DSC Merge Mode,
  1291. * the left DSC must be used, right DSC cannot be used alone.
  1292. * For right-only partial update, this means swap layer mixers to map
  1293. * Left LM to Right INTF. On later HW this was relaxed.
  1294. * - In DSC Merge mode, the physical encoder has already registered
  1295. * PP0 as the master, to switch to right-only we would have to
  1296. * reprogram to be driven by PP1 instead.
  1297. * To support both cases, we prefer to support the mixer swap solution.
  1298. */
  1299. if (!encoder_in_dsc_merge)
  1300. return;
  1301. is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) &&
  1302. !sde_kms_rect_is_null(&cstate->lm_roi[1]);
  1303. if (is_right_only && !sde_crtc->mixers_swapped) {
  1304. /* right-only update swap mixers */
  1305. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1306. sde_crtc->mixers_swapped = true;
  1307. } else if (!is_right_only && sde_crtc->mixers_swapped) {
  1308. /* left-only or full update, swap back */
  1309. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1310. sde_crtc->mixers_swapped = false;
  1311. }
  1312. SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n",
  1313. sde_crtc->name, is_right_only, sde_crtc->mixers_swapped,
  1314. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1315. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1316. SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped,
  1317. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1318. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1319. }
  1320. /**
  1321. * _sde_crtc_blend_setup - configure crtc mixers
  1322. * @crtc: Pointer to drm crtc structure
  1323. * @old_state: Pointer to old crtc state
  1324. * @add_planes: Whether or not to add planes to mixers
  1325. */
  1326. static void _sde_crtc_blend_setup(struct drm_crtc *crtc,
  1327. struct drm_crtc_state *old_state, bool add_planes)
  1328. {
  1329. struct sde_crtc *sde_crtc;
  1330. struct sde_crtc_state *sde_crtc_state;
  1331. struct sde_crtc_mixer *mixer;
  1332. struct sde_hw_ctl *ctl;
  1333. struct sde_hw_mixer *lm;
  1334. struct sde_ctl_flush_cfg cfg = {0,};
  1335. int i;
  1336. if (!crtc)
  1337. return;
  1338. sde_crtc = to_sde_crtc(crtc);
  1339. sde_crtc_state = to_sde_crtc_state(crtc->state);
  1340. mixer = sde_crtc->mixers;
  1341. SDE_DEBUG("%s\n", sde_crtc->name);
  1342. if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  1343. SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
  1344. return;
  1345. }
  1346. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1347. if (!mixer[i].hw_lm) {
  1348. SDE_ERROR("invalid lm or ctl assigned to mixer\n");
  1349. return;
  1350. }
  1351. mixer[i].mixer_op_mode = 0;
  1352. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS,
  1353. sde_crtc_state->dirty)) {
  1354. /* clear dim_layer settings */
  1355. lm = mixer[i].hw_lm;
  1356. if (lm->ops.clear_dim_layer)
  1357. lm->ops.clear_dim_layer(lm);
  1358. }
  1359. }
  1360. _sde_crtc_swap_mixers_for_right_partial_update(crtc);
  1361. /* initialize stage cfg */
  1362. memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg));
  1363. memset(&sde_crtc->active_cfg, 0, sizeof(sde_crtc->active_cfg));
  1364. if (add_planes)
  1365. _sde_crtc_blend_setup_mixer(crtc, old_state, sde_crtc, mixer);
  1366. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1367. const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i];
  1368. ctl = mixer[i].hw_ctl;
  1369. lm = mixer[i].hw_lm;
  1370. if (sde_kms_rect_is_null(lm_roi)) {
  1371. SDE_DEBUG(
  1372. "%s: lm%d leave ctl%d mask 0 since null roi\n",
  1373. sde_crtc->name, lm->idx - LM_0,
  1374. ctl->idx - CTL_0);
  1375. continue;
  1376. }
  1377. lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
  1378. /* stage config flush mask */
  1379. ctl->ops.update_bitmask_mixer(ctl, mixer[i].hw_lm->idx, 1);
  1380. ctl->ops.get_pending_flush(ctl, &cfg);
  1381. SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
  1382. mixer[i].hw_lm->idx - LM_0,
  1383. mixer[i].mixer_op_mode,
  1384. ctl->idx - CTL_0,
  1385. cfg.pending_flush_mask);
  1386. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1387. &sde_crtc->stage_cfg, &sde_crtc->active_cfg);
  1388. }
  1389. _sde_crtc_program_lm_output_roi(crtc);
  1390. }
  1391. int sde_crtc_find_plane_fb_modes(struct drm_crtc *crtc,
  1392. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1393. {
  1394. struct drm_plane *plane;
  1395. struct sde_plane_state *sde_pstate;
  1396. uint32_t mode = 0;
  1397. int rc;
  1398. if (!crtc) {
  1399. SDE_ERROR("invalid state\n");
  1400. return -EINVAL;
  1401. }
  1402. *fb_ns = 0;
  1403. *fb_sec = 0;
  1404. *fb_sec_dir = 0;
  1405. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1406. if (IS_ERR_OR_NULL(plane) || IS_ERR_OR_NULL(plane->state)) {
  1407. rc = PTR_ERR(plane);
  1408. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1409. DRMID(crtc), DRMID(plane), rc);
  1410. return rc;
  1411. }
  1412. sde_pstate = to_sde_plane_state(plane->state);
  1413. mode = sde_plane_get_property(sde_pstate,
  1414. PLANE_PROP_FB_TRANSLATION_MODE);
  1415. switch (mode) {
  1416. case SDE_DRM_FB_NON_SEC:
  1417. (*fb_ns)++;
  1418. break;
  1419. case SDE_DRM_FB_SEC:
  1420. (*fb_sec)++;
  1421. break;
  1422. case SDE_DRM_FB_SEC_DIR_TRANS:
  1423. (*fb_sec_dir)++;
  1424. break;
  1425. default:
  1426. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1427. DRMID(plane), mode);
  1428. return -EINVAL;
  1429. }
  1430. }
  1431. return 0;
  1432. }
  1433. int sde_crtc_state_find_plane_fb_modes(struct drm_crtc_state *state,
  1434. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1435. {
  1436. struct drm_plane *plane;
  1437. const struct drm_plane_state *pstate;
  1438. struct sde_plane_state *sde_pstate;
  1439. uint32_t mode = 0;
  1440. int rc;
  1441. if (!state) {
  1442. SDE_ERROR("invalid state\n");
  1443. return -EINVAL;
  1444. }
  1445. *fb_ns = 0;
  1446. *fb_sec = 0;
  1447. *fb_sec_dir = 0;
  1448. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  1449. if (IS_ERR_OR_NULL(pstate)) {
  1450. rc = PTR_ERR(pstate);
  1451. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1452. DRMID(state->crtc), DRMID(plane), rc);
  1453. return rc;
  1454. }
  1455. sde_pstate = to_sde_plane_state(pstate);
  1456. mode = sde_plane_get_property(sde_pstate,
  1457. PLANE_PROP_FB_TRANSLATION_MODE);
  1458. switch (mode) {
  1459. case SDE_DRM_FB_NON_SEC:
  1460. (*fb_ns)++;
  1461. break;
  1462. case SDE_DRM_FB_SEC:
  1463. (*fb_sec)++;
  1464. break;
  1465. case SDE_DRM_FB_SEC_DIR_TRANS:
  1466. (*fb_sec_dir)++;
  1467. break;
  1468. default:
  1469. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1470. DRMID(plane), mode);
  1471. return -EINVAL;
  1472. }
  1473. }
  1474. return 0;
  1475. }
  1476. static void _sde_drm_fb_sec_dir_trans(
  1477. struct sde_kms_smmu_state_data *smmu_state, uint32_t secure_level,
  1478. struct sde_mdss_cfg *catalog, bool old_valid_fb, int *ops)
  1479. {
  1480. /* secure display usecase */
  1481. if ((smmu_state->state == ATTACHED)
  1482. && (secure_level == SDE_DRM_SEC_ONLY)) {
  1483. smmu_state->state = catalog->sui_ns_allowed ?
  1484. DETACH_SEC_REQ : DETACH_ALL_REQ;
  1485. smmu_state->secure_level = secure_level;
  1486. smmu_state->transition_type = PRE_COMMIT;
  1487. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1488. if (old_valid_fb)
  1489. *ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE |
  1490. SDE_KMS_OPS_CLEANUP_PLANE_FB);
  1491. if (catalog->sui_misr_supported)
  1492. smmu_state->sui_misr_state =
  1493. SUI_MISR_ENABLE_REQ;
  1494. /* secure camera usecase */
  1495. } else if (smmu_state->state == ATTACHED) {
  1496. smmu_state->state = DETACH_SEC_REQ;
  1497. smmu_state->secure_level = secure_level;
  1498. smmu_state->transition_type = PRE_COMMIT;
  1499. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1500. }
  1501. }
  1502. static void _sde_drm_fb_transactions(
  1503. struct sde_kms_smmu_state_data *smmu_state,
  1504. struct sde_mdss_cfg *catalog, bool old_valid_fb, bool post_commit,
  1505. int *ops)
  1506. {
  1507. if (((smmu_state->state == DETACHED)
  1508. || (smmu_state->state == DETACH_ALL_REQ))
  1509. || ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)
  1510. && ((smmu_state->state == DETACHED_SEC)
  1511. || (smmu_state->state == DETACH_SEC_REQ)))) {
  1512. smmu_state->state = catalog->sui_ns_allowed ?
  1513. ATTACH_SEC_REQ : ATTACH_ALL_REQ;
  1514. smmu_state->transition_type = post_commit ?
  1515. POST_COMMIT : PRE_COMMIT;
  1516. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1517. if (old_valid_fb)
  1518. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1519. if (catalog->sui_misr_supported)
  1520. smmu_state->sui_misr_state =
  1521. SUI_MISR_DISABLE_REQ;
  1522. } else if ((smmu_state->state == DETACHED_SEC)
  1523. || (smmu_state->state == DETACH_SEC_REQ)) {
  1524. smmu_state->state = ATTACH_SEC_REQ;
  1525. smmu_state->transition_type = post_commit ?
  1526. POST_COMMIT : PRE_COMMIT;
  1527. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1528. if (old_valid_fb)
  1529. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1530. }
  1531. }
  1532. /**
  1533. * sde_crtc_get_secure_transition_ops - determines the operations that
  1534. * need to be performed before transitioning to secure state
  1535. * This function should be called after swapping the new state
  1536. * @crtc: Pointer to drm crtc structure
  1537. * Returns the bitmask of operations need to be performed, -Error in
  1538. * case of error cases
  1539. */
  1540. int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
  1541. struct drm_crtc_state *old_crtc_state,
  1542. bool old_valid_fb)
  1543. {
  1544. struct drm_plane *plane;
  1545. struct drm_encoder *encoder;
  1546. struct sde_crtc *sde_crtc;
  1547. struct sde_kms *sde_kms;
  1548. struct sde_mdss_cfg *catalog;
  1549. struct sde_kms_smmu_state_data *smmu_state;
  1550. uint32_t translation_mode = 0, secure_level;
  1551. int ops = 0;
  1552. bool post_commit = false;
  1553. if (!crtc || !crtc->state) {
  1554. SDE_ERROR("invalid crtc\n");
  1555. return -EINVAL;
  1556. }
  1557. sde_kms = _sde_crtc_get_kms(crtc);
  1558. if (!sde_kms)
  1559. return -EINVAL;
  1560. smmu_state = &sde_kms->smmu_state;
  1561. smmu_state->prev_state = smmu_state->state;
  1562. smmu_state->prev_secure_level = smmu_state->secure_level;
  1563. sde_crtc = to_sde_crtc(crtc);
  1564. secure_level = sde_crtc_get_secure_level(crtc, crtc->state);
  1565. catalog = sde_kms->catalog;
  1566. /*
  1567. * SMMU operations need to be delayed in case of video mode panels
  1568. * when switching back to non_secure mode
  1569. */
  1570. drm_for_each_encoder_mask(encoder, crtc->dev,
  1571. crtc->state->encoder_mask) {
  1572. if (sde_encoder_is_dsi_display(encoder))
  1573. post_commit |= sde_encoder_check_curr_mode(encoder,
  1574. MSM_DISPLAY_VIDEO_MODE);
  1575. }
  1576. SDE_DEBUG("crtc%d: secure_level %d old_valid_fb %d post_commit %d\n",
  1577. DRMID(crtc), secure_level, old_valid_fb, post_commit);
  1578. SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,
  1579. old_valid_fb, post_commit, SDE_EVTLOG_FUNC_ENTRY);
  1580. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1581. if (!plane->state)
  1582. continue;
  1583. translation_mode = sde_plane_get_property(
  1584. to_sde_plane_state(plane->state),
  1585. PLANE_PROP_FB_TRANSLATION_MODE);
  1586. if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) {
  1587. SDE_ERROR("crtc%d: invalid translation_mode %d\n",
  1588. DRMID(crtc), translation_mode);
  1589. return -EINVAL;
  1590. }
  1591. /* we can break if we find sec_dir plane */
  1592. if (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)
  1593. break;
  1594. }
  1595. mutex_lock(&sde_kms->secure_transition_lock);
  1596. switch (translation_mode) {
  1597. case SDE_DRM_FB_SEC_DIR_TRANS:
  1598. _sde_drm_fb_sec_dir_trans(smmu_state, secure_level,
  1599. catalog, old_valid_fb, &ops);
  1600. break;
  1601. case SDE_DRM_FB_SEC:
  1602. case SDE_DRM_FB_NON_SEC:
  1603. _sde_drm_fb_transactions(smmu_state, catalog,
  1604. old_valid_fb, post_commit, &ops);
  1605. break;
  1606. default:
  1607. SDE_ERROR("crtc%d: invalid plane fb_mode %d\n",
  1608. DRMID(crtc), translation_mode);
  1609. ops = -EINVAL;
  1610. }
  1611. /* log only during actual transition times */
  1612. if (ops) {
  1613. SDE_DEBUG("crtc%d: state%d sec%d sec_lvl%d type%d ops%x\n",
  1614. DRMID(crtc), smmu_state->state,
  1615. secure_level, smmu_state->secure_level,
  1616. smmu_state->transition_type, ops);
  1617. SDE_EVT32(DRMID(crtc), secure_level, translation_mode,
  1618. smmu_state->state, smmu_state->transition_type,
  1619. smmu_state->secure_level, old_valid_fb,
  1620. post_commit, ops, SDE_EVTLOG_FUNC_EXIT);
  1621. }
  1622. mutex_unlock(&sde_kms->secure_transition_lock);
  1623. return ops;
  1624. }
  1625. /**
  1626. * _sde_crtc_setup_scaler3_lut - Set up scaler lut
  1627. * LUTs are configured only once during boot
  1628. * @sde_crtc: Pointer to sde crtc
  1629. * @cstate: Pointer to sde crtc state
  1630. */
  1631. static int _sde_crtc_set_dest_scaler_lut(struct sde_crtc *sde_crtc,
  1632. struct sde_crtc_state *cstate, uint32_t lut_idx)
  1633. {
  1634. struct sde_hw_scaler3_lut_cfg *cfg;
  1635. struct sde_kms *sde_kms;
  1636. u32 *lut_data = NULL;
  1637. size_t len = 0;
  1638. int ret = 0;
  1639. if (!sde_crtc || !cstate) {
  1640. SDE_ERROR("invalid args\n");
  1641. return -EINVAL;
  1642. }
  1643. sde_kms = _sde_crtc_get_kms(&sde_crtc->base);
  1644. if (!sde_kms)
  1645. return -EINVAL;
  1646. if (is_qseed3_rev_qseed3lite(sde_kms->catalog))
  1647. return 0;
  1648. lut_data = msm_property_get_blob(&sde_crtc->property_info,
  1649. &cstate->property_state, &len, lut_idx);
  1650. if (!lut_data || !len) {
  1651. SDE_DEBUG("%s: lut(%d): cleared: %pK, %zu\n", sde_crtc->name,
  1652. lut_idx, lut_data, len);
  1653. lut_data = NULL;
  1654. len = 0;
  1655. }
  1656. cfg = &cstate->scl3_lut_cfg;
  1657. switch (lut_idx) {
  1658. case CRTC_PROP_DEST_SCALER_LUT_ED:
  1659. cfg->dir_lut = lut_data;
  1660. cfg->dir_len = len;
  1661. break;
  1662. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  1663. cfg->cir_lut = lut_data;
  1664. cfg->cir_len = len;
  1665. break;
  1666. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  1667. cfg->sep_lut = lut_data;
  1668. cfg->sep_len = len;
  1669. break;
  1670. default:
  1671. ret = -EINVAL;
  1672. SDE_ERROR("%s:invalid LUT idx(%d)\n", sde_crtc->name, lut_idx);
  1673. SDE_EVT32(DRMID(&sde_crtc->base), lut_idx, SDE_EVTLOG_ERROR);
  1674. break;
  1675. }
  1676. cfg->is_configured = cfg->dir_lut && cfg->cir_lut && cfg->sep_lut;
  1677. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), ret, lut_idx, len,
  1678. cfg->is_configured);
  1679. return ret;
  1680. }
  1681. void sde_crtc_timeline_status(struct drm_crtc *crtc)
  1682. {
  1683. struct sde_crtc *sde_crtc;
  1684. if (!crtc) {
  1685. SDE_ERROR("invalid crtc\n");
  1686. return;
  1687. }
  1688. sde_crtc = to_sde_crtc(crtc);
  1689. sde_fence_timeline_status(sde_crtc->output_fence, &crtc->base);
  1690. }
  1691. static int _sde_validate_hw_resources(struct sde_crtc *sde_crtc)
  1692. {
  1693. int i;
  1694. /**
  1695. * Check if sufficient hw resources are
  1696. * available as per target caps & topology
  1697. */
  1698. if (!sde_crtc) {
  1699. SDE_ERROR("invalid argument\n");
  1700. return -EINVAL;
  1701. }
  1702. if (!sde_crtc->num_mixers ||
  1703. sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
  1704. SDE_ERROR("%s: invalid number mixers: %d\n",
  1705. sde_crtc->name, sde_crtc->num_mixers);
  1706. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1707. SDE_EVTLOG_ERROR);
  1708. return -EINVAL;
  1709. }
  1710. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1711. if (!sde_crtc->mixers[i].hw_lm || !sde_crtc->mixers[i].hw_ctl
  1712. || !sde_crtc->mixers[i].hw_ds) {
  1713. SDE_ERROR("%s:insufficient resources for mixer(%d)\n",
  1714. sde_crtc->name, i);
  1715. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1716. i, sde_crtc->mixers[i].hw_lm,
  1717. sde_crtc->mixers[i].hw_ctl,
  1718. sde_crtc->mixers[i].hw_ds, SDE_EVTLOG_ERROR);
  1719. return -EINVAL;
  1720. }
  1721. }
  1722. return 0;
  1723. }
  1724. /**
  1725. * _sde_crtc_dest_scaler_setup - Set up dest scaler block
  1726. * @crtc: Pointer to drm crtc
  1727. */
  1728. static void _sde_crtc_dest_scaler_setup(struct drm_crtc *crtc)
  1729. {
  1730. struct sde_crtc *sde_crtc;
  1731. struct sde_crtc_state *cstate;
  1732. struct sde_hw_mixer *hw_lm;
  1733. struct sde_hw_ctl *hw_ctl;
  1734. struct sde_hw_ds *hw_ds;
  1735. struct sde_hw_ds_cfg *cfg;
  1736. struct sde_kms *kms;
  1737. u32 op_mode = 0;
  1738. u32 lm_idx = 0, num_mixers = 0;
  1739. int i, count = 0;
  1740. if (!crtc)
  1741. return;
  1742. sde_crtc = to_sde_crtc(crtc);
  1743. cstate = to_sde_crtc_state(crtc->state);
  1744. kms = _sde_crtc_get_kms(crtc);
  1745. num_mixers = sde_crtc->num_mixers;
  1746. count = cstate->num_ds;
  1747. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1748. SDE_EVT32(DRMID(crtc), num_mixers, count, cstate->dirty[0],
  1749. cstate->num_ds_enabled);
  1750. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  1751. SDE_DEBUG("no change in settings, skip commit\n");
  1752. } else if (!kms || !kms->catalog) {
  1753. SDE_ERROR("crtc%d:invalid parameters\n", crtc->base.id);
  1754. } else if (!kms->catalog->mdp[0].has_dest_scaler) {
  1755. SDE_DEBUG("dest scaler feature not supported\n");
  1756. } else if (_sde_validate_hw_resources(sde_crtc)) {
  1757. //do nothing
  1758. } else if ((!cstate->scl3_lut_cfg.is_configured) &&
  1759. (!is_qseed3_rev_qseed3lite(kms->catalog))) {
  1760. SDE_ERROR("crtc%d:no LUT data available\n", crtc->base.id);
  1761. } else {
  1762. for (i = 0; i < count; i++) {
  1763. cfg = &cstate->ds_cfg[i];
  1764. if (!cfg->flags)
  1765. continue;
  1766. lm_idx = cfg->idx;
  1767. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  1768. hw_ctl = sde_crtc->mixers[lm_idx].hw_ctl;
  1769. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  1770. /* Setup op mode - Dual/single */
  1771. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  1772. op_mode |= BIT(hw_ds->idx - DS_0);
  1773. if ((i == count-1) && hw_ds->ops.setup_opmode) {
  1774. op_mode |= (cstate->num_ds_enabled ==
  1775. CRTC_DUAL_MIXERS) ?
  1776. SDE_DS_OP_MODE_DUAL : 0;
  1777. hw_ds->ops.setup_opmode(hw_ds, op_mode);
  1778. SDE_EVT32_VERBOSE(DRMID(crtc), op_mode);
  1779. }
  1780. /* Setup scaler */
  1781. if ((cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE) ||
  1782. (cfg->flags &
  1783. SDE_DRM_DESTSCALER_ENHANCER_UPDATE)) {
  1784. if (hw_ds->ops.setup_scaler)
  1785. hw_ds->ops.setup_scaler(hw_ds,
  1786. &cfg->scl3_cfg,
  1787. &cstate->scl3_lut_cfg);
  1788. }
  1789. /*
  1790. * Dest scaler shares the flush bit of the LM in control
  1791. */
  1792. if (hw_ctl && hw_ctl->ops.update_bitmask_mixer)
  1793. hw_ctl->ops.update_bitmask_mixer(
  1794. hw_ctl, hw_lm->idx, 1);
  1795. }
  1796. }
  1797. }
  1798. static void sde_crtc_frame_event_cb(void *data, u32 event)
  1799. {
  1800. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1801. struct sde_crtc *sde_crtc;
  1802. struct msm_drm_private *priv;
  1803. struct sde_crtc_frame_event *fevent;
  1804. struct sde_kms_frame_event_cb_data *cb_data;
  1805. struct drm_plane *plane;
  1806. u32 ubwc_error;
  1807. unsigned long flags;
  1808. u32 crtc_id;
  1809. cb_data = (struct sde_kms_frame_event_cb_data *)data;
  1810. if (!data) {
  1811. SDE_ERROR("invalid parameters\n");
  1812. return;
  1813. }
  1814. crtc = cb_data->crtc;
  1815. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  1816. SDE_ERROR("invalid parameters\n");
  1817. return;
  1818. }
  1819. sde_crtc = to_sde_crtc(crtc);
  1820. priv = crtc->dev->dev_private;
  1821. crtc_id = drm_crtc_index(crtc);
  1822. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1823. SDE_EVT32_VERBOSE(DRMID(crtc), event);
  1824. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  1825. fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
  1826. struct sde_crtc_frame_event, list);
  1827. if (fevent)
  1828. list_del_init(&fevent->list);
  1829. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  1830. if (!fevent) {
  1831. SDE_ERROR("crtc%d event %d overflow\n",
  1832. crtc->base.id, event);
  1833. SDE_EVT32(DRMID(crtc), event);
  1834. return;
  1835. }
  1836. /* log and clear plane ubwc errors if any */
  1837. if (event & (SDE_ENCODER_FRAME_EVENT_ERROR
  1838. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  1839. | SDE_ENCODER_FRAME_EVENT_DONE)) {
  1840. drm_for_each_plane_mask(plane, crtc->dev,
  1841. sde_crtc->plane_mask_old) {
  1842. ubwc_error = sde_plane_get_ubwc_error(plane);
  1843. if (ubwc_error) {
  1844. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1845. ubwc_error, SDE_EVTLOG_ERROR);
  1846. SDE_DEBUG("crtc%d plane %d ubwc_error %d\n",
  1847. DRMID(crtc), DRMID(plane),
  1848. ubwc_error);
  1849. sde_plane_clear_ubwc_error(plane);
  1850. }
  1851. }
  1852. }
  1853. fevent->event = event;
  1854. fevent->crtc = crtc;
  1855. fevent->connector = cb_data->connector;
  1856. fevent->ts = ktime_get();
  1857. kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
  1858. }
  1859. void sde_crtc_prepare_commit(struct drm_crtc *crtc,
  1860. struct drm_crtc_state *old_state)
  1861. {
  1862. struct drm_device *dev;
  1863. struct sde_crtc *sde_crtc;
  1864. struct sde_crtc_state *cstate;
  1865. struct drm_connector *conn;
  1866. struct drm_encoder *encoder;
  1867. struct drm_connector_list_iter conn_iter;
  1868. if (!crtc || !crtc->state) {
  1869. SDE_ERROR("invalid crtc\n");
  1870. return;
  1871. }
  1872. dev = crtc->dev;
  1873. sde_crtc = to_sde_crtc(crtc);
  1874. cstate = to_sde_crtc_state(crtc->state);
  1875. SDE_EVT32_VERBOSE(DRMID(crtc));
  1876. SDE_ATRACE_BEGIN("sde_crtc_prepare_commit");
  1877. /* identify connectors attached to this crtc */
  1878. cstate->num_connectors = 0;
  1879. drm_connector_list_iter_begin(dev, &conn_iter);
  1880. drm_for_each_connector_iter(conn, &conn_iter)
  1881. if (conn->state && conn->state->crtc == crtc &&
  1882. cstate->num_connectors < MAX_CONNECTORS) {
  1883. encoder = conn->state->best_encoder;
  1884. if (encoder)
  1885. sde_encoder_register_frame_event_callback(
  1886. encoder,
  1887. sde_crtc_frame_event_cb,
  1888. crtc);
  1889. cstate->connectors[cstate->num_connectors++] = conn;
  1890. sde_connector_prepare_fence(conn);
  1891. }
  1892. drm_connector_list_iter_end(&conn_iter);
  1893. /* prepare main output fence */
  1894. sde_fence_prepare(sde_crtc->output_fence);
  1895. SDE_ATRACE_END("sde_crtc_prepare_commit");
  1896. }
  1897. /**
  1898. * sde_crtc_complete_flip - signal pending page_flip events
  1899. * Any pending vblank events are added to the vblank_event_list
  1900. * so that the next vblank interrupt shall signal them.
  1901. * However PAGE_FLIP events are not handled through the vblank_event_list.
  1902. * This API signals any pending PAGE_FLIP events requested through
  1903. * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event.
  1904. * if file!=NULL, this is preclose potential cancel-flip path
  1905. * @crtc: Pointer to drm crtc structure
  1906. * @file: Pointer to drm file
  1907. */
  1908. void sde_crtc_complete_flip(struct drm_crtc *crtc,
  1909. struct drm_file *file)
  1910. {
  1911. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1912. struct drm_device *dev = crtc->dev;
  1913. struct drm_pending_vblank_event *event;
  1914. unsigned long flags;
  1915. spin_lock_irqsave(&dev->event_lock, flags);
  1916. event = sde_crtc->event;
  1917. if (!event)
  1918. goto end;
  1919. /*
  1920. * if regular vblank case (!file) or if cancel-flip from
  1921. * preclose on file that requested flip, then send the
  1922. * event:
  1923. */
  1924. if (!file || (event->base.file_priv == file)) {
  1925. sde_crtc->event = NULL;
  1926. DRM_DEBUG_VBL("%s: send event: %pK\n",
  1927. sde_crtc->name, event);
  1928. SDE_EVT32_VERBOSE(DRMID(crtc));
  1929. drm_crtc_send_vblank_event(crtc, event);
  1930. }
  1931. end:
  1932. spin_unlock_irqrestore(&dev->event_lock, flags);
  1933. }
  1934. enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc,
  1935. struct drm_crtc_state *cstate)
  1936. {
  1937. struct drm_encoder *encoder;
  1938. if (!crtc || !crtc->dev || !cstate) {
  1939. SDE_ERROR("invalid crtc\n");
  1940. return INTF_MODE_NONE;
  1941. }
  1942. drm_for_each_encoder_mask(encoder, crtc->dev,
  1943. cstate->encoder_mask) {
  1944. /* continue if copy encoder is encountered */
  1945. if (sde_encoder_in_clone_mode(encoder))
  1946. continue;
  1947. return sde_encoder_get_intf_mode(encoder);
  1948. }
  1949. return INTF_MODE_NONE;
  1950. }
  1951. u32 sde_crtc_get_fps_mode(struct drm_crtc *crtc)
  1952. {
  1953. struct drm_encoder *encoder;
  1954. if (!crtc || !crtc->dev) {
  1955. SDE_ERROR("invalid crtc\n");
  1956. return INTF_MODE_NONE;
  1957. }
  1958. drm_for_each_encoder(encoder, crtc->dev)
  1959. if ((encoder->crtc == crtc)
  1960. && !sde_encoder_in_cont_splash(encoder))
  1961. return sde_encoder_get_fps(encoder);
  1962. return 0;
  1963. }
  1964. static void sde_crtc_vblank_cb(void *data)
  1965. {
  1966. struct drm_crtc *crtc = (struct drm_crtc *)data;
  1967. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1968. /* keep statistics on vblank callback - with auto reset via debugfs */
  1969. if (ktime_compare(sde_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
  1970. sde_crtc->vblank_cb_time = ktime_get();
  1971. else
  1972. sde_crtc->vblank_cb_count++;
  1973. sde_crtc->vblank_last_cb_time = ktime_get();
  1974. sysfs_notify_dirent(sde_crtc->vsync_event_sf);
  1975. drm_crtc_handle_vblank(crtc);
  1976. DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
  1977. SDE_EVT32_VERBOSE(DRMID(crtc));
  1978. }
  1979. static void _sde_crtc_retire_event(struct drm_connector *connector,
  1980. ktime_t ts, enum sde_fence_event fence_event)
  1981. {
  1982. if (!connector) {
  1983. SDE_ERROR("invalid param\n");
  1984. return;
  1985. }
  1986. SDE_ATRACE_BEGIN("signal_retire_fence");
  1987. sde_connector_complete_commit(connector, ts, fence_event);
  1988. SDE_ATRACE_END("signal_retire_fence");
  1989. }
  1990. static void sde_crtc_frame_event_work(struct kthread_work *work)
  1991. {
  1992. struct msm_drm_private *priv;
  1993. struct sde_crtc_frame_event *fevent;
  1994. struct drm_crtc *crtc;
  1995. struct sde_crtc *sde_crtc;
  1996. struct sde_kms *sde_kms;
  1997. unsigned long flags;
  1998. bool in_clone_mode = false;
  1999. if (!work) {
  2000. SDE_ERROR("invalid work handle\n");
  2001. return;
  2002. }
  2003. fevent = container_of(work, struct sde_crtc_frame_event, work);
  2004. if (!fevent->crtc || !fevent->crtc->state) {
  2005. SDE_ERROR("invalid crtc\n");
  2006. return;
  2007. }
  2008. crtc = fevent->crtc;
  2009. sde_crtc = to_sde_crtc(crtc);
  2010. sde_kms = _sde_crtc_get_kms(crtc);
  2011. if (!sde_kms) {
  2012. SDE_ERROR("invalid kms handle\n");
  2013. return;
  2014. }
  2015. priv = sde_kms->dev->dev_private;
  2016. SDE_ATRACE_BEGIN("crtc_frame_event");
  2017. SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
  2018. ktime_to_ns(fevent->ts));
  2019. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY);
  2020. in_clone_mode = (fevent->event & SDE_ENCODER_FRAME_EVENT_CWB_DONE) ?
  2021. true : false;
  2022. if (!in_clone_mode && (fevent->event & (SDE_ENCODER_FRAME_EVENT_ERROR
  2023. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  2024. | SDE_ENCODER_FRAME_EVENT_DONE))) {
  2025. if (atomic_read(&sde_crtc->frame_pending) < 1) {
  2026. /* this should not happen */
  2027. SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
  2028. crtc->base.id,
  2029. ktime_to_ns(fevent->ts),
  2030. atomic_read(&sde_crtc->frame_pending));
  2031. SDE_EVT32(DRMID(crtc), fevent->event,
  2032. SDE_EVTLOG_FUNC_CASE1);
  2033. } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
  2034. /* release bandwidth and other resources */
  2035. SDE_DEBUG("crtc%d ts:%lld last pending\n",
  2036. crtc->base.id,
  2037. ktime_to_ns(fevent->ts));
  2038. SDE_EVT32(DRMID(crtc), fevent->event,
  2039. SDE_EVTLOG_FUNC_CASE2);
  2040. sde_core_perf_crtc_release_bw(crtc);
  2041. } else {
  2042. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
  2043. SDE_EVTLOG_FUNC_CASE3);
  2044. }
  2045. }
  2046. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) {
  2047. SDE_ATRACE_BEGIN("signal_release_fence");
  2048. sde_fence_signal(sde_crtc->output_fence, fevent->ts,
  2049. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2050. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2051. SDE_ATRACE_END("signal_release_fence");
  2052. }
  2053. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  2054. /* this api should be called without spin_lock */
  2055. _sde_crtc_retire_event(fevent->connector, fevent->ts,
  2056. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2057. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2058. if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
  2059. SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
  2060. crtc->base.id, ktime_to_ns(fevent->ts));
  2061. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  2062. list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
  2063. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  2064. SDE_ATRACE_END("crtc_frame_event");
  2065. }
  2066. void sde_crtc_complete_commit(struct drm_crtc *crtc,
  2067. struct drm_crtc_state *old_state)
  2068. {
  2069. struct sde_crtc *sde_crtc;
  2070. if (!crtc || !crtc->state) {
  2071. SDE_ERROR("invalid crtc\n");
  2072. return;
  2073. }
  2074. sde_crtc = to_sde_crtc(crtc);
  2075. SDE_EVT32_VERBOSE(DRMID(crtc));
  2076. sde_core_perf_crtc_update(crtc, 0, false);
  2077. }
  2078. /**
  2079. * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
  2080. * @cstate: Pointer to sde crtc state
  2081. */
  2082. static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
  2083. {
  2084. if (!cstate) {
  2085. SDE_ERROR("invalid cstate\n");
  2086. return;
  2087. }
  2088. cstate->input_fence_timeout_ns =
  2089. sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
  2090. cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
  2091. }
  2092. /**
  2093. * _sde_crtc_clear_dim_layers_v1 - clear all dim layer settings
  2094. * @cstate: Pointer to sde crtc state
  2095. */
  2096. static void _sde_crtc_clear_dim_layers_v1(struct sde_crtc_state *cstate)
  2097. {
  2098. u32 i;
  2099. if (!cstate)
  2100. return;
  2101. for (i = 0; i < cstate->num_dim_layers; i++)
  2102. memset(&cstate->dim_layer[i], 0, sizeof(cstate->dim_layer[i]));
  2103. cstate->num_dim_layers = 0;
  2104. }
  2105. /**
  2106. * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  2107. * @cstate: Pointer to sde crtc state
  2108. * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
  2109. */
  2110. static void _sde_crtc_set_dim_layer_v1(struct drm_crtc *crtc,
  2111. struct sde_crtc_state *cstate, void __user *usr_ptr)
  2112. {
  2113. struct sde_drm_dim_layer_v1 dim_layer_v1;
  2114. struct sde_drm_dim_layer_cfg *user_cfg;
  2115. struct sde_hw_dim_layer *dim_layer;
  2116. u32 count, i;
  2117. struct sde_kms *kms;
  2118. if (!crtc || !cstate) {
  2119. SDE_ERROR("invalid crtc or cstate\n");
  2120. return;
  2121. }
  2122. dim_layer = cstate->dim_layer;
  2123. if (!usr_ptr) {
  2124. /* usr_ptr is null when setting the default property value */
  2125. _sde_crtc_clear_dim_layers_v1(cstate);
  2126. SDE_DEBUG("dim_layer data removed\n");
  2127. goto clear;
  2128. }
  2129. kms = _sde_crtc_get_kms(crtc);
  2130. if (!kms || !kms->catalog) {
  2131. SDE_ERROR("invalid kms\n");
  2132. return;
  2133. }
  2134. if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
  2135. SDE_ERROR("failed to copy dim_layer data\n");
  2136. return;
  2137. }
  2138. count = dim_layer_v1.num_layers;
  2139. if (count > SDE_MAX_DIM_LAYERS) {
  2140. SDE_ERROR("invalid number of dim_layers:%d", count);
  2141. return;
  2142. }
  2143. /* populate from user space */
  2144. cstate->num_dim_layers = count;
  2145. for (i = 0; i < count; i++) {
  2146. user_cfg = &dim_layer_v1.layer_cfg[i];
  2147. dim_layer[i].flags = user_cfg->flags;
  2148. dim_layer[i].stage = (kms->catalog->has_base_layer) ?
  2149. user_cfg->stage : user_cfg->stage +
  2150. SDE_STAGE_0;
  2151. dim_layer[i].rect.x = user_cfg->rect.x1;
  2152. dim_layer[i].rect.y = user_cfg->rect.y1;
  2153. dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1;
  2154. dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1;
  2155. dim_layer[i].color_fill = (struct sde_mdss_color) {
  2156. user_cfg->color_fill.color_0,
  2157. user_cfg->color_fill.color_1,
  2158. user_cfg->color_fill.color_2,
  2159. user_cfg->color_fill.color_3,
  2160. };
  2161. SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n",
  2162. i, dim_layer[i].flags, dim_layer[i].stage);
  2163. SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n",
  2164. dim_layer[i].rect.x, dim_layer[i].rect.y,
  2165. dim_layer[i].rect.w, dim_layer[i].rect.h,
  2166. dim_layer[i].color_fill.color_0,
  2167. dim_layer[i].color_fill.color_1,
  2168. dim_layer[i].color_fill.color_2,
  2169. dim_layer[i].color_fill.color_3);
  2170. }
  2171. clear:
  2172. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  2173. }
  2174. /**
  2175. * _sde_crtc_set_dest_scaler - copy dest scaler settings from userspace
  2176. * @sde_crtc : Pointer to sde crtc
  2177. * @cstate : Pointer to sde crtc state
  2178. * @usr_ptr: User ptr for sde_drm_dest_scaler_data struct
  2179. */
  2180. static int _sde_crtc_set_dest_scaler(struct sde_crtc *sde_crtc,
  2181. struct sde_crtc_state *cstate,
  2182. void __user *usr_ptr)
  2183. {
  2184. struct sde_drm_dest_scaler_data ds_data;
  2185. struct sde_drm_dest_scaler_cfg *ds_cfg_usr;
  2186. struct sde_drm_scaler_v2 scaler_v2;
  2187. void __user *scaler_v2_usr;
  2188. int i, count;
  2189. if (!sde_crtc || !cstate) {
  2190. SDE_ERROR("invalid sde_crtc/state\n");
  2191. return -EINVAL;
  2192. }
  2193. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  2194. if (!usr_ptr) {
  2195. SDE_DEBUG("ds data removed\n");
  2196. return 0;
  2197. }
  2198. if (copy_from_user(&ds_data, usr_ptr, sizeof(ds_data))) {
  2199. SDE_ERROR("%s:failed to copy dest scaler data from user\n",
  2200. sde_crtc->name);
  2201. return -EINVAL;
  2202. }
  2203. count = ds_data.num_dest_scaler;
  2204. if (!count) {
  2205. SDE_DEBUG("no ds data available\n");
  2206. return 0;
  2207. }
  2208. if (count > SDE_MAX_DS_COUNT) {
  2209. SDE_ERROR("%s: invalid config: num_ds(%d) max(%d)\n",
  2210. sde_crtc->name, count, SDE_MAX_DS_COUNT);
  2211. SDE_EVT32(DRMID(&sde_crtc->base), count, SDE_EVTLOG_ERROR);
  2212. return -EINVAL;
  2213. }
  2214. /* Populate from user space */
  2215. for (i = 0; i < count; i++) {
  2216. ds_cfg_usr = &ds_data.ds_cfg[i];
  2217. cstate->ds_cfg[i].idx = ds_cfg_usr->index;
  2218. cstate->ds_cfg[i].flags = ds_cfg_usr->flags;
  2219. cstate->ds_cfg[i].lm_width = ds_cfg_usr->lm_width;
  2220. cstate->ds_cfg[i].lm_height = ds_cfg_usr->lm_height;
  2221. memset(&scaler_v2, 0, sizeof(scaler_v2));
  2222. if (ds_cfg_usr->scaler_cfg) {
  2223. scaler_v2_usr =
  2224. (void __user *)((uintptr_t)ds_cfg_usr->scaler_cfg);
  2225. if (copy_from_user(&scaler_v2, scaler_v2_usr,
  2226. sizeof(scaler_v2))) {
  2227. SDE_ERROR("%s:scaler: copy from user failed\n",
  2228. sde_crtc->name);
  2229. return -EINVAL;
  2230. }
  2231. }
  2232. sde_set_scaler_v2(&cstate->ds_cfg[i].scl3_cfg, &scaler_v2);
  2233. SDE_DEBUG("en(%d)dir(%d)de(%d) src(%dx%d) dst(%dx%d)\n",
  2234. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2235. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2236. scaler_v2.dst_width, scaler_v2.dst_height);
  2237. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base),
  2238. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2239. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2240. scaler_v2.dst_width, scaler_v2.dst_height);
  2241. SDE_DEBUG("ds cfg[%d]-ndx(%d) flags(%d) lm(%dx%d)\n",
  2242. i, ds_cfg_usr->index, ds_cfg_usr->flags,
  2243. ds_cfg_usr->lm_width, ds_cfg_usr->lm_height);
  2244. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), i, ds_cfg_usr->index,
  2245. ds_cfg_usr->flags, ds_cfg_usr->lm_width,
  2246. ds_cfg_usr->lm_height);
  2247. }
  2248. cstate->num_ds = count;
  2249. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2250. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), count);
  2251. return 0;
  2252. }
  2253. static int _sde_crtc_check_dest_scaler_lm(struct drm_crtc *crtc,
  2254. struct drm_display_mode *mode, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2255. u32 prev_lm_width, u32 prev_lm_height)
  2256. {
  2257. if (cfg->lm_width > hdisplay || cfg->lm_height > mode->vdisplay
  2258. || !cfg->lm_width || !cfg->lm_height) {
  2259. SDE_ERROR("crtc%d: lm size[%d,%d] display [%d,%d]\n",
  2260. crtc->base.id, cfg->lm_width, cfg->lm_height,
  2261. hdisplay, mode->vdisplay);
  2262. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2263. hdisplay, mode->vdisplay, SDE_EVTLOG_ERROR);
  2264. return -E2BIG;
  2265. }
  2266. if (!prev_lm_width && !prev_lm_height) {
  2267. prev_lm_width = cfg->lm_width;
  2268. prev_lm_height = cfg->lm_height;
  2269. } else {
  2270. if (cfg->lm_width != prev_lm_width ||
  2271. cfg->lm_height != prev_lm_height) {
  2272. SDE_ERROR("crtc%d:lm left[%d,%d]right[%d %d]\n",
  2273. crtc->base.id, cfg->lm_width,
  2274. cfg->lm_height, prev_lm_width,
  2275. prev_lm_height);
  2276. SDE_EVT32(DRMID(crtc), cfg->lm_width,
  2277. cfg->lm_height, prev_lm_width,
  2278. prev_lm_height, SDE_EVTLOG_ERROR);
  2279. return -EINVAL;
  2280. }
  2281. }
  2282. return 0;
  2283. }
  2284. static int _sde_crtc_check_dest_scaler_cfg(struct drm_crtc *crtc,
  2285. struct sde_crtc *sde_crtc, struct drm_display_mode *mode,
  2286. struct sde_hw_ds *hw_ds, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2287. u32 max_in_width, u32 max_out_width)
  2288. {
  2289. if (cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE ||
  2290. cfg->flags & SDE_DRM_DESTSCALER_ENHANCER_UPDATE) {
  2291. /**
  2292. * Scaler src and dst width shouldn't exceed the maximum
  2293. * width limitation. Also, if there is no partial update
  2294. * dst width and height must match display resolution.
  2295. */
  2296. if (cfg->scl3_cfg.src_width[0] > max_in_width ||
  2297. cfg->scl3_cfg.dst_width > max_out_width ||
  2298. !cfg->scl3_cfg.src_width[0] ||
  2299. !cfg->scl3_cfg.dst_width ||
  2300. (!(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE)
  2301. && (cfg->scl3_cfg.dst_width != hdisplay ||
  2302. cfg->scl3_cfg.dst_height != mode->vdisplay))) {
  2303. SDE_ERROR("crtc%d: ", crtc->base.id);
  2304. SDE_ERROR("src_w(%d) dst(%dx%d) display(%dx%d)",
  2305. cfg->scl3_cfg.src_width[0],
  2306. cfg->scl3_cfg.dst_width,
  2307. cfg->scl3_cfg.dst_height,
  2308. hdisplay, mode->vdisplay);
  2309. SDE_ERROR("num_mixers(%d) flags(%d) ds-%d:\n",
  2310. sde_crtc->num_mixers, cfg->flags,
  2311. hw_ds->idx - DS_0);
  2312. SDE_ERROR("scale_en = %d, DE_en =%d\n",
  2313. cfg->scl3_cfg.enable,
  2314. cfg->scl3_cfg.de.enable);
  2315. SDE_EVT32(DRMID(crtc), cfg->scl3_cfg.enable,
  2316. cfg->scl3_cfg.de.enable, cfg->flags,
  2317. max_in_width, max_out_width,
  2318. cfg->scl3_cfg.src_width[0],
  2319. cfg->scl3_cfg.dst_width,
  2320. cfg->scl3_cfg.dst_height, hdisplay,
  2321. mode->vdisplay, sde_crtc->num_mixers,
  2322. SDE_EVTLOG_ERROR);
  2323. cfg->flags &=
  2324. ~SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2325. cfg->flags &=
  2326. ~SDE_DRM_DESTSCALER_ENHANCER_UPDATE;
  2327. return -EINVAL;
  2328. }
  2329. }
  2330. return 0;
  2331. }
  2332. static int _sde_crtc_check_dest_scaler_validate_ds(struct drm_crtc *crtc,
  2333. struct sde_crtc *sde_crtc, struct sde_crtc_state *cstate,
  2334. struct drm_display_mode *mode, struct sde_hw_ds *hw_ds,
  2335. struct sde_hw_ds_cfg *cfg, u32 hdisplay, u32 *num_ds_enable,
  2336. u32 prev_lm_width, u32 prev_lm_height, u32 max_in_width,
  2337. u32 max_out_width)
  2338. {
  2339. int i, ret;
  2340. u32 lm_idx;
  2341. for (i = 0; i < cstate->num_ds; i++) {
  2342. cfg = &cstate->ds_cfg[i];
  2343. lm_idx = cfg->idx;
  2344. /**
  2345. * Validate against topology
  2346. * No of dest scalers should match the num of mixers
  2347. * unless it is partial update left only/right only use case
  2348. */
  2349. if (lm_idx >= sde_crtc->num_mixers || (i != lm_idx &&
  2350. !(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2351. SDE_ERROR("crtc%d: ds_cfg id(%d):idx(%d), flags(%d)\n",
  2352. crtc->base.id, i, lm_idx, cfg->flags);
  2353. SDE_EVT32(DRMID(crtc), i, lm_idx, cfg->flags,
  2354. SDE_EVTLOG_ERROR);
  2355. return -EINVAL;
  2356. }
  2357. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  2358. if (!max_in_width && !max_out_width) {
  2359. max_in_width = hw_ds->scl->top->maxinputwidth;
  2360. max_out_width = hw_ds->scl->top->maxoutputwidth;
  2361. if (cstate->num_ds == CRTC_DUAL_MIXERS)
  2362. max_in_width -= SDE_DS_OVERFETCH_SIZE;
  2363. SDE_DEBUG("max DS width [%d,%d] for num_ds = %d\n",
  2364. max_in_width, max_out_width, cstate->num_ds);
  2365. }
  2366. /* Check LM width and height */
  2367. ret = _sde_crtc_check_dest_scaler_lm(crtc, mode, cfg, hdisplay,
  2368. prev_lm_width, prev_lm_height);
  2369. if (ret)
  2370. return ret;
  2371. /* Check scaler data */
  2372. ret = _sde_crtc_check_dest_scaler_cfg(crtc, sde_crtc, mode,
  2373. hw_ds, cfg, hdisplay,
  2374. max_in_width, max_out_width);
  2375. if (ret)
  2376. return ret;
  2377. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  2378. (*num_ds_enable)++;
  2379. SDE_DEBUG("ds[%d]: flags[0x%X]\n",
  2380. hw_ds->idx - DS_0, cfg->flags);
  2381. SDE_EVT32_VERBOSE(DRMID(crtc), hw_ds->idx - DS_0, cfg->flags);
  2382. }
  2383. return 0;
  2384. }
  2385. static void _sde_crtc_check_dest_scaler_data_disable(struct drm_crtc *crtc,
  2386. struct sde_crtc_state *cstate, struct sde_hw_ds_cfg *cfg,
  2387. u32 num_ds_enable)
  2388. {
  2389. int i;
  2390. SDE_DEBUG("dest scaler status : %d -> %d\n",
  2391. cstate->num_ds_enabled, num_ds_enable);
  2392. SDE_EVT32_VERBOSE(DRMID(crtc), cstate->num_ds_enabled, num_ds_enable,
  2393. cstate->num_ds, cstate->dirty[0]);
  2394. if (cstate->num_ds_enabled != num_ds_enable) {
  2395. /* Disabling destination scaler */
  2396. if (!num_ds_enable) {
  2397. for (i = 0; i < cstate->num_ds; i++) {
  2398. cfg = &cstate->ds_cfg[i];
  2399. cfg->idx = i;
  2400. /* Update scaler settings in disable case */
  2401. cfg->flags = SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2402. cfg->scl3_cfg.enable = 0;
  2403. cfg->scl3_cfg.de.enable = 0;
  2404. }
  2405. }
  2406. cstate->num_ds_enabled = num_ds_enable;
  2407. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2408. } else {
  2409. if (!cstate->num_ds_enabled)
  2410. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2411. }
  2412. }
  2413. /**
  2414. * _sde_crtc_check_dest_scaler_data - validate the dest scaler data
  2415. * @crtc : Pointer to drm crtc
  2416. * @state : Pointer to drm crtc state
  2417. */
  2418. static int _sde_crtc_check_dest_scaler_data(struct drm_crtc *crtc,
  2419. struct drm_crtc_state *state)
  2420. {
  2421. struct sde_crtc *sde_crtc;
  2422. struct sde_crtc_state *cstate;
  2423. struct drm_display_mode *mode;
  2424. struct sde_kms *kms;
  2425. struct sde_hw_ds *hw_ds = NULL;
  2426. struct sde_hw_ds_cfg *cfg = NULL;
  2427. u32 ret = 0;
  2428. u32 num_ds_enable = 0, hdisplay = 0;
  2429. u32 max_in_width = 0, max_out_width = 0;
  2430. u32 prev_lm_width = 0, prev_lm_height = 0;
  2431. if (!crtc || !state)
  2432. return -EINVAL;
  2433. sde_crtc = to_sde_crtc(crtc);
  2434. cstate = to_sde_crtc_state(state);
  2435. kms = _sde_crtc_get_kms(crtc);
  2436. mode = &state->adjusted_mode;
  2437. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2438. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  2439. SDE_DEBUG("dest scaler property not set, skip validation\n");
  2440. return 0;
  2441. }
  2442. if (!kms || !kms->catalog) {
  2443. SDE_ERROR("crtc%d: invalid parameters\n", crtc->base.id);
  2444. return -EINVAL;
  2445. }
  2446. if (!kms->catalog->mdp[0].has_dest_scaler) {
  2447. SDE_DEBUG("dest scaler feature not supported\n");
  2448. return 0;
  2449. }
  2450. if (!sde_crtc->num_mixers) {
  2451. SDE_DEBUG("mixers not allocated\n");
  2452. return 0;
  2453. }
  2454. ret = _sde_validate_hw_resources(sde_crtc);
  2455. if (ret)
  2456. goto err;
  2457. /**
  2458. * No of dest scalers shouldn't exceed hw ds block count and
  2459. * also, match the num of mixers unless it is partial update
  2460. * left only/right only use case - currently PU + DS is not supported
  2461. */
  2462. if (cstate->num_ds > kms->catalog->ds_count ||
  2463. ((cstate->num_ds != sde_crtc->num_mixers) &&
  2464. !(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2465. SDE_ERROR("crtc%d: num_ds(%d), hw_ds_cnt(%d) flags(%d)\n",
  2466. crtc->base.id, cstate->num_ds, kms->catalog->ds_count,
  2467. cstate->ds_cfg[0].flags);
  2468. ret = -EINVAL;
  2469. goto err;
  2470. }
  2471. /**
  2472. * Check if DS needs to be enabled or disabled
  2473. * In case of enable, validate the data
  2474. */
  2475. if (!(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_ENABLE)) {
  2476. SDE_DEBUG("disable dest scaler, num(%d) flags(%d)\n",
  2477. cstate->num_ds, cstate->ds_cfg[0].flags);
  2478. goto disable;
  2479. }
  2480. /* Display resolution */
  2481. hdisplay = mode->hdisplay/sde_crtc->num_mixers;
  2482. /* Validate the DS data */
  2483. ret = _sde_crtc_check_dest_scaler_validate_ds(crtc, sde_crtc, cstate,
  2484. mode, hw_ds, cfg, hdisplay, &num_ds_enable,
  2485. prev_lm_width, prev_lm_height,
  2486. max_in_width, max_out_width);
  2487. if (ret)
  2488. goto err;
  2489. disable:
  2490. _sde_crtc_check_dest_scaler_data_disable(crtc, cstate, cfg,
  2491. num_ds_enable);
  2492. return 0;
  2493. err:
  2494. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2495. return ret;
  2496. }
  2497. /**
  2498. * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences
  2499. * @crtc: Pointer to CRTC object
  2500. */
  2501. static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
  2502. {
  2503. struct drm_plane *plane = NULL;
  2504. uint32_t wait_ms = 1;
  2505. ktime_t kt_end, kt_wait;
  2506. int rc = 0;
  2507. SDE_DEBUG("\n");
  2508. if (!crtc || !crtc->state) {
  2509. SDE_ERROR("invalid crtc/state %pK\n", crtc);
  2510. return;
  2511. }
  2512. /* use monotonic timer to limit total fence wait time */
  2513. kt_end = ktime_add_ns(ktime_get(),
  2514. to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
  2515. /*
  2516. * Wait for fences sequentially, as all of them need to be signalled
  2517. * before we can proceed.
  2518. *
  2519. * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
  2520. * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
  2521. * that each plane can check its fence status and react appropriately
  2522. * if its fence has timed out. Call input fence wait multiple times if
  2523. * fence wait is interrupted due to interrupt call.
  2524. */
  2525. SDE_ATRACE_BEGIN("plane_wait_input_fence");
  2526. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2527. do {
  2528. kt_wait = ktime_sub(kt_end, ktime_get());
  2529. if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
  2530. wait_ms = ktime_to_ms(kt_wait);
  2531. else
  2532. wait_ms = 0;
  2533. rc = sde_plane_wait_input_fence(plane, wait_ms);
  2534. } while (wait_ms && rc == -ERESTARTSYS);
  2535. }
  2536. SDE_ATRACE_END("plane_wait_input_fence");
  2537. }
  2538. static void _sde_crtc_setup_mixer_for_encoder(
  2539. struct drm_crtc *crtc,
  2540. struct drm_encoder *enc)
  2541. {
  2542. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2543. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  2544. struct sde_rm *rm = &sde_kms->rm;
  2545. struct sde_crtc_mixer *mixer;
  2546. struct sde_hw_ctl *last_valid_ctl = NULL;
  2547. int i;
  2548. struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter, ds_iter;
  2549. sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
  2550. sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
  2551. sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
  2552. sde_rm_init_hw_iter(&ds_iter, enc->base.id, SDE_HW_BLK_DS);
  2553. /* Set up all the mixers and ctls reserved by this encoder */
  2554. for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
  2555. mixer = &sde_crtc->mixers[i];
  2556. if (!sde_rm_get_hw(rm, &lm_iter))
  2557. break;
  2558. mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  2559. /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
  2560. if (!sde_rm_get_hw(rm, &ctl_iter)) {
  2561. SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
  2562. mixer->hw_lm->idx - LM_0);
  2563. mixer->hw_ctl = last_valid_ctl;
  2564. } else {
  2565. mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
  2566. last_valid_ctl = mixer->hw_ctl;
  2567. sde_crtc->num_ctls++;
  2568. }
  2569. /* Shouldn't happen, mixers are always >= ctls */
  2570. if (!mixer->hw_ctl) {
  2571. SDE_ERROR("no valid ctls found for lm %d\n",
  2572. mixer->hw_lm->idx - LM_0);
  2573. return;
  2574. }
  2575. /* Dspp may be null */
  2576. (void) sde_rm_get_hw(rm, &dspp_iter);
  2577. mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw;
  2578. /* DS may be null */
  2579. (void) sde_rm_get_hw(rm, &ds_iter);
  2580. mixer->hw_ds = (struct sde_hw_ds *)ds_iter.hw;
  2581. mixer->encoder = enc;
  2582. sde_crtc->num_mixers++;
  2583. SDE_DEBUG("setup mixer %d: lm %d\n",
  2584. i, mixer->hw_lm->idx - LM_0);
  2585. SDE_DEBUG("setup mixer %d: ctl %d\n",
  2586. i, mixer->hw_ctl->idx - CTL_0);
  2587. if (mixer->hw_ds)
  2588. SDE_DEBUG("setup mixer %d: ds %d\n",
  2589. i, mixer->hw_ds->idx - DS_0);
  2590. }
  2591. }
  2592. static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
  2593. {
  2594. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2595. struct drm_encoder *enc;
  2596. sde_crtc->num_ctls = 0;
  2597. sde_crtc->num_mixers = 0;
  2598. sde_crtc->mixers_swapped = false;
  2599. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  2600. mutex_lock(&sde_crtc->crtc_lock);
  2601. /* Check for mixers on all encoders attached to this crtc */
  2602. list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
  2603. if (enc->crtc != crtc)
  2604. continue;
  2605. /* avoid overwriting mixers info from a copy encoder */
  2606. if (sde_encoder_in_clone_mode(enc))
  2607. continue;
  2608. _sde_crtc_setup_mixer_for_encoder(crtc, enc);
  2609. }
  2610. mutex_unlock(&sde_crtc->crtc_lock);
  2611. _sde_crtc_check_dest_scaler_data(crtc, crtc->state);
  2612. }
  2613. static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
  2614. {
  2615. int i;
  2616. struct sde_crtc_state *cstate;
  2617. cstate = to_sde_crtc_state(state);
  2618. cstate->is_ppsplit = false;
  2619. for (i = 0; i < cstate->num_connectors; i++) {
  2620. struct drm_connector *conn = cstate->connectors[i];
  2621. if (sde_connector_get_topology_name(conn) ==
  2622. SDE_RM_TOPOLOGY_PPSPLIT)
  2623. cstate->is_ppsplit = true;
  2624. }
  2625. }
  2626. static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc,
  2627. struct drm_crtc_state *state)
  2628. {
  2629. struct sde_crtc *sde_crtc;
  2630. struct sde_crtc_state *cstate;
  2631. struct drm_display_mode *adj_mode;
  2632. u32 crtc_split_width;
  2633. int i;
  2634. if (!crtc || !state) {
  2635. SDE_ERROR("invalid args\n");
  2636. return;
  2637. }
  2638. sde_crtc = to_sde_crtc(crtc);
  2639. cstate = to_sde_crtc_state(state);
  2640. adj_mode = &state->adjusted_mode;
  2641. crtc_split_width = sde_crtc_get_mixer_width(sde_crtc, cstate, adj_mode);
  2642. for (i = 0; i < sde_crtc->num_mixers; i++) {
  2643. cstate->lm_bounds[i].x = crtc_split_width * i;
  2644. cstate->lm_bounds[i].y = 0;
  2645. cstate->lm_bounds[i].w = crtc_split_width;
  2646. cstate->lm_bounds[i].h =
  2647. sde_crtc_get_mixer_height(sde_crtc, cstate, adj_mode);
  2648. memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i],
  2649. sizeof(cstate->lm_roi[i]));
  2650. SDE_EVT32_VERBOSE(DRMID(crtc), i,
  2651. cstate->lm_bounds[i].x, cstate->lm_bounds[i].y,
  2652. cstate->lm_bounds[i].w, cstate->lm_bounds[i].h);
  2653. SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i,
  2654. cstate->lm_roi[i].x, cstate->lm_roi[i].y,
  2655. cstate->lm_roi[i].w, cstate->lm_roi[i].h);
  2656. }
  2657. drm_mode_debug_printmodeline(adj_mode);
  2658. }
  2659. static void _sde_crtc_clear_all_blend_stages(struct sde_crtc *sde_crtc)
  2660. {
  2661. struct sde_crtc_mixer mixer;
  2662. /*
  2663. * Use mixer[0] to get hw_ctl which will use ops to clear
  2664. * all blendstages. Clear all blendstages will iterate through
  2665. * all mixers.
  2666. */
  2667. if (sde_crtc->num_mixers) {
  2668. mixer = sde_crtc->mixers[0];
  2669. if (mixer.hw_ctl && mixer.hw_ctl->ops.clear_all_blendstages)
  2670. mixer.hw_ctl->ops.clear_all_blendstages(mixer.hw_ctl);
  2671. }
  2672. }
  2673. static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
  2674. struct drm_crtc_state *old_state)
  2675. {
  2676. struct sde_crtc *sde_crtc;
  2677. struct drm_encoder *encoder;
  2678. struct drm_device *dev;
  2679. struct sde_kms *sde_kms;
  2680. struct sde_splash_display *splash_display;
  2681. bool cont_splash_enabled = false;
  2682. size_t i;
  2683. if (!crtc) {
  2684. SDE_ERROR("invalid crtc\n");
  2685. return;
  2686. }
  2687. if (!crtc->state->enable) {
  2688. SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
  2689. crtc->base.id, crtc->state->enable);
  2690. return;
  2691. }
  2692. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2693. SDE_ERROR("power resource is not enabled\n");
  2694. return;
  2695. }
  2696. sde_kms = _sde_crtc_get_kms(crtc);
  2697. if (!sde_kms)
  2698. return;
  2699. SDE_ATRACE_BEGIN("crtc_atomic_begin");
  2700. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2701. sde_crtc = to_sde_crtc(crtc);
  2702. dev = crtc->dev;
  2703. if (!sde_crtc->num_mixers) {
  2704. _sde_crtc_setup_mixers(crtc);
  2705. _sde_crtc_setup_is_ppsplit(crtc->state);
  2706. _sde_crtc_setup_lm_bounds(crtc, crtc->state);
  2707. _sde_crtc_clear_all_blend_stages(sde_crtc);
  2708. }
  2709. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2710. if (encoder->crtc != crtc)
  2711. continue;
  2712. /* encoder will trigger pending mask now */
  2713. sde_encoder_trigger_kickoff_pending(encoder);
  2714. }
  2715. /* update performance setting */
  2716. sde_core_perf_crtc_update(crtc, 1, false);
  2717. /*
  2718. * If no mixers have been allocated in sde_crtc_atomic_check(),
  2719. * it means we are trying to flush a CRTC whose state is disabled:
  2720. * nothing else needs to be done.
  2721. */
  2722. if (unlikely(!sde_crtc->num_mixers))
  2723. goto end;
  2724. _sde_crtc_blend_setup(crtc, old_state, true);
  2725. _sde_crtc_dest_scaler_setup(crtc);
  2726. /* cancel the idle notify delayed work */
  2727. if (sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
  2728. MSM_DISPLAY_VIDEO_MODE) &&
  2729. kthread_cancel_delayed_work_sync(&sde_crtc->idle_notify_work))
  2730. SDE_DEBUG("idle notify work cancelled\n");
  2731. /*
  2732. * Since CP properties use AXI buffer to program the
  2733. * HW, check if context bank is in attached state,
  2734. * apply color processing properties only if
  2735. * smmu state is attached,
  2736. */
  2737. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2738. splash_display = &sde_kms->splash_data.splash_display[i];
  2739. if (splash_display->cont_splash_enabled &&
  2740. splash_display->encoder &&
  2741. crtc == splash_display->encoder->crtc)
  2742. cont_splash_enabled = true;
  2743. }
  2744. if (sde_kms_is_cp_operation_allowed(sde_kms) &&
  2745. (cont_splash_enabled || sde_crtc->enabled))
  2746. sde_cp_crtc_apply_properties(crtc);
  2747. /*
  2748. * PP_DONE irq is only used by command mode for now.
  2749. * It is better to request pending before FLUSH and START trigger
  2750. * to make sure no pp_done irq missed.
  2751. * This is safe because no pp_done will happen before SW trigger
  2752. * in command mode.
  2753. */
  2754. end:
  2755. SDE_ATRACE_END("crtc_atomic_begin");
  2756. }
  2757. static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
  2758. struct drm_crtc_state *old_crtc_state)
  2759. {
  2760. struct drm_encoder *encoder;
  2761. struct sde_crtc *sde_crtc;
  2762. struct drm_device *dev;
  2763. struct drm_plane *plane;
  2764. struct msm_drm_private *priv;
  2765. struct msm_drm_thread *event_thread;
  2766. struct sde_crtc_state *cstate;
  2767. struct sde_kms *sde_kms;
  2768. int idle_time = 0;
  2769. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  2770. SDE_ERROR("invalid crtc\n");
  2771. return;
  2772. }
  2773. if (!crtc->state->enable) {
  2774. SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
  2775. crtc->base.id, crtc->state->enable);
  2776. return;
  2777. }
  2778. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2779. SDE_ERROR("power resource is not enabled\n");
  2780. return;
  2781. }
  2782. sde_kms = _sde_crtc_get_kms(crtc);
  2783. if (!sde_kms) {
  2784. SDE_ERROR("invalid kms\n");
  2785. return;
  2786. }
  2787. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2788. sde_crtc = to_sde_crtc(crtc);
  2789. cstate = to_sde_crtc_state(crtc->state);
  2790. dev = crtc->dev;
  2791. priv = dev->dev_private;
  2792. if (crtc->index >= ARRAY_SIZE(priv->event_thread)) {
  2793. SDE_ERROR("invalid crtc index[%d]\n", crtc->index);
  2794. return;
  2795. }
  2796. event_thread = &priv->event_thread[crtc->index];
  2797. idle_time = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_TIMEOUT);
  2798. /*
  2799. * If no mixers has been allocated in sde_crtc_atomic_check(),
  2800. * it means we are trying to flush a CRTC whose state is disabled:
  2801. * nothing else needs to be done.
  2802. */
  2803. if (unlikely(!sde_crtc->num_mixers))
  2804. return;
  2805. SDE_ATRACE_BEGIN("sde_crtc_atomic_flush");
  2806. /*
  2807. * For planes without commit update, drm framework will not add
  2808. * those planes to current state since hardware update is not
  2809. * required. However, if those planes were power collapsed since
  2810. * last commit cycle, driver has to restore the hardware state
  2811. * of those planes explicitly here prior to plane flush.
  2812. * Also use this iteration to see if any plane requires cache,
  2813. * so during the perf update driver can activate/deactivate
  2814. * the cache accordingly.
  2815. */
  2816. sde_crtc->new_perf.llcc_active = false;
  2817. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2818. sde_plane_restore(plane);
  2819. if (sde_plane_is_cache_required(plane))
  2820. sde_crtc->new_perf.llcc_active = true;
  2821. }
  2822. /* wait for acquire fences before anything else is done */
  2823. _sde_crtc_wait_for_fences(crtc);
  2824. /* schedule the idle notify delayed work */
  2825. if (idle_time && sde_encoder_check_curr_mode(
  2826. sde_crtc->mixers[0].encoder,
  2827. MSM_DISPLAY_VIDEO_MODE)) {
  2828. kthread_queue_delayed_work(&event_thread->worker,
  2829. &sde_crtc->idle_notify_work,
  2830. msecs_to_jiffies(idle_time));
  2831. SDE_DEBUG("schedule idle notify work in %dms\n", idle_time);
  2832. }
  2833. if (!cstate->rsc_update) {
  2834. drm_for_each_encoder_mask(encoder, dev,
  2835. crtc->state->encoder_mask) {
  2836. cstate->rsc_client =
  2837. sde_encoder_get_rsc_client(encoder);
  2838. }
  2839. cstate->rsc_update = true;
  2840. }
  2841. /*
  2842. * Final plane updates: Give each plane a chance to complete all
  2843. * required writes/flushing before crtc's "flush
  2844. * everything" call below.
  2845. */
  2846. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2847. if (sde_kms->smmu_state.transition_error)
  2848. sde_plane_set_error(plane, true);
  2849. sde_plane_flush(plane);
  2850. }
  2851. /* Kickoff will be scheduled by outer layer */
  2852. SDE_ATRACE_END("sde_crtc_atomic_flush");
  2853. }
  2854. /**
  2855. * sde_crtc_destroy_state - state destroy hook
  2856. * @crtc: drm CRTC
  2857. * @state: CRTC state object to release
  2858. */
  2859. static void sde_crtc_destroy_state(struct drm_crtc *crtc,
  2860. struct drm_crtc_state *state)
  2861. {
  2862. struct sde_crtc *sde_crtc;
  2863. struct sde_crtc_state *cstate;
  2864. struct drm_encoder *enc;
  2865. struct sde_kms *sde_kms;
  2866. if (!crtc || !state) {
  2867. SDE_ERROR("invalid argument(s)\n");
  2868. return;
  2869. }
  2870. sde_crtc = to_sde_crtc(crtc);
  2871. cstate = to_sde_crtc_state(state);
  2872. sde_kms = _sde_crtc_get_kms(crtc);
  2873. if (!sde_kms) {
  2874. SDE_ERROR("invalid sde_kms\n");
  2875. return;
  2876. }
  2877. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2878. drm_for_each_encoder_mask(enc, crtc->dev, state->encoder_mask)
  2879. sde_rm_release(&sde_kms->rm, enc, true);
  2880. __drm_atomic_helper_crtc_destroy_state(state);
  2881. /* destroy value helper */
  2882. msm_property_destroy_state(&sde_crtc->property_info, cstate,
  2883. &cstate->property_state);
  2884. }
  2885. static int _sde_crtc_flush_event_thread(struct drm_crtc *crtc)
  2886. {
  2887. struct sde_crtc *sde_crtc;
  2888. int i;
  2889. if (!crtc) {
  2890. SDE_ERROR("invalid argument\n");
  2891. return -EINVAL;
  2892. }
  2893. sde_crtc = to_sde_crtc(crtc);
  2894. if (!atomic_read(&sde_crtc->frame_pending)) {
  2895. SDE_DEBUG("no frames pending\n");
  2896. return 0;
  2897. }
  2898. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  2899. /*
  2900. * flush all the event thread work to make sure all the
  2901. * FRAME_EVENTS from encoder are propagated to crtc
  2902. */
  2903. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  2904. if (list_empty(&sde_crtc->frame_events[i].list))
  2905. kthread_flush_work(&sde_crtc->frame_events[i].work);
  2906. }
  2907. SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  2908. return 0;
  2909. }
  2910. /**
  2911. * _sde_crtc_remove_pipe_flush - remove staged pipes from flush mask
  2912. * @crtc: Pointer to crtc structure
  2913. */
  2914. static void _sde_crtc_remove_pipe_flush(struct drm_crtc *crtc)
  2915. {
  2916. struct drm_plane *plane;
  2917. struct drm_plane_state *state;
  2918. struct sde_crtc *sde_crtc;
  2919. struct sde_crtc_mixer *mixer;
  2920. struct sde_hw_ctl *ctl;
  2921. if (!crtc)
  2922. return;
  2923. sde_crtc = to_sde_crtc(crtc);
  2924. mixer = sde_crtc->mixers;
  2925. if (!mixer)
  2926. return;
  2927. ctl = mixer->hw_ctl;
  2928. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2929. state = plane->state;
  2930. if (!state)
  2931. continue;
  2932. /* clear plane flush bitmask */
  2933. sde_plane_ctl_flush(plane, ctl, false);
  2934. }
  2935. }
  2936. /**
  2937. * sde_crtc_reset_hw - attempt hardware reset on errors
  2938. * @crtc: Pointer to DRM crtc instance
  2939. * @old_state: Pointer to crtc state for previous commit
  2940. * @recovery_events: Whether or not recovery events are enabled
  2941. * Returns: Zero if current commit should still be attempted
  2942. */
  2943. int sde_crtc_reset_hw(struct drm_crtc *crtc, struct drm_crtc_state *old_state,
  2944. bool recovery_events)
  2945. {
  2946. struct drm_plane *plane_halt[MAX_PLANES];
  2947. struct drm_plane *plane;
  2948. struct drm_encoder *encoder;
  2949. struct sde_crtc *sde_crtc;
  2950. struct sde_crtc_state *cstate;
  2951. struct sde_hw_ctl *ctl;
  2952. signed int i, plane_count;
  2953. int rc;
  2954. if (!crtc || !crtc->dev || !old_state || !crtc->state)
  2955. return -EINVAL;
  2956. sde_crtc = to_sde_crtc(crtc);
  2957. cstate = to_sde_crtc_state(crtc->state);
  2958. SDE_EVT32(DRMID(crtc), recovery_events, SDE_EVTLOG_FUNC_ENTRY);
  2959. /* optionally generate a panic instead of performing a h/w reset */
  2960. SDE_DBG_CTRL("stop_ftrace", "reset_hw_panic");
  2961. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2962. ctl = sde_crtc->mixers[i].hw_ctl;
  2963. if (!ctl || !ctl->ops.reset)
  2964. continue;
  2965. rc = ctl->ops.reset(ctl);
  2966. if (rc) {
  2967. SDE_DEBUG("crtc%d: ctl%d reset failure\n",
  2968. crtc->base.id, ctl->idx - CTL_0);
  2969. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0,
  2970. SDE_EVTLOG_ERROR);
  2971. break;
  2972. }
  2973. }
  2974. /* Early out if simple ctl reset succeeded */
  2975. if (i == sde_crtc->num_ctls)
  2976. return 0;
  2977. SDE_DEBUG("crtc%d: issuing hard reset\n", DRMID(crtc));
  2978. /* force all components in the system into reset at the same time */
  2979. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  2980. ctl = sde_crtc->mixers[i].hw_ctl;
  2981. if (!ctl || !ctl->ops.hard_reset)
  2982. continue;
  2983. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0);
  2984. ctl->ops.hard_reset(ctl, true);
  2985. }
  2986. plane_count = 0;
  2987. drm_atomic_crtc_state_for_each_plane(plane, old_state) {
  2988. if (plane_count >= ARRAY_SIZE(plane_halt))
  2989. break;
  2990. plane_halt[plane_count++] = plane;
  2991. sde_plane_halt_requests(plane, true);
  2992. sde_plane_set_revalidate(plane, true);
  2993. }
  2994. /* provide safe "border color only" commit configuration for later */
  2995. _sde_crtc_remove_pipe_flush(crtc);
  2996. _sde_crtc_blend_setup(crtc, old_state, false);
  2997. /* take h/w components out of reset */
  2998. for (i = plane_count - 1; i >= 0; --i)
  2999. sde_plane_halt_requests(plane_halt[i], false);
  3000. /* attempt to poll for start of frame cycle before reset release */
  3001. list_for_each_entry(encoder,
  3002. &crtc->dev->mode_config.encoder_list, head) {
  3003. if (encoder->crtc != crtc)
  3004. continue;
  3005. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3006. sde_encoder_poll_line_counts(encoder);
  3007. }
  3008. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3009. ctl = sde_crtc->mixers[i].hw_ctl;
  3010. if (!ctl || !ctl->ops.hard_reset)
  3011. continue;
  3012. ctl->ops.hard_reset(ctl, false);
  3013. }
  3014. list_for_each_entry(encoder,
  3015. &crtc->dev->mode_config.encoder_list, head) {
  3016. if (encoder->crtc != crtc)
  3017. continue;
  3018. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3019. sde_encoder_kickoff(encoder, false);
  3020. }
  3021. /* panic the device if VBIF is not in good state */
  3022. return !recovery_events ? 0 : -EAGAIN;
  3023. }
  3024. void sde_crtc_commit_kickoff(struct drm_crtc *crtc,
  3025. struct drm_crtc_state *old_state)
  3026. {
  3027. struct drm_encoder *encoder;
  3028. struct drm_device *dev;
  3029. struct sde_crtc *sde_crtc;
  3030. struct msm_drm_private *priv;
  3031. struct sde_kms *sde_kms;
  3032. struct sde_crtc_state *cstate;
  3033. bool is_error = false;
  3034. unsigned long flags;
  3035. enum sde_crtc_idle_pc_state idle_pc_state;
  3036. struct sde_encoder_kickoff_params params = { 0 };
  3037. if (!crtc) {
  3038. SDE_ERROR("invalid argument\n");
  3039. return;
  3040. }
  3041. dev = crtc->dev;
  3042. sde_crtc = to_sde_crtc(crtc);
  3043. sde_kms = _sde_crtc_get_kms(crtc);
  3044. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3045. SDE_ERROR("invalid argument\n");
  3046. return;
  3047. }
  3048. priv = sde_kms->dev->dev_private;
  3049. cstate = to_sde_crtc_state(crtc->state);
  3050. /*
  3051. * If no mixers has been allocated in sde_crtc_atomic_check(),
  3052. * it means we are trying to start a CRTC whose state is disabled:
  3053. * nothing else needs to be done.
  3054. */
  3055. if (unlikely(!sde_crtc->num_mixers))
  3056. return;
  3057. SDE_ATRACE_BEGIN("crtc_commit");
  3058. idle_pc_state = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_PC_STATE);
  3059. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3060. if (encoder->crtc != crtc)
  3061. continue;
  3062. /*
  3063. * Encoder will flush/start now, unless it has a tx pending.
  3064. * If so, it may delay and flush at an irq event (e.g. ppdone)
  3065. */
  3066. params.affected_displays = _sde_crtc_get_displays_affected(crtc,
  3067. crtc->state);
  3068. if (sde_encoder_prepare_for_kickoff(encoder, &params))
  3069. sde_crtc->needs_hw_reset = true;
  3070. if (idle_pc_state != IDLE_PC_NONE)
  3071. sde_encoder_control_idle_pc(encoder,
  3072. (idle_pc_state == IDLE_PC_ENABLE) ? true : false);
  3073. }
  3074. /*
  3075. * Optionally attempt h/w recovery if any errors were detected while
  3076. * preparing for the kickoff
  3077. */
  3078. if (sde_crtc->needs_hw_reset) {
  3079. sde_crtc->frame_trigger_mode = params.frame_trigger_mode;
  3080. if (sde_crtc->frame_trigger_mode
  3081. != FRAME_DONE_WAIT_POSTED_START &&
  3082. sde_crtc_reset_hw(crtc, old_state,
  3083. params.recovery_events_enabled))
  3084. is_error = true;
  3085. sde_crtc->needs_hw_reset = false;
  3086. }
  3087. sde_crtc_calc_fps(sde_crtc);
  3088. SDE_ATRACE_BEGIN("flush_event_thread");
  3089. _sde_crtc_flush_event_thread(crtc);
  3090. SDE_ATRACE_END("flush_event_thread");
  3091. sde_crtc->plane_mask_old = crtc->state->plane_mask;
  3092. if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
  3093. /* acquire bandwidth and other resources */
  3094. SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
  3095. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1);
  3096. } else {
  3097. SDE_DEBUG("crtc%d commit\n", crtc->base.id);
  3098. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2);
  3099. }
  3100. sde_crtc->play_count++;
  3101. sde_vbif_clear_errors(sde_kms);
  3102. if (is_error) {
  3103. _sde_crtc_remove_pipe_flush(crtc);
  3104. _sde_crtc_blend_setup(crtc, old_state, false);
  3105. }
  3106. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3107. if (encoder->crtc != crtc)
  3108. continue;
  3109. sde_encoder_kickoff(encoder, false);
  3110. }
  3111. /* store the event after frame trigger */
  3112. if (sde_crtc->event) {
  3113. WARN_ON(sde_crtc->event);
  3114. } else {
  3115. spin_lock_irqsave(&dev->event_lock, flags);
  3116. sde_crtc->event = crtc->state->event;
  3117. spin_unlock_irqrestore(&dev->event_lock, flags);
  3118. }
  3119. SDE_ATRACE_END("crtc_commit");
  3120. }
  3121. /**
  3122. * _sde_crtc_vblank_enable_no_lock - update power resource and vblank request
  3123. * @sde_crtc: Pointer to sde crtc structure
  3124. * @enable: Whether to enable/disable vblanks
  3125. *
  3126. * @Return: error code
  3127. */
  3128. static int _sde_crtc_vblank_enable_no_lock(
  3129. struct sde_crtc *sde_crtc, bool enable)
  3130. {
  3131. struct drm_crtc *crtc;
  3132. struct drm_encoder *enc;
  3133. if (!sde_crtc) {
  3134. SDE_ERROR("invalid crtc\n");
  3135. return -EINVAL;
  3136. }
  3137. crtc = &sde_crtc->base;
  3138. if (enable) {
  3139. int ret;
  3140. /* drop lock since power crtc cb may try to re-acquire lock */
  3141. mutex_unlock(&sde_crtc->crtc_lock);
  3142. ret = pm_runtime_get_sync(crtc->dev->dev);
  3143. mutex_lock(&sde_crtc->crtc_lock);
  3144. if (ret < 0)
  3145. return ret;
  3146. drm_for_each_encoder_mask(enc, crtc->dev,
  3147. crtc->state->encoder_mask) {
  3148. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3149. sde_crtc->enabled);
  3150. sde_encoder_register_vblank_callback(enc,
  3151. sde_crtc_vblank_cb, (void *)crtc);
  3152. }
  3153. } else {
  3154. drm_for_each_encoder_mask(enc, crtc->dev,
  3155. crtc->state->encoder_mask) {
  3156. SDE_EVT32(DRMID(&sde_crtc->base), DRMID(enc), enable,
  3157. sde_crtc->enabled);
  3158. sde_encoder_register_vblank_callback(enc, NULL, NULL);
  3159. }
  3160. /* drop lock since power crtc cb may try to re-acquire lock */
  3161. mutex_unlock(&sde_crtc->crtc_lock);
  3162. pm_runtime_put_sync(crtc->dev->dev);
  3163. mutex_lock(&sde_crtc->crtc_lock);
  3164. }
  3165. return 0;
  3166. }
  3167. /**
  3168. * sde_crtc_duplicate_state - state duplicate hook
  3169. * @crtc: Pointer to drm crtc structure
  3170. * @Returns: Pointer to new drm_crtc_state structure
  3171. */
  3172. static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
  3173. {
  3174. struct sde_crtc *sde_crtc;
  3175. struct sde_crtc_state *cstate, *old_cstate;
  3176. if (!crtc || !crtc->state) {
  3177. SDE_ERROR("invalid argument(s)\n");
  3178. return NULL;
  3179. }
  3180. sde_crtc = to_sde_crtc(crtc);
  3181. old_cstate = to_sde_crtc_state(crtc->state);
  3182. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3183. if (!cstate) {
  3184. SDE_ERROR("failed to allocate state\n");
  3185. return NULL;
  3186. }
  3187. /* duplicate value helper */
  3188. msm_property_duplicate_state(&sde_crtc->property_info,
  3189. old_cstate, cstate,
  3190. &cstate->property_state, cstate->property_values);
  3191. /* clear destination scaler dirty bit */
  3192. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  3193. /* duplicate base helper */
  3194. __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
  3195. return &cstate->base;
  3196. }
  3197. /**
  3198. * sde_crtc_reset - reset hook for CRTCs
  3199. * Resets the atomic state for @crtc by freeing the state pointer (which might
  3200. * be NULL, e.g. at driver load time) and allocating a new empty state object.
  3201. * @crtc: Pointer to drm crtc structure
  3202. */
  3203. static void sde_crtc_reset(struct drm_crtc *crtc)
  3204. {
  3205. struct sde_crtc *sde_crtc;
  3206. struct sde_crtc_state *cstate;
  3207. if (!crtc) {
  3208. SDE_ERROR("invalid crtc\n");
  3209. return;
  3210. }
  3211. /* revert suspend actions, if necessary */
  3212. if (!sde_crtc_is_reset_required(crtc)) {
  3213. SDE_DEBUG("avoiding reset for crtc:%d\n", crtc->base.id);
  3214. return;
  3215. }
  3216. /* remove previous state, if present */
  3217. if (crtc->state) {
  3218. sde_crtc_destroy_state(crtc, crtc->state);
  3219. crtc->state = 0;
  3220. }
  3221. sde_crtc = to_sde_crtc(crtc);
  3222. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3223. if (!cstate) {
  3224. SDE_ERROR("failed to allocate state\n");
  3225. return;
  3226. }
  3227. /* reset value helper */
  3228. msm_property_reset_state(&sde_crtc->property_info, cstate,
  3229. &cstate->property_state,
  3230. cstate->property_values);
  3231. _sde_crtc_set_input_fence_timeout(cstate);
  3232. cstate->base.crtc = crtc;
  3233. crtc->state = &cstate->base;
  3234. }
  3235. static void sde_crtc_handle_power_event(u32 event_type, void *arg)
  3236. {
  3237. struct drm_crtc *crtc = arg;
  3238. struct sde_crtc *sde_crtc;
  3239. struct sde_crtc_state *cstate;
  3240. struct drm_plane *plane;
  3241. struct drm_encoder *encoder;
  3242. u32 power_on;
  3243. unsigned long flags;
  3244. struct sde_crtc_irq_info *node = NULL;
  3245. int ret = 0;
  3246. struct drm_event event;
  3247. if (!crtc) {
  3248. SDE_ERROR("invalid crtc\n");
  3249. return;
  3250. }
  3251. sde_crtc = to_sde_crtc(crtc);
  3252. cstate = to_sde_crtc_state(crtc->state);
  3253. mutex_lock(&sde_crtc->crtc_lock);
  3254. SDE_EVT32(DRMID(crtc), event_type);
  3255. switch (event_type) {
  3256. case SDE_POWER_EVENT_POST_ENABLE:
  3257. /* restore encoder; crtc will be programmed during commit */
  3258. drm_for_each_encoder_mask(encoder, crtc->dev,
  3259. crtc->state->encoder_mask) {
  3260. sde_encoder_virt_restore(encoder);
  3261. }
  3262. /* restore UIDLE */
  3263. sde_core_perf_crtc_update_uidle(crtc, true);
  3264. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3265. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3266. ret = 0;
  3267. if (node->func)
  3268. ret = node->func(crtc, true, &node->irq);
  3269. if (ret)
  3270. SDE_ERROR("%s failed to enable event %x\n",
  3271. sde_crtc->name, node->event);
  3272. }
  3273. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3274. sde_cp_crtc_post_ipc(crtc);
  3275. break;
  3276. case SDE_POWER_EVENT_PRE_DISABLE:
  3277. drm_for_each_encoder_mask(encoder, crtc->dev,
  3278. crtc->state->encoder_mask) {
  3279. /*
  3280. * disable the vsync source after updating the
  3281. * rsc state. rsc state update might have vsync wait
  3282. * and vsync source must be disabled after it.
  3283. * It will avoid generating any vsync from this point
  3284. * till mode-2 entry. It is SW workaround for HW
  3285. * limitation and should not be removed without
  3286. * checking the updated design.
  3287. */
  3288. sde_encoder_control_te(encoder, false);
  3289. }
  3290. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3291. node = NULL;
  3292. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3293. ret = 0;
  3294. if (node->func)
  3295. ret = node->func(crtc, false, &node->irq);
  3296. if (ret)
  3297. SDE_ERROR("%s failed to disable event %x\n",
  3298. sde_crtc->name, node->event);
  3299. }
  3300. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3301. sde_cp_crtc_pre_ipc(crtc);
  3302. break;
  3303. case SDE_POWER_EVENT_POST_DISABLE:
  3304. /*
  3305. * set revalidate flag in planes, so it will be re-programmed
  3306. * in the next frame update
  3307. */
  3308. drm_atomic_crtc_for_each_plane(plane, crtc)
  3309. sde_plane_set_revalidate(plane, true);
  3310. sde_cp_crtc_suspend(crtc);
  3311. /* reconfigure everything on next frame update */
  3312. bitmap_fill(cstate->dirty, SDE_CRTC_DIRTY_MAX);
  3313. event.type = DRM_EVENT_SDE_POWER;
  3314. event.length = sizeof(power_on);
  3315. power_on = 0;
  3316. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3317. (u8 *)&power_on);
  3318. break;
  3319. default:
  3320. SDE_DEBUG("event:%d not handled\n", event_type);
  3321. break;
  3322. }
  3323. mutex_unlock(&sde_crtc->crtc_lock);
  3324. }
  3325. static void sde_crtc_disable(struct drm_crtc *crtc)
  3326. {
  3327. struct sde_kms *sde_kms;
  3328. struct sde_crtc *sde_crtc;
  3329. struct sde_crtc_state *cstate;
  3330. struct drm_encoder *encoder;
  3331. struct msm_drm_private *priv;
  3332. unsigned long flags;
  3333. struct sde_crtc_irq_info *node = NULL;
  3334. struct drm_event event;
  3335. u32 power_on;
  3336. bool in_cont_splash = false;
  3337. int ret, i;
  3338. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
  3339. SDE_ERROR("invalid crtc\n");
  3340. return;
  3341. }
  3342. sde_kms = _sde_crtc_get_kms(crtc);
  3343. if (!sde_kms) {
  3344. SDE_ERROR("invalid kms\n");
  3345. return;
  3346. }
  3347. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3348. SDE_ERROR("power resource is not enabled\n");
  3349. return;
  3350. }
  3351. sde_crtc = to_sde_crtc(crtc);
  3352. cstate = to_sde_crtc_state(crtc->state);
  3353. priv = crtc->dev->dev_private;
  3354. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3355. drm_crtc_vblank_off(crtc);
  3356. mutex_lock(&sde_crtc->crtc_lock);
  3357. SDE_EVT32_VERBOSE(DRMID(crtc));
  3358. /* update color processing on suspend */
  3359. event.type = DRM_EVENT_CRTC_POWER;
  3360. event.length = sizeof(u32);
  3361. sde_cp_crtc_suspend(crtc);
  3362. power_on = 0;
  3363. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3364. (u8 *)&power_on);
  3365. bitmap_fill(cstate->dirty, SDE_CRTC_DIRTY_MAX);
  3366. _sde_crtc_flush_event_thread(crtc);
  3367. SDE_EVT32(DRMID(crtc), sde_crtc->enabled,
  3368. crtc->state->active, crtc->state->enable);
  3369. sde_crtc->enabled = false;
  3370. /* Try to disable uidle */
  3371. sde_core_perf_crtc_update_uidle(crtc, false);
  3372. if (atomic_read(&sde_crtc->frame_pending)) {
  3373. SDE_ERROR("crtc%d frame_pending%d\n", crtc->base.id,
  3374. atomic_read(&sde_crtc->frame_pending));
  3375. SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending),
  3376. SDE_EVTLOG_FUNC_CASE2);
  3377. sde_core_perf_crtc_release_bw(crtc);
  3378. atomic_set(&sde_crtc->frame_pending, 0);
  3379. }
  3380. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3381. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3382. ret = 0;
  3383. if (node->func)
  3384. ret = node->func(crtc, false, &node->irq);
  3385. if (ret)
  3386. SDE_ERROR("%s failed to disable event %x\n",
  3387. sde_crtc->name, node->event);
  3388. }
  3389. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3390. drm_for_each_encoder_mask(encoder, crtc->dev,
  3391. crtc->state->encoder_mask) {
  3392. if (sde_encoder_in_cont_splash(encoder)) {
  3393. in_cont_splash = true;
  3394. break;
  3395. }
  3396. }
  3397. /* avoid clk/bw downvote if cont-splash is enabled */
  3398. if (!in_cont_splash)
  3399. sde_core_perf_crtc_update(crtc, 0, true);
  3400. drm_for_each_encoder_mask(encoder, crtc->dev,
  3401. crtc->state->encoder_mask) {
  3402. sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
  3403. cstate->rsc_client = NULL;
  3404. cstate->rsc_update = false;
  3405. /*
  3406. * reset idle power-collapse to original state during suspend;
  3407. * user-mode will change the state on resume, if required
  3408. */
  3409. if (sde_kms->catalog->has_idle_pc)
  3410. sde_encoder_control_idle_pc(encoder, true);
  3411. }
  3412. if (sde_crtc->power_event)
  3413. sde_power_handle_unregister_event(&priv->phandle,
  3414. sde_crtc->power_event);
  3415. /**
  3416. * All callbacks are unregistered and frame done waits are complete
  3417. * at this point. No buffers are accessed by hardware.
  3418. * reset the fence timeline if crtc will not be enabled for this commit
  3419. */
  3420. if (!crtc->state->active || !crtc->state->enable) {
  3421. sde_fence_signal(sde_crtc->output_fence,
  3422. ktime_get(), SDE_FENCE_RESET_TIMELINE);
  3423. for (i = 0; i < cstate->num_connectors; ++i)
  3424. sde_connector_commit_reset(cstate->connectors[i],
  3425. ktime_get());
  3426. }
  3427. _sde_crtc_clear_all_blend_stages(sde_crtc);
  3428. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  3429. sde_crtc->num_mixers = 0;
  3430. sde_crtc->mixers_swapped = false;
  3431. /* disable clk & bw control until clk & bw properties are set */
  3432. cstate->bw_control = false;
  3433. cstate->bw_split_vote = false;
  3434. mutex_unlock(&sde_crtc->crtc_lock);
  3435. }
  3436. static void sde_crtc_enable(struct drm_crtc *crtc,
  3437. struct drm_crtc_state *old_crtc_state)
  3438. {
  3439. struct sde_crtc *sde_crtc;
  3440. struct drm_encoder *encoder;
  3441. struct msm_drm_private *priv;
  3442. unsigned long flags;
  3443. struct sde_crtc_irq_info *node = NULL;
  3444. struct drm_event event;
  3445. u32 power_on;
  3446. int ret, i;
  3447. struct sde_crtc_state *cstate;
  3448. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  3449. SDE_ERROR("invalid crtc\n");
  3450. return;
  3451. }
  3452. priv = crtc->dev->dev_private;
  3453. cstate = to_sde_crtc_state(crtc->state);
  3454. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3455. SDE_ERROR("power resource is not enabled\n");
  3456. return;
  3457. }
  3458. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3459. SDE_EVT32_VERBOSE(DRMID(crtc));
  3460. sde_crtc = to_sde_crtc(crtc);
  3461. /*
  3462. * Avoid drm_crtc_vblank_on during seamless DMS case
  3463. * when CRTC is already in enabled state
  3464. */
  3465. if (!sde_crtc->enabled)
  3466. drm_crtc_vblank_on(crtc);
  3467. mutex_lock(&sde_crtc->crtc_lock);
  3468. SDE_EVT32(DRMID(crtc), sde_crtc->enabled);
  3469. /*
  3470. * Try to enable uidle (if possible), we do this before the call
  3471. * to return early during seamless dms mode, so any fps
  3472. * change is also consider to enable/disable UIDLE
  3473. */
  3474. sde_core_perf_crtc_update_uidle(crtc, true);
  3475. /* return early if crtc is already enabled, do this after UIDLE check */
  3476. if (sde_crtc->enabled) {
  3477. if (msm_is_mode_seamless_dms(&crtc->state->adjusted_mode) ||
  3478. msm_is_mode_seamless_dyn_clk(&crtc->state->adjusted_mode))
  3479. SDE_DEBUG("%s extra crtc enable expected during DMS\n",
  3480. sde_crtc->name);
  3481. else
  3482. WARN(1, "%s unexpected crtc enable\n", sde_crtc->name);
  3483. mutex_unlock(&sde_crtc->crtc_lock);
  3484. return;
  3485. }
  3486. drm_for_each_encoder_mask(encoder, crtc->dev,
  3487. crtc->state->encoder_mask) {
  3488. sde_encoder_register_frame_event_callback(encoder,
  3489. sde_crtc_frame_event_cb, crtc);
  3490. }
  3491. sde_crtc->enabled = true;
  3492. /* update color processing on resume */
  3493. event.type = DRM_EVENT_CRTC_POWER;
  3494. event.length = sizeof(u32);
  3495. sde_cp_crtc_resume(crtc);
  3496. power_on = 1;
  3497. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event,
  3498. (u8 *)&power_on);
  3499. mutex_unlock(&sde_crtc->crtc_lock);
  3500. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3501. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3502. ret = 0;
  3503. if (node->func)
  3504. ret = node->func(crtc, true, &node->irq);
  3505. if (ret)
  3506. SDE_ERROR("%s failed to enable event %x\n",
  3507. sde_crtc->name, node->event);
  3508. }
  3509. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3510. sde_crtc->power_event = sde_power_handle_register_event(
  3511. &priv->phandle,
  3512. SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE |
  3513. SDE_POWER_EVENT_PRE_DISABLE,
  3514. sde_crtc_handle_power_event, crtc, sde_crtc->name);
  3515. /* Enable ESD thread */
  3516. for (i = 0; i < cstate->num_connectors; i++)
  3517. sde_connector_schedule_status_work(cstate->connectors[i], true);
  3518. }
  3519. /* no input validation - caller API has all the checks */
  3520. static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state,
  3521. struct plane_state pstates[], int cnt)
  3522. {
  3523. struct sde_crtc_state *cstate = to_sde_crtc_state(state);
  3524. struct drm_display_mode *mode = &state->adjusted_mode;
  3525. const struct drm_plane_state *pstate;
  3526. struct sde_plane_state *sde_pstate;
  3527. int rc = 0, i;
  3528. /* Check dim layer rect bounds and stage */
  3529. for (i = 0; i < cstate->num_dim_layers; i++) {
  3530. if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y,
  3531. cstate->dim_layer[i].rect.h, mode->vdisplay)) ||
  3532. (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x,
  3533. cstate->dim_layer[i].rect.w, mode->hdisplay)) ||
  3534. (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) ||
  3535. (!cstate->dim_layer[i].rect.w) ||
  3536. (!cstate->dim_layer[i].rect.h)) {
  3537. SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
  3538. cstate->dim_layer[i].rect.x,
  3539. cstate->dim_layer[i].rect.y,
  3540. cstate->dim_layer[i].rect.w,
  3541. cstate->dim_layer[i].rect.h,
  3542. cstate->dim_layer[i].stage);
  3543. SDE_ERROR("display: %dx%d\n", mode->hdisplay,
  3544. mode->vdisplay);
  3545. rc = -E2BIG;
  3546. goto end;
  3547. }
  3548. }
  3549. /* log all src and excl_rect, useful for debugging */
  3550. for (i = 0; i < cnt; i++) {
  3551. pstate = pstates[i].drm_pstate;
  3552. sde_pstate = to_sde_plane_state(pstate);
  3553. SDE_DEBUG("p %d z %d src{%d,%d,%d,%d} excl_rect{%d,%d,%d,%d}\n",
  3554. pstate->plane->base.id, pstates[i].stage,
  3555. pstate->crtc_x, pstate->crtc_y,
  3556. pstate->crtc_w, pstate->crtc_h,
  3557. sde_pstate->excl_rect.x, sde_pstate->excl_rect.y,
  3558. sde_pstate->excl_rect.w, sde_pstate->excl_rect.h);
  3559. }
  3560. end:
  3561. return rc;
  3562. }
  3563. static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
  3564. struct drm_crtc_state *state, struct plane_state pstates[],
  3565. struct sde_crtc_state *cstate, struct sde_kms *sde_kms,
  3566. int cnt, int secure, int fb_ns, int fb_sec, int fb_sec_dir)
  3567. {
  3568. struct drm_plane *plane;
  3569. int i;
  3570. if (secure == SDE_DRM_SEC_ONLY) {
  3571. /*
  3572. * validate planes - only fb_sec_dir is allowed during sec_crtc
  3573. * - fb_sec_dir is for secure camera preview and
  3574. * secure display use case
  3575. * - fb_sec is for secure video playback
  3576. * - fb_ns is for normal non secure use cases
  3577. */
  3578. if (fb_ns || fb_sec) {
  3579. SDE_ERROR(
  3580. "crtc%d: invalid fb_modes Sec:%d, NS:%d, Sec_Dir:%d\n",
  3581. DRMID(crtc), fb_sec, fb_ns, fb_sec_dir);
  3582. return -EINVAL;
  3583. }
  3584. /*
  3585. * - only one blending stage is allowed in sec_crtc
  3586. * - validate if pipe is allowed for sec-ui updates
  3587. */
  3588. for (i = 1; i < cnt; i++) {
  3589. if (!pstates[i].drm_pstate
  3590. || !pstates[i].drm_pstate->plane) {
  3591. SDE_ERROR("crtc%d: invalid pstate at i:%d\n",
  3592. DRMID(crtc), i);
  3593. return -EINVAL;
  3594. }
  3595. plane = pstates[i].drm_pstate->plane;
  3596. if (!sde_plane_is_sec_ui_allowed(plane)) {
  3597. SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",
  3598. DRMID(crtc), plane->base.id);
  3599. return -EINVAL;
  3600. } else if (pstates[i].stage != pstates[i-1].stage) {
  3601. SDE_ERROR(
  3602. "crtc%d: invalid blend stages %d:%d, %d:%d\n",
  3603. DRMID(crtc), i, pstates[i].stage,
  3604. i-1, pstates[i-1].stage);
  3605. return -EINVAL;
  3606. }
  3607. }
  3608. /* check if all the dim_layers are in the same stage */
  3609. for (i = 1; i < cstate->num_dim_layers; i++) {
  3610. if (cstate->dim_layer[i].stage !=
  3611. cstate->dim_layer[i-1].stage) {
  3612. SDE_ERROR(
  3613. "crtc%d: invalid dimlayer stage %d:%d, %d:%d\n",
  3614. DRMID(crtc),
  3615. i, cstate->dim_layer[i].stage,
  3616. i-1, cstate->dim_layer[i-1].stage);
  3617. return -EINVAL;
  3618. }
  3619. }
  3620. /*
  3621. * if secure-ui supported blendstage is specified,
  3622. * - fail empty commit
  3623. * - validate dim_layer or plane is staged in the supported
  3624. * blendstage
  3625. */
  3626. if (sde_kms->catalog->sui_supported_blendstage) {
  3627. int sec_stage = cnt ? pstates[0].sde_pstate->stage :
  3628. cstate->dim_layer[0].stage;
  3629. if (!sde_kms->catalog->has_base_layer)
  3630. sec_stage -= SDE_STAGE_0;
  3631. if ((!cnt && !cstate->num_dim_layers) ||
  3632. (sde_kms->catalog->sui_supported_blendstage
  3633. != sec_stage)) {
  3634. SDE_ERROR(
  3635. "crtc%d: empty cnt%d/dim%d or bad stage%d\n",
  3636. DRMID(crtc), cnt,
  3637. cstate->num_dim_layers, sec_stage);
  3638. return -EINVAL;
  3639. }
  3640. }
  3641. }
  3642. return 0;
  3643. }
  3644. static int _sde_crtc_check_secure_single_encoder(struct drm_crtc *crtc,
  3645. struct drm_crtc_state *state, int fb_sec_dir)
  3646. {
  3647. struct drm_encoder *encoder;
  3648. int encoder_cnt = 0;
  3649. if (fb_sec_dir) {
  3650. drm_for_each_encoder_mask(encoder, crtc->dev,
  3651. state->encoder_mask)
  3652. encoder_cnt++;
  3653. if (encoder_cnt > MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) {
  3654. SDE_ERROR("crtc:%d invalid number of encoders:%d\n",
  3655. DRMID(crtc), encoder_cnt);
  3656. return -EINVAL;
  3657. }
  3658. }
  3659. return 0;
  3660. }
  3661. static int _sde_crtc_check_secure_state_smmu_translation(struct drm_crtc *crtc,
  3662. struct drm_crtc_state *state, struct sde_kms *sde_kms, int secure,
  3663. int fb_ns, int fb_sec, int fb_sec_dir)
  3664. {
  3665. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  3666. struct drm_encoder *encoder;
  3667. int is_video_mode = false;
  3668. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  3669. if (sde_encoder_is_dsi_display(encoder))
  3670. is_video_mode |= sde_encoder_check_curr_mode(encoder,
  3671. MSM_DISPLAY_VIDEO_MODE);
  3672. }
  3673. /*
  3674. * Secure display to secure camera needs without direct
  3675. * transition is currently not allowed
  3676. */
  3677. if (fb_sec_dir && secure == SDE_DRM_SEC_NON_SEC &&
  3678. smmu_state->state != ATTACHED &&
  3679. smmu_state->secure_level == SDE_DRM_SEC_ONLY) {
  3680. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3681. smmu_state->state, smmu_state->secure_level,
  3682. secure);
  3683. goto sec_err;
  3684. }
  3685. /*
  3686. * In video mode check for null commit before transition
  3687. * from secure to non secure and vice versa
  3688. */
  3689. if (is_video_mode && smmu_state &&
  3690. state->plane_mask && crtc->state->plane_mask &&
  3691. ((fb_sec_dir && ((smmu_state->state == ATTACHED) &&
  3692. (secure == SDE_DRM_SEC_ONLY))) ||
  3693. (fb_ns && ((smmu_state->state == DETACHED) ||
  3694. (smmu_state->state == DETACH_ALL_REQ))) ||
  3695. (fb_ns && ((smmu_state->state == DETACHED_SEC) ||
  3696. (smmu_state->state == DETACH_SEC_REQ)) &&
  3697. (smmu_state->secure_level == SDE_DRM_SEC_ONLY)))) {
  3698. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  3699. smmu_state->state, smmu_state->secure_level,
  3700. secure, crtc->state->plane_mask, state->plane_mask);
  3701. goto sec_err;
  3702. }
  3703. return 0;
  3704. sec_err:
  3705. SDE_ERROR(
  3706. "crtc%d Invalid transition;sec%d state%d slvl%d ns%d sdir%d\n",
  3707. DRMID(crtc), secure, smmu_state->state,
  3708. smmu_state->secure_level, fb_ns, fb_sec_dir);
  3709. return -EINVAL;
  3710. }
  3711. static int _sde_crtc_check_secure_conn(struct drm_crtc *crtc,
  3712. struct drm_crtc_state *state, uint32_t fb_sec)
  3713. {
  3714. bool conn_secure = false, is_wb = false;
  3715. struct drm_connector *conn;
  3716. struct drm_connector_state *conn_state;
  3717. int i;
  3718. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  3719. if (conn_state && conn_state->crtc == crtc) {
  3720. if (conn->connector_type ==
  3721. DRM_MODE_CONNECTOR_VIRTUAL)
  3722. is_wb = true;
  3723. if (sde_connector_get_property(conn_state,
  3724. CONNECTOR_PROP_FB_TRANSLATION_MODE) ==
  3725. SDE_DRM_FB_SEC)
  3726. conn_secure = true;
  3727. }
  3728. }
  3729. /*
  3730. * If any input buffers are secure for wb,
  3731. * the output buffer must also be secure.
  3732. */
  3733. if (is_wb && fb_sec && !conn_secure) {
  3734. SDE_ERROR("crtc%d: input fb sec %d, output fb secure %d\n",
  3735. DRMID(crtc), fb_sec, conn_secure);
  3736. return -EINVAL;
  3737. }
  3738. return 0;
  3739. }
  3740. static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
  3741. struct drm_crtc_state *state, struct plane_state pstates[],
  3742. int cnt)
  3743. {
  3744. struct sde_crtc_state *cstate;
  3745. struct sde_kms *sde_kms;
  3746. uint32_t secure;
  3747. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  3748. int rc;
  3749. if (!crtc || !state) {
  3750. SDE_ERROR("invalid arguments\n");
  3751. return -EINVAL;
  3752. }
  3753. sde_kms = _sde_crtc_get_kms(crtc);
  3754. if (!sde_kms || !sde_kms->catalog) {
  3755. SDE_ERROR("invalid kms\n");
  3756. return -EINVAL;
  3757. }
  3758. cstate = to_sde_crtc_state(state);
  3759. secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL);
  3760. rc = sde_crtc_state_find_plane_fb_modes(state, &fb_ns,
  3761. &fb_sec, &fb_sec_dir);
  3762. if (rc)
  3763. return rc;
  3764. rc = _sde_crtc_check_secure_blend_config(crtc, state, pstates, cstate,
  3765. sde_kms, cnt, secure, fb_ns, fb_sec, fb_sec_dir);
  3766. if (rc)
  3767. return rc;
  3768. rc = _sde_crtc_check_secure_conn(crtc, state, fb_sec);
  3769. if (rc)
  3770. return rc;
  3771. /*
  3772. * secure_crtc is not allowed in a shared toppolgy
  3773. * across different encoders.
  3774. */
  3775. rc = _sde_crtc_check_secure_single_encoder(crtc, state, fb_sec_dir);
  3776. if (rc)
  3777. return rc;
  3778. rc = _sde_crtc_check_secure_state_smmu_translation(crtc, state, sde_kms,
  3779. secure, fb_ns, fb_sec, fb_sec_dir);
  3780. if (rc)
  3781. return rc;
  3782. SDE_DEBUG("crtc:%d Secure validation successful\n", DRMID(crtc));
  3783. return 0;
  3784. }
  3785. static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
  3786. struct drm_crtc_state *state,
  3787. struct drm_display_mode *mode,
  3788. struct plane_state *pstates,
  3789. struct drm_plane *plane,
  3790. struct sde_multirect_plane_states *multirect_plane,
  3791. int *cnt)
  3792. {
  3793. struct sde_crtc *sde_crtc;
  3794. struct sde_crtc_state *cstate;
  3795. const struct drm_plane_state *pstate;
  3796. const struct drm_plane_state *pipe_staged[SSPP_MAX];
  3797. int rc = 0, multirect_count = 0, i, mixer_width, mixer_height;
  3798. int inc_sde_stage = 0;
  3799. struct sde_kms *kms;
  3800. sde_crtc = to_sde_crtc(crtc);
  3801. cstate = to_sde_crtc_state(state);
  3802. kms = _sde_crtc_get_kms(crtc);
  3803. if (!kms || !kms->catalog) {
  3804. SDE_ERROR("invalid kms\n");
  3805. return -EINVAL;
  3806. }
  3807. memset(pipe_staged, 0, sizeof(pipe_staged));
  3808. mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  3809. mixer_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  3810. if (cstate->num_ds_enabled)
  3811. mixer_width = mixer_width * cstate->num_ds_enabled;
  3812. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  3813. if (IS_ERR_OR_NULL(pstate)) {
  3814. rc = PTR_ERR(pstate);
  3815. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  3816. sde_crtc->name, plane->base.id, rc);
  3817. return rc;
  3818. }
  3819. if (*cnt >= SDE_PSTATES_MAX)
  3820. continue;
  3821. pstates[*cnt].sde_pstate = to_sde_plane_state(pstate);
  3822. pstates[*cnt].drm_pstate = pstate;
  3823. pstates[*cnt].stage = sde_plane_get_property(
  3824. pstates[*cnt].sde_pstate, PLANE_PROP_ZPOS);
  3825. pstates[*cnt].pipe_id = sde_plane_pipe(plane);
  3826. if (!kms->catalog->has_base_layer)
  3827. inc_sde_stage = SDE_STAGE_0;
  3828. /* check dim layer stage with every plane */
  3829. for (i = 0; i < cstate->num_dim_layers; i++) {
  3830. if (cstate->dim_layer[i].stage ==
  3831. (pstates[*cnt].stage + inc_sde_stage)) {
  3832. SDE_ERROR(
  3833. "plane:%d/dim_layer:%i-same stage:%d\n",
  3834. plane->base.id, i,
  3835. cstate->dim_layer[i].stage);
  3836. return -EINVAL;
  3837. }
  3838. }
  3839. if (pipe_staged[pstates[*cnt].pipe_id]) {
  3840. multirect_plane[multirect_count].r0 =
  3841. pipe_staged[pstates[*cnt].pipe_id];
  3842. multirect_plane[multirect_count].r1 = pstate;
  3843. multirect_count++;
  3844. pipe_staged[pstates[*cnt].pipe_id] = NULL;
  3845. } else {
  3846. pipe_staged[pstates[*cnt].pipe_id] = pstate;
  3847. }
  3848. (*cnt)++;
  3849. if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h,
  3850. mode->vdisplay) ||
  3851. CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w,
  3852. mode->hdisplay)) {
  3853. SDE_ERROR("invalid vertical/horizontal destination\n");
  3854. SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n",
  3855. pstate->crtc_y, pstate->crtc_h, mode->vdisplay,
  3856. pstate->crtc_x, pstate->crtc_w, mode->hdisplay);
  3857. return -E2BIG;
  3858. }
  3859. if (cstate->num_ds_enabled &&
  3860. ((pstate->crtc_h > mixer_height) ||
  3861. (pstate->crtc_w > mixer_width))) {
  3862. SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n",
  3863. pstate->crtc_w, pstate->crtc_h,
  3864. mixer_width, mixer_height);
  3865. return -E2BIG;
  3866. }
  3867. }
  3868. for (i = 1; i < SSPP_MAX; i++) {
  3869. if (pipe_staged[i]) {
  3870. if (is_sde_plane_virtual(pipe_staged[i]->plane)) {
  3871. SDE_ERROR(
  3872. "r1 only virt plane:%d not supported\n",
  3873. pipe_staged[i]->plane->base.id);
  3874. return -EINVAL;
  3875. }
  3876. sde_plane_clear_multirect(pipe_staged[i]);
  3877. }
  3878. }
  3879. for (i = 0; i < multirect_count; i++) {
  3880. if (sde_plane_validate_multirect_v2(&multirect_plane[i])) {
  3881. SDE_ERROR(
  3882. "multirect validation failed for planes (%d - %d)\n",
  3883. multirect_plane[i].r0->plane->base.id,
  3884. multirect_plane[i].r1->plane->base.id);
  3885. return -EINVAL;
  3886. }
  3887. }
  3888. return rc;
  3889. }
  3890. static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
  3891. struct sde_crtc *sde_crtc,
  3892. struct plane_state *pstates,
  3893. struct sde_crtc_state *cstate,
  3894. struct drm_display_mode *mode,
  3895. int cnt)
  3896. {
  3897. int rc = 0, i, z_pos;
  3898. u32 zpos_cnt = 0;
  3899. struct drm_crtc *crtc;
  3900. struct sde_kms *kms;
  3901. crtc = &sde_crtc->base;
  3902. kms = _sde_crtc_get_kms(crtc);
  3903. if (!kms || !kms->catalog) {
  3904. SDE_ERROR("Invalid kms\n");
  3905. return -EINVAL;
  3906. }
  3907. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  3908. rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);
  3909. if (rc)
  3910. return rc;
  3911. if (!sde_is_custom_client()) {
  3912. int stage_old = pstates[0].stage;
  3913. z_pos = 0;
  3914. for (i = 0; i < cnt; i++) {
  3915. if (stage_old != pstates[i].stage)
  3916. ++z_pos;
  3917. stage_old = pstates[i].stage;
  3918. pstates[i].stage = z_pos;
  3919. }
  3920. }
  3921. z_pos = -1;
  3922. for (i = 0; i < cnt; i++) {
  3923. /* reset counts at every new blend stage */
  3924. if (pstates[i].stage != z_pos) {
  3925. zpos_cnt = 0;
  3926. z_pos = pstates[i].stage;
  3927. }
  3928. /* verify z_pos setting before using it */
  3929. if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
  3930. SDE_ERROR("> %d plane stages assigned\n",
  3931. SDE_STAGE_MAX - SDE_STAGE_0);
  3932. return -EINVAL;
  3933. } else if (zpos_cnt == 2) {
  3934. SDE_ERROR("> 2 planes @ stage %d\n", z_pos);
  3935. return -EINVAL;
  3936. } else {
  3937. zpos_cnt++;
  3938. }
  3939. if (!kms->catalog->has_base_layer)
  3940. pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
  3941. else
  3942. pstates[i].sde_pstate->stage = z_pos;
  3943. SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos);
  3944. }
  3945. return rc;
  3946. }
  3947. static int _sde_crtc_atomic_check_pstates(struct drm_crtc *crtc,
  3948. struct drm_crtc_state *state,
  3949. struct plane_state *pstates,
  3950. struct sde_multirect_plane_states *multirect_plane)
  3951. {
  3952. struct sde_crtc *sde_crtc;
  3953. struct sde_crtc_state *cstate;
  3954. struct sde_kms *kms;
  3955. struct drm_plane *plane = NULL;
  3956. struct drm_display_mode *mode;
  3957. int rc = 0, cnt = 0;
  3958. kms = _sde_crtc_get_kms(crtc);
  3959. if (!kms || !kms->catalog) {
  3960. SDE_ERROR("invalid parameters\n");
  3961. return -EINVAL;
  3962. }
  3963. sde_crtc = to_sde_crtc(crtc);
  3964. cstate = to_sde_crtc_state(state);
  3965. mode = &state->adjusted_mode;
  3966. /* get plane state for all drm planes associated with crtc state */
  3967. rc = _sde_crtc_check_get_pstates(crtc, state, mode, pstates,
  3968. plane, multirect_plane, &cnt);
  3969. if (rc)
  3970. return rc;
  3971. /* assign mixer stages based on sorted zpos property */
  3972. rc = _sde_crtc_check_zpos(state, sde_crtc, pstates, cstate, mode, cnt);
  3973. if (rc)
  3974. return rc;
  3975. rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);
  3976. if (rc)
  3977. return rc;
  3978. /*
  3979. * validate and set source split:
  3980. * use pstates sorted by stage to check planes on same stage
  3981. * we assume that all pipes are in source split so its valid to compare
  3982. * without taking into account left/right mixer placement
  3983. */
  3984. rc = _sde_crtc_validate_src_split_order(crtc, pstates, cnt);
  3985. if (rc)
  3986. return rc;
  3987. return 0;
  3988. }
  3989. static int sde_crtc_atomic_check(struct drm_crtc *crtc,
  3990. struct drm_crtc_state *state)
  3991. {
  3992. struct drm_device *dev;
  3993. struct sde_crtc *sde_crtc;
  3994. struct plane_state *pstates = NULL;
  3995. struct sde_crtc_state *cstate;
  3996. struct drm_display_mode *mode;
  3997. int rc = 0;
  3998. struct sde_multirect_plane_states *multirect_plane = NULL;
  3999. struct drm_connector *conn;
  4000. struct drm_connector_list_iter conn_iter;
  4001. if (!crtc) {
  4002. SDE_ERROR("invalid crtc\n");
  4003. return -EINVAL;
  4004. }
  4005. dev = crtc->dev;
  4006. sde_crtc = to_sde_crtc(crtc);
  4007. cstate = to_sde_crtc_state(state);
  4008. if (!state->enable || !state->active) {
  4009. SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
  4010. crtc->base.id, state->enable, state->active);
  4011. goto end;
  4012. }
  4013. pstates = kcalloc(SDE_PSTATES_MAX,
  4014. sizeof(struct plane_state), GFP_KERNEL);
  4015. multirect_plane = kcalloc(SDE_MULTIRECT_PLANE_MAX,
  4016. sizeof(struct sde_multirect_plane_states),
  4017. GFP_KERNEL);
  4018. if (!pstates || !multirect_plane) {
  4019. rc = -ENOMEM;
  4020. goto end;
  4021. }
  4022. mode = &state->adjusted_mode;
  4023. SDE_DEBUG("%s: check", sde_crtc->name);
  4024. /* force a full mode set if active state changed */
  4025. if (state->active_changed)
  4026. state->mode_changed = true;
  4027. rc = _sde_crtc_check_dest_scaler_data(crtc, state);
  4028. if (rc) {
  4029. SDE_ERROR("crtc%d failed dest scaler check %d\n",
  4030. crtc->base.id, rc);
  4031. goto end;
  4032. }
  4033. /* identify connectors attached to this crtc */
  4034. cstate->num_connectors = 0;
  4035. drm_connector_list_iter_begin(dev, &conn_iter);
  4036. drm_for_each_connector_iter(conn, &conn_iter)
  4037. if (conn->state && conn->state->crtc == crtc &&
  4038. cstate->num_connectors < MAX_CONNECTORS) {
  4039. cstate->connectors[cstate->num_connectors++] = conn;
  4040. }
  4041. drm_connector_list_iter_end(&conn_iter);
  4042. _sde_crtc_setup_is_ppsplit(state);
  4043. _sde_crtc_setup_lm_bounds(crtc, state);
  4044. rc = _sde_crtc_atomic_check_pstates(crtc, state, pstates,
  4045. multirect_plane);
  4046. if (rc) {
  4047. SDE_ERROR("crtc%d failed pstate check %d\n", crtc->base.id, rc);
  4048. goto end;
  4049. }
  4050. rc = sde_core_perf_crtc_check(crtc, state);
  4051. if (rc) {
  4052. SDE_ERROR("crtc%d failed performance check %d\n",
  4053. crtc->base.id, rc);
  4054. goto end;
  4055. }
  4056. rc = _sde_crtc_check_rois(crtc, state);
  4057. if (rc) {
  4058. SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc);
  4059. goto end;
  4060. }
  4061. rc = sde_cp_crtc_check_properties(crtc, state);
  4062. if (rc) {
  4063. SDE_ERROR("crtc%d failed cp properties check %d\n",
  4064. crtc->base.id, rc);
  4065. goto end;
  4066. }
  4067. end:
  4068. kfree(pstates);
  4069. kfree(multirect_plane);
  4070. return rc;
  4071. }
  4072. int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
  4073. {
  4074. struct sde_crtc *sde_crtc;
  4075. int ret;
  4076. if (!crtc) {
  4077. SDE_ERROR("invalid crtc\n");
  4078. return -EINVAL;
  4079. }
  4080. sde_crtc = to_sde_crtc(crtc);
  4081. mutex_lock(&sde_crtc->crtc_lock);
  4082. SDE_EVT32(DRMID(&sde_crtc->base), en, sde_crtc->enabled);
  4083. ret = _sde_crtc_vblank_enable_no_lock(sde_crtc, en);
  4084. if (ret)
  4085. SDE_ERROR("%s vblank enable failed: %d\n",
  4086. sde_crtc->name, ret);
  4087. mutex_unlock(&sde_crtc->crtc_lock);
  4088. return 0;
  4089. }
  4090. static void sde_crtc_install_dest_scale_properties(struct sde_crtc *sde_crtc,
  4091. struct sde_mdss_cfg *catalog, struct sde_kms_info *info)
  4092. {
  4093. sde_kms_info_add_keyint(info, "has_dest_scaler",
  4094. catalog->mdp[0].has_dest_scaler);
  4095. sde_kms_info_add_keyint(info, "dest_scaler_count",
  4096. catalog->ds_count);
  4097. if (catalog->ds[0].top) {
  4098. sde_kms_info_add_keyint(info,
  4099. "max_dest_scaler_input_width",
  4100. catalog->ds[0].top->maxinputwidth);
  4101. sde_kms_info_add_keyint(info,
  4102. "max_dest_scaler_output_width",
  4103. catalog->ds[0].top->maxoutputwidth);
  4104. sde_kms_info_add_keyint(info, "max_dest_scale_up",
  4105. catalog->ds[0].top->maxupscale);
  4106. }
  4107. if (catalog->ds[0].features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  4108. msm_property_install_volatile_range(
  4109. &sde_crtc->property_info, "dest_scaler",
  4110. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4111. msm_property_install_blob(&sde_crtc->property_info,
  4112. "ds_lut_ed", 0,
  4113. CRTC_PROP_DEST_SCALER_LUT_ED);
  4114. msm_property_install_blob(&sde_crtc->property_info,
  4115. "ds_lut_cir", 0,
  4116. CRTC_PROP_DEST_SCALER_LUT_CIR);
  4117. msm_property_install_blob(&sde_crtc->property_info,
  4118. "ds_lut_sep", 0,
  4119. CRTC_PROP_DEST_SCALER_LUT_SEP);
  4120. } else if (catalog->ds[0].features
  4121. & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  4122. msm_property_install_volatile_range(
  4123. &sde_crtc->property_info, "dest_scaler",
  4124. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4125. }
  4126. }
  4127. static void sde_crtc_install_perf_properties(struct sde_crtc *sde_crtc,
  4128. struct sde_kms *sde_kms, struct sde_mdss_cfg *catalog,
  4129. struct sde_kms_info *info)
  4130. {
  4131. msm_property_install_range(&sde_crtc->property_info,
  4132. "core_clk", 0x0, 0, U64_MAX,
  4133. sde_kms->perf.max_core_clk_rate,
  4134. CRTC_PROP_CORE_CLK);
  4135. msm_property_install_range(&sde_crtc->property_info,
  4136. "core_ab", 0x0, 0, U64_MAX,
  4137. catalog->perf.max_bw_high * 1000ULL,
  4138. CRTC_PROP_CORE_AB);
  4139. msm_property_install_range(&sde_crtc->property_info,
  4140. "core_ib", 0x0, 0, U64_MAX,
  4141. catalog->perf.max_bw_high * 1000ULL,
  4142. CRTC_PROP_CORE_IB);
  4143. msm_property_install_range(&sde_crtc->property_info,
  4144. "llcc_ab", 0x0, 0, U64_MAX,
  4145. catalog->perf.max_bw_high * 1000ULL,
  4146. CRTC_PROP_LLCC_AB);
  4147. msm_property_install_range(&sde_crtc->property_info,
  4148. "llcc_ib", 0x0, 0, U64_MAX,
  4149. catalog->perf.max_bw_high * 1000ULL,
  4150. CRTC_PROP_LLCC_IB);
  4151. msm_property_install_range(&sde_crtc->property_info,
  4152. "dram_ab", 0x0, 0, U64_MAX,
  4153. catalog->perf.max_bw_high * 1000ULL,
  4154. CRTC_PROP_DRAM_AB);
  4155. msm_property_install_range(&sde_crtc->property_info,
  4156. "dram_ib", 0x0, 0, U64_MAX,
  4157. catalog->perf.max_bw_high * 1000ULL,
  4158. CRTC_PROP_DRAM_IB);
  4159. msm_property_install_range(&sde_crtc->property_info,
  4160. "rot_prefill_bw", 0, 0, U64_MAX,
  4161. catalog->perf.max_bw_high * 1000ULL,
  4162. CRTC_PROP_ROT_PREFILL_BW);
  4163. msm_property_install_range(&sde_crtc->property_info,
  4164. "rot_clk", 0, 0, U64_MAX,
  4165. sde_kms->perf.max_core_clk_rate,
  4166. CRTC_PROP_ROT_CLK);
  4167. if (catalog->perf.max_bw_low)
  4168. sde_kms_info_add_keyint(info, "max_bandwidth_low",
  4169. catalog->perf.max_bw_low * 1000LL);
  4170. if (catalog->perf.max_bw_high)
  4171. sde_kms_info_add_keyint(info, "max_bandwidth_high",
  4172. catalog->perf.max_bw_high * 1000LL);
  4173. if (catalog->perf.min_core_ib)
  4174. sde_kms_info_add_keyint(info, "min_core_ib",
  4175. catalog->perf.min_core_ib * 1000LL);
  4176. if (catalog->perf.min_llcc_ib)
  4177. sde_kms_info_add_keyint(info, "min_llcc_ib",
  4178. catalog->perf.min_llcc_ib * 1000LL);
  4179. if (catalog->perf.min_dram_ib)
  4180. sde_kms_info_add_keyint(info, "min_dram_ib",
  4181. catalog->perf.min_dram_ib * 1000LL);
  4182. if (sde_kms->perf.max_core_clk_rate)
  4183. sde_kms_info_add_keyint(info, "max_mdp_clk",
  4184. sde_kms->perf.max_core_clk_rate);
  4185. }
  4186. static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
  4187. struct sde_mdss_cfg *catalog)
  4188. {
  4189. int i, j;
  4190. sde_kms_info_reset(info);
  4191. sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
  4192. sde_kms_info_add_keyint(info, "max_linewidth",
  4193. catalog->max_mixer_width);
  4194. sde_kms_info_add_keyint(info, "max_blendstages",
  4195. catalog->max_mixer_blendstages);
  4196. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2)
  4197. sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
  4198. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3)
  4199. sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
  4200. if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)
  4201. sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
  4202. sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version);
  4203. sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
  4204. catalog->macrotile_mode);
  4205. sde_kms_info_add_keyint(info, "UBWC highest banking bit",
  4206. catalog->mdp[0].highest_bank_bit);
  4207. sde_kms_info_add_keyint(info, "UBWC swizzle",
  4208. catalog->mdp[0].ubwc_swizzle);
  4209. if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
  4210. sde_kms_info_add_keystr(info, "DDR version", "DDR4");
  4211. else
  4212. sde_kms_info_add_keystr(info, "DDR version", "DDR5");
  4213. if (sde_is_custom_client()) {
  4214. /* No support for SMART_DMA_V1 yet */
  4215. if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
  4216. sde_kms_info_add_keystr(info,
  4217. "smart_dma_rev", "smart_dma_v2");
  4218. else if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2p5)
  4219. sde_kms_info_add_keystr(info,
  4220. "smart_dma_rev", "smart_dma_v2p5");
  4221. }
  4222. sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
  4223. sde_kms_info_add_keyint(info, "has_hdr", catalog->has_hdr);
  4224. sde_kms_info_add_keyint(info, "has_hdr_plus", catalog->has_hdr_plus);
  4225. if (catalog->uidle_cfg.uidle_rev)
  4226. sde_kms_info_add_keyint(info, "has_uidle",
  4227. true);
  4228. for (i = 0; i < catalog->limit_count; i++) {
  4229. sde_kms_info_add_keyint(info,
  4230. catalog->limit_cfg[i].name,
  4231. catalog->limit_cfg[i].lmt_case_cnt);
  4232. for (j = 0; j < catalog->limit_cfg[i].lmt_case_cnt; j++) {
  4233. sde_kms_info_add_keyint(info,
  4234. catalog->limit_cfg[i].vector_cfg[j].usecase,
  4235. catalog->limit_cfg[i].vector_cfg[j].value);
  4236. }
  4237. if (!strcmp(catalog->limit_cfg[i].name,
  4238. "sspp_linewidth_usecases"))
  4239. sde_kms_info_add_keyint(info,
  4240. "sspp_linewidth_values",
  4241. catalog->limit_cfg[i].lmt_vec_cnt);
  4242. else if (!strcmp(catalog->limit_cfg[i].name,
  4243. "sde_bwlimit_usecases"))
  4244. sde_kms_info_add_keyint(info,
  4245. "sde_bwlimit_values",
  4246. catalog->limit_cfg[i].lmt_vec_cnt);
  4247. for (j = 0; j < catalog->limit_cfg[i].lmt_vec_cnt; j++) {
  4248. sde_kms_info_add_keyint(info, "limit_usecase",
  4249. catalog->limit_cfg[i].value_cfg[j].use_concur);
  4250. sde_kms_info_add_keyint(info, "limit_value",
  4251. catalog->limit_cfg[i].value_cfg[j].value);
  4252. }
  4253. }
  4254. sde_kms_info_add_keystr(info, "core_ib_ff",
  4255. catalog->perf.core_ib_ff);
  4256. sde_kms_info_add_keystr(info, "core_clk_ff",
  4257. catalog->perf.core_clk_ff);
  4258. sde_kms_info_add_keystr(info, "comp_ratio_rt",
  4259. catalog->perf.comp_ratio_rt);
  4260. sde_kms_info_add_keystr(info, "comp_ratio_nrt",
  4261. catalog->perf.comp_ratio_nrt);
  4262. sde_kms_info_add_keyint(info, "dest_scale_prefill_lines",
  4263. catalog->perf.dest_scale_prefill_lines);
  4264. sde_kms_info_add_keyint(info, "undersized_prefill_lines",
  4265. catalog->perf.undersized_prefill_lines);
  4266. sde_kms_info_add_keyint(info, "macrotile_prefill_lines",
  4267. catalog->perf.macrotile_prefill_lines);
  4268. sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines",
  4269. catalog->perf.yuv_nv12_prefill_lines);
  4270. sde_kms_info_add_keyint(info, "linear_prefill_lines",
  4271. catalog->perf.linear_prefill_lines);
  4272. sde_kms_info_add_keyint(info, "downscaling_prefill_lines",
  4273. catalog->perf.downscaling_prefill_lines);
  4274. sde_kms_info_add_keyint(info, "xtra_prefill_lines",
  4275. catalog->perf.xtra_prefill_lines);
  4276. sde_kms_info_add_keyint(info, "amortizable_threshold",
  4277. catalog->perf.amortizable_threshold);
  4278. sde_kms_info_add_keyint(info, "min_prefill_lines",
  4279. catalog->perf.min_prefill_lines);
  4280. sde_kms_info_add_keyint(info, "num_mnoc_ports",
  4281. catalog->perf.num_mnoc_ports);
  4282. sde_kms_info_add_keyint(info, "axi_bus_width",
  4283. catalog->perf.axi_bus_width);
  4284. sde_kms_info_add_keyint(info, "sec_ui_blendstage",
  4285. catalog->sui_supported_blendstage);
  4286. if (catalog->ubwc_bw_calc_version)
  4287. sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",
  4288. catalog->ubwc_bw_calc_version);
  4289. }
  4290. /**
  4291. * sde_crtc_install_properties - install all drm properties for crtc
  4292. * @crtc: Pointer to drm crtc structure
  4293. */
  4294. static void sde_crtc_install_properties(struct drm_crtc *crtc,
  4295. struct sde_mdss_cfg *catalog)
  4296. {
  4297. struct sde_crtc *sde_crtc;
  4298. struct sde_kms_info *info;
  4299. struct sde_kms *sde_kms;
  4300. static const struct drm_prop_enum_list e_secure_level[] = {
  4301. {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"},
  4302. {SDE_DRM_SEC_ONLY, "sec_only"},
  4303. };
  4304. static const struct drm_prop_enum_list e_cwb_data_points[] = {
  4305. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  4306. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  4307. };
  4308. static const struct drm_prop_enum_list e_idle_pc_state[] = {
  4309. {IDLE_PC_NONE, "idle_pc_none"},
  4310. {IDLE_PC_ENABLE, "idle_pc_enable"},
  4311. {IDLE_PC_DISABLE, "idle_pc_disable"},
  4312. };
  4313. SDE_DEBUG("\n");
  4314. if (!crtc || !catalog) {
  4315. SDE_ERROR("invalid crtc or catalog\n");
  4316. return;
  4317. }
  4318. sde_crtc = to_sde_crtc(crtc);
  4319. sde_kms = _sde_crtc_get_kms(crtc);
  4320. if (!sde_kms) {
  4321. SDE_ERROR("invalid argument\n");
  4322. return;
  4323. }
  4324. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  4325. if (!info) {
  4326. SDE_ERROR("failed to allocate info memory\n");
  4327. return;
  4328. }
  4329. sde_crtc_setup_capabilities_blob(info, catalog);
  4330. msm_property_install_range(&sde_crtc->property_info,
  4331. "input_fence_timeout", 0x0, 0,
  4332. SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, SDE_CRTC_INPUT_FENCE_TIMEOUT,
  4333. CRTC_PROP_INPUT_FENCE_TIMEOUT);
  4334. msm_property_install_volatile_range(&sde_crtc->property_info,
  4335. "output_fence", 0x0, 0, ~0, 0, CRTC_PROP_OUTPUT_FENCE);
  4336. msm_property_install_range(&sde_crtc->property_info,
  4337. "output_fence_offset", 0x0, 0, 1, 0,
  4338. CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4339. sde_crtc_install_perf_properties(sde_crtc, sde_kms, catalog, info);
  4340. msm_property_install_range(&sde_crtc->property_info,
  4341. "idle_time", 0, 0, U64_MAX, 0,
  4342. CRTC_PROP_IDLE_TIMEOUT);
  4343. if (catalog->has_idle_pc)
  4344. msm_property_install_enum(&sde_crtc->property_info,
  4345. "idle_pc_state", 0x0, 0, e_idle_pc_state,
  4346. ARRAY_SIZE(e_idle_pc_state),
  4347. CRTC_PROP_IDLE_PC_STATE);
  4348. if (catalog->has_cwb_support)
  4349. msm_property_install_enum(&sde_crtc->property_info,
  4350. "capture_mode", 0, 0, e_cwb_data_points,
  4351. ARRAY_SIZE(e_cwb_data_points),
  4352. CRTC_PROP_CAPTURE_OUTPUT);
  4353. msm_property_install_volatile_range(&sde_crtc->property_info,
  4354. "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);
  4355. msm_property_install_enum(&sde_crtc->property_info, "security_level",
  4356. 0x0, 0, e_secure_level,
  4357. ARRAY_SIZE(e_secure_level),
  4358. CRTC_PROP_SECURITY_LEVEL);
  4359. if (catalog->has_dim_layer) {
  4360. msm_property_install_volatile_range(&sde_crtc->property_info,
  4361. "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
  4362. sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
  4363. SDE_MAX_DIM_LAYERS);
  4364. }
  4365. if (catalog->mdp[0].has_dest_scaler)
  4366. sde_crtc_install_dest_scale_properties(sde_crtc, catalog,
  4367. info);
  4368. if (catalog->dspp_count && catalog->rc_count)
  4369. sde_kms_info_add_keyint(info, "rc_mem_size",
  4370. catalog->dspp[0].sblk->rc.mem_total_size);
  4371. msm_property_install_blob(&sde_crtc->property_info, "capabilities",
  4372. DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
  4373. sde_kms_info_add_keyint(info, "use_baselayer_for_stage",
  4374. catalog->has_base_layer);
  4375. msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
  4376. info->data, SDE_KMS_INFO_DATALEN(info),
  4377. CRTC_PROP_INFO);
  4378. kfree(info);
  4379. }
  4380. static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
  4381. const struct drm_crtc_state *state, uint64_t *val)
  4382. {
  4383. struct sde_crtc *sde_crtc;
  4384. struct sde_crtc_state *cstate;
  4385. uint32_t offset;
  4386. bool is_vid = false;
  4387. struct drm_encoder *encoder;
  4388. sde_crtc = to_sde_crtc(crtc);
  4389. cstate = to_sde_crtc_state(state);
  4390. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  4391. if (sde_encoder_check_curr_mode(encoder,
  4392. MSM_DISPLAY_VIDEO_MODE))
  4393. is_vid = true;
  4394. if (is_vid)
  4395. break;
  4396. }
  4397. offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4398. /*
  4399. * Increment trigger offset for vidoe mode alone as its release fence
  4400. * can be triggered only after the next frame-update. For cmd mode &
  4401. * virtual displays the release fence for the current frame can be
  4402. * triggered right after PP_DONE/WB_DONE interrupt
  4403. */
  4404. if (is_vid)
  4405. offset++;
  4406. /*
  4407. * Hwcomposer now queries the fences using the commit list in atomic
  4408. * commit ioctl. The offset should be set to next timeline
  4409. * which will be incremented during the prepare commit phase
  4410. */
  4411. offset++;
  4412. return sde_fence_create(sde_crtc->output_fence, val, offset);
  4413. }
  4414. /**
  4415. * sde_crtc_atomic_set_property - atomically set a crtc drm property
  4416. * @crtc: Pointer to drm crtc structure
  4417. * @state: Pointer to drm crtc state structure
  4418. * @property: Pointer to targeted drm property
  4419. * @val: Updated property value
  4420. * @Returns: Zero on success
  4421. */
  4422. static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
  4423. struct drm_crtc_state *state,
  4424. struct drm_property *property,
  4425. uint64_t val)
  4426. {
  4427. struct sde_crtc *sde_crtc;
  4428. struct sde_crtc_state *cstate;
  4429. int idx, ret;
  4430. uint64_t fence_user_fd;
  4431. uint64_t __user prev_user_fd;
  4432. if (!crtc || !state || !property) {
  4433. SDE_ERROR("invalid argument(s)\n");
  4434. return -EINVAL;
  4435. }
  4436. sde_crtc = to_sde_crtc(crtc);
  4437. cstate = to_sde_crtc_state(state);
  4438. SDE_ATRACE_BEGIN("sde_crtc_atomic_set_property");
  4439. /* check with cp property system first */
  4440. ret = sde_cp_crtc_set_property(crtc, property, val);
  4441. if (ret != -ENOENT)
  4442. goto exit;
  4443. /* if not handled by cp, check msm_property system */
  4444. ret = msm_property_atomic_set(&sde_crtc->property_info,
  4445. &cstate->property_state, property, val);
  4446. if (ret)
  4447. goto exit;
  4448. idx = msm_property_index(&sde_crtc->property_info, property);
  4449. switch (idx) {
  4450. case CRTC_PROP_INPUT_FENCE_TIMEOUT:
  4451. _sde_crtc_set_input_fence_timeout(cstate);
  4452. break;
  4453. case CRTC_PROP_DIM_LAYER_V1:
  4454. _sde_crtc_set_dim_layer_v1(crtc, cstate,
  4455. (void __user *)(uintptr_t)val);
  4456. break;
  4457. case CRTC_PROP_ROI_V1:
  4458. ret = _sde_crtc_set_roi_v1(state,
  4459. (void __user *)(uintptr_t)val);
  4460. break;
  4461. case CRTC_PROP_DEST_SCALER:
  4462. ret = _sde_crtc_set_dest_scaler(sde_crtc, cstate,
  4463. (void __user *)(uintptr_t)val);
  4464. break;
  4465. case CRTC_PROP_DEST_SCALER_LUT_ED:
  4466. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  4467. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  4468. ret = _sde_crtc_set_dest_scaler_lut(sde_crtc, cstate, idx);
  4469. break;
  4470. case CRTC_PROP_CORE_CLK:
  4471. case CRTC_PROP_CORE_AB:
  4472. case CRTC_PROP_CORE_IB:
  4473. cstate->bw_control = true;
  4474. break;
  4475. case CRTC_PROP_LLCC_AB:
  4476. case CRTC_PROP_LLCC_IB:
  4477. case CRTC_PROP_DRAM_AB:
  4478. case CRTC_PROP_DRAM_IB:
  4479. cstate->bw_control = true;
  4480. cstate->bw_split_vote = true;
  4481. break;
  4482. case CRTC_PROP_OUTPUT_FENCE:
  4483. if (!val)
  4484. goto exit;
  4485. ret = copy_from_user(&prev_user_fd, (void __user *)val,
  4486. sizeof(uint64_t));
  4487. if (ret) {
  4488. SDE_ERROR("copy from user failed rc:%d\n", ret);
  4489. ret = -EFAULT;
  4490. goto exit;
  4491. }
  4492. /*
  4493. * client is expected to reset the property to -1 before
  4494. * requesting for the release fence
  4495. */
  4496. if (prev_user_fd == -1) {
  4497. ret = _sde_crtc_get_output_fence(crtc, state,
  4498. &fence_user_fd);
  4499. if (ret) {
  4500. SDE_ERROR("fence create failed rc:%d\n", ret);
  4501. goto exit;
  4502. }
  4503. ret = copy_to_user((uint64_t __user *)(uintptr_t)val,
  4504. &fence_user_fd, sizeof(uint64_t));
  4505. if (ret) {
  4506. SDE_ERROR("copy to user failed rc:%d\n", ret);
  4507. put_unused_fd(fence_user_fd);
  4508. ret = -EFAULT;
  4509. goto exit;
  4510. }
  4511. }
  4512. break;
  4513. default:
  4514. /* nothing to do */
  4515. break;
  4516. }
  4517. exit:
  4518. if (ret) {
  4519. if (ret != -EPERM)
  4520. SDE_ERROR("%s: failed to set property%d %s: %d\n",
  4521. crtc->name, DRMID(property),
  4522. property->name, ret);
  4523. else
  4524. SDE_DEBUG("%s: failed to set property%d %s: %d\n",
  4525. crtc->name, DRMID(property),
  4526. property->name, ret);
  4527. } else {
  4528. SDE_DEBUG("%s: %s[%d] <= 0x%llx\n", crtc->name, property->name,
  4529. property->base.id, val);
  4530. }
  4531. SDE_ATRACE_END("sde_crtc_atomic_set_property");
  4532. return ret;
  4533. }
  4534. void sde_crtc_set_qos_dirty(struct drm_crtc *crtc)
  4535. {
  4536. struct drm_plane *plane;
  4537. struct drm_plane_state *state;
  4538. struct sde_plane_state *pstate;
  4539. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4540. state = plane->state;
  4541. if (!state)
  4542. continue;
  4543. pstate = to_sde_plane_state(state);
  4544. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  4545. }
  4546. }
  4547. /**
  4548. * sde_crtc_atomic_get_property - retrieve a crtc drm property
  4549. * @crtc: Pointer to drm crtc structure
  4550. * @state: Pointer to drm crtc state structure
  4551. * @property: Pointer to targeted drm property
  4552. * @val: Pointer to variable for receiving property value
  4553. * @Returns: Zero on success
  4554. */
  4555. static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
  4556. const struct drm_crtc_state *state,
  4557. struct drm_property *property,
  4558. uint64_t *val)
  4559. {
  4560. struct sde_crtc *sde_crtc;
  4561. struct sde_crtc_state *cstate;
  4562. int ret = -EINVAL, i;
  4563. if (!crtc || !state) {
  4564. SDE_ERROR("invalid argument(s)\n");
  4565. goto end;
  4566. }
  4567. sde_crtc = to_sde_crtc(crtc);
  4568. cstate = to_sde_crtc_state(state);
  4569. i = msm_property_index(&sde_crtc->property_info, property);
  4570. if (i == CRTC_PROP_OUTPUT_FENCE) {
  4571. *val = ~0;
  4572. ret = 0;
  4573. } else {
  4574. ret = msm_property_atomic_get(&sde_crtc->property_info,
  4575. &cstate->property_state, property, val);
  4576. if (ret)
  4577. ret = sde_cp_crtc_get_property(crtc, property, val);
  4578. }
  4579. if (ret)
  4580. DRM_ERROR("get property failed\n");
  4581. end:
  4582. return ret;
  4583. }
  4584. int sde_crtc_helper_reset_custom_properties(struct drm_crtc *crtc,
  4585. struct drm_crtc_state *crtc_state)
  4586. {
  4587. struct sde_crtc *sde_crtc;
  4588. struct sde_crtc_state *cstate;
  4589. struct drm_property *drm_prop;
  4590. enum msm_mdp_crtc_property prop_idx;
  4591. if (!crtc || !crtc_state) {
  4592. SDE_ERROR("invalid params\n");
  4593. return -EINVAL;
  4594. }
  4595. sde_crtc = to_sde_crtc(crtc);
  4596. cstate = to_sde_crtc_state(crtc_state);
  4597. sde_cp_crtc_clear(crtc);
  4598. for (prop_idx = 0; prop_idx < CRTC_PROP_COUNT; prop_idx++) {
  4599. uint64_t val = cstate->property_values[prop_idx].value;
  4600. uint64_t def;
  4601. int ret;
  4602. drm_prop = msm_property_index_to_drm_property(
  4603. &sde_crtc->property_info, prop_idx);
  4604. if (!drm_prop) {
  4605. /* not all props will be installed, based on caps */
  4606. SDE_DEBUG("%s: invalid property index %d\n",
  4607. sde_crtc->name, prop_idx);
  4608. continue;
  4609. }
  4610. def = msm_property_get_default(&sde_crtc->property_info,
  4611. prop_idx);
  4612. if (val == def)
  4613. continue;
  4614. SDE_DEBUG("%s: set prop %s idx %d from %llu to %llu\n",
  4615. sde_crtc->name, drm_prop->name, prop_idx, val,
  4616. def);
  4617. ret = sde_crtc_atomic_set_property(crtc, crtc_state, drm_prop,
  4618. def);
  4619. if (ret) {
  4620. SDE_ERROR("%s: set property failed, idx %d ret %d\n",
  4621. sde_crtc->name, prop_idx, ret);
  4622. continue;
  4623. }
  4624. }
  4625. return 0;
  4626. }
  4627. void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count)
  4628. {
  4629. struct sde_crtc *sde_crtc;
  4630. struct sde_crtc_mixer *m;
  4631. int i;
  4632. if (!crtc) {
  4633. SDE_ERROR("invalid argument\n");
  4634. return;
  4635. }
  4636. sde_crtc = to_sde_crtc(crtc);
  4637. sde_crtc->misr_enable_sui = enable;
  4638. sde_crtc->misr_frame_count = frame_count;
  4639. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4640. m = &sde_crtc->mixers[i];
  4641. if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
  4642. continue;
  4643. m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
  4644. }
  4645. }
  4646. void sde_crtc_get_misr_info(struct drm_crtc *crtc,
  4647. struct sde_crtc_misr_info *crtc_misr_info)
  4648. {
  4649. struct sde_crtc *sde_crtc;
  4650. struct sde_kms *sde_kms;
  4651. if (!crtc_misr_info) {
  4652. SDE_ERROR("invalid misr info\n");
  4653. return;
  4654. }
  4655. crtc_misr_info->misr_enable = false;
  4656. crtc_misr_info->misr_frame_count = 0;
  4657. if (!crtc) {
  4658. SDE_ERROR("invalid crtc\n");
  4659. return;
  4660. }
  4661. sde_kms = _sde_crtc_get_kms(crtc);
  4662. if (!sde_kms) {
  4663. SDE_ERROR("invalid sde_kms\n");
  4664. return;
  4665. }
  4666. if (sde_kms_is_secure_session_inprogress(sde_kms))
  4667. return;
  4668. sde_crtc = to_sde_crtc(crtc);
  4669. crtc_misr_info->misr_enable =
  4670. sde_crtc->misr_enable_debugfs ? true : false;
  4671. crtc_misr_info->misr_frame_count = sde_crtc->misr_frame_count;
  4672. }
  4673. #ifdef CONFIG_DEBUG_FS
  4674. static int _sde_debugfs_status_show(struct seq_file *s, void *data)
  4675. {
  4676. struct sde_crtc *sde_crtc;
  4677. struct sde_plane_state *pstate = NULL;
  4678. struct sde_crtc_mixer *m;
  4679. struct drm_crtc *crtc;
  4680. struct drm_plane *plane;
  4681. struct drm_display_mode *mode;
  4682. struct drm_framebuffer *fb;
  4683. struct drm_plane_state *state;
  4684. struct sde_crtc_state *cstate;
  4685. int i, out_width, out_height;
  4686. if (!s || !s->private)
  4687. return -EINVAL;
  4688. sde_crtc = s->private;
  4689. crtc = &sde_crtc->base;
  4690. cstate = to_sde_crtc_state(crtc->state);
  4691. mutex_lock(&sde_crtc->crtc_lock);
  4692. mode = &crtc->state->adjusted_mode;
  4693. out_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  4694. out_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  4695. seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
  4696. mode->hdisplay, mode->vdisplay);
  4697. seq_puts(s, "\n");
  4698. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4699. m = &sde_crtc->mixers[i];
  4700. if (!m->hw_lm)
  4701. seq_printf(s, "\tmixer[%d] has no lm\n", i);
  4702. else if (!m->hw_ctl)
  4703. seq_printf(s, "\tmixer[%d] has no ctl\n", i);
  4704. else
  4705. seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
  4706. m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
  4707. out_width, out_height);
  4708. }
  4709. seq_puts(s, "\n");
  4710. for (i = 0; i < cstate->num_dim_layers; i++) {
  4711. struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i];
  4712. seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n",
  4713. i, dim_layer->stage, dim_layer->flags);
  4714. seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n",
  4715. dim_layer->rect.x, dim_layer->rect.y,
  4716. dim_layer->rect.w, dim_layer->rect.h);
  4717. seq_printf(s,
  4718. "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n",
  4719. dim_layer->color_fill.color_0,
  4720. dim_layer->color_fill.color_1,
  4721. dim_layer->color_fill.color_2,
  4722. dim_layer->color_fill.color_3);
  4723. seq_puts(s, "\n");
  4724. }
  4725. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4726. pstate = to_sde_plane_state(plane->state);
  4727. state = plane->state;
  4728. if (!pstate || !state)
  4729. continue;
  4730. seq_printf(s, "\tplane:%u stage:%d rotation:%d\n",
  4731. plane->base.id, pstate->stage, pstate->rotation);
  4732. if (plane->state->fb) {
  4733. fb = plane->state->fb;
  4734. seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
  4735. fb->base.id, (char *) &fb->format->format,
  4736. fb->width, fb->height);
  4737. for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
  4738. seq_printf(s, "cpp[%d]:%u ",
  4739. i, fb->format->cpp[i]);
  4740. seq_puts(s, "\n\t");
  4741. seq_printf(s, "modifier:%8llu ", fb->modifier);
  4742. seq_puts(s, "\n");
  4743. seq_puts(s, "\t");
  4744. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
  4745. seq_printf(s, "pitches[%d]:%8u ", i,
  4746. fb->pitches[i]);
  4747. seq_puts(s, "\n");
  4748. seq_puts(s, "\t");
  4749. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
  4750. seq_printf(s, "offsets[%d]:%8u ", i,
  4751. fb->offsets[i]);
  4752. seq_puts(s, "\n");
  4753. }
  4754. seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
  4755. state->src_x >> 16, state->src_y >> 16,
  4756. state->src_w >> 16, state->src_h >> 16);
  4757. seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
  4758. state->crtc_x, state->crtc_y, state->crtc_w,
  4759. state->crtc_h);
  4760. seq_printf(s, "\tmultirect: mode: %d index: %d\n",
  4761. pstate->multirect_mode, pstate->multirect_index);
  4762. seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n",
  4763. pstate->excl_rect.x, pstate->excl_rect.y,
  4764. pstate->excl_rect.w, pstate->excl_rect.h);
  4765. seq_puts(s, "\n");
  4766. }
  4767. if (sde_crtc->vblank_cb_count) {
  4768. ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
  4769. u32 diff_ms = ktime_to_ms(diff);
  4770. u64 fps = diff_ms ? DIV_ROUND_CLOSEST(
  4771. sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
  4772. seq_printf(s,
  4773. "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
  4774. fps, sde_crtc->vblank_cb_count,
  4775. ktime_to_ms(diff), sde_crtc->play_count);
  4776. /* reset time & count for next measurement */
  4777. sde_crtc->vblank_cb_count = 0;
  4778. sde_crtc->vblank_cb_time = ktime_set(0, 0);
  4779. }
  4780. mutex_unlock(&sde_crtc->crtc_lock);
  4781. return 0;
  4782. }
  4783. static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
  4784. {
  4785. return single_open(file, _sde_debugfs_status_show, inode->i_private);
  4786. }
  4787. static ssize_t _sde_crtc_misr_setup(struct file *file,
  4788. const char __user *user_buf, size_t count, loff_t *ppos)
  4789. {
  4790. struct drm_crtc *crtc;
  4791. struct sde_crtc *sde_crtc;
  4792. int rc;
  4793. char buf[MISR_BUFF_SIZE + 1];
  4794. u32 frame_count, enable;
  4795. size_t buff_copy;
  4796. struct sde_kms *sde_kms;
  4797. if (!file || !file->private_data)
  4798. return -EINVAL;
  4799. sde_crtc = file->private_data;
  4800. crtc = &sde_crtc->base;
  4801. sde_kms = _sde_crtc_get_kms(crtc);
  4802. if (!sde_kms) {
  4803. SDE_ERROR("invalid sde_kms\n");
  4804. return -EINVAL;
  4805. }
  4806. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  4807. if (copy_from_user(buf, user_buf, buff_copy)) {
  4808. SDE_ERROR("buffer copy failed\n");
  4809. return -EINVAL;
  4810. }
  4811. buf[buff_copy] = 0; /* end of string */
  4812. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  4813. return -EINVAL;
  4814. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4815. SDE_DEBUG("crtc:%d misr enable/disable not allowed\n",
  4816. DRMID(crtc));
  4817. return -EINVAL;
  4818. }
  4819. rc = pm_runtime_get_sync(crtc->dev->dev);
  4820. if (rc < 0)
  4821. return rc;
  4822. sde_crtc->misr_enable_debugfs = enable;
  4823. sde_crtc_misr_setup(crtc, enable, frame_count);
  4824. pm_runtime_put_sync(crtc->dev->dev);
  4825. return count;
  4826. }
  4827. static ssize_t _sde_crtc_misr_read(struct file *file,
  4828. char __user *user_buff, size_t count, loff_t *ppos)
  4829. {
  4830. struct drm_crtc *crtc;
  4831. struct sde_crtc *sde_crtc;
  4832. struct sde_kms *sde_kms;
  4833. struct sde_crtc_mixer *m;
  4834. int i = 0, rc;
  4835. ssize_t len = 0;
  4836. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  4837. if (*ppos)
  4838. return 0;
  4839. if (!file || !file->private_data)
  4840. return -EINVAL;
  4841. sde_crtc = file->private_data;
  4842. crtc = &sde_crtc->base;
  4843. sde_kms = _sde_crtc_get_kms(crtc);
  4844. if (!sde_kms)
  4845. return -EINVAL;
  4846. rc = pm_runtime_get_sync(crtc->dev->dev);
  4847. if (rc < 0)
  4848. return rc;
  4849. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  4850. SDE_DEBUG("crtc:%d misr read not allowed\n", DRMID(crtc));
  4851. goto end;
  4852. }
  4853. if (!sde_crtc->misr_enable_debugfs) {
  4854. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4855. "disabled\n");
  4856. goto buff_check;
  4857. }
  4858. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  4859. u32 misr_value = 0;
  4860. m = &sde_crtc->mixers[i];
  4861. if (!m->hw_lm || !m->hw_lm->ops.collect_misr) {
  4862. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4863. "invalid\n");
  4864. SDE_ERROR("crtc:%d invalid misr ops\n", DRMID(crtc));
  4865. continue;
  4866. }
  4867. rc = m->hw_lm->ops.collect_misr(m->hw_lm, false, &misr_value);
  4868. if (rc) {
  4869. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4870. "invalid\n");
  4871. SDE_ERROR("crtc:%d failed to collect misr %d\n",
  4872. DRMID(crtc), rc);
  4873. continue;
  4874. } else {
  4875. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4876. "lm idx:%d\n", m->hw_lm->idx - LM_0);
  4877. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  4878. "0x%x\n", misr_value);
  4879. }
  4880. }
  4881. buff_check:
  4882. if (count <= len) {
  4883. len = 0;
  4884. goto end;
  4885. }
  4886. if (copy_to_user(user_buff, buf, len)) {
  4887. len = -EFAULT;
  4888. goto end;
  4889. }
  4890. *ppos += len; /* increase offset */
  4891. end:
  4892. pm_runtime_put_sync(crtc->dev->dev);
  4893. return len;
  4894. }
  4895. #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \
  4896. static int __prefix ## _open(struct inode *inode, struct file *file) \
  4897. { \
  4898. return single_open(file, __prefix ## _show, inode->i_private); \
  4899. } \
  4900. static const struct file_operations __prefix ## _fops = { \
  4901. .owner = THIS_MODULE, \
  4902. .open = __prefix ## _open, \
  4903. .release = single_release, \
  4904. .read = seq_read, \
  4905. .llseek = seq_lseek, \
  4906. }
  4907. static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
  4908. {
  4909. struct drm_crtc *crtc = (struct drm_crtc *) s->private;
  4910. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4911. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  4912. int i;
  4913. seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
  4914. seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
  4915. seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc,
  4916. crtc->state));
  4917. seq_printf(s, "core_clk_rate: %llu\n",
  4918. sde_crtc->cur_perf.core_clk_rate);
  4919. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  4920. i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
  4921. seq_printf(s, "bw_ctl[%s]: %llu\n",
  4922. sde_power_handle_get_dbus_name(i),
  4923. sde_crtc->cur_perf.bw_ctl[i]);
  4924. seq_printf(s, "max_per_pipe_ib[%s]: %llu\n",
  4925. sde_power_handle_get_dbus_name(i),
  4926. sde_crtc->cur_perf.max_per_pipe_ib[i]);
  4927. }
  4928. return 0;
  4929. }
  4930. DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
  4931. static int _sde_debugfs_fence_status_show(struct seq_file *s, void *data)
  4932. {
  4933. struct drm_crtc *crtc;
  4934. struct drm_plane *plane;
  4935. struct drm_connector *conn;
  4936. struct drm_mode_object *drm_obj;
  4937. struct sde_crtc *sde_crtc;
  4938. struct sde_crtc_state *cstate;
  4939. struct sde_fence_context *ctx;
  4940. struct drm_connector_list_iter conn_iter;
  4941. struct drm_device *dev;
  4942. if (!s || !s->private)
  4943. return -EINVAL;
  4944. sde_crtc = s->private;
  4945. crtc = &sde_crtc->base;
  4946. dev = crtc->dev;
  4947. cstate = to_sde_crtc_state(crtc->state);
  4948. /* Dump input fence info */
  4949. seq_puts(s, "===Input fence===\n");
  4950. drm_atomic_crtc_for_each_plane(plane, crtc) {
  4951. struct sde_plane_state *pstate;
  4952. struct dma_fence *fence;
  4953. pstate = to_sde_plane_state(plane->state);
  4954. if (!pstate)
  4955. continue;
  4956. seq_printf(s, "plane:%u stage:%d\n", plane->base.id,
  4957. pstate->stage);
  4958. fence = pstate->input_fence;
  4959. if (fence)
  4960. sde_fence_list_dump(fence, &s);
  4961. }
  4962. /* Dump release fence info */
  4963. seq_puts(s, "\n");
  4964. seq_puts(s, "===Release fence===\n");
  4965. ctx = sde_crtc->output_fence;
  4966. drm_obj = &crtc->base;
  4967. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  4968. seq_puts(s, "\n");
  4969. /* Dump retire fence info */
  4970. seq_puts(s, "===Retire fence===\n");
  4971. drm_connector_list_iter_begin(dev, &conn_iter);
  4972. drm_for_each_connector_iter(conn, &conn_iter)
  4973. if (conn->state && conn->state->crtc == crtc &&
  4974. cstate->num_connectors < MAX_CONNECTORS) {
  4975. struct sde_connector *c_conn;
  4976. c_conn = to_sde_connector(conn);
  4977. ctx = c_conn->retire_fence;
  4978. drm_obj = &conn->base;
  4979. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  4980. }
  4981. drm_connector_list_iter_end(&conn_iter);
  4982. seq_puts(s, "\n");
  4983. return 0;
  4984. }
  4985. static int _sde_debugfs_fence_status(struct inode *inode, struct file *file)
  4986. {
  4987. return single_open(file, _sde_debugfs_fence_status_show,
  4988. inode->i_private);
  4989. }
  4990. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  4991. {
  4992. struct sde_crtc *sde_crtc;
  4993. struct sde_kms *sde_kms;
  4994. static const struct file_operations debugfs_status_fops = {
  4995. .open = _sde_debugfs_status_open,
  4996. .read = seq_read,
  4997. .llseek = seq_lseek,
  4998. .release = single_release,
  4999. };
  5000. static const struct file_operations debugfs_misr_fops = {
  5001. .open = simple_open,
  5002. .read = _sde_crtc_misr_read,
  5003. .write = _sde_crtc_misr_setup,
  5004. };
  5005. static const struct file_operations debugfs_fps_fops = {
  5006. .open = _sde_debugfs_fps_status,
  5007. .read = seq_read,
  5008. };
  5009. static const struct file_operations debugfs_fence_fops = {
  5010. .open = _sde_debugfs_fence_status,
  5011. .read = seq_read,
  5012. };
  5013. if (!crtc)
  5014. return -EINVAL;
  5015. sde_crtc = to_sde_crtc(crtc);
  5016. sde_kms = _sde_crtc_get_kms(crtc);
  5017. if (!sde_kms)
  5018. return -EINVAL;
  5019. sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
  5020. crtc->dev->primary->debugfs_root);
  5021. if (!sde_crtc->debugfs_root)
  5022. return -ENOMEM;
  5023. /* don't error check these */
  5024. debugfs_create_file("status", 0400,
  5025. sde_crtc->debugfs_root,
  5026. sde_crtc, &debugfs_status_fops);
  5027. debugfs_create_file("state", 0400,
  5028. sde_crtc->debugfs_root,
  5029. &sde_crtc->base,
  5030. &sde_crtc_debugfs_state_fops);
  5031. debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root,
  5032. sde_crtc, &debugfs_misr_fops);
  5033. debugfs_create_file("fps", 0400, sde_crtc->debugfs_root,
  5034. sde_crtc, &debugfs_fps_fops);
  5035. debugfs_create_file("fence_status", 0400, sde_crtc->debugfs_root,
  5036. sde_crtc, &debugfs_fence_fops);
  5037. return 0;
  5038. }
  5039. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5040. {
  5041. struct sde_crtc *sde_crtc;
  5042. if (!crtc)
  5043. return;
  5044. sde_crtc = to_sde_crtc(crtc);
  5045. debugfs_remove_recursive(sde_crtc->debugfs_root);
  5046. }
  5047. #else
  5048. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  5049. {
  5050. return 0;
  5051. }
  5052. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5053. {
  5054. }
  5055. #endif /* CONFIG_DEBUG_FS */
  5056. static int sde_crtc_late_register(struct drm_crtc *crtc)
  5057. {
  5058. return _sde_crtc_init_debugfs(crtc);
  5059. }
  5060. static void sde_crtc_early_unregister(struct drm_crtc *crtc)
  5061. {
  5062. _sde_crtc_destroy_debugfs(crtc);
  5063. }
  5064. static const struct drm_crtc_funcs sde_crtc_funcs = {
  5065. .set_config = drm_atomic_helper_set_config,
  5066. .destroy = sde_crtc_destroy,
  5067. .page_flip = drm_atomic_helper_page_flip,
  5068. .atomic_set_property = sde_crtc_atomic_set_property,
  5069. .atomic_get_property = sde_crtc_atomic_get_property,
  5070. .reset = sde_crtc_reset,
  5071. .atomic_duplicate_state = sde_crtc_duplicate_state,
  5072. .atomic_destroy_state = sde_crtc_destroy_state,
  5073. .late_register = sde_crtc_late_register,
  5074. .early_unregister = sde_crtc_early_unregister,
  5075. };
  5076. static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
  5077. .mode_fixup = sde_crtc_mode_fixup,
  5078. .disable = sde_crtc_disable,
  5079. .atomic_enable = sde_crtc_enable,
  5080. .atomic_check = sde_crtc_atomic_check,
  5081. .atomic_begin = sde_crtc_atomic_begin,
  5082. .atomic_flush = sde_crtc_atomic_flush,
  5083. };
  5084. static void _sde_crtc_event_cb(struct kthread_work *work)
  5085. {
  5086. struct sde_crtc_event *event;
  5087. struct sde_crtc *sde_crtc;
  5088. unsigned long irq_flags;
  5089. if (!work) {
  5090. SDE_ERROR("invalid work item\n");
  5091. return;
  5092. }
  5093. event = container_of(work, struct sde_crtc_event, kt_work);
  5094. /* set sde_crtc to NULL for static work structures */
  5095. sde_crtc = event->sde_crtc;
  5096. if (!sde_crtc)
  5097. return;
  5098. if (event->cb_func)
  5099. event->cb_func(&sde_crtc->base, event->usr);
  5100. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5101. list_add_tail(&event->list, &sde_crtc->event_free_list);
  5102. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5103. }
  5104. int sde_crtc_event_queue(struct drm_crtc *crtc,
  5105. void (*func)(struct drm_crtc *crtc, void *usr),
  5106. void *usr, bool color_processing_event)
  5107. {
  5108. unsigned long irq_flags;
  5109. struct sde_crtc *sde_crtc;
  5110. struct msm_drm_private *priv;
  5111. struct sde_crtc_event *event = NULL;
  5112. u32 crtc_id;
  5113. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) {
  5114. SDE_ERROR("invalid parameters\n");
  5115. return -EINVAL;
  5116. }
  5117. sde_crtc = to_sde_crtc(crtc);
  5118. priv = crtc->dev->dev_private;
  5119. crtc_id = drm_crtc_index(crtc);
  5120. /*
  5121. * Obtain an event struct from the private cache. This event
  5122. * queue may be called from ISR contexts, so use a private
  5123. * cache to avoid calling any memory allocation functions.
  5124. */
  5125. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5126. if (!list_empty(&sde_crtc->event_free_list)) {
  5127. event = list_first_entry(&sde_crtc->event_free_list,
  5128. struct sde_crtc_event, list);
  5129. list_del_init(&event->list);
  5130. }
  5131. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5132. if (!event)
  5133. return -ENOMEM;
  5134. /* populate event node */
  5135. event->sde_crtc = sde_crtc;
  5136. event->cb_func = func;
  5137. event->usr = usr;
  5138. /* queue new event request */
  5139. kthread_init_work(&event->kt_work, _sde_crtc_event_cb);
  5140. if (color_processing_event)
  5141. kthread_queue_work(&priv->pp_event_worker,
  5142. &event->kt_work);
  5143. else
  5144. kthread_queue_work(&priv->event_thread[crtc_id].worker,
  5145. &event->kt_work);
  5146. return 0;
  5147. }
  5148. static int _sde_crtc_init_events(struct sde_crtc *sde_crtc)
  5149. {
  5150. int i, rc = 0;
  5151. if (!sde_crtc) {
  5152. SDE_ERROR("invalid crtc\n");
  5153. return -EINVAL;
  5154. }
  5155. spin_lock_init(&sde_crtc->event_lock);
  5156. INIT_LIST_HEAD(&sde_crtc->event_free_list);
  5157. for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i)
  5158. list_add_tail(&sde_crtc->event_cache[i].list,
  5159. &sde_crtc->event_free_list);
  5160. return rc;
  5161. }
  5162. /*
  5163. * __sde_crtc_idle_notify_work - signal idle timeout to user space
  5164. */
  5165. static void __sde_crtc_idle_notify_work(struct kthread_work *work)
  5166. {
  5167. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5168. idle_notify_work.work);
  5169. struct drm_crtc *crtc;
  5170. struct drm_event event;
  5171. int ret = 0;
  5172. if (!sde_crtc) {
  5173. SDE_ERROR("invalid sde crtc\n");
  5174. } else {
  5175. crtc = &sde_crtc->base;
  5176. event.type = DRM_EVENT_IDLE_NOTIFY;
  5177. event.length = sizeof(u32);
  5178. msm_mode_object_event_notify(&crtc->base, crtc->dev,
  5179. &event, (u8 *)&ret);
  5180. SDE_DEBUG("crtc[%d]: idle timeout notified\n", crtc->base.id);
  5181. }
  5182. }
  5183. /* initialize crtc */
  5184. struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
  5185. {
  5186. struct drm_crtc *crtc = NULL;
  5187. struct sde_crtc *sde_crtc = NULL;
  5188. struct msm_drm_private *priv = NULL;
  5189. struct sde_kms *kms = NULL;
  5190. int i, rc;
  5191. priv = dev->dev_private;
  5192. kms = to_sde_kms(priv->kms);
  5193. sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
  5194. if (!sde_crtc)
  5195. return ERR_PTR(-ENOMEM);
  5196. crtc = &sde_crtc->base;
  5197. crtc->dev = dev;
  5198. mutex_init(&sde_crtc->crtc_lock);
  5199. spin_lock_init(&sde_crtc->spin_lock);
  5200. atomic_set(&sde_crtc->frame_pending, 0);
  5201. sde_crtc->enabled = false;
  5202. /* Below parameters are for fps calculation for sysfs node */
  5203. sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC;
  5204. sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT,
  5205. sizeof(ktime_t), GFP_KERNEL);
  5206. if (!sde_crtc->fps_info.time_buf)
  5207. SDE_ERROR("invalid buffer\n");
  5208. else
  5209. memset(sde_crtc->fps_info.time_buf, 0,
  5210. sizeof(*(sde_crtc->fps_info.time_buf)));
  5211. INIT_LIST_HEAD(&sde_crtc->frame_event_list);
  5212. INIT_LIST_HEAD(&sde_crtc->user_event_list);
  5213. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  5214. INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
  5215. list_add(&sde_crtc->frame_events[i].list,
  5216. &sde_crtc->frame_event_list);
  5217. kthread_init_work(&sde_crtc->frame_events[i].work,
  5218. sde_crtc_frame_event_work);
  5219. }
  5220. drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs,
  5221. NULL);
  5222. drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
  5223. /* save user friendly CRTC name for later */
  5224. snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
  5225. /* initialize event handling */
  5226. rc = _sde_crtc_init_events(sde_crtc);
  5227. if (rc) {
  5228. drm_crtc_cleanup(crtc);
  5229. kfree(sde_crtc);
  5230. return ERR_PTR(rc);
  5231. }
  5232. /* initialize output fence support */
  5233. sde_crtc->output_fence = sde_fence_init(sde_crtc->name, crtc->base.id);
  5234. if (IS_ERR(sde_crtc->output_fence)) {
  5235. rc = PTR_ERR(sde_crtc->output_fence);
  5236. SDE_ERROR("failed to init fence, %d\n", rc);
  5237. drm_crtc_cleanup(crtc);
  5238. kfree(sde_crtc);
  5239. return ERR_PTR(rc);
  5240. }
  5241. /* create CRTC properties */
  5242. msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
  5243. priv->crtc_property, sde_crtc->property_data,
  5244. CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
  5245. sizeof(struct sde_crtc_state));
  5246. sde_crtc_install_properties(crtc, kms->catalog);
  5247. /* Install color processing properties */
  5248. sde_cp_crtc_init(crtc);
  5249. sde_cp_crtc_install_properties(crtc);
  5250. sde_crtc->cur_perf.llcc_active = false;
  5251. sde_crtc->new_perf.llcc_active = false;
  5252. kthread_init_delayed_work(&sde_crtc->idle_notify_work,
  5253. __sde_crtc_idle_notify_work);
  5254. SDE_DEBUG("crtc=%d new_llcc=%d, old_llcc=%d\n",
  5255. crtc->base.id,
  5256. sde_crtc->new_perf.llcc_active,
  5257. sde_crtc->cur_perf.llcc_active);
  5258. SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);
  5259. return crtc;
  5260. }
  5261. int sde_crtc_post_init(struct drm_device *dev, struct drm_crtc *crtc)
  5262. {
  5263. struct sde_crtc *sde_crtc;
  5264. int rc = 0;
  5265. if (!dev || !dev->primary || !dev->primary->kdev || !crtc) {
  5266. SDE_ERROR("invalid input param(s)\n");
  5267. rc = -EINVAL;
  5268. goto end;
  5269. }
  5270. sde_crtc = to_sde_crtc(crtc);
  5271. sde_crtc->sysfs_dev = device_create_with_groups(
  5272. dev->primary->kdev->class, dev->primary->kdev, 0, crtc,
  5273. sde_crtc_attr_groups, "sde-crtc-%d", crtc->index);
  5274. if (IS_ERR_OR_NULL(sde_crtc->sysfs_dev)) {
  5275. SDE_ERROR("crtc:%d sysfs create failed rc:%ld\n", crtc->index,
  5276. PTR_ERR(sde_crtc->sysfs_dev));
  5277. if (!sde_crtc->sysfs_dev)
  5278. rc = -EINVAL;
  5279. else
  5280. rc = PTR_ERR(sde_crtc->sysfs_dev);
  5281. goto end;
  5282. }
  5283. sde_crtc->vsync_event_sf = sysfs_get_dirent(
  5284. sde_crtc->sysfs_dev->kobj.sd, "vsync_event");
  5285. if (!sde_crtc->vsync_event_sf)
  5286. SDE_ERROR("crtc:%d vsync_event sysfs create failed\n",
  5287. crtc->base.id);
  5288. end:
  5289. return rc;
  5290. }
  5291. static int _sde_crtc_event_enable(struct sde_kms *kms,
  5292. struct drm_crtc *crtc_drm, u32 event)
  5293. {
  5294. struct sde_crtc *crtc = NULL;
  5295. struct sde_crtc_irq_info *node;
  5296. unsigned long flags;
  5297. bool found = false;
  5298. int ret, i = 0;
  5299. bool add_event = false;
  5300. crtc = to_sde_crtc(crtc_drm);
  5301. spin_lock_irqsave(&crtc->spin_lock, flags);
  5302. list_for_each_entry(node, &crtc->user_event_list, list) {
  5303. if (node->event == event) {
  5304. found = true;
  5305. break;
  5306. }
  5307. }
  5308. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5309. /* event already enabled */
  5310. if (found)
  5311. return 0;
  5312. node = NULL;
  5313. for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
  5314. if (custom_events[i].event == event &&
  5315. custom_events[i].func) {
  5316. node = kzalloc(sizeof(*node), GFP_KERNEL);
  5317. if (!node)
  5318. return -ENOMEM;
  5319. INIT_LIST_HEAD(&node->list);
  5320. INIT_LIST_HEAD(&node->irq.list);
  5321. node->func = custom_events[i].func;
  5322. node->event = event;
  5323. node->state = IRQ_NOINIT;
  5324. spin_lock_init(&node->state_lock);
  5325. break;
  5326. }
  5327. }
  5328. if (!node) {
  5329. SDE_ERROR("unsupported event %x\n", event);
  5330. return -EINVAL;
  5331. }
  5332. ret = 0;
  5333. if (crtc_drm->enabled) {
  5334. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5335. if (ret < 0) {
  5336. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5337. kfree(node);
  5338. return ret;
  5339. }
  5340. INIT_LIST_HEAD(&node->irq.list);
  5341. mutex_lock(&crtc->crtc_lock);
  5342. ret = node->func(crtc_drm, true, &node->irq);
  5343. if (!ret) {
  5344. spin_lock_irqsave(&crtc->spin_lock, flags);
  5345. list_add_tail(&node->list, &crtc->user_event_list);
  5346. add_event = true;
  5347. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5348. }
  5349. mutex_unlock(&crtc->crtc_lock);
  5350. pm_runtime_put_sync(crtc_drm->dev->dev);
  5351. }
  5352. if (add_event)
  5353. return 0;
  5354. if (!ret) {
  5355. spin_lock_irqsave(&crtc->spin_lock, flags);
  5356. list_add_tail(&node->list, &crtc->user_event_list);
  5357. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5358. } else {
  5359. kfree(node);
  5360. }
  5361. return ret;
  5362. }
  5363. static int _sde_crtc_event_disable(struct sde_kms *kms,
  5364. struct drm_crtc *crtc_drm, u32 event)
  5365. {
  5366. struct sde_crtc *crtc = NULL;
  5367. struct sde_crtc_irq_info *node = NULL;
  5368. unsigned long flags;
  5369. bool found = false;
  5370. int ret;
  5371. crtc = to_sde_crtc(crtc_drm);
  5372. spin_lock_irqsave(&crtc->spin_lock, flags);
  5373. list_for_each_entry(node, &crtc->user_event_list, list) {
  5374. if (node->event == event) {
  5375. list_del_init(&node->list);
  5376. found = true;
  5377. break;
  5378. }
  5379. }
  5380. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5381. /* event already disabled */
  5382. if (!found)
  5383. return 0;
  5384. /**
  5385. * crtc is disabled interrupts are cleared remove from the list,
  5386. * no need to disable/de-register.
  5387. */
  5388. if (!crtc_drm->enabled) {
  5389. kfree(node);
  5390. return 0;
  5391. }
  5392. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  5393. if (ret < 0) {
  5394. SDE_ERROR("failed to enable power resource %d\n", ret);
  5395. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  5396. kfree(node);
  5397. return ret;
  5398. }
  5399. ret = node->func(crtc_drm, false, &node->irq);
  5400. if (ret) {
  5401. spin_lock_irqsave(&crtc->spin_lock, flags);
  5402. list_add_tail(&node->list, &crtc->user_event_list);
  5403. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  5404. } else {
  5405. kfree(node);
  5406. }
  5407. pm_runtime_put_sync(crtc_drm->dev->dev);
  5408. return ret;
  5409. }
  5410. int sde_crtc_register_custom_event(struct sde_kms *kms,
  5411. struct drm_crtc *crtc_drm, u32 event, bool en)
  5412. {
  5413. struct sde_crtc *crtc = NULL;
  5414. int ret;
  5415. crtc = to_sde_crtc(crtc_drm);
  5416. if (!crtc || !kms || !kms->dev) {
  5417. DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc,
  5418. kms, ((kms) ? (kms->dev) : NULL));
  5419. return -EINVAL;
  5420. }
  5421. if (en)
  5422. ret = _sde_crtc_event_enable(kms, crtc_drm, event);
  5423. else
  5424. ret = _sde_crtc_event_disable(kms, crtc_drm, event);
  5425. return ret;
  5426. }
  5427. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  5428. bool en, struct sde_irq_callback *irq)
  5429. {
  5430. return 0;
  5431. }
  5432. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  5433. struct sde_irq_callback *noirq)
  5434. {
  5435. /*
  5436. * IRQ object noirq is not being used here since there is
  5437. * no crtc irq from pm event.
  5438. */
  5439. return 0;
  5440. }
  5441. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  5442. bool en, struct sde_irq_callback *irq)
  5443. {
  5444. return 0;
  5445. }
  5446. /**
  5447. * sde_crtc_update_cont_splash_settings - update mixer settings
  5448. * and initial clk during device bootup for cont_splash use case
  5449. * @crtc: Pointer to drm crtc structure
  5450. */
  5451. void sde_crtc_update_cont_splash_settings(struct drm_crtc *crtc)
  5452. {
  5453. struct sde_kms *kms = NULL;
  5454. struct msm_drm_private *priv;
  5455. struct sde_crtc *sde_crtc;
  5456. u64 rate;
  5457. if (!crtc || !crtc->state || !crtc->dev || !crtc->dev->dev_private) {
  5458. SDE_ERROR("invalid crtc\n");
  5459. return;
  5460. }
  5461. priv = crtc->dev->dev_private;
  5462. kms = to_sde_kms(priv->kms);
  5463. if (!kms || !kms->catalog) {
  5464. SDE_ERROR("invalid parameters\n");
  5465. return;
  5466. }
  5467. _sde_crtc_setup_mixers(crtc);
  5468. crtc->enabled = true;
  5469. /* update core clk value for initial state with cont-splash */
  5470. sde_crtc = to_sde_crtc(crtc);
  5471. rate = sde_power_clk_get_rate(&priv->phandle, kms->perf.clk_name);
  5472. sde_crtc->cur_perf.core_clk_rate = (rate > 0) ?
  5473. rate : kms->perf.max_core_clk_rate;
  5474. sde_crtc->cur_perf.core_clk_rate = kms->perf.max_core_clk_rate;
  5475. }