hal_tx.h 28 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #if !defined(HAL_TX_H)
  20. #define HAL_TX_H
  21. /*---------------------------------------------------------------------------
  22. Include files
  23. ---------------------------------------------------------------------------*/
  24. #include "hal_api.h"
  25. #include "wcss_version.h"
  26. #include "hal_hw_headers.h"
  27. #include "hal_tx_hw_defines.h"
  28. #define HAL_WBM_RELEASE_RING_2_BUFFER_TYPE 0
  29. #define HAL_WBM_RELEASE_RING_2_DESC_TYPE 1
  30. #define HAL_TX_DESC_TLV_TAG_OFFSET 1
  31. #define HAL_TX_DESC_TLV_LEN_OFFSET 10
  32. /*---------------------------------------------------------------------------
  33. Preprocessor definitions and constants
  34. ---------------------------------------------------------------------------*/
  35. #define HAL_OFFSET(block, field) block ## _ ## field ## _OFFSET
  36. #define HAL_TX_LSB(block, field) block ## _ ## field ## _LSB
  37. #define HAL_TX_MASK(block, field) block ## _ ## field ## _MASK
  38. #define HAL_TX_DESC_OFFSET(desc, block, field) \
  39. (((uint8_t *)desc) + HAL_OFFSET(block, field))
  40. #define HAL_SET_FLD(desc, block , field) \
  41. (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field)))
  42. #define HAL_SET_FLD_OFFSET(desc, block , field, offset) \
  43. (*(uint32_t *) ((uint8_t *) desc + HAL_OFFSET(block, field) + (offset)))
  44. #define HAL_SET_FLD_64(desc, block, field) \
  45. (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field)))
  46. #define HAL_SET_FLD_OFFSET_64(desc, block, field, offset) \
  47. (*(uint64_t *)((uint8_t *)desc + HAL_OFFSET(block, field) + (offset)))
  48. #define HAL_TX_DESC_SET_TLV_HDR(desc, tag, len) \
  49. do { \
  50. uint32_t temp = 0; \
  51. temp |= (tag << HAL_TX_DESC_TLV_TAG_OFFSET); \
  52. temp |= (len << HAL_TX_DESC_TLV_LEN_OFFSET); \
  53. (*(uint32_t *)desc) = temp; \
  54. } while (0)
  55. #define HAL_TX_TCL_DATA_TAG WIFITCL_DATA_CMD_E
  56. #define HAL_TX_TCL_CMD_TAG WIFITCL_GSE_CMD_E
  57. #define HAL_TX_SM(block, field, value) \
  58. ((value << (block ## _ ## field ## _LSB)) & \
  59. (block ## _ ## field ## _MASK))
  60. #define HAL_TX_MS(block, field, value) \
  61. (((value) & (block ## _ ## field ## _MASK)) >> \
  62. (block ## _ ## field ## _LSB))
  63. #define HAL_TX_DESC_GET(desc, block, field) \
  64. HAL_TX_MS(block, field, HAL_SET_FLD(desc, block, field))
  65. #define HAL_TX_DESC_OFFSET_GET(desc, block, field, offset) \
  66. HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET(desc, block, field, offset))
  67. #define HAL_TX_DESC_SUBBLOCK_GET(desc, block, sub, field) \
  68. HAL_TX_MS(sub, field, HAL_SET_FLD(desc, block, sub))
  69. #define HAL_TX_DESC_GET_64(desc, block, field) \
  70. HAL_TX_MS(block, field, HAL_SET_FLD_64(desc, block, field))
  71. #define HAL_TX_DESC_OFFSET_GET_64(desc, block, field, offset) \
  72. HAL_TX_MS(block, field, HAL_SET_FLD_OFFSET_64(desc, block, field,\
  73. offset))
  74. #define HAL_TX_DESC_SUBBLOCK_GET_64(desc, block, sub, field) \
  75. HAL_TX_MS(sub, field, HAL_SET_FLD_64(desc, block, sub))
  76. #define HAL_TX_BUF_TYPE_BUFFER 0
  77. #define HAL_TX_BUF_TYPE_EXT_DESC 1
  78. #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
  79. #define HAL_TX_DESC_LEN_DWORDS (NUM_OF_DWORDS_TCL_DATA_CMD)
  80. #define HAL_TX_DESC_LEN_BYTES (NUM_OF_DWORDS_TCL_DATA_CMD * 4)
  81. #define HAL_TX_EXTENSION_DESC_LEN_DWORDS (NUM_OF_DWORDS_TX_MSDU_EXTENSION)
  82. #define HAL_TX_EXTENSION_DESC_LEN_BYTES (NUM_OF_DWORDS_TX_MSDU_EXTENSION * 4)
  83. #define NUM_OF_DWORDS_WBM_RELEASE_RING 8
  84. #define HAL_TX_COMPLETION_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
  85. #define HAL_TX_COMPLETION_DESC_LEN_BYTES (NUM_OF_DWORDS_WBM_RELEASE_RING*4)
  86. #define HAL_TX_BITS_PER_TID 3
  87. #define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1)
  88. #define HAL_TX_NUM_DSCP_PER_REGISTER 10
  89. #define HAL_MAX_HW_DSCP_TID_MAPS 2
  90. #define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32
  91. #define HAL_MAX_HW_DSCP_TID_V2_MAPS 48
  92. #define HAL_MAX_HW_DSCP_TID_V2_MAPS_5332 24
  93. #define HTT_META_HEADER_LEN_BYTES 64
  94. #define HAL_TX_EXT_DESC_WITH_META_DATA \
  95. (HTT_META_HEADER_LEN_BYTES + HAL_TX_EXTENSION_DESC_LEN_BYTES)
  96. #define HAL_TX_NUM_PCP_PER_REGISTER 8
  97. /* Length of WBM release ring without the status words */
  98. #define HAL_TX_COMPLETION_DESC_BASE_LEN 12
  99. #define HAL_TX_COMP_RELEASE_SOURCE_TQM 0
  100. #define HAL_TX_COMP_RELEASE_SOURCE_REO 2
  101. #define HAL_TX_COMP_RELEASE_SOURCE_FW 3
  102. /* Define a place-holder release reason for FW */
  103. #define HAL_TX_COMP_RELEASE_REASON_FW 99
  104. /*
  105. * Offset of HTT Tx Descriptor in WBM Completion
  106. * HTT Tx Desc structure is passed from firmware to host overlaid
  107. * on wbm_release_ring DWORDs 2,3 ,4 and 5for software based completions
  108. * (Exception frames and TQM bypass frames)
  109. */
  110. #define HAL_TX_COMP_HTT_STATUS_OFFSET 8
  111. #ifdef CONFIG_BERYLLIUM
  112. #define HAL_TX_COMP_HTT_STATUS_LEN 20
  113. #else
  114. #define HAL_TX_COMP_HTT_STATUS_LEN 16
  115. #endif
  116. #define HAL_TX_BUF_TYPE_BUFFER 0
  117. #define HAL_TX_BUF_TYPE_EXT_DESC 1
  118. #define HAL_TX_EXT_DESC_BUF_OFFSET TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET
  119. #define HAL_TX_EXT_BUF_LOW_MASK TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK
  120. #define HAL_TX_EXT_BUF_HI_MASK TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK
  121. #define HAL_TX_EXT_BUF_LEN_MASK TX_MSDU_EXTENSION_7_BUF0_LEN_MASK
  122. #define HAL_TX_EXT_BUF_LEN_LSB TX_MSDU_EXTENSION_7_BUF0_LEN_LSB
  123. #define HAL_TX_EXT_BUF_WD_SIZE 2
  124. #define HAL_TX_DESC_ADDRX_EN 0x1
  125. #define HAL_TX_DESC_ADDRY_EN 0x2
  126. #define HAL_TX_DESC_DEFAULT_LMAC_ID 0x3
  127. #define HAL_TX_ADDR_SEARCH_DEFAULT 0x0
  128. #define HAL_TX_ADDR_INDEX_SEARCH 0x1
  129. #define HAL_TX_FLOW_INDEX_SEARCH 0x2
  130. #define HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc)(((*(((uint32_t *)wbm_desc) + \
  131. (HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_OFFSET >> 2))) & \
  132. HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_MASK) >> \
  133. HAL_WBM2SW_RING_RELEASE_SOURCE_MODULE_LSB)
  134. #define HAL_WBM_SW0_BM_ID(sw0_bm_id) (sw0_bm_id)
  135. #define HAL_WBM_SW1_BM_ID(sw0_bm_id) ((sw0_bm_id) + 1)
  136. #define HAL_WBM_SW2_BM_ID(sw0_bm_id) ((sw0_bm_id) + 2)
  137. #define HAL_WBM_SW3_BM_ID(sw0_bm_id) ((sw0_bm_id) + 3)
  138. #define HAL_WBM_SW4_BM_ID(sw0_bm_id) ((sw0_bm_id) + 4)
  139. #define HAL_WBM_SW5_BM_ID(sw0_bm_id) ((sw0_bm_id) + 5)
  140. #define HAL_WBM_SW6_BM_ID(sw0_bm_id) ((sw0_bm_id) + 6)
  141. /*---------------------------------------------------------------------------
  142. Structures
  143. ---------------------------------------------------------------------------*/
  144. /**
  145. * struct hal_tx_completion_status - HAL Tx completion descriptor contents
  146. * @status: frame acked/failed
  147. * @release_src: release source = TQM/FW
  148. * @ack_frame_rssi: RSSI of the received ACK or BA frame
  149. * @first_msdu: Indicates this MSDU is the first MSDU in AMSDU
  150. * @last_msdu: Indicates this MSDU is the last MSDU in AMSDU
  151. * @msdu_part_of_amsdu : Indicates this MSDU was part of an A-MSDU in MPDU
  152. * @bw: Indicates the BW of the upcoming transmission -
  153. * <enum 0 transmit_bw_20_MHz>
  154. * <enum 1 transmit_bw_40_MHz>
  155. * <enum 2 transmit_bw_80_MHz>
  156. * <enum 3 transmit_bw_160_MHz>
  157. * @pkt_type: Transmit Packet Type
  158. * @stbc: When set, STBC transmission rate was used
  159. * @ldpc: When set, use LDPC transmission rates
  160. * @sgi: <enum 0 0_8_us_sgi > Legacy normal GI
  161. * <enum 1 0_4_us_sgi > Legacy short GI
  162. * <enum 2 1_6_us_sgi > HE related GI
  163. * <enum 3 3_2_us_sgi > HE
  164. * @mcs: Transmit MCS Rate
  165. * @ofdma: Set when the transmission was an OFDMA transmission
  166. * @tones_in_ru: The number of tones in the RU used.
  167. * @tsf: Lower 32 bits of the TSF
  168. * @ppdu_id: TSF, snapshot of this value when transmission of the
  169. * PPDU containing the frame finished.
  170. * @transmit_cnt: Number of times this frame has been transmitted
  171. * @tid: TID of the flow or MPDU queue
  172. * @peer_id: Peer ID of the flow or MPDU queue
  173. * @buffer_timestamp: Frame system entrance timestamp in units of 1024
  174. * microseconds
  175. */
  176. struct hal_tx_completion_status {
  177. uint8_t status;
  178. uint8_t release_src;
  179. uint8_t ack_frame_rssi;
  180. uint8_t first_msdu:1,
  181. last_msdu:1,
  182. msdu_part_of_amsdu:1;
  183. uint32_t bw:2,
  184. pkt_type:4,
  185. stbc:1,
  186. ldpc:1,
  187. sgi:2,
  188. mcs:4,
  189. ofdma:1,
  190. tones_in_ru:12,
  191. valid:1;
  192. uint32_t tsf;
  193. uint32_t ppdu_id;
  194. uint8_t transmit_cnt;
  195. uint8_t tid;
  196. uint16_t peer_id;
  197. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  198. uint32_t buffer_timestamp:19;
  199. #endif
  200. };
  201. /**
  202. * struct hal_tx_desc_comp_s - hal tx completion descriptor contents
  203. * @desc: Transmit status information from descriptor
  204. */
  205. struct hal_tx_desc_comp_s {
  206. uint32_t desc[HAL_TX_COMPLETION_DESC_LEN_DWORDS];
  207. };
  208. /*
  209. * enum hal_tx_encrypt_type - Type of decrypt cipher used (valid only for RAW)
  210. * @HAL_TX_ENCRYPT_TYPE_WEP_40: WEP 40-bit
  211. * @HAL_TX_ENCRYPT_TYPE_WEP_10: WEP 10-bit
  212. * @HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC: TKIP without MIC
  213. * @HAL_TX_ENCRYPT_TYPE_WEP_128: WEP_128
  214. * @HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC: TKIP_WITH_MIC
  215. * @HAL_TX_ENCRYPT_TYPE_WAPI: WAPI
  216. * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_128: AES_CCMP_128
  217. * @HAL_TX_ENCRYPT_TYPE_NO_CIPHER: NO CIPHER
  218. * @HAL_TX_ENCRYPT_TYPE_AES_CCMP_256: AES_CCMP_256
  219. * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_128: AES_GCMP_128
  220. * @HAL_TX_ENCRYPT_TYPE_AES_GCMP_256: AES_GCMP_256
  221. * @HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4: WAPI GCM SM4
  222. */
  223. enum hal_tx_encrypt_type {
  224. HAL_TX_ENCRYPT_TYPE_WEP_40 = 0,
  225. HAL_TX_ENCRYPT_TYPE_WEP_104 = 1 ,
  226. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC = 2,
  227. HAL_TX_ENCRYPT_TYPE_WEP_128 = 3,
  228. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC = 4,
  229. HAL_TX_ENCRYPT_TYPE_WAPI = 5,
  230. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128 = 6,
  231. HAL_TX_ENCRYPT_TYPE_NO_CIPHER = 7,
  232. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256 = 8,
  233. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128 = 9,
  234. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256 = 10,
  235. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4 = 11,
  236. };
  237. /*
  238. * enum hal_tx_encap_type - Encapsulation type that HW will perform
  239. * @HAL_TX_ENCAP_TYPE_RAW: Raw Packet Type
  240. * @HAL_TX_ENCAP_TYPE_NWIFI: Native WiFi Type
  241. * @HAL_TX_ENCAP_TYPE_ETHERNET: Ethernet
  242. * @HAL_TX_ENCAP_TYPE_802_3: 802.3 Frame
  243. */
  244. enum hal_tx_encap_type {
  245. HAL_TX_ENCAP_TYPE_RAW = 0,
  246. HAL_TX_ENCAP_TYPE_NWIFI = 1,
  247. HAL_TX_ENCAP_TYPE_ETHERNET = 2,
  248. HAL_TX_ENCAP_TYPE_802_3 = 3,
  249. };
  250. /**
  251. * enum hal_tx_tqm_release_reason - TQM Release reason codes
  252. *
  253. * @HAL_TX_TQM_RR_FRAME_ACKED : ACK of BA for it was received
  254. * @HAL_TX_TQM_RR_REM_CMD_REM : Remove cmd of type “Remove_mpdus” initiated
  255. * by SW
  256. * @HAL_TX_TQM_RR_REM_CMD_TX : Remove command of type Remove_transmitted_mpdus
  257. * initiated by SW
  258. * @HAL_TX_TQM_RR_REM_CMD_NOTX : Remove cmd of type Remove_untransmitted_mpdus
  259. * initiated by SW
  260. * @HAL_TX_TQM_RR_REM_CMD_AGED : Remove command of type “Remove_aged_mpdus” or
  261. * “Remove_aged_msdus” initiated by SW
  262. * @HAL_TX_TQM_RR_FW_REASON1 : Remove command where fw indicated that
  263. * remove reason is fw_reason1
  264. * @HAL_TX_TQM_RR_FW_REASON2 : Remove command where fw indicated that
  265. * remove reason is fw_reason2
  266. * @HAL_TX_TQM_RR_FW_REASON3 : Remove command where fw indicated that
  267. * remove reason is fw_reason3
  268. * @HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE : Remove command where fw indicated that
  269. * remove reason is remove disable queue
  270. * @HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING: Remove command from fw to remove
  271. * all mpdu until 1st non-match
  272. * @HAL_TX_TQM_RR_DROP_THRESHOLD: Dropped due to drop threshold criteria
  273. * @HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE: Dropped due to link desc not available
  274. * @HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU: Dropped due drop bit set or null flow
  275. * @HAL_TX_TQM_RR_MULTICAST_DROP: Dropped due mcast drop set for VDEV
  276. * @HAL_TX_TQM_RR_VDEV_MISMATCH_DROP: Dropped due to being set with
  277. * 'TCL_drop_reason'
  278. *
  279. */
  280. enum hal_tx_tqm_release_reason {
  281. HAL_TX_TQM_RR_FRAME_ACKED,
  282. HAL_TX_TQM_RR_REM_CMD_REM,
  283. HAL_TX_TQM_RR_REM_CMD_TX,
  284. HAL_TX_TQM_RR_REM_CMD_NOTX,
  285. HAL_TX_TQM_RR_REM_CMD_AGED,
  286. HAL_TX_TQM_RR_FW_REASON1,
  287. HAL_TX_TQM_RR_FW_REASON2,
  288. HAL_TX_TQM_RR_FW_REASON3,
  289. HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE,
  290. HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING,
  291. HAL_TX_TQM_RR_DROP_THRESHOLD,
  292. HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE,
  293. HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU,
  294. HAL_TX_TQM_RR_MULTICAST_DROP,
  295. HAL_TX_TQM_RR_VDEV_MISMATCH_DROP,
  296. };
  297. /* enum - Table IDs for 2 DSCP-TID mapping Tables that TCL H/W supports
  298. * @HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT: Default DSCP-TID mapping table
  299. * @HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE: DSCP-TID map override table
  300. */
  301. enum hal_tx_dscp_tid_table_id {
  302. HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT,
  303. HAL_TX_DSCP_TID_MAP_TABLE_OVERRIDE,
  304. };
  305. /*---------------------------------------------------------------------------
  306. Function declarations and documentation
  307. ---------------------------------------------------------------------------*/
  308. /*---------------------------------------------------------------------------
  309. Tx MSDU Extension Descriptor accessor APIs
  310. ---------------------------------------------------------------------------*/
  311. /**
  312. * hal_tx_ext_desc_set_tso_enable() - Set TSO Enable Flag
  313. * @desc: Handle to Tx MSDU Extension Descriptor
  314. * @tso_en: bool value set to true if TSO is enabled
  315. *
  316. * Return: none
  317. */
  318. static inline void hal_tx_ext_desc_set_tso_enable(void *desc,
  319. uint8_t tso_en)
  320. {
  321. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE) |=
  322. HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TSO_ENABLE, tso_en);
  323. }
  324. /**
  325. * hal_tx_ext_desc_set_tso_flags() - Set TSO Flags
  326. * @desc: Handle to Tx MSDU Extension Descriptor
  327. * @flags: 32-bit word with all TSO flags consolidated
  328. *
  329. * Return: none
  330. */
  331. static inline void hal_tx_ext_desc_set_tso_flags(void *desc,
  332. uint32_t tso_flags)
  333. {
  334. HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, TSO_ENABLE, 0) =
  335. tso_flags;
  336. }
  337. /**
  338. * hal_tx_ext_desc_set_tcp_flags() - Enable HW Checksum offload
  339. * @desc: Handle to Tx MSDU Extension Descriptor
  340. * @tcp_flags: TCP flags {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}
  341. * @mask: TCP flag mask. Tcp_flag is inserted into the header
  342. * based on the mask, if tso is enabled
  343. *
  344. * Return: none
  345. */
  346. static inline void hal_tx_ext_desc_set_tcp_flags(void *desc,
  347. uint16_t tcp_flags,
  348. uint16_t mask)
  349. {
  350. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_FLAG) |=
  351. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG, tcp_flags)) |
  352. (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_FLAG_MASK, mask)));
  353. }
  354. /**
  355. * hal_tx_ext_desc_set_msdu_length() - Set L2 and IP Lengths
  356. * @desc: Handle to Tx MSDU Extension Descriptor
  357. * @l2_len: L2 length for the msdu, if tso is enabled
  358. * @ip_len: IP length for the msdu, if tso is enabled
  359. *
  360. * Return: none
  361. */
  362. static inline void hal_tx_ext_desc_set_msdu_length(void *desc,
  363. uint16_t l2_len,
  364. uint16_t ip_len)
  365. {
  366. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, L2_LENGTH) |=
  367. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, L2_LENGTH, l2_len)) |
  368. (HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_LENGTH, ip_len)));
  369. }
  370. /**
  371. * hal_tx_ext_desc_set_tcp_seq() - Set TCP Sequence number
  372. * @desc: Handle to Tx MSDU Extension Descriptor
  373. * @seq_num: Tcp_seq_number for the msdu, if tso is enabled
  374. *
  375. * Return: none
  376. */
  377. static inline void hal_tx_ext_desc_set_tcp_seq(void *desc,
  378. uint32_t seq_num)
  379. {
  380. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER) |=
  381. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, TCP_SEQ_NUMBER, seq_num)));
  382. }
  383. /**
  384. * hal_tx_ext_desc_set_ip_id() - Set IP Identification field
  385. * @desc: Handle to Tx MSDU Extension Descriptor
  386. * @id: IP Id field for the msdu, if tso is enabled
  387. *
  388. * Return: none
  389. */
  390. static inline void hal_tx_ext_desc_set_ip_id(void *desc,
  391. uint16_t id)
  392. {
  393. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION) |=
  394. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, IP_IDENTIFICATION, id)));
  395. }
  396. /**
  397. * hal_tx_ext_desc_set_buffer() - Set Buffer Pointer and Length for a fragment
  398. * @desc: Handle to Tx MSDU Extension Descriptor
  399. * @frag_num: Fragment number (value can be 0 to 5)
  400. * @paddr_lo: Lower 32-bit of Buffer Physical address
  401. * @paddr_hi: Upper 32-bit of Buffer Physical address
  402. * @length: Buffer Length
  403. *
  404. * Return: none
  405. */
  406. static inline void hal_tx_ext_desc_set_buffer(void *desc,
  407. uint8_t frag_num,
  408. uint32_t paddr_lo,
  409. uint16_t paddr_hi,
  410. uint16_t length)
  411. {
  412. HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0,
  413. (frag_num << 3)) |=
  414. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo)));
  415. HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32,
  416. (frag_num << 3)) |=
  417. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32,
  418. (paddr_hi))));
  419. HAL_SET_FLD_OFFSET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN,
  420. (frag_num << 3)) |=
  421. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length)));
  422. }
  423. /**
  424. * hal_tx_ext_desc_get_frag_info() - Get the frag_num'th frag iova and len
  425. * @desc: Handle to Tx MSDU Extension Descriptor
  426. * @frag_num: fragment number (value can be 0 to 5)
  427. * @iova: fragment dma address
  428. * @len: fragment Length
  429. *
  430. * Return: None
  431. */
  432. static inline void hal_tx_ext_desc_get_frag_info(void *desc, uint8_t frag_num,
  433. qdf_dma_addr_t *iova,
  434. uint32_t *len)
  435. {
  436. uint64_t iova_hi;
  437. *iova = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION,
  438. BUF0_PTR_31_0, (frag_num << 3));
  439. iova_hi = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION,
  440. BUF0_PTR_39_32, (frag_num << 3));
  441. *iova |= (iova_hi << 32);
  442. *len = HAL_TX_DESC_OFFSET_GET(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN,
  443. (frag_num << 3));
  444. }
  445. /**
  446. * hal_tx_ext_desc_set_buffer0_param() - Set Buffer 0 Pointer and Length
  447. * @desc: Handle to Tx MSDU Extension Descriptor
  448. * @paddr_lo: Lower 32-bit of Buffer Physical address
  449. * @paddr_hi: Upper 32-bit of Buffer Physical address
  450. * @length: Buffer 0 Length
  451. *
  452. * Return: none
  453. */
  454. static inline void hal_tx_ext_desc_set_buffer0_param(void *desc,
  455. uint32_t paddr_lo,
  456. uint16_t paddr_hi,
  457. uint16_t length)
  458. {
  459. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0) |=
  460. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_PTR_31_0, paddr_lo)));
  461. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_PTR_39_32) |=
  462. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION,
  463. BUF0_PTR_39_32, paddr_hi)));
  464. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF0_LEN) |=
  465. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF0_LEN, length)));
  466. }
  467. /**
  468. * hal_tx_ext_desc_set_buffer1_param() - Set Buffer 1 Pointer and Length
  469. * @desc: Handle to Tx MSDU Extension Descriptor
  470. * @paddr_lo: Lower 32-bit of Buffer Physical address
  471. * @paddr_hi: Upper 32-bit of Buffer Physical address
  472. * @length: Buffer 1 Length
  473. *
  474. * Return: none
  475. */
  476. static inline void hal_tx_ext_desc_set_buffer1_param(void *desc,
  477. uint32_t paddr_lo,
  478. uint16_t paddr_hi,
  479. uint16_t length)
  480. {
  481. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0) |=
  482. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_PTR_31_0, paddr_lo)));
  483. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_PTR_39_32) |=
  484. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION,
  485. BUF1_PTR_39_32, paddr_hi)));
  486. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF1_LEN) |=
  487. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF1_LEN, length)));
  488. }
  489. /**
  490. * hal_tx_ext_desc_set_buffer2_param() - Set Buffer 2 Pointer and Length
  491. * @desc: Handle to Tx MSDU Extension Descriptor
  492. * @paddr_lo: Lower 32-bit of Buffer Physical address
  493. * @paddr_hi: Upper 32-bit of Buffer Physical address
  494. * @length: Buffer 2 Length
  495. *
  496. * Return: none
  497. */
  498. static inline void hal_tx_ext_desc_set_buffer2_param(void *desc,
  499. uint32_t paddr_lo,
  500. uint16_t paddr_hi,
  501. uint16_t length)
  502. {
  503. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0) |=
  504. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_31_0,
  505. paddr_lo)));
  506. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32) |=
  507. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_PTR_39_32,
  508. paddr_hi)));
  509. HAL_SET_FLD(desc, HAL_TX_MSDU_EXTENSION, BUF2_LEN) |=
  510. ((HAL_TX_SM(HAL_TX_MSDU_EXTENSION, BUF2_LEN, length)));
  511. }
  512. /**
  513. * hal_tx_ext_desc_sync - Commit the descriptor to Hardware
  514. * @desc_cached: Cached descriptor that software maintains
  515. * @hw_desc: Hardware descriptor to be updated
  516. *
  517. * Return: none
  518. */
  519. static inline void hal_tx_ext_desc_sync(uint8_t *desc_cached,
  520. uint8_t *hw_desc)
  521. {
  522. qdf_mem_copy(&hw_desc[0], &desc_cached[0],
  523. HAL_TX_EXT_DESC_WITH_META_DATA);
  524. }
  525. /**
  526. * hal_tx_ext_desc_get_tso_enable() - Set TSO Enable Flag
  527. * @hal_tx_ext_desc: Handle to Tx MSDU Extension Descriptor
  528. *
  529. * Return: tso_enable value in the descriptor
  530. */
  531. static inline uint32_t hal_tx_ext_desc_get_tso_enable(void *hal_tx_ext_desc)
  532. {
  533. uint32_t *desc = (uint32_t *) hal_tx_ext_desc;
  534. return (*desc & HAL_TX_MSDU_EXTENSION_TSO_ENABLE_MASK) >>
  535. HAL_TX_MSDU_EXTENSION_TSO_ENABLE_LSB;
  536. }
  537. /*---------------------------------------------------------------------------
  538. WBM Descriptor accessor APIs for Tx completions
  539. ---------------------------------------------------------------------------*/
  540. /**
  541. * hal_tx_comp_get_buffer_type() - Buffer or Descriptor type
  542. * @hal_desc: completion ring descriptor pointer
  543. *
  544. * This function will return the type of pointer - buffer or descriptor
  545. *
  546. * Return: buffer type
  547. */
  548. static inline uint32_t hal_tx_comp_get_buffer_type(void *hal_desc)
  549. {
  550. uint32_t comp_desc =
  551. *(uint32_t *) (((uint8_t *) hal_desc) +
  552. HAL_TX_COMP_BUFFER_OR_DESC_TYPE_OFFSET);
  553. return (comp_desc & HAL_TX_COMP_BUFFER_OR_DESC_TYPE_MASK) >>
  554. HAL_TX_COMP_BUFFER_OR_DESC_TYPE_LSB;
  555. }
  556. #ifdef QCA_WIFI_KIWI
  557. /**
  558. * hal_tx_comp_get_buffer_source() - Get buffer release source value
  559. * @hal_desc: completion ring descriptor pointer
  560. *
  561. * This function will get buffer release source from Tx completion descriptor
  562. *
  563. * Return: buffer release source
  564. */
  565. static inline uint32_t
  566. hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl,
  567. void *hal_desc)
  568. {
  569. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  570. return hal_soc->ops->hal_tx_comp_get_buffer_source(hal_desc);
  571. }
  572. #else
  573. static inline uint32_t
  574. hal_tx_comp_get_buffer_source(hal_soc_handle_t hal_soc_hdl,
  575. void *hal_desc)
  576. {
  577. return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc);
  578. }
  579. #endif
  580. /**
  581. * hal_tx_comp_get_release_reason() - TQM Release reason
  582. * @hal_desc: completion ring descriptor pointer
  583. *
  584. * This function will return the type of pointer - buffer or descriptor
  585. *
  586. * Return: buffer type
  587. */
  588. static inline
  589. uint8_t hal_tx_comp_get_release_reason(void *hal_desc,
  590. hal_soc_handle_t hal_soc_hdl)
  591. {
  592. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  593. return hal_soc->ops->hal_tx_comp_get_release_reason(hal_desc);
  594. }
  595. /**
  596. * hal_tx_comp_get_peer_id() - Get peer_id value()
  597. * @hal_desc: completion ring descriptor pointer
  598. *
  599. * This function will get peer_id value from Tx completion descriptor
  600. *
  601. * Return: buffer release source
  602. */
  603. static inline uint16_t hal_tx_comp_get_peer_id(void *hal_desc)
  604. {
  605. uint32_t comp_desc =
  606. *(uint32_t *)(((uint8_t *)hal_desc) +
  607. HAL_TX_COMP_SW_PEER_ID_OFFSET);
  608. return (comp_desc & HAL_TX_COMP_SW_PEER_ID_MASK) >>
  609. HAL_TX_COMP_SW_PEER_ID_LSB;
  610. }
  611. /**
  612. * hal_tx_comp_get_tx_status() - Get tx transmission status()
  613. * @hal_desc: completion ring descriptor pointer
  614. *
  615. * This function will get transmit status value from Tx completion descriptor
  616. *
  617. * Return: buffer release source
  618. */
  619. static inline uint8_t hal_tx_comp_get_tx_status(void *hal_desc)
  620. {
  621. uint32_t comp_desc =
  622. *(uint32_t *)(((uint8_t *)hal_desc) +
  623. HAL_TX_COMP_TQM_RELEASE_REASON_OFFSET);
  624. return (comp_desc & HAL_TX_COMP_TQM_RELEASE_REASON_MASK) >>
  625. HAL_TX_COMP_TQM_RELEASE_REASON_LSB;
  626. }
  627. /**
  628. * hal_tx_comp_desc_sync() - collect hardware descriptor contents
  629. * @hal_desc: hardware descriptor pointer
  630. * @comp: software descriptor pointer
  631. * @read_status: 0 - Do not read status words from descriptors
  632. * 1 - Enable reading of status words from descriptor
  633. *
  634. * This function will collect hardware release ring element contents and
  635. * translate to software descriptor content
  636. *
  637. * Return: none
  638. */
  639. static inline void hal_tx_comp_desc_sync(void *hw_desc,
  640. struct hal_tx_desc_comp_s *comp,
  641. bool read_status)
  642. {
  643. if (!read_status)
  644. qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_BASE_LEN);
  645. else
  646. qdf_mem_copy(comp, hw_desc, HAL_TX_COMPLETION_DESC_LEN_BYTES);
  647. }
  648. /**
  649. * hal_dump_comp_desc() - dump tx completion descriptor
  650. * @hal_desc: hardware descriptor pointer
  651. *
  652. * This function will print tx completion descriptor
  653. *
  654. * Return: none
  655. */
  656. static inline void hal_dump_comp_desc(void *hw_desc)
  657. {
  658. struct hal_tx_desc_comp_s *comp =
  659. (struct hal_tx_desc_comp_s *)hw_desc;
  660. uint32_t i;
  661. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  662. "Current tx completion descriptor is");
  663. for (i = 0; i < HAL_TX_COMPLETION_DESC_LEN_DWORDS; i++) {
  664. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  665. "DWORD[i] = 0x%x", comp->desc[i]);
  666. }
  667. }
  668. /**
  669. * hal_tx_comp_get_htt_desc() - Read the HTT portion of WBM Descriptor
  670. * @hal_desc: Hardware (WBM) descriptor pointer
  671. * @htt_desc: Software HTT descriptor pointer
  672. *
  673. * This function will read the HTT structure overlaid on WBM descriptor
  674. * into a cached software descriptor
  675. *
  676. */
  677. static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc)
  678. {
  679. uint8_t *desc = hw_desc + HAL_TX_COMP_HTT_STATUS_OFFSET;
  680. qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN);
  681. }
  682. /**
  683. * hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG
  684. * @hal_soc_hdl: Handle to HAL SoC structure
  685. * @hal_srng: Handle to HAL SRNG structure
  686. *
  687. * Return: none
  688. */
  689. static inline void hal_tx_init_data_ring(hal_soc_handle_t hal_soc_hdl,
  690. hal_ring_handle_t hal_ring_hdl)
  691. {
  692. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  693. hal_soc->ops->hal_tx_init_data_ring(hal_soc_hdl, hal_ring_hdl);
  694. }
  695. /**
  696. * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table
  697. *
  698. * @soc: HAL SoC context
  699. * @map: DSCP-TID mapping table
  700. * @id: mapping table ID - 0,1
  701. *
  702. * Return: void
  703. */
  704. static inline void hal_tx_set_dscp_tid_map(hal_soc_handle_t hal_soc_hdl,
  705. uint8_t *map, uint8_t id)
  706. {
  707. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  708. hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id);
  709. }
  710. /**
  711. * hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user
  712. *
  713. * @soc: HAL SoC context
  714. * @map: DSCP-TID mapping table
  715. * @id : MAP ID
  716. * @dscp: DSCP_TID map index
  717. *
  718. * Return: void
  719. */
  720. static inline
  721. void hal_tx_update_dscp_tid(hal_soc_handle_t hal_soc_hdl, uint8_t tid,
  722. uint8_t id, uint8_t dscp)
  723. {
  724. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  725. hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp);
  726. }
  727. /**
  728. * hal_tx_comp_get_status() - TQM Release reason
  729. * @hal_desc: completion ring Tx status
  730. *
  731. * This function will parse the WBM completion descriptor and populate in
  732. * HAL structure
  733. *
  734. * Return: none
  735. */
  736. static inline void hal_tx_comp_get_status(void *desc, void *ts,
  737. hal_soc_handle_t hal_soc_hdl)
  738. {
  739. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  740. hal_soc->ops->hal_tx_comp_get_status(desc, ts, hal_soc);
  741. }
  742. /**
  743. * hal_tx_set_pcp_tid_map_default() - Configure default PCP to TID map table
  744. *
  745. * @soc: HAL SoC context
  746. * @map: PCP-TID mapping table
  747. *
  748. * Return: void
  749. */
  750. static inline void hal_tx_set_pcp_tid_map_default(hal_soc_handle_t hal_soc_hdl,
  751. uint8_t *map)
  752. {
  753. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  754. hal_soc->ops->hal_tx_set_pcp_tid_map(hal_soc, map);
  755. }
  756. /**
  757. * hal_tx_update_pcp_tid_map() - Update PCP to TID map table
  758. *
  759. * @soc: HAL SoC context
  760. * @pcp: pcp value
  761. * @tid: tid no
  762. *
  763. * Return: void
  764. */
  765. static inline void hal_tx_update_pcp_tid_map(hal_soc_handle_t hal_soc_hdl,
  766. uint8_t pcp, uint8_t tid)
  767. {
  768. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  769. hal_soc->ops->hal_tx_update_pcp_tid_map(hal_soc, pcp, tid);
  770. }
  771. /**
  772. * hal_tx_set_tidmap_prty() - Configure TIDmap priority
  773. *
  774. * @soc: HAL SoC context
  775. * @val: priority value
  776. *
  777. * Return: void
  778. */
  779. static inline
  780. void hal_tx_set_tidmap_prty(hal_soc_handle_t hal_soc_hdl, uint8_t val)
  781. {
  782. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  783. hal_soc->ops->hal_tx_set_tidmap_prty(hal_soc, val);
  784. }
  785. /**
  786. * hal_get_wbm_internal_error() - wbm internal error
  787. * @hal_desc: completion ring descriptor pointer
  788. *
  789. * This function will return the type of pointer - buffer or descriptor
  790. *
  791. * Return: buffer type
  792. */
  793. static inline
  794. uint8_t hal_get_wbm_internal_error(hal_soc_handle_t hal_soc_hdl, void *hal_desc)
  795. {
  796. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  797. return hal_soc->ops->hal_get_wbm_internal_error(hal_desc);
  798. }
  799. #endif /* HAL_TX_H */