hal_be_tx.h 12 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_BE_TX_H_
  19. #define _HAL_BE_TX_H_
  20. #include "hal_be_hw_headers.h"
  21. #include "hal_tx.h"
  22. enum hal_be_tx_ret_buf_manager {
  23. HAL_BE_WBM_SW0_BM_ID = 5,
  24. HAL_BE_WBM_SW1_BM_ID = 6,
  25. HAL_BE_WBM_SW2_BM_ID = 7,
  26. HAL_BE_WBM_SW3_BM_ID = 8,
  27. HAL_BE_WBM_SW4_BM_ID = 9,
  28. HAL_BE_WBM_SW5_BM_ID = 10,
  29. HAL_BE_WBM_SW6_BM_ID = 11,
  30. };
  31. /*---------------------------------------------------------------------------
  32. * Structures
  33. * ---------------------------------------------------------------------------
  34. */
  35. /**
  36. * struct hal_tx_bank_config - SW config bank params
  37. * @epd: EPD indication flag
  38. * @encap_type: encapsulation type
  39. * @encrypt_type: encrypt type
  40. * @src_buffer_swap: big-endia switch for packet buffer
  41. * @link_meta_swap: big-endian switch for link metadata
  42. * @index_lookup_enable: Enabel index lookup
  43. * @addrx_en: Address-X search
  44. * @addry_en: Address-Y search
  45. * @mesh_enable:mesh enable flag
  46. * @vdev_id_check_en: vdev id check
  47. * @pmac_id: mac id
  48. * @mcast_pkt_ctrl: mulitcast packet control
  49. * @val: value representing bank config
  50. */
  51. union hal_tx_bank_config {
  52. struct {
  53. uint32_t epd:1,
  54. encap_type:2,
  55. encrypt_type:4,
  56. src_buffer_swap:1,
  57. link_meta_swap:1,
  58. index_lookup_enable:1,
  59. addrx_en:1,
  60. addry_en:1,
  61. mesh_enable:2,
  62. vdev_id_check_en:1,
  63. pmac_id:2,
  64. mcast_pkt_ctrl:2,
  65. reserved:13;
  66. };
  67. uint32_t val;
  68. };
  69. /*---------------------------------------------------------------------------
  70. * Function declarations and documentation
  71. * ---------------------------------------------------------------------------
  72. */
  73. /*---------------------------------------------------------------------------
  74. * TCL Descriptor accessor APIs
  75. *---------------------------------------------------------------------------
  76. */
  77. /**
  78. * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
  79. * @desc: Handle to Tx Descriptor
  80. * @data_length: MSDU length in case of direct descriptor.
  81. * Length of link extension descriptor in case of Link extension
  82. * descriptor.Includes the length of Metadata
  83. * Return: None
  84. */
  85. static inline void hal_tx_desc_set_buf_length(void *desc,
  86. uint16_t data_length)
  87. {
  88. HAL_SET_FLD(desc, TCL_DATA_CMD, DATA_LENGTH) |=
  89. HAL_TX_SM(TCL_DATA_CMD, DATA_LENGTH, data_length);
  90. }
  91. /**
  92. * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor
  93. * @desc: Handle to Tx Descriptor
  94. * @offset: Packet offset from Metadata in case of direct buffer descriptor.
  95. *
  96. * Return: void
  97. */
  98. static inline void hal_tx_desc_set_buf_offset(void *desc,
  99. uint8_t offset)
  100. {
  101. HAL_SET_FLD(desc, TCL_DATA_CMD, PACKET_OFFSET) |=
  102. HAL_TX_SM(TCL_DATA_CMD, PACKET_OFFSET, offset);
  103. }
  104. /**
  105. * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags
  106. * Tx Descriptor for MSDU_buffer type
  107. * @desc: Handle to Tx Descriptor
  108. * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
  109. *
  110. * Return: void
  111. */
  112. static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
  113. uint8_t en)
  114. {
  115. HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
  116. (HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV4_CHECKSUM_EN, en) |
  117. HAL_TX_SM(TCL_DATA_CMD, UDP_OVER_IPV6_CHECKSUM_EN, en) |
  118. HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV4_CHECKSUM_EN, en) |
  119. HAL_TX_SM(TCL_DATA_CMD, TCP_OVER_IPV6_CHECKSUM_EN, en));
  120. }
  121. /**
  122. * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in
  123. * Tx Descriptor for MSDU_buffer type
  124. * @desc: Handle to Tx Descriptor
  125. * @checksum_en_flags: ipv4 checksum enable flags
  126. *
  127. * Return: void
  128. */
  129. static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
  130. uint8_t en)
  131. {
  132. HAL_SET_FLD(desc, TCL_DATA_CMD, IPV4_CHECKSUM_EN) |=
  133. HAL_TX_SM(TCL_DATA_CMD, IPV4_CHECKSUM_EN, en);
  134. }
  135. /**
  136. * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor
  137. * @desc:Handle to Tx Descriptor
  138. * @metadata: Metadata to be sent to Firmware
  139. *
  140. * Return: void
  141. */
  142. static inline void hal_tx_desc_set_fw_metadata(void *desc,
  143. uint16_t metadata)
  144. {
  145. HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_NUMBER) |=
  146. HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_NUMBER, metadata);
  147. }
  148. /**
  149. * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor.
  150. * @desc:Handle to Tx Descriptor
  151. * @to_fw: if set, Forward packet to FW along with classification result
  152. *
  153. * Return: void
  154. */
  155. static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
  156. {
  157. HAL_SET_FLD(desc, TCL_DATA_CMD, TO_FW) |=
  158. HAL_TX_SM(TCL_DATA_CMD, TO_FW, to_fw);
  159. }
  160. /**
  161. * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in
  162. * frame) to be used for Tx Frame
  163. * @desc: Handle to Tx Descriptor
  164. * @hlos_tid: HLOS TID
  165. *
  166. * Return: void
  167. */
  168. static inline void hal_tx_desc_set_hlos_tid(void *desc,
  169. uint8_t hlos_tid)
  170. {
  171. HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID) |=
  172. HAL_TX_SM(TCL_DATA_CMD, HLOS_TID, hlos_tid);
  173. HAL_SET_FLD(desc, TCL_DATA_CMD, HLOS_TID_OVERWRITE) |=
  174. HAL_TX_SM(TCL_DATA_CMD, HLOS_TID_OVERWRITE, 1);
  175. }
  176. /**
  177. * hal_tx_desc_sync - Commit the descriptor to Hardware
  178. * @hal_tx_des_cached: Cached descriptor that software maintains
  179. * @hw_desc: Hardware descriptor to be updated
  180. */
  181. static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
  182. void *hw_desc)
  183. {
  184. qdf_mem_copy(hw_desc, hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
  185. }
  186. static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id)
  187. {
  188. HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |=
  189. HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id);
  190. }
  191. static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id)
  192. {
  193. HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |=
  194. HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id);
  195. }
  196. static inline void
  197. hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type)
  198. {
  199. HAL_SET_FLD(desc, TCL_DATA_CMD, TCL_CMD_TYPE) |=
  200. HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type);
  201. }
  202. /*---------------------------------------------------------------------------
  203. * WBM Descriptor accessor APIs for Tx completions
  204. * ---------------------------------------------------------------------------
  205. */
  206. /**
  207. * hal_tx_get_wbm_sw0_bm_id() - Get the BM ID for first tx completion ring
  208. *
  209. * Return: BM ID for first tx completion ring
  210. */
  211. static inline uint32_t hal_tx_get_wbm_sw0_bm_id(void)
  212. {
  213. return HAL_BE_WBM_SW0_BM_ID;
  214. }
  215. /**
  216. * hal_tx_comp_get_desc_id() - Get TX descriptor id within comp descriptor
  217. * @hal_desc: completion ring descriptor pointer
  218. *
  219. * This function will tx descriptor id, cookie, within hardware completion
  220. * descriptor. For cases when cookie conversion is disabled, the sw_cookie
  221. * is present in the 2nd DWORD.
  222. *
  223. * Return: cookie
  224. */
  225. static inline uint32_t hal_tx_comp_get_desc_id(void *hal_desc)
  226. {
  227. uint32_t comp_desc =
  228. *(uint32_t *)(((uint8_t *)hal_desc) +
  229. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET);
  230. /* Cookie is placed on 2nd word */
  231. return (comp_desc & BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK) >>
  232. BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB;
  233. }
  234. /**
  235. * hal_tx_comp_get_paddr() - Get paddr within comp descriptor
  236. * @hal_desc: completion ring descriptor pointer
  237. *
  238. * This function will get buffer physical address within hardware completion
  239. * descriptor
  240. *
  241. * Return: Buffer physical address
  242. */
  243. static inline qdf_dma_addr_t hal_tx_comp_get_paddr(void *hal_desc)
  244. {
  245. uint32_t paddr_lo;
  246. uint32_t paddr_hi;
  247. paddr_lo = *(uint32_t *)(((uint8_t *)hal_desc) +
  248. BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET);
  249. paddr_hi = *(uint32_t *)(((uint8_t *)hal_desc) +
  250. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET);
  251. paddr_hi = (paddr_hi & BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK) >>
  252. BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB;
  253. return (qdf_dma_addr_t)(paddr_lo | (((uint64_t)paddr_hi) << 32));
  254. }
  255. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  256. /* HW set dowrd-2 bit30 to 1 if HW CC is done */
  257. #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_OFFSET 0x8
  258. #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_MASK 0x40000000
  259. #define HAL_WBM2SW_COMPLETION_RING_TX_CC_DONE_LSB 0x1E
  260. /**
  261. * hal_tx_comp_get_cookie_convert_done() - Get cookie conversion done flag
  262. * @hal_desc: completion ring descriptor pointer
  263. *
  264. * This function will get the bit value that indicate HW cookie
  265. * conversion done or not
  266. *
  267. * Return: 1 - HW cookie conversion done, 0 - not
  268. */
  269. static inline uint8_t hal_tx_comp_get_cookie_convert_done(void *hal_desc)
  270. {
  271. return HAL_TX_DESC_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_TX,
  272. CC_DONE);
  273. }
  274. #endif
  275. /**
  276. * hal_tx_comp_get_desc_va() - Get Desc virtual address within completion Desc
  277. * @hal_desc: completion ring descriptor pointer
  278. *
  279. * This function will get the TX Desc virtual address
  280. *
  281. * Return: TX desc virtual address
  282. */
  283. static inline uintptr_t hal_tx_comp_get_desc_va(void *hal_desc)
  284. {
  285. uint64_t va_from_desc;
  286. va_from_desc = HAL_TX_DESC_GET(hal_desc,
  287. WBM2SW_COMPLETION_RING_TX,
  288. BUFFER_VIRT_ADDR_31_0) |
  289. (((uint64_t)HAL_TX_DESC_GET(
  290. hal_desc,
  291. WBM2SW_COMPLETION_RING_TX,
  292. BUFFER_VIRT_ADDR_63_32)) << 32);
  293. return (uintptr_t)va_from_desc;
  294. }
  295. /*---------------------------------------------------------------------------
  296. * TX BANK register accessor APIs
  297. * ---------------------------------------------------------------------------
  298. */
  299. /**
  300. * hal_tx_get_num_tcl_banks() - Get number of banks for target
  301. *
  302. * Return: None
  303. */
  304. static inline uint8_t
  305. hal_tx_get_num_tcl_banks(hal_soc_handle_t hal_soc_hdl)
  306. {
  307. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  308. if (hal_soc->ops->hal_tx_get_num_tcl_banks)
  309. return hal_soc->ops->hal_tx_get_num_tcl_banks();
  310. return 0;
  311. }
  312. /**
  313. * hal_tx_populate_bank_register() - populate the bank register with
  314. * the software configs.
  315. * @soc: HAL soc handle
  316. * @config: bank config
  317. * @bank_id: bank id to be configured
  318. *
  319. * Returns: None
  320. */
  321. static inline void
  322. hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
  323. union hal_tx_bank_config *config,
  324. uint8_t bank_id)
  325. {
  326. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  327. uint32_t reg_addr, reg_val = 0;
  328. reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE,
  329. bank_id);
  330. reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT);
  331. reg_val |= (config->encap_type <<
  332. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT);
  333. reg_val |= (config->encrypt_type <<
  334. HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT);
  335. reg_val |= (config->src_buffer_swap <<
  336. HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT);
  337. reg_val |= (config->link_meta_swap <<
  338. HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT);
  339. reg_val |= (config->index_lookup_enable <<
  340. HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT);
  341. reg_val |= (config->addrx_en <<
  342. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT);
  343. reg_val |= (config->addry_en <<
  344. HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT);
  345. reg_val |= (config->mesh_enable <<
  346. HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT);
  347. reg_val |= (config->vdev_id_check_en <<
  348. HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT);
  349. reg_val |= (config->pmac_id <<
  350. HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT);
  351. reg_val |= (config->mcast_pkt_ctrl <<
  352. HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT);
  353. HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
  354. }
  355. #endif /* _HAL_BE_TX_H_ */