sde_hw_dspp.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <drm/msm_drm_pp.h>
  6. #include "sde_hw_mdss.h"
  7. #include "sde_hwio.h"
  8. #include "sde_hw_catalog.h"
  9. #include "sde_hw_dspp.h"
  10. #include "sde_hw_color_processing.h"
  11. #include "sde_dbg.h"
  12. #include "sde_ad4.h"
  13. #include "sde_hw_rc.h"
  14. #include "sde_kms.h"
  15. #define DSPP_VALID_START_OFF 0x800
  16. static struct sde_dspp_cfg *_dspp_offset(enum sde_dspp dspp,
  17. struct sde_mdss_cfg *m,
  18. void __iomem *addr,
  19. struct sde_hw_blk_reg_map *b)
  20. {
  21. int i;
  22. if (!m || !addr || !b)
  23. return ERR_PTR(-EINVAL);
  24. for (i = 0; i < m->dspp_count; i++) {
  25. if (dspp == m->dspp[i].id) {
  26. b->base_off = addr;
  27. b->blk_off = m->dspp[i].base;
  28. b->length = m->dspp[i].len;
  29. b->hwversion = m->hwversion;
  30. b->log_mask = SDE_DBG_MASK_DSPP;
  31. return &m->dspp[i];
  32. }
  33. }
  34. return ERR_PTR(-EINVAL);
  35. }
  36. static void dspp_igc(struct sde_hw_dspp *c)
  37. {
  38. int ret = 0;
  39. if (c->cap->sblk->igc.version == SDE_COLOR_PROCESS_VER(0x3, 0x1)) {
  40. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_IGC, c->idx);
  41. if (!ret)
  42. c->ops.setup_igc = reg_dmav1_setup_dspp_igcv31;
  43. else
  44. c->ops.setup_igc = sde_setup_dspp_igcv3;
  45. } else if (c->cap->sblk->igc.version ==
  46. SDE_COLOR_PROCESS_VER(0x4, 0x0)) {
  47. c->ops.setup_igc = NULL;
  48. ret = reg_dmav2_init_dspp_op_v4(SDE_DSPP_IGC, c->idx);
  49. if (!ret)
  50. c->ops.setup_igc = reg_dmav2_setup_dspp_igcv4;
  51. }
  52. }
  53. static void dspp_pcc(struct sde_hw_dspp *c)
  54. {
  55. int ret = 0;
  56. if (c->cap->sblk->pcc.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7)))
  57. c->ops.setup_pcc = sde_setup_dspp_pcc_v1_7;
  58. else if (c->cap->sblk->pcc.version ==
  59. (SDE_COLOR_PROCESS_VER(0x4, 0x0))) {
  60. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_PCC, c->idx);
  61. if (!ret)
  62. c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv4;
  63. else
  64. c->ops.setup_pcc = sde_setup_dspp_pccv4;
  65. } else if (c->cap->sblk->pcc.version ==
  66. (SDE_COLOR_PROCESS_VER(0x5, 0x0))) {
  67. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_PCC, c->idx);
  68. if (!ret)
  69. c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv5;
  70. else
  71. c->ops.setup_pcc = NULL;
  72. }
  73. }
  74. static void dspp_gc(struct sde_hw_dspp *c)
  75. {
  76. int ret = 0;
  77. if (c->cap->sblk->gc.version == SDE_COLOR_PROCESS_VER(0x1, 8)) {
  78. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GC, c->idx);
  79. if (!ret)
  80. c->ops.setup_gc = reg_dmav1_setup_dspp_gcv18;
  81. /**
  82. * programming for v18 through ahb is same as v17,
  83. * hence assign v17 function
  84. */
  85. else
  86. c->ops.setup_gc = sde_setup_dspp_gc_v1_7;
  87. }
  88. }
  89. static void dspp_hsic(struct sde_hw_dspp *c)
  90. {
  91. int ret = 0;
  92. if (c->cap->sblk->hsic.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
  93. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_HSIC, c->idx);
  94. if (!ret)
  95. c->ops.setup_pa_hsic = reg_dmav1_setup_dspp_pa_hsicv17;
  96. else
  97. c->ops.setup_pa_hsic = sde_setup_dspp_pa_hsic_v17;
  98. }
  99. }
  100. static void dspp_memcolor(struct sde_hw_dspp *c)
  101. {
  102. int ret = 0;
  103. if (c->cap->sblk->memcolor.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
  104. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_MEMCOLOR, c->idx);
  105. if (!ret) {
  106. c->ops.setup_pa_memcol_skin =
  107. reg_dmav1_setup_dspp_memcol_skinv17;
  108. c->ops.setup_pa_memcol_sky =
  109. reg_dmav1_setup_dspp_memcol_skyv17;
  110. c->ops.setup_pa_memcol_foliage =
  111. reg_dmav1_setup_dspp_memcol_folv17;
  112. c->ops.setup_pa_memcol_prot =
  113. reg_dmav1_setup_dspp_memcol_protv17;
  114. } else {
  115. c->ops.setup_pa_memcol_skin =
  116. sde_setup_dspp_memcol_skin_v17;
  117. c->ops.setup_pa_memcol_sky =
  118. sde_setup_dspp_memcol_sky_v17;
  119. c->ops.setup_pa_memcol_foliage =
  120. sde_setup_dspp_memcol_foliage_v17;
  121. c->ops.setup_pa_memcol_prot =
  122. sde_setup_dspp_memcol_prot_v17;
  123. }
  124. }
  125. }
  126. static void dspp_sixzone(struct sde_hw_dspp *c)
  127. {
  128. int ret = 0;
  129. if (c->cap->sblk->sixzone.version == SDE_COLOR_PROCESS_VER(0x1, 0x7)) {
  130. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_SIXZONE, c->idx);
  131. if (!ret)
  132. c->ops.setup_sixzone = reg_dmav1_setup_dspp_sixzonev17;
  133. else
  134. c->ops.setup_sixzone = sde_setup_dspp_sixzone_v17;
  135. }
  136. }
  137. static void dspp_gamut(struct sde_hw_dspp *c)
  138. {
  139. int ret = 0;
  140. if (c->cap->sblk->gamut.version == SDE_COLOR_PROCESS_VER(0x4, 0)) {
  141. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  142. if (!ret)
  143. c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv4;
  144. else
  145. c->ops.setup_gamut = sde_setup_dspp_3d_gamutv4;
  146. } else if (c->cap->sblk->gamut.version ==
  147. SDE_COLOR_PROCESS_VER(0x4, 1)) {
  148. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  149. if (!ret)
  150. c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv41;
  151. else
  152. c->ops.setup_gamut = sde_setup_dspp_3d_gamutv41;
  153. } else if (c->cap->sblk->gamut.version ==
  154. SDE_COLOR_PROCESS_VER(0x4, 2)) {
  155. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  156. c->ops.setup_gamut = NULL;
  157. if (!ret)
  158. c->ops.setup_gamut = reg_dmav1_setup_dspp_3d_gamutv42;
  159. } else if (c->cap->sblk->gamut.version ==
  160. SDE_COLOR_PROCESS_VER(0x4, 3)) {
  161. c->ops.setup_gamut = NULL;
  162. ret = reg_dmav2_init_dspp_op_v4(SDE_DSPP_GAMUT, c->idx);
  163. if (!ret)
  164. c->ops.setup_gamut = reg_dmav2_setup_dspp_3d_gamutv43;
  165. }
  166. }
  167. static void dspp_dither(struct sde_hw_dspp *c)
  168. {
  169. if (c->cap->sblk->dither.version == SDE_COLOR_PROCESS_VER(0x1, 0x7))
  170. c->ops.setup_pa_dither = sde_setup_dspp_dither_v1_7;
  171. }
  172. static void dspp_hist(struct sde_hw_dspp *c)
  173. {
  174. if (c->cap->sblk->hist.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
  175. c->ops.setup_histogram = sde_setup_dspp_hist_v1_7;
  176. c->ops.read_histogram = sde_read_dspp_hist_v1_7;
  177. c->ops.lock_histogram = sde_lock_dspp_hist_v1_7;
  178. }
  179. }
  180. static void dspp_vlut(struct sde_hw_dspp *c)
  181. {
  182. int ret = 0;
  183. if (c->cap->sblk->vlut.version == (SDE_COLOR_PROCESS_VER(0x1, 0x7))) {
  184. c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_7;
  185. } else if (c->cap->sblk->vlut.version ==
  186. (SDE_COLOR_PROCESS_VER(0x1, 0x8))) {
  187. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_VLUT, c->idx);
  188. if (!ret)
  189. c->ops.setup_vlut = reg_dmav1_setup_dspp_vlutv18;
  190. else
  191. c->ops.setup_vlut = sde_setup_dspp_pa_vlut_v1_8;
  192. }
  193. }
  194. static void dspp_ad(struct sde_hw_dspp *c)
  195. {
  196. if (c->cap->sblk->ad.version == SDE_COLOR_PROCESS_VER(4, 0)) {
  197. c->ops.setup_ad = sde_setup_dspp_ad4;
  198. c->ops.ad_read_intr_resp = sde_read_intr_resp_ad4;
  199. c->ops.validate_ad = sde_validate_dspp_ad4;
  200. }
  201. }
  202. static void dspp_ltm(struct sde_hw_dspp *c)
  203. {
  204. int ret = 0;
  205. if (c->cap->sblk->ltm.version == SDE_COLOR_PROCESS_VER(0x1, 0x0) ||
  206. c->cap->sblk->ltm.version == SDE_COLOR_PROCESS_VER(0x1, 0x1)) {
  207. ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_INIT, c->idx);
  208. if (!ret)
  209. ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_ROI, c->idx);
  210. if (!ret)
  211. ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_VLUT, c->idx);
  212. if (!ret) {
  213. c->ops.setup_ltm_init = reg_dmav1_setup_ltm_initv1;
  214. c->ops.setup_ltm_roi = reg_dmav1_setup_ltm_roiv1;
  215. c->ops.setup_ltm_vlut = reg_dmav1_setup_ltm_vlutv1;
  216. c->ops.setup_ltm_thresh = sde_setup_dspp_ltm_threshv1;
  217. c->ops.setup_ltm_hist_ctrl =
  218. sde_setup_dspp_ltm_hist_ctrlv1;
  219. c->ops.setup_ltm_hist_buffer =
  220. sde_setup_dspp_ltm_hist_bufferv1;
  221. c->ops.ltm_read_intr_status = sde_ltm_read_intr_status;
  222. } else {
  223. c->ops.setup_ltm_init = NULL;
  224. c->ops.setup_ltm_roi = NULL;
  225. c->ops.setup_ltm_vlut = NULL;
  226. c->ops.setup_ltm_thresh = NULL;
  227. c->ops.setup_ltm_hist_ctrl = NULL;
  228. c->ops.setup_ltm_hist_buffer = NULL;
  229. c->ops.ltm_read_intr_status = NULL;
  230. }
  231. if (!ret && c->cap->sblk->ltm.version ==
  232. SDE_COLOR_PROCESS_VER(0x1, 0x1))
  233. c->ltm_checksum_support = true;
  234. else
  235. c->ltm_checksum_support = false;
  236. }
  237. }
  238. static void dspp_rc(struct sde_hw_dspp *c)
  239. {
  240. int ret = 0;
  241. if (!c) {
  242. SDE_ERROR("invalid arguments\n");
  243. return;
  244. }
  245. if (c->cap->sblk->rc.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
  246. ret = sde_hw_rc_init(c);
  247. if (ret) {
  248. SDE_ERROR("rc init failed, ret %d\n", ret);
  249. return;
  250. }
  251. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_RC, c->idx);
  252. if (!ret)
  253. c->ops.setup_rc_data =
  254. sde_hw_rc_setup_data_dma;
  255. else
  256. c->ops.setup_rc_data =
  257. sde_hw_rc_setup_data_ahb;
  258. c->ops.validate_rc_mask = sde_hw_rc_check_mask;
  259. c->ops.setup_rc_mask = sde_hw_rc_setup_mask;
  260. c->ops.validate_rc_pu_roi = sde_hw_rc_check_pu_roi;
  261. c->ops.setup_rc_pu_roi = sde_hw_rc_setup_pu_roi;
  262. }
  263. }
  264. static void dspp_spr(struct sde_hw_dspp *c)
  265. {
  266. int ret = 0;
  267. if (!c) {
  268. SDE_ERROR("invalid arguments\n");
  269. return;
  270. }
  271. c->ops.setup_spr_init_config = NULL;
  272. c->ops.setup_spr_pu_config = NULL;
  273. if (c->cap->sblk->spr.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
  274. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_SPR, c->idx);
  275. if (ret) {
  276. SDE_ERROR("regdma init failed for spr, ret %d\n", ret);
  277. return;
  278. }
  279. c->ops.setup_spr_init_config = reg_dmav1_setup_spr_init_cfgv1;
  280. c->ops.setup_spr_pu_config = reg_dmav1_setup_spr_pu_cfgv1;
  281. }
  282. }
  283. static void dspp_demura(struct sde_hw_dspp *c)
  284. {
  285. int ret;
  286. if (c->cap->sblk->demura.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
  287. ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_DEMURA, c->idx);
  288. c->ops.setup_demura_cfg = NULL;
  289. c->ops.setup_demura_backlight_cfg = NULL;
  290. if (!ret) {
  291. c->ops.setup_demura_cfg = reg_dmav1_setup_demurav1;
  292. c->ops.setup_demura_backlight_cfg =
  293. sde_demura_backlight_cfg;
  294. c->ops.demura_read_plane_status =
  295. sde_demura_read_plane_status;
  296. c->ops.setup_demura_pu_config = sde_demura_pu_cfg;
  297. }
  298. }
  299. }
  300. static void (*dspp_blocks[SDE_DSPP_MAX])(struct sde_hw_dspp *c);
  301. static void _init_dspp_ops(void)
  302. {
  303. dspp_blocks[SDE_DSPP_IGC] = dspp_igc;
  304. dspp_blocks[SDE_DSPP_PCC] = dspp_pcc;
  305. dspp_blocks[SDE_DSPP_GC] = dspp_gc;
  306. dspp_blocks[SDE_DSPP_HSIC] = dspp_hsic;
  307. dspp_blocks[SDE_DSPP_MEMCOLOR] = dspp_memcolor;
  308. dspp_blocks[SDE_DSPP_SIXZONE] = dspp_sixzone;
  309. dspp_blocks[SDE_DSPP_GAMUT] = dspp_gamut;
  310. dspp_blocks[SDE_DSPP_DITHER] = dspp_dither;
  311. dspp_blocks[SDE_DSPP_HIST] = dspp_hist;
  312. dspp_blocks[SDE_DSPP_VLUT] = dspp_vlut;
  313. dspp_blocks[SDE_DSPP_AD] = dspp_ad;
  314. dspp_blocks[SDE_DSPP_LTM] = dspp_ltm;
  315. dspp_blocks[SDE_DSPP_RC] = dspp_rc;
  316. dspp_blocks[SDE_DSPP_SPR] = dspp_spr;
  317. dspp_blocks[SDE_DSPP_DEMURA] = dspp_demura;
  318. }
  319. static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features)
  320. {
  321. int i = 0;
  322. if (!c->cap->sblk)
  323. return;
  324. for (i = 0; i < SDE_DSPP_MAX; i++) {
  325. if (!test_bit(i, &features))
  326. continue;
  327. if (dspp_blocks[i])
  328. dspp_blocks[i](c);
  329. }
  330. }
  331. static struct sde_hw_blk_ops sde_hw_ops = {
  332. .start = NULL,
  333. .stop = NULL,
  334. };
  335. struct sde_hw_dspp *sde_hw_dspp_init(enum sde_dspp idx,
  336. void __iomem *addr,
  337. struct sde_mdss_cfg *m)
  338. {
  339. struct sde_hw_dspp *c;
  340. struct sde_dspp_cfg *cfg;
  341. int rc;
  342. char buf[256];
  343. if (!addr || !m)
  344. return ERR_PTR(-EINVAL);
  345. c = kzalloc(sizeof(*c), GFP_KERNEL);
  346. if (!c)
  347. return ERR_PTR(-ENOMEM);
  348. cfg = _dspp_offset(idx, m, addr, &c->hw);
  349. if (IS_ERR_OR_NULL(cfg)) {
  350. kfree(c);
  351. return ERR_PTR(-EINVAL);
  352. }
  353. /* Populate DSPP Top HW block */
  354. c->hw_top.base_off = addr;
  355. c->hw_top.blk_off = m->dspp_top.base;
  356. c->hw_top.length = m->dspp_top.len;
  357. c->hw_top.hwversion = m->hwversion;
  358. c->hw_top.log_mask = SDE_DBG_MASK_DSPP;
  359. /* Assign ops */
  360. c->idx = idx;
  361. c->cap = cfg;
  362. _init_dspp_ops();
  363. _setup_dspp_ops(c, c->cap->features);
  364. rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_DSPP, idx, &sde_hw_ops);
  365. if (rc) {
  366. SDE_ERROR("failed to init hw blk %d\n", rc);
  367. goto blk_init_error;
  368. }
  369. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
  370. c->hw.blk_off + DSPP_VALID_START_OFF,
  371. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  372. if ((cfg->sblk->ltm.id == SDE_DSPP_LTM) && cfg->sblk->ltm.base) {
  373. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "LTM",
  374. c->hw.blk_off + cfg->sblk->ltm.base,
  375. c->hw.blk_off + cfg->sblk->ltm.base + 0xC4,
  376. c->hw.xin_id);
  377. }
  378. if ((cfg->sblk->rc.id == SDE_DSPP_RC) && cfg->sblk->rc.base) {
  379. snprintf(buf, ARRAY_SIZE(buf), "%s_%d", "rc", c->idx - DSPP_0);
  380. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, buf,
  381. c->hw.blk_off + cfg->sblk->rc.base,
  382. c->hw.blk_off + cfg->sblk->rc.base +
  383. cfg->sblk->rc.len, c->hw.xin_id);
  384. }
  385. if ((cfg->sblk->spr.id == SDE_DSPP_SPR) && cfg->sblk->spr.base) {
  386. snprintf(buf, ARRAY_SIZE(buf), "%s_%d", "spr", c->idx - DSPP_0);
  387. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, buf,
  388. c->hw.blk_off + cfg->sblk->spr.base,
  389. c->hw.blk_off + cfg->sblk->spr.base +
  390. cfg->sblk->spr.len, c->hw.xin_id);
  391. }
  392. if ((cfg->sblk->demura.id == SDE_DSPP_DEMURA) &&
  393. cfg->sblk->demura.base) {
  394. snprintf(buf, ARRAY_SIZE(buf), "%s_%d", "demura",
  395. c->idx - DSPP_0);
  396. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, buf,
  397. c->hw.blk_off + cfg->sblk->demura.base,
  398. c->hw.blk_off + cfg->sblk->demura.base +
  399. cfg->sblk->demura.len, c->hw.xin_id);
  400. }
  401. return c;
  402. blk_init_error:
  403. kfree(c);
  404. return ERR_PTR(rc);
  405. }
  406. void sde_hw_dspp_destroy(struct sde_hw_dspp *dspp)
  407. {
  408. if (dspp) {
  409. reg_dmav1_deinit_dspp_ops(dspp->idx);
  410. reg_dmav1_deinit_ltm_ops(dspp->idx);
  411. sde_hw_blk_destroy(&dspp->base);
  412. }
  413. kfree(dspp);
  414. }