sde_hw_ctl.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/delay.h>
  6. #include "sde_hwio.h"
  7. #include "sde_hw_ctl.h"
  8. #include "sde_dbg.h"
  9. #include "sde_kms.h"
  10. #include "sde_reg_dma.h"
  11. #define CTL_LAYER(lm) \
  12. (((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
  13. #define CTL_LAYER_EXT(lm) \
  14. (0x40 + (((lm) - LM_0) * 0x004))
  15. #define CTL_LAYER_EXT2(lm) \
  16. (0x70 + (((lm) - LM_0) * 0x004))
  17. #define CTL_LAYER_EXT3(lm) \
  18. (0xA0 + (((lm) - LM_0) * 0x004))
  19. #define CTL_TOP 0x014
  20. #define CTL_FLUSH 0x018
  21. #define CTL_START 0x01C
  22. #define CTL_PREPARE 0x0d0
  23. #define CTL_SW_RESET 0x030
  24. #define CTL_SW_RESET_OVERRIDE 0x060
  25. #define CTL_STATUS 0x064
  26. #define CTL_LAYER_EXTN_OFFSET 0x40
  27. #define CTL_ROT_TOP 0x0C0
  28. #define CTL_ROT_FLUSH 0x0C4
  29. #define CTL_ROT_START 0x0CC
  30. #define CTL_MERGE_3D_ACTIVE 0x0E4
  31. #define CTL_DSC_ACTIVE 0x0E8
  32. #define CTL_WB_ACTIVE 0x0EC
  33. #define CTL_CWB_ACTIVE 0x0F0
  34. #define CTL_INTF_ACTIVE 0x0F4
  35. #define CTL_CDM_ACTIVE 0x0F8
  36. #define CTL_FETCH_PIPE_ACTIVE 0x0FC
  37. #define CTL_MERGE_3D_FLUSH 0x100
  38. #define CTL_DSC_FLUSH 0x104
  39. #define CTL_WB_FLUSH 0x108
  40. #define CTL_CWB_FLUSH 0x10C
  41. #define CTL_INTF_FLUSH 0x110
  42. #define CTL_CDM_FLUSH 0x114
  43. #define CTL_PERIPH_FLUSH 0x128
  44. #define CTL_DSPP_0_FLUSH 0x13c
  45. #define CTL_INTF_MASTER 0x134
  46. #define CTL_UIDLE_ACTIVE 0x138
  47. #define CTL_MIXER_BORDER_OUT BIT(24)
  48. #define CTL_FLUSH_MASK_ROT BIT(27)
  49. #define CTL_FLUSH_MASK_CTL BIT(17)
  50. #define CTL_NUM_EXT 4
  51. #define CTL_SSPP_MAX_RECTS 2
  52. #define SDE_REG_RESET_TIMEOUT_US 2000
  53. #define SDE_REG_WAIT_RESET_TIMEOUT_US 100000
  54. #define UPDATE_MASK(m, idx, en) \
  55. ((m) = (en) ? ((m) | BIT((idx))) : ((m) & ~BIT((idx))))
  56. #define CTL_INVALID_BIT 0xffff
  57. #define VDC_IDX(i) ((i) + 16)
  58. #define UPDATE_ACTIVE(r, idx, en) UPDATE_MASK((r), (idx), (en))
  59. /**
  60. * List of SSPP bits in CTL_FLUSH
  61. */
  62. static const u32 sspp_tbl[SSPP_MAX] = { SDE_NONE, 0, 1, 2, 18, 3, 4, 5,
  63. 19, 11, 12, 24, 25, SDE_NONE, SDE_NONE};
  64. /**
  65. * List of layer mixer bits in CTL_FLUSH
  66. */
  67. static const u32 mixer_tbl[LM_MAX] = {SDE_NONE, 6, 7, 8, 9, 10, 20,
  68. SDE_NONE};
  69. /**
  70. * List of DSPP bits in CTL_FLUSH
  71. */
  72. static const u32 dspp_tbl[DSPP_MAX] = {SDE_NONE, 13, 14, 15, 21};
  73. /**
  74. * List of DSPP PA LUT bits in CTL_FLUSH
  75. */
  76. static const u32 dspp_pav_tbl[DSPP_MAX] = {SDE_NONE, 3, 4, 5, 19};
  77. /**
  78. * List of CDM LUT bits in CTL_FLUSH
  79. */
  80. static const u32 cdm_tbl[CDM_MAX] = {SDE_NONE, 26};
  81. /**
  82. * List of WB bits in CTL_FLUSH
  83. */
  84. static const u32 wb_tbl[WB_MAX] = {SDE_NONE, SDE_NONE, SDE_NONE, 16};
  85. /**
  86. * List of ROT bits in CTL_FLUSH
  87. */
  88. static const u32 rot_tbl[ROT_MAX] = {SDE_NONE, 27};
  89. /**
  90. * List of INTF bits in CTL_FLUSH
  91. */
  92. static const u32 intf_tbl[INTF_MAX] = {SDE_NONE, 31, 30, 29, 28};
  93. /**
  94. * Below definitions are for CTL supporting SDE_CTL_ACTIVE_CFG,
  95. * certain blocks have the individual flush control as well,
  96. * for such blocks flush is done by flushing individual control and
  97. * top level control.
  98. */
  99. /**
  100. * List of SSPP bits in CTL_FETCH_PIPE_ACTIVE
  101. */
  102. static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
  103. CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
  104. 1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};
  105. /**
  106. * list of WB bits in CTL_WB_FLUSH
  107. */
  108. static const u32 wb_flush_tbl[WB_MAX] = {SDE_NONE, SDE_NONE, SDE_NONE, 2};
  109. /**
  110. * list of INTF bits in CTL_INTF_FLUSH
  111. */
  112. static const u32 intf_flush_tbl[INTF_MAX] = {SDE_NONE, 0, 1, 2, 3, 4, 5};
  113. /**
  114. * list of DSC bits in CTL_DSC_FLUSH
  115. */
  116. static const u32 dsc_flush_tbl[DSC_MAX] = {SDE_NONE, 0, 1, 2, 3, 4, 5};
  117. /**
  118. * list of VDC bits in CTL_DSC_FLUSH
  119. */
  120. static const u32 vdc_flush_tbl[DSC_MAX] = {SDE_NONE, 16, 17};
  121. /**
  122. * list of MERGE_3D bits in CTL_MERGE_3D_FLUSH
  123. */
  124. static const u32 merge_3d_tbl[MERGE_3D_MAX] = {SDE_NONE, 0, 1, 2};
  125. /**
  126. * list of CDM bits in CTL_CDM_FLUSH
  127. */
  128. static const u32 cdm_flush_tbl[CDM_MAX] = {SDE_NONE, 0};
  129. /**
  130. * list of CWB bits in CTL_CWB_FLUSH
  131. */
  132. static const u32 cwb_flush_tbl[CWB_MAX] = {SDE_NONE, SDE_NONE, 1, 2, 3,
  133. 4, 5};
  134. /**
  135. * list of CWB bits in CTL_CWB_FLUSH for dedicated cwb
  136. */
  137. static const u32 dcwb_flush_tbl[CWB_MAX] = {SDE_NONE, SDE_NONE, 0, 1};
  138. /**
  139. * list of DSPP sub-blk flush bits in CTL_DSPP_x_FLUSH
  140. */
  141. static const u32 dspp_sub_blk_flush_tbl[SDE_DSPP_MAX] = {
  142. [SDE_DSPP_IGC] = 2,
  143. [SDE_DSPP_PCC] = 4,
  144. [SDE_DSPP_GC] = 5,
  145. [SDE_DSPP_HSIC] = 0,
  146. [SDE_DSPP_MEMCOLOR] = 0,
  147. [SDE_DSPP_SIXZONE] = 0,
  148. [SDE_DSPP_GAMUT] = 3,
  149. [SDE_DSPP_DITHER] = 0,
  150. [SDE_DSPP_HIST] = 0,
  151. [SDE_DSPP_VLUT] = 1,
  152. [SDE_DSPP_AD] = 0,
  153. [SDE_DSPP_LTM] = 7,
  154. [SDE_DSPP_SPR] = 8,
  155. [SDE_DSPP_DEMURA] = 9,
  156. [SDE_DSPP_RC] = 10,
  157. [SDE_DSPP_SB] = 31,
  158. };
  159. /**
  160. * struct ctl_sspp_stage_reg_map: Describes bit layout for a sspp stage cfg
  161. * @ext: Index to indicate LAYER_x_EXT id for given sspp
  162. * @start: Start position of blend stage bits for given sspp
  163. * @bits: Number of bits from @start assigned for given sspp
  164. * @sec_bit_mask: Bitmask to add to LAYER_x_EXT1 for missing bit of sspp
  165. */
  166. struct ctl_sspp_stage_reg_map {
  167. u32 ext;
  168. u32 start;
  169. u32 bits;
  170. u32 sec_bit_mask;
  171. };
  172. /* list of ctl_sspp_stage_reg_map for all the sppp */
  173. static const struct ctl_sspp_stage_reg_map
  174. sspp_reg_cfg_tbl[SSPP_MAX][CTL_SSPP_MAX_RECTS] = {
  175. /* SSPP_NONE */{ {0, 0, 0, 0}, {0, 0, 0, 0} },
  176. /* SSPP_VIG0 */{ {0, 0, 3, BIT(0)}, {3, 0, 4, 0} },
  177. /* SSPP_VIG1 */{ {0, 3, 3, BIT(2)}, {3, 4, 4, 0} },
  178. /* SSPP_VIG2 */{ {0, 6, 3, BIT(4)}, {3, 8, 4, 0} },
  179. /* SSPP_VIG3 */{ {0, 26, 3, BIT(6)}, {3, 12, 4, 0} },
  180. /* SSPP_RGB0 */{ {0, 9, 3, BIT(8)}, {0, 0, 0, 0} },
  181. /* SSPP_RGB1 */{ {0, 12, 3, BIT(10)}, {0, 0, 0, 0} },
  182. /* SSPP_RGB2 */{ {0, 15, 3, BIT(12)}, {0, 0, 0, 0} },
  183. /* SSPP_RGB3 */{ {0, 29, 3, BIT(14)}, {0, 0, 0, 0} },
  184. /* SSPP_DMA0 */{ {0, 18, 3, BIT(16)}, {2, 8, 4, 0} },
  185. /* SSPP_DMA1 */{ {0, 21, 3, BIT(18)}, {2, 12, 4, 0} },
  186. /* SSPP_DMA2 */{ {2, 0, 4, 0}, {2, 16, 4, 0} },
  187. /* SSPP_DMA3 */{ {2, 4, 4, 0}, {2, 20, 4, 0} },
  188. /* SSPP_CURSOR0 */{ {1, 20, 4, 0}, {0, 0, 0, 0} },
  189. /* SSPP_CURSOR1 */{ {1, 26, 4, 0}, {0, 0, 0, 0} }
  190. };
  191. /**
  192. * Individual flush bit in CTL_FLUSH
  193. */
  194. #define WB_IDX 16
  195. #define DSC_IDX 22
  196. #define MERGE_3D_IDX 23
  197. #define CDM_IDX 26
  198. #define CWB_IDX 28
  199. #define DSPP_IDX 29
  200. #define PERIPH_IDX 30
  201. #define INTF_IDX 31
  202. /* struct ctl_hw_flush_cfg: Defines the active ctl hw flush config,
  203. * See enum ctl_hw_flush_type for types
  204. * @blk_max: Maximum hw idx
  205. * @flush_reg: Register with corresponding active ctl hw
  206. * @flush_idx: Corresponding index in ctl flush
  207. * @flush_mask_idx: Index of hw flush mask to use
  208. * @flush_tbl: Pointer to flush table
  209. */
  210. struct ctl_hw_flush_cfg {
  211. u32 blk_max;
  212. u32 flush_reg;
  213. u32 flush_idx;
  214. u32 flush_mask_idx;
  215. const u32 *flush_tbl;
  216. };
  217. static const struct ctl_hw_flush_cfg
  218. ctl_hw_flush_cfg_tbl_v1[SDE_HW_FLUSH_MAX] = {
  219. {WB_MAX, CTL_WB_FLUSH, WB_IDX, SDE_HW_FLUSH_WB,
  220. wb_flush_tbl}, /* SDE_HW_FLUSH_WB */
  221. {DSC_MAX, CTL_DSC_FLUSH, DSC_IDX, SDE_HW_FLUSH_DSC,
  222. dsc_flush_tbl}, /* SDE_HW_FLUSH_DSC */
  223. /* VDC is flushed to dsc, flush_reg = 0 so flush is done only once */
  224. {VDC_MAX, 0, DSC_IDX, SDE_HW_FLUSH_DSC,
  225. vdc_flush_tbl}, /* SDE_HW_FLUSH_VDC */
  226. {MERGE_3D_MAX, CTL_MERGE_3D_FLUSH, MERGE_3D_IDX, SDE_HW_FLUSH_MERGE_3D,
  227. merge_3d_tbl}, /* SDE_HW_FLUSH_MERGE_3D */
  228. {CDM_MAX, CTL_CDM_FLUSH, CDM_IDX, SDE_HW_FLUSH_CDM,
  229. cdm_flush_tbl}, /* SDE_HW_FLUSH_CDM */
  230. {CWB_MAX, CTL_CWB_FLUSH, CWB_IDX, SDE_HW_FLUSH_CWB,
  231. cwb_flush_tbl}, /* SDE_HW_FLUSH_CWB */
  232. {INTF_MAX, CTL_PERIPH_FLUSH, PERIPH_IDX, SDE_HW_FLUSH_PERIPH,
  233. intf_flush_tbl }, /* SDE_HW_FLUSH_PERIPH */
  234. {INTF_MAX, CTL_INTF_FLUSH, INTF_IDX, SDE_HW_FLUSH_INTF,
  235. intf_flush_tbl } /* SDE_HW_FLUSH_INTF */
  236. };
  237. static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl,
  238. struct sde_mdss_cfg *m,
  239. void __iomem *addr,
  240. struct sde_hw_blk_reg_map *b)
  241. {
  242. int i;
  243. for (i = 0; i < m->ctl_count; i++) {
  244. if (ctl == m->ctl[i].id) {
  245. b->base_off = addr;
  246. b->blk_off = m->ctl[i].base;
  247. b->length = m->ctl[i].len;
  248. b->hwversion = m->hwversion;
  249. b->log_mask = SDE_DBG_MASK_CTL;
  250. return &m->ctl[i];
  251. }
  252. }
  253. return ERR_PTR(-ENOMEM);
  254. }
  255. static int _mixer_stages(const struct sde_lm_cfg *mixer, int count,
  256. enum sde_lm lm)
  257. {
  258. int i;
  259. int stages = -EINVAL;
  260. for (i = 0; i < count; i++) {
  261. if (lm == mixer[i].id) {
  262. stages = mixer[i].sblk->maxblendstages;
  263. break;
  264. }
  265. }
  266. return stages;
  267. }
  268. static inline bool _is_dspp_flush_pending(struct sde_hw_ctl *ctx)
  269. {
  270. int i;
  271. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++) {
  272. if (ctx->flush.pending_dspp_flush_masks[i])
  273. return true;
  274. }
  275. return false;
  276. }
  277. static inline int sde_hw_ctl_trigger_start(struct sde_hw_ctl *ctx)
  278. {
  279. if (!ctx)
  280. return -EINVAL;
  281. SDE_REG_WRITE(&ctx->hw, CTL_START, 0x1);
  282. return 0;
  283. }
  284. static inline int sde_hw_ctl_get_start_state(struct sde_hw_ctl *ctx)
  285. {
  286. if (!ctx)
  287. return -EINVAL;
  288. return SDE_REG_READ(&ctx->hw, CTL_START);
  289. }
  290. static inline int sde_hw_ctl_trigger_pending(struct sde_hw_ctl *ctx)
  291. {
  292. if (!ctx)
  293. return -EINVAL;
  294. SDE_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
  295. return 0;
  296. }
  297. static inline int sde_hw_ctl_clear_pending_flush(struct sde_hw_ctl *ctx)
  298. {
  299. if (!ctx)
  300. return -EINVAL;
  301. memset(&ctx->flush, 0, sizeof(ctx->flush));
  302. return 0;
  303. }
  304. static inline int sde_hw_ctl_update_pending_flush(struct sde_hw_ctl *ctx,
  305. struct sde_ctl_flush_cfg *cfg)
  306. {
  307. if (!ctx || !cfg)
  308. return -EINVAL;
  309. ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
  310. return 0;
  311. }
  312. static int sde_hw_ctl_get_pending_flush(struct sde_hw_ctl *ctx,
  313. struct sde_ctl_flush_cfg *cfg)
  314. {
  315. if (!ctx || !cfg)
  316. return -EINVAL;
  317. memcpy(cfg, &ctx->flush, sizeof(*cfg));
  318. return 0;
  319. }
  320. static inline int sde_hw_ctl_trigger_flush(struct sde_hw_ctl *ctx)
  321. {
  322. if (!ctx)
  323. return -EINVAL;
  324. SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
  325. return 0;
  326. }
  327. static inline u32 sde_hw_ctl_get_flush_register(struct sde_hw_ctl *ctx)
  328. {
  329. struct sde_hw_blk_reg_map *c;
  330. u32 rot_op_mode;
  331. if (!ctx)
  332. return 0;
  333. c = &ctx->hw;
  334. rot_op_mode = SDE_REG_READ(c, CTL_ROT_TOP) & 0x3;
  335. /* rotate flush bit is undefined if offline mode, so ignore it */
  336. if (rot_op_mode == SDE_CTL_ROT_OP_MODE_OFFLINE)
  337. return SDE_REG_READ(c, CTL_FLUSH) & ~CTL_FLUSH_MASK_ROT;
  338. return SDE_REG_READ(c, CTL_FLUSH);
  339. }
  340. static inline void sde_hw_ctl_uidle_enable(struct sde_hw_ctl *ctx, bool enable)
  341. {
  342. u32 val;
  343. if (!ctx)
  344. return;
  345. val = SDE_REG_READ(&ctx->hw, CTL_UIDLE_ACTIVE);
  346. val = (val & ~BIT(0)) | (enable ? BIT(0) : 0);
  347. SDE_REG_WRITE(&ctx->hw, CTL_UIDLE_ACTIVE, val);
  348. }
  349. static inline int sde_hw_ctl_update_bitmask_sspp(struct sde_hw_ctl *ctx,
  350. enum sde_sspp sspp,
  351. bool enable)
  352. {
  353. if (!ctx)
  354. return -EINVAL;
  355. if (!(sspp > SSPP_NONE) || !(sspp < SSPP_MAX)) {
  356. SDE_ERROR("Unsupported pipe %d\n", sspp);
  357. return -EINVAL;
  358. }
  359. UPDATE_MASK(ctx->flush.pending_flush_mask, sspp_tbl[sspp], enable);
  360. return 0;
  361. }
  362. static inline int sde_hw_ctl_update_bitmask_mixer(struct sde_hw_ctl *ctx,
  363. enum sde_lm lm,
  364. bool enable)
  365. {
  366. if (!ctx)
  367. return -EINVAL;
  368. if (!(lm > SDE_NONE) || !(lm < LM_MAX)) {
  369. SDE_ERROR("Unsupported mixer %d\n", lm);
  370. return -EINVAL;
  371. }
  372. UPDATE_MASK(ctx->flush.pending_flush_mask, mixer_tbl[lm], enable);
  373. ctx->flush.pending_flush_mask |= CTL_FLUSH_MASK_CTL;
  374. return 0;
  375. }
  376. static inline int sde_hw_ctl_update_bitmask_dspp(struct sde_hw_ctl *ctx,
  377. enum sde_dspp dspp,
  378. bool enable)
  379. {
  380. if (!ctx)
  381. return -EINVAL;
  382. if (!(dspp > SDE_NONE) || !(dspp < DSPP_MAX)) {
  383. SDE_ERROR("Unsupported dspp %d\n", dspp);
  384. return -EINVAL;
  385. }
  386. UPDATE_MASK(ctx->flush.pending_flush_mask, dspp_tbl[dspp], enable);
  387. return 0;
  388. }
  389. static inline int sde_hw_ctl_update_bitmask_dspp_pavlut(struct sde_hw_ctl *ctx,
  390. enum sde_dspp dspp, bool enable)
  391. {
  392. if (!ctx)
  393. return -EINVAL;
  394. if (!(dspp > SDE_NONE) || !(dspp < DSPP_MAX)) {
  395. SDE_ERROR("Unsupported dspp %d\n", dspp);
  396. return -EINVAL;
  397. }
  398. UPDATE_MASK(ctx->flush.pending_flush_mask, dspp_pav_tbl[dspp], enable);
  399. return 0;
  400. }
  401. static inline int sde_hw_ctl_update_bitmask_cdm(struct sde_hw_ctl *ctx,
  402. enum sde_cdm cdm,
  403. bool enable)
  404. {
  405. if (!ctx)
  406. return -EINVAL;
  407. if (!(cdm > SDE_NONE) || !(cdm < CDM_MAX) || (cdm == CDM_1)) {
  408. SDE_ERROR("Unsupported cdm %d\n", cdm);
  409. return -EINVAL;
  410. }
  411. UPDATE_MASK(ctx->flush.pending_flush_mask, cdm_tbl[cdm], enable);
  412. return 0;
  413. }
  414. static inline int sde_hw_ctl_update_bitmask_wb(struct sde_hw_ctl *ctx,
  415. enum sde_wb wb, bool enable)
  416. {
  417. if (!ctx)
  418. return -EINVAL;
  419. if (!(wb > SDE_NONE) || !(wb < WB_MAX) ||
  420. (wb == WB_0) || (wb == WB_1)) {
  421. SDE_ERROR("Unsupported wb %d\n", wb);
  422. return -EINVAL;
  423. }
  424. UPDATE_MASK(ctx->flush.pending_flush_mask, wb_tbl[wb], enable);
  425. return 0;
  426. }
  427. static inline int sde_hw_ctl_update_bitmask_intf(struct sde_hw_ctl *ctx,
  428. enum sde_intf intf, bool enable)
  429. {
  430. if (!ctx)
  431. return -EINVAL;
  432. if (!(intf > SDE_NONE) || !(intf < INTF_MAX) || (intf > INTF_4)) {
  433. SDE_ERROR("Unsupported intf %d\n", intf);
  434. return -EINVAL;
  435. }
  436. UPDATE_MASK(ctx->flush.pending_flush_mask, intf_tbl[intf], enable);
  437. return 0;
  438. }
  439. static inline int sde_hw_ctl_update_bitmask(struct sde_hw_ctl *ctx,
  440. enum ctl_hw_flush_type type, u32 blk_idx, bool enable)
  441. {
  442. int ret = 0;
  443. if (!ctx)
  444. return -EINVAL;
  445. switch (type) {
  446. case SDE_HW_FLUSH_CDM:
  447. ret = sde_hw_ctl_update_bitmask_cdm(ctx, blk_idx, enable);
  448. break;
  449. case SDE_HW_FLUSH_WB:
  450. ret = sde_hw_ctl_update_bitmask_wb(ctx, blk_idx, enable);
  451. break;
  452. case SDE_HW_FLUSH_INTF:
  453. ret = sde_hw_ctl_update_bitmask_intf(ctx, blk_idx, enable);
  454. break;
  455. default:
  456. break;
  457. }
  458. return ret;
  459. }
  460. static inline int sde_hw_ctl_update_bitmask_v1(struct sde_hw_ctl *ctx,
  461. enum ctl_hw_flush_type type, u32 blk_idx, bool enable)
  462. {
  463. const struct ctl_hw_flush_cfg *cfg;
  464. if (!ctx || !(type < SDE_HW_FLUSH_MAX))
  465. return -EINVAL;
  466. cfg = &ctl_hw_flush_cfg_tbl_v1[type];
  467. if ((blk_idx <= SDE_NONE) || (blk_idx >= cfg->blk_max)) {
  468. SDE_ERROR("Unsupported hw idx, type:%d, blk_idx:%d, blk_max:%d",
  469. type, blk_idx, cfg->blk_max);
  470. return -EINVAL;
  471. }
  472. UPDATE_MASK(ctx->flush.pending_hw_flush_mask[cfg->flush_mask_idx],
  473. cfg->flush_tbl[blk_idx], enable);
  474. if (ctx->flush.pending_hw_flush_mask[cfg->flush_mask_idx])
  475. UPDATE_MASK(ctx->flush.pending_flush_mask, cfg->flush_idx, 1);
  476. else
  477. UPDATE_MASK(ctx->flush.pending_flush_mask, cfg->flush_idx, 0);
  478. return 0;
  479. }
  480. static inline int sde_hw_ctl_update_pending_flush_v1(
  481. struct sde_hw_ctl *ctx,
  482. struct sde_ctl_flush_cfg *cfg)
  483. {
  484. int i = 0;
  485. if (!ctx || !cfg)
  486. return -EINVAL;
  487. for (i = 0; i < SDE_HW_FLUSH_MAX; i++)
  488. ctx->flush.pending_hw_flush_mask[i] |=
  489. cfg->pending_hw_flush_mask[i];
  490. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++)
  491. ctx->flush.pending_dspp_flush_masks[i] |=
  492. cfg->pending_dspp_flush_masks[i];
  493. ctx->flush.pending_flush_mask |= cfg->pending_flush_mask;
  494. return 0;
  495. }
  496. static inline int sde_hw_ctl_update_bitmask_dspp_subblk(struct sde_hw_ctl *ctx,
  497. enum sde_dspp dspp, u32 sub_blk, bool enable)
  498. {
  499. if (!ctx || dspp < DSPP_0 || dspp >= DSPP_MAX ||
  500. sub_blk < SDE_DSPP_IGC || sub_blk >= SDE_DSPP_MAX) {
  501. SDE_ERROR("invalid args - ctx %s, dspp %d sub_block %d\n",
  502. ctx ? "valid" : "invalid", dspp, sub_blk);
  503. return -EINVAL;
  504. }
  505. UPDATE_MASK(ctx->flush.pending_dspp_flush_masks[dspp - DSPP_0],
  506. dspp_sub_blk_flush_tbl[sub_blk], enable);
  507. if (_is_dspp_flush_pending(ctx))
  508. UPDATE_MASK(ctx->flush.pending_flush_mask, DSPP_IDX, 1);
  509. else
  510. UPDATE_MASK(ctx->flush.pending_flush_mask, DSPP_IDX, 0);
  511. return 0;
  512. }
  513. static void sde_hw_ctl_set_fetch_pipe_active(struct sde_hw_ctl *ctx,
  514. unsigned long *fetch_active)
  515. {
  516. int i;
  517. u32 val = 0;
  518. if (fetch_active) {
  519. for (i = 0; i < SSPP_MAX; i++) {
  520. if (test_bit(i, fetch_active) &&
  521. fetch_tbl[i] != CTL_INVALID_BIT)
  522. val |= BIT(fetch_tbl[i]);
  523. }
  524. }
  525. SDE_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);
  526. }
  527. static u32 sde_hw_ctl_get_active_fetch_pipes(struct sde_hw_ctl *ctx)
  528. {
  529. int i;
  530. u32 fetch_info, fetch_active = 0;
  531. if (!ctx) {
  532. DRM_ERROR("invalid args - ctx invalid\n");
  533. return 0;
  534. }
  535. fetch_info = SDE_REG_READ(&ctx->hw, CTL_FETCH_PIPE_ACTIVE);
  536. for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
  537. if (fetch_tbl[i] != CTL_INVALID_BIT &&
  538. fetch_info & BIT(fetch_tbl[i])) {
  539. fetch_active |= BIT(i);
  540. }
  541. }
  542. return fetch_active;
  543. }
  544. static inline void _sde_hw_ctl_write_dspp_flushes(struct sde_hw_ctl *ctx) {
  545. int i;
  546. bool has_dspp_flushes = ctx->caps->features &
  547. BIT(SDE_CTL_UNIFIED_DSPP_FLUSH);
  548. if (!has_dspp_flushes)
  549. return;
  550. for (i = 0; i < CTL_MAX_DSPP_COUNT; i++) {
  551. u32 pending = ctx->flush.pending_dspp_flush_masks[i];
  552. if (pending)
  553. SDE_REG_WRITE(&ctx->hw, CTL_DSPP_0_FLUSH + (i * 4),
  554. pending);
  555. }
  556. }
  557. static inline int sde_hw_ctl_trigger_flush_v1(struct sde_hw_ctl *ctx)
  558. {
  559. int i = 0;
  560. const struct ctl_hw_flush_cfg *cfg = &ctl_hw_flush_cfg_tbl_v1[0];
  561. if (!ctx)
  562. return -EINVAL;
  563. if (ctx->flush.pending_flush_mask & BIT(DSPP_IDX))
  564. _sde_hw_ctl_write_dspp_flushes(ctx);
  565. for (i = 0; i < SDE_HW_FLUSH_MAX; i++)
  566. if (cfg[i].flush_reg &&
  567. ctx->flush.pending_flush_mask &
  568. BIT(cfg[i].flush_idx))
  569. SDE_REG_WRITE(&ctx->hw,
  570. cfg[i].flush_reg,
  571. ctx->flush.pending_hw_flush_mask[i]);
  572. SDE_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->flush.pending_flush_mask);
  573. return 0;
  574. }
  575. static inline u32 sde_hw_ctl_get_intf_v1(struct sde_hw_ctl *ctx)
  576. {
  577. struct sde_hw_blk_reg_map *c;
  578. u32 intf_active;
  579. if (!ctx) {
  580. pr_err("Invalid input argument\n");
  581. return 0;
  582. }
  583. c = &ctx->hw;
  584. intf_active = SDE_REG_READ(c, CTL_INTF_ACTIVE);
  585. return intf_active;
  586. }
  587. static inline u32 sde_hw_ctl_get_intf(struct sde_hw_ctl *ctx)
  588. {
  589. struct sde_hw_blk_reg_map *c;
  590. u32 ctl_top;
  591. u32 intf_active = 0;
  592. if (!ctx) {
  593. pr_err("Invalid input argument\n");
  594. return 0;
  595. }
  596. c = &ctx->hw;
  597. ctl_top = SDE_REG_READ(c, CTL_TOP);
  598. intf_active = (ctl_top > 0) ?
  599. BIT(ctl_top - 1) : 0;
  600. return intf_active;
  601. }
  602. static u32 sde_hw_ctl_poll_reset_status(struct sde_hw_ctl *ctx, u32 timeout_us)
  603. {
  604. struct sde_hw_blk_reg_map *c;
  605. ktime_t timeout;
  606. u32 status;
  607. if (!ctx)
  608. return 0;
  609. c = &ctx->hw;
  610. timeout = ktime_add_us(ktime_get(), timeout_us);
  611. /*
  612. * it takes around 30us to have mdp finish resetting its ctl path
  613. * poll every 50us so that reset should be completed at 1st poll
  614. */
  615. do {
  616. status = SDE_REG_READ(c, CTL_SW_RESET);
  617. status &= 0x1;
  618. if (status)
  619. usleep_range(20, 50);
  620. } while (status && ktime_compare_safe(ktime_get(), timeout) < 0);
  621. return status;
  622. }
  623. static u32 sde_hw_ctl_get_reset_status(struct sde_hw_ctl *ctx)
  624. {
  625. if (!ctx)
  626. return 0;
  627. return (u32)SDE_REG_READ(&ctx->hw, CTL_SW_RESET);
  628. }
  629. static u32 sde_hw_ctl_get_scheduler_status(struct sde_hw_ctl *ctx)
  630. {
  631. if (!ctx)
  632. return INVALID_CTL_STATUS;
  633. return (u32)SDE_REG_READ(&ctx->hw, CTL_STATUS);
  634. }
  635. static int sde_hw_ctl_reset_control(struct sde_hw_ctl *ctx)
  636. {
  637. struct sde_hw_blk_reg_map *c;
  638. if (!ctx)
  639. return 0;
  640. c = &ctx->hw;
  641. pr_debug("issuing hw ctl reset for ctl:%d\n", ctx->idx);
  642. SDE_REG_WRITE(c, CTL_SW_RESET, 0x1);
  643. if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_RESET_TIMEOUT_US))
  644. return -EINVAL;
  645. return 0;
  646. }
  647. static void sde_hw_ctl_hard_reset(struct sde_hw_ctl *ctx, bool enable)
  648. {
  649. struct sde_hw_blk_reg_map *c;
  650. if (!ctx)
  651. return;
  652. c = &ctx->hw;
  653. pr_debug("hw ctl hard reset for ctl:%d, %d\n",
  654. ctx->idx - CTL_0, enable);
  655. SDE_REG_WRITE(c, CTL_SW_RESET_OVERRIDE, enable);
  656. }
  657. static int sde_hw_ctl_wait_reset_status(struct sde_hw_ctl *ctx)
  658. {
  659. struct sde_hw_blk_reg_map *c;
  660. u32 status;
  661. if (!ctx)
  662. return 0;
  663. c = &ctx->hw;
  664. status = SDE_REG_READ(c, CTL_SW_RESET);
  665. status &= 0x01;
  666. if (!status)
  667. return 0;
  668. pr_debug("hw ctl reset is set for ctl:%d\n", ctx->idx);
  669. if (sde_hw_ctl_poll_reset_status(ctx, SDE_REG_WAIT_RESET_TIMEOUT_US)) {
  670. pr_err("hw recovery is not complete for ctl:%d\n", ctx->idx);
  671. return -EINVAL;
  672. }
  673. return 0;
  674. }
  675. static void sde_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx)
  676. {
  677. struct sde_hw_blk_reg_map *c;
  678. int i;
  679. if (!ctx)
  680. return;
  681. c = &ctx->hw;
  682. for (i = 0; i < ctx->mixer_count; i++) {
  683. int mixer_id = ctx->mixer_hw_caps[i].id;
  684. SDE_REG_WRITE(c, CTL_LAYER(mixer_id), 0);
  685. SDE_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);
  686. SDE_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);
  687. SDE_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);
  688. }
  689. SDE_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
  690. }
  691. static void _sde_hw_ctl_get_mixer_cfg(struct sde_hw_ctl *ctx,
  692. struct sde_hw_stage_cfg *stage_cfg, int stages, u32 *cfg)
  693. {
  694. int i, j, pipes_per_stage;
  695. const struct ctl_sspp_stage_reg_map *reg_map;
  696. if (test_bit(SDE_MIXER_SOURCESPLIT, &ctx->mixer_hw_caps->features))
  697. pipes_per_stage = PIPES_PER_STAGE;
  698. else
  699. pipes_per_stage = 1;
  700. for (i = 0; i <= stages; i++) {
  701. /* overflow to ext register if 'i + 1 > 7' */
  702. for (j = 0 ; j < pipes_per_stage; j++) {
  703. enum sde_sspp pipe = stage_cfg->stage[i][j];
  704. enum sde_sspp_multirect_index rect_index =
  705. stage_cfg->multirect_index[i][j];
  706. u32 mixer_value;
  707. if (!pipe || pipe >= SSPP_MAX || rect_index >= SDE_SSPP_RECT_MAX)
  708. continue;
  709. /* Handle multi rect enums */
  710. if (rect_index == SDE_SSPP_RECT_SOLO)
  711. rect_index = SDE_SSPP_RECT_0;
  712. reg_map = &sspp_reg_cfg_tbl[pipe][rect_index-1];
  713. if (!reg_map->bits)
  714. continue;
  715. mixer_value = (i + 1) & (BIT(reg_map->bits) - 1);
  716. cfg[reg_map->ext] |= (mixer_value << reg_map->start);
  717. if ((i + 1) > mixer_value)
  718. cfg[1] |= reg_map->sec_bit_mask;
  719. }
  720. }
  721. }
  722. static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
  723. enum sde_lm lm, struct sde_hw_stage_cfg *stage_cfg,
  724. bool disable_border)
  725. {
  726. struct sde_hw_blk_reg_map *c;
  727. u32 cfg[CTL_NUM_EXT] = { 0 };
  728. int stages;
  729. if (!ctx)
  730. return;
  731. stages = _mixer_stages(ctx->mixer_hw_caps, ctx->mixer_count, lm);
  732. if (stages < 0)
  733. return;
  734. c = &ctx->hw;
  735. if (stage_cfg)
  736. _sde_hw_ctl_get_mixer_cfg(ctx, stage_cfg, stages, cfg);
  737. if (!disable_border &&
  738. ((!cfg[0] && !cfg[1] && !cfg[2] && !cfg[3]) ||
  739. (stage_cfg && !stage_cfg->stage[0][0])))
  740. cfg[0] |= CTL_MIXER_BORDER_OUT;
  741. SDE_REG_WRITE(c, CTL_LAYER(lm), cfg[0]);
  742. SDE_REG_WRITE(c, CTL_LAYER_EXT(lm), cfg[1]);
  743. SDE_REG_WRITE(c, CTL_LAYER_EXT2(lm), cfg[2]);
  744. SDE_REG_WRITE(c, CTL_LAYER_EXT3(lm), cfg[3]);
  745. }
  746. static u32 sde_hw_ctl_get_staged_sspp(struct sde_hw_ctl *ctx, enum sde_lm lm,
  747. struct sde_sspp_index_info *info, u32 info_max_cnt)
  748. {
  749. int i, j;
  750. u32 count = 0;
  751. u32 mask = 0;
  752. bool staged;
  753. u32 mixercfg[CTL_NUM_EXT];
  754. struct sde_hw_blk_reg_map *c;
  755. const struct ctl_sspp_stage_reg_map *sspp_cfg;
  756. if (!ctx || (lm >= LM_MAX) || !info)
  757. return count;
  758. c = &ctx->hw;
  759. mixercfg[0] = SDE_REG_READ(c, CTL_LAYER(lm));
  760. mixercfg[1] = SDE_REG_READ(c, CTL_LAYER_EXT(lm));
  761. mixercfg[2] = SDE_REG_READ(c, CTL_LAYER_EXT2(lm));
  762. mixercfg[3] = SDE_REG_READ(c, CTL_LAYER_EXT3(lm));
  763. for (i = SSPP_VIG0; i < SSPP_MAX; i++) {
  764. for (j = 0; j < CTL_SSPP_MAX_RECTS; j++) {
  765. if (count >= info_max_cnt)
  766. goto end;
  767. sspp_cfg = &sspp_reg_cfg_tbl[i][j];
  768. if (!sspp_cfg->bits || sspp_cfg->ext >= CTL_NUM_EXT)
  769. continue;
  770. mask = ((0x1 << sspp_cfg->bits) - 1) << sspp_cfg->start;
  771. staged = mixercfg[sspp_cfg->ext] & mask;
  772. if (!staged)
  773. staged = mixercfg[1] & sspp_cfg->sec_bit_mask;
  774. if (staged) {
  775. info[count].sspp = i;
  776. info[count].is_virtual = j;
  777. count++;
  778. }
  779. }
  780. }
  781. end:
  782. return count;
  783. }
  784. static int sde_hw_ctl_intf_cfg_v1(struct sde_hw_ctl *ctx,
  785. struct sde_hw_intf_cfg_v1 *cfg)
  786. {
  787. struct sde_hw_blk_reg_map *c;
  788. u32 intf_active = 0;
  789. u32 wb_active = 0;
  790. u32 merge_3d_active = 0;
  791. u32 cwb_active = 0;
  792. u32 mode_sel = 0xf0000000;
  793. u32 cdm_active = 0;
  794. u32 intf_master = 0;
  795. u32 i;
  796. if (!ctx)
  797. return -EINVAL;
  798. c = &ctx->hw;
  799. for (i = 0; i < cfg->intf_count; i++) {
  800. if (cfg->intf[i])
  801. intf_active |= BIT(cfg->intf[i] - INTF_0);
  802. }
  803. if (cfg->intf_count > 1)
  804. intf_master = BIT(cfg->intf_master - INTF_0);
  805. for (i = 0; i < cfg->wb_count; i++) {
  806. if (cfg->wb[i])
  807. wb_active |= BIT(cfg->wb[i] - WB_0);
  808. }
  809. for (i = 0; i < cfg->merge_3d_count; i++) {
  810. if (cfg->merge_3d[i])
  811. merge_3d_active |= BIT(cfg->merge_3d[i] - MERGE_3D_0);
  812. }
  813. for (i = 0; i < cfg->cwb_count; i++) {
  814. if (cfg->cwb[i])
  815. cwb_active |= BIT(cfg->cwb[i] - CWB_0);
  816. }
  817. for (i = 0; i < cfg->cdm_count; i++) {
  818. if (cfg->cdm[i])
  819. cdm_active |= BIT(cfg->cdm[i] - CDM_0);
  820. }
  821. if (cfg->intf_mode_sel == SDE_CTL_MODE_SEL_CMD)
  822. mode_sel |= BIT(17);
  823. SDE_REG_WRITE(c, CTL_TOP, mode_sel);
  824. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  825. SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
  826. SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
  827. SDE_REG_WRITE(c, CTL_CDM_ACTIVE, cdm_active);
  828. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  829. SDE_REG_WRITE(c, CTL_INTF_MASTER, intf_master);
  830. return 0;
  831. }
  832. static int sde_hw_ctl_reset_post_disable(struct sde_hw_ctl *ctx,
  833. struct sde_hw_intf_cfg_v1 *cfg, u32 merge_3d_idx)
  834. {
  835. struct sde_hw_blk_reg_map *c;
  836. u32 intf_active = 0, wb_active = 0, merge_3d_active = 0;
  837. u32 intf_flush = 0, wb_flush = 0;
  838. u32 i;
  839. if (!ctx || !cfg) {
  840. SDE_ERROR("invalid hw_ctl or hw_intf blk\n");
  841. return -EINVAL;
  842. }
  843. c = &ctx->hw;
  844. for (i = 0; i < cfg->intf_count; i++) {
  845. if (cfg->intf[i]) {
  846. intf_active &= ~BIT(cfg->intf[i] - INTF_0);
  847. intf_flush |= BIT(cfg->intf[i] - INTF_0);
  848. }
  849. }
  850. for (i = 0; i < cfg->wb_count; i++) {
  851. if (cfg->wb[i]) {
  852. wb_active &= ~BIT(cfg->wb[i] - WB_0);
  853. wb_flush |= BIT(cfg->wb[i] - WB_0);
  854. }
  855. }
  856. if (merge_3d_idx) {
  857. /* disable and flush merge3d_blk */
  858. merge_3d_active &= ~BIT(merge_3d_idx - MERGE_3D_0);
  859. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_MERGE_3D] =
  860. BIT(merge_3d_idx - MERGE_3D_0);
  861. UPDATE_MASK(ctx->flush.pending_flush_mask, MERGE_3D_IDX, 1);
  862. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  863. }
  864. sde_hw_ctl_clear_all_blendstages(ctx);
  865. if (cfg->intf_count) {
  866. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_INTF] =
  867. intf_flush;
  868. UPDATE_MASK(ctx->flush.pending_flush_mask, INTF_IDX, 1);
  869. SDE_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
  870. }
  871. if (cfg->wb_count) {
  872. ctx->flush.pending_hw_flush_mask[SDE_HW_FLUSH_WB] = wb_flush;
  873. UPDATE_MASK(ctx->flush.pending_flush_mask, WB_IDX, 1);
  874. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  875. }
  876. return 0;
  877. }
  878. static int sde_hw_ctl_update_intf_cfg(struct sde_hw_ctl *ctx,
  879. struct sde_hw_intf_cfg_v1 *cfg, bool enable)
  880. {
  881. int i;
  882. u32 cwb_active = 0;
  883. u32 merge_3d_active = 0;
  884. u32 wb_active = 0;
  885. u32 dsc_active = 0;
  886. u32 vdc_active = 0;
  887. struct sde_hw_blk_reg_map *c;
  888. if (!ctx)
  889. return -EINVAL;
  890. c = &ctx->hw;
  891. if (cfg->cwb_count) {
  892. cwb_active = SDE_REG_READ(c, CTL_CWB_ACTIVE);
  893. for (i = 0; i < cfg->cwb_count; i++) {
  894. if (cfg->cwb[i])
  895. UPDATE_ACTIVE(cwb_active,
  896. (cfg->cwb[i] - CWB_0),
  897. enable);
  898. }
  899. wb_active = enable ? BIT(2) : 0;
  900. SDE_REG_WRITE(c, CTL_CWB_ACTIVE, cwb_active);
  901. SDE_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
  902. }
  903. if (cfg->merge_3d_count) {
  904. merge_3d_active = SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE);
  905. for (i = 0; i < cfg->merge_3d_count; i++) {
  906. if (cfg->merge_3d[i])
  907. UPDATE_ACTIVE(merge_3d_active,
  908. (cfg->merge_3d[i] - MERGE_3D_0),
  909. enable);
  910. }
  911. SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
  912. }
  913. if (cfg->dsc_count) {
  914. dsc_active = SDE_REG_READ(c, CTL_DSC_ACTIVE);
  915. for (i = 0; i < cfg->dsc_count; i++) {
  916. if (cfg->dsc[i])
  917. UPDATE_ACTIVE(dsc_active,
  918. (cfg->dsc[i] - DSC_0), enable);
  919. }
  920. SDE_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
  921. }
  922. if (cfg->vdc_count) {
  923. vdc_active = SDE_REG_READ(c, CTL_DSC_ACTIVE);
  924. for (i = 0; i < cfg->vdc_count; i++) {
  925. if (cfg->vdc[i])
  926. UPDATE_ACTIVE(vdc_active,
  927. VDC_IDX(cfg->vdc[i] - VDC_0), enable);
  928. }
  929. SDE_REG_WRITE(c, CTL_DSC_ACTIVE, vdc_active);
  930. }
  931. return 0;
  932. }
  933. static int sde_hw_ctl_intf_cfg(struct sde_hw_ctl *ctx,
  934. struct sde_hw_intf_cfg *cfg)
  935. {
  936. struct sde_hw_blk_reg_map *c;
  937. u32 intf_cfg = 0;
  938. if (!ctx)
  939. return -EINVAL;
  940. c = &ctx->hw;
  941. intf_cfg |= (cfg->intf & 0xF) << 4;
  942. if (cfg->wb)
  943. intf_cfg |= (cfg->wb & 0x3) + 2;
  944. if (cfg->mode_3d) {
  945. intf_cfg |= BIT(19);
  946. intf_cfg |= (cfg->mode_3d - 0x1) << 20;
  947. }
  948. switch (cfg->intf_mode_sel) {
  949. case SDE_CTL_MODE_SEL_VID:
  950. intf_cfg &= ~BIT(17);
  951. intf_cfg &= ~(0x3 << 15);
  952. break;
  953. case SDE_CTL_MODE_SEL_CMD:
  954. intf_cfg |= BIT(17);
  955. intf_cfg |= ((cfg->stream_sel & 0x3) << 15);
  956. break;
  957. default:
  958. pr_err("unknown interface type %d\n", cfg->intf_mode_sel);
  959. return -EINVAL;
  960. }
  961. SDE_REG_WRITE(c, CTL_TOP, intf_cfg);
  962. return 0;
  963. }
  964. static void sde_hw_ctl_update_wb_cfg(struct sde_hw_ctl *ctx,
  965. struct sde_hw_intf_cfg *cfg, bool enable)
  966. {
  967. struct sde_hw_blk_reg_map *c = &ctx->hw;
  968. u32 intf_cfg = 0;
  969. if (!cfg->wb)
  970. return;
  971. intf_cfg = SDE_REG_READ(c, CTL_TOP);
  972. if (enable)
  973. intf_cfg |= (cfg->wb & 0x3) + 2;
  974. else
  975. intf_cfg &= ~((cfg->wb & 0x3) + 2);
  976. SDE_REG_WRITE(c, CTL_TOP, intf_cfg);
  977. }
  978. static inline u32 sde_hw_ctl_read_ctl_layers(struct sde_hw_ctl *ctx, int index)
  979. {
  980. struct sde_hw_blk_reg_map *c;
  981. u32 ctl_top;
  982. if (!ctx) {
  983. pr_err("Invalid input argument\n");
  984. return 0;
  985. }
  986. c = &ctx->hw;
  987. ctl_top = SDE_REG_READ(c, CTL_LAYER(index));
  988. pr_debug("Ctl_layer value = 0x%x\n", ctl_top);
  989. return ctl_top;
  990. }
  991. static inline bool sde_hw_ctl_read_active_status(struct sde_hw_ctl *ctx,
  992. enum sde_hw_blk_type blk, int index)
  993. {
  994. struct sde_hw_blk_reg_map *c;
  995. if (!ctx) {
  996. pr_err("Invalid input argument\n");
  997. return 0;
  998. }
  999. c = &ctx->hw;
  1000. switch (blk) {
  1001. case SDE_HW_BLK_MERGE_3D:
  1002. return (SDE_REG_READ(c, CTL_MERGE_3D_ACTIVE) &
  1003. BIT(index - MERGE_3D_0)) ? true : false;
  1004. case SDE_HW_BLK_DSC:
  1005. return (SDE_REG_READ(c, CTL_DSC_ACTIVE) &
  1006. BIT(index - DSC_0)) ? true : false;
  1007. case SDE_HW_BLK_WB:
  1008. return (SDE_REG_READ(c, CTL_WB_ACTIVE) &
  1009. BIT(index - WB_0)) ? true : false;
  1010. case SDE_HW_BLK_CDM:
  1011. return (SDE_REG_READ(c, CTL_CDM_ACTIVE) &
  1012. BIT(index - CDM_0)) ? true : false;
  1013. case SDE_HW_BLK_INTF:
  1014. return (SDE_REG_READ(c, CTL_INTF_ACTIVE) &
  1015. BIT(index - INTF_0)) ? true : false;
  1016. default:
  1017. pr_err("unsupported blk %d\n", blk);
  1018. return false;
  1019. };
  1020. return false;
  1021. }
  1022. static int sde_hw_reg_dma_flush(struct sde_hw_ctl *ctx, bool blocking)
  1023. {
  1024. struct sde_hw_reg_dma_ops *ops = sde_reg_dma_get_ops();
  1025. if (!ctx)
  1026. return -EINVAL;
  1027. if (ops && ops->last_command)
  1028. return ops->last_command(ctx, DMA_CTL_QUEUE0,
  1029. (blocking ? REG_DMA_WAIT4_COMP : REG_DMA_NOWAIT));
  1030. return 0;
  1031. }
  1032. static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
  1033. unsigned long cap)
  1034. {
  1035. if (cap & BIT(SDE_CTL_ACTIVE_CFG)) {
  1036. ops->update_pending_flush =
  1037. sde_hw_ctl_update_pending_flush_v1;
  1038. ops->trigger_flush = sde_hw_ctl_trigger_flush_v1;
  1039. ops->setup_intf_cfg_v1 = sde_hw_ctl_intf_cfg_v1;
  1040. ops->update_intf_cfg = sde_hw_ctl_update_intf_cfg;
  1041. ops->update_bitmask = sde_hw_ctl_update_bitmask_v1;
  1042. ops->get_ctl_intf = sde_hw_ctl_get_intf_v1;
  1043. ops->reset_post_disable = sde_hw_ctl_reset_post_disable;
  1044. ops->get_scheduler_status = sde_hw_ctl_get_scheduler_status;
  1045. ops->read_active_status = sde_hw_ctl_read_active_status;
  1046. ops->set_active_pipes = sde_hw_ctl_set_fetch_pipe_active;
  1047. ops->get_active_pipes = sde_hw_ctl_get_active_fetch_pipes;
  1048. } else {
  1049. ops->update_pending_flush = sde_hw_ctl_update_pending_flush;
  1050. ops->trigger_flush = sde_hw_ctl_trigger_flush;
  1051. ops->setup_intf_cfg = sde_hw_ctl_intf_cfg;
  1052. ops->update_bitmask = sde_hw_ctl_update_bitmask;
  1053. ops->get_ctl_intf = sde_hw_ctl_get_intf;
  1054. }
  1055. ops->clear_pending_flush = sde_hw_ctl_clear_pending_flush;
  1056. ops->get_pending_flush = sde_hw_ctl_get_pending_flush;
  1057. ops->get_flush_register = sde_hw_ctl_get_flush_register;
  1058. ops->trigger_start = sde_hw_ctl_trigger_start;
  1059. ops->trigger_pending = sde_hw_ctl_trigger_pending;
  1060. ops->read_ctl_layers = sde_hw_ctl_read_ctl_layers;
  1061. ops->update_wb_cfg = sde_hw_ctl_update_wb_cfg;
  1062. ops->reset = sde_hw_ctl_reset_control;
  1063. ops->get_reset = sde_hw_ctl_get_reset_status;
  1064. ops->hard_reset = sde_hw_ctl_hard_reset;
  1065. ops->wait_reset_status = sde_hw_ctl_wait_reset_status;
  1066. ops->clear_all_blendstages = sde_hw_ctl_clear_all_blendstages;
  1067. ops->setup_blendstage = sde_hw_ctl_setup_blendstage;
  1068. ops->get_staged_sspp = sde_hw_ctl_get_staged_sspp;
  1069. ops->update_bitmask_sspp = sde_hw_ctl_update_bitmask_sspp;
  1070. ops->update_bitmask_mixer = sde_hw_ctl_update_bitmask_mixer;
  1071. ops->reg_dma_flush = sde_hw_reg_dma_flush;
  1072. ops->get_start_state = sde_hw_ctl_get_start_state;
  1073. if (cap & BIT(SDE_CTL_UNIFIED_DSPP_FLUSH)) {
  1074. ops->update_bitmask_dspp_subblk =
  1075. sde_hw_ctl_update_bitmask_dspp_subblk;
  1076. } else {
  1077. ops->update_bitmask_dspp = sde_hw_ctl_update_bitmask_dspp;
  1078. ops->update_bitmask_dspp_pavlut =
  1079. sde_hw_ctl_update_bitmask_dspp_pavlut;
  1080. }
  1081. if (cap & BIT(SDE_CTL_UIDLE))
  1082. ops->uidle_enable = sde_hw_ctl_uidle_enable;
  1083. };
  1084. static struct sde_hw_blk_ops sde_hw_ops = {
  1085. .start = NULL,
  1086. .stop = NULL,
  1087. };
  1088. struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx,
  1089. void __iomem *addr,
  1090. struct sde_mdss_cfg *m)
  1091. {
  1092. struct sde_hw_ctl *c;
  1093. struct sde_ctl_cfg *cfg;
  1094. int rc;
  1095. c = kzalloc(sizeof(*c), GFP_KERNEL);
  1096. if (!c)
  1097. return ERR_PTR(-ENOMEM);
  1098. cfg = _ctl_offset(idx, m, addr, &c->hw);
  1099. if (IS_ERR_OR_NULL(cfg)) {
  1100. kfree(c);
  1101. pr_err("failed to create sde_hw_ctl %d\n", idx);
  1102. return ERR_PTR(-EINVAL);
  1103. }
  1104. c->caps = cfg;
  1105. _setup_ctl_ops(&c->ops, c->caps->features);
  1106. c->idx = idx;
  1107. c->mixer_count = m->mixer_count;
  1108. c->mixer_hw_caps = m->mixer;
  1109. rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_CTL, idx, &sde_hw_ops);
  1110. if (rc) {
  1111. SDE_ERROR("failed to init hw blk %d\n", rc);
  1112. goto blk_init_error;
  1113. }
  1114. sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
  1115. c->hw.blk_off + c->hw.length, c->hw.xin_id);
  1116. return c;
  1117. blk_init_error:
  1118. kfree(c);
  1119. return ERR_PTR(rc);
  1120. }
  1121. void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx)
  1122. {
  1123. if (ctx)
  1124. sde_hw_blk_destroy(&ctx->base);
  1125. kfree(ctx);
  1126. }