sde_crtc.c 202 KB

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  1. /*
  2. * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/sort.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/ktime.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/drm_mode.h>
  24. #include <drm/drm_crtc.h>
  25. #include <drm/drm_probe_helper.h>
  26. #include <drm/drm_flip_work.h>
  27. #include "sde_kms.h"
  28. #include "sde_hw_lm.h"
  29. #include "sde_hw_ctl.h"
  30. #include "sde_crtc.h"
  31. #include "sde_plane.h"
  32. #include "sde_hw_util.h"
  33. #include "sde_hw_catalog.h"
  34. #include "sde_color_processing.h"
  35. #include "sde_encoder.h"
  36. #include "sde_connector.h"
  37. #include "sde_vbif.h"
  38. #include "sde_power_handle.h"
  39. #include "sde_core_perf.h"
  40. #include "sde_trace.h"
  41. #include "msm_drv.h"
  42. #include "sde_vm.h"
  43. #define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4)
  44. #define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2)
  45. struct sde_crtc_custom_events {
  46. u32 event;
  47. int (*func)(struct drm_crtc *crtc, bool en,
  48. struct sde_irq_callback *irq);
  49. };
  50. struct vblank_work {
  51. struct kthread_work work;
  52. int crtc_id;
  53. bool enable;
  54. struct msm_drm_private *priv;
  55. };
  56. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  57. bool en, struct sde_irq_callback *ad_irq);
  58. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  59. bool en, struct sde_irq_callback *idle_irq);
  60. static int sde_crtc_mmrm_interrupt_handler(struct drm_crtc *crtc_drm,
  61. bool en, struct sde_irq_callback *idle_irq);
  62. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  63. struct sde_irq_callback *noirq);
  64. static int _sde_crtc_set_noise_layer(struct sde_crtc *sde_crtc,
  65. struct sde_crtc_state *cstate,
  66. void __user *usr_ptr);
  67. static struct sde_crtc_custom_events custom_events[] = {
  68. {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt},
  69. {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler},
  70. {DRM_EVENT_IDLE_NOTIFY, sde_crtc_idle_interrupt_handler},
  71. {DRM_EVENT_HISTOGRAM, sde_cp_hist_interrupt},
  72. {DRM_EVENT_SDE_POWER, sde_crtc_pm_event_handler},
  73. {DRM_EVENT_LTM_HIST, sde_cp_ltm_hist_interrupt},
  74. {DRM_EVENT_LTM_WB_PB, sde_cp_ltm_wb_pb_interrupt},
  75. {DRM_EVENT_LTM_OFF, sde_cp_ltm_off_event_handler},
  76. {DRM_EVENT_MMRM_CB, sde_crtc_mmrm_interrupt_handler},
  77. };
  78. /* default input fence timeout, in ms */
  79. #define SDE_CRTC_INPUT_FENCE_TIMEOUT 10000
  80. /*
  81. * The default input fence timeout is 2 seconds while max allowed
  82. * range is 10 seconds. Any value above 10 seconds adds glitches beyond
  83. * tolerance limit.
  84. */
  85. #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
  86. /* layer mixer index on sde_crtc */
  87. #define LEFT_MIXER 0
  88. #define RIGHT_MIXER 1
  89. #define MISR_BUFF_SIZE 256
  90. /*
  91. * Time period for fps calculation in micro seconds.
  92. * Default value is set to 1 sec.
  93. */
  94. #define DEFAULT_FPS_PERIOD_1_SEC 1000000
  95. #define MAX_FPS_PERIOD_5_SECONDS 5000000
  96. #define MAX_FRAME_COUNT 1000
  97. #define MILI_TO_MICRO 1000
  98. #define SKIP_STAGING_PIPE_ZPOS 255
  99. static void sde_crtc_install_noise_layer_properties(struct sde_crtc *sde_crtc,
  100. struct sde_mdss_cfg *catalog, struct sde_kms_info *info);
  101. static void sde_cp_crtc_apply_noise(struct drm_crtc *crtc,
  102. struct drm_crtc_state *state);
  103. static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
  104. {
  105. struct msm_drm_private *priv;
  106. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  107. SDE_ERROR("invalid crtc\n");
  108. return NULL;
  109. }
  110. priv = crtc->dev->dev_private;
  111. if (!priv || !priv->kms) {
  112. SDE_ERROR("invalid kms\n");
  113. return NULL;
  114. }
  115. return to_sde_kms(priv->kms);
  116. }
  117. /**
  118. * sde_crtc_calc_fps() - Calculates fps value.
  119. * @sde_crtc : CRTC structure
  120. *
  121. * This function is called at frame done. It counts the number
  122. * of frames done for every 1 sec. Stores the value in measured_fps.
  123. * measured_fps value is 10 times the calculated fps value.
  124. * For example, measured_fps= 594 for calculated fps of 59.4
  125. */
  126. static void sde_crtc_calc_fps(struct sde_crtc *sde_crtc)
  127. {
  128. ktime_t current_time_us;
  129. u64 fps, diff_us;
  130. current_time_us = ktime_get();
  131. diff_us = (u64)ktime_us_delta(current_time_us,
  132. sde_crtc->fps_info.last_sampled_time_us);
  133. sde_crtc->fps_info.frame_count++;
  134. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  135. /* Multiplying with 10 to get fps in floating point */
  136. fps = ((u64)sde_crtc->fps_info.frame_count)
  137. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  138. do_div(fps, diff_us);
  139. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  140. SDE_DEBUG(" FPS for crtc%d is %d.%d\n",
  141. sde_crtc->base.base.id, (unsigned int)fps/10,
  142. (unsigned int)fps%10);
  143. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  144. sde_crtc->fps_info.frame_count = 0;
  145. }
  146. if (!sde_crtc->fps_info.time_buf)
  147. return;
  148. /**
  149. * Array indexing is based on sliding window algorithm.
  150. * sde_crtc->time_buf has a maximum capacity of MAX_FRAME_COUNT
  151. * time slots. As the count increases to MAX_FRAME_COUNT + 1, the
  152. * counter loops around and comes back to the first index to store
  153. * the next ktime.
  154. */
  155. sde_crtc->fps_info.time_buf[sde_crtc->fps_info.next_time_index++] =
  156. ktime_get();
  157. sde_crtc->fps_info.next_time_index %= MAX_FRAME_COUNT;
  158. }
  159. static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc)
  160. {
  161. if (!sde_crtc)
  162. return;
  163. }
  164. #ifdef CONFIG_DEBUG_FS
  165. static int _sde_debugfs_fps_status_show(struct seq_file *s, void *data)
  166. {
  167. struct sde_crtc *sde_crtc;
  168. u64 fps_int, fps_float;
  169. ktime_t current_time_us;
  170. u64 fps, diff_us;
  171. if (!s || !s->private) {
  172. SDE_ERROR("invalid input param(s)\n");
  173. return -EAGAIN;
  174. }
  175. sde_crtc = s->private;
  176. current_time_us = ktime_get();
  177. diff_us = (u64)ktime_us_delta(current_time_us,
  178. sde_crtc->fps_info.last_sampled_time_us);
  179. if (diff_us >= DEFAULT_FPS_PERIOD_1_SEC) {
  180. /* Multiplying with 10 to get fps in floating point */
  181. fps = ((u64)sde_crtc->fps_info.frame_count)
  182. * DEFAULT_FPS_PERIOD_1_SEC * 10;
  183. do_div(fps, diff_us);
  184. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  185. sde_crtc->fps_info.last_sampled_time_us = current_time_us;
  186. sde_crtc->fps_info.frame_count = 0;
  187. SDE_DEBUG("Measured FPS for crtc%d is %d.%d\n",
  188. sde_crtc->base.base.id, (unsigned int)fps/10,
  189. (unsigned int)fps%10);
  190. }
  191. fps_int = (unsigned int) sde_crtc->fps_info.measured_fps;
  192. fps_float = do_div(fps_int, 10);
  193. seq_printf(s, "fps: %llu.%llu\n", fps_int, fps_float);
  194. return 0;
  195. }
  196. static int _sde_debugfs_fps_status(struct inode *inode, struct file *file)
  197. {
  198. return single_open(file, _sde_debugfs_fps_status_show,
  199. inode->i_private);
  200. }
  201. #endif
  202. static ssize_t fps_periodicity_ms_store(struct device *device,
  203. struct device_attribute *attr, const char *buf, size_t count)
  204. {
  205. struct drm_crtc *crtc;
  206. struct sde_crtc *sde_crtc;
  207. int res;
  208. /* Base of the input */
  209. int cnt = 10;
  210. if (!device || !buf) {
  211. SDE_ERROR("invalid input param(s)\n");
  212. return -EAGAIN;
  213. }
  214. crtc = dev_get_drvdata(device);
  215. if (!crtc)
  216. return -EINVAL;
  217. sde_crtc = to_sde_crtc(crtc);
  218. res = kstrtou32(buf, cnt, &sde_crtc->fps_info.fps_periodic_duration);
  219. if (res < 0)
  220. return res;
  221. if (sde_crtc->fps_info.fps_periodic_duration <= 0)
  222. sde_crtc->fps_info.fps_periodic_duration =
  223. DEFAULT_FPS_PERIOD_1_SEC;
  224. else if ((sde_crtc->fps_info.fps_periodic_duration) * MILI_TO_MICRO >
  225. MAX_FPS_PERIOD_5_SECONDS)
  226. sde_crtc->fps_info.fps_periodic_duration =
  227. MAX_FPS_PERIOD_5_SECONDS;
  228. else
  229. sde_crtc->fps_info.fps_periodic_duration *= MILI_TO_MICRO;
  230. return count;
  231. }
  232. static ssize_t fps_periodicity_ms_show(struct device *device,
  233. struct device_attribute *attr, char *buf)
  234. {
  235. struct drm_crtc *crtc;
  236. struct sde_crtc *sde_crtc;
  237. if (!device || !buf) {
  238. SDE_ERROR("invalid input param(s)\n");
  239. return -EAGAIN;
  240. }
  241. crtc = dev_get_drvdata(device);
  242. if (!crtc)
  243. return -EINVAL;
  244. sde_crtc = to_sde_crtc(crtc);
  245. return scnprintf(buf, PAGE_SIZE, "%d\n",
  246. (sde_crtc->fps_info.fps_periodic_duration)/MILI_TO_MICRO);
  247. }
  248. static ssize_t measured_fps_show(struct device *device,
  249. struct device_attribute *attr, char *buf)
  250. {
  251. struct drm_crtc *crtc;
  252. struct sde_crtc *sde_crtc;
  253. uint64_t fps_int, fps_decimal;
  254. u64 fps = 0, frame_count = 0;
  255. ktime_t current_time;
  256. int i = 0, current_time_index;
  257. u64 diff_us;
  258. if (!device || !buf) {
  259. SDE_ERROR("invalid input param(s)\n");
  260. return -EAGAIN;
  261. }
  262. crtc = dev_get_drvdata(device);
  263. if (!crtc) {
  264. scnprintf(buf, PAGE_SIZE, "fps information not available");
  265. return -EINVAL;
  266. }
  267. sde_crtc = to_sde_crtc(crtc);
  268. if (!sde_crtc->fps_info.time_buf) {
  269. scnprintf(buf, PAGE_SIZE,
  270. "timebuf null - fps information not available");
  271. return -EINVAL;
  272. }
  273. /**
  274. * Whenever the time_index counter comes to zero upon decrementing,
  275. * it is set to the last index since it is the next index that we
  276. * should check for calculating the buftime.
  277. */
  278. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  279. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  280. current_time = ktime_get();
  281. for (i = 0; i < MAX_FRAME_COUNT; i++) {
  282. u64 ptime = (u64)ktime_to_us(current_time);
  283. u64 buftime = (u64)ktime_to_us(
  284. sde_crtc->fps_info.time_buf[current_time_index]);
  285. diff_us = (u64)ktime_us_delta(current_time,
  286. sde_crtc->fps_info.time_buf[current_time_index]);
  287. if (ptime > buftime && diff_us >= (u64)
  288. sde_crtc->fps_info.fps_periodic_duration) {
  289. /* Multiplying with 10 to get fps in floating point */
  290. fps = frame_count * DEFAULT_FPS_PERIOD_1_SEC * 10;
  291. do_div(fps, diff_us);
  292. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  293. SDE_DEBUG("measured fps: %d\n",
  294. sde_crtc->fps_info.measured_fps);
  295. break;
  296. }
  297. current_time_index = (current_time_index == 0) ?
  298. (MAX_FRAME_COUNT - 1) : (current_time_index - 1);
  299. SDE_DEBUG("current time index: %d\n", current_time_index);
  300. frame_count++;
  301. }
  302. if (i == MAX_FRAME_COUNT) {
  303. current_time_index = (sde_crtc->fps_info.next_time_index == 0) ?
  304. MAX_FRAME_COUNT - 1 : (sde_crtc->fps_info.next_time_index - 1);
  305. diff_us = (u64)ktime_us_delta(current_time,
  306. sde_crtc->fps_info.time_buf[current_time_index]);
  307. if (diff_us >= sde_crtc->fps_info.fps_periodic_duration) {
  308. /* Multiplying with 10 to get fps in floating point */
  309. fps = (frame_count) * DEFAULT_FPS_PERIOD_1_SEC * 10;
  310. do_div(fps, diff_us);
  311. sde_crtc->fps_info.measured_fps = (unsigned int)fps;
  312. }
  313. }
  314. fps_int = (uint64_t) sde_crtc->fps_info.measured_fps;
  315. fps_decimal = do_div(fps_int, 10);
  316. return scnprintf(buf, PAGE_SIZE,
  317. "fps: %lld.%lld duration:%d frame_count:%lld\n", fps_int, fps_decimal,
  318. sde_crtc->fps_info.fps_periodic_duration, frame_count);
  319. }
  320. static ssize_t vsync_event_show(struct device *device,
  321. struct device_attribute *attr, char *buf)
  322. {
  323. struct drm_crtc *crtc;
  324. struct sde_crtc *sde_crtc;
  325. struct drm_encoder *encoder;
  326. int avr_status = -EPIPE;
  327. if (!device || !buf) {
  328. SDE_ERROR("invalid input param(s)\n");
  329. return -EAGAIN;
  330. }
  331. crtc = dev_get_drvdata(device);
  332. sde_crtc = to_sde_crtc(crtc);
  333. mutex_lock(&sde_crtc->crtc_lock);
  334. if (sde_crtc->enabled) {
  335. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
  336. if (sde_encoder_in_clone_mode(encoder))
  337. continue;
  338. avr_status = sde_encoder_get_avr_status(encoder);
  339. break;
  340. }
  341. }
  342. mutex_unlock(&sde_crtc->crtc_lock);
  343. return scnprintf(buf, PAGE_SIZE, "VSYNC=%llu\nAVR_STATUS=%d\n",
  344. ktime_to_ns(sde_crtc->vblank_last_cb_time), avr_status);
  345. }
  346. static ssize_t retire_frame_event_show(struct device *device,
  347. struct device_attribute *attr, char *buf)
  348. {
  349. struct drm_crtc *crtc;
  350. struct sde_crtc *sde_crtc;
  351. if (!device || !buf) {
  352. SDE_ERROR("invalid input param(s)\n");
  353. return -EAGAIN;
  354. }
  355. crtc = dev_get_drvdata(device);
  356. sde_crtc = to_sde_crtc(crtc);
  357. return scnprintf(buf, PAGE_SIZE, "RETIRE_FRAME_TIME=%llu\n",
  358. ktime_to_ns(sde_crtc->retire_frame_event_time));
  359. }
  360. static DEVICE_ATTR_RO(vsync_event);
  361. static DEVICE_ATTR_RO(measured_fps);
  362. static DEVICE_ATTR_RW(fps_periodicity_ms);
  363. static DEVICE_ATTR_RO(retire_frame_event);
  364. static struct attribute *sde_crtc_dev_attrs[] = {
  365. &dev_attr_vsync_event.attr,
  366. &dev_attr_measured_fps.attr,
  367. &dev_attr_fps_periodicity_ms.attr,
  368. &dev_attr_retire_frame_event.attr,
  369. NULL
  370. };
  371. static const struct attribute_group sde_crtc_attr_group = {
  372. .attrs = sde_crtc_dev_attrs,
  373. };
  374. static const struct attribute_group *sde_crtc_attr_groups[] = {
  375. &sde_crtc_attr_group,
  376. NULL,
  377. };
  378. static void sde_crtc_event_notify(struct drm_crtc *crtc, uint32_t type, uint32_t len, uint64_t val)
  379. {
  380. struct drm_event event;
  381. if (!crtc) {
  382. SDE_ERROR("invalid crtc\n");
  383. return;
  384. }
  385. event.type = type;
  386. event.length = len;
  387. msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, (u8 *)&val);
  388. SDE_EVT32(DRMID(crtc), type, len, val >> 32, val & 0xFFFFFFFF);
  389. SDE_DEBUG("crtc:%d event(%d) value(%llu) notified\n", DRMID(crtc), type, val);
  390. }
  391. static void sde_crtc_destroy(struct drm_crtc *crtc)
  392. {
  393. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  394. SDE_DEBUG("\n");
  395. if (!crtc)
  396. return;
  397. if (sde_crtc->vsync_event_sf)
  398. sysfs_put(sde_crtc->vsync_event_sf);
  399. if (sde_crtc->retire_frame_event_sf)
  400. sysfs_put(sde_crtc->retire_frame_event_sf);
  401. if (sde_crtc->sysfs_dev)
  402. device_unregister(sde_crtc->sysfs_dev);
  403. if (sde_crtc->blob_info)
  404. drm_property_blob_put(sde_crtc->blob_info);
  405. msm_property_destroy(&sde_crtc->property_info);
  406. sde_cp_crtc_destroy_properties(crtc);
  407. sde_fence_deinit(sde_crtc->output_fence);
  408. _sde_crtc_deinit_events(sde_crtc);
  409. drm_crtc_cleanup(crtc);
  410. mutex_destroy(&sde_crtc->crtc_lock);
  411. kfree(sde_crtc);
  412. }
  413. struct msm_display_mode *sde_crtc_get_msm_mode(struct drm_crtc_state *c_state)
  414. {
  415. struct drm_connector *connector;
  416. struct drm_encoder *encoder;
  417. struct sde_connector_state *conn_state;
  418. bool encoder_valid = false;
  419. drm_for_each_encoder_mask(encoder, c_state->crtc->dev,
  420. c_state->encoder_mask) {
  421. if (!sde_encoder_in_clone_mode(encoder)) {
  422. encoder_valid = true;
  423. break;
  424. }
  425. }
  426. if (!encoder_valid)
  427. return NULL;
  428. connector = sde_encoder_get_connector(c_state->crtc->dev, encoder);
  429. if (!connector)
  430. return NULL;
  431. conn_state = to_sde_connector_state(connector->state);
  432. if (!conn_state)
  433. return NULL;
  434. return &conn_state->msm_mode;
  435. }
  436. static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
  437. const struct drm_display_mode *mode,
  438. struct drm_display_mode *adjusted_mode)
  439. {
  440. struct msm_display_mode *msm_mode;
  441. struct drm_crtc_state *c_state;
  442. struct drm_connector *connector;
  443. struct drm_encoder *encoder;
  444. struct drm_connector_state *new_conn_state;
  445. struct sde_connector_state *c_conn_state = NULL;
  446. bool encoder_valid = false;
  447. int i;
  448. SDE_DEBUG("\n");
  449. c_state = container_of(adjusted_mode, struct drm_crtc_state,
  450. adjusted_mode);
  451. drm_for_each_encoder_mask(encoder, c_state->crtc->dev,
  452. c_state->encoder_mask) {
  453. if (!sde_encoder_in_clone_mode(encoder)) {
  454. encoder_valid = true;
  455. break;
  456. }
  457. }
  458. if (!encoder_valid) {
  459. SDE_ERROR("encoder not found\n");
  460. return true;
  461. }
  462. for_each_new_connector_in_state(c_state->state, connector,
  463. new_conn_state, i) {
  464. if (new_conn_state->best_encoder == encoder) {
  465. c_conn_state = to_sde_connector_state(new_conn_state);
  466. break;
  467. }
  468. }
  469. if (!c_conn_state) {
  470. SDE_ERROR("could not get connector state\n");
  471. return true;
  472. }
  473. msm_mode = &c_conn_state->msm_mode;
  474. if ((msm_is_mode_seamless(msm_mode) ||
  475. (msm_is_mode_seamless_vrr(msm_mode) ||
  476. msm_is_mode_seamless_dyn_clk(msm_mode))) &&
  477. (!crtc->enabled)) {
  478. SDE_ERROR("crtc state prevents seamless transition\n");
  479. return false;
  480. }
  481. return true;
  482. }
  483. static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
  484. struct sde_plane_state *pstate, struct sde_format *format)
  485. {
  486. uint32_t blend_op, fg_alpha, bg_alpha;
  487. uint32_t blend_type;
  488. struct sde_hw_mixer *lm = mixer->hw_lm;
  489. /* default to opaque blending */
  490. fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
  491. bg_alpha = 0xFF - fg_alpha;
  492. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
  493. blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
  494. SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
  495. switch (blend_type) {
  496. case SDE_DRM_BLEND_OP_OPAQUE:
  497. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  498. SDE_BLEND_BG_ALPHA_BG_CONST;
  499. break;
  500. case SDE_DRM_BLEND_OP_PREMULTIPLIED:
  501. if (format->alpha_enable) {
  502. blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
  503. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  504. if (fg_alpha != 0xff) {
  505. bg_alpha = fg_alpha;
  506. blend_op |= SDE_BLEND_BG_MOD_ALPHA |
  507. SDE_BLEND_BG_INV_MOD_ALPHA;
  508. } else {
  509. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  510. }
  511. }
  512. break;
  513. case SDE_DRM_BLEND_OP_COVERAGE:
  514. if (format->alpha_enable) {
  515. blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
  516. SDE_BLEND_BG_ALPHA_FG_PIXEL;
  517. if (fg_alpha != 0xff) {
  518. bg_alpha = fg_alpha;
  519. blend_op |= SDE_BLEND_FG_MOD_ALPHA |
  520. SDE_BLEND_BG_MOD_ALPHA |
  521. SDE_BLEND_BG_INV_MOD_ALPHA;
  522. } else {
  523. blend_op |= SDE_BLEND_BG_INV_ALPHA;
  524. }
  525. }
  526. break;
  527. default:
  528. /* do nothing */
  529. break;
  530. }
  531. lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
  532. bg_alpha, blend_op);
  533. SDE_DEBUG(
  534. "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
  535. (char *) &format->base.pixel_format,
  536. format->alpha_enable, fg_alpha, bg_alpha, blend_op);
  537. }
  538. static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
  539. struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer,
  540. struct sde_hw_dim_layer *dim_layer)
  541. {
  542. struct sde_crtc_state *cstate;
  543. struct sde_hw_mixer *lm;
  544. struct sde_hw_dim_layer split_dim_layer;
  545. int i;
  546. if (!dim_layer->rect.w || !dim_layer->rect.h) {
  547. SDE_DEBUG("empty dim_layer\n");
  548. return;
  549. }
  550. cstate = to_sde_crtc_state(crtc->state);
  551. SDE_DEBUG("dim_layer - flags:%d, stage:%d\n",
  552. dim_layer->flags, dim_layer->stage);
  553. split_dim_layer.stage = dim_layer->stage;
  554. split_dim_layer.color_fill = dim_layer->color_fill;
  555. /*
  556. * traverse through the layer mixers attached to crtc and find the
  557. * intersecting dim layer rect in each LM and program accordingly.
  558. */
  559. for (i = 0; i < sde_crtc->num_mixers; i++) {
  560. split_dim_layer.flags = dim_layer->flags;
  561. sde_kms_rect_intersect(&cstate->lm_roi[i], &dim_layer->rect,
  562. &split_dim_layer.rect);
  563. if (sde_kms_rect_is_null(&split_dim_layer.rect)) {
  564. /*
  565. * no extra programming required for non-intersecting
  566. * layer mixers with INCLUSIVE dim layer
  567. */
  568. if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE)
  569. continue;
  570. /*
  571. * program the other non-intersecting layer mixers with
  572. * INCLUSIVE dim layer of full size for uniformity
  573. * with EXCLUSIVE dim layer config.
  574. */
  575. split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE;
  576. split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE;
  577. memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i],
  578. sizeof(split_dim_layer.rect));
  579. } else {
  580. split_dim_layer.rect.x =
  581. split_dim_layer.rect.x -
  582. cstate->lm_roi[i].x;
  583. split_dim_layer.rect.y =
  584. split_dim_layer.rect.y -
  585. cstate->lm_roi[i].y;
  586. }
  587. SDE_EVT32(DRMID(crtc), dim_layer->stage,
  588. cstate->lm_roi[i].x,
  589. cstate->lm_roi[i].y,
  590. cstate->lm_roi[i].w,
  591. cstate->lm_roi[i].h,
  592. dim_layer->rect.x,
  593. dim_layer->rect.y,
  594. dim_layer->rect.w,
  595. dim_layer->rect.h,
  596. split_dim_layer.rect.x,
  597. split_dim_layer.rect.y,
  598. split_dim_layer.rect.w,
  599. split_dim_layer.rect.h);
  600. SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n",
  601. i, split_dim_layer.rect.x, split_dim_layer.rect.y,
  602. split_dim_layer.rect.w, split_dim_layer.rect.h);
  603. lm = mixer[i].hw_lm;
  604. mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
  605. lm->ops.setup_dim_layer(lm, &split_dim_layer);
  606. }
  607. }
  608. void sde_crtc_get_crtc_roi(struct drm_crtc_state *state,
  609. const struct sde_rect **crtc_roi)
  610. {
  611. struct sde_crtc_state *crtc_state;
  612. if (!state || !crtc_roi)
  613. return;
  614. crtc_state = to_sde_crtc_state(state);
  615. *crtc_roi = &crtc_state->crtc_roi;
  616. }
  617. bool sde_crtc_is_crtc_roi_dirty(struct drm_crtc_state *state)
  618. {
  619. struct sde_crtc_state *cstate;
  620. struct sde_crtc *sde_crtc;
  621. if (!state || !state->crtc)
  622. return false;
  623. sde_crtc = to_sde_crtc(state->crtc);
  624. cstate = to_sde_crtc_state(state);
  625. return msm_property_is_dirty(&sde_crtc->property_info,
  626. &cstate->property_state, CRTC_PROP_ROI_V1);
  627. }
  628. static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state,
  629. void __user *usr_ptr)
  630. {
  631. struct drm_crtc *crtc;
  632. struct sde_crtc_state *cstate;
  633. struct sde_drm_roi_v1 roi_v1;
  634. int i;
  635. if (!state) {
  636. SDE_ERROR("invalid args\n");
  637. return -EINVAL;
  638. }
  639. cstate = to_sde_crtc_state(state);
  640. crtc = cstate->base.crtc;
  641. memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list));
  642. if (!usr_ptr) {
  643. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  644. return 0;
  645. }
  646. if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) {
  647. SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc));
  648. return -EINVAL;
  649. }
  650. SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects);
  651. if (roi_v1.num_rects == 0) {
  652. SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc));
  653. return 0;
  654. }
  655. if (roi_v1.num_rects > SDE_MAX_ROI_V1) {
  656. SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc),
  657. roi_v1.num_rects);
  658. return -EINVAL;
  659. }
  660. cstate->user_roi_list.num_rects = roi_v1.num_rects;
  661. for (i = 0; i < roi_v1.num_rects; ++i) {
  662. cstate->user_roi_list.roi[i] = roi_v1.roi[i];
  663. SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n",
  664. DRMID(crtc), i,
  665. cstate->user_roi_list.roi[i].x1,
  666. cstate->user_roi_list.roi[i].y1,
  667. cstate->user_roi_list.roi[i].x2,
  668. cstate->user_roi_list.roi[i].y2);
  669. SDE_EVT32_VERBOSE(DRMID(crtc),
  670. cstate->user_roi_list.roi[i].x1,
  671. cstate->user_roi_list.roi[i].y1,
  672. cstate->user_roi_list.roi[i].x2,
  673. cstate->user_roi_list.roi[i].y2);
  674. }
  675. return 0;
  676. }
  677. static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc,
  678. struct drm_crtc_state *state)
  679. {
  680. struct drm_connector *conn;
  681. struct drm_connector_state *conn_state;
  682. struct sde_crtc *sde_crtc;
  683. struct sde_crtc_state *crtc_state;
  684. struct sde_rect *crtc_roi;
  685. struct msm_mode_info mode_info;
  686. int i = 0;
  687. int rc;
  688. bool is_crtc_roi_dirty;
  689. bool is_conn_roi_dirty;
  690. if (!crtc || !state)
  691. return -EINVAL;
  692. sde_crtc = to_sde_crtc(crtc);
  693. crtc_state = to_sde_crtc_state(state);
  694. crtc_roi = &crtc_state->crtc_roi;
  695. is_crtc_roi_dirty = sde_crtc_is_crtc_roi_dirty(state);
  696. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  697. struct sde_connector *sde_conn;
  698. struct sde_connector_state *sde_conn_state;
  699. struct sde_rect conn_roi;
  700. if (!conn_state || conn_state->crtc != crtc)
  701. continue;
  702. rc = sde_connector_state_get_mode_info(conn_state, &mode_info);
  703. if (rc) {
  704. SDE_ERROR("failed to get mode info\n");
  705. return -EINVAL;
  706. }
  707. sde_conn = to_sde_connector(conn_state->connector);
  708. sde_conn_state = to_sde_connector_state(conn_state);
  709. is_conn_roi_dirty = msm_property_is_dirty(&sde_conn->property_info,
  710. &sde_conn_state->property_state,
  711. CONNECTOR_PROP_ROI_V1);
  712. /*
  713. * Check against CRTC ROI and Connector ROI not being updated together.
  714. * This restriction should be relaxed when Connector ROI scaling is
  715. * supported and while in clone mode.
  716. */
  717. if (!sde_encoder_in_clone_mode(sde_conn->encoder) &&
  718. is_conn_roi_dirty != is_crtc_roi_dirty) {
  719. SDE_ERROR("connector/crtc rois not updated together\n");
  720. return -EINVAL;
  721. }
  722. if (!mode_info.roi_caps.enabled)
  723. continue;
  724. /*
  725. * current driver only supports same connector and crtc size,
  726. * but if support for different sizes is added, driver needs
  727. * to check the connector roi here to make sure is full screen
  728. * for dsc 3d-mux topology that doesn't support partial update.
  729. */
  730. if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list,
  731. sizeof(crtc_state->user_roi_list))) {
  732. SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n",
  733. sde_crtc->name);
  734. return -EINVAL;
  735. }
  736. sde_kms_rect_merge_rectangles(&sde_conn_state->rois, &conn_roi);
  737. SDE_DEBUG("conn_roi x:%u, y:%u, w:%u, h:%u\n",
  738. conn_roi.x, conn_roi.y,
  739. conn_roi.w, conn_roi.h);
  740. SDE_EVT32_VERBOSE(DRMID(crtc), DRMID(conn),
  741. conn_roi.x, conn_roi.y,
  742. conn_roi.w, conn_roi.h);
  743. }
  744. sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi);
  745. /* clear the ROI to null if it matches full screen anyways */
  746. if (crtc_roi->x == 0 && crtc_roi->y == 0 &&
  747. crtc_roi->w == state->adjusted_mode.hdisplay &&
  748. crtc_roi->h == state->adjusted_mode.vdisplay)
  749. memset(crtc_roi, 0, sizeof(*crtc_roi));
  750. SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name,
  751. crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h);
  752. SDE_EVT32_VERBOSE(DRMID(crtc), crtc_roi->x, crtc_roi->y, crtc_roi->w,
  753. crtc_roi->h);
  754. return 0;
  755. }
  756. static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc,
  757. struct drm_crtc_state *state)
  758. {
  759. struct sde_crtc *sde_crtc;
  760. struct sde_crtc_state *crtc_state;
  761. struct drm_connector *conn;
  762. struct drm_connector_state *conn_state;
  763. int i;
  764. if (!crtc || !state)
  765. return -EINVAL;
  766. sde_crtc = to_sde_crtc(crtc);
  767. crtc_state = to_sde_crtc_state(state);
  768. if (sde_kms_rect_is_null(&crtc_state->crtc_roi))
  769. return 0;
  770. /* partial update active, check if autorefresh is also requested */
  771. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  772. uint64_t autorefresh;
  773. if (!conn_state || conn_state->crtc != crtc)
  774. continue;
  775. autorefresh = sde_connector_get_property(conn_state,
  776. CONNECTOR_PROP_AUTOREFRESH);
  777. if (autorefresh) {
  778. SDE_ERROR(
  779. "%s: autorefresh & partial crtc roi incompatible %llu\n",
  780. sde_crtc->name, autorefresh);
  781. return -EINVAL;
  782. }
  783. }
  784. return 0;
  785. }
  786. static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc,
  787. struct drm_crtc_state *state, int lm_idx)
  788. {
  789. struct sde_kms *sde_kms;
  790. struct sde_crtc *sde_crtc;
  791. struct sde_crtc_state *crtc_state;
  792. const struct sde_rect *crtc_roi;
  793. const struct sde_rect *lm_bounds;
  794. struct sde_rect *lm_roi;
  795. if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds))
  796. return -EINVAL;
  797. sde_kms = _sde_crtc_get_kms(crtc);
  798. if (!sde_kms || !sde_kms->catalog) {
  799. SDE_ERROR("invalid parameters\n");
  800. return -EINVAL;
  801. }
  802. sde_crtc = to_sde_crtc(crtc);
  803. crtc_state = to_sde_crtc_state(state);
  804. crtc_roi = &crtc_state->crtc_roi;
  805. lm_bounds = &crtc_state->lm_bounds[lm_idx];
  806. lm_roi = &crtc_state->lm_roi[lm_idx];
  807. if (sde_kms_rect_is_null(crtc_roi))
  808. memcpy(lm_roi, lm_bounds, sizeof(*lm_roi));
  809. else
  810. sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi);
  811. SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx,
  812. lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h);
  813. /*
  814. * partial update is not supported with 3dmux dsc or dest scaler.
  815. * hence, crtc roi must match the mixer dimensions.
  816. */
  817. if (crtc_state->num_ds_enabled ||
  818. sde_rm_topology_is_group(&sde_kms->rm, state,
  819. SDE_RM_TOPOLOGY_GROUP_3DMERGE_DSC)) {
  820. if (memcmp(lm_roi, lm_bounds, sizeof(struct sde_rect))) {
  821. SDE_ERROR("Unsupported: Dest scaler/3d mux DSC + PU\n");
  822. return -EINVAL;
  823. }
  824. }
  825. /* if any dimension is zero, clear all dimensions for clarity */
  826. if (sde_kms_rect_is_null(lm_roi))
  827. memset(lm_roi, 0, sizeof(*lm_roi));
  828. return 0;
  829. }
  830. static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc,
  831. struct drm_crtc_state *state)
  832. {
  833. struct sde_crtc *sde_crtc;
  834. struct sde_crtc_state *crtc_state;
  835. u32 disp_bitmask = 0;
  836. int i;
  837. if (!crtc || !state) {
  838. pr_err("Invalid crtc or state\n");
  839. return 0;
  840. }
  841. sde_crtc = to_sde_crtc(crtc);
  842. crtc_state = to_sde_crtc_state(state);
  843. /* pingpong split: one ROI, one LM, two physical displays */
  844. if (crtc_state->is_ppsplit) {
  845. u32 lm_split_width = crtc_state->lm_bounds[0].w / 2;
  846. struct sde_rect *roi = &crtc_state->lm_roi[0];
  847. if (sde_kms_rect_is_null(roi))
  848. disp_bitmask = 0;
  849. else if ((u32)roi->x + (u32)roi->w <= lm_split_width)
  850. disp_bitmask = BIT(0); /* left only */
  851. else if (roi->x >= lm_split_width)
  852. disp_bitmask = BIT(1); /* right only */
  853. else
  854. disp_bitmask = BIT(0) | BIT(1); /* left and right */
  855. } else if (sde_crtc->mixers_swapped) {
  856. disp_bitmask = BIT(0);
  857. } else {
  858. for (i = 0; i < sde_crtc->num_mixers; i++) {
  859. if (!sde_kms_rect_is_null(
  860. &crtc_state->lm_roi[i]))
  861. disp_bitmask |= BIT(i);
  862. }
  863. }
  864. SDE_DEBUG("affected displays 0x%x\n", disp_bitmask);
  865. return disp_bitmask;
  866. }
  867. static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc,
  868. struct drm_crtc_state *state)
  869. {
  870. struct sde_crtc *sde_crtc;
  871. struct sde_crtc_state *crtc_state;
  872. const struct sde_rect *roi[MAX_MIXERS_PER_CRTC];
  873. if (!crtc || !state)
  874. return -EINVAL;
  875. sde_crtc = to_sde_crtc(crtc);
  876. crtc_state = to_sde_crtc_state(state);
  877. if (sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  878. SDE_ERROR("%s: unsupported number of mixers: %d\n",
  879. sde_crtc->name, sde_crtc->num_mixers);
  880. return -EINVAL;
  881. }
  882. /*
  883. * If using pingpong split: one ROI, one LM, two physical displays
  884. * then the ROI must be centered on the panel split boundary and
  885. * be of equal width across the split.
  886. */
  887. if (crtc_state->is_ppsplit) {
  888. u16 panel_split_width;
  889. u32 display_mask;
  890. roi[0] = &crtc_state->lm_roi[0];
  891. if (sde_kms_rect_is_null(roi[0]))
  892. return 0;
  893. display_mask = _sde_crtc_get_displays_affected(crtc, state);
  894. if (display_mask != (BIT(0) | BIT(1)))
  895. return 0;
  896. panel_split_width = crtc_state->lm_bounds[0].w / 2;
  897. if (roi[0]->x + roi[0]->w / 2 != panel_split_width) {
  898. SDE_ERROR("%s: roi x %d w %d split %d\n",
  899. sde_crtc->name, roi[0]->x, roi[0]->w,
  900. panel_split_width);
  901. return -EINVAL;
  902. }
  903. return 0;
  904. }
  905. /*
  906. * On certain HW, if using 2 LM, ROIs must be split evenly between the
  907. * LMs and be of equal width.
  908. */
  909. if (sde_crtc->num_mixers < CRTC_DUAL_MIXERS_ONLY)
  910. return 0;
  911. roi[0] = &crtc_state->lm_roi[0];
  912. roi[1] = &crtc_state->lm_roi[1];
  913. /* if one of the roi is null it's a left/right-only update */
  914. if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1]))
  915. return 0;
  916. /* check lm rois are equal width & first roi ends at 2nd roi */
  917. if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) {
  918. SDE_ERROR(
  919. "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n",
  920. sde_crtc->name, roi[0]->x, roi[0]->w,
  921. roi[1]->x, roi[1]->w);
  922. return -EINVAL;
  923. }
  924. return 0;
  925. }
  926. static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc,
  927. struct drm_crtc_state *state)
  928. {
  929. struct sde_crtc *sde_crtc;
  930. struct sde_crtc_state *crtc_state;
  931. const struct sde_rect *crtc_roi;
  932. const struct drm_plane_state *pstate;
  933. struct drm_plane *plane;
  934. if (!crtc || !state)
  935. return -EINVAL;
  936. /*
  937. * Reject commit if a Plane CRTC destination coordinates fall outside
  938. * the partial CRTC ROI. LM output is determined via connector ROIs,
  939. * if they are specified, not Plane CRTC ROIs.
  940. */
  941. sde_crtc = to_sde_crtc(crtc);
  942. crtc_state = to_sde_crtc_state(state);
  943. crtc_roi = &crtc_state->crtc_roi;
  944. if (sde_kms_rect_is_null(crtc_roi))
  945. return 0;
  946. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  947. struct sde_rect plane_roi, intersection;
  948. if (IS_ERR_OR_NULL(pstate)) {
  949. int rc = PTR_ERR(pstate);
  950. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  951. sde_crtc->name, plane->base.id, rc);
  952. return rc;
  953. }
  954. plane_roi.x = pstate->crtc_x;
  955. plane_roi.y = pstate->crtc_y;
  956. plane_roi.w = pstate->crtc_w;
  957. plane_roi.h = pstate->crtc_h;
  958. sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection);
  959. if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) {
  960. SDE_ERROR(
  961. "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n",
  962. sde_crtc->name, plane->base.id,
  963. plane_roi.x, plane_roi.y,
  964. plane_roi.w, plane_roi.h,
  965. crtc_roi->x, crtc_roi->y,
  966. crtc_roi->w, crtc_roi->h);
  967. return -E2BIG;
  968. }
  969. }
  970. return 0;
  971. }
  972. static int _sde_crtc_check_rois(struct drm_crtc *crtc,
  973. struct drm_crtc_state *state)
  974. {
  975. struct sde_crtc *sde_crtc;
  976. struct sde_crtc_state *sde_crtc_state;
  977. struct msm_mode_info mode_info;
  978. int rc, lm_idx, i;
  979. if (!crtc || !state)
  980. return -EINVAL;
  981. memset(&mode_info, 0, sizeof(mode_info));
  982. sde_crtc = to_sde_crtc(crtc);
  983. sde_crtc_state = to_sde_crtc_state(state);
  984. /*
  985. * check connector array cached at modeset time since incoming atomic
  986. * state may not include any connectors if they aren't modified
  987. */
  988. for (i = 0; i < sde_crtc_state->num_connectors; i++) {
  989. struct drm_connector *conn = sde_crtc_state->connectors[i];
  990. if (!conn || !conn->state)
  991. continue;
  992. rc = sde_connector_state_get_mode_info(conn->state, &mode_info);
  993. if (rc) {
  994. SDE_ERROR("failed to get mode info\n");
  995. return -EINVAL;
  996. }
  997. if (!mode_info.roi_caps.enabled)
  998. continue;
  999. if (sde_crtc_state->user_roi_list.num_rects >
  1000. mode_info.roi_caps.num_roi) {
  1001. SDE_ERROR("roi count is exceeding limit, %d > %d\n",
  1002. sde_crtc_state->user_roi_list.num_rects,
  1003. mode_info.roi_caps.num_roi);
  1004. return -E2BIG;
  1005. }
  1006. rc = _sde_crtc_set_crtc_roi(crtc, state);
  1007. if (rc)
  1008. return rc;
  1009. rc = _sde_crtc_check_autorefresh(crtc, state);
  1010. if (rc)
  1011. return rc;
  1012. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  1013. rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx);
  1014. if (rc)
  1015. return rc;
  1016. }
  1017. rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state);
  1018. if (rc)
  1019. return rc;
  1020. rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state);
  1021. if (rc)
  1022. return rc;
  1023. }
  1024. return 0;
  1025. }
  1026. static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc)
  1027. {
  1028. struct sde_crtc *sde_crtc;
  1029. struct sde_crtc_state *cstate;
  1030. const struct sde_rect *lm_roi;
  1031. struct sde_hw_mixer *hw_lm;
  1032. bool right_mixer = false;
  1033. bool lm_updated = false;
  1034. int lm_idx;
  1035. if (!crtc)
  1036. return;
  1037. sde_crtc = to_sde_crtc(crtc);
  1038. cstate = to_sde_crtc_state(crtc->state);
  1039. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  1040. struct sde_hw_mixer_cfg cfg;
  1041. lm_roi = &cstate->lm_roi[lm_idx];
  1042. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  1043. if (!sde_crtc->mixers_swapped)
  1044. right_mixer = lm_idx % MAX_MIXERS_PER_LAYOUT;
  1045. if (lm_roi->w != hw_lm->cfg.out_width ||
  1046. lm_roi->h != hw_lm->cfg.out_height ||
  1047. right_mixer != hw_lm->cfg.right_mixer) {
  1048. hw_lm->cfg.out_width = lm_roi->w;
  1049. hw_lm->cfg.out_height = lm_roi->h;
  1050. hw_lm->cfg.right_mixer = right_mixer;
  1051. cfg.out_width = lm_roi->w;
  1052. cfg.out_height = lm_roi->h;
  1053. cfg.right_mixer = right_mixer;
  1054. cfg.flags = 0;
  1055. hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
  1056. lm_updated = true;
  1057. }
  1058. SDE_EVT32(DRMID(crtc), lm_idx, lm_roi->x, lm_roi->y, lm_roi->w,
  1059. lm_roi->h, right_mixer, lm_updated);
  1060. }
  1061. if (lm_updated)
  1062. sde_cp_crtc_res_change(crtc);
  1063. }
  1064. struct plane_state {
  1065. struct sde_plane_state *sde_pstate;
  1066. const struct drm_plane_state *drm_pstate;
  1067. int stage;
  1068. u32 pipe_id;
  1069. };
  1070. static int pstate_cmp(const void *a, const void *b)
  1071. {
  1072. struct plane_state *pa = (struct plane_state *)a;
  1073. struct plane_state *pb = (struct plane_state *)b;
  1074. int rc = 0;
  1075. int pa_zpos, pb_zpos;
  1076. enum sde_layout pa_layout, pb_layout;
  1077. if ((!pa || !pa->sde_pstate) || (!pb || !pb->sde_pstate))
  1078. return rc;
  1079. pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
  1080. pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
  1081. pa_layout = pa->sde_pstate->layout;
  1082. pb_layout = pb->sde_pstate->layout;
  1083. if (pa_zpos != pb_zpos)
  1084. rc = pa_zpos - pb_zpos;
  1085. else if (pa_layout != pb_layout)
  1086. rc = pa_layout - pb_layout;
  1087. else
  1088. rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
  1089. return rc;
  1090. }
  1091. /*
  1092. * validate and set source split:
  1093. * use pstates sorted by stage to check planes on same stage
  1094. * we assume that all pipes are in source split so its valid to compare
  1095. * without taking into account left/right mixer placement
  1096. */
  1097. static int _sde_crtc_validate_src_split_order(struct drm_crtc *crtc,
  1098. struct plane_state *pstates, int cnt)
  1099. {
  1100. struct plane_state *prv_pstate, *cur_pstate;
  1101. enum sde_layout prev_layout, cur_layout;
  1102. struct sde_rect left_rect, right_rect;
  1103. struct sde_kms *sde_kms;
  1104. int32_t left_pid, right_pid;
  1105. int32_t stage;
  1106. int i, rc = 0;
  1107. sde_kms = _sde_crtc_get_kms(crtc);
  1108. if (!sde_kms || !sde_kms->catalog) {
  1109. SDE_ERROR("invalid parameters\n");
  1110. return -EINVAL;
  1111. }
  1112. for (i = 1; i < cnt; i++) {
  1113. prv_pstate = &pstates[i - 1];
  1114. cur_pstate = &pstates[i];
  1115. prev_layout = prv_pstate->sde_pstate->layout;
  1116. cur_layout = cur_pstate->sde_pstate->layout;
  1117. if (prv_pstate->stage != cur_pstate->stage ||
  1118. prev_layout != cur_layout)
  1119. continue;
  1120. stage = cur_pstate->stage;
  1121. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1122. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1123. prv_pstate->drm_pstate->crtc_y,
  1124. prv_pstate->drm_pstate->crtc_w,
  1125. prv_pstate->drm_pstate->crtc_h, false);
  1126. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1127. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1128. cur_pstate->drm_pstate->crtc_y,
  1129. cur_pstate->drm_pstate->crtc_w,
  1130. cur_pstate->drm_pstate->crtc_h, false);
  1131. if (right_rect.x < left_rect.x) {
  1132. swap(left_pid, right_pid);
  1133. swap(left_rect, right_rect);
  1134. swap(prv_pstate, cur_pstate);
  1135. }
  1136. /*
  1137. * - planes are enumerated in pipe-priority order such that
  1138. * planes with lower drm_id must be left-most in a shared
  1139. * blend-stage when using source split.
  1140. * - planes in source split must be contiguous in width
  1141. * - planes in source split must have same dest yoff and height
  1142. */
  1143. if ((right_pid < left_pid) &&
  1144. !sde_kms->catalog->pipe_order_type) {
  1145. SDE_ERROR(
  1146. "invalid src split cfg, stage:%d left:%d right:%d\n",
  1147. stage, left_pid, right_pid);
  1148. return -EINVAL;
  1149. } else if (right_rect.x != (left_rect.x + left_rect.w)) {
  1150. SDE_ERROR(
  1151. "invalid coordinates, stage:%d l:%d-%d r:%d-%d\n",
  1152. stage, left_rect.x, left_rect.w,
  1153. right_rect.x, right_rect.w);
  1154. return -EINVAL;
  1155. } else if ((left_rect.y != right_rect.y) ||
  1156. (left_rect.h != right_rect.h)) {
  1157. SDE_ERROR(
  1158. "stage:%d invalid yoff/ht: l_yxh:%dx%d r_yxh:%dx%d\n",
  1159. stage, left_rect.y, left_rect.h,
  1160. right_rect.y, right_rect.h);
  1161. return -EINVAL;
  1162. }
  1163. }
  1164. return rc;
  1165. }
  1166. static void _sde_crtc_set_src_split_order(struct drm_crtc *crtc,
  1167. struct plane_state *pstates, int cnt)
  1168. {
  1169. struct plane_state *prv_pstate, *cur_pstate, *nxt_pstate;
  1170. enum sde_layout prev_layout, cur_layout;
  1171. struct sde_kms *sde_kms;
  1172. struct sde_rect left_rect, right_rect;
  1173. int32_t left_pid, right_pid;
  1174. int32_t stage;
  1175. int i;
  1176. sde_kms = _sde_crtc_get_kms(crtc);
  1177. if (!sde_kms || !sde_kms->catalog) {
  1178. SDE_ERROR("invalid parameters\n");
  1179. return;
  1180. }
  1181. if (!sde_kms->catalog->pipe_order_type)
  1182. return;
  1183. for (i = 0; i < cnt; i++) {
  1184. prv_pstate = (i > 0) ? &pstates[i - 1] : NULL;
  1185. cur_pstate = &pstates[i];
  1186. nxt_pstate = ((i + 1) < cnt) ? &pstates[i + 1] : NULL;
  1187. prev_layout = prv_pstate ? prv_pstate->sde_pstate->layout :
  1188. SDE_LAYOUT_NONE;
  1189. cur_layout = cur_pstate->sde_pstate->layout;
  1190. if ((!prv_pstate) || (prv_pstate->stage != cur_pstate->stage)
  1191. || (prev_layout != cur_layout)) {
  1192. /*
  1193. * reset if prv or nxt pipes are not in the same stage
  1194. * as the cur pipe
  1195. */
  1196. if ((!nxt_pstate)
  1197. || (nxt_pstate->stage != cur_pstate->stage)
  1198. || (nxt_pstate->sde_pstate->layout !=
  1199. cur_pstate->sde_pstate->layout))
  1200. cur_pstate->sde_pstate->pipe_order_flags = 0;
  1201. continue;
  1202. }
  1203. stage = cur_pstate->stage;
  1204. left_pid = prv_pstate->sde_pstate->base.plane->base.id;
  1205. POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x,
  1206. prv_pstate->drm_pstate->crtc_y,
  1207. prv_pstate->drm_pstate->crtc_w,
  1208. prv_pstate->drm_pstate->crtc_h, false);
  1209. right_pid = cur_pstate->sde_pstate->base.plane->base.id;
  1210. POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x,
  1211. cur_pstate->drm_pstate->crtc_y,
  1212. cur_pstate->drm_pstate->crtc_w,
  1213. cur_pstate->drm_pstate->crtc_h, false);
  1214. if (right_rect.x < left_rect.x) {
  1215. swap(left_pid, right_pid);
  1216. swap(left_rect, right_rect);
  1217. swap(prv_pstate, cur_pstate);
  1218. }
  1219. cur_pstate->sde_pstate->pipe_order_flags = SDE_SSPP_RIGHT;
  1220. prv_pstate->sde_pstate->pipe_order_flags = 0;
  1221. }
  1222. for (i = 0; i < cnt; i++) {
  1223. cur_pstate = &pstates[i];
  1224. sde_plane_setup_src_split_order(
  1225. cur_pstate->drm_pstate->plane,
  1226. cur_pstate->sde_pstate->multirect_index,
  1227. cur_pstate->sde_pstate->pipe_order_flags);
  1228. }
  1229. }
  1230. static void _sde_crtc_setup_blend_cfg_by_stage(struct sde_crtc_mixer *mixer,
  1231. int num_mixers, struct plane_state *pstates, int cnt)
  1232. {
  1233. int i, lm_idx;
  1234. struct sde_format *format;
  1235. bool blend_stage[SDE_STAGE_MAX] = { false };
  1236. u32 blend_type;
  1237. for (i = cnt - 1; i >= 0; i--) {
  1238. blend_type = sde_plane_get_property(pstates[i].sde_pstate,
  1239. PLANE_PROP_BLEND_OP);
  1240. /* stage has already been programmed or BLEND_OP_SKIP type */
  1241. if (blend_stage[pstates[i].sde_pstate->stage] ||
  1242. blend_type == SDE_DRM_BLEND_OP_SKIP)
  1243. continue;
  1244. for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) {
  1245. format = to_sde_format(msm_framebuffer_format(
  1246. pstates[i].sde_pstate->base.fb));
  1247. if (!format) {
  1248. SDE_ERROR("invalid format\n");
  1249. return;
  1250. }
  1251. _sde_crtc_setup_blend_cfg(mixer + lm_idx,
  1252. pstates[i].sde_pstate, format);
  1253. blend_stage[pstates[i].sde_pstate->stage] = true;
  1254. }
  1255. }
  1256. }
  1257. static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
  1258. struct drm_crtc_state *old_state, struct sde_crtc *sde_crtc,
  1259. struct sde_crtc_mixer *mixer)
  1260. {
  1261. struct drm_plane *plane;
  1262. struct drm_framebuffer *fb;
  1263. struct drm_plane_state *state;
  1264. struct sde_crtc_state *cstate;
  1265. struct sde_plane_state *pstate = NULL;
  1266. struct plane_state *pstates = NULL;
  1267. struct sde_format *format;
  1268. struct sde_hw_ctl *ctl;
  1269. struct sde_hw_mixer *lm;
  1270. struct sde_hw_stage_cfg *stage_cfg;
  1271. struct sde_rect plane_crtc_roi;
  1272. uint32_t stage_idx, lm_idx, layout_idx;
  1273. int zpos_cnt[MAX_LAYOUTS_PER_CRTC][SDE_STAGE_MAX + 1];
  1274. int i, mode, cnt = 0;
  1275. bool bg_alpha_enable = false;
  1276. u32 blend_type;
  1277. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  1278. DECLARE_BITMAP(fetch_active, SSPP_MAX);
  1279. if (!sde_crtc || !crtc->state || !mixer) {
  1280. SDE_ERROR("invalid sde_crtc or mixer\n");
  1281. return;
  1282. }
  1283. ctl = mixer->hw_ctl;
  1284. lm = mixer->hw_lm;
  1285. cstate = to_sde_crtc_state(crtc->state);
  1286. pstates = kcalloc(SDE_PSTATES_MAX,
  1287. sizeof(struct plane_state), GFP_KERNEL);
  1288. if (!pstates)
  1289. return;
  1290. memset(fetch_active, 0, sizeof(fetch_active));
  1291. memset(zpos_cnt, 0, sizeof(zpos_cnt));
  1292. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1293. state = plane->state;
  1294. if (!state)
  1295. continue;
  1296. plane_crtc_roi.x = state->crtc_x;
  1297. plane_crtc_roi.y = state->crtc_y;
  1298. plane_crtc_roi.w = state->crtc_w;
  1299. plane_crtc_roi.h = state->crtc_h;
  1300. pstate = to_sde_plane_state(state);
  1301. fb = state->fb;
  1302. mode = sde_plane_get_property(pstate,
  1303. PLANE_PROP_FB_TRANSLATION_MODE);
  1304. set_bit(sde_plane_pipe(plane), fetch_active);
  1305. sde_plane_ctl_flush(plane, ctl, true);
  1306. SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
  1307. crtc->base.id,
  1308. pstate->stage,
  1309. plane->base.id,
  1310. sde_plane_pipe(plane) - SSPP_VIG0,
  1311. state->fb ? state->fb->base.id : -1);
  1312. format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
  1313. if (!format) {
  1314. SDE_ERROR("invalid format\n");
  1315. goto end;
  1316. }
  1317. blend_type = sde_plane_get_property(pstate,
  1318. PLANE_PROP_BLEND_OP);
  1319. if (blend_type == SDE_DRM_BLEND_OP_SKIP) {
  1320. skip_blend_plane.valid_plane = true;
  1321. skip_blend_plane.plane = sde_plane_pipe(plane);
  1322. skip_blend_plane.height = plane_crtc_roi.h;
  1323. skip_blend_plane.width = plane_crtc_roi.w;
  1324. sde_cp_set_skip_blend_plane_info(crtc, &skip_blend_plane);
  1325. }
  1326. if (blend_type != SDE_DRM_BLEND_OP_SKIP) {
  1327. if (pstate->stage == SDE_STAGE_BASE &&
  1328. format->alpha_enable)
  1329. bg_alpha_enable = true;
  1330. SDE_EVT32(DRMID(crtc), DRMID(plane),
  1331. state->fb ? state->fb->base.id : -1,
  1332. state->src_x >> 16, state->src_y >> 16,
  1333. state->src_w >> 16, state->src_h >> 16,
  1334. state->crtc_x, state->crtc_y,
  1335. state->crtc_w, state->crtc_h,
  1336. pstate->rotation, mode);
  1337. /*
  1338. * none or left layout will program to layer mixer
  1339. * group 0, right layout will program to layer mixer
  1340. * group 1.
  1341. */
  1342. if (pstate->layout <= SDE_LAYOUT_LEFT)
  1343. layout_idx = 0;
  1344. else
  1345. layout_idx = 1;
  1346. stage_cfg = &sde_crtc->stage_cfg[layout_idx];
  1347. stage_idx = zpos_cnt[layout_idx][pstate->stage]++;
  1348. stage_cfg->stage[pstate->stage][stage_idx] =
  1349. sde_plane_pipe(plane);
  1350. stage_cfg->multirect_index[pstate->stage][stage_idx] =
  1351. pstate->multirect_index;
  1352. SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx,
  1353. sde_plane_pipe(plane) - SSPP_VIG0,
  1354. pstate->stage,
  1355. pstate->multirect_index,
  1356. pstate->multirect_mode,
  1357. format->base.pixel_format,
  1358. fb ? fb->modifier : 0,
  1359. layout_idx);
  1360. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers;
  1361. lm_idx++) {
  1362. if (bg_alpha_enable && !format->alpha_enable)
  1363. mixer[lm_idx].mixer_op_mode = 0;
  1364. else
  1365. mixer[lm_idx].mixer_op_mode |=
  1366. 1 << pstate->stage;
  1367. }
  1368. }
  1369. if (cnt >= SDE_PSTATES_MAX)
  1370. continue;
  1371. pstates[cnt].sde_pstate = pstate;
  1372. pstates[cnt].drm_pstate = state;
  1373. if (blend_type == SDE_DRM_BLEND_OP_SKIP)
  1374. pstates[cnt].stage = SKIP_STAGING_PIPE_ZPOS;
  1375. else
  1376. pstates[cnt].stage = sde_plane_get_property(
  1377. pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
  1378. pstates[cnt].pipe_id = sde_plane_pipe(plane);
  1379. cnt++;
  1380. }
  1381. /* blend config update */
  1382. _sde_crtc_setup_blend_cfg_by_stage(mixer, sde_crtc->num_mixers,
  1383. pstates, cnt);
  1384. if (ctl->ops.set_active_pipes)
  1385. ctl->ops.set_active_pipes(ctl, fetch_active);
  1386. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  1387. _sde_crtc_set_src_split_order(crtc, pstates, cnt);
  1388. if (lm && lm->ops.setup_dim_layer) {
  1389. cstate = to_sde_crtc_state(crtc->state);
  1390. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty)) {
  1391. for (i = 0; i < cstate->num_dim_layers; i++)
  1392. _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc,
  1393. mixer, &cstate->dim_layer[i]);
  1394. clear_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  1395. }
  1396. }
  1397. end:
  1398. kfree(pstates);
  1399. }
  1400. static void _sde_crtc_swap_mixers_for_right_partial_update(
  1401. struct drm_crtc *crtc)
  1402. {
  1403. struct sde_crtc *sde_crtc;
  1404. struct sde_crtc_state *cstate;
  1405. struct drm_encoder *drm_enc;
  1406. bool is_right_only;
  1407. bool encoder_in_dsc_merge = false;
  1408. if (!crtc || !crtc->state)
  1409. return;
  1410. sde_crtc = to_sde_crtc(crtc);
  1411. cstate = to_sde_crtc_state(crtc->state);
  1412. if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS_ONLY)
  1413. return;
  1414. drm_for_each_encoder_mask(drm_enc, crtc->dev,
  1415. crtc->state->encoder_mask) {
  1416. if (sde_encoder_is_dsc_merge(drm_enc)) {
  1417. encoder_in_dsc_merge = true;
  1418. break;
  1419. }
  1420. }
  1421. /**
  1422. * For right-only partial update with DSC merge, we swap LM0 & LM1.
  1423. * This is due to two reasons:
  1424. * - On 8996, there is a DSC HW requirement that in DSC Merge Mode,
  1425. * the left DSC must be used, right DSC cannot be used alone.
  1426. * For right-only partial update, this means swap layer mixers to map
  1427. * Left LM to Right INTF. On later HW this was relaxed.
  1428. * - In DSC Merge mode, the physical encoder has already registered
  1429. * PP0 as the master, to switch to right-only we would have to
  1430. * reprogram to be driven by PP1 instead.
  1431. * To support both cases, we prefer to support the mixer swap solution.
  1432. */
  1433. if (!encoder_in_dsc_merge) {
  1434. if (sde_crtc->mixers_swapped) {
  1435. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1436. sde_crtc->mixers_swapped = false;
  1437. SDE_EVT32(SDE_EVTLOG_FUNC_CASE1);
  1438. }
  1439. return;
  1440. }
  1441. is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) &&
  1442. !sde_kms_rect_is_null(&cstate->lm_roi[1]);
  1443. if (is_right_only && !sde_crtc->mixers_swapped) {
  1444. /* right-only update swap mixers */
  1445. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1446. sde_crtc->mixers_swapped = true;
  1447. } else if (!is_right_only && sde_crtc->mixers_swapped) {
  1448. /* left-only or full update, swap back */
  1449. swap(sde_crtc->mixers[0], sde_crtc->mixers[1]);
  1450. sde_crtc->mixers_swapped = false;
  1451. }
  1452. SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n",
  1453. sde_crtc->name, is_right_only, sde_crtc->mixers_swapped,
  1454. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1455. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1456. SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped,
  1457. sde_crtc->mixers[0].hw_lm->idx - LM_0,
  1458. sde_crtc->mixers[1].hw_lm->idx - LM_0);
  1459. }
  1460. /**
  1461. * _sde_crtc_blend_setup - configure crtc mixers
  1462. * @crtc: Pointer to drm crtc structure
  1463. * @old_state: Pointer to old crtc state
  1464. * @add_planes: Whether or not to add planes to mixers
  1465. */
  1466. static void _sde_crtc_blend_setup(struct drm_crtc *crtc,
  1467. struct drm_crtc_state *old_state, bool add_planes)
  1468. {
  1469. struct sde_crtc *sde_crtc;
  1470. struct sde_crtc_state *sde_crtc_state;
  1471. struct sde_crtc_mixer *mixer;
  1472. struct sde_hw_ctl *ctl;
  1473. struct sde_hw_mixer *lm;
  1474. struct sde_ctl_flush_cfg cfg = {0,};
  1475. int i;
  1476. if (!crtc)
  1477. return;
  1478. sde_crtc = to_sde_crtc(crtc);
  1479. sde_crtc_state = to_sde_crtc_state(crtc->state);
  1480. mixer = sde_crtc->mixers;
  1481. SDE_DEBUG("%s\n", sde_crtc->name);
  1482. if (sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  1483. SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
  1484. return;
  1485. }
  1486. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1487. if (!mixer[i].hw_lm) {
  1488. SDE_ERROR("invalid lm or ctl assigned to mixer\n");
  1489. return;
  1490. }
  1491. mixer[i].mixer_op_mode = 0;
  1492. if (test_bit(SDE_CRTC_DIRTY_DIM_LAYERS,
  1493. sde_crtc_state->dirty)) {
  1494. /* clear dim_layer settings */
  1495. lm = mixer[i].hw_lm;
  1496. if (lm->ops.clear_dim_layer)
  1497. lm->ops.clear_dim_layer(lm);
  1498. }
  1499. }
  1500. _sde_crtc_swap_mixers_for_right_partial_update(crtc);
  1501. /* initialize stage cfg */
  1502. memset(&sde_crtc->stage_cfg, 0, sizeof(sde_crtc->stage_cfg));
  1503. if (add_planes)
  1504. _sde_crtc_blend_setup_mixer(crtc, old_state, sde_crtc, mixer);
  1505. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1506. const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i];
  1507. int lm_layout = i / MAX_MIXERS_PER_LAYOUT;
  1508. ctl = mixer[i].hw_ctl;
  1509. lm = mixer[i].hw_lm;
  1510. if (sde_kms_rect_is_null(lm_roi))
  1511. sde_crtc->mixers[i].mixer_op_mode = 0;
  1512. lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
  1513. /* stage config flush mask */
  1514. ctl->ops.update_bitmask_mixer(ctl, mixer[i].hw_lm->idx, 1);
  1515. ctl->ops.get_pending_flush(ctl, &cfg);
  1516. SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
  1517. mixer[i].hw_lm->idx - LM_0,
  1518. mixer[i].mixer_op_mode,
  1519. ctl->idx - CTL_0,
  1520. cfg.pending_flush_mask);
  1521. if (sde_kms_rect_is_null(lm_roi)) {
  1522. SDE_DEBUG(
  1523. "%s: lm%d leave ctl%d mask 0 since null roi\n",
  1524. sde_crtc->name, lm->idx - LM_0,
  1525. ctl->idx - CTL_0);
  1526. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1527. NULL, true);
  1528. } else {
  1529. ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
  1530. &sde_crtc->stage_cfg[lm_layout],
  1531. false);
  1532. }
  1533. }
  1534. _sde_crtc_program_lm_output_roi(crtc);
  1535. }
  1536. int sde_crtc_find_plane_fb_modes(struct drm_crtc *crtc,
  1537. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1538. {
  1539. struct drm_plane *plane;
  1540. struct sde_plane_state *sde_pstate;
  1541. uint32_t mode = 0;
  1542. int rc;
  1543. if (!crtc) {
  1544. SDE_ERROR("invalid state\n");
  1545. return -EINVAL;
  1546. }
  1547. *fb_ns = 0;
  1548. *fb_sec = 0;
  1549. *fb_sec_dir = 0;
  1550. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1551. if (IS_ERR_OR_NULL(plane) || IS_ERR_OR_NULL(plane->state)) {
  1552. rc = PTR_ERR(plane);
  1553. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1554. DRMID(crtc), DRMID(plane), rc);
  1555. return rc;
  1556. }
  1557. sde_pstate = to_sde_plane_state(plane->state);
  1558. mode = sde_plane_get_property(sde_pstate,
  1559. PLANE_PROP_FB_TRANSLATION_MODE);
  1560. switch (mode) {
  1561. case SDE_DRM_FB_NON_SEC:
  1562. (*fb_ns)++;
  1563. break;
  1564. case SDE_DRM_FB_SEC:
  1565. (*fb_sec)++;
  1566. break;
  1567. case SDE_DRM_FB_SEC_DIR_TRANS:
  1568. (*fb_sec_dir)++;
  1569. break;
  1570. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1571. break;
  1572. default:
  1573. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1574. DRMID(plane), mode);
  1575. return -EINVAL;
  1576. }
  1577. }
  1578. return 0;
  1579. }
  1580. int sde_crtc_state_find_plane_fb_modes(struct drm_crtc_state *state,
  1581. uint32_t *fb_ns, uint32_t *fb_sec, uint32_t *fb_sec_dir)
  1582. {
  1583. struct drm_plane *plane;
  1584. const struct drm_plane_state *pstate;
  1585. struct sde_plane_state *sde_pstate;
  1586. uint32_t mode = 0;
  1587. int rc;
  1588. if (!state) {
  1589. SDE_ERROR("invalid state\n");
  1590. return -EINVAL;
  1591. }
  1592. *fb_ns = 0;
  1593. *fb_sec = 0;
  1594. *fb_sec_dir = 0;
  1595. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  1596. if (IS_ERR_OR_NULL(pstate)) {
  1597. rc = PTR_ERR(pstate);
  1598. SDE_ERROR("crtc%d failed to get plane%d state%d\n",
  1599. DRMID(state->crtc), DRMID(plane), rc);
  1600. return rc;
  1601. }
  1602. sde_pstate = to_sde_plane_state(pstate);
  1603. mode = sde_plane_get_property(sde_pstate,
  1604. PLANE_PROP_FB_TRANSLATION_MODE);
  1605. switch (mode) {
  1606. case SDE_DRM_FB_NON_SEC:
  1607. (*fb_ns)++;
  1608. break;
  1609. case SDE_DRM_FB_SEC:
  1610. (*fb_sec)++;
  1611. break;
  1612. case SDE_DRM_FB_SEC_DIR_TRANS:
  1613. (*fb_sec_dir)++;
  1614. break;
  1615. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1616. break;
  1617. default:
  1618. SDE_ERROR("Error: Plane[%d], fb_trans_mode:%d",
  1619. DRMID(plane), mode);
  1620. return -EINVAL;
  1621. }
  1622. }
  1623. return 0;
  1624. }
  1625. static void _sde_drm_fb_sec_dir_trans(
  1626. struct sde_kms_smmu_state_data *smmu_state, uint32_t secure_level,
  1627. struct sde_mdss_cfg *catalog, bool old_valid_fb, int *ops)
  1628. {
  1629. /* secure display usecase */
  1630. if ((smmu_state->state == ATTACHED)
  1631. && (secure_level == SDE_DRM_SEC_ONLY)) {
  1632. smmu_state->state = catalog->sui_ns_allowed ?
  1633. DETACH_SEC_REQ : DETACH_ALL_REQ;
  1634. smmu_state->secure_level = secure_level;
  1635. smmu_state->transition_type = PRE_COMMIT;
  1636. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1637. if (old_valid_fb)
  1638. *ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE |
  1639. SDE_KMS_OPS_CLEANUP_PLANE_FB);
  1640. if (catalog->sui_misr_supported)
  1641. smmu_state->sui_misr_state =
  1642. SUI_MISR_ENABLE_REQ;
  1643. /* secure camera usecase */
  1644. } else if (smmu_state->state == ATTACHED) {
  1645. smmu_state->state = DETACH_SEC_REQ;
  1646. smmu_state->secure_level = secure_level;
  1647. smmu_state->transition_type = PRE_COMMIT;
  1648. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1649. }
  1650. }
  1651. static void _sde_drm_fb_transactions(
  1652. struct sde_kms_smmu_state_data *smmu_state,
  1653. struct sde_mdss_cfg *catalog, bool old_valid_fb, bool post_commit,
  1654. int *ops)
  1655. {
  1656. if (((smmu_state->state == DETACHED)
  1657. || (smmu_state->state == DETACH_ALL_REQ))
  1658. || ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)
  1659. && ((smmu_state->state == DETACHED_SEC)
  1660. || (smmu_state->state == DETACH_SEC_REQ)))) {
  1661. smmu_state->state = catalog->sui_ns_allowed ?
  1662. ATTACH_SEC_REQ : ATTACH_ALL_REQ;
  1663. smmu_state->transition_type = post_commit ?
  1664. POST_COMMIT : PRE_COMMIT;
  1665. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1666. if (old_valid_fb)
  1667. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1668. if (catalog->sui_misr_supported)
  1669. smmu_state->sui_misr_state =
  1670. SUI_MISR_DISABLE_REQ;
  1671. } else if ((smmu_state->state == DETACHED_SEC)
  1672. || (smmu_state->state == DETACH_SEC_REQ)) {
  1673. smmu_state->state = ATTACH_SEC_REQ;
  1674. smmu_state->transition_type = post_commit ?
  1675. POST_COMMIT : PRE_COMMIT;
  1676. *ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
  1677. if (old_valid_fb)
  1678. *ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
  1679. }
  1680. }
  1681. /**
  1682. * sde_crtc_get_secure_transition_ops - determines the operations that
  1683. * need to be performed before transitioning to secure state
  1684. * This function should be called after swapping the new state
  1685. * @crtc: Pointer to drm crtc structure
  1686. * Returns the bitmask of operations need to be performed, -Error in
  1687. * case of error cases
  1688. */
  1689. int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
  1690. struct drm_crtc_state *old_crtc_state,
  1691. bool old_valid_fb)
  1692. {
  1693. struct drm_plane *plane;
  1694. struct drm_encoder *encoder;
  1695. struct sde_crtc *sde_crtc;
  1696. struct sde_kms *sde_kms;
  1697. struct sde_mdss_cfg *catalog;
  1698. struct sde_kms_smmu_state_data *smmu_state;
  1699. uint32_t translation_mode = 0, secure_level;
  1700. int ops = 0;
  1701. bool post_commit = false;
  1702. if (!crtc || !crtc->state) {
  1703. SDE_ERROR("invalid crtc\n");
  1704. return -EINVAL;
  1705. }
  1706. sde_kms = _sde_crtc_get_kms(crtc);
  1707. if (!sde_kms)
  1708. return -EINVAL;
  1709. smmu_state = &sde_kms->smmu_state;
  1710. smmu_state->prev_state = smmu_state->state;
  1711. smmu_state->prev_secure_level = smmu_state->secure_level;
  1712. sde_crtc = to_sde_crtc(crtc);
  1713. secure_level = sde_crtc_get_secure_level(crtc, crtc->state);
  1714. catalog = sde_kms->catalog;
  1715. /*
  1716. * SMMU operations need to be delayed in case of video mode panels
  1717. * when switching back to non_secure mode
  1718. */
  1719. drm_for_each_encoder_mask(encoder, crtc->dev,
  1720. crtc->state->encoder_mask) {
  1721. if (sde_encoder_is_dsi_display(encoder))
  1722. post_commit |= sde_encoder_check_curr_mode(encoder,
  1723. MSM_DISPLAY_VIDEO_MODE);
  1724. }
  1725. SDE_DEBUG("crtc%d: secure_level %d old_valid_fb %d post_commit %d\n",
  1726. DRMID(crtc), secure_level, old_valid_fb, post_commit);
  1727. SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,
  1728. old_valid_fb, post_commit, SDE_EVTLOG_FUNC_ENTRY);
  1729. drm_atomic_crtc_for_each_plane(plane, crtc) {
  1730. if (!plane->state)
  1731. continue;
  1732. translation_mode = sde_plane_get_property(
  1733. to_sde_plane_state(plane->state),
  1734. PLANE_PROP_FB_TRANSLATION_MODE);
  1735. if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) {
  1736. SDE_ERROR("crtc%d: invalid translation_mode %d\n",
  1737. DRMID(crtc), translation_mode);
  1738. return -EINVAL;
  1739. }
  1740. /* we can break if we find sec_dir plane */
  1741. if (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)
  1742. break;
  1743. }
  1744. mutex_lock(&sde_kms->secure_transition_lock);
  1745. switch (translation_mode) {
  1746. case SDE_DRM_FB_SEC_DIR_TRANS:
  1747. _sde_drm_fb_sec_dir_trans(smmu_state, secure_level,
  1748. catalog, old_valid_fb, &ops);
  1749. break;
  1750. case SDE_DRM_FB_SEC:
  1751. case SDE_DRM_FB_NON_SEC:
  1752. _sde_drm_fb_transactions(smmu_state, catalog,
  1753. old_valid_fb, post_commit, &ops);
  1754. break;
  1755. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  1756. ops = 0;
  1757. break;
  1758. default:
  1759. SDE_ERROR("crtc%d: invalid plane fb_mode %d\n",
  1760. DRMID(crtc), translation_mode);
  1761. ops = -EINVAL;
  1762. }
  1763. /* log only during actual transition times */
  1764. if (ops) {
  1765. SDE_DEBUG("crtc%d: state%d sec%d sec_lvl%d type%d ops%x\n",
  1766. DRMID(crtc), smmu_state->state,
  1767. secure_level, smmu_state->secure_level,
  1768. smmu_state->transition_type, ops);
  1769. SDE_EVT32(DRMID(crtc), secure_level, translation_mode,
  1770. smmu_state->state, smmu_state->transition_type,
  1771. smmu_state->secure_level, old_valid_fb,
  1772. post_commit, ops, SDE_EVTLOG_FUNC_EXIT);
  1773. }
  1774. mutex_unlock(&sde_kms->secure_transition_lock);
  1775. return ops;
  1776. }
  1777. /**
  1778. * _sde_crtc_setup_scaler3_lut - Set up scaler lut
  1779. * LUTs are configured only once during boot
  1780. * @sde_crtc: Pointer to sde crtc
  1781. * @cstate: Pointer to sde crtc state
  1782. */
  1783. static int _sde_crtc_set_dest_scaler_lut(struct sde_crtc *sde_crtc,
  1784. struct sde_crtc_state *cstate, uint32_t lut_idx)
  1785. {
  1786. struct sde_hw_scaler3_lut_cfg *cfg;
  1787. struct sde_kms *sde_kms;
  1788. u32 *lut_data = NULL;
  1789. size_t len = 0;
  1790. int ret = 0;
  1791. if (!sde_crtc || !cstate) {
  1792. SDE_ERROR("invalid args\n");
  1793. return -EINVAL;
  1794. }
  1795. sde_kms = _sde_crtc_get_kms(&sde_crtc->base);
  1796. if (!sde_kms)
  1797. return -EINVAL;
  1798. if (is_qseed3_rev_qseed3lite(sde_kms->catalog))
  1799. return 0;
  1800. lut_data = msm_property_get_blob(&sde_crtc->property_info,
  1801. &cstate->property_state, &len, lut_idx);
  1802. if (!lut_data || !len) {
  1803. SDE_DEBUG("%s: lut(%d): cleared: %pK, %zu\n", sde_crtc->name,
  1804. lut_idx, lut_data, len);
  1805. lut_data = NULL;
  1806. len = 0;
  1807. }
  1808. cfg = &cstate->scl3_lut_cfg;
  1809. switch (lut_idx) {
  1810. case CRTC_PROP_DEST_SCALER_LUT_ED:
  1811. cfg->dir_lut = lut_data;
  1812. cfg->dir_len = len;
  1813. break;
  1814. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  1815. cfg->cir_lut = lut_data;
  1816. cfg->cir_len = len;
  1817. break;
  1818. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  1819. cfg->sep_lut = lut_data;
  1820. cfg->sep_len = len;
  1821. break;
  1822. default:
  1823. ret = -EINVAL;
  1824. SDE_ERROR("%s:invalid LUT idx(%d)\n", sde_crtc->name, lut_idx);
  1825. SDE_EVT32(DRMID(&sde_crtc->base), lut_idx, SDE_EVTLOG_ERROR);
  1826. break;
  1827. }
  1828. cfg->is_configured = cfg->dir_lut && cfg->cir_lut && cfg->sep_lut;
  1829. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), ret, lut_idx, len,
  1830. cfg->is_configured);
  1831. return ret;
  1832. }
  1833. void sde_crtc_timeline_status(struct drm_crtc *crtc)
  1834. {
  1835. struct sde_crtc *sde_crtc;
  1836. if (!crtc) {
  1837. SDE_ERROR("invalid crtc\n");
  1838. return;
  1839. }
  1840. sde_crtc = to_sde_crtc(crtc);
  1841. sde_fence_timeline_status(sde_crtc->output_fence, &crtc->base);
  1842. }
  1843. static int _sde_validate_hw_resources(struct sde_crtc *sde_crtc)
  1844. {
  1845. int i;
  1846. /**
  1847. * Check if sufficient hw resources are
  1848. * available as per target caps & topology
  1849. */
  1850. if (!sde_crtc) {
  1851. SDE_ERROR("invalid argument\n");
  1852. return -EINVAL;
  1853. }
  1854. if (!sde_crtc->num_mixers ||
  1855. sde_crtc->num_mixers > MAX_MIXERS_PER_CRTC) {
  1856. SDE_ERROR("%s: invalid number mixers: %d\n",
  1857. sde_crtc->name, sde_crtc->num_mixers);
  1858. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1859. SDE_EVTLOG_ERROR);
  1860. return -EINVAL;
  1861. }
  1862. for (i = 0; i < sde_crtc->num_mixers; i++) {
  1863. if (!sde_crtc->mixers[i].hw_lm || !sde_crtc->mixers[i].hw_ctl
  1864. || !sde_crtc->mixers[i].hw_ds) {
  1865. SDE_ERROR("%s:insufficient resources for mixer(%d)\n",
  1866. sde_crtc->name, i);
  1867. SDE_EVT32(DRMID(&sde_crtc->base), sde_crtc->num_mixers,
  1868. i, sde_crtc->mixers[i].hw_lm,
  1869. sde_crtc->mixers[i].hw_ctl,
  1870. sde_crtc->mixers[i].hw_ds, SDE_EVTLOG_ERROR);
  1871. return -EINVAL;
  1872. }
  1873. }
  1874. return 0;
  1875. }
  1876. /**
  1877. * _sde_crtc_dest_scaler_setup - Set up dest scaler block
  1878. * @crtc: Pointer to drm crtc
  1879. */
  1880. static void _sde_crtc_dest_scaler_setup(struct drm_crtc *crtc)
  1881. {
  1882. struct sde_crtc *sde_crtc;
  1883. struct sde_crtc_state *cstate;
  1884. struct sde_hw_mixer *hw_lm;
  1885. struct sde_hw_ctl *hw_ctl;
  1886. struct sde_hw_ds *hw_ds;
  1887. struct sde_hw_ds_cfg *cfg;
  1888. struct sde_kms *kms;
  1889. u32 op_mode = 0;
  1890. u32 lm_idx = 0, num_mixers = 0;
  1891. int i, count = 0;
  1892. if (!crtc)
  1893. return;
  1894. sde_crtc = to_sde_crtc(crtc);
  1895. cstate = to_sde_crtc_state(crtc->state);
  1896. kms = _sde_crtc_get_kms(crtc);
  1897. num_mixers = sde_crtc->num_mixers;
  1898. count = cstate->num_ds;
  1899. SDE_DEBUG("crtc%d\n", crtc->base.id);
  1900. SDE_EVT32(DRMID(crtc), num_mixers, count, cstate->dirty[0],
  1901. cstate->num_ds_enabled);
  1902. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  1903. SDE_DEBUG("no change in settings, skip commit\n");
  1904. } else if (!kms || !kms->catalog) {
  1905. SDE_ERROR("crtc%d:invalid parameters\n", crtc->base.id);
  1906. } else if (!kms->catalog->mdp[0].has_dest_scaler) {
  1907. SDE_DEBUG("dest scaler feature not supported\n");
  1908. } else if (_sde_validate_hw_resources(sde_crtc)) {
  1909. //do nothing
  1910. } else if ((!cstate->scl3_lut_cfg.is_configured) &&
  1911. (!is_qseed3_rev_qseed3lite(kms->catalog))) {
  1912. SDE_ERROR("crtc%d:no LUT data available\n", crtc->base.id);
  1913. } else {
  1914. for (i = 0; i < count; i++) {
  1915. cfg = &cstate->ds_cfg[i];
  1916. if (!cfg->flags)
  1917. continue;
  1918. lm_idx = cfg->idx;
  1919. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  1920. hw_ctl = sde_crtc->mixers[lm_idx].hw_ctl;
  1921. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  1922. /* Setup op mode - Dual/single */
  1923. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  1924. op_mode |= BIT(hw_ds->idx - DS_0);
  1925. if ((i == count-1) && hw_ds->ops.setup_opmode) {
  1926. op_mode |= (cstate->num_ds_enabled ==
  1927. CRTC_DUAL_MIXERS_ONLY) ?
  1928. SDE_DS_OP_MODE_DUAL : 0;
  1929. hw_ds->ops.setup_opmode(hw_ds, op_mode);
  1930. SDE_EVT32_VERBOSE(DRMID(crtc), op_mode);
  1931. }
  1932. /* Setup scaler */
  1933. if ((cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE) ||
  1934. (cfg->flags &
  1935. SDE_DRM_DESTSCALER_ENHANCER_UPDATE)) {
  1936. if (hw_ds->ops.setup_scaler)
  1937. hw_ds->ops.setup_scaler(hw_ds,
  1938. &cfg->scl3_cfg,
  1939. &cstate->scl3_lut_cfg);
  1940. }
  1941. /*
  1942. * Dest scaler shares the flush bit of the LM in control
  1943. */
  1944. if (hw_ctl && hw_ctl->ops.update_bitmask_mixer)
  1945. hw_ctl->ops.update_bitmask_mixer(
  1946. hw_ctl, hw_lm->idx, 1);
  1947. }
  1948. }
  1949. }
  1950. static void _sde_crtc_put_frame_data_buffer(struct sde_frame_data_buffer *buf)
  1951. {
  1952. if (!buf)
  1953. return;
  1954. msm_gem_put_buffer(buf->gem);
  1955. kfree(buf);
  1956. buf = NULL;
  1957. }
  1958. static int _sde_crtc_get_frame_data_buffer(struct drm_crtc *crtc, uint32_t fd)
  1959. {
  1960. struct sde_crtc *sde_crtc;
  1961. struct sde_frame_data_buffer *buf;
  1962. uint32_t cur_buf;
  1963. sde_crtc = to_sde_crtc(crtc);
  1964. cur_buf = sde_crtc->frame_data.cnt;
  1965. buf = kzalloc(sizeof(struct sde_frame_data_buffer), GFP_KERNEL);
  1966. if (!buf)
  1967. return -ENOMEM;
  1968. sde_crtc->frame_data.buf[cur_buf] = buf;
  1969. buf->fb = drm_framebuffer_lookup(crtc->dev, NULL, fd);
  1970. if (!buf->fb) {
  1971. SDE_ERROR("unable to get fb");
  1972. return -EINVAL;
  1973. }
  1974. buf->gem = msm_framebuffer_bo(buf->fb, 0);
  1975. if (!buf->gem) {
  1976. SDE_ERROR("unable to get drm gem");
  1977. return -EINVAL;
  1978. }
  1979. return msm_gem_get_buffer(buf->gem, crtc->dev, buf->fb,
  1980. sizeof(struct sde_drm_frame_data_packet));
  1981. }
  1982. static void _sde_crtc_set_frame_data_buffers(struct drm_crtc *crtc,
  1983. struct sde_crtc_state *cstate, void __user *usr)
  1984. {
  1985. struct sde_crtc *sde_crtc;
  1986. struct sde_drm_frame_data_buffers_ctrl ctrl;
  1987. int i, ret;
  1988. if (!crtc || !cstate || !usr)
  1989. return;
  1990. sde_crtc = to_sde_crtc(crtc);
  1991. ret = copy_from_user(&ctrl, usr, sizeof(ctrl));
  1992. if (ret) {
  1993. SDE_ERROR("failed to copy frame data ctrl, ret %d\n", ret);
  1994. return;
  1995. }
  1996. if (!ctrl.num_buffers) {
  1997. SDE_DEBUG("clearing frame data buffers");
  1998. goto exit;
  1999. } else if (ctrl.num_buffers > SDE_FRAME_DATA_BUFFER_MAX) {
  2000. SDE_ERROR("invalid number of buffers %d", ctrl.num_buffers);
  2001. return;
  2002. }
  2003. for (i = 0; i < ctrl.num_buffers; i++) {
  2004. if (_sde_crtc_get_frame_data_buffer(crtc, ctrl.fds[i])) {
  2005. SDE_ERROR("unable to set buffer for fd %d", ctrl.fds[i]);
  2006. goto exit;
  2007. }
  2008. sde_crtc->frame_data.cnt++;
  2009. }
  2010. return;
  2011. exit:
  2012. while (sde_crtc->frame_data.cnt--)
  2013. _sde_crtc_put_frame_data_buffer(
  2014. sde_crtc->frame_data.buf[sde_crtc->frame_data.cnt]);
  2015. }
  2016. static void _sde_crtc_frame_data_notify(struct drm_crtc *crtc,
  2017. struct sde_drm_frame_data_packet *frame_data_packet)
  2018. {
  2019. struct sde_crtc *sde_crtc;
  2020. struct sde_drm_frame_data_buf buf;
  2021. struct msm_gem_object *msm_gem;
  2022. u32 cur_buf;
  2023. sde_crtc = to_sde_crtc(crtc);
  2024. cur_buf = sde_crtc->frame_data.idx;
  2025. msm_gem = to_msm_bo(sde_crtc->frame_data.buf[cur_buf]->gem);
  2026. buf.fd = sde_crtc->frame_data.buf[cur_buf]->fd;
  2027. buf.offset = msm_gem->offset;
  2028. sde_crtc_event_notify(crtc, DRM_EVENT_FRAME_DATA, sizeof(struct sde_drm_frame_data_buf),
  2029. (uint64_t)(&buf));
  2030. sde_crtc->frame_data.idx = ++sde_crtc->frame_data.idx % sde_crtc->frame_data.cnt;
  2031. }
  2032. void sde_crtc_get_frame_data(struct drm_crtc *crtc)
  2033. {
  2034. struct sde_crtc *sde_crtc;
  2035. struct drm_plane *plane;
  2036. struct sde_drm_frame_data_packet frame_data_packet = {0, 0};
  2037. struct sde_drm_frame_data_packet *data;
  2038. struct sde_frame_data *frame_data;
  2039. int i = 0;
  2040. if (!crtc || !crtc->state)
  2041. return;
  2042. sde_crtc = to_sde_crtc(crtc);
  2043. frame_data = &sde_crtc->frame_data;
  2044. if (frame_data->cnt) {
  2045. struct msm_gem_object *msm_gem;
  2046. msm_gem = to_msm_bo(frame_data->buf[frame_data->cnt]->gem);
  2047. data = (struct sde_drm_frame_data_packet *)
  2048. (((u8 *)msm_gem->vaddr) + msm_gem->offset);
  2049. } else {
  2050. data = &frame_data_packet;
  2051. }
  2052. data->commit_count = sde_crtc->play_count;
  2053. data->frame_count = sde_crtc->fps_info.frame_count;
  2054. /* Collect plane specific data */
  2055. drm_for_each_plane_mask(plane, crtc->dev, sde_crtc->plane_mask_old)
  2056. sde_plane_get_frame_data(plane, &data->plane_frame_data[i]);
  2057. if (frame_data->cnt)
  2058. _sde_crtc_frame_data_notify(crtc, data);
  2059. }
  2060. static void sde_crtc_frame_event_cb(void *data, u32 event, ktime_t ts)
  2061. {
  2062. struct drm_crtc *crtc = (struct drm_crtc *)data;
  2063. struct sde_crtc *sde_crtc;
  2064. struct msm_drm_private *priv;
  2065. struct sde_crtc_frame_event *fevent;
  2066. struct sde_kms_frame_event_cb_data *cb_data;
  2067. unsigned long flags;
  2068. u32 crtc_id;
  2069. cb_data = (struct sde_kms_frame_event_cb_data *)data;
  2070. if (!data) {
  2071. SDE_ERROR("invalid parameters\n");
  2072. return;
  2073. }
  2074. crtc = cb_data->crtc;
  2075. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  2076. SDE_ERROR("invalid parameters\n");
  2077. return;
  2078. }
  2079. sde_crtc = to_sde_crtc(crtc);
  2080. priv = crtc->dev->dev_private;
  2081. crtc_id = drm_crtc_index(crtc);
  2082. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2083. SDE_EVT32_VERBOSE(DRMID(crtc), event);
  2084. spin_lock_irqsave(&sde_crtc->fevent_spin_lock, flags);
  2085. fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
  2086. struct sde_crtc_frame_event, list);
  2087. if (fevent)
  2088. list_del_init(&fevent->list);
  2089. spin_unlock_irqrestore(&sde_crtc->fevent_spin_lock, flags);
  2090. if (!fevent) {
  2091. SDE_ERROR("crtc%d event %d overflow\n",
  2092. crtc->base.id, event);
  2093. SDE_EVT32(DRMID(crtc), event);
  2094. return;
  2095. }
  2096. /* log and clear plane ubwc errors if any */
  2097. if (event & (SDE_ENCODER_FRAME_EVENT_ERROR
  2098. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  2099. | SDE_ENCODER_FRAME_EVENT_DONE))
  2100. sde_crtc_get_frame_data(crtc);
  2101. if ((event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE) &&
  2102. (sde_crtc && sde_crtc->retire_frame_event_sf)) {
  2103. sde_crtc->retire_frame_event_time = ktime_get();
  2104. sysfs_notify_dirent(sde_crtc->retire_frame_event_sf);
  2105. }
  2106. fevent->event = event;
  2107. fevent->ts = ts;
  2108. fevent->crtc = crtc;
  2109. fevent->connector = cb_data->connector;
  2110. kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
  2111. }
  2112. void sde_crtc_prepare_commit(struct drm_crtc *crtc,
  2113. struct drm_crtc_state *old_state)
  2114. {
  2115. struct drm_device *dev;
  2116. struct sde_crtc *sde_crtc;
  2117. struct sde_crtc_state *cstate;
  2118. struct drm_connector *conn;
  2119. struct drm_encoder *encoder;
  2120. struct drm_connector_list_iter conn_iter;
  2121. if (!crtc || !crtc->state) {
  2122. SDE_ERROR("invalid crtc\n");
  2123. return;
  2124. }
  2125. dev = crtc->dev;
  2126. sde_crtc = to_sde_crtc(crtc);
  2127. cstate = to_sde_crtc_state(crtc->state);
  2128. SDE_EVT32_VERBOSE(DRMID(crtc));
  2129. SDE_ATRACE_BEGIN("sde_crtc_prepare_commit");
  2130. /* identify connectors attached to this crtc */
  2131. cstate->num_connectors = 0;
  2132. drm_connector_list_iter_begin(dev, &conn_iter);
  2133. drm_for_each_connector_iter(conn, &conn_iter)
  2134. if (conn->state && conn->state->crtc == crtc &&
  2135. cstate->num_connectors < MAX_CONNECTORS) {
  2136. encoder = conn->state->best_encoder;
  2137. if (encoder)
  2138. sde_encoder_register_frame_event_callback(
  2139. encoder,
  2140. sde_crtc_frame_event_cb,
  2141. crtc);
  2142. cstate->connectors[cstate->num_connectors++] = conn;
  2143. sde_connector_prepare_fence(conn);
  2144. }
  2145. drm_connector_list_iter_end(&conn_iter);
  2146. /* prepare main output fence */
  2147. sde_fence_prepare(sde_crtc->output_fence);
  2148. SDE_ATRACE_END("sde_crtc_prepare_commit");
  2149. }
  2150. /**
  2151. * sde_crtc_complete_flip - signal pending page_flip events
  2152. * Any pending vblank events are added to the vblank_event_list
  2153. * so that the next vblank interrupt shall signal them.
  2154. * However PAGE_FLIP events are not handled through the vblank_event_list.
  2155. * This API signals any pending PAGE_FLIP events requested through
  2156. * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event.
  2157. * if file!=NULL, this is preclose potential cancel-flip path
  2158. * @crtc: Pointer to drm crtc structure
  2159. * @file: Pointer to drm file
  2160. */
  2161. void sde_crtc_complete_flip(struct drm_crtc *crtc,
  2162. struct drm_file *file)
  2163. {
  2164. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2165. struct drm_device *dev = crtc->dev;
  2166. struct drm_pending_vblank_event *event;
  2167. unsigned long flags;
  2168. spin_lock_irqsave(&dev->event_lock, flags);
  2169. event = sde_crtc->event;
  2170. if (!event)
  2171. goto end;
  2172. /*
  2173. * if regular vblank case (!file) or if cancel-flip from
  2174. * preclose on file that requested flip, then send the
  2175. * event:
  2176. */
  2177. if (!file || (event->base.file_priv == file)) {
  2178. sde_crtc->event = NULL;
  2179. DRM_DEBUG_VBL("%s: send event: %pK\n",
  2180. sde_crtc->name, event);
  2181. SDE_EVT32_VERBOSE(DRMID(crtc));
  2182. drm_crtc_send_vblank_event(crtc, event);
  2183. }
  2184. end:
  2185. spin_unlock_irqrestore(&dev->event_lock, flags);
  2186. }
  2187. enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc,
  2188. struct drm_crtc_state *cstate)
  2189. {
  2190. struct drm_encoder *encoder;
  2191. if (!crtc || !crtc->dev || !cstate) {
  2192. SDE_ERROR("invalid crtc\n");
  2193. return INTF_MODE_NONE;
  2194. }
  2195. drm_for_each_encoder_mask(encoder, crtc->dev,
  2196. cstate->encoder_mask) {
  2197. /* continue if copy encoder is encountered */
  2198. if (sde_encoder_in_clone_mode(encoder))
  2199. continue;
  2200. return sde_encoder_get_intf_mode(encoder);
  2201. }
  2202. return INTF_MODE_NONE;
  2203. }
  2204. u32 sde_crtc_get_fps_mode(struct drm_crtc *crtc)
  2205. {
  2206. struct drm_encoder *encoder;
  2207. if (!crtc || !crtc->dev) {
  2208. SDE_ERROR("invalid crtc\n");
  2209. return INTF_MODE_NONE;
  2210. }
  2211. drm_for_each_encoder(encoder, crtc->dev)
  2212. if ((encoder->crtc == crtc)
  2213. && !sde_encoder_in_cont_splash(encoder))
  2214. return sde_encoder_get_fps(encoder);
  2215. return 0;
  2216. }
  2217. u32 sde_crtc_get_dfps_maxfps(struct drm_crtc *crtc)
  2218. {
  2219. struct drm_encoder *encoder;
  2220. if (!crtc || !crtc->dev) {
  2221. SDE_ERROR("invalid crtc\n");
  2222. return 0;
  2223. }
  2224. drm_for_each_encoder_mask(encoder, crtc->dev,
  2225. crtc->state->encoder_mask) {
  2226. if (!sde_encoder_in_cont_splash(encoder))
  2227. return sde_encoder_get_dfps_maxfps(encoder);
  2228. }
  2229. return 0;
  2230. }
  2231. static void sde_crtc_vblank_cb(void *data, ktime_t ts)
  2232. {
  2233. struct drm_crtc *crtc = (struct drm_crtc *)data;
  2234. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2235. /* keep statistics on vblank callback - with auto reset via debugfs */
  2236. if (ktime_compare(sde_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
  2237. sde_crtc->vblank_cb_time = ts;
  2238. else
  2239. sde_crtc->vblank_cb_count++;
  2240. sde_crtc->vblank_last_cb_time = ts;
  2241. sysfs_notify_dirent(sde_crtc->vsync_event_sf);
  2242. drm_crtc_handle_vblank(crtc);
  2243. DRM_DEBUG_VBL("crtc%d, ts:%llu\n", crtc->base.id, ktime_to_us(ts));
  2244. SDE_EVT32_VERBOSE(DRMID(crtc), ktime_to_us(ts));
  2245. }
  2246. static void _sde_crtc_retire_event(struct drm_connector *connector,
  2247. ktime_t ts, enum sde_fence_event fence_event)
  2248. {
  2249. if (!connector) {
  2250. SDE_ERROR("invalid param\n");
  2251. return;
  2252. }
  2253. SDE_ATRACE_BEGIN("signal_retire_fence");
  2254. sde_connector_complete_commit(connector, ts, fence_event);
  2255. SDE_ATRACE_END("signal_retire_fence");
  2256. }
  2257. static void sde_crtc_frame_event_work(struct kthread_work *work)
  2258. {
  2259. struct msm_drm_private *priv;
  2260. struct sde_crtc_frame_event *fevent;
  2261. struct drm_crtc *crtc;
  2262. struct sde_crtc *sde_crtc;
  2263. struct sde_kms *sde_kms;
  2264. unsigned long flags;
  2265. bool in_clone_mode = false;
  2266. if (!work) {
  2267. SDE_ERROR("invalid work handle\n");
  2268. return;
  2269. }
  2270. fevent = container_of(work, struct sde_crtc_frame_event, work);
  2271. if (!fevent->crtc || !fevent->crtc->state) {
  2272. SDE_ERROR("invalid crtc\n");
  2273. return;
  2274. }
  2275. crtc = fevent->crtc;
  2276. sde_crtc = to_sde_crtc(crtc);
  2277. sde_kms = _sde_crtc_get_kms(crtc);
  2278. if (!sde_kms) {
  2279. SDE_ERROR("invalid kms handle\n");
  2280. return;
  2281. }
  2282. priv = sde_kms->dev->dev_private;
  2283. SDE_ATRACE_BEGIN("crtc_frame_event");
  2284. SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
  2285. ktime_to_ns(fevent->ts));
  2286. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_ENTRY);
  2287. in_clone_mode = (fevent->event & SDE_ENCODER_FRAME_EVENT_CWB_DONE) ?
  2288. true : false;
  2289. if (!in_clone_mode && (fevent->event & (SDE_ENCODER_FRAME_EVENT_ERROR
  2290. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD
  2291. | SDE_ENCODER_FRAME_EVENT_DONE))) {
  2292. if (atomic_read(&sde_crtc->frame_pending) < 1) {
  2293. /* this should not happen */
  2294. SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
  2295. crtc->base.id,
  2296. ktime_to_ns(fevent->ts),
  2297. atomic_read(&sde_crtc->frame_pending));
  2298. SDE_EVT32(DRMID(crtc), fevent->event,
  2299. SDE_EVTLOG_FUNC_CASE1);
  2300. } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
  2301. /* release bandwidth and other resources */
  2302. SDE_DEBUG("crtc%d ts:%lld last pending\n",
  2303. crtc->base.id,
  2304. ktime_to_ns(fevent->ts));
  2305. SDE_EVT32(DRMID(crtc), fevent->event,
  2306. SDE_EVTLOG_FUNC_CASE2);
  2307. sde_core_perf_crtc_release_bw(crtc);
  2308. } else {
  2309. SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
  2310. SDE_EVTLOG_FUNC_CASE3);
  2311. }
  2312. }
  2313. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RELEASE_FENCE) {
  2314. SDE_ATRACE_BEGIN("signal_release_fence");
  2315. sde_fence_signal(sde_crtc->output_fence, fevent->ts,
  2316. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2317. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2318. SDE_ATRACE_END("signal_release_fence");
  2319. }
  2320. if (fevent->event & SDE_ENCODER_FRAME_EVENT_SIGNAL_RETIRE_FENCE)
  2321. /* this api should be called without spin_lock */
  2322. _sde_crtc_retire_event(fevent->connector, fevent->ts,
  2323. (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR)
  2324. ? SDE_FENCE_SIGNAL_ERROR : SDE_FENCE_SIGNAL);
  2325. if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
  2326. SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
  2327. crtc->base.id, ktime_to_ns(fevent->ts));
  2328. spin_lock_irqsave(&sde_crtc->fevent_spin_lock, flags);
  2329. list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
  2330. spin_unlock_irqrestore(&sde_crtc->fevent_spin_lock, flags);
  2331. SDE_ATRACE_END("crtc_frame_event");
  2332. }
  2333. void sde_crtc_complete_commit(struct drm_crtc *crtc,
  2334. struct drm_crtc_state *old_state)
  2335. {
  2336. struct sde_crtc *sde_crtc;
  2337. u32 power_on = 1;
  2338. if (!crtc || !crtc->state) {
  2339. SDE_ERROR("invalid crtc\n");
  2340. return;
  2341. }
  2342. sde_crtc = to_sde_crtc(crtc);
  2343. SDE_EVT32_VERBOSE(DRMID(crtc));
  2344. if (crtc->state->active_changed && crtc->state->active)
  2345. sde_crtc_event_notify(crtc, DRM_EVENT_CRTC_POWER, sizeof(u32), power_on);
  2346. sde_core_perf_crtc_update(crtc, 0, false);
  2347. }
  2348. /**
  2349. * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
  2350. * @cstate: Pointer to sde crtc state
  2351. */
  2352. static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
  2353. {
  2354. if (!cstate) {
  2355. SDE_ERROR("invalid cstate\n");
  2356. return;
  2357. }
  2358. cstate->input_fence_timeout_ns =
  2359. sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
  2360. cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
  2361. }
  2362. /**
  2363. * _sde_crtc_clear_dim_layers_v1 - clear all dim layer settings
  2364. * @cstate: Pointer to sde crtc state
  2365. */
  2366. static void _sde_crtc_clear_dim_layers_v1(struct sde_crtc_state *cstate)
  2367. {
  2368. u32 i;
  2369. if (!cstate)
  2370. return;
  2371. for (i = 0; i < cstate->num_dim_layers; i++)
  2372. memset(&cstate->dim_layer[i], 0, sizeof(cstate->dim_layer[i]));
  2373. cstate->num_dim_layers = 0;
  2374. }
  2375. /**
  2376. * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  2377. * @cstate: Pointer to sde crtc state
  2378. * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
  2379. */
  2380. static void _sde_crtc_set_dim_layer_v1(struct drm_crtc *crtc,
  2381. struct sde_crtc_state *cstate, void __user *usr_ptr)
  2382. {
  2383. struct sde_drm_dim_layer_v1 dim_layer_v1;
  2384. struct sde_drm_dim_layer_cfg *user_cfg;
  2385. struct sde_hw_dim_layer *dim_layer;
  2386. u32 count, i;
  2387. struct sde_kms *kms;
  2388. if (!crtc || !cstate) {
  2389. SDE_ERROR("invalid crtc or cstate\n");
  2390. return;
  2391. }
  2392. dim_layer = cstate->dim_layer;
  2393. if (!usr_ptr) {
  2394. /* usr_ptr is null when setting the default property value */
  2395. _sde_crtc_clear_dim_layers_v1(cstate);
  2396. SDE_DEBUG("dim_layer data removed\n");
  2397. goto clear;
  2398. }
  2399. kms = _sde_crtc_get_kms(crtc);
  2400. if (!kms || !kms->catalog) {
  2401. SDE_ERROR("invalid kms\n");
  2402. return;
  2403. }
  2404. if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
  2405. SDE_ERROR("failed to copy dim_layer data\n");
  2406. return;
  2407. }
  2408. count = dim_layer_v1.num_layers;
  2409. if (count > SDE_MAX_DIM_LAYERS) {
  2410. SDE_ERROR("invalid number of dim_layers:%d", count);
  2411. return;
  2412. }
  2413. /* populate from user space */
  2414. cstate->num_dim_layers = count;
  2415. for (i = 0; i < count; i++) {
  2416. user_cfg = &dim_layer_v1.layer_cfg[i];
  2417. dim_layer[i].flags = user_cfg->flags;
  2418. dim_layer[i].stage = (kms->catalog->has_base_layer) ?
  2419. user_cfg->stage : user_cfg->stage +
  2420. SDE_STAGE_0;
  2421. dim_layer[i].rect.x = user_cfg->rect.x1;
  2422. dim_layer[i].rect.y = user_cfg->rect.y1;
  2423. dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1;
  2424. dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1;
  2425. dim_layer[i].color_fill = (struct sde_mdss_color) {
  2426. user_cfg->color_fill.color_0,
  2427. user_cfg->color_fill.color_1,
  2428. user_cfg->color_fill.color_2,
  2429. user_cfg->color_fill.color_3,
  2430. };
  2431. SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n",
  2432. i, dim_layer[i].flags, dim_layer[i].stage);
  2433. SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n",
  2434. dim_layer[i].rect.x, dim_layer[i].rect.y,
  2435. dim_layer[i].rect.w, dim_layer[i].rect.h,
  2436. dim_layer[i].color_fill.color_0,
  2437. dim_layer[i].color_fill.color_1,
  2438. dim_layer[i].color_fill.color_2,
  2439. dim_layer[i].color_fill.color_3);
  2440. }
  2441. clear:
  2442. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  2443. }
  2444. /**
  2445. * _sde_crtc_set_dest_scaler - copy dest scaler settings from userspace
  2446. * @sde_crtc : Pointer to sde crtc
  2447. * @cstate : Pointer to sde crtc state
  2448. * @usr_ptr: User ptr for sde_drm_dest_scaler_data struct
  2449. */
  2450. static int _sde_crtc_set_dest_scaler(struct sde_crtc *sde_crtc,
  2451. struct sde_crtc_state *cstate,
  2452. void __user *usr_ptr)
  2453. {
  2454. struct sde_drm_dest_scaler_data ds_data;
  2455. struct sde_drm_dest_scaler_cfg *ds_cfg_usr;
  2456. struct sde_drm_scaler_v2 scaler_v2;
  2457. void __user *scaler_v2_usr;
  2458. int i, count;
  2459. if (!sde_crtc || !cstate) {
  2460. SDE_ERROR("invalid sde_crtc/state\n");
  2461. return -EINVAL;
  2462. }
  2463. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  2464. if (!usr_ptr) {
  2465. SDE_DEBUG("ds data removed\n");
  2466. return 0;
  2467. }
  2468. if (copy_from_user(&ds_data, usr_ptr, sizeof(ds_data))) {
  2469. SDE_ERROR("%s:failed to copy dest scaler data from user\n",
  2470. sde_crtc->name);
  2471. return -EINVAL;
  2472. }
  2473. count = ds_data.num_dest_scaler;
  2474. if (!count) {
  2475. SDE_DEBUG("no ds data available\n");
  2476. return 0;
  2477. }
  2478. if (count > SDE_MAX_DS_COUNT) {
  2479. SDE_ERROR("%s: invalid config: num_ds(%d) max(%d)\n",
  2480. sde_crtc->name, count, SDE_MAX_DS_COUNT);
  2481. SDE_EVT32(DRMID(&sde_crtc->base), count, SDE_EVTLOG_ERROR);
  2482. return -EINVAL;
  2483. }
  2484. /* Populate from user space */
  2485. for (i = 0; i < count; i++) {
  2486. ds_cfg_usr = &ds_data.ds_cfg[i];
  2487. cstate->ds_cfg[i].idx = ds_cfg_usr->index;
  2488. cstate->ds_cfg[i].flags = ds_cfg_usr->flags;
  2489. cstate->ds_cfg[i].lm_width = ds_cfg_usr->lm_width;
  2490. cstate->ds_cfg[i].lm_height = ds_cfg_usr->lm_height;
  2491. memset(&scaler_v2, 0, sizeof(scaler_v2));
  2492. if (ds_cfg_usr->scaler_cfg) {
  2493. scaler_v2_usr =
  2494. (void __user *)((uintptr_t)ds_cfg_usr->scaler_cfg);
  2495. if (copy_from_user(&scaler_v2, scaler_v2_usr,
  2496. sizeof(scaler_v2))) {
  2497. SDE_ERROR("%s:scaler: copy from user failed\n",
  2498. sde_crtc->name);
  2499. return -EINVAL;
  2500. }
  2501. }
  2502. sde_set_scaler_v2(&cstate->ds_cfg[i].scl3_cfg, &scaler_v2);
  2503. SDE_DEBUG("en(%d)dir(%d)de(%d) src(%dx%d) dst(%dx%d)\n",
  2504. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2505. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2506. scaler_v2.dst_width, scaler_v2.dst_height);
  2507. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base),
  2508. scaler_v2.enable, scaler_v2.dir_en, scaler_v2.de.enable,
  2509. scaler_v2.src_width[0], scaler_v2.src_height[0],
  2510. scaler_v2.dst_width, scaler_v2.dst_height);
  2511. SDE_DEBUG("ds cfg[%d]-ndx(%d) flags(%d) lm(%dx%d)\n",
  2512. i, ds_cfg_usr->index, ds_cfg_usr->flags,
  2513. ds_cfg_usr->lm_width, ds_cfg_usr->lm_height);
  2514. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), i, ds_cfg_usr->index,
  2515. ds_cfg_usr->flags, ds_cfg_usr->lm_width,
  2516. ds_cfg_usr->lm_height);
  2517. }
  2518. cstate->num_ds = count;
  2519. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2520. SDE_EVT32_VERBOSE(DRMID(&sde_crtc->base), count);
  2521. return 0;
  2522. }
  2523. static int _sde_crtc_check_dest_scaler_lm(struct drm_crtc *crtc,
  2524. struct drm_display_mode *mode, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2525. struct sde_hw_ds_cfg *prev_cfg)
  2526. {
  2527. if (cfg->lm_width > hdisplay || cfg->lm_height > mode->vdisplay
  2528. || !cfg->lm_width || !cfg->lm_height) {
  2529. SDE_ERROR("crtc%d: lm size[%d,%d] display [%d,%d]\n",
  2530. crtc->base.id, cfg->lm_width, cfg->lm_height,
  2531. hdisplay, mode->vdisplay);
  2532. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2533. hdisplay, mode->vdisplay, SDE_EVTLOG_ERROR);
  2534. return -E2BIG;
  2535. }
  2536. if (prev_cfg && (cfg->lm_width != prev_cfg->lm_width ||
  2537. cfg->lm_height != prev_cfg->lm_height)) {
  2538. SDE_ERROR("crtc%d: uneven lm split [%d,%d], [%d %d]\n",
  2539. crtc->base.id, cfg->lm_width,
  2540. cfg->lm_height, prev_cfg->lm_width,
  2541. prev_cfg->lm_height);
  2542. SDE_EVT32(DRMID(crtc), cfg->lm_width, cfg->lm_height,
  2543. prev_cfg->lm_width, prev_cfg->lm_height,
  2544. SDE_EVTLOG_ERROR);
  2545. return -EINVAL;
  2546. }
  2547. return 0;
  2548. }
  2549. static int _sde_crtc_check_dest_scaler_cfg(struct drm_crtc *crtc,
  2550. struct sde_crtc *sde_crtc, struct drm_display_mode *mode,
  2551. struct sde_hw_ds *hw_ds, struct sde_hw_ds_cfg *cfg, u32 hdisplay,
  2552. u32 max_in_width, u32 max_out_width)
  2553. {
  2554. if (cfg->flags & SDE_DRM_DESTSCALER_SCALE_UPDATE ||
  2555. cfg->flags & SDE_DRM_DESTSCALER_ENHANCER_UPDATE) {
  2556. /**
  2557. * Scaler src and dst width shouldn't exceed the maximum
  2558. * width limitation. Also, if there is no partial update
  2559. * dst width and height must match display resolution.
  2560. */
  2561. if (cfg->scl3_cfg.src_width[0] > max_in_width ||
  2562. cfg->scl3_cfg.dst_width > max_out_width ||
  2563. !cfg->scl3_cfg.src_width[0] ||
  2564. !cfg->scl3_cfg.dst_width ||
  2565. (!(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE)
  2566. && (cfg->scl3_cfg.dst_width != hdisplay ||
  2567. cfg->scl3_cfg.dst_height != mode->vdisplay))) {
  2568. SDE_ERROR("crtc%d: ", crtc->base.id);
  2569. SDE_ERROR("src_w(%d) dst(%dx%d) display(%dx%d)",
  2570. cfg->scl3_cfg.src_width[0],
  2571. cfg->scl3_cfg.dst_width,
  2572. cfg->scl3_cfg.dst_height,
  2573. hdisplay, mode->vdisplay);
  2574. SDE_ERROR("num_mixers(%d) flags(%d) ds-%d:\n",
  2575. sde_crtc->num_mixers, cfg->flags,
  2576. hw_ds->idx - DS_0);
  2577. SDE_ERROR("scale_en = %d, DE_en =%d\n",
  2578. cfg->scl3_cfg.enable,
  2579. cfg->scl3_cfg.de.enable);
  2580. SDE_EVT32(DRMID(crtc), cfg->scl3_cfg.enable,
  2581. cfg->scl3_cfg.de.enable, cfg->flags,
  2582. max_in_width, max_out_width,
  2583. cfg->scl3_cfg.src_width[0],
  2584. cfg->scl3_cfg.dst_width,
  2585. cfg->scl3_cfg.dst_height, hdisplay,
  2586. mode->vdisplay, sde_crtc->num_mixers,
  2587. SDE_EVTLOG_ERROR);
  2588. cfg->flags &=
  2589. ~SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2590. cfg->flags &=
  2591. ~SDE_DRM_DESTSCALER_ENHANCER_UPDATE;
  2592. return -EINVAL;
  2593. }
  2594. }
  2595. return 0;
  2596. }
  2597. static int _sde_crtc_check_dest_scaler_validate_ds(struct drm_crtc *crtc,
  2598. struct sde_crtc *sde_crtc, struct sde_crtc_state *cstate,
  2599. struct drm_display_mode *mode, struct sde_hw_ds *hw_ds,
  2600. u32 hdisplay, u32 *num_ds_enable, u32 max_in_width, u32 max_out_width)
  2601. {
  2602. int i, ret;
  2603. u32 lm_idx;
  2604. struct sde_hw_ds_cfg *cfg, *prev_cfg;
  2605. for (i = 0; i < cstate->num_ds; i++) {
  2606. cfg = &cstate->ds_cfg[i];
  2607. prev_cfg = (i > 0) ? &cstate->ds_cfg[i - 1] : NULL;
  2608. lm_idx = cfg->idx;
  2609. /**
  2610. * Validate against topology
  2611. * No of dest scalers should match the num of mixers
  2612. * unless it is partial update left only/right only use case
  2613. */
  2614. if (lm_idx >= sde_crtc->num_mixers || (i != lm_idx &&
  2615. !(cfg->flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2616. SDE_ERROR("crtc%d: ds_cfg id(%d):idx(%d), flags(%d)\n",
  2617. crtc->base.id, i, lm_idx, cfg->flags);
  2618. SDE_EVT32(DRMID(crtc), i, lm_idx, cfg->flags,
  2619. SDE_EVTLOG_ERROR);
  2620. return -EINVAL;
  2621. }
  2622. hw_ds = sde_crtc->mixers[lm_idx].hw_ds;
  2623. if (!max_in_width && !max_out_width) {
  2624. max_in_width = hw_ds->scl->top->maxinputwidth;
  2625. max_out_width = hw_ds->scl->top->maxoutputwidth;
  2626. if (cstate->num_ds == CRTC_DUAL_MIXERS_ONLY)
  2627. max_in_width -= SDE_DS_OVERFETCH_SIZE;
  2628. SDE_DEBUG("max DS width [%d,%d] for num_ds = %d\n",
  2629. max_in_width, max_out_width, cstate->num_ds);
  2630. }
  2631. /* Check LM width and height */
  2632. ret = _sde_crtc_check_dest_scaler_lm(crtc, mode, cfg, hdisplay,
  2633. prev_cfg);
  2634. if (ret)
  2635. return ret;
  2636. /* Check scaler data */
  2637. ret = _sde_crtc_check_dest_scaler_cfg(crtc, sde_crtc, mode,
  2638. hw_ds, cfg, hdisplay,
  2639. max_in_width, max_out_width);
  2640. if (ret)
  2641. return ret;
  2642. if (cfg->flags & SDE_DRM_DESTSCALER_ENABLE)
  2643. (*num_ds_enable)++;
  2644. SDE_DEBUG("ds[%d]: flags[0x%X]\n",
  2645. hw_ds->idx - DS_0, cfg->flags);
  2646. SDE_EVT32_VERBOSE(DRMID(crtc), hw_ds->idx - DS_0, cfg->flags);
  2647. }
  2648. return 0;
  2649. }
  2650. static void _sde_crtc_check_dest_scaler_data_disable(struct drm_crtc *crtc,
  2651. struct sde_crtc_state *cstate, u32 num_ds_enable)
  2652. {
  2653. struct sde_hw_ds_cfg *cfg;
  2654. int i;
  2655. SDE_DEBUG("dest scaler status : %d -> %d\n",
  2656. cstate->num_ds_enabled, num_ds_enable);
  2657. SDE_EVT32_VERBOSE(DRMID(crtc), cstate->num_ds_enabled, num_ds_enable,
  2658. cstate->num_ds, cstate->dirty[0]);
  2659. if (cstate->num_ds_enabled != num_ds_enable) {
  2660. /* Disabling destination scaler */
  2661. if (!num_ds_enable) {
  2662. for (i = 0; i < cstate->num_ds; i++) {
  2663. cfg = &cstate->ds_cfg[i];
  2664. cfg->idx = i;
  2665. /* Update scaler settings in disable case */
  2666. cfg->flags = SDE_DRM_DESTSCALER_SCALE_UPDATE;
  2667. cfg->scl3_cfg.enable = 0;
  2668. cfg->scl3_cfg.de.enable = 0;
  2669. }
  2670. }
  2671. cstate->num_ds_enabled = num_ds_enable;
  2672. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2673. } else {
  2674. if (!cstate->num_ds_enabled)
  2675. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2676. }
  2677. }
  2678. /**
  2679. * _sde_crtc_check_dest_scaler_data - validate the dest scaler data
  2680. * @crtc : Pointer to drm crtc
  2681. * @state : Pointer to drm crtc state
  2682. */
  2683. static int _sde_crtc_check_dest_scaler_data(struct drm_crtc *crtc,
  2684. struct drm_crtc_state *state)
  2685. {
  2686. struct sde_crtc *sde_crtc;
  2687. struct sde_crtc_state *cstate;
  2688. struct drm_display_mode *mode;
  2689. struct sde_kms *kms;
  2690. struct sde_hw_ds *hw_ds = NULL;
  2691. u32 ret = 0;
  2692. u32 num_ds_enable = 0, hdisplay = 0;
  2693. u32 max_in_width = 0, max_out_width = 0;
  2694. if (!crtc || !state)
  2695. return -EINVAL;
  2696. sde_crtc = to_sde_crtc(crtc);
  2697. cstate = to_sde_crtc_state(state);
  2698. kms = _sde_crtc_get_kms(crtc);
  2699. mode = &state->adjusted_mode;
  2700. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2701. if (!test_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty)) {
  2702. SDE_DEBUG("dest scaler property not set, skip validation\n");
  2703. return 0;
  2704. }
  2705. if (!kms || !kms->catalog) {
  2706. SDE_ERROR("crtc%d: invalid parameters\n", crtc->base.id);
  2707. return -EINVAL;
  2708. }
  2709. if (!kms->catalog->mdp[0].has_dest_scaler) {
  2710. SDE_DEBUG("dest scaler feature not supported\n");
  2711. return 0;
  2712. }
  2713. if (!sde_crtc->num_mixers) {
  2714. SDE_DEBUG("mixers not allocated\n");
  2715. return 0;
  2716. }
  2717. ret = _sde_validate_hw_resources(sde_crtc);
  2718. if (ret)
  2719. goto err;
  2720. /**
  2721. * No of dest scalers shouldn't exceed hw ds block count and
  2722. * also, match the num of mixers unless it is partial update
  2723. * left only/right only use case - currently PU + DS is not supported
  2724. */
  2725. if (cstate->num_ds > kms->catalog->ds_count ||
  2726. ((cstate->num_ds != sde_crtc->num_mixers) &&
  2727. !(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_PU_ENABLE))) {
  2728. SDE_ERROR("crtc%d: num_ds(%d), hw_ds_cnt(%d) flags(%d)\n",
  2729. crtc->base.id, cstate->num_ds, kms->catalog->ds_count,
  2730. cstate->ds_cfg[0].flags);
  2731. ret = -EINVAL;
  2732. goto err;
  2733. }
  2734. /**
  2735. * Check if DS needs to be enabled or disabled
  2736. * In case of enable, validate the data
  2737. */
  2738. if (!(cstate->ds_cfg[0].flags & SDE_DRM_DESTSCALER_ENABLE)) {
  2739. SDE_DEBUG("disable dest scaler, num(%d) flags(%d)\n",
  2740. cstate->num_ds, cstate->ds_cfg[0].flags);
  2741. goto disable;
  2742. }
  2743. /* Display resolution */
  2744. hdisplay = mode->hdisplay/sde_crtc->num_mixers;
  2745. /* Validate the DS data */
  2746. ret = _sde_crtc_check_dest_scaler_validate_ds(crtc, sde_crtc, cstate,
  2747. mode, hw_ds, hdisplay, &num_ds_enable,
  2748. max_in_width, max_out_width);
  2749. if (ret)
  2750. goto err;
  2751. disable:
  2752. _sde_crtc_check_dest_scaler_data_disable(crtc, cstate, num_ds_enable);
  2753. return 0;
  2754. err:
  2755. clear_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  2756. return ret;
  2757. }
  2758. /**
  2759. * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences
  2760. * @crtc: Pointer to CRTC object
  2761. */
  2762. static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
  2763. {
  2764. struct drm_plane *plane = NULL;
  2765. uint32_t wait_ms = 1;
  2766. ktime_t kt_end, kt_wait;
  2767. int rc = 0;
  2768. SDE_DEBUG("\n");
  2769. if (!crtc || !crtc->state) {
  2770. SDE_ERROR("invalid crtc/state %pK\n", crtc);
  2771. return;
  2772. }
  2773. /* use monotonic timer to limit total fence wait time */
  2774. kt_end = ktime_add_ns(ktime_get(),
  2775. to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
  2776. /*
  2777. * Wait for fences sequentially, as all of them need to be signalled
  2778. * before we can proceed.
  2779. *
  2780. * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
  2781. * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
  2782. * that each plane can check its fence status and react appropriately
  2783. * if its fence has timed out. Call input fence wait multiple times if
  2784. * fence wait is interrupted due to interrupt call.
  2785. */
  2786. SDE_ATRACE_BEGIN("plane_wait_input_fence");
  2787. drm_atomic_crtc_for_each_plane(plane, crtc) {
  2788. do {
  2789. kt_wait = ktime_sub(kt_end, ktime_get());
  2790. if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
  2791. wait_ms = ktime_to_ms(kt_wait);
  2792. else
  2793. wait_ms = 0;
  2794. rc = sde_plane_wait_input_fence(plane, wait_ms);
  2795. } while (wait_ms && rc == -ERESTARTSYS);
  2796. }
  2797. SDE_ATRACE_END("plane_wait_input_fence");
  2798. }
  2799. static void _sde_crtc_setup_mixer_for_encoder(
  2800. struct drm_crtc *crtc,
  2801. struct drm_encoder *enc)
  2802. {
  2803. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2804. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  2805. struct sde_rm *rm = &sde_kms->rm;
  2806. struct sde_crtc_mixer *mixer;
  2807. struct sde_hw_ctl *last_valid_ctl = NULL;
  2808. int i;
  2809. struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter, ds_iter;
  2810. sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
  2811. sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
  2812. sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
  2813. sde_rm_init_hw_iter(&ds_iter, enc->base.id, SDE_HW_BLK_DS);
  2814. /* Set up all the mixers and ctls reserved by this encoder */
  2815. for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
  2816. mixer = &sde_crtc->mixers[i];
  2817. if (!sde_rm_get_hw(rm, &lm_iter))
  2818. break;
  2819. mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  2820. /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
  2821. if (!sde_rm_get_hw(rm, &ctl_iter)) {
  2822. SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
  2823. mixer->hw_lm->idx - LM_0);
  2824. mixer->hw_ctl = last_valid_ctl;
  2825. } else {
  2826. mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
  2827. last_valid_ctl = mixer->hw_ctl;
  2828. sde_crtc->num_ctls++;
  2829. }
  2830. /* Shouldn't happen, mixers are always >= ctls */
  2831. if (!mixer->hw_ctl) {
  2832. SDE_ERROR("no valid ctls found for lm %d\n",
  2833. mixer->hw_lm->idx - LM_0);
  2834. return;
  2835. }
  2836. /* Dspp may be null */
  2837. (void) sde_rm_get_hw(rm, &dspp_iter);
  2838. mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw;
  2839. /* DS may be null */
  2840. (void) sde_rm_get_hw(rm, &ds_iter);
  2841. mixer->hw_ds = (struct sde_hw_ds *)ds_iter.hw;
  2842. mixer->encoder = enc;
  2843. sde_crtc->num_mixers++;
  2844. SDE_DEBUG("setup mixer %d: lm %d\n",
  2845. i, mixer->hw_lm->idx - LM_0);
  2846. SDE_DEBUG("setup mixer %d: ctl %d\n",
  2847. i, mixer->hw_ctl->idx - CTL_0);
  2848. if (mixer->hw_ds)
  2849. SDE_DEBUG("setup mixer %d: ds %d\n",
  2850. i, mixer->hw_ds->idx - DS_0);
  2851. }
  2852. }
  2853. static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
  2854. {
  2855. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2856. struct drm_encoder *enc;
  2857. sde_crtc->num_ctls = 0;
  2858. sde_crtc->num_mixers = 0;
  2859. sde_crtc->mixers_swapped = false;
  2860. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  2861. mutex_lock(&sde_crtc->crtc_lock);
  2862. /* Check for mixers on all encoders attached to this crtc */
  2863. list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
  2864. if (enc->crtc != crtc)
  2865. continue;
  2866. /* avoid overwriting mixers info from a copy encoder */
  2867. if (sde_encoder_in_clone_mode(enc))
  2868. continue;
  2869. _sde_crtc_setup_mixer_for_encoder(crtc, enc);
  2870. }
  2871. mutex_unlock(&sde_crtc->crtc_lock);
  2872. _sde_crtc_check_dest_scaler_data(crtc, crtc->state);
  2873. }
  2874. static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
  2875. {
  2876. int i;
  2877. struct sde_crtc_state *cstate;
  2878. cstate = to_sde_crtc_state(state);
  2879. cstate->is_ppsplit = false;
  2880. for (i = 0; i < cstate->num_connectors; i++) {
  2881. struct drm_connector *conn = cstate->connectors[i];
  2882. if (sde_connector_get_topology_name(conn) ==
  2883. SDE_RM_TOPOLOGY_PPSPLIT)
  2884. cstate->is_ppsplit = true;
  2885. }
  2886. }
  2887. static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc,
  2888. struct drm_crtc_state *state)
  2889. {
  2890. struct sde_crtc *sde_crtc;
  2891. struct sde_crtc_state *cstate;
  2892. struct drm_display_mode *adj_mode;
  2893. u32 crtc_split_width;
  2894. int i;
  2895. if (!crtc || !state) {
  2896. SDE_ERROR("invalid args\n");
  2897. return;
  2898. }
  2899. sde_crtc = to_sde_crtc(crtc);
  2900. cstate = to_sde_crtc_state(state);
  2901. adj_mode = &state->adjusted_mode;
  2902. crtc_split_width = sde_crtc_get_mixer_width(sde_crtc, cstate, adj_mode);
  2903. for (i = 0; i < sde_crtc->num_mixers; i++) {
  2904. cstate->lm_bounds[i].x = crtc_split_width * i;
  2905. cstate->lm_bounds[i].y = 0;
  2906. cstate->lm_bounds[i].w = crtc_split_width;
  2907. cstate->lm_bounds[i].h =
  2908. sde_crtc_get_mixer_height(sde_crtc, cstate, adj_mode);
  2909. memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i],
  2910. sizeof(cstate->lm_roi[i]));
  2911. SDE_EVT32_VERBOSE(DRMID(crtc), i,
  2912. cstate->lm_bounds[i].x, cstate->lm_bounds[i].y,
  2913. cstate->lm_bounds[i].w, cstate->lm_bounds[i].h);
  2914. SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i,
  2915. cstate->lm_roi[i].x, cstate->lm_roi[i].y,
  2916. cstate->lm_roi[i].w, cstate->lm_roi[i].h);
  2917. }
  2918. drm_mode_debug_printmodeline(adj_mode);
  2919. }
  2920. static void _sde_crtc_clear_all_blend_stages(struct sde_crtc *sde_crtc)
  2921. {
  2922. struct sde_crtc_mixer mixer;
  2923. /*
  2924. * Use mixer[0] to get hw_ctl which will use ops to clear
  2925. * all blendstages. Clear all blendstages will iterate through
  2926. * all mixers.
  2927. */
  2928. if (sde_crtc->num_mixers) {
  2929. mixer = sde_crtc->mixers[0];
  2930. if (mixer.hw_ctl && mixer.hw_ctl->ops.clear_all_blendstages)
  2931. mixer.hw_ctl->ops.clear_all_blendstages(mixer.hw_ctl);
  2932. if (mixer.hw_ctl && mixer.hw_ctl->ops.set_active_pipes)
  2933. mixer.hw_ctl->ops.set_active_pipes(mixer.hw_ctl, NULL);
  2934. }
  2935. }
  2936. static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
  2937. struct drm_crtc_state *old_state)
  2938. {
  2939. struct sde_crtc *sde_crtc;
  2940. struct drm_encoder *encoder;
  2941. struct drm_device *dev;
  2942. struct sde_kms *sde_kms;
  2943. struct sde_splash_display *splash_display;
  2944. bool cont_splash_enabled = false;
  2945. size_t i;
  2946. if (!crtc) {
  2947. SDE_ERROR("invalid crtc\n");
  2948. return;
  2949. }
  2950. if (!crtc->state->enable) {
  2951. SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
  2952. crtc->base.id, crtc->state->enable);
  2953. return;
  2954. }
  2955. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  2956. SDE_ERROR("power resource is not enabled\n");
  2957. return;
  2958. }
  2959. sde_kms = _sde_crtc_get_kms(crtc);
  2960. if (!sde_kms)
  2961. return;
  2962. SDE_ATRACE_BEGIN("crtc_atomic_begin");
  2963. SDE_DEBUG("crtc%d\n", crtc->base.id);
  2964. sde_crtc = to_sde_crtc(crtc);
  2965. dev = crtc->dev;
  2966. if (!sde_crtc->num_mixers) {
  2967. _sde_crtc_setup_mixers(crtc);
  2968. _sde_crtc_setup_is_ppsplit(crtc->state);
  2969. _sde_crtc_setup_lm_bounds(crtc, crtc->state);
  2970. _sde_crtc_clear_all_blend_stages(sde_crtc);
  2971. }
  2972. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2973. if (encoder->crtc != crtc)
  2974. continue;
  2975. /* encoder will trigger pending mask now */
  2976. sde_encoder_trigger_kickoff_pending(encoder);
  2977. }
  2978. /* update performance setting */
  2979. sde_core_perf_crtc_update(crtc, 1, false);
  2980. /*
  2981. * If no mixers have been allocated in sde_crtc_atomic_check(),
  2982. * it means we are trying to flush a CRTC whose state is disabled:
  2983. * nothing else needs to be done.
  2984. */
  2985. if (unlikely(!sde_crtc->num_mixers))
  2986. goto end;
  2987. _sde_crtc_blend_setup(crtc, old_state, true);
  2988. _sde_crtc_dest_scaler_setup(crtc);
  2989. sde_cp_crtc_apply_noise(crtc, old_state);
  2990. if (crtc->state->mode_changed)
  2991. sde_core_perf_crtc_update_uidle(crtc, true);
  2992. /*
  2993. * Since CP properties use AXI buffer to program the
  2994. * HW, check if context bank is in attached state,
  2995. * apply color processing properties only if
  2996. * smmu state is attached,
  2997. */
  2998. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2999. splash_display = &sde_kms->splash_data.splash_display[i];
  3000. if (splash_display->cont_splash_enabled &&
  3001. splash_display->encoder &&
  3002. crtc == splash_display->encoder->crtc)
  3003. cont_splash_enabled = true;
  3004. }
  3005. if (sde_kms_is_cp_operation_allowed(sde_kms))
  3006. sde_cp_crtc_apply_properties(crtc);
  3007. if (!sde_crtc->enabled)
  3008. sde_cp_crtc_suspend(crtc);
  3009. /*
  3010. * PP_DONE irq is only used by command mode for now.
  3011. * It is better to request pending before FLUSH and START trigger
  3012. * to make sure no pp_done irq missed.
  3013. * This is safe because no pp_done will happen before SW trigger
  3014. * in command mode.
  3015. */
  3016. end:
  3017. SDE_ATRACE_END("crtc_atomic_begin");
  3018. }
  3019. static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
  3020. struct drm_crtc_state *old_crtc_state)
  3021. {
  3022. struct drm_encoder *encoder;
  3023. struct sde_crtc *sde_crtc;
  3024. struct drm_device *dev;
  3025. struct drm_plane *plane;
  3026. struct msm_drm_private *priv;
  3027. struct sde_crtc_state *cstate;
  3028. struct sde_kms *sde_kms;
  3029. int i;
  3030. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  3031. SDE_ERROR("invalid crtc\n");
  3032. return;
  3033. }
  3034. if (!crtc->state->enable) {
  3035. SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
  3036. crtc->base.id, crtc->state->enable);
  3037. return;
  3038. }
  3039. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3040. SDE_ERROR("power resource is not enabled\n");
  3041. return;
  3042. }
  3043. sde_kms = _sde_crtc_get_kms(crtc);
  3044. if (!sde_kms) {
  3045. SDE_ERROR("invalid kms\n");
  3046. return;
  3047. }
  3048. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3049. sde_crtc = to_sde_crtc(crtc);
  3050. cstate = to_sde_crtc_state(crtc->state);
  3051. dev = crtc->dev;
  3052. priv = dev->dev_private;
  3053. if ((sde_crtc->cache_state == CACHE_STATE_PRE_CACHE) &&
  3054. sde_crtc_get_property(cstate, CRTC_PROP_CACHE_STATE))
  3055. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_WRITE,
  3056. false);
  3057. else
  3058. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL, false);
  3059. /*
  3060. * If no mixers has been allocated in sde_crtc_atomic_check(),
  3061. * it means we are trying to flush a CRTC whose state is disabled:
  3062. * nothing else needs to be done.
  3063. */
  3064. if (unlikely(!sde_crtc->num_mixers))
  3065. return;
  3066. SDE_ATRACE_BEGIN("sde_crtc_atomic_flush");
  3067. /*
  3068. * For planes without commit update, drm framework will not add
  3069. * those planes to current state since hardware update is not
  3070. * required. However, if those planes were power collapsed since
  3071. * last commit cycle, driver has to restore the hardware state
  3072. * of those planes explicitly here prior to plane flush.
  3073. * Also use this iteration to see if any plane requires cache,
  3074. * so during the perf update driver can activate/deactivate
  3075. * the cache accordingly.
  3076. */
  3077. for (i = 0; i < SDE_SYS_CACHE_MAX; i++)
  3078. sde_crtc->new_perf.llcc_active[i] = false;
  3079. drm_atomic_crtc_for_each_plane(plane, crtc) {
  3080. sde_plane_restore(plane);
  3081. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  3082. if (sde_plane_is_cache_required(plane, i))
  3083. sde_crtc->new_perf.llcc_active[i] = true;
  3084. }
  3085. }
  3086. sde_core_perf_crtc_update_llcc(crtc);
  3087. /* wait for acquire fences before anything else is done */
  3088. _sde_crtc_wait_for_fences(crtc);
  3089. if (!cstate->rsc_update) {
  3090. drm_for_each_encoder_mask(encoder, dev,
  3091. crtc->state->encoder_mask) {
  3092. cstate->rsc_client =
  3093. sde_encoder_get_rsc_client(encoder);
  3094. }
  3095. cstate->rsc_update = true;
  3096. }
  3097. /*
  3098. * Final plane updates: Give each plane a chance to complete all
  3099. * required writes/flushing before crtc's "flush
  3100. * everything" call below.
  3101. */
  3102. drm_atomic_crtc_for_each_plane(plane, crtc) {
  3103. if (sde_kms->smmu_state.transition_error)
  3104. sde_plane_set_error(plane, true);
  3105. sde_plane_flush(plane);
  3106. }
  3107. /* Kickoff will be scheduled by outer layer */
  3108. SDE_ATRACE_END("sde_crtc_atomic_flush");
  3109. }
  3110. /**
  3111. * sde_crtc_destroy_state - state destroy hook
  3112. * @crtc: drm CRTC
  3113. * @state: CRTC state object to release
  3114. */
  3115. static void sde_crtc_destroy_state(struct drm_crtc *crtc,
  3116. struct drm_crtc_state *state)
  3117. {
  3118. struct sde_crtc *sde_crtc;
  3119. struct sde_crtc_state *cstate;
  3120. struct drm_encoder *enc;
  3121. struct sde_kms *sde_kms;
  3122. if (!crtc || !state) {
  3123. SDE_ERROR("invalid argument(s)\n");
  3124. return;
  3125. }
  3126. sde_crtc = to_sde_crtc(crtc);
  3127. cstate = to_sde_crtc_state(state);
  3128. sde_kms = _sde_crtc_get_kms(crtc);
  3129. if (!sde_kms) {
  3130. SDE_ERROR("invalid sde_kms\n");
  3131. return;
  3132. }
  3133. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3134. drm_for_each_encoder_mask(enc, crtc->dev, state->encoder_mask)
  3135. sde_rm_release(&sde_kms->rm, enc, true);
  3136. sde_cp_clear_state_info(state);
  3137. __drm_atomic_helper_crtc_destroy_state(state);
  3138. /* destroy value helper */
  3139. msm_property_destroy_state(&sde_crtc->property_info, cstate,
  3140. &cstate->property_state);
  3141. }
  3142. static int _sde_crtc_flush_frame_events(struct drm_crtc *crtc)
  3143. {
  3144. struct sde_crtc *sde_crtc;
  3145. int i;
  3146. if (!crtc) {
  3147. SDE_ERROR("invalid argument\n");
  3148. return -EINVAL;
  3149. }
  3150. sde_crtc = to_sde_crtc(crtc);
  3151. if (!atomic_read(&sde_crtc->frame_pending)) {
  3152. SDE_DEBUG("no frames pending\n");
  3153. return 0;
  3154. }
  3155. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  3156. /*
  3157. * flush all the event thread work to make sure all the
  3158. * FRAME_EVENTS from encoder are propagated to crtc
  3159. */
  3160. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  3161. if (list_empty(&sde_crtc->frame_events[i].list))
  3162. kthread_flush_work(&sde_crtc->frame_events[i].work);
  3163. }
  3164. SDE_EVT32_VERBOSE(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  3165. return 0;
  3166. }
  3167. /**
  3168. * _sde_crtc_remove_pipe_flush - remove staged pipes from flush mask
  3169. * @crtc: Pointer to crtc structure
  3170. */
  3171. static void _sde_crtc_remove_pipe_flush(struct drm_crtc *crtc)
  3172. {
  3173. struct drm_plane *plane;
  3174. struct drm_plane_state *state;
  3175. struct sde_crtc *sde_crtc;
  3176. struct sde_crtc_mixer *mixer;
  3177. struct sde_hw_ctl *ctl;
  3178. if (!crtc)
  3179. return;
  3180. sde_crtc = to_sde_crtc(crtc);
  3181. mixer = sde_crtc->mixers;
  3182. if (!mixer)
  3183. return;
  3184. ctl = mixer->hw_ctl;
  3185. drm_atomic_crtc_for_each_plane(plane, crtc) {
  3186. state = plane->state;
  3187. if (!state)
  3188. continue;
  3189. /* clear plane flush bitmask */
  3190. sde_plane_ctl_flush(plane, ctl, false);
  3191. }
  3192. }
  3193. static void _sde_crtc_schedule_idle_notify(struct drm_crtc *crtc)
  3194. {
  3195. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3196. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  3197. struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
  3198. struct msm_drm_private *priv;
  3199. struct msm_drm_thread *event_thread;
  3200. int idle_time = 0;
  3201. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3202. return;
  3203. priv = sde_kms->dev->dev_private;
  3204. idle_time = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_TIMEOUT);
  3205. if (!idle_time ||
  3206. !sde_encoder_check_curr_mode(sde_crtc->mixers[0].encoder,
  3207. MSM_DISPLAY_VIDEO_MODE) ||
  3208. (crtc->index >= ARRAY_SIZE(priv->event_thread)) ||
  3209. (sde_crtc->cache_state > CACHE_STATE_NORMAL))
  3210. return;
  3211. /* schedule the idle notify delayed work */
  3212. event_thread = &priv->event_thread[crtc->index];
  3213. kthread_mod_delayed_work(&event_thread->worker,
  3214. &sde_crtc->idle_notify_work, msecs_to_jiffies(idle_time));
  3215. SDE_DEBUG("schedule idle notify work in %dms\n", idle_time);
  3216. }
  3217. /**
  3218. * sde_crtc_reset_hw - attempt hardware reset on errors
  3219. * @crtc: Pointer to DRM crtc instance
  3220. * @old_state: Pointer to crtc state for previous commit
  3221. * @recovery_events: Whether or not recovery events are enabled
  3222. * Returns: Zero if current commit should still be attempted
  3223. */
  3224. int sde_crtc_reset_hw(struct drm_crtc *crtc, struct drm_crtc_state *old_state,
  3225. bool recovery_events)
  3226. {
  3227. struct drm_plane *plane_halt[MAX_PLANES];
  3228. struct drm_plane *plane;
  3229. struct drm_encoder *encoder;
  3230. struct sde_crtc *sde_crtc;
  3231. struct sde_crtc_state *cstate;
  3232. struct sde_hw_ctl *ctl;
  3233. signed int i, plane_count;
  3234. int rc;
  3235. if (!crtc || !crtc->dev || !old_state || !crtc->state)
  3236. return -EINVAL;
  3237. sde_crtc = to_sde_crtc(crtc);
  3238. cstate = to_sde_crtc_state(crtc->state);
  3239. SDE_EVT32(DRMID(crtc), recovery_events, SDE_EVTLOG_FUNC_ENTRY);
  3240. /* optionally generate a panic instead of performing a h/w reset */
  3241. SDE_DBG_CTRL("stop_ftrace", "reset_hw_panic");
  3242. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3243. ctl = sde_crtc->mixers[i].hw_ctl;
  3244. if (!ctl || !ctl->ops.reset)
  3245. continue;
  3246. rc = ctl->ops.reset(ctl);
  3247. if (rc) {
  3248. SDE_DEBUG("crtc%d: ctl%d reset failure\n",
  3249. crtc->base.id, ctl->idx - CTL_0);
  3250. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0,
  3251. SDE_EVTLOG_ERROR);
  3252. break;
  3253. }
  3254. }
  3255. /*
  3256. * Early out if simple ctl reset succeeded or reset is
  3257. * being performed after timeout
  3258. */
  3259. if (i == sde_crtc->num_ctls || crtc->state == old_state)
  3260. return 0;
  3261. SDE_DEBUG("crtc%d: issuing hard reset\n", DRMID(crtc));
  3262. /* force all components in the system into reset at the same time */
  3263. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3264. ctl = sde_crtc->mixers[i].hw_ctl;
  3265. if (!ctl || !ctl->ops.hard_reset)
  3266. continue;
  3267. SDE_EVT32(DRMID(crtc), ctl->idx - CTL_0);
  3268. ctl->ops.hard_reset(ctl, true);
  3269. }
  3270. plane_count = 0;
  3271. drm_atomic_crtc_state_for_each_plane(plane, old_state) {
  3272. if (plane_count >= ARRAY_SIZE(plane_halt))
  3273. break;
  3274. plane_halt[plane_count++] = plane;
  3275. sde_plane_halt_requests(plane, true);
  3276. sde_plane_set_revalidate(plane, true);
  3277. }
  3278. /* provide safe "border color only" commit configuration for later */
  3279. _sde_crtc_remove_pipe_flush(crtc);
  3280. _sde_crtc_blend_setup(crtc, old_state, false);
  3281. /* take h/w components out of reset */
  3282. for (i = plane_count - 1; i >= 0; --i)
  3283. sde_plane_halt_requests(plane_halt[i], false);
  3284. /* attempt to poll for start of frame cycle before reset release */
  3285. list_for_each_entry(encoder,
  3286. &crtc->dev->mode_config.encoder_list, head) {
  3287. if (encoder->crtc != crtc)
  3288. continue;
  3289. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3290. sde_encoder_poll_line_counts(encoder);
  3291. }
  3292. for (i = 0; i < sde_crtc->num_ctls; ++i) {
  3293. ctl = sde_crtc->mixers[i].hw_ctl;
  3294. if (!ctl || !ctl->ops.hard_reset)
  3295. continue;
  3296. ctl->ops.hard_reset(ctl, false);
  3297. }
  3298. list_for_each_entry(encoder,
  3299. &crtc->dev->mode_config.encoder_list, head) {
  3300. if (encoder->crtc != crtc)
  3301. continue;
  3302. if (sde_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
  3303. sde_encoder_kickoff(encoder, false, true);
  3304. }
  3305. /* panic the device if VBIF is not in good state */
  3306. return !recovery_events ? 0 : -EAGAIN;
  3307. }
  3308. void sde_crtc_commit_kickoff(struct drm_crtc *crtc,
  3309. struct drm_crtc_state *old_state)
  3310. {
  3311. struct drm_encoder *encoder;
  3312. struct drm_device *dev;
  3313. struct sde_crtc *sde_crtc;
  3314. struct sde_kms *sde_kms;
  3315. struct sde_crtc_state *cstate;
  3316. bool is_error = false;
  3317. unsigned long flags;
  3318. enum sde_crtc_idle_pc_state idle_pc_state;
  3319. struct sde_encoder_kickoff_params params = { 0 };
  3320. if (!crtc) {
  3321. SDE_ERROR("invalid argument\n");
  3322. return;
  3323. }
  3324. dev = crtc->dev;
  3325. sde_crtc = to_sde_crtc(crtc);
  3326. sde_kms = _sde_crtc_get_kms(crtc);
  3327. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3328. SDE_ERROR("invalid argument\n");
  3329. return;
  3330. }
  3331. cstate = to_sde_crtc_state(crtc->state);
  3332. /*
  3333. * If no mixers has been allocated in sde_crtc_atomic_check(),
  3334. * it means we are trying to start a CRTC whose state is disabled:
  3335. * nothing else needs to be done.
  3336. */
  3337. if (unlikely(!sde_crtc->num_mixers))
  3338. return;
  3339. SDE_ATRACE_BEGIN("crtc_commit");
  3340. idle_pc_state = sde_crtc_get_property(cstate, CRTC_PROP_IDLE_PC_STATE);
  3341. sde_crtc->kickoff_in_progress = true;
  3342. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3343. if (encoder->crtc != crtc)
  3344. continue;
  3345. /*
  3346. * Encoder will flush/start now, unless it has a tx pending.
  3347. * If so, it may delay and flush at an irq event (e.g. ppdone)
  3348. */
  3349. params.affected_displays = _sde_crtc_get_displays_affected(crtc,
  3350. crtc->state);
  3351. if (sde_encoder_prepare_for_kickoff(encoder, &params))
  3352. sde_crtc->needs_hw_reset = true;
  3353. if (idle_pc_state != IDLE_PC_NONE)
  3354. sde_encoder_control_idle_pc(encoder,
  3355. (idle_pc_state == IDLE_PC_ENABLE) ? true : false);
  3356. }
  3357. /*
  3358. * Optionally attempt h/w recovery if any errors were detected while
  3359. * preparing for the kickoff
  3360. */
  3361. if (sde_crtc->needs_hw_reset) {
  3362. sde_crtc->frame_trigger_mode = params.frame_trigger_mode;
  3363. if (sde_crtc->frame_trigger_mode
  3364. != FRAME_DONE_WAIT_POSTED_START &&
  3365. sde_crtc_reset_hw(crtc, old_state,
  3366. params.recovery_events_enabled))
  3367. is_error = true;
  3368. sde_crtc->needs_hw_reset = false;
  3369. }
  3370. sde_crtc_calc_fps(sde_crtc);
  3371. SDE_ATRACE_BEGIN("flush_event_thread");
  3372. _sde_crtc_flush_frame_events(crtc);
  3373. SDE_ATRACE_END("flush_event_thread");
  3374. sde_crtc->plane_mask_old = crtc->state->plane_mask;
  3375. if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
  3376. /* acquire bandwidth and other resources */
  3377. SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
  3378. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE1);
  3379. } else {
  3380. SDE_DEBUG("crtc%d commit\n", crtc->base.id);
  3381. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_CASE2);
  3382. }
  3383. sde_crtc->play_count++;
  3384. sde_vbif_clear_errors(sde_kms);
  3385. if (is_error) {
  3386. _sde_crtc_remove_pipe_flush(crtc);
  3387. _sde_crtc_blend_setup(crtc, old_state, false);
  3388. }
  3389. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3390. if (encoder->crtc != crtc)
  3391. continue;
  3392. sde_encoder_kickoff(encoder, false, true);
  3393. }
  3394. sde_crtc->kickoff_in_progress = false;
  3395. /* store the event after frame trigger */
  3396. if (sde_crtc->event) {
  3397. WARN_ON(sde_crtc->event);
  3398. } else {
  3399. spin_lock_irqsave(&dev->event_lock, flags);
  3400. sde_crtc->event = crtc->state->event;
  3401. spin_unlock_irqrestore(&dev->event_lock, flags);
  3402. }
  3403. _sde_crtc_schedule_idle_notify(crtc);
  3404. SDE_ATRACE_END("crtc_commit");
  3405. }
  3406. /**
  3407. * _sde_crtc_vblank_enable - update power resource and vblank request
  3408. * @sde_crtc: Pointer to sde crtc structure
  3409. * @enable: Whether to enable/disable vblanks
  3410. *
  3411. * @Return: error code
  3412. */
  3413. static int _sde_crtc_vblank_enable(
  3414. struct sde_crtc *sde_crtc, bool enable)
  3415. {
  3416. struct drm_crtc *crtc;
  3417. struct drm_encoder *enc;
  3418. if (!sde_crtc) {
  3419. SDE_ERROR("invalid crtc\n");
  3420. return -EINVAL;
  3421. }
  3422. crtc = &sde_crtc->base;
  3423. SDE_EVT32(DRMID(crtc), enable, sde_crtc->enabled,
  3424. crtc->state->encoder_mask,
  3425. sde_crtc->cached_encoder_mask);
  3426. if (enable) {
  3427. int ret;
  3428. ret = pm_runtime_get_sync(crtc->dev->dev);
  3429. if (ret < 0)
  3430. return ret;
  3431. mutex_lock(&sde_crtc->crtc_lock);
  3432. drm_for_each_encoder_mask(enc, crtc->dev,
  3433. sde_crtc->cached_encoder_mask) {
  3434. SDE_EVT32(DRMID(crtc), DRMID(enc));
  3435. sde_encoder_register_vblank_callback(enc,
  3436. sde_crtc_vblank_cb, (void *)crtc);
  3437. }
  3438. mutex_unlock(&sde_crtc->crtc_lock);
  3439. } else {
  3440. mutex_lock(&sde_crtc->crtc_lock);
  3441. drm_for_each_encoder_mask(enc, crtc->dev,
  3442. sde_crtc->cached_encoder_mask) {
  3443. SDE_EVT32(DRMID(crtc), DRMID(enc));
  3444. sde_encoder_register_vblank_callback(enc, NULL, NULL);
  3445. }
  3446. mutex_unlock(&sde_crtc->crtc_lock);
  3447. pm_runtime_put_sync(crtc->dev->dev);
  3448. }
  3449. return 0;
  3450. }
  3451. /**
  3452. * sde_crtc_duplicate_state - state duplicate hook
  3453. * @crtc: Pointer to drm crtc structure
  3454. * @Returns: Pointer to new drm_crtc_state structure
  3455. */
  3456. static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
  3457. {
  3458. struct sde_crtc *sde_crtc;
  3459. struct sde_crtc_state *cstate, *old_cstate;
  3460. if (!crtc || !crtc->state) {
  3461. SDE_ERROR("invalid argument(s)\n");
  3462. return NULL;
  3463. }
  3464. sde_crtc = to_sde_crtc(crtc);
  3465. old_cstate = to_sde_crtc_state(crtc->state);
  3466. if (old_cstate->cont_splash_populated) {
  3467. crtc->state->plane_mask = 0;
  3468. crtc->state->connector_mask = 0;
  3469. crtc->state->encoder_mask = 0;
  3470. crtc->state->enable = false;
  3471. old_cstate->cont_splash_populated = false;
  3472. }
  3473. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3474. if (!cstate) {
  3475. SDE_ERROR("failed to allocate state\n");
  3476. return NULL;
  3477. }
  3478. /* duplicate value helper */
  3479. msm_property_duplicate_state(&sde_crtc->property_info,
  3480. old_cstate, cstate,
  3481. &cstate->property_state, cstate->property_values);
  3482. sde_cp_duplicate_state_info(&old_cstate->base, &cstate->base);
  3483. /* duplicate base helper */
  3484. __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
  3485. return &cstate->base;
  3486. }
  3487. /**
  3488. * sde_crtc_reset - reset hook for CRTCs
  3489. * Resets the atomic state for @crtc by freeing the state pointer (which might
  3490. * be NULL, e.g. at driver load time) and allocating a new empty state object.
  3491. * @crtc: Pointer to drm crtc structure
  3492. */
  3493. static void sde_crtc_reset(struct drm_crtc *crtc)
  3494. {
  3495. struct sde_crtc *sde_crtc;
  3496. struct sde_crtc_state *cstate;
  3497. if (!crtc) {
  3498. SDE_ERROR("invalid crtc\n");
  3499. return;
  3500. }
  3501. /* revert suspend actions, if necessary */
  3502. if (!sde_crtc_is_reset_required(crtc)) {
  3503. SDE_DEBUG("avoiding reset for crtc:%d\n", crtc->base.id);
  3504. return;
  3505. }
  3506. /* remove previous state, if present */
  3507. if (crtc->state) {
  3508. sde_crtc_destroy_state(crtc, crtc->state);
  3509. crtc->state = 0;
  3510. }
  3511. sde_crtc = to_sde_crtc(crtc);
  3512. cstate = msm_property_alloc_state(&sde_crtc->property_info);
  3513. if (!cstate) {
  3514. SDE_ERROR("failed to allocate state\n");
  3515. return;
  3516. }
  3517. /* reset value helper */
  3518. msm_property_reset_state(&sde_crtc->property_info, cstate,
  3519. &cstate->property_state,
  3520. cstate->property_values);
  3521. _sde_crtc_set_input_fence_timeout(cstate);
  3522. cstate->base.crtc = crtc;
  3523. crtc->state = &cstate->base;
  3524. }
  3525. static void sde_crtc_clear_cached_mixer_cfg(struct drm_crtc *crtc)
  3526. {
  3527. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3528. struct sde_hw_mixer *hw_lm;
  3529. int lm_idx;
  3530. /* clearing lm cfg marks it dirty to force reprogramming next update */
  3531. for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) {
  3532. hw_lm = sde_crtc->mixers[lm_idx].hw_lm;
  3533. hw_lm->cfg.out_width = 0;
  3534. hw_lm->cfg.out_height = 0;
  3535. }
  3536. SDE_EVT32(DRMID(crtc));
  3537. }
  3538. void sde_crtc_reset_sw_state(struct drm_crtc *crtc)
  3539. {
  3540. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  3541. struct drm_plane *plane;
  3542. /* mark planes, mixers, and other blocks dirty for next update */
  3543. drm_atomic_crtc_for_each_plane(plane, crtc)
  3544. sde_plane_set_revalidate(plane, true);
  3545. /* mark mixers dirty for next update */
  3546. sde_crtc_clear_cached_mixer_cfg(crtc);
  3547. /* mark other properties which need to be dirty for next update */
  3548. set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, cstate->dirty);
  3549. if (cstate->num_ds_enabled)
  3550. set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
  3551. }
  3552. static void sde_crtc_post_ipc(struct drm_crtc *crtc)
  3553. {
  3554. struct sde_crtc *sde_crtc;
  3555. struct sde_crtc_state *cstate;
  3556. struct drm_encoder *encoder;
  3557. sde_crtc = to_sde_crtc(crtc);
  3558. cstate = to_sde_crtc_state(crtc->state);
  3559. /* restore encoder; crtc will be programmed during commit */
  3560. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  3561. sde_encoder_virt_restore(encoder);
  3562. /* restore UIDLE */
  3563. sde_core_perf_crtc_update_uidle(crtc, true);
  3564. sde_cp_crtc_post_ipc(crtc);
  3565. }
  3566. static void sde_crtc_mmrm_cb_notification(struct drm_crtc *crtc)
  3567. {
  3568. struct msm_drm_private *priv;
  3569. unsigned long requested_clk;
  3570. struct sde_kms *kms = NULL;
  3571. if (!crtc->dev->dev_private) {
  3572. pr_err("invalid crtc priv\n");
  3573. return;
  3574. }
  3575. priv = crtc->dev->dev_private;
  3576. kms = to_sde_kms(priv->kms);
  3577. if (!kms) {
  3578. SDE_ERROR("invalid parameters\n");
  3579. return;
  3580. }
  3581. requested_clk = sde_power_mmrm_get_requested_clk(&priv->phandle,
  3582. kms->perf.clk_name);
  3583. /* notify user space the reduced clk rate */
  3584. sde_crtc_event_notify(crtc, DRM_EVENT_MMRM_CB, sizeof(unsigned long), requested_clk);
  3585. SDE_DEBUG("crtc[%d]: MMRM cb notified clk:%d\n",
  3586. crtc->base.id, requested_clk);
  3587. }
  3588. static void sde_crtc_handle_power_event(u32 event_type, void *arg)
  3589. {
  3590. struct drm_crtc *crtc = arg;
  3591. struct sde_crtc *sde_crtc;
  3592. struct drm_encoder *encoder;
  3593. u32 power_on;
  3594. unsigned long flags;
  3595. struct sde_crtc_irq_info *node = NULL;
  3596. int ret = 0;
  3597. if (!crtc) {
  3598. SDE_ERROR("invalid crtc\n");
  3599. return;
  3600. }
  3601. sde_crtc = to_sde_crtc(crtc);
  3602. mutex_lock(&sde_crtc->crtc_lock);
  3603. SDE_EVT32(DRMID(crtc), event_type);
  3604. switch (event_type) {
  3605. case SDE_POWER_EVENT_POST_ENABLE:
  3606. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3607. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3608. ret = 0;
  3609. if (node->func)
  3610. ret = node->func(crtc, true, &node->irq);
  3611. if (ret)
  3612. SDE_ERROR("%s failed to enable event %x\n",
  3613. sde_crtc->name, node->event);
  3614. }
  3615. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3616. sde_crtc_post_ipc(crtc);
  3617. break;
  3618. case SDE_POWER_EVENT_PRE_DISABLE:
  3619. drm_for_each_encoder_mask(encoder, crtc->dev,
  3620. crtc->state->encoder_mask) {
  3621. /*
  3622. * disable the vsync source after updating the
  3623. * rsc state. rsc state update might have vsync wait
  3624. * and vsync source must be disabled after it.
  3625. * It will avoid generating any vsync from this point
  3626. * till mode-2 entry. It is SW workaround for HW
  3627. * limitation and should not be removed without
  3628. * checking the updated design.
  3629. */
  3630. sde_encoder_control_te(encoder, false);
  3631. }
  3632. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3633. node = NULL;
  3634. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3635. ret = 0;
  3636. if (node->func)
  3637. ret = node->func(crtc, false, &node->irq);
  3638. if (ret)
  3639. SDE_ERROR("%s failed to disable event %x\n",
  3640. sde_crtc->name, node->event);
  3641. }
  3642. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3643. sde_cp_crtc_pre_ipc(crtc);
  3644. break;
  3645. case SDE_POWER_EVENT_POST_DISABLE:
  3646. sde_crtc_reset_sw_state(crtc);
  3647. sde_cp_crtc_suspend(crtc);
  3648. power_on = 0;
  3649. sde_crtc_event_notify(crtc, DRM_EVENT_SDE_POWER, sizeof(u32), power_on);
  3650. break;
  3651. case SDE_POWER_EVENT_MMRM_CALLBACK:
  3652. sde_crtc_mmrm_cb_notification(crtc);
  3653. break;
  3654. default:
  3655. SDE_DEBUG("event:%d not handled\n", event_type);
  3656. break;
  3657. }
  3658. mutex_unlock(&sde_crtc->crtc_lock);
  3659. }
  3660. static void _sde_crtc_reset(struct drm_crtc *crtc)
  3661. {
  3662. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  3663. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  3664. /* mark mixer cfgs dirty before wiping them */
  3665. sde_crtc_clear_cached_mixer_cfg(crtc);
  3666. memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
  3667. sde_crtc->num_mixers = 0;
  3668. sde_crtc->mixers_swapped = false;
  3669. /* disable clk & bw control until clk & bw properties are set */
  3670. cstate->bw_control = false;
  3671. cstate->bw_split_vote = false;
  3672. sde_crtc_static_img_control(crtc, CACHE_STATE_DISABLED, false);
  3673. }
  3674. static void sde_crtc_disable(struct drm_crtc *crtc)
  3675. {
  3676. struct sde_kms *sde_kms;
  3677. struct sde_crtc *sde_crtc;
  3678. struct sde_crtc_state *cstate;
  3679. struct drm_encoder *encoder;
  3680. struct msm_drm_private *priv;
  3681. unsigned long flags;
  3682. struct sde_crtc_irq_info *node = NULL;
  3683. u32 power_on;
  3684. bool in_cont_splash = false;
  3685. int ret, i;
  3686. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
  3687. SDE_ERROR("invalid crtc\n");
  3688. return;
  3689. }
  3690. sde_kms = _sde_crtc_get_kms(crtc);
  3691. if (!sde_kms) {
  3692. SDE_ERROR("invalid kms\n");
  3693. return;
  3694. }
  3695. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3696. SDE_ERROR("power resource is not enabled\n");
  3697. return;
  3698. }
  3699. sde_crtc = to_sde_crtc(crtc);
  3700. cstate = to_sde_crtc_state(crtc->state);
  3701. priv = crtc->dev->dev_private;
  3702. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3703. drm_crtc_vblank_off(crtc);
  3704. mutex_lock(&sde_crtc->crtc_lock);
  3705. SDE_EVT32_VERBOSE(DRMID(crtc));
  3706. /* update color processing on suspend */
  3707. sde_cp_crtc_suspend(crtc);
  3708. mutex_unlock(&sde_crtc->crtc_lock);
  3709. kthread_flush_worker(&priv->event_thread[crtc->index].worker);
  3710. mutex_lock(&sde_crtc->crtc_lock);
  3711. kthread_cancel_delayed_work_sync(&sde_crtc->static_cache_read_work);
  3712. kthread_cancel_delayed_work_sync(&sde_crtc->idle_notify_work);
  3713. SDE_EVT32(DRMID(crtc), sde_crtc->enabled, crtc->state->active,
  3714. crtc->state->enable, sde_crtc->cached_encoder_mask);
  3715. sde_crtc->enabled = false;
  3716. sde_crtc->cached_encoder_mask = 0;
  3717. /* Try to disable uidle */
  3718. sde_core_perf_crtc_update_uidle(crtc, false);
  3719. if (atomic_read(&sde_crtc->frame_pending)) {
  3720. SDE_ERROR("crtc%d frame_pending%d\n", crtc->base.id,
  3721. atomic_read(&sde_crtc->frame_pending));
  3722. SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending),
  3723. SDE_EVTLOG_FUNC_CASE2);
  3724. sde_core_perf_crtc_release_bw(crtc);
  3725. atomic_set(&sde_crtc->frame_pending, 0);
  3726. }
  3727. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3728. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3729. ret = 0;
  3730. if (node->func)
  3731. ret = node->func(crtc, false, &node->irq);
  3732. if (ret)
  3733. SDE_ERROR("%s failed to disable event %x\n",
  3734. sde_crtc->name, node->event);
  3735. }
  3736. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3737. drm_for_each_encoder_mask(encoder, crtc->dev,
  3738. crtc->state->encoder_mask) {
  3739. if (sde_encoder_in_cont_splash(encoder)) {
  3740. in_cont_splash = true;
  3741. break;
  3742. }
  3743. }
  3744. /* avoid clk/bw downvote if cont-splash is enabled */
  3745. if (!in_cont_splash)
  3746. sde_core_perf_crtc_update(crtc, 0, true);
  3747. drm_for_each_encoder_mask(encoder, crtc->dev,
  3748. crtc->state->encoder_mask) {
  3749. sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
  3750. cstate->rsc_client = NULL;
  3751. cstate->rsc_update = false;
  3752. /*
  3753. * reset idle power-collapse to original state during suspend;
  3754. * user-mode will change the state on resume, if required
  3755. */
  3756. if (sde_kms->catalog->has_idle_pc)
  3757. sde_encoder_control_idle_pc(encoder, true);
  3758. }
  3759. if (sde_crtc->power_event) {
  3760. sde_power_handle_unregister_event(&priv->phandle,
  3761. sde_crtc->power_event);
  3762. sde_crtc->power_event = NULL;
  3763. }
  3764. /**
  3765. * All callbacks are unregistered and frame done waits are complete
  3766. * at this point. No buffers are accessed by hardware.
  3767. * reset the fence timeline if crtc will not be enabled for this commit
  3768. */
  3769. if (!crtc->state->active || !crtc->state->enable) {
  3770. sde_fence_signal(sde_crtc->output_fence,
  3771. ktime_get(), SDE_FENCE_RESET_TIMELINE);
  3772. for (i = 0; i < cstate->num_connectors; ++i)
  3773. sde_connector_commit_reset(cstate->connectors[i],
  3774. ktime_get());
  3775. }
  3776. _sde_crtc_reset(crtc);
  3777. sde_cp_crtc_disable(crtc);
  3778. power_on = 0;
  3779. sde_crtc_event_notify(crtc, DRM_EVENT_CRTC_POWER, sizeof(u32), power_on);
  3780. mutex_unlock(&sde_crtc->crtc_lock);
  3781. }
  3782. static void sde_crtc_enable(struct drm_crtc *crtc,
  3783. struct drm_crtc_state *old_crtc_state)
  3784. {
  3785. struct sde_crtc *sde_crtc;
  3786. struct drm_encoder *encoder;
  3787. struct msm_drm_private *priv;
  3788. unsigned long flags;
  3789. struct sde_crtc_irq_info *node = NULL;
  3790. int ret, i;
  3791. struct sde_crtc_state *cstate;
  3792. struct msm_display_mode *msm_mode;
  3793. if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
  3794. SDE_ERROR("invalid crtc\n");
  3795. return;
  3796. }
  3797. priv = crtc->dev->dev_private;
  3798. cstate = to_sde_crtc_state(crtc->state);
  3799. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  3800. SDE_ERROR("power resource is not enabled\n");
  3801. return;
  3802. }
  3803. SDE_DEBUG("crtc%d\n", crtc->base.id);
  3804. SDE_EVT32_VERBOSE(DRMID(crtc));
  3805. sde_crtc = to_sde_crtc(crtc);
  3806. /*
  3807. * Avoid drm_crtc_vblank_on during seamless DMS case
  3808. * when CRTC is already in enabled state
  3809. */
  3810. if (!sde_crtc->enabled) {
  3811. /* cache the encoder mask now for vblank work */
  3812. sde_crtc->cached_encoder_mask = crtc->state->encoder_mask;
  3813. /* max possible vsync_cnt(atomic_t) soft counter */
  3814. drm_crtc_set_max_vblank_count(crtc, INT_MAX);
  3815. drm_crtc_vblank_on(crtc);
  3816. }
  3817. mutex_lock(&sde_crtc->crtc_lock);
  3818. SDE_EVT32(DRMID(crtc), sde_crtc->enabled);
  3819. /*
  3820. * Try to enable uidle (if possible), we do this before the call
  3821. * to return early during seamless dms mode, so any fps
  3822. * change is also consider to enable/disable UIDLE
  3823. */
  3824. sde_core_perf_crtc_update_uidle(crtc, true);
  3825. msm_mode = sde_crtc_get_msm_mode(crtc->state);
  3826. if (!msm_mode){
  3827. SDE_ERROR("invalid msm mode, %s\n",
  3828. crtc->state->adjusted_mode.name);
  3829. return;
  3830. }
  3831. /* return early if crtc is already enabled, do this after UIDLE check */
  3832. if (sde_crtc->enabled) {
  3833. if (msm_is_mode_seamless_dms(msm_mode) ||
  3834. msm_is_mode_seamless_dyn_clk(msm_mode))
  3835. SDE_DEBUG("%s extra crtc enable expected during DMS\n",
  3836. sde_crtc->name);
  3837. else
  3838. WARN(1, "%s unexpected crtc enable\n", sde_crtc->name);
  3839. mutex_unlock(&sde_crtc->crtc_lock);
  3840. return;
  3841. }
  3842. drm_for_each_encoder_mask(encoder, crtc->dev,
  3843. crtc->state->encoder_mask) {
  3844. sde_encoder_register_frame_event_callback(encoder,
  3845. sde_crtc_frame_event_cb, crtc);
  3846. sde_crtc_static_img_control(crtc, CACHE_STATE_NORMAL,
  3847. sde_encoder_check_curr_mode(encoder,
  3848. MSM_DISPLAY_VIDEO_MODE));
  3849. }
  3850. sde_crtc->enabled = true;
  3851. sde_cp_crtc_enable(crtc);
  3852. /* update color processing on resume */
  3853. sde_cp_crtc_resume(crtc);
  3854. mutex_unlock(&sde_crtc->crtc_lock);
  3855. spin_lock_irqsave(&sde_crtc->spin_lock, flags);
  3856. list_for_each_entry(node, &sde_crtc->user_event_list, list) {
  3857. ret = 0;
  3858. if (node->func)
  3859. ret = node->func(crtc, true, &node->irq);
  3860. if (ret)
  3861. SDE_ERROR("%s failed to enable event %x\n",
  3862. sde_crtc->name, node->event);
  3863. }
  3864. spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
  3865. sde_crtc->power_event = sde_power_handle_register_event(
  3866. &priv->phandle,
  3867. SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE |
  3868. SDE_POWER_EVENT_PRE_DISABLE | SDE_POWER_EVENT_MMRM_CALLBACK,
  3869. sde_crtc_handle_power_event, crtc, sde_crtc->name);
  3870. /* Enable ESD thread */
  3871. for (i = 0; i < cstate->num_connectors; i++)
  3872. sde_connector_schedule_status_work(cstate->connectors[i], true);
  3873. }
  3874. /* no input validation - caller API has all the checks */
  3875. static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state,
  3876. struct plane_state pstates[], int cnt)
  3877. {
  3878. struct sde_crtc_state *cstate = to_sde_crtc_state(state);
  3879. struct drm_display_mode *mode = &state->adjusted_mode;
  3880. const struct drm_plane_state *pstate;
  3881. struct sde_plane_state *sde_pstate;
  3882. int rc = 0, i;
  3883. /* Check dim layer rect bounds and stage */
  3884. for (i = 0; i < cstate->num_dim_layers; i++) {
  3885. if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y,
  3886. cstate->dim_layer[i].rect.h, mode->vdisplay)) ||
  3887. (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x,
  3888. cstate->dim_layer[i].rect.w, mode->hdisplay)) ||
  3889. (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) ||
  3890. (!cstate->dim_layer[i].rect.w) ||
  3891. (!cstate->dim_layer[i].rect.h)) {
  3892. SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
  3893. cstate->dim_layer[i].rect.x,
  3894. cstate->dim_layer[i].rect.y,
  3895. cstate->dim_layer[i].rect.w,
  3896. cstate->dim_layer[i].rect.h,
  3897. cstate->dim_layer[i].stage);
  3898. SDE_ERROR("display: %dx%d\n", mode->hdisplay,
  3899. mode->vdisplay);
  3900. rc = -E2BIG;
  3901. goto end;
  3902. }
  3903. }
  3904. /* log all src and excl_rect, useful for debugging */
  3905. for (i = 0; i < cnt; i++) {
  3906. pstate = pstates[i].drm_pstate;
  3907. sde_pstate = to_sde_plane_state(pstate);
  3908. SDE_DEBUG("p %d z %d src{%d,%d,%d,%d} excl_rect{%d,%d,%d,%d}\n",
  3909. pstate->plane->base.id, pstates[i].stage,
  3910. pstate->crtc_x, pstate->crtc_y,
  3911. pstate->crtc_w, pstate->crtc_h,
  3912. sde_pstate->excl_rect.x, sde_pstate->excl_rect.y,
  3913. sde_pstate->excl_rect.w, sde_pstate->excl_rect.h);
  3914. }
  3915. end:
  3916. return rc;
  3917. }
  3918. static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
  3919. struct drm_crtc_state *state, struct plane_state pstates[],
  3920. struct sde_crtc_state *cstate, struct sde_kms *sde_kms,
  3921. int cnt, int secure, int fb_ns, int fb_sec, int fb_sec_dir)
  3922. {
  3923. struct drm_plane *plane;
  3924. int i;
  3925. if (secure == SDE_DRM_SEC_ONLY) {
  3926. /*
  3927. * validate planes - only fb_sec_dir is allowed during sec_crtc
  3928. * - fb_sec_dir is for secure camera preview and
  3929. * secure display use case
  3930. * - fb_sec is for secure video playback
  3931. * - fb_ns is for normal non secure use cases
  3932. */
  3933. if (fb_ns || fb_sec) {
  3934. SDE_ERROR(
  3935. "crtc%d: invalid fb_modes Sec:%d, NS:%d, Sec_Dir:%d\n",
  3936. DRMID(crtc), fb_sec, fb_ns, fb_sec_dir);
  3937. return -EINVAL;
  3938. }
  3939. /*
  3940. * - only one blending stage is allowed in sec_crtc
  3941. * - validate if pipe is allowed for sec-ui updates
  3942. */
  3943. for (i = 1; i < cnt; i++) {
  3944. if (!pstates[i].drm_pstate
  3945. || !pstates[i].drm_pstate->plane) {
  3946. SDE_ERROR("crtc%d: invalid pstate at i:%d\n",
  3947. DRMID(crtc), i);
  3948. return -EINVAL;
  3949. }
  3950. plane = pstates[i].drm_pstate->plane;
  3951. if (!sde_plane_is_sec_ui_allowed(plane)) {
  3952. SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",
  3953. DRMID(crtc), plane->base.id);
  3954. return -EINVAL;
  3955. } else if (pstates[i].stage != pstates[i-1].stage) {
  3956. SDE_ERROR(
  3957. "crtc%d: invalid blend stages %d:%d, %d:%d\n",
  3958. DRMID(crtc), i, pstates[i].stage,
  3959. i-1, pstates[i-1].stage);
  3960. return -EINVAL;
  3961. }
  3962. }
  3963. /* check if all the dim_layers are in the same stage */
  3964. for (i = 1; i < cstate->num_dim_layers; i++) {
  3965. if (cstate->dim_layer[i].stage !=
  3966. cstate->dim_layer[i-1].stage) {
  3967. SDE_ERROR(
  3968. "crtc%d: invalid dimlayer stage %d:%d, %d:%d\n",
  3969. DRMID(crtc),
  3970. i, cstate->dim_layer[i].stage,
  3971. i-1, cstate->dim_layer[i-1].stage);
  3972. return -EINVAL;
  3973. }
  3974. }
  3975. /*
  3976. * if secure-ui supported blendstage is specified,
  3977. * - fail empty commit
  3978. * - validate dim_layer or plane is staged in the supported
  3979. * blendstage
  3980. */
  3981. if (sde_kms->catalog->sui_supported_blendstage) {
  3982. int sec_stage = cnt ? pstates[0].sde_pstate->stage :
  3983. cstate->dim_layer[0].stage;
  3984. if (!sde_kms->catalog->has_base_layer)
  3985. sec_stage -= SDE_STAGE_0;
  3986. if ((!cnt && !cstate->num_dim_layers) ||
  3987. (sde_kms->catalog->sui_supported_blendstage
  3988. != sec_stage)) {
  3989. SDE_ERROR(
  3990. "crtc%d: empty cnt%d/dim%d or bad stage%d\n",
  3991. DRMID(crtc), cnt,
  3992. cstate->num_dim_layers, sec_stage);
  3993. return -EINVAL;
  3994. }
  3995. }
  3996. }
  3997. return 0;
  3998. }
  3999. static int _sde_crtc_check_secure_single_encoder(struct drm_crtc *crtc,
  4000. struct drm_crtc_state *state, int fb_sec_dir)
  4001. {
  4002. struct drm_encoder *encoder;
  4003. int encoder_cnt = 0;
  4004. if (fb_sec_dir) {
  4005. drm_for_each_encoder_mask(encoder, crtc->dev,
  4006. state->encoder_mask)
  4007. encoder_cnt++;
  4008. if (encoder_cnt > MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) {
  4009. SDE_ERROR("crtc:%d invalid number of encoders:%d\n",
  4010. DRMID(crtc), encoder_cnt);
  4011. return -EINVAL;
  4012. }
  4013. }
  4014. return 0;
  4015. }
  4016. static int _sde_crtc_check_secure_state_smmu_translation(struct drm_crtc *crtc,
  4017. struct drm_crtc_state *state, struct sde_kms *sde_kms, int secure,
  4018. int fb_ns, int fb_sec, int fb_sec_dir)
  4019. {
  4020. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  4021. struct drm_encoder *encoder;
  4022. int is_video_mode = false;
  4023. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  4024. if (sde_encoder_is_dsi_display(encoder))
  4025. is_video_mode |= sde_encoder_check_curr_mode(encoder,
  4026. MSM_DISPLAY_VIDEO_MODE);
  4027. }
  4028. /*
  4029. * Secure display to secure camera needs without direct
  4030. * transition is currently not allowed
  4031. */
  4032. if (fb_sec_dir && secure == SDE_DRM_SEC_NON_SEC &&
  4033. smmu_state->state != ATTACHED &&
  4034. smmu_state->secure_level == SDE_DRM_SEC_ONLY) {
  4035. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  4036. smmu_state->state, smmu_state->secure_level,
  4037. secure);
  4038. goto sec_err;
  4039. }
  4040. /*
  4041. * In video mode check for null commit before transition
  4042. * from secure to non secure and vice versa
  4043. */
  4044. if (is_video_mode && smmu_state &&
  4045. state->plane_mask && crtc->state->plane_mask &&
  4046. ((fb_sec_dir && ((smmu_state->state == ATTACHED) &&
  4047. (secure == SDE_DRM_SEC_ONLY))) ||
  4048. (fb_ns && ((smmu_state->state == DETACHED) ||
  4049. (smmu_state->state == DETACH_ALL_REQ))) ||
  4050. (fb_ns && ((smmu_state->state == DETACHED_SEC) ||
  4051. (smmu_state->state == DETACH_SEC_REQ)) &&
  4052. (smmu_state->secure_level == SDE_DRM_SEC_ONLY)))) {
  4053. SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,
  4054. smmu_state->state, smmu_state->secure_level,
  4055. secure, crtc->state->plane_mask, state->plane_mask);
  4056. goto sec_err;
  4057. }
  4058. return 0;
  4059. sec_err:
  4060. SDE_ERROR(
  4061. "crtc%d Invalid transition;sec%d state%d slvl%d ns%d sdir%d\n",
  4062. DRMID(crtc), secure, smmu_state->state,
  4063. smmu_state->secure_level, fb_ns, fb_sec_dir);
  4064. return -EINVAL;
  4065. }
  4066. static int _sde_crtc_check_secure_conn(struct drm_crtc *crtc,
  4067. struct drm_crtc_state *state, uint32_t fb_sec)
  4068. {
  4069. bool conn_secure = false, is_wb = false;
  4070. struct drm_connector *conn;
  4071. struct drm_connector_state *conn_state;
  4072. int i;
  4073. for_each_new_connector_in_state(state->state, conn, conn_state, i) {
  4074. if (conn_state && conn_state->crtc == crtc) {
  4075. if (conn->connector_type ==
  4076. DRM_MODE_CONNECTOR_VIRTUAL)
  4077. is_wb = true;
  4078. if (sde_connector_get_property(conn_state,
  4079. CONNECTOR_PROP_FB_TRANSLATION_MODE) ==
  4080. SDE_DRM_FB_SEC)
  4081. conn_secure = true;
  4082. }
  4083. }
  4084. /*
  4085. * If any input buffers are secure for wb,
  4086. * the output buffer must also be secure.
  4087. */
  4088. if (is_wb && fb_sec && !conn_secure) {
  4089. SDE_ERROR("crtc%d: input fb sec %d, output fb secure %d\n",
  4090. DRMID(crtc), fb_sec, conn_secure);
  4091. return -EINVAL;
  4092. }
  4093. return 0;
  4094. }
  4095. static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
  4096. struct drm_crtc_state *state, struct plane_state pstates[],
  4097. int cnt)
  4098. {
  4099. struct sde_crtc_state *cstate;
  4100. struct sde_kms *sde_kms;
  4101. uint32_t secure;
  4102. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  4103. int rc;
  4104. if (!crtc || !state) {
  4105. SDE_ERROR("invalid arguments\n");
  4106. return -EINVAL;
  4107. }
  4108. sde_kms = _sde_crtc_get_kms(crtc);
  4109. if (!sde_kms || !sde_kms->catalog) {
  4110. SDE_ERROR("invalid kms\n");
  4111. return -EINVAL;
  4112. }
  4113. cstate = to_sde_crtc_state(state);
  4114. secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL);
  4115. rc = sde_crtc_state_find_plane_fb_modes(state, &fb_ns,
  4116. &fb_sec, &fb_sec_dir);
  4117. if (rc)
  4118. return rc;
  4119. rc = _sde_crtc_check_secure_blend_config(crtc, state, pstates, cstate,
  4120. sde_kms, cnt, secure, fb_ns, fb_sec, fb_sec_dir);
  4121. if (rc)
  4122. return rc;
  4123. rc = _sde_crtc_check_secure_conn(crtc, state, fb_sec);
  4124. if (rc)
  4125. return rc;
  4126. /*
  4127. * secure_crtc is not allowed in a shared toppolgy
  4128. * across different encoders.
  4129. */
  4130. rc = _sde_crtc_check_secure_single_encoder(crtc, state, fb_sec_dir);
  4131. if (rc)
  4132. return rc;
  4133. rc = _sde_crtc_check_secure_state_smmu_translation(crtc, state, sde_kms,
  4134. secure, fb_ns, fb_sec, fb_sec_dir);
  4135. if (rc)
  4136. return rc;
  4137. SDE_DEBUG("crtc:%d Secure validation successful\n", DRMID(crtc));
  4138. return 0;
  4139. }
  4140. static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
  4141. struct drm_crtc_state *state,
  4142. struct drm_display_mode *mode,
  4143. struct plane_state *pstates,
  4144. struct drm_plane *plane,
  4145. struct sde_multirect_plane_states *multirect_plane,
  4146. int *cnt)
  4147. {
  4148. struct sde_crtc *sde_crtc;
  4149. struct sde_crtc_state *cstate;
  4150. const struct drm_plane_state *pstate;
  4151. const struct drm_plane_state *pipe_staged[SSPP_MAX];
  4152. int rc = 0, multirect_count = 0, i, mixer_width, mixer_height;
  4153. int inc_sde_stage = 0;
  4154. struct sde_kms *kms;
  4155. u32 blend_type;
  4156. sde_crtc = to_sde_crtc(crtc);
  4157. cstate = to_sde_crtc_state(state);
  4158. kms = _sde_crtc_get_kms(crtc);
  4159. if (!kms || !kms->catalog) {
  4160. SDE_ERROR("invalid kms\n");
  4161. return -EINVAL;
  4162. }
  4163. memset(pipe_staged, 0, sizeof(pipe_staged));
  4164. mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  4165. mixer_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  4166. if (cstate->num_ds_enabled)
  4167. mixer_width = mixer_width * cstate->num_ds_enabled;
  4168. drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
  4169. if (IS_ERR_OR_NULL(pstate)) {
  4170. rc = PTR_ERR(pstate);
  4171. SDE_ERROR("%s: failed to get plane%d state, %d\n",
  4172. sde_crtc->name, plane->base.id, rc);
  4173. return rc;
  4174. }
  4175. if (*cnt >= SDE_PSTATES_MAX)
  4176. continue;
  4177. pstates[*cnt].sde_pstate = to_sde_plane_state(pstate);
  4178. pstates[*cnt].drm_pstate = pstate;
  4179. pstates[*cnt].stage = sde_plane_get_property(
  4180. pstates[*cnt].sde_pstate, PLANE_PROP_ZPOS);
  4181. pstates[*cnt].pipe_id = sde_plane_pipe(plane);
  4182. blend_type = sde_plane_get_property(pstates[*cnt].sde_pstate,
  4183. PLANE_PROP_BLEND_OP);
  4184. if (!kms->catalog->has_base_layer)
  4185. inc_sde_stage = SDE_STAGE_0;
  4186. /* check dim layer stage with every plane */
  4187. for (i = 0; i < cstate->num_dim_layers; i++) {
  4188. if (cstate->dim_layer[i].stage ==
  4189. (pstates[*cnt].stage + inc_sde_stage)) {
  4190. SDE_ERROR(
  4191. "plane:%d/dim_layer:%i-same stage:%d\n",
  4192. plane->base.id, i,
  4193. cstate->dim_layer[i].stage);
  4194. return -EINVAL;
  4195. }
  4196. }
  4197. if (pipe_staged[pstates[*cnt].pipe_id]) {
  4198. multirect_plane[multirect_count].r0 =
  4199. pipe_staged[pstates[*cnt].pipe_id];
  4200. multirect_plane[multirect_count].r1 = pstate;
  4201. multirect_count++;
  4202. pipe_staged[pstates[*cnt].pipe_id] = NULL;
  4203. } else {
  4204. pipe_staged[pstates[*cnt].pipe_id] = pstate;
  4205. }
  4206. (*cnt)++;
  4207. if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h,
  4208. mode->vdisplay) ||
  4209. CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w,
  4210. mode->hdisplay)) {
  4211. SDE_ERROR("invalid vertical/horizontal destination\n");
  4212. SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n",
  4213. pstate->crtc_y, pstate->crtc_h, mode->vdisplay,
  4214. pstate->crtc_x, pstate->crtc_w, mode->hdisplay);
  4215. return -E2BIG;
  4216. }
  4217. if (blend_type != SDE_DRM_BLEND_OP_SKIP && cstate->num_ds_enabled &&
  4218. ((pstate->crtc_h > mixer_height) ||
  4219. (pstate->crtc_w > mixer_width))) {
  4220. SDE_ERROR("plane w/h:%x*%x > mixer w/h:%x*%x\n",
  4221. pstate->crtc_w, pstate->crtc_h,
  4222. mixer_width, mixer_height);
  4223. return -E2BIG;
  4224. }
  4225. }
  4226. for (i = 1; i < SSPP_MAX; i++) {
  4227. if (pipe_staged[i]) {
  4228. sde_plane_clear_multirect(pipe_staged[i]);
  4229. if (is_sde_plane_virtual(pipe_staged[i]->plane)) {
  4230. struct sde_plane_state *psde_state;
  4231. SDE_DEBUG("r1 only virt plane:%d staged\n",
  4232. pipe_staged[i]->plane->base.id);
  4233. psde_state = to_sde_plane_state(
  4234. pipe_staged[i]);
  4235. psde_state->multirect_index = SDE_SSPP_RECT_1;
  4236. }
  4237. }
  4238. }
  4239. for (i = 0; i < multirect_count; i++) {
  4240. if (sde_plane_validate_multirect_v2(&multirect_plane[i])) {
  4241. SDE_ERROR(
  4242. "multirect validation failed for planes (%d - %d)\n",
  4243. multirect_plane[i].r0->plane->base.id,
  4244. multirect_plane[i].r1->plane->base.id);
  4245. return -EINVAL;
  4246. }
  4247. }
  4248. return rc;
  4249. }
  4250. static int _sde_crtc_noise_layer_check_zpos(struct sde_crtc_state *cstate,
  4251. u32 zpos) {
  4252. if (!test_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty) ||
  4253. !cstate->noise_layer_en) {
  4254. SDE_DEBUG("noise layer not enabled %d\n", cstate->noise_layer_en);
  4255. return 0;
  4256. }
  4257. if (cstate->layer_cfg.zposn == zpos ||
  4258. cstate->layer_cfg.zposattn == zpos) {
  4259. SDE_ERROR("invalid zpos %d zposn %d zposattn %d\n", zpos,
  4260. cstate->layer_cfg.zposn, cstate->layer_cfg.zposattn);
  4261. return -EINVAL;
  4262. }
  4263. return 0;
  4264. }
  4265. static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
  4266. struct sde_crtc *sde_crtc,
  4267. struct plane_state *pstates,
  4268. struct sde_crtc_state *cstate,
  4269. struct drm_display_mode *mode,
  4270. int cnt)
  4271. {
  4272. int rc = 0, i, z_pos;
  4273. u32 zpos_cnt = 0;
  4274. struct drm_crtc *crtc;
  4275. struct sde_kms *kms;
  4276. enum sde_layout layout;
  4277. crtc = &sde_crtc->base;
  4278. kms = _sde_crtc_get_kms(crtc);
  4279. if (!kms || !kms->catalog) {
  4280. SDE_ERROR("Invalid kms\n");
  4281. return -EINVAL;
  4282. }
  4283. sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
  4284. rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);
  4285. if (rc)
  4286. return rc;
  4287. if (!sde_is_custom_client()) {
  4288. int stage_old = pstates[0].stage;
  4289. z_pos = 0;
  4290. for (i = 0; i < cnt; i++) {
  4291. if (stage_old != pstates[i].stage)
  4292. ++z_pos;
  4293. stage_old = pstates[i].stage;
  4294. pstates[i].stage = z_pos;
  4295. }
  4296. }
  4297. z_pos = -1;
  4298. layout = SDE_LAYOUT_NONE;
  4299. for (i = 0; i < cnt; i++) {
  4300. /* reset counts at every new blend stage */
  4301. if (pstates[i].stage != z_pos ||
  4302. pstates[i].sde_pstate->layout != layout) {
  4303. zpos_cnt = 0;
  4304. z_pos = pstates[i].stage;
  4305. layout = pstates[i].sde_pstate->layout;
  4306. }
  4307. /* verify z_pos setting before using it */
  4308. if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
  4309. SDE_ERROR("> %d plane stages assigned\n",
  4310. SDE_STAGE_MAX - SDE_STAGE_0);
  4311. return -EINVAL;
  4312. } else if (zpos_cnt == 2) {
  4313. SDE_ERROR("> 2 planes @ stage %d\n", z_pos);
  4314. return -EINVAL;
  4315. } else {
  4316. zpos_cnt++;
  4317. }
  4318. rc = _sde_crtc_noise_layer_check_zpos(cstate, z_pos);
  4319. if (rc)
  4320. break;
  4321. if (!kms->catalog->has_base_layer)
  4322. pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
  4323. else
  4324. pstates[i].sde_pstate->stage = z_pos;
  4325. SDE_DEBUG("%s: layout %d, zpos %d", sde_crtc->name, layout,
  4326. z_pos);
  4327. }
  4328. return rc;
  4329. }
  4330. static int _sde_crtc_atomic_check_pstates(struct drm_crtc *crtc,
  4331. struct drm_crtc_state *state,
  4332. struct plane_state *pstates,
  4333. struct sde_multirect_plane_states *multirect_plane)
  4334. {
  4335. struct sde_crtc *sde_crtc;
  4336. struct sde_crtc_state *cstate;
  4337. struct sde_kms *kms;
  4338. struct drm_plane *plane = NULL;
  4339. struct drm_display_mode *mode;
  4340. int rc = 0, cnt = 0;
  4341. kms = _sde_crtc_get_kms(crtc);
  4342. if (!kms || !kms->catalog) {
  4343. SDE_ERROR("invalid parameters\n");
  4344. return -EINVAL;
  4345. }
  4346. sde_crtc = to_sde_crtc(crtc);
  4347. cstate = to_sde_crtc_state(state);
  4348. mode = &state->adjusted_mode;
  4349. /* get plane state for all drm planes associated with crtc state */
  4350. rc = _sde_crtc_check_get_pstates(crtc, state, mode, pstates,
  4351. plane, multirect_plane, &cnt);
  4352. if (rc)
  4353. return rc;
  4354. /* assign mixer stages based on sorted zpos property */
  4355. rc = _sde_crtc_check_zpos(state, sde_crtc, pstates, cstate, mode, cnt);
  4356. if (rc)
  4357. return rc;
  4358. rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);
  4359. if (rc)
  4360. return rc;
  4361. /*
  4362. * validate and set source split:
  4363. * use pstates sorted by stage to check planes on same stage
  4364. * we assume that all pipes are in source split so its valid to compare
  4365. * without taking into account left/right mixer placement
  4366. */
  4367. rc = _sde_crtc_validate_src_split_order(crtc, pstates, cnt);
  4368. if (rc)
  4369. return rc;
  4370. return 0;
  4371. }
  4372. static int _sde_crtc_check_plane_layout(struct drm_crtc *crtc,
  4373. struct drm_crtc_state *crtc_state)
  4374. {
  4375. struct sde_kms *kms;
  4376. struct drm_plane *plane;
  4377. struct drm_plane_state *plane_state;
  4378. struct sde_plane_state *pstate;
  4379. int layout_split;
  4380. kms = _sde_crtc_get_kms(crtc);
  4381. if (!kms || !kms->catalog) {
  4382. SDE_ERROR("invalid parameters\n");
  4383. return -EINVAL;
  4384. }
  4385. if (!sde_rm_topology_is_group(&kms->rm, crtc_state,
  4386. SDE_RM_TOPOLOGY_GROUP_QUADPIPE))
  4387. return 0;
  4388. drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
  4389. plane_state = drm_atomic_get_existing_plane_state(
  4390. crtc_state->state, plane);
  4391. if (!plane_state)
  4392. continue;
  4393. pstate = to_sde_plane_state(plane_state);
  4394. layout_split = crtc_state->mode.hdisplay >> 1;
  4395. if (plane_state->crtc_x >= layout_split) {
  4396. plane_state->crtc_x -= layout_split;
  4397. pstate->layout_offset = layout_split;
  4398. pstate->layout = SDE_LAYOUT_RIGHT;
  4399. } else {
  4400. pstate->layout_offset = -1;
  4401. pstate->layout = SDE_LAYOUT_LEFT;
  4402. }
  4403. SDE_DEBUG("plane%d updated: crtc_x=%d layout=%d\n",
  4404. DRMID(plane), plane_state->crtc_x,
  4405. pstate->layout);
  4406. /* check layout boundary */
  4407. if (CHECK_LAYER_BOUNDS(plane_state->crtc_x,
  4408. plane_state->crtc_w, layout_split)) {
  4409. SDE_ERROR("invalid horizontal destination\n");
  4410. SDE_ERROR("x:%d w:%d hdisp:%d layout:%d\n",
  4411. plane_state->crtc_x,
  4412. plane_state->crtc_w,
  4413. layout_split, pstate->layout);
  4414. return -E2BIG;
  4415. }
  4416. }
  4417. return 0;
  4418. }
  4419. static int sde_crtc_atomic_check(struct drm_crtc *crtc,
  4420. struct drm_crtc_state *state)
  4421. {
  4422. struct drm_device *dev;
  4423. struct sde_crtc *sde_crtc;
  4424. struct plane_state *pstates = NULL;
  4425. struct sde_crtc_state *cstate;
  4426. struct drm_display_mode *mode;
  4427. int rc = 0;
  4428. struct sde_multirect_plane_states *multirect_plane = NULL;
  4429. struct drm_connector *conn;
  4430. struct drm_connector_list_iter conn_iter;
  4431. if (!crtc) {
  4432. SDE_ERROR("invalid crtc\n");
  4433. return -EINVAL;
  4434. }
  4435. dev = crtc->dev;
  4436. sde_crtc = to_sde_crtc(crtc);
  4437. cstate = to_sde_crtc_state(state);
  4438. if (!state->enable || !state->active) {
  4439. SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
  4440. crtc->base.id, state->enable, state->active);
  4441. goto end;
  4442. }
  4443. pstates = kcalloc(SDE_PSTATES_MAX,
  4444. sizeof(struct plane_state), GFP_KERNEL);
  4445. multirect_plane = kcalloc(SDE_MULTIRECT_PLANE_MAX,
  4446. sizeof(struct sde_multirect_plane_states),
  4447. GFP_KERNEL);
  4448. if (!pstates || !multirect_plane) {
  4449. rc = -ENOMEM;
  4450. goto end;
  4451. }
  4452. mode = &state->adjusted_mode;
  4453. SDE_DEBUG("%s: check", sde_crtc->name);
  4454. /* force a full mode set if active state changed */
  4455. if (state->active_changed)
  4456. state->mode_changed = true;
  4457. /* identify connectors attached to this crtc */
  4458. cstate->num_connectors = 0;
  4459. drm_connector_list_iter_begin(dev, &conn_iter);
  4460. drm_for_each_connector_iter(conn, &conn_iter)
  4461. if ((state->connector_mask & (1 << drm_connector_index(conn)))
  4462. && cstate->num_connectors < MAX_CONNECTORS) {
  4463. cstate->connectors[cstate->num_connectors++] = conn;
  4464. }
  4465. drm_connector_list_iter_end(&conn_iter);
  4466. rc = _sde_crtc_check_dest_scaler_data(crtc, state);
  4467. if (rc) {
  4468. SDE_ERROR("crtc%d failed dest scaler check %d\n",
  4469. crtc->base.id, rc);
  4470. goto end;
  4471. }
  4472. rc = _sde_crtc_check_plane_layout(crtc, state);
  4473. if (rc) {
  4474. SDE_ERROR("crtc%d failed plane layout check %d\n",
  4475. crtc->base.id, rc);
  4476. goto end;
  4477. }
  4478. _sde_crtc_setup_is_ppsplit(state);
  4479. _sde_crtc_setup_lm_bounds(crtc, state);
  4480. rc = _sde_crtc_atomic_check_pstates(crtc, state, pstates,
  4481. multirect_plane);
  4482. if (rc) {
  4483. SDE_ERROR("crtc%d failed pstate check %d\n", crtc->base.id, rc);
  4484. goto end;
  4485. }
  4486. rc = sde_core_perf_crtc_check(crtc, state);
  4487. if (rc) {
  4488. SDE_ERROR("crtc%d failed performance check %d\n",
  4489. crtc->base.id, rc);
  4490. goto end;
  4491. }
  4492. rc = _sde_crtc_check_rois(crtc, state);
  4493. if (rc) {
  4494. SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc);
  4495. goto end;
  4496. }
  4497. rc = sde_cp_crtc_check_properties(crtc, state);
  4498. if (rc) {
  4499. SDE_ERROR("crtc%d failed cp properties check %d\n",
  4500. crtc->base.id, rc);
  4501. goto end;
  4502. }
  4503. end:
  4504. kfree(pstates);
  4505. kfree(multirect_plane);
  4506. return rc;
  4507. }
  4508. /**
  4509. * sde_crtc_get_num_datapath - get the number of datapath active
  4510. * of primary connector
  4511. * @crtc: Pointer to DRM crtc object
  4512. * @connector: Pointer to DRM connector object of WB in CWB case
  4513. */
  4514. int sde_crtc_get_num_datapath(struct drm_crtc *crtc,
  4515. struct drm_connector *connector)
  4516. {
  4517. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  4518. struct sde_connector_state *sde_conn_state = NULL;
  4519. struct drm_connector *conn;
  4520. struct drm_connector_list_iter conn_iter;
  4521. if (!sde_crtc || !connector) {
  4522. SDE_DEBUG("Invalid argument\n");
  4523. return 0;
  4524. }
  4525. if (sde_crtc->num_mixers)
  4526. return sde_crtc->num_mixers;
  4527. drm_connector_list_iter_begin(crtc->dev, &conn_iter);
  4528. drm_for_each_connector_iter(conn, &conn_iter) {
  4529. if (conn->state && conn->state->crtc == crtc &&
  4530. conn != connector)
  4531. sde_conn_state = to_sde_connector_state(conn->state);
  4532. }
  4533. drm_connector_list_iter_end(&conn_iter);
  4534. if (sde_conn_state)
  4535. return sde_conn_state->mode_info.topology.num_lm;
  4536. return 0;
  4537. }
  4538. int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
  4539. {
  4540. struct sde_crtc *sde_crtc;
  4541. int ret;
  4542. if (!crtc) {
  4543. SDE_ERROR("invalid crtc\n");
  4544. return -EINVAL;
  4545. }
  4546. sde_crtc = to_sde_crtc(crtc);
  4547. ret = _sde_crtc_vblank_enable(sde_crtc, en);
  4548. if (ret)
  4549. SDE_ERROR("%s vblank enable failed: %d\n",
  4550. sde_crtc->name, ret);
  4551. return 0;
  4552. }
  4553. static u32 sde_crtc_get_vblank_counter(struct drm_crtc *crtc)
  4554. {
  4555. struct drm_encoder *encoder;
  4556. struct sde_crtc *sde_crtc;
  4557. if (!crtc)
  4558. return 0;
  4559. sde_crtc = to_sde_crtc(crtc);
  4560. drm_for_each_encoder_mask(encoder, crtc->dev, sde_crtc->cached_encoder_mask) {
  4561. if (sde_encoder_in_clone_mode(encoder))
  4562. continue;
  4563. return sde_encoder_get_frame_count(encoder);
  4564. }
  4565. return 0;
  4566. }
  4567. static bool sde_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
  4568. ktime_t *tvblank, bool in_vblank_irq)
  4569. {
  4570. struct drm_encoder *encoder;
  4571. struct sde_crtc *sde_crtc;
  4572. if (!crtc)
  4573. return false;
  4574. sde_crtc = to_sde_crtc(crtc);
  4575. drm_for_each_encoder_mask(encoder, crtc->dev, sde_crtc->cached_encoder_mask) {
  4576. if (sde_encoder_in_clone_mode(encoder))
  4577. continue;
  4578. return sde_encoder_get_vblank_timestamp(encoder, tvblank);
  4579. }
  4580. return false;
  4581. }
  4582. static void sde_crtc_install_dest_scale_properties(struct sde_crtc *sde_crtc,
  4583. struct sde_mdss_cfg *catalog, struct sde_kms_info *info)
  4584. {
  4585. sde_kms_info_add_keyint(info, "has_dest_scaler",
  4586. catalog->mdp[0].has_dest_scaler);
  4587. sde_kms_info_add_keyint(info, "dest_scaler_count",
  4588. catalog->ds_count);
  4589. if (catalog->ds[0].top) {
  4590. sde_kms_info_add_keyint(info,
  4591. "max_dest_scaler_input_width",
  4592. catalog->ds[0].top->maxinputwidth);
  4593. sde_kms_info_add_keyint(info,
  4594. "max_dest_scaler_output_width",
  4595. catalog->ds[0].top->maxoutputwidth);
  4596. sde_kms_info_add_keyint(info, "max_dest_scale_up",
  4597. catalog->ds[0].top->maxupscale);
  4598. }
  4599. if (catalog->ds[0].features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  4600. msm_property_install_volatile_range(
  4601. &sde_crtc->property_info, "dest_scaler",
  4602. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4603. msm_property_install_blob(&sde_crtc->property_info,
  4604. "ds_lut_ed", 0,
  4605. CRTC_PROP_DEST_SCALER_LUT_ED);
  4606. msm_property_install_blob(&sde_crtc->property_info,
  4607. "ds_lut_cir", 0,
  4608. CRTC_PROP_DEST_SCALER_LUT_CIR);
  4609. msm_property_install_blob(&sde_crtc->property_info,
  4610. "ds_lut_sep", 0,
  4611. CRTC_PROP_DEST_SCALER_LUT_SEP);
  4612. } else if (catalog->ds[0].features
  4613. & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  4614. msm_property_install_volatile_range(
  4615. &sde_crtc->property_info, "dest_scaler",
  4616. 0x0, 0, ~0, 0, CRTC_PROP_DEST_SCALER);
  4617. }
  4618. }
  4619. static void sde_crtc_install_perf_properties(struct sde_crtc *sde_crtc,
  4620. struct sde_kms *sde_kms, struct sde_mdss_cfg *catalog,
  4621. struct sde_kms_info *info)
  4622. {
  4623. msm_property_install_range(&sde_crtc->property_info,
  4624. "core_clk", 0x0, 0, U64_MAX,
  4625. sde_kms->perf.max_core_clk_rate,
  4626. CRTC_PROP_CORE_CLK);
  4627. msm_property_install_range(&sde_crtc->property_info,
  4628. "core_ab", 0x0, 0, U64_MAX,
  4629. catalog->perf.max_bw_high * 1000ULL,
  4630. CRTC_PROP_CORE_AB);
  4631. msm_property_install_range(&sde_crtc->property_info,
  4632. "core_ib", 0x0, 0, U64_MAX,
  4633. catalog->perf.max_bw_high * 1000ULL,
  4634. CRTC_PROP_CORE_IB);
  4635. msm_property_install_range(&sde_crtc->property_info,
  4636. "llcc_ab", 0x0, 0, U64_MAX,
  4637. catalog->perf.max_bw_high * 1000ULL,
  4638. CRTC_PROP_LLCC_AB);
  4639. msm_property_install_range(&sde_crtc->property_info,
  4640. "llcc_ib", 0x0, 0, U64_MAX,
  4641. catalog->perf.max_bw_high * 1000ULL,
  4642. CRTC_PROP_LLCC_IB);
  4643. msm_property_install_range(&sde_crtc->property_info,
  4644. "dram_ab", 0x0, 0, U64_MAX,
  4645. catalog->perf.max_bw_high * 1000ULL,
  4646. CRTC_PROP_DRAM_AB);
  4647. msm_property_install_range(&sde_crtc->property_info,
  4648. "dram_ib", 0x0, 0, U64_MAX,
  4649. catalog->perf.max_bw_high * 1000ULL,
  4650. CRTC_PROP_DRAM_IB);
  4651. msm_property_install_range(&sde_crtc->property_info,
  4652. "rot_prefill_bw", 0, 0, U64_MAX,
  4653. catalog->perf.max_bw_high * 1000ULL,
  4654. CRTC_PROP_ROT_PREFILL_BW);
  4655. msm_property_install_range(&sde_crtc->property_info,
  4656. "rot_clk", 0, 0, U64_MAX,
  4657. sde_kms->perf.max_core_clk_rate,
  4658. CRTC_PROP_ROT_CLK);
  4659. if (catalog->perf.max_bw_low)
  4660. sde_kms_info_add_keyint(info, "max_bandwidth_low",
  4661. catalog->perf.max_bw_low * 1000LL);
  4662. if (catalog->perf.max_bw_high)
  4663. sde_kms_info_add_keyint(info, "max_bandwidth_high",
  4664. catalog->perf.max_bw_high * 1000LL);
  4665. if (catalog->perf.min_core_ib)
  4666. sde_kms_info_add_keyint(info, "min_core_ib",
  4667. catalog->perf.min_core_ib * 1000LL);
  4668. if (catalog->perf.min_llcc_ib)
  4669. sde_kms_info_add_keyint(info, "min_llcc_ib",
  4670. catalog->perf.min_llcc_ib * 1000LL);
  4671. if (catalog->perf.min_dram_ib)
  4672. sde_kms_info_add_keyint(info, "min_dram_ib",
  4673. catalog->perf.min_dram_ib * 1000LL);
  4674. if (sde_kms->perf.max_core_clk_rate)
  4675. sde_kms_info_add_keyint(info, "max_mdp_clk",
  4676. sde_kms->perf.max_core_clk_rate);
  4677. }
  4678. static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
  4679. struct sde_mdss_cfg *catalog)
  4680. {
  4681. sde_kms_info_reset(info);
  4682. sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
  4683. sde_kms_info_add_keyint(info, "max_linewidth",
  4684. catalog->max_mixer_width);
  4685. sde_kms_info_add_keyint(info, "max_blendstages",
  4686. catalog->max_mixer_blendstages);
  4687. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED2)
  4688. sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
  4689. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3)
  4690. sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
  4691. if (catalog->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3LITE)
  4692. sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");
  4693. if (catalog->ubwc_version) {
  4694. sde_kms_info_add_keyint(info, "UBWC version",
  4695. catalog->ubwc_version);
  4696. sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
  4697. catalog->macrotile_mode);
  4698. sde_kms_info_add_keyint(info, "UBWC highest banking bit",
  4699. catalog->mdp[0].highest_bank_bit);
  4700. sde_kms_info_add_keyint(info, "UBWC swizzle",
  4701. catalog->mdp[0].ubwc_swizzle);
  4702. }
  4703. if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
  4704. sde_kms_info_add_keystr(info, "DDR version", "DDR4");
  4705. else
  4706. sde_kms_info_add_keystr(info, "DDR version", "DDR5");
  4707. if (sde_is_custom_client()) {
  4708. /* No support for SMART_DMA_V1 yet */
  4709. if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
  4710. sde_kms_info_add_keystr(info,
  4711. "smart_dma_rev", "smart_dma_v2");
  4712. else if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2p5)
  4713. sde_kms_info_add_keystr(info,
  4714. "smart_dma_rev", "smart_dma_v2p5");
  4715. }
  4716. sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
  4717. sde_kms_info_add_keyint(info, "has_hdr", catalog->has_hdr);
  4718. sde_kms_info_add_keyint(info, "has_hdr_plus", catalog->has_hdr_plus);
  4719. sde_kms_info_add_keyint(info, "skip_inline_rot_threshold",
  4720. catalog->skip_inline_rot_threshold);
  4721. if (catalog->uidle_cfg.uidle_rev)
  4722. sde_kms_info_add_keyint(info, "has_uidle",
  4723. true);
  4724. sde_kms_info_add_keystr(info, "core_ib_ff",
  4725. catalog->perf.core_ib_ff);
  4726. sde_kms_info_add_keystr(info, "core_clk_ff",
  4727. catalog->perf.core_clk_ff);
  4728. sde_kms_info_add_keystr(info, "comp_ratio_rt",
  4729. catalog->perf.comp_ratio_rt);
  4730. sde_kms_info_add_keystr(info, "comp_ratio_nrt",
  4731. catalog->perf.comp_ratio_nrt);
  4732. sde_kms_info_add_keyint(info, "dest_scale_prefill_lines",
  4733. catalog->perf.dest_scale_prefill_lines);
  4734. sde_kms_info_add_keyint(info, "undersized_prefill_lines",
  4735. catalog->perf.undersized_prefill_lines);
  4736. sde_kms_info_add_keyint(info, "macrotile_prefill_lines",
  4737. catalog->perf.macrotile_prefill_lines);
  4738. sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines",
  4739. catalog->perf.yuv_nv12_prefill_lines);
  4740. sde_kms_info_add_keyint(info, "linear_prefill_lines",
  4741. catalog->perf.linear_prefill_lines);
  4742. sde_kms_info_add_keyint(info, "downscaling_prefill_lines",
  4743. catalog->perf.downscaling_prefill_lines);
  4744. sde_kms_info_add_keyint(info, "xtra_prefill_lines",
  4745. catalog->perf.xtra_prefill_lines);
  4746. sde_kms_info_add_keyint(info, "amortizable_threshold",
  4747. catalog->perf.amortizable_threshold);
  4748. sde_kms_info_add_keyint(info, "min_prefill_lines",
  4749. catalog->perf.min_prefill_lines);
  4750. sde_kms_info_add_keyint(info, "num_mnoc_ports",
  4751. catalog->perf.num_mnoc_ports);
  4752. sde_kms_info_add_keyint(info, "axi_bus_width",
  4753. catalog->perf.axi_bus_width);
  4754. sde_kms_info_add_keyint(info, "sec_ui_blendstage",
  4755. catalog->sui_supported_blendstage);
  4756. if (catalog->ubwc_bw_calc_version)
  4757. sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",
  4758. catalog->ubwc_bw_calc_version);
  4759. }
  4760. /**
  4761. * sde_crtc_install_properties - install all drm properties for crtc
  4762. * @crtc: Pointer to drm crtc structure
  4763. */
  4764. static void sde_crtc_install_properties(struct drm_crtc *crtc,
  4765. struct sde_mdss_cfg *catalog)
  4766. {
  4767. struct sde_crtc *sde_crtc;
  4768. struct sde_kms_info *info;
  4769. struct sde_kms *sde_kms;
  4770. static const struct drm_prop_enum_list e_secure_level[] = {
  4771. {SDE_DRM_SEC_NON_SEC, "sec_and_non_sec"},
  4772. {SDE_DRM_SEC_ONLY, "sec_only"},
  4773. };
  4774. static const struct drm_prop_enum_list e_cwb_data_points[] = {
  4775. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  4776. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  4777. };
  4778. static const struct drm_prop_enum_list e_dcwb_data_points[] = {
  4779. {CAPTURE_MIXER_OUT, "capture_mixer_out"},
  4780. {CAPTURE_DSPP_OUT, "capture_pp_out"},
  4781. {CAPTURE_DEMURA_OUT, "capture_demura_out"},
  4782. };
  4783. static const struct drm_prop_enum_list e_idle_pc_state[] = {
  4784. {IDLE_PC_NONE, "idle_pc_none"},
  4785. {IDLE_PC_ENABLE, "idle_pc_enable"},
  4786. {IDLE_PC_DISABLE, "idle_pc_disable"},
  4787. };
  4788. static const struct drm_prop_enum_list e_cache_state[] = {
  4789. {CACHE_STATE_DISABLED, "cache_state_disabled"},
  4790. {CACHE_STATE_ENABLED, "cache_state_enabled"},
  4791. };
  4792. static const struct drm_prop_enum_list e_vm_req_state[] = {
  4793. {VM_REQ_NONE, "vm_req_none"},
  4794. {VM_REQ_RELEASE, "vm_req_release"},
  4795. {VM_REQ_ACQUIRE, "vm_req_acquire"},
  4796. };
  4797. SDE_DEBUG("\n");
  4798. if (!crtc || !catalog) {
  4799. SDE_ERROR("invalid crtc or catalog\n");
  4800. return;
  4801. }
  4802. sde_crtc = to_sde_crtc(crtc);
  4803. sde_kms = _sde_crtc_get_kms(crtc);
  4804. if (!sde_kms) {
  4805. SDE_ERROR("invalid argument\n");
  4806. return;
  4807. }
  4808. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  4809. if (!info) {
  4810. SDE_ERROR("failed to allocate info memory\n");
  4811. return;
  4812. }
  4813. sde_crtc_setup_capabilities_blob(info, catalog);
  4814. msm_property_install_range(&sde_crtc->property_info,
  4815. "input_fence_timeout", 0x0, 0,
  4816. SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, SDE_CRTC_INPUT_FENCE_TIMEOUT,
  4817. CRTC_PROP_INPUT_FENCE_TIMEOUT);
  4818. msm_property_install_volatile_range(&sde_crtc->property_info,
  4819. "output_fence", 0x0, 0, ~0, 0, CRTC_PROP_OUTPUT_FENCE);
  4820. msm_property_install_range(&sde_crtc->property_info,
  4821. "output_fence_offset", 0x0, 0, 1, 0,
  4822. CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4823. sde_crtc_install_perf_properties(sde_crtc, sde_kms, catalog, info);
  4824. msm_property_install_range(&sde_crtc->property_info,
  4825. "idle_time", 0, 0, U64_MAX, 0,
  4826. CRTC_PROP_IDLE_TIMEOUT);
  4827. if (catalog->has_trusted_vm_support) {
  4828. int init_idx = sde_in_trusted_vm(sde_kms) ? 1 : 0;
  4829. msm_property_install_enum(&sde_crtc->property_info,
  4830. "vm_request_state", 0x0, 0, e_vm_req_state,
  4831. ARRAY_SIZE(e_vm_req_state), init_idx,
  4832. CRTC_PROP_VM_REQ_STATE);
  4833. }
  4834. if (catalog->has_idle_pc)
  4835. msm_property_install_enum(&sde_crtc->property_info,
  4836. "idle_pc_state", 0x0, 0, e_idle_pc_state,
  4837. ARRAY_SIZE(e_idle_pc_state), 0,
  4838. CRTC_PROP_IDLE_PC_STATE);
  4839. if (catalog->has_dedicated_cwb_support)
  4840. msm_property_install_enum(&sde_crtc->property_info,
  4841. "capture_mode", 0, 0, e_dcwb_data_points,
  4842. ARRAY_SIZE(e_dcwb_data_points), 0,
  4843. CRTC_PROP_CAPTURE_OUTPUT);
  4844. else if (catalog->has_cwb_support)
  4845. msm_property_install_enum(&sde_crtc->property_info,
  4846. "capture_mode", 0, 0, e_cwb_data_points,
  4847. ARRAY_SIZE(e_cwb_data_points), 0,
  4848. CRTC_PROP_CAPTURE_OUTPUT);
  4849. msm_property_install_volatile_range(&sde_crtc->property_info,
  4850. "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1);
  4851. msm_property_install_enum(&sde_crtc->property_info, "security_level",
  4852. 0x0, 0, e_secure_level,
  4853. ARRAY_SIZE(e_secure_level), 0,
  4854. CRTC_PROP_SECURITY_LEVEL);
  4855. if (catalog->syscache_supported)
  4856. msm_property_install_enum(&sde_crtc->property_info, "cache_state",
  4857. 0x0, 0, e_cache_state,
  4858. ARRAY_SIZE(e_cache_state), 0,
  4859. CRTC_PROP_CACHE_STATE);
  4860. if (catalog->has_dim_layer) {
  4861. msm_property_install_volatile_range(&sde_crtc->property_info,
  4862. "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
  4863. sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers",
  4864. SDE_MAX_DIM_LAYERS);
  4865. }
  4866. if (catalog->mdp[0].has_dest_scaler)
  4867. sde_crtc_install_dest_scale_properties(sde_crtc, catalog,
  4868. info);
  4869. if (catalog->dspp_count) {
  4870. sde_kms_info_add_keyint(info, "dspp_count",
  4871. catalog->dspp_count);
  4872. if (catalog->rc_count)
  4873. sde_kms_info_add_keyint(info, "rc_mem_size",
  4874. catalog->dspp[0].sblk->rc.mem_total_size);
  4875. if (catalog->demura_count)
  4876. sde_kms_info_add_keyint(info, "demura_count",
  4877. catalog->demura_count);
  4878. }
  4879. msm_property_install_blob(&sde_crtc->property_info, "capabilities",
  4880. DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
  4881. sde_kms_info_add_keyint(info, "use_baselayer_for_stage",
  4882. catalog->has_base_layer);
  4883. msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
  4884. info->data, SDE_KMS_INFO_DATALEN(info),
  4885. CRTC_PROP_INFO);
  4886. sde_crtc_install_noise_layer_properties(sde_crtc, catalog, info);
  4887. if (catalog->has_ubwc_stats)
  4888. msm_property_install_range(&sde_crtc->property_info, "frame_data",
  4889. 0x0, 0, ~0, 0, CRTC_PROP_FRAME_DATA_BUF);
  4890. kfree(info);
  4891. }
  4892. static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
  4893. const struct drm_crtc_state *state, uint64_t *val)
  4894. {
  4895. struct sde_crtc *sde_crtc;
  4896. struct sde_crtc_state *cstate;
  4897. uint32_t offset;
  4898. bool is_vid = false;
  4899. struct drm_encoder *encoder;
  4900. sde_crtc = to_sde_crtc(crtc);
  4901. cstate = to_sde_crtc_state(state);
  4902. drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
  4903. if (sde_encoder_check_curr_mode(encoder,
  4904. MSM_DISPLAY_VIDEO_MODE))
  4905. is_vid = true;
  4906. if (is_vid)
  4907. break;
  4908. }
  4909. offset = sde_crtc_get_property(cstate, CRTC_PROP_OUTPUT_FENCE_OFFSET);
  4910. /*
  4911. * Increment trigger offset for vidoe mode alone as its release fence
  4912. * can be triggered only after the next frame-update. For cmd mode &
  4913. * virtual displays the release fence for the current frame can be
  4914. * triggered right after PP_DONE/WB_DONE interrupt
  4915. */
  4916. if (is_vid)
  4917. offset++;
  4918. /*
  4919. * Hwcomposer now queries the fences using the commit list in atomic
  4920. * commit ioctl. The offset should be set to next timeline
  4921. * which will be incremented during the prepare commit phase
  4922. */
  4923. offset++;
  4924. return sde_fence_create(sde_crtc->output_fence, val, offset);
  4925. }
  4926. /**
  4927. * sde_crtc_atomic_set_property - atomically set a crtc drm property
  4928. * @crtc: Pointer to drm crtc structure
  4929. * @state: Pointer to drm crtc state structure
  4930. * @property: Pointer to targeted drm property
  4931. * @val: Updated property value
  4932. * @Returns: Zero on success
  4933. */
  4934. static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
  4935. struct drm_crtc_state *state,
  4936. struct drm_property *property,
  4937. uint64_t val)
  4938. {
  4939. struct sde_crtc *sde_crtc;
  4940. struct sde_crtc_state *cstate;
  4941. int idx, ret;
  4942. uint64_t fence_user_fd;
  4943. uint64_t __user prev_user_fd;
  4944. if (!crtc || !state || !property) {
  4945. SDE_ERROR("invalid argument(s)\n");
  4946. return -EINVAL;
  4947. }
  4948. sde_crtc = to_sde_crtc(crtc);
  4949. cstate = to_sde_crtc_state(state);
  4950. SDE_ATRACE_BEGIN("sde_crtc_atomic_set_property");
  4951. /* check with cp property system first */
  4952. ret = sde_cp_crtc_set_property(crtc, state, property, val);
  4953. if (ret != -ENOENT)
  4954. goto exit;
  4955. /* if not handled by cp, check msm_property system */
  4956. ret = msm_property_atomic_set(&sde_crtc->property_info,
  4957. &cstate->property_state, property, val);
  4958. if (ret)
  4959. goto exit;
  4960. idx = msm_property_index(&sde_crtc->property_info, property);
  4961. switch (idx) {
  4962. case CRTC_PROP_INPUT_FENCE_TIMEOUT:
  4963. _sde_crtc_set_input_fence_timeout(cstate);
  4964. break;
  4965. case CRTC_PROP_DIM_LAYER_V1:
  4966. _sde_crtc_set_dim_layer_v1(crtc, cstate,
  4967. (void __user *)(uintptr_t)val);
  4968. break;
  4969. case CRTC_PROP_ROI_V1:
  4970. ret = _sde_crtc_set_roi_v1(state,
  4971. (void __user *)(uintptr_t)val);
  4972. break;
  4973. case CRTC_PROP_DEST_SCALER:
  4974. ret = _sde_crtc_set_dest_scaler(sde_crtc, cstate,
  4975. (void __user *)(uintptr_t)val);
  4976. break;
  4977. case CRTC_PROP_DEST_SCALER_LUT_ED:
  4978. case CRTC_PROP_DEST_SCALER_LUT_CIR:
  4979. case CRTC_PROP_DEST_SCALER_LUT_SEP:
  4980. ret = _sde_crtc_set_dest_scaler_lut(sde_crtc, cstate, idx);
  4981. break;
  4982. case CRTC_PROP_CORE_CLK:
  4983. case CRTC_PROP_CORE_AB:
  4984. case CRTC_PROP_CORE_IB:
  4985. cstate->bw_control = true;
  4986. break;
  4987. case CRTC_PROP_LLCC_AB:
  4988. case CRTC_PROP_LLCC_IB:
  4989. case CRTC_PROP_DRAM_AB:
  4990. case CRTC_PROP_DRAM_IB:
  4991. cstate->bw_control = true;
  4992. cstate->bw_split_vote = true;
  4993. break;
  4994. case CRTC_PROP_OUTPUT_FENCE:
  4995. if (!val)
  4996. goto exit;
  4997. ret = copy_from_user(&prev_user_fd, (void __user *)val,
  4998. sizeof(uint64_t));
  4999. if (ret) {
  5000. SDE_ERROR("copy from user failed rc:%d\n", ret);
  5001. ret = -EFAULT;
  5002. goto exit;
  5003. }
  5004. /*
  5005. * client is expected to reset the property to -1 before
  5006. * requesting for the release fence
  5007. */
  5008. if (prev_user_fd == -1) {
  5009. ret = _sde_crtc_get_output_fence(crtc, state,
  5010. &fence_user_fd);
  5011. if (ret) {
  5012. SDE_ERROR("fence create failed rc:%d\n", ret);
  5013. goto exit;
  5014. }
  5015. ret = copy_to_user((uint64_t __user *)(uintptr_t)val,
  5016. &fence_user_fd, sizeof(uint64_t));
  5017. if (ret) {
  5018. SDE_ERROR("copy to user failed rc:%d\n", ret);
  5019. put_unused_fd(fence_user_fd);
  5020. ret = -EFAULT;
  5021. goto exit;
  5022. }
  5023. }
  5024. break;
  5025. case CRTC_PROP_NOISE_LAYER_V1:
  5026. _sde_crtc_set_noise_layer(sde_crtc, cstate,
  5027. (void __user *)(uintptr_t)val);
  5028. break;
  5029. case CRTC_PROP_FRAME_DATA_BUF:
  5030. _sde_crtc_set_frame_data_buffers(crtc, cstate, (void __user *)(uintptr_t)val);
  5031. break;
  5032. default:
  5033. /* nothing to do */
  5034. break;
  5035. }
  5036. exit:
  5037. if (ret) {
  5038. if (ret != -EPERM)
  5039. SDE_ERROR("%s: failed to set property%d %s: %d\n",
  5040. crtc->name, DRMID(property),
  5041. property->name, ret);
  5042. else
  5043. SDE_DEBUG("%s: failed to set property%d %s: %d\n",
  5044. crtc->name, DRMID(property),
  5045. property->name, ret);
  5046. } else {
  5047. SDE_DEBUG("%s: %s[%d] <= 0x%llx\n", crtc->name, property->name,
  5048. property->base.id, val);
  5049. }
  5050. SDE_ATRACE_END("sde_crtc_atomic_set_property");
  5051. return ret;
  5052. }
  5053. static void sde_crtc_update_line_time(struct drm_crtc *crtc)
  5054. {
  5055. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  5056. struct drm_encoder *encoder;
  5057. u32 min_transfer_time = 0, updated_fps = 0;
  5058. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
  5059. if (sde_encoder_check_curr_mode(encoder, MSM_DISPLAY_CMD_MODE))
  5060. sde_encoder_get_transfer_time(encoder, &min_transfer_time);
  5061. }
  5062. if (min_transfer_time) {
  5063. /* get fps by doing 1000 ms / transfer_time */
  5064. updated_fps = DIV_ROUND_UP(1000000, min_transfer_time);
  5065. /* get line time by doing 1000ns / (fps * vactive) */
  5066. sde_crtc->line_time_in_ns = DIV_ROUND_UP(1000000000,
  5067. updated_fps * crtc->mode.vdisplay);
  5068. } else {
  5069. /* get line time by doing 1000ns / (fps * vtotal) */
  5070. sde_crtc->line_time_in_ns = DIV_ROUND_UP(1000000000,
  5071. drm_mode_vrefresh(&crtc->mode) * crtc->mode.vtotal);
  5072. }
  5073. SDE_EVT32(min_transfer_time, updated_fps, crtc->mode.vdisplay, crtc->mode.vtotal,
  5074. drm_mode_vrefresh(&crtc->mode), sde_crtc->line_time_in_ns);
  5075. }
  5076. void sde_crtc_set_qos_dirty(struct drm_crtc *crtc)
  5077. {
  5078. struct drm_plane *plane;
  5079. struct drm_plane_state *state;
  5080. struct sde_plane_state *pstate;
  5081. drm_atomic_crtc_for_each_plane(plane, crtc) {
  5082. state = plane->state;
  5083. if (!state)
  5084. continue;
  5085. pstate = to_sde_plane_state(state);
  5086. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  5087. }
  5088. sde_crtc_update_line_time(crtc);
  5089. }
  5090. /**
  5091. * sde_crtc_atomic_get_property - retrieve a crtc drm property
  5092. * @crtc: Pointer to drm crtc structure
  5093. * @state: Pointer to drm crtc state structure
  5094. * @property: Pointer to targeted drm property
  5095. * @val: Pointer to variable for receiving property value
  5096. * @Returns: Zero on success
  5097. */
  5098. static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
  5099. const struct drm_crtc_state *state,
  5100. struct drm_property *property,
  5101. uint64_t *val)
  5102. {
  5103. struct sde_crtc *sde_crtc;
  5104. struct sde_crtc_state *cstate;
  5105. int ret = -EINVAL, i;
  5106. if (!crtc || !state) {
  5107. SDE_ERROR("invalid argument(s)\n");
  5108. goto end;
  5109. }
  5110. sde_crtc = to_sde_crtc(crtc);
  5111. cstate = to_sde_crtc_state(state);
  5112. i = msm_property_index(&sde_crtc->property_info, property);
  5113. if (i == CRTC_PROP_OUTPUT_FENCE) {
  5114. *val = ~0;
  5115. ret = 0;
  5116. } else {
  5117. ret = msm_property_atomic_get(&sde_crtc->property_info,
  5118. &cstate->property_state, property, val);
  5119. if (ret)
  5120. ret = sde_cp_crtc_get_property(crtc, property, val);
  5121. }
  5122. if (ret)
  5123. DRM_ERROR("get property failed\n");
  5124. end:
  5125. return ret;
  5126. }
  5127. int sde_crtc_helper_reset_custom_properties(struct drm_crtc *crtc,
  5128. struct drm_crtc_state *crtc_state)
  5129. {
  5130. struct sde_crtc *sde_crtc;
  5131. struct sde_crtc_state *cstate;
  5132. struct drm_property *drm_prop;
  5133. enum msm_mdp_crtc_property prop_idx;
  5134. if (!crtc || !crtc_state) {
  5135. SDE_ERROR("invalid params\n");
  5136. return -EINVAL;
  5137. }
  5138. sde_crtc = to_sde_crtc(crtc);
  5139. cstate = to_sde_crtc_state(crtc_state);
  5140. sde_cp_crtc_clear(crtc);
  5141. for (prop_idx = 0; prop_idx < CRTC_PROP_COUNT; prop_idx++) {
  5142. uint64_t val = cstate->property_values[prop_idx].value;
  5143. uint64_t def;
  5144. int ret;
  5145. drm_prop = msm_property_index_to_drm_property(
  5146. &sde_crtc->property_info, prop_idx);
  5147. if (!drm_prop) {
  5148. /* not all props will be installed, based on caps */
  5149. SDE_DEBUG("%s: invalid property index %d\n",
  5150. sde_crtc->name, prop_idx);
  5151. continue;
  5152. }
  5153. def = msm_property_get_default(&sde_crtc->property_info,
  5154. prop_idx);
  5155. if (val == def)
  5156. continue;
  5157. SDE_DEBUG("%s: set prop %s idx %d from %llu to %llu\n",
  5158. sde_crtc->name, drm_prop->name, prop_idx, val,
  5159. def);
  5160. ret = sde_crtc_atomic_set_property(crtc, crtc_state, drm_prop,
  5161. def);
  5162. if (ret) {
  5163. SDE_ERROR("%s: set property failed, idx %d ret %d\n",
  5164. sde_crtc->name, prop_idx, ret);
  5165. continue;
  5166. }
  5167. }
  5168. /* disable clk and bw control until clk & bw properties are set */
  5169. cstate->bw_control = false;
  5170. cstate->bw_split_vote = false;
  5171. return 0;
  5172. }
  5173. void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count)
  5174. {
  5175. struct sde_crtc *sde_crtc;
  5176. struct sde_crtc_mixer *m;
  5177. int i;
  5178. if (!crtc) {
  5179. SDE_ERROR("invalid argument\n");
  5180. return;
  5181. }
  5182. sde_crtc = to_sde_crtc(crtc);
  5183. sde_crtc->misr_enable_sui = enable;
  5184. sde_crtc->misr_frame_count = frame_count;
  5185. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  5186. m = &sde_crtc->mixers[i];
  5187. if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
  5188. continue;
  5189. m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
  5190. }
  5191. }
  5192. void sde_crtc_get_misr_info(struct drm_crtc *crtc,
  5193. struct sde_crtc_misr_info *crtc_misr_info)
  5194. {
  5195. struct sde_crtc *sde_crtc;
  5196. struct sde_kms *sde_kms;
  5197. if (!crtc_misr_info) {
  5198. SDE_ERROR("invalid misr info\n");
  5199. return;
  5200. }
  5201. crtc_misr_info->misr_enable = false;
  5202. crtc_misr_info->misr_frame_count = 0;
  5203. if (!crtc) {
  5204. SDE_ERROR("invalid crtc\n");
  5205. return;
  5206. }
  5207. sde_kms = _sde_crtc_get_kms(crtc);
  5208. if (!sde_kms) {
  5209. SDE_ERROR("invalid sde_kms\n");
  5210. return;
  5211. }
  5212. if (sde_kms_is_secure_session_inprogress(sde_kms))
  5213. return;
  5214. sde_crtc = to_sde_crtc(crtc);
  5215. crtc_misr_info->misr_enable =
  5216. sde_crtc->misr_enable_debugfs ? true : false;
  5217. crtc_misr_info->misr_frame_count = sde_crtc->misr_frame_count;
  5218. }
  5219. #ifdef CONFIG_DEBUG_FS
  5220. static int _sde_debugfs_status_show(struct seq_file *s, void *data)
  5221. {
  5222. struct sde_crtc *sde_crtc;
  5223. struct sde_plane_state *pstate = NULL;
  5224. struct sde_crtc_mixer *m;
  5225. struct drm_crtc *crtc;
  5226. struct drm_plane *plane;
  5227. struct drm_display_mode *mode;
  5228. struct drm_framebuffer *fb;
  5229. struct drm_plane_state *state;
  5230. struct sde_crtc_state *cstate;
  5231. int i, out_width, out_height;
  5232. if (!s || !s->private)
  5233. return -EINVAL;
  5234. sde_crtc = s->private;
  5235. crtc = &sde_crtc->base;
  5236. cstate = to_sde_crtc_state(crtc->state);
  5237. mutex_lock(&sde_crtc->crtc_lock);
  5238. mode = &crtc->state->adjusted_mode;
  5239. out_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
  5240. out_height = sde_crtc_get_mixer_height(sde_crtc, cstate, mode);
  5241. seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
  5242. mode->hdisplay, mode->vdisplay);
  5243. seq_puts(s, "\n");
  5244. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  5245. m = &sde_crtc->mixers[i];
  5246. if (!m->hw_lm)
  5247. seq_printf(s, "\tmixer[%d] has no lm\n", i);
  5248. else if (!m->hw_ctl)
  5249. seq_printf(s, "\tmixer[%d] has no ctl\n", i);
  5250. else
  5251. seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
  5252. m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
  5253. out_width, out_height);
  5254. }
  5255. seq_puts(s, "\n");
  5256. for (i = 0; i < cstate->num_dim_layers; i++) {
  5257. struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i];
  5258. seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n",
  5259. i, dim_layer->stage, dim_layer->flags);
  5260. seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n",
  5261. dim_layer->rect.x, dim_layer->rect.y,
  5262. dim_layer->rect.w, dim_layer->rect.h);
  5263. seq_printf(s,
  5264. "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n",
  5265. dim_layer->color_fill.color_0,
  5266. dim_layer->color_fill.color_1,
  5267. dim_layer->color_fill.color_2,
  5268. dim_layer->color_fill.color_3);
  5269. seq_puts(s, "\n");
  5270. }
  5271. drm_atomic_crtc_for_each_plane(plane, crtc) {
  5272. pstate = to_sde_plane_state(plane->state);
  5273. state = plane->state;
  5274. if (!pstate || !state)
  5275. continue;
  5276. seq_printf(s, "\tplane:%u stage:%d rotation:%d\n",
  5277. plane->base.id, pstate->stage, pstate->rotation);
  5278. if (plane->state->fb) {
  5279. fb = plane->state->fb;
  5280. seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
  5281. fb->base.id, (char *) &fb->format->format,
  5282. fb->width, fb->height);
  5283. for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
  5284. seq_printf(s, "cpp[%d]:%u ",
  5285. i, fb->format->cpp[i]);
  5286. seq_puts(s, "\n\t");
  5287. seq_printf(s, "modifier:%8llu ", fb->modifier);
  5288. seq_puts(s, "\n");
  5289. seq_puts(s, "\t");
  5290. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
  5291. seq_printf(s, "pitches[%d]:%8u ", i,
  5292. fb->pitches[i]);
  5293. seq_puts(s, "\n");
  5294. seq_puts(s, "\t");
  5295. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
  5296. seq_printf(s, "offsets[%d]:%8u ", i,
  5297. fb->offsets[i]);
  5298. seq_puts(s, "\n");
  5299. }
  5300. seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
  5301. state->src_x >> 16, state->src_y >> 16,
  5302. state->src_w >> 16, state->src_h >> 16);
  5303. seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
  5304. state->crtc_x, state->crtc_y, state->crtc_w,
  5305. state->crtc_h);
  5306. seq_printf(s, "\tmultirect: mode: %d index: %d\n",
  5307. pstate->multirect_mode, pstate->multirect_index);
  5308. seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n",
  5309. pstate->excl_rect.x, pstate->excl_rect.y,
  5310. pstate->excl_rect.w, pstate->excl_rect.h);
  5311. seq_puts(s, "\n");
  5312. }
  5313. if (sde_crtc->vblank_cb_count) {
  5314. ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
  5315. u32 diff_ms = ktime_to_ms(diff);
  5316. u64 fps = diff_ms ? DIV_ROUND_CLOSEST(
  5317. sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
  5318. seq_printf(s,
  5319. "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
  5320. fps, sde_crtc->vblank_cb_count,
  5321. ktime_to_ms(diff), sde_crtc->play_count);
  5322. /* reset time & count for next measurement */
  5323. sde_crtc->vblank_cb_count = 0;
  5324. sde_crtc->vblank_cb_time = ktime_set(0, 0);
  5325. }
  5326. mutex_unlock(&sde_crtc->crtc_lock);
  5327. return 0;
  5328. }
  5329. static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
  5330. {
  5331. return single_open(file, _sde_debugfs_status_show, inode->i_private);
  5332. }
  5333. static ssize_t _sde_crtc_misr_setup(struct file *file,
  5334. const char __user *user_buf, size_t count, loff_t *ppos)
  5335. {
  5336. struct drm_crtc *crtc;
  5337. struct sde_crtc *sde_crtc;
  5338. char buf[MISR_BUFF_SIZE + 1];
  5339. u32 frame_count, enable;
  5340. size_t buff_copy;
  5341. struct sde_kms *sde_kms;
  5342. if (!file || !file->private_data)
  5343. return -EINVAL;
  5344. sde_crtc = file->private_data;
  5345. crtc = &sde_crtc->base;
  5346. sde_kms = _sde_crtc_get_kms(crtc);
  5347. if (!sde_kms) {
  5348. SDE_ERROR("invalid sde_kms\n");
  5349. return -EINVAL;
  5350. }
  5351. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  5352. if (copy_from_user(buf, user_buf, buff_copy)) {
  5353. SDE_ERROR("buffer copy failed\n");
  5354. return -EINVAL;
  5355. }
  5356. buf[buff_copy] = 0; /* end of string */
  5357. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  5358. return -EINVAL;
  5359. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  5360. SDE_DEBUG("crtc:%d misr enable/disable not allowed\n",
  5361. DRMID(crtc));
  5362. return -EINVAL;
  5363. }
  5364. sde_crtc->misr_enable_debugfs = enable;
  5365. sde_crtc->misr_frame_count = frame_count;
  5366. sde_crtc->misr_reconfigure = true;
  5367. return count;
  5368. }
  5369. static ssize_t _sde_crtc_misr_read(struct file *file,
  5370. char __user *user_buff, size_t count, loff_t *ppos)
  5371. {
  5372. struct drm_crtc *crtc;
  5373. struct sde_crtc *sde_crtc;
  5374. struct sde_kms *sde_kms;
  5375. struct sde_crtc_mixer *m;
  5376. struct sde_vm_ops *vm_ops;
  5377. int i = 0, rc;
  5378. ssize_t len = 0;
  5379. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  5380. if (*ppos)
  5381. return 0;
  5382. if (!file || !file->private_data)
  5383. return -EINVAL;
  5384. sde_crtc = file->private_data;
  5385. crtc = &sde_crtc->base;
  5386. sde_kms = _sde_crtc_get_kms(crtc);
  5387. if (!sde_kms)
  5388. return -EINVAL;
  5389. rc = pm_runtime_get_sync(crtc->dev->dev);
  5390. if (rc < 0)
  5391. return rc;
  5392. vm_ops = sde_vm_get_ops(sde_kms);
  5393. sde_vm_lock(sde_kms);
  5394. if (vm_ops && vm_ops->vm_owns_hw && !vm_ops->vm_owns_hw(sde_kms)) {
  5395. SDE_DEBUG("op not supported due to HW unavailability\n");
  5396. rc = -EOPNOTSUPP;
  5397. goto end;
  5398. }
  5399. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  5400. SDE_DEBUG("crtc:%d misr read not allowed\n", DRMID(crtc));
  5401. rc = -EOPNOTSUPP;
  5402. goto end;
  5403. }
  5404. if (!sde_crtc->misr_enable_debugfs) {
  5405. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5406. "disabled\n");
  5407. goto buff_check;
  5408. }
  5409. for (i = 0; i < sde_crtc->num_mixers; ++i) {
  5410. u32 misr_value = 0;
  5411. m = &sde_crtc->mixers[i];
  5412. if (!m->hw_lm || !m->hw_lm->ops.collect_misr) {
  5413. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5414. "invalid\n");
  5415. SDE_ERROR("crtc:%d invalid misr ops\n", DRMID(crtc));
  5416. continue;
  5417. }
  5418. rc = m->hw_lm->ops.collect_misr(m->hw_lm, false, &misr_value);
  5419. if (rc) {
  5420. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5421. "invalid\n");
  5422. SDE_ERROR("crtc:%d failed to collect misr %d\n",
  5423. DRMID(crtc), rc);
  5424. continue;
  5425. } else {
  5426. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5427. "lm idx:%d\n", m->hw_lm->idx - LM_0);
  5428. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  5429. "0x%x\n", misr_value);
  5430. }
  5431. }
  5432. buff_check:
  5433. if (count <= len) {
  5434. len = 0;
  5435. goto end;
  5436. }
  5437. if (copy_to_user(user_buff, buf, len)) {
  5438. len = -EFAULT;
  5439. goto end;
  5440. }
  5441. *ppos += len; /* increase offset */
  5442. end:
  5443. sde_vm_unlock(sde_kms);
  5444. pm_runtime_put_sync(crtc->dev->dev);
  5445. return len;
  5446. }
  5447. #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \
  5448. static int __prefix ## _open(struct inode *inode, struct file *file) \
  5449. { \
  5450. return single_open(file, __prefix ## _show, inode->i_private); \
  5451. } \
  5452. static const struct file_operations __prefix ## _fops = { \
  5453. .owner = THIS_MODULE, \
  5454. .open = __prefix ## _open, \
  5455. .release = single_release, \
  5456. .read = seq_read, \
  5457. .llseek = seq_lseek, \
  5458. }
  5459. static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
  5460. {
  5461. struct drm_crtc *crtc = (struct drm_crtc *) s->private;
  5462. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  5463. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  5464. int i;
  5465. seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
  5466. seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
  5467. seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc,
  5468. crtc->state));
  5469. seq_printf(s, "core_clk_rate: %llu\n",
  5470. sde_crtc->cur_perf.core_clk_rate);
  5471. for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC;
  5472. i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
  5473. seq_printf(s, "bw_ctl[%s]: %llu\n",
  5474. sde_power_handle_get_dbus_name(i),
  5475. sde_crtc->cur_perf.bw_ctl[i]);
  5476. seq_printf(s, "max_per_pipe_ib[%s]: %llu\n",
  5477. sde_power_handle_get_dbus_name(i),
  5478. sde_crtc->cur_perf.max_per_pipe_ib[i]);
  5479. }
  5480. return 0;
  5481. }
  5482. DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
  5483. static int _sde_debugfs_fence_status_show(struct seq_file *s, void *data)
  5484. {
  5485. struct drm_crtc *crtc;
  5486. struct drm_plane *plane;
  5487. struct drm_connector *conn;
  5488. struct drm_mode_object *drm_obj;
  5489. struct sde_crtc *sde_crtc;
  5490. struct sde_crtc_state *cstate;
  5491. struct sde_fence_context *ctx;
  5492. struct drm_connector_list_iter conn_iter;
  5493. struct drm_device *dev;
  5494. if (!s || !s->private)
  5495. return -EINVAL;
  5496. sde_crtc = s->private;
  5497. crtc = &sde_crtc->base;
  5498. dev = crtc->dev;
  5499. cstate = to_sde_crtc_state(crtc->state);
  5500. if (!sde_crtc->kickoff_in_progress)
  5501. goto skip_input_fence;
  5502. /* Dump input fence info */
  5503. seq_puts(s, "===Input fence===\n");
  5504. drm_atomic_crtc_for_each_plane(plane, crtc) {
  5505. struct sde_plane_state *pstate;
  5506. struct dma_fence *fence;
  5507. pstate = to_sde_plane_state(plane->state);
  5508. if (!pstate)
  5509. continue;
  5510. seq_printf(s, "plane:%u stage:%d\n", plane->base.id,
  5511. pstate->stage);
  5512. SDE_EVT32(DRMID(crtc), plane->base.id, pstate->input_fence);
  5513. if (pstate->input_fence) {
  5514. rcu_read_lock();
  5515. fence = dma_fence_get_rcu(pstate->input_fence);
  5516. rcu_read_unlock();
  5517. if (fence) {
  5518. sde_fence_list_dump(fence, &s);
  5519. dma_fence_put(fence);
  5520. }
  5521. }
  5522. }
  5523. skip_input_fence:
  5524. /* Dump release fence info */
  5525. seq_puts(s, "\n");
  5526. seq_puts(s, "===Release fence===\n");
  5527. ctx = sde_crtc->output_fence;
  5528. drm_obj = &crtc->base;
  5529. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  5530. seq_puts(s, "\n");
  5531. /* Dump retire fence info */
  5532. seq_puts(s, "===Retire fence===\n");
  5533. drm_connector_list_iter_begin(dev, &conn_iter);
  5534. drm_for_each_connector_iter(conn, &conn_iter)
  5535. if (conn->state && conn->state->crtc == crtc &&
  5536. cstate->num_connectors < MAX_CONNECTORS) {
  5537. struct sde_connector *c_conn;
  5538. c_conn = to_sde_connector(conn);
  5539. ctx = c_conn->retire_fence;
  5540. drm_obj = &conn->base;
  5541. sde_debugfs_timeline_dump(ctx, drm_obj, &s);
  5542. }
  5543. drm_connector_list_iter_end(&conn_iter);
  5544. seq_puts(s, "\n");
  5545. return 0;
  5546. }
  5547. static int _sde_debugfs_fence_status(struct inode *inode, struct file *file)
  5548. {
  5549. return single_open(file, _sde_debugfs_fence_status_show,
  5550. inode->i_private);
  5551. }
  5552. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  5553. {
  5554. struct sde_crtc *sde_crtc;
  5555. struct sde_kms *sde_kms;
  5556. static const struct file_operations debugfs_status_fops = {
  5557. .open = _sde_debugfs_status_open,
  5558. .read = seq_read,
  5559. .llseek = seq_lseek,
  5560. .release = single_release,
  5561. };
  5562. static const struct file_operations debugfs_misr_fops = {
  5563. .open = simple_open,
  5564. .read = _sde_crtc_misr_read,
  5565. .write = _sde_crtc_misr_setup,
  5566. };
  5567. static const struct file_operations debugfs_fps_fops = {
  5568. .open = _sde_debugfs_fps_status,
  5569. .read = seq_read,
  5570. };
  5571. static const struct file_operations debugfs_fence_fops = {
  5572. .open = _sde_debugfs_fence_status,
  5573. .read = seq_read,
  5574. };
  5575. if (!crtc)
  5576. return -EINVAL;
  5577. sde_crtc = to_sde_crtc(crtc);
  5578. sde_kms = _sde_crtc_get_kms(crtc);
  5579. if (!sde_kms)
  5580. return -EINVAL;
  5581. sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
  5582. crtc->dev->primary->debugfs_root);
  5583. if (!sde_crtc->debugfs_root)
  5584. return -ENOMEM;
  5585. /* don't error check these */
  5586. debugfs_create_file("status", 0400,
  5587. sde_crtc->debugfs_root,
  5588. sde_crtc, &debugfs_status_fops);
  5589. debugfs_create_file("state", 0400,
  5590. sde_crtc->debugfs_root,
  5591. &sde_crtc->base,
  5592. &sde_crtc_debugfs_state_fops);
  5593. debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root,
  5594. sde_crtc, &debugfs_misr_fops);
  5595. debugfs_create_file("fps", 0400, sde_crtc->debugfs_root,
  5596. sde_crtc, &debugfs_fps_fops);
  5597. debugfs_create_file("fence_status", 0400, sde_crtc->debugfs_root,
  5598. sde_crtc, &debugfs_fence_fops);
  5599. return 0;
  5600. }
  5601. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5602. {
  5603. struct sde_crtc *sde_crtc;
  5604. if (!crtc)
  5605. return;
  5606. sde_crtc = to_sde_crtc(crtc);
  5607. debugfs_remove_recursive(sde_crtc->debugfs_root);
  5608. }
  5609. #else
  5610. static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
  5611. {
  5612. return 0;
  5613. }
  5614. static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
  5615. {
  5616. }
  5617. #endif /* CONFIG_DEBUG_FS */
  5618. static void vblank_ctrl_worker(struct kthread_work *work)
  5619. {
  5620. struct vblank_work *cur_work = container_of(work,
  5621. struct vblank_work, work);
  5622. struct msm_drm_private *priv = cur_work->priv;
  5623. sde_crtc_vblank(priv->crtcs[cur_work->crtc_id], cur_work->enable);
  5624. kfree(cur_work);
  5625. }
  5626. static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
  5627. int crtc_id, bool enable)
  5628. {
  5629. struct vblank_work *cur_work;
  5630. struct drm_crtc *crtc;
  5631. struct kthread_worker *worker;
  5632. if (!priv || crtc_id >= priv->num_crtcs)
  5633. return -EINVAL;
  5634. cur_work = kzalloc(sizeof(*cur_work), GFP_ATOMIC);
  5635. if (!cur_work)
  5636. return -ENOMEM;
  5637. crtc = priv->crtcs[crtc_id];
  5638. kthread_init_work(&cur_work->work, vblank_ctrl_worker);
  5639. cur_work->crtc_id = crtc_id;
  5640. cur_work->enable = enable;
  5641. cur_work->priv = priv;
  5642. worker = &priv->event_thread[crtc_id].worker;
  5643. kthread_queue_work(worker, &cur_work->work);
  5644. return 0;
  5645. }
  5646. static int sde_crtc_enable_vblank(struct drm_crtc *crtc)
  5647. {
  5648. struct drm_device *dev = crtc->dev;
  5649. unsigned int pipe = crtc->index;
  5650. struct msm_drm_private *priv = dev->dev_private;
  5651. struct msm_kms *kms = priv->kms;
  5652. if (!kms)
  5653. return -ENXIO;
  5654. DBG("dev=%pK, crtc=%u", dev, pipe);
  5655. return vblank_ctrl_queue_work(priv, pipe, true);
  5656. }
  5657. static void sde_crtc_disable_vblank(struct drm_crtc *crtc)
  5658. {
  5659. struct drm_device *dev = crtc->dev;
  5660. unsigned int pipe = crtc->index;
  5661. struct msm_drm_private *priv = dev->dev_private;
  5662. struct msm_kms *kms = priv->kms;
  5663. if (!kms)
  5664. return;
  5665. DBG("dev=%pK, crtc=%u", dev, pipe);
  5666. vblank_ctrl_queue_work(priv, pipe, false);
  5667. }
  5668. static int sde_crtc_late_register(struct drm_crtc *crtc)
  5669. {
  5670. return _sde_crtc_init_debugfs(crtc);
  5671. }
  5672. static void sde_crtc_early_unregister(struct drm_crtc *crtc)
  5673. {
  5674. _sde_crtc_destroy_debugfs(crtc);
  5675. }
  5676. static const struct drm_crtc_funcs sde_crtc_funcs = {
  5677. .set_config = drm_atomic_helper_set_config,
  5678. .destroy = sde_crtc_destroy,
  5679. .enable_vblank = sde_crtc_enable_vblank,
  5680. .disable_vblank = sde_crtc_disable_vblank,
  5681. .page_flip = drm_atomic_helper_page_flip,
  5682. .atomic_set_property = sde_crtc_atomic_set_property,
  5683. .atomic_get_property = sde_crtc_atomic_get_property,
  5684. .reset = sde_crtc_reset,
  5685. .atomic_duplicate_state = sde_crtc_duplicate_state,
  5686. .atomic_destroy_state = sde_crtc_destroy_state,
  5687. .late_register = sde_crtc_late_register,
  5688. .early_unregister = sde_crtc_early_unregister,
  5689. };
  5690. static const struct drm_crtc_funcs sde_crtc_funcs_v1 = {
  5691. .set_config = drm_atomic_helper_set_config,
  5692. .destroy = sde_crtc_destroy,
  5693. .enable_vblank = sde_crtc_enable_vblank,
  5694. .disable_vblank = sde_crtc_disable_vblank,
  5695. .page_flip = drm_atomic_helper_page_flip,
  5696. .atomic_set_property = sde_crtc_atomic_set_property,
  5697. .atomic_get_property = sde_crtc_atomic_get_property,
  5698. .reset = sde_crtc_reset,
  5699. .atomic_duplicate_state = sde_crtc_duplicate_state,
  5700. .atomic_destroy_state = sde_crtc_destroy_state,
  5701. .late_register = sde_crtc_late_register,
  5702. .early_unregister = sde_crtc_early_unregister,
  5703. .get_vblank_timestamp = sde_crtc_get_vblank_timestamp,
  5704. .get_vblank_counter = sde_crtc_get_vblank_counter,
  5705. };
  5706. static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
  5707. .mode_fixup = sde_crtc_mode_fixup,
  5708. .disable = sde_crtc_disable,
  5709. .atomic_enable = sde_crtc_enable,
  5710. .atomic_check = sde_crtc_atomic_check,
  5711. .atomic_begin = sde_crtc_atomic_begin,
  5712. .atomic_flush = sde_crtc_atomic_flush,
  5713. };
  5714. static void _sde_crtc_event_cb(struct kthread_work *work)
  5715. {
  5716. struct sde_crtc_event *event;
  5717. struct sde_crtc *sde_crtc;
  5718. unsigned long irq_flags;
  5719. if (!work) {
  5720. SDE_ERROR("invalid work item\n");
  5721. return;
  5722. }
  5723. event = container_of(work, struct sde_crtc_event, kt_work);
  5724. /* set sde_crtc to NULL for static work structures */
  5725. sde_crtc = event->sde_crtc;
  5726. if (!sde_crtc)
  5727. return;
  5728. if (event->cb_func)
  5729. event->cb_func(&sde_crtc->base, event->usr);
  5730. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5731. list_add_tail(&event->list, &sde_crtc->event_free_list);
  5732. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5733. }
  5734. int sde_crtc_event_queue(struct drm_crtc *crtc,
  5735. void (*func)(struct drm_crtc *crtc, void *usr),
  5736. void *usr, bool color_processing_event)
  5737. {
  5738. unsigned long irq_flags;
  5739. struct sde_crtc *sde_crtc;
  5740. struct msm_drm_private *priv;
  5741. struct sde_crtc_event *event = NULL;
  5742. u32 crtc_id;
  5743. if (!crtc || !crtc->dev || !crtc->dev->dev_private || !func) {
  5744. SDE_ERROR("invalid parameters\n");
  5745. return -EINVAL;
  5746. }
  5747. sde_crtc = to_sde_crtc(crtc);
  5748. priv = crtc->dev->dev_private;
  5749. crtc_id = drm_crtc_index(crtc);
  5750. /*
  5751. * Obtain an event struct from the private cache. This event
  5752. * queue may be called from ISR contexts, so use a private
  5753. * cache to avoid calling any memory allocation functions.
  5754. */
  5755. spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
  5756. if (!list_empty(&sde_crtc->event_free_list)) {
  5757. event = list_first_entry(&sde_crtc->event_free_list,
  5758. struct sde_crtc_event, list);
  5759. list_del_init(&event->list);
  5760. }
  5761. spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
  5762. if (!event)
  5763. return -ENOMEM;
  5764. /* populate event node */
  5765. event->sde_crtc = sde_crtc;
  5766. event->cb_func = func;
  5767. event->usr = usr;
  5768. /* queue new event request */
  5769. kthread_init_work(&event->kt_work, _sde_crtc_event_cb);
  5770. if (color_processing_event)
  5771. kthread_queue_work(&priv->pp_event_worker,
  5772. &event->kt_work);
  5773. else
  5774. kthread_queue_work(&priv->event_thread[crtc_id].worker,
  5775. &event->kt_work);
  5776. return 0;
  5777. }
  5778. static int _sde_crtc_init_events(struct sde_crtc *sde_crtc)
  5779. {
  5780. int i, rc = 0;
  5781. if (!sde_crtc) {
  5782. SDE_ERROR("invalid crtc\n");
  5783. return -EINVAL;
  5784. }
  5785. spin_lock_init(&sde_crtc->event_lock);
  5786. INIT_LIST_HEAD(&sde_crtc->event_free_list);
  5787. for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i)
  5788. list_add_tail(&sde_crtc->event_cache[i].list,
  5789. &sde_crtc->event_free_list);
  5790. return rc;
  5791. }
  5792. void sde_crtc_static_img_control(struct drm_crtc *crtc,
  5793. enum sde_crtc_cache_state state,
  5794. bool is_vidmode)
  5795. {
  5796. struct drm_plane *plane;
  5797. struct sde_crtc *sde_crtc;
  5798. struct sde_kms *sde_kms;
  5799. if (!crtc || !crtc->dev)
  5800. return;
  5801. sde_kms = _sde_crtc_get_kms(crtc);
  5802. if (!sde_kms || !sde_kms->catalog) {
  5803. SDE_ERROR("invalid params\n");
  5804. return;
  5805. }
  5806. if (!sde_kms->catalog->syscache_supported) {
  5807. SDE_DEBUG("syscache not supported\n");
  5808. return;
  5809. }
  5810. sde_crtc = to_sde_crtc(crtc);
  5811. if (sde_crtc->cache_state == state)
  5812. return;
  5813. switch (state) {
  5814. case CACHE_STATE_NORMAL:
  5815. if (sde_crtc->cache_state == CACHE_STATE_DISABLED
  5816. && !is_vidmode)
  5817. return;
  5818. kthread_cancel_delayed_work_sync(
  5819. &sde_crtc->static_cache_read_work);
  5820. break;
  5821. case CACHE_STATE_PRE_CACHE:
  5822. if (sde_crtc->cache_state != CACHE_STATE_NORMAL)
  5823. return;
  5824. break;
  5825. case CACHE_STATE_FRAME_WRITE:
  5826. if (sde_crtc->cache_state != CACHE_STATE_PRE_CACHE)
  5827. return;
  5828. break;
  5829. case CACHE_STATE_FRAME_READ:
  5830. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  5831. return;
  5832. break;
  5833. case CACHE_STATE_DISABLED:
  5834. break;
  5835. default:
  5836. return;
  5837. }
  5838. sde_crtc->cache_state = state;
  5839. drm_atomic_crtc_for_each_plane(plane, crtc)
  5840. sde_plane_static_img_control(plane, state);
  5841. }
  5842. /*
  5843. * __sde_crtc_static_cache_read_work - transition to cache read
  5844. */
  5845. void __sde_crtc_static_cache_read_work(struct kthread_work *work)
  5846. {
  5847. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5848. static_cache_read_work.work);
  5849. struct drm_crtc *crtc = &sde_crtc->base;
  5850. struct sde_hw_ctl *ctl = sde_crtc->mixers[0].hw_ctl;
  5851. struct drm_encoder *enc, *drm_enc = NULL;
  5852. struct drm_plane *plane;
  5853. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  5854. return;
  5855. drm_for_each_encoder_mask(enc, crtc->dev, crtc->state->encoder_mask) {
  5856. drm_enc = enc;
  5857. if (sde_encoder_in_clone_mode(drm_enc))
  5858. return;
  5859. }
  5860. if (!drm_enc || !ctl || !sde_crtc->num_mixers) {
  5861. SDE_ERROR("invalid object, drm_enc:%d, ctl:%d\n", !drm_enc,
  5862. !ctl);
  5863. return;
  5864. }
  5865. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_ENTRY);
  5866. sde_crtc_static_img_control(crtc, CACHE_STATE_FRAME_READ, false);
  5867. /* flush only the sys-cache enabled SSPPs */
  5868. if (ctl->ops.clear_pending_flush)
  5869. ctl->ops.clear_pending_flush(ctl);
  5870. drm_atomic_crtc_for_each_plane(plane, crtc)
  5871. sde_plane_ctl_flush(plane, ctl, true);
  5872. /* kickoff encoder and wait for VBLANK */
  5873. sde_encoder_kickoff(drm_enc, false, false);
  5874. sde_encoder_wait_for_event(drm_enc, MSM_ENC_VBLANK);
  5875. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  5876. }
  5877. void sde_crtc_static_cache_read_kickoff(struct drm_crtc *crtc)
  5878. {
  5879. struct drm_device *dev;
  5880. struct msm_drm_private *priv;
  5881. struct msm_drm_thread *disp_thread;
  5882. struct sde_crtc *sde_crtc;
  5883. struct sde_crtc_state *cstate;
  5884. u32 msecs_fps = 0;
  5885. if (!crtc)
  5886. return;
  5887. dev = crtc->dev;
  5888. sde_crtc = to_sde_crtc(crtc);
  5889. cstate = to_sde_crtc_state(crtc->state);
  5890. if (!dev || !dev->dev_private || !sde_crtc)
  5891. return;
  5892. priv = dev->dev_private;
  5893. disp_thread = &priv->disp_thread[crtc->index];
  5894. if (sde_crtc->cache_state != CACHE_STATE_FRAME_WRITE)
  5895. return;
  5896. msecs_fps = DIV_ROUND_UP((1 * 1000), sde_crtc_get_fps_mode(crtc));
  5897. /* Kickoff transition to read state after next vblank */
  5898. kthread_queue_delayed_work(&disp_thread->worker,
  5899. &sde_crtc->static_cache_read_work,
  5900. msecs_to_jiffies(msecs_fps));
  5901. }
  5902. /*
  5903. * __sde_crtc_idle_notify_work - signal idle timeout to user space
  5904. */
  5905. static void __sde_crtc_idle_notify_work(struct kthread_work *work)
  5906. {
  5907. struct sde_crtc *sde_crtc = container_of(work, struct sde_crtc,
  5908. idle_notify_work.work);
  5909. struct drm_crtc *crtc;
  5910. int ret = 0;
  5911. if (!sde_crtc) {
  5912. SDE_ERROR("invalid sde crtc\n");
  5913. } else {
  5914. crtc = &sde_crtc->base;
  5915. sde_crtc_event_notify(crtc, DRM_EVENT_IDLE_NOTIFY, sizeof(u32), ret);
  5916. SDE_DEBUG("crtc[%d]: idle timeout notified\n", crtc->base.id);
  5917. sde_crtc_static_img_control(crtc, CACHE_STATE_PRE_CACHE, false);
  5918. }
  5919. }
  5920. /* initialize crtc */
  5921. struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
  5922. {
  5923. struct drm_crtc *crtc = NULL;
  5924. struct sde_crtc *sde_crtc = NULL;
  5925. struct msm_drm_private *priv = NULL;
  5926. struct sde_kms *kms = NULL;
  5927. const struct drm_crtc_funcs *crtc_funcs;
  5928. int i, rc;
  5929. priv = dev->dev_private;
  5930. kms = to_sde_kms(priv->kms);
  5931. sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
  5932. if (!sde_crtc)
  5933. return ERR_PTR(-ENOMEM);
  5934. crtc = &sde_crtc->base;
  5935. crtc->dev = dev;
  5936. mutex_init(&sde_crtc->crtc_lock);
  5937. spin_lock_init(&sde_crtc->spin_lock);
  5938. spin_lock_init(&sde_crtc->fevent_spin_lock);
  5939. atomic_set(&sde_crtc->frame_pending, 0);
  5940. sde_crtc->enabled = false;
  5941. sde_crtc->kickoff_in_progress = false;
  5942. /* Below parameters are for fps calculation for sysfs node */
  5943. sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC;
  5944. sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT,
  5945. sizeof(ktime_t), GFP_KERNEL);
  5946. if (!sde_crtc->fps_info.time_buf)
  5947. SDE_ERROR("invalid buffer\n");
  5948. else
  5949. memset(sde_crtc->fps_info.time_buf, 0,
  5950. sizeof(*(sde_crtc->fps_info.time_buf)));
  5951. INIT_LIST_HEAD(&sde_crtc->frame_event_list);
  5952. INIT_LIST_HEAD(&sde_crtc->user_event_list);
  5953. for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
  5954. INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
  5955. list_add(&sde_crtc->frame_events[i].list,
  5956. &sde_crtc->frame_event_list);
  5957. kthread_init_work(&sde_crtc->frame_events[i].work,
  5958. sde_crtc_frame_event_work);
  5959. }
  5960. crtc_funcs = kms->catalog->has_precise_vsync_ts ? &sde_crtc_funcs_v1 : &sde_crtc_funcs;
  5961. drm_crtc_init_with_planes(dev, crtc, plane, NULL, crtc_funcs, NULL);
  5962. drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
  5963. /* save user friendly CRTC name for later */
  5964. snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
  5965. /* initialize event handling */
  5966. rc = _sde_crtc_init_events(sde_crtc);
  5967. if (rc) {
  5968. drm_crtc_cleanup(crtc);
  5969. kfree(sde_crtc);
  5970. return ERR_PTR(rc);
  5971. }
  5972. /* initialize output fence support */
  5973. sde_crtc->output_fence = sde_fence_init(sde_crtc->name, crtc->base.id);
  5974. if (IS_ERR(sde_crtc->output_fence)) {
  5975. rc = PTR_ERR(sde_crtc->output_fence);
  5976. SDE_ERROR("failed to init fence, %d\n", rc);
  5977. drm_crtc_cleanup(crtc);
  5978. kfree(sde_crtc);
  5979. return ERR_PTR(rc);
  5980. }
  5981. /* create CRTC properties */
  5982. msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
  5983. priv->crtc_property, sde_crtc->property_data,
  5984. CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
  5985. sizeof(struct sde_crtc_state));
  5986. sde_crtc_install_properties(crtc, kms->catalog);
  5987. /* Install color processing properties */
  5988. sde_cp_crtc_init(crtc);
  5989. sde_cp_crtc_install_properties(crtc);
  5990. for (i = 0; i < SDE_SYS_CACHE_MAX; i++) {
  5991. sde_crtc->cur_perf.llcc_active[i] = false;
  5992. sde_crtc->new_perf.llcc_active[i] = false;
  5993. }
  5994. kthread_init_delayed_work(&sde_crtc->idle_notify_work,
  5995. __sde_crtc_idle_notify_work);
  5996. kthread_init_delayed_work(&sde_crtc->static_cache_read_work,
  5997. __sde_crtc_static_cache_read_work);
  5998. SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);
  5999. return crtc;
  6000. }
  6001. int sde_crtc_post_init(struct drm_device *dev, struct drm_crtc *crtc)
  6002. {
  6003. struct sde_crtc *sde_crtc;
  6004. int rc = 0;
  6005. if (!dev || !dev->primary || !dev->primary->kdev || !crtc) {
  6006. SDE_ERROR("invalid input param(s)\n");
  6007. rc = -EINVAL;
  6008. goto end;
  6009. }
  6010. sde_crtc = to_sde_crtc(crtc);
  6011. sde_crtc->sysfs_dev = device_create_with_groups(
  6012. dev->primary->kdev->class, dev->primary->kdev, 0, crtc,
  6013. sde_crtc_attr_groups, "sde-crtc-%d", crtc->index);
  6014. if (IS_ERR_OR_NULL(sde_crtc->sysfs_dev)) {
  6015. SDE_ERROR("crtc:%d sysfs create failed rc:%ld\n", crtc->index,
  6016. PTR_ERR(sde_crtc->sysfs_dev));
  6017. if (!sde_crtc->sysfs_dev)
  6018. rc = -EINVAL;
  6019. else
  6020. rc = PTR_ERR(sde_crtc->sysfs_dev);
  6021. goto end;
  6022. }
  6023. sde_crtc->vsync_event_sf = sysfs_get_dirent(
  6024. sde_crtc->sysfs_dev->kobj.sd, "vsync_event");
  6025. if (!sde_crtc->vsync_event_sf)
  6026. SDE_ERROR("crtc:%d vsync_event sysfs create failed\n",
  6027. crtc->base.id);
  6028. sde_crtc->retire_frame_event_sf = sysfs_get_dirent(
  6029. sde_crtc->sysfs_dev->kobj.sd, "retire_frame_event");
  6030. if (!sde_crtc->retire_frame_event_sf)
  6031. SDE_ERROR("crtc:%d retire frame event sysfs create failed\n",
  6032. crtc->base.id);
  6033. end:
  6034. return rc;
  6035. }
  6036. static int _sde_crtc_event_enable(struct sde_kms *kms,
  6037. struct drm_crtc *crtc_drm, u32 event)
  6038. {
  6039. struct sde_crtc *crtc = NULL;
  6040. struct sde_crtc_irq_info *node;
  6041. unsigned long flags;
  6042. bool found = false;
  6043. int ret, i = 0;
  6044. bool add_event = false;
  6045. crtc = to_sde_crtc(crtc_drm);
  6046. spin_lock_irqsave(&crtc->spin_lock, flags);
  6047. list_for_each_entry(node, &crtc->user_event_list, list) {
  6048. if (node->event == event) {
  6049. found = true;
  6050. break;
  6051. }
  6052. }
  6053. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6054. /* event already enabled */
  6055. if (found)
  6056. return 0;
  6057. node = NULL;
  6058. for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
  6059. if (custom_events[i].event == event &&
  6060. custom_events[i].func) {
  6061. node = kzalloc(sizeof(*node), GFP_KERNEL);
  6062. if (!node)
  6063. return -ENOMEM;
  6064. INIT_LIST_HEAD(&node->list);
  6065. INIT_LIST_HEAD(&node->irq.list);
  6066. node->func = custom_events[i].func;
  6067. node->event = event;
  6068. node->state = IRQ_NOINIT;
  6069. spin_lock_init(&node->state_lock);
  6070. break;
  6071. }
  6072. }
  6073. if (!node) {
  6074. SDE_ERROR("unsupported event %x\n", event);
  6075. return -EINVAL;
  6076. }
  6077. ret = 0;
  6078. if (crtc_drm->enabled) {
  6079. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  6080. if (ret < 0) {
  6081. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  6082. kfree(node);
  6083. return ret;
  6084. }
  6085. INIT_LIST_HEAD(&node->irq.list);
  6086. mutex_lock(&crtc->crtc_lock);
  6087. ret = node->func(crtc_drm, true, &node->irq);
  6088. if (!ret) {
  6089. spin_lock_irqsave(&crtc->spin_lock, flags);
  6090. list_add_tail(&node->list, &crtc->user_event_list);
  6091. add_event = true;
  6092. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6093. }
  6094. mutex_unlock(&crtc->crtc_lock);
  6095. pm_runtime_put_sync(crtc_drm->dev->dev);
  6096. }
  6097. if (add_event)
  6098. return 0;
  6099. if (!ret) {
  6100. spin_lock_irqsave(&crtc->spin_lock, flags);
  6101. list_add_tail(&node->list, &crtc->user_event_list);
  6102. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6103. } else {
  6104. kfree(node);
  6105. }
  6106. return ret;
  6107. }
  6108. static int _sde_crtc_event_disable(struct sde_kms *kms,
  6109. struct drm_crtc *crtc_drm, u32 event)
  6110. {
  6111. struct sde_crtc *crtc = NULL;
  6112. struct sde_crtc_irq_info *node = NULL;
  6113. unsigned long flags;
  6114. bool found = false;
  6115. int ret;
  6116. crtc = to_sde_crtc(crtc_drm);
  6117. spin_lock_irqsave(&crtc->spin_lock, flags);
  6118. list_for_each_entry(node, &crtc->user_event_list, list) {
  6119. if (node->event == event) {
  6120. list_del_init(&node->list);
  6121. found = true;
  6122. break;
  6123. }
  6124. }
  6125. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6126. /* event already disabled */
  6127. if (!found)
  6128. return 0;
  6129. /**
  6130. * crtc is disabled interrupts are cleared remove from the list,
  6131. * no need to disable/de-register.
  6132. */
  6133. if (!crtc_drm->enabled) {
  6134. kfree(node);
  6135. return 0;
  6136. }
  6137. ret = pm_runtime_get_sync(crtc_drm->dev->dev);
  6138. if (ret < 0) {
  6139. SDE_ERROR("failed to enable power resource %d\n", ret);
  6140. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  6141. kfree(node);
  6142. return ret;
  6143. }
  6144. ret = node->func(crtc_drm, false, &node->irq);
  6145. if (ret) {
  6146. spin_lock_irqsave(&crtc->spin_lock, flags);
  6147. list_add_tail(&node->list, &crtc->user_event_list);
  6148. spin_unlock_irqrestore(&crtc->spin_lock, flags);
  6149. } else {
  6150. kfree(node);
  6151. }
  6152. pm_runtime_put_sync(crtc_drm->dev->dev);
  6153. return ret;
  6154. }
  6155. int sde_crtc_register_custom_event(struct sde_kms *kms,
  6156. struct drm_crtc *crtc_drm, u32 event, bool en)
  6157. {
  6158. struct sde_crtc *crtc = NULL;
  6159. int ret;
  6160. crtc = to_sde_crtc(crtc_drm);
  6161. if (!crtc || !kms || !kms->dev) {
  6162. DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc,
  6163. kms, ((kms) ? (kms->dev) : NULL));
  6164. return -EINVAL;
  6165. }
  6166. if (en)
  6167. ret = _sde_crtc_event_enable(kms, crtc_drm, event);
  6168. else
  6169. ret = _sde_crtc_event_disable(kms, crtc_drm, event);
  6170. return ret;
  6171. }
  6172. static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
  6173. bool en, struct sde_irq_callback *irq)
  6174. {
  6175. return 0;
  6176. }
  6177. static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
  6178. struct sde_irq_callback *noirq)
  6179. {
  6180. /*
  6181. * IRQ object noirq is not being used here since there is
  6182. * no crtc irq from pm event.
  6183. */
  6184. return 0;
  6185. }
  6186. static int sde_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
  6187. bool en, struct sde_irq_callback *irq)
  6188. {
  6189. return 0;
  6190. }
  6191. static int sde_crtc_mmrm_interrupt_handler(struct drm_crtc *crtc_drm,
  6192. bool en, struct sde_irq_callback *irq)
  6193. {
  6194. return 0;
  6195. }
  6196. /**
  6197. * sde_crtc_update_cont_splash_settings - update mixer settings
  6198. * and initial clk during device bootup for cont_splash use case
  6199. * @crtc: Pointer to drm crtc structure
  6200. */
  6201. void sde_crtc_update_cont_splash_settings(struct drm_crtc *crtc)
  6202. {
  6203. struct sde_kms *kms = NULL;
  6204. struct msm_drm_private *priv;
  6205. struct sde_crtc *sde_crtc;
  6206. u64 rate;
  6207. if (!crtc || !crtc->state || !crtc->dev || !crtc->dev->dev_private) {
  6208. SDE_ERROR("invalid crtc\n");
  6209. return;
  6210. }
  6211. priv = crtc->dev->dev_private;
  6212. kms = to_sde_kms(priv->kms);
  6213. if (!kms || !kms->catalog) {
  6214. SDE_ERROR("invalid parameters\n");
  6215. return;
  6216. }
  6217. _sde_crtc_setup_mixers(crtc);
  6218. sde_cp_crtc_refresh_status_properties(crtc);
  6219. crtc->enabled = true;
  6220. /* update core clk value for initial state with cont-splash */
  6221. sde_crtc = to_sde_crtc(crtc);
  6222. rate = sde_power_clk_get_rate(&priv->phandle, kms->perf.clk_name);
  6223. sde_crtc->cur_perf.core_clk_rate = (rate > 0) ?
  6224. rate : kms->perf.max_core_clk_rate;
  6225. sde_crtc->cur_perf.core_clk_rate = kms->perf.max_core_clk_rate;
  6226. }
  6227. static void sde_crtc_install_noise_layer_properties(struct sde_crtc *sde_crtc,
  6228. struct sde_mdss_cfg *catalog, struct sde_kms_info *info)
  6229. {
  6230. struct sde_lm_cfg *lm;
  6231. char feature_name[256];
  6232. u32 version;
  6233. if (!catalog->mixer_count)
  6234. return;
  6235. lm = &catalog->mixer[0];
  6236. if (!(lm->features & BIT(SDE_MIXER_NOISE_LAYER)))
  6237. return;
  6238. version = lm->sblk->nlayer.version >> 16;
  6239. snprintf(feature_name, ARRAY_SIZE(feature_name), "%s%d", "noise_layer_v", version);
  6240. switch (version) {
  6241. case 1:
  6242. sde_kms_info_add_keyint(info, "has_noise_layer", 1);
  6243. msm_property_install_volatile_range(&sde_crtc->property_info,
  6244. feature_name, 0x0, 0, ~0, 0, CRTC_PROP_NOISE_LAYER_V1);
  6245. break;
  6246. default:
  6247. SDE_ERROR("unsupported noise layer version %d\n", version);
  6248. break;
  6249. }
  6250. }
  6251. static int _sde_crtc_set_noise_layer(struct sde_crtc *sde_crtc,
  6252. struct sde_crtc_state *cstate,
  6253. void __user *usr_ptr)
  6254. {
  6255. int ret;
  6256. if (!sde_crtc || !cstate) {
  6257. SDE_ERROR("invalid sde_crtc/state\n");
  6258. return -EINVAL;
  6259. }
  6260. SDE_DEBUG("crtc %s\n", sde_crtc->name);
  6261. if (!usr_ptr) {
  6262. SDE_DEBUG("noise layer removed\n");
  6263. cstate->noise_layer_en = false;
  6264. set_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty);
  6265. return 0;
  6266. }
  6267. ret = copy_from_user(&cstate->layer_cfg, usr_ptr,
  6268. sizeof(cstate->layer_cfg));
  6269. if (ret) {
  6270. SDE_ERROR("failed to copy noise layer %d\n", ret);
  6271. return -EFAULT;
  6272. }
  6273. if (cstate->layer_cfg.zposn != cstate->layer_cfg.zposattn - 1 ||
  6274. cstate->layer_cfg.zposattn >= SDE_STAGE_MAX ||
  6275. !cstate->layer_cfg.attn_factor ||
  6276. cstate->layer_cfg.attn_factor > DRM_NOISE_ATTN_MAX ||
  6277. cstate->layer_cfg.strength > DRM_NOISE_STREN_MAX ||
  6278. !cstate->layer_cfg.alpha_noise ||
  6279. cstate->layer_cfg.alpha_noise > DRM_NOISE_ATTN_MAX) {
  6280. SDE_ERROR("invalid param zposn %d zposattn %d attn_factor %d \
  6281. strength %d alpha noise %d\n", cstate->layer_cfg.zposn,
  6282. cstate->layer_cfg.zposattn, cstate->layer_cfg.attn_factor,
  6283. cstate->layer_cfg.strength, cstate->layer_cfg.alpha_noise);
  6284. return -EINVAL;
  6285. }
  6286. cstate->noise_layer_en = true;
  6287. set_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty);
  6288. return 0;
  6289. }
  6290. static void sde_cp_crtc_apply_noise(struct drm_crtc *crtc,
  6291. struct drm_crtc_state *state)
  6292. {
  6293. struct sde_crtc *scrtc = to_sde_crtc(crtc);
  6294. struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
  6295. struct sde_hw_mixer *lm;
  6296. int i;
  6297. struct sde_hw_noise_layer_cfg cfg;
  6298. struct sde_kms *kms;
  6299. if (!test_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty))
  6300. return;
  6301. kms = _sde_crtc_get_kms(crtc);
  6302. if (!kms || !kms->catalog) {
  6303. SDE_ERROR("Invalid kms\n");
  6304. return;
  6305. }
  6306. cfg.flags = cstate->layer_cfg.flags;
  6307. cfg.alpha_noise = cstate->layer_cfg.alpha_noise;
  6308. cfg.attn_factor = cstate->layer_cfg.attn_factor;
  6309. cfg.strength = cstate->layer_cfg.strength;
  6310. if (!kms->catalog->has_base_layer) {
  6311. cfg.noise_blend_stage = cstate->layer_cfg.zposn + SDE_STAGE_0;
  6312. cfg.attn_blend_stage = cstate->layer_cfg.zposattn + SDE_STAGE_0;
  6313. } else {
  6314. cfg.noise_blend_stage = cstate->layer_cfg.zposn;
  6315. cfg.attn_blend_stage = cstate->layer_cfg.zposattn;
  6316. }
  6317. for (i = 0; i < scrtc->num_mixers; i++) {
  6318. lm = scrtc->mixers[i].hw_lm;
  6319. if (!lm->ops.setup_noise_layer)
  6320. break;
  6321. if (!cstate->noise_layer_en)
  6322. lm->ops.setup_noise_layer(lm, NULL);
  6323. else
  6324. lm->ops.setup_noise_layer(lm, &cfg);
  6325. }
  6326. if (!cstate->noise_layer_en)
  6327. clear_bit(SDE_CRTC_NOISE_LAYER, cstate->dirty);
  6328. }
  6329. void sde_crtc_disable_cp_features(struct drm_crtc *crtc)
  6330. {
  6331. sde_cp_disable_features(crtc);
  6332. }