d4422e276e
Add support for external mclk configuration based on input sample clock. Change-Id: I90b40636e6c3877c5ab9d2c2a60c4d61a83b149e Signed-off-by: Nirav Khatri <khatri@codeaurora.org>
160 linhas
5.7 KiB
C
160 linhas
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef __EP92_H__
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#define __EP92_H__
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/* EP92 register addresses */
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/* BI = Basic Info */
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#define EP92_BI_VENDOR_ID_0 0x00
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#define EP92_BI_VENDOR_ID_1 0x01
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#define EP92_BI_DEVICE_ID_0 0x02
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#define EP92_BI_DEVICE_ID_1 0x03
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#define EP92_BI_VERSION_NUM 0x04
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#define EP92_BI_VERSION_YEAR 0x05
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#define EP92_BI_VERSION_MONTH 0x06
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#define EP92_BI_VERSION_DATE 0x07
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#define EP92_BI_GENERAL_INFO_0 0x08
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#define EP92_BI_GENERAL_INFO_1 0x09
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#define EP92_BI_GENERAL_INFO_2 0x0A
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#define EP92_BI_GENERAL_INFO_3 0x0B
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#define EP92_BI_GENERAL_INFO_4 0x0C
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#define EP92_BI_GENERAL_INFO_5 0x0D
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#define EP92_BI_GENERAL_INFO_6 0x0E
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#define EP92_ISP_MODE_ENTER_ISP 0x0F
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#define EP92_GENERAL_CONTROL_0 0x10
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#define EP92_GENERAL_CONTROL_1 0x11
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#define EP92_GENERAL_CONTROL_2 0x12
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#define EP92_GENERAL_CONTROL_3 0x13
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#define EP92_GENERAL_CONTROL_4 0x14
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#define EP92_CEC_EVENT_CODE 0x15
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#define EP92_CEC_EVENT_PARAM_1 0x16
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#define EP92_CEC_EVENT_PARAM_2 0x17
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#define EP92_CEC_EVENT_PARAM_3 0x18
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#define EP92_CEC_EVENT_PARAM_4 0x19
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/* RESERVED 0x1A */
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/* ... ... */
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/* RESERVED 0x1F */
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#define EP92_AUDIO_INFO_SYSTEM_STATUS_0 0x20
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#define EP92_AUDIO_INFO_SYSTEM_STATUS_1 0x21
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#define EP92_AUDIO_INFO_AUDIO_STATUS 0x22
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#define EP92_AUDIO_INFO_CHANNEL_STATUS_0 0x23
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#define EP92_AUDIO_INFO_CHANNEL_STATUS_1 0x24
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#define EP92_AUDIO_INFO_CHANNEL_STATUS_2 0x25
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#define EP92_AUDIO_INFO_CHANNEL_STATUS_3 0x26
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#define EP92_AUDIO_INFO_CHANNEL_STATUS_4 0x27
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#define EP92_AUDIO_INFO_ADO_INFO_FRAME_0 0x28
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#define EP92_AUDIO_INFO_ADO_INFO_FRAME_1 0x29
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#define EP92_AUDIO_INFO_ADO_INFO_FRAME_2 0x2A
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#define EP92_AUDIO_INFO_ADO_INFO_FRAME_3 0x2B
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#define EP92_AUDIO_INFO_ADO_INFO_FRAME_4 0x2C
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#define EP92_AUDIO_INFO_ADO_INFO_FRAME_5 0x2D
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#define EP92_OTHER_PACKETS_HDMI_VS_0 0x2E
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#define EP92_OTHER_PACKETS_HDMI_VS_1 0x2F
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#define EP92_OTHER_PACKETS_ACP_PACKET 0x30
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#define EP92_OTHER_PACKETS_AVI_INFO_FRAME_0 0x31
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#define EP92_OTHER_PACKETS_AVI_INFO_FRAME_1 0x32
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#define EP92_OTHER_PACKETS_AVI_INFO_FRAME_2 0x33
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#define EP92_OTHER_PACKETS_AVI_INFO_FRAME_3 0x34
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#define EP92_OTHER_PACKETS_AVI_INFO_FRAME_4 0x35
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#define EP92_OTHER_PACKETS_GC_PACKET_0 0x36
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#define EP92_OTHER_PACKETS_GC_PACKET_1 0x37
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#define EP92_OTHER_PACKETS_GC_PACKET_2 0x38
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#define EP92_MAX_REGISTER_ADDR EP92_OTHER_PACKETS_GC_PACKET_2
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/* shift/masks for register bits
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* GI = General Info
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* GC = General Control
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* AI = Audio Info
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*/
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#define EP92_GI_ADO_CHF_MASK 0x01
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#define EP92_GI_CEC_ECF_MASK 0x02
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#define EP92_GI_TX_HOT_PLUG_SHIFT 7
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#define EP92_GI_TX_HOT_PLUG_MASK 0x80
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#define EP92_GI_VIDEO_LATENCY_SHIFT 0
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#define EP92_GI_VIDEO_LATENCY_MASK 0xff
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#define EP92_GC_POWER_SHIFT 7
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#define EP92_GC_POWER_MASK 0x80
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#define EP92_GC_AUDIO_PATH_SHIFT 5
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#define EP92_GC_AUDIO_PATH_MASK 0x20
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#define EP92_GC_CEC_MUTE_SHIFT 1
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#define EP92_GC_CEC_MUTE_MASK 0x02
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#define EP92_GC_ARC_EN_SHIFT 0
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#define EP92_GC_ARC_EN_MASK 0x01
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#define EP92_GC_ARC_DIS_SHIFT 6
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#define EP92_GC_ARC_DIS_MASK 0x40
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#define EP92_GC_RX_SEL_SHIFT 0
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#define EP92_GC_RX_SEL_MASK 0x07
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#define EP92_GC_CEC_VOLUME_SHIFT 0
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#define EP92_GC_CEC_VOLUME_MASK 0xff
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#define EP92_GC_LINK_ON0_SHIFT 0
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#define EP92_GC_LINK_ON0_MASK 0x01
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#define EP92_GC_LINK_ON1_SHIFT 1
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#define EP92_GC_LINK_ON1_MASK 0x02
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#define EP92_GC_LINK_ON2_SHIFT 2
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#define EP92_GC_LINK_ON2_MASK 0x04
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#define EP92_AI_MCLK_ON_SHIFT 6
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#define EP92_AI_MCLK_ON_MASK 0x40
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#define EP92_AI_AVMUTE_SHIFT 5
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#define EP92_AI_AVMUTE_MASK 0x20
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#define EP92_AI_LAYOUT_SHIFT 0
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#define EP92_AI_LAYOUT_MASK 0x01
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#define EP92_AI_HBR_ADO_SHIFT 5
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#define EP92_AI_HBR_ADO_MASK 0x20
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#define EP92_AI_STD_ADO_SHIFT 3
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#define EP92_AI_STD_ADO_MASK 0x08
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#define EP92_AI_RATE_MASK 0x07
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#define EP92_AI_NPCM_MASK 0x02
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#define EP92_AI_PREEMPH_SHIFT 3
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#define EP92_AI_PREEMPH_MASK 0x38
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#define EP92_AI_CH_COUNT_MASK 0x07
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#define EP92_AI_CH_ALLOC_MASK 0xff
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#define EP92_AI_DSD_ADO_SHIFT 4
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#define EP92_AI_DSD_ADO_MASK 0x10
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#define EP92_AI_DSD_RATE_SHIFT 4
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#define EP92_AI_DSD_RATE_MASK 0x30
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#define EP92_2CHOICE_MASK 1
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#define EP92_GC_CEC_VOLUME_MIN 0
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#define EP92_GC_CEC_VOLUME_MAX 100
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#define EP92_AI_RATE_MIN 0
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#define EP92_AI_RATE_MAX 768000
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#define EP92_AI_CH_COUNT_MIN 0
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#define EP92_AI_CH_COUNT_MAX 8
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#define EP92_AI_CH_ALLOC_MIN 0
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#define EP92_AI_CH_ALLOC_MAX 0xff
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#define EP92_STATUS_NO_SIGNAL 0
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#define EP92_STATUS_AUDIO_ACTIVE 1
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/* kcontrol storage indices */
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enum {
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EP92_KCTL_POWER = 0,
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EP92_KCTL_AUDIO_PATH,
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EP92_KCTL_CEC_MUTE,
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EP92_KCTL_ARC_EN,
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EP92_KCTL_RX_SEL,
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EP92_KCTL_CEC_VOLUME,
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EP92_KCTL_STATE,
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EP92_KCTL_AVMUTE,
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EP92_KCTL_LAYOUT,
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EP92_KCTL_MODE,
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EP92_KCTL_RATE,
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EP92_KCTL_CH_COUNT,
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EP92_KCTL_CH_ALLOC,
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EP92_KCTL_MAX
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};
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int ep92_set_ext_mclk(struct snd_soc_codec *codec, uint32_t mclk_freq);
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#endif /* __EP92_H__ */
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