eb601eca1e
Write TID-no correctly for DSCP-value if 2 consecutive registers are needed to configure the mapping. Change-Id: I857f95e2d1bda0214a32b2802f1dcc460be87085
243 sor
6.7 KiB
C
243 sor
6.7 KiB
C
/*
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* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hal_hw_headers.h"
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#include "hal_internal.h"
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#include "cdp_txrx_mon_struct.h"
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#include "qdf_trace.h"
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#include "hal_rx.h"
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#include "hal_tx.h"
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#include "dp_types.h"
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#include "hal_api_mon.h"
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/**
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* hal_tx_desc_set_dscp_tid_table_id_8074v2() - Sets DSCP to TID conversion
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* table ID
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* @desc: Handle to Tx Descriptor
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* @id: DSCP to tid conversion table to be used for this frame
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*
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* Return: void
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*/
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static void hal_tx_desc_set_dscp_tid_table_id_8074v2(void *desc, uint8_t id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_5,
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DSCP_TID_TABLE_NUM) |=
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HAL_TX_SM(TCL_DATA_CMD_5,
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DSCP_TID_TABLE_NUM, id);
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}
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#define DSCP_TID_TABLE_SIZE 24
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#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
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#define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
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/**
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* hal_tx_set_dscp_tid_map_8074v2() - Configure default DSCP to TID map table
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id: mapping table ID - 0,1
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*
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* DSCP are mapped to 8 TID values using TID values programmed
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* in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0)
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* and DSCP_TID2_MAP_<0 to 6> (id = 1)
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* Each mapping register has TID mapping for 10 DSCP values
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*
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* Return: none
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*/
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static void hal_tx_set_dscp_tid_map_8074v2(struct hal_soc *soc,
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uint8_t *map,
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uint8_t id)
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{
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int i;
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uint32_t addr, cmn_reg_addr;
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uint32_t value = 0, regval;
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uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
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if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS)
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return;
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cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
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id * NUM_WORDS_PER_DSCP_TID_TABLE);
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/* Enable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval |=
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(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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/* Write 8 (24 bits) DSCP-TID mappings in each interation */
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for (i = 0; i < 64; i += 8) {
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value = (map[i] |
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(map[i + 1] << 0x3) |
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(map[i + 2] << 0x6) |
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(map[i + 3] << 0x9) |
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(map[i + 4] << 0xc) |
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(map[i + 5] << 0xf) |
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(map[i + 6] << 0x12) |
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(map[i + 7] << 0x15));
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qdf_mem_copy(&val[cnt], &value, 3);
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cnt += 3;
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}
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for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
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regval = *(uint32_t *)(val + i);
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HAL_REG_WRITE(soc, addr,
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(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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addr += 4;
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}
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/* Diasble read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval &=
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~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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}
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/**
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* hal_tx_update_dscp_tid_8074v2() - Update the dscp tid map table as
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updated by user
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id : MAP ID
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* @dscp: DSCP_TID map index
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*
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* Return: void
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*/
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static void hal_tx_update_dscp_tid_8074v2(struct hal_soc *soc, uint8_t tid,
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uint8_t id, uint8_t dscp)
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{
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uint32_t addr, addr1, cmn_reg_addr, regmask = 0xFFFFFFFF;
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uint32_t start_value = 0, end_value = 0;
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uint32_t regval;
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uint8_t end_bits = 0;
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uint8_t start_bits = 0;
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uint32_t start_index, end_index;
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cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
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id * NUM_WORDS_PER_DSCP_TID_TABLE);
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start_index = dscp * HAL_TX_BITS_PER_TID;
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end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
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% HAL_TX_NUM_DSCP_REGISTER_SIZE;
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start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
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addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
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HAL_TX_NUM_DSCP_REGISTER_SIZE));
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if (end_index < start_index) {
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end_bits = end_index + 1;
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start_bits = HAL_TX_BITS_PER_TID - end_bits;
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start_value = tid << start_index;
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end_value = tid >> start_bits;
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addr1 = addr + 4;
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} else {
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start_bits = HAL_TX_BITS_PER_TID - end_bits;
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start_value = tid << start_index;
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addr1 = 0;
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}
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/* Enable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval |=
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(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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regval = HAL_REG_READ(soc, addr);
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if (end_index < start_index)
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regval &= (regmask >> start_bits);
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else
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regval &= ~(7 << start_index);
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regval |= start_value;
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HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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if (addr1) {
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regval = HAL_REG_READ(soc, addr1);
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regval &= (~0) << end_bits;
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regval |= end_value;
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HAL_REG_WRITE(soc, addr1, (regval &
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HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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}
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/* Diasble read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval &=
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~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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}
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/**
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* hal_tx_desc_set_lmac_id - Set the lmac_id value
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* @desc: Handle to Tx Descriptor
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* @lmac_id: mac Id to ast matching
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* b00 – mac 0
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* b01 – mac 1
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* b10 – mac 2
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* b11 – all macs (legacy HK way)
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*
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* Return: void
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*/
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static void hal_tx_desc_set_lmac_id_8074v2(void *desc, uint8_t lmac_id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
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HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
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}
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/**
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* hal_tx_init_cmd_credit_ring_8074v2() - Initialize command/credit SRNG
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* @hal_soc_hdl: Handle to HAL SoC structure
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* @hal_srng: Handle to HAL SRNG structure
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*
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* Return: none
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*/
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static inline void hal_tx_init_cmd_credit_ring_8074v2(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl)
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{
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uint8_t *desc_addr;
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struct hal_srng_params srng_params;
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uint32_t desc_size;
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uint32_t num_desc;
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hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params);
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desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
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desc_size = sizeof(struct tcl_data_cmd);
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num_desc = srng_params.num_entries;
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while (num_desc) {
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/* using CMD/CREDIT Ring to send DATA CMD tag */
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HAL_TX_DESC_SET_TLV_HDR(desc_addr, WIFITCL_DATA_CMD_E,
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desc_size);
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desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
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num_desc--;
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}
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}
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