main.c 109 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/elf.h>
  9. #include <linux/jiffies.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/pm_wakeup.h>
  15. #include <linux/reboot.h>
  16. #include <linux/rwsem.h>
  17. #include <linux/suspend.h>
  18. #include <linux/timer.h>
  19. #include <linux/version.h>
  20. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0))
  21. #include <linux/panic_notifier.h>
  22. #endif
  23. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  24. #include <soc/qcom/minidump.h>
  25. #endif
  26. #include "cnss_plat_ipc_qmi.h"
  27. #include "cnss_utils.h"
  28. #include "main.h"
  29. #include "bus.h"
  30. #include "debug.h"
  31. #include "genl.h"
  32. #include "reg.h"
  33. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  34. #include "smcinvoke.h"
  35. #include "smcinvoke_object.h"
  36. #include "IClientEnv.h"
  37. #define HW_STATE_UID 0x108
  38. #define HW_OP_GET_STATE 1
  39. #define HW_WIFI_UID 0x508
  40. #define FEATURE_NOT_SUPPORTED 12
  41. #define PERIPHERAL_NOT_FOUND 10
  42. #endif
  43. #define CNSS_DUMP_FORMAT_VER 0x11
  44. #define CNSS_DUMP_FORMAT_VER_V2 0x22
  45. #define CNSS_DUMP_MAGIC_VER_V2 0x42445953
  46. #define CNSS_DUMP_NAME "CNSS_WLAN"
  47. #define CNSS_DUMP_DESC_SIZE 0x1000
  48. #define CNSS_DUMP_SEG_VER 0x1
  49. #define FILE_SYSTEM_READY 1
  50. #define FW_READY_TIMEOUT 20000
  51. #define FW_ASSERT_TIMEOUT 5000
  52. #define CNSS_EVENT_PENDING 2989
  53. #define POWER_RESET_MIN_DELAY_MS 100
  54. #define CNSS_QUIRKS_DEFAULT 0
  55. #ifdef CONFIG_CNSS_EMULATION
  56. #define CNSS_MHI_TIMEOUT_DEFAULT 90000
  57. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 2000
  58. #define CNSS_QMI_TIMEOUT_DEFAULT 90000
  59. #else
  60. #define CNSS_MHI_TIMEOUT_DEFAULT 0
  61. #define CNSS_MHI_M2_TIMEOUT_DEFAULT 25
  62. #define CNSS_QMI_TIMEOUT_DEFAULT 10000
  63. #endif
  64. #define CNSS_BDF_TYPE_DEFAULT CNSS_BDF_ELF
  65. #define CNSS_TIME_SYNC_PERIOD_DEFAULT 900000
  66. #define CNSS_MIN_TIME_SYNC_PERIOD 2000
  67. #define CNSS_DMS_QMI_CONNECTION_WAIT_MS 50
  68. #define CNSS_DMS_QMI_CONNECTION_WAIT_RETRY 200
  69. #define CNSS_DAEMON_CONNECT_TIMEOUT_MS 30000
  70. #define CNSS_CAL_DB_FILE_NAME "wlfw_cal_db.bin"
  71. #define CNSS_CAL_START_PROBE_WAIT_RETRY_MAX 100
  72. #define CNSS_CAL_START_PROBE_WAIT_MS 500
  73. enum cnss_cal_db_op {
  74. CNSS_CAL_DB_UPLOAD,
  75. CNSS_CAL_DB_DOWNLOAD,
  76. CNSS_CAL_DB_INVALID_OP,
  77. };
  78. enum cnss_recovery_type {
  79. CNSS_WLAN_RECOVERY = 0x1,
  80. CNSS_PCSS_RECOVERY = 0x2,
  81. };
  82. static struct cnss_plat_data *plat_env;
  83. static bool cnss_allow_driver_loading;
  84. static DECLARE_RWSEM(cnss_pm_sem);
  85. static struct cnss_fw_files FW_FILES_QCA6174_FW_3_0 = {
  86. "qwlan30.bin", "bdwlan30.bin", "otp30.bin", "utf30.bin",
  87. "utfbd30.bin", "epping30.bin", "evicted30.bin"
  88. };
  89. static struct cnss_fw_files FW_FILES_DEFAULT = {
  90. "qwlan.bin", "bdwlan.bin", "otp.bin", "utf.bin",
  91. "utfbd.bin", "epping.bin", "evicted.bin"
  92. };
  93. struct cnss_driver_event {
  94. struct list_head list;
  95. enum cnss_driver_event_type type;
  96. bool sync;
  97. struct completion complete;
  98. int ret;
  99. void *data;
  100. };
  101. static void cnss_set_plat_priv(struct platform_device *plat_dev,
  102. struct cnss_plat_data *plat_priv)
  103. {
  104. plat_env = plat_priv;
  105. }
  106. bool cnss_check_driver_loading_allowed(void)
  107. {
  108. return cnss_allow_driver_loading;
  109. }
  110. struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev)
  111. {
  112. return plat_env;
  113. }
  114. /**
  115. * cnss_get_mem_seg_count - Get segment count of memory
  116. * @type: memory type
  117. * @seg: segment count
  118. *
  119. * Return: 0 on success, negative value on failure
  120. */
  121. int cnss_get_mem_seg_count(enum cnss_remote_mem_type type, u32 *seg)
  122. {
  123. struct cnss_plat_data *plat_priv;
  124. plat_priv = cnss_get_plat_priv(NULL);
  125. if (!plat_priv)
  126. return -ENODEV;
  127. switch (type) {
  128. case CNSS_REMOTE_MEM_TYPE_FW:
  129. *seg = plat_priv->fw_mem_seg_len;
  130. break;
  131. case CNSS_REMOTE_MEM_TYPE_QDSS:
  132. *seg = plat_priv->qdss_mem_seg_len;
  133. break;
  134. default:
  135. return -EINVAL;
  136. }
  137. return 0;
  138. }
  139. EXPORT_SYMBOL(cnss_get_mem_seg_count);
  140. /**
  141. * cnss_get_mem_segment_info - Get memory info of different type
  142. * @type: memory type
  143. * @segment: array to save the segment info
  144. * @seg: segment count
  145. *
  146. * Return: 0 on success, negative value on failure
  147. */
  148. int cnss_get_mem_segment_info(enum cnss_remote_mem_type type,
  149. struct cnss_mem_segment segment[],
  150. u32 segment_count)
  151. {
  152. struct cnss_plat_data *plat_priv;
  153. u32 i;
  154. plat_priv = cnss_get_plat_priv(NULL);
  155. if (!plat_priv)
  156. return -ENODEV;
  157. switch (type) {
  158. case CNSS_REMOTE_MEM_TYPE_FW:
  159. if (segment_count > plat_priv->fw_mem_seg_len)
  160. segment_count = plat_priv->fw_mem_seg_len;
  161. for (i = 0; i < segment_count; i++) {
  162. segment[i].size = plat_priv->fw_mem[i].size;
  163. segment[i].va = plat_priv->fw_mem[i].va;
  164. segment[i].pa = plat_priv->fw_mem[i].pa;
  165. }
  166. break;
  167. case CNSS_REMOTE_MEM_TYPE_QDSS:
  168. if (segment_count > plat_priv->qdss_mem_seg_len)
  169. segment_count = plat_priv->qdss_mem_seg_len;
  170. for (i = 0; i < segment_count; i++) {
  171. segment[i].size = plat_priv->qdss_mem[i].size;
  172. segment[i].va = plat_priv->qdss_mem[i].va;
  173. segment[i].pa = plat_priv->qdss_mem[i].pa;
  174. }
  175. break;
  176. default:
  177. return -EINVAL;
  178. }
  179. return 0;
  180. }
  181. EXPORT_SYMBOL(cnss_get_mem_segment_info);
  182. int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
  183. enum cnss_feature_v01 feature)
  184. {
  185. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  186. return -EINVAL;
  187. plat_priv->feature_list |= 1 << feature;
  188. return 0;
  189. }
  190. int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
  191. enum cnss_feature_v01 feature)
  192. {
  193. if (unlikely(!plat_priv || feature >= CNSS_MAX_FEATURE_V01))
  194. return -EINVAL;
  195. plat_priv->feature_list &= ~(1 << feature);
  196. return 0;
  197. }
  198. int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
  199. u64 *feature_list)
  200. {
  201. if (unlikely(!plat_priv))
  202. return -EINVAL;
  203. *feature_list = plat_priv->feature_list;
  204. return 0;
  205. }
  206. static int cnss_pm_notify(struct notifier_block *b,
  207. unsigned long event, void *p)
  208. {
  209. switch (event) {
  210. case PM_SUSPEND_PREPARE:
  211. down_write(&cnss_pm_sem);
  212. break;
  213. case PM_POST_SUSPEND:
  214. up_write(&cnss_pm_sem);
  215. break;
  216. }
  217. return NOTIFY_DONE;
  218. }
  219. static struct notifier_block cnss_pm_notifier = {
  220. .notifier_call = cnss_pm_notify,
  221. };
  222. void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv)
  223. {
  224. if (atomic_inc_return(&plat_priv->pm_count) != 1)
  225. return;
  226. cnss_pr_dbg("PM stay awake, state: 0x%lx, count: %d\n",
  227. plat_priv->driver_state,
  228. atomic_read(&plat_priv->pm_count));
  229. pm_stay_awake(&plat_priv->plat_dev->dev);
  230. }
  231. void cnss_pm_relax(struct cnss_plat_data *plat_priv)
  232. {
  233. int r = atomic_dec_return(&plat_priv->pm_count);
  234. WARN_ON(r < 0);
  235. if (r != 0)
  236. return;
  237. cnss_pr_dbg("PM relax, state: 0x%lx, count: %d\n",
  238. plat_priv->driver_state,
  239. atomic_read(&plat_priv->pm_count));
  240. pm_relax(&plat_priv->plat_dev->dev);
  241. }
  242. void cnss_lock_pm_sem(struct device *dev)
  243. {
  244. down_read(&cnss_pm_sem);
  245. }
  246. EXPORT_SYMBOL(cnss_lock_pm_sem);
  247. void cnss_release_pm_sem(struct device *dev)
  248. {
  249. up_read(&cnss_pm_sem);
  250. }
  251. EXPORT_SYMBOL(cnss_release_pm_sem);
  252. int cnss_get_fw_files_for_target(struct device *dev,
  253. struct cnss_fw_files *pfw_files,
  254. u32 target_type, u32 target_version)
  255. {
  256. if (!pfw_files)
  257. return -ENODEV;
  258. switch (target_version) {
  259. case QCA6174_REV3_VERSION:
  260. case QCA6174_REV3_2_VERSION:
  261. memcpy(pfw_files, &FW_FILES_QCA6174_FW_3_0, sizeof(*pfw_files));
  262. break;
  263. default:
  264. memcpy(pfw_files, &FW_FILES_DEFAULT, sizeof(*pfw_files));
  265. cnss_pr_err("Unknown target version, type: 0x%X, version: 0x%X",
  266. target_type, target_version);
  267. break;
  268. }
  269. return 0;
  270. }
  271. EXPORT_SYMBOL(cnss_get_fw_files_for_target);
  272. int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
  273. {
  274. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  275. if (!plat_priv)
  276. return -ENODEV;
  277. if (!cap)
  278. return -EINVAL;
  279. *cap = plat_priv->cap;
  280. cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);
  281. return 0;
  282. }
  283. EXPORT_SYMBOL(cnss_get_platform_cap);
  284. void cnss_request_pm_qos(struct device *dev, u32 qos_val)
  285. {
  286. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  287. if (!plat_priv)
  288. return;
  289. cpu_latency_qos_add_request(&plat_priv->qos_request, qos_val);
  290. }
  291. EXPORT_SYMBOL(cnss_request_pm_qos);
  292. void cnss_remove_pm_qos(struct device *dev)
  293. {
  294. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  295. if (!plat_priv)
  296. return;
  297. cpu_latency_qos_remove_request(&plat_priv->qos_request);
  298. }
  299. EXPORT_SYMBOL(cnss_remove_pm_qos);
  300. int cnss_wlan_enable(struct device *dev,
  301. struct cnss_wlan_enable_cfg *config,
  302. enum cnss_driver_mode mode,
  303. const char *host_version)
  304. {
  305. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  306. int ret = 0;
  307. if (!plat_priv)
  308. return -ENODEV;
  309. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  310. return 0;
  311. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  312. return 0;
  313. if (!config || !host_version) {
  314. cnss_pr_err("Invalid config or host_version pointer\n");
  315. return -EINVAL;
  316. }
  317. cnss_pr_dbg("Mode: %d, config: %pK, host_version: %s\n",
  318. mode, config, host_version);
  319. if (mode == CNSS_WALTEST || mode == CNSS_CCPM)
  320. goto skip_cfg;
  321. ret = cnss_wlfw_wlan_cfg_send_sync(plat_priv, config, host_version);
  322. if (ret)
  323. goto out;
  324. skip_cfg:
  325. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, mode);
  326. out:
  327. return ret;
  328. }
  329. EXPORT_SYMBOL(cnss_wlan_enable);
  330. int cnss_wlan_disable(struct device *dev, enum cnss_driver_mode mode)
  331. {
  332. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  333. int ret = 0;
  334. if (!plat_priv)
  335. return -ENODEV;
  336. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  337. return 0;
  338. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks))
  339. return 0;
  340. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  341. cnss_bus_free_qdss_mem(plat_priv);
  342. return ret;
  343. }
  344. EXPORT_SYMBOL(cnss_wlan_disable);
  345. int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
  346. u32 data_len, u8 *output)
  347. {
  348. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  349. int ret = 0;
  350. if (!plat_priv) {
  351. cnss_pr_err("plat_priv is NULL!\n");
  352. return -EINVAL;
  353. }
  354. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  355. return 0;
  356. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  357. cnss_pr_err("Invalid state for athdiag read: 0x%lx\n",
  358. plat_priv->driver_state);
  359. ret = -EINVAL;
  360. goto out;
  361. }
  362. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, offset, mem_type,
  363. data_len, output);
  364. out:
  365. return ret;
  366. }
  367. EXPORT_SYMBOL(cnss_athdiag_read);
  368. int cnss_athdiag_write(struct device *dev, u32 offset, u32 mem_type,
  369. u32 data_len, u8 *input)
  370. {
  371. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  372. int ret = 0;
  373. if (!plat_priv) {
  374. cnss_pr_err("plat_priv is NULL!\n");
  375. return -EINVAL;
  376. }
  377. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  378. return 0;
  379. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  380. cnss_pr_err("Invalid state for athdiag write: 0x%lx\n",
  381. plat_priv->driver_state);
  382. ret = -EINVAL;
  383. goto out;
  384. }
  385. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, offset, mem_type,
  386. data_len, input);
  387. out:
  388. return ret;
  389. }
  390. EXPORT_SYMBOL(cnss_athdiag_write);
  391. int cnss_set_fw_log_mode(struct device *dev, u8 fw_log_mode)
  392. {
  393. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  394. if (!plat_priv)
  395. return -ENODEV;
  396. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  397. return 0;
  398. return cnss_wlfw_ini_send_sync(plat_priv, fw_log_mode);
  399. }
  400. EXPORT_SYMBOL(cnss_set_fw_log_mode);
  401. int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed)
  402. {
  403. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  404. if (!plat_priv)
  405. return -EINVAL;
  406. if (!plat_priv->fw_pcie_gen_switch) {
  407. cnss_pr_err("Firmware does not support PCIe gen switch\n");
  408. return -EOPNOTSUPP;
  409. }
  410. if (pcie_gen_speed < QMI_PCIE_GEN_SPEED_1_V01 ||
  411. pcie_gen_speed > QMI_PCIE_GEN_SPEED_3_V01)
  412. return -EINVAL;
  413. cnss_pr_dbg("WLAN provided PCIE gen speed: %d\n", pcie_gen_speed);
  414. plat_priv->pcie_gen_speed = pcie_gen_speed;
  415. return 0;
  416. }
  417. EXPORT_SYMBOL(cnss_set_pcie_gen_speed);
  418. static int cnss_fw_mem_ready_hdlr(struct cnss_plat_data *plat_priv)
  419. {
  420. int ret = 0;
  421. if (!plat_priv)
  422. return -ENODEV;
  423. set_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  424. ret = cnss_wlfw_tgt_cap_send_sync(plat_priv);
  425. if (ret)
  426. goto out;
  427. if (plat_priv->hds_enabled)
  428. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_HDS);
  429. cnss_wlfw_bdf_dnld_send_sync(plat_priv, CNSS_BDF_REGDB);
  430. cnss_wlfw_ini_file_send_sync(plat_priv, WLFW_CONN_ROAM_INI_V01);
  431. ret = cnss_wlfw_bdf_dnld_send_sync(plat_priv,
  432. plat_priv->ctrl_params.bdf_type);
  433. if (ret)
  434. goto out;
  435. ret = cnss_bus_load_m3(plat_priv);
  436. if (ret)
  437. goto out;
  438. ret = cnss_wlfw_m3_dnld_send_sync(plat_priv);
  439. if (ret)
  440. goto out;
  441. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  442. return 0;
  443. out:
  444. return ret;
  445. }
  446. static int cnss_request_antenna_sharing(struct cnss_plat_data *plat_priv)
  447. {
  448. int ret = 0;
  449. if (!plat_priv->antenna) {
  450. ret = cnss_wlfw_antenna_switch_send_sync(plat_priv);
  451. if (ret)
  452. goto out;
  453. }
  454. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state)) {
  455. ret = coex_antenna_switch_to_wlan_send_sync_msg(plat_priv);
  456. if (ret)
  457. goto out;
  458. }
  459. ret = cnss_wlfw_antenna_grant_send_sync(plat_priv);
  460. if (ret)
  461. goto out;
  462. return 0;
  463. out:
  464. return ret;
  465. }
  466. static void cnss_release_antenna_sharing(struct cnss_plat_data *plat_priv)
  467. {
  468. if (test_bit(CNSS_COEX_CONNECTED, &plat_priv->driver_state))
  469. coex_antenna_switch_to_mdm_send_sync_msg(plat_priv);
  470. }
  471. static int cnss_setup_dms_mac(struct cnss_plat_data *plat_priv)
  472. {
  473. u32 i;
  474. int ret = 0;
  475. struct cnss_plat_ipc_daemon_config *cfg;
  476. ret = cnss_qmi_get_dms_mac(plat_priv);
  477. if (ret == 0 && plat_priv->dms.mac_valid)
  478. goto qmi_send;
  479. /* DTSI property use-nv-mac is used to force DMS MAC address for WLAN.
  480. * Thus assert on failure to get MAC from DMS even after retries
  481. */
  482. if (plat_priv->use_nv_mac) {
  483. /* Check if Daemon says platform support DMS MAC provisioning */
  484. cfg = cnss_plat_ipc_qmi_daemon_config();
  485. if (cfg) {
  486. if (!cfg->dms_mac_addr_supported) {
  487. cnss_pr_err("DMS MAC address not supported\n");
  488. CNSS_ASSERT(0);
  489. return -EINVAL;
  490. }
  491. }
  492. for (i = 0; i < CNSS_DMS_QMI_CONNECTION_WAIT_RETRY; i++) {
  493. if (plat_priv->dms.mac_valid)
  494. break;
  495. ret = cnss_qmi_get_dms_mac(plat_priv);
  496. if (ret == 0)
  497. break;
  498. msleep(CNSS_DMS_QMI_CONNECTION_WAIT_MS);
  499. }
  500. if (!plat_priv->dms.mac_valid) {
  501. cnss_pr_err("Unable to get MAC from DMS after retries\n");
  502. CNSS_ASSERT(0);
  503. return -EINVAL;
  504. }
  505. }
  506. qmi_send:
  507. if (plat_priv->dms.mac_valid)
  508. ret =
  509. cnss_wlfw_wlan_mac_req_send_sync(plat_priv, plat_priv->dms.mac,
  510. ARRAY_SIZE(plat_priv->dms.mac));
  511. return ret;
  512. }
  513. static int cnss_cal_db_mem_update(struct cnss_plat_data *plat_priv,
  514. enum cnss_cal_db_op op, u32 *size)
  515. {
  516. int ret = 0;
  517. u32 timeout = cnss_get_timeout(plat_priv,
  518. CNSS_TIMEOUT_DAEMON_CONNECTION);
  519. enum cnss_plat_ipc_qmi_client_id_v01 client_id =
  520. CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01;
  521. if (op >= CNSS_CAL_DB_INVALID_OP)
  522. return -EINVAL;
  523. if (!plat_priv->cbc_file_download) {
  524. cnss_pr_info("CAL DB file not required as per BDF\n");
  525. return 0;
  526. }
  527. if (*size == 0) {
  528. cnss_pr_err("Invalid cal file size\n");
  529. return -EINVAL;
  530. }
  531. if (!test_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state)) {
  532. cnss_pr_info("Waiting for CNSS Daemon connection\n");
  533. ret = wait_for_completion_timeout(&plat_priv->daemon_connected,
  534. msecs_to_jiffies(timeout));
  535. if (!ret) {
  536. cnss_pr_err("Daemon not yet connected\n");
  537. CNSS_ASSERT(0);
  538. return ret;
  539. }
  540. }
  541. if (!plat_priv->cal_mem->va) {
  542. cnss_pr_err("CAL DB Memory not setup for FW\n");
  543. return -EINVAL;
  544. }
  545. /* Copy CAL DB file contents to/from CAL_TYPE_DDR mem allocated to FW */
  546. if (op == CNSS_CAL_DB_DOWNLOAD) {
  547. cnss_pr_dbg("Initiating Calibration file download to mem\n");
  548. ret = cnss_plat_ipc_qmi_file_download(client_id,
  549. CNSS_CAL_DB_FILE_NAME,
  550. plat_priv->cal_mem->va,
  551. size);
  552. } else {
  553. cnss_pr_dbg("Initiating Calibration mem upload to file\n");
  554. ret = cnss_plat_ipc_qmi_file_upload(client_id,
  555. CNSS_CAL_DB_FILE_NAME,
  556. plat_priv->cal_mem->va,
  557. *size);
  558. }
  559. if (ret)
  560. cnss_pr_err("Cal DB file %s %s failure\n",
  561. CNSS_CAL_DB_FILE_NAME,
  562. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload");
  563. else
  564. cnss_pr_dbg("Cal DB file %s %s size %d done\n",
  565. CNSS_CAL_DB_FILE_NAME,
  566. op == CNSS_CAL_DB_DOWNLOAD ? "download" : "upload",
  567. *size);
  568. return ret;
  569. }
  570. static int cnss_cal_mem_upload_to_file(struct cnss_plat_data *plat_priv)
  571. {
  572. if (plat_priv->cal_file_size > plat_priv->cal_mem->size) {
  573. cnss_pr_err("Cal file size is larger than Cal DB Mem size\n");
  574. return -EINVAL;
  575. }
  576. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_UPLOAD,
  577. &plat_priv->cal_file_size);
  578. }
  579. static int cnss_cal_file_download_to_mem(struct cnss_plat_data *plat_priv,
  580. u32 *cal_file_size)
  581. {
  582. /* To download pass the total size of cal DB mem allocated.
  583. * After cal file is download to mem, its size is updated in
  584. * return pointer
  585. */
  586. *cal_file_size = plat_priv->cal_mem->size;
  587. return cnss_cal_db_mem_update(plat_priv, CNSS_CAL_DB_DOWNLOAD,
  588. cal_file_size);
  589. }
  590. static int cnss_fw_ready_hdlr(struct cnss_plat_data *plat_priv)
  591. {
  592. int ret = 0;
  593. u32 cal_file_size = 0;
  594. if (!plat_priv)
  595. return -ENODEV;
  596. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  597. cnss_pr_err("Reboot is in progress, ignore FW ready\n");
  598. return -EINVAL;
  599. }
  600. cnss_pr_dbg("Processing FW Init Done..\n");
  601. del_timer(&plat_priv->fw_boot_timer);
  602. set_bit(CNSS_FW_READY, &plat_priv->driver_state);
  603. clear_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state);
  604. cnss_wlfw_send_pcie_gen_speed_sync(plat_priv);
  605. if (test_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state)) {
  606. clear_bit(CNSS_FW_BOOT_RECOVERY, &plat_priv->driver_state);
  607. clear_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  608. }
  609. if (test_bit(ENABLE_WALTEST, &plat_priv->ctrl_params.quirks)) {
  610. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  611. CNSS_WALTEST);
  612. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  613. cnss_request_antenna_sharing(plat_priv);
  614. cnss_cal_file_download_to_mem(plat_priv, &cal_file_size);
  615. cnss_wlfw_cal_report_req_send_sync(plat_priv, cal_file_size);
  616. plat_priv->cal_time = jiffies;
  617. ret = cnss_wlfw_wlan_mode_send_sync(plat_priv,
  618. CNSS_CALIBRATION);
  619. } else {
  620. ret = cnss_setup_dms_mac(plat_priv);
  621. ret = cnss_bus_call_driver_probe(plat_priv);
  622. }
  623. if (ret && test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  624. goto out;
  625. else if (ret)
  626. goto shutdown;
  627. cnss_vreg_unvote_type(plat_priv, CNSS_VREG_PRIM);
  628. return 0;
  629. shutdown:
  630. cnss_bus_dev_shutdown(plat_priv);
  631. clear_bit(CNSS_FW_READY, &plat_priv->driver_state);
  632. clear_bit(CNSS_FW_MEM_READY, &plat_priv->driver_state);
  633. out:
  634. return ret;
  635. }
  636. static char *cnss_driver_event_to_str(enum cnss_driver_event_type type)
  637. {
  638. switch (type) {
  639. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  640. return "SERVER_ARRIVE";
  641. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  642. return "SERVER_EXIT";
  643. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  644. return "REQUEST_MEM";
  645. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  646. return "FW_MEM_READY";
  647. case CNSS_DRIVER_EVENT_FW_READY:
  648. return "FW_READY";
  649. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  650. return "COLD_BOOT_CAL_START";
  651. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  652. return "COLD_BOOT_CAL_DONE";
  653. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  654. return "REGISTER_DRIVER";
  655. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  656. return "UNREGISTER_DRIVER";
  657. case CNSS_DRIVER_EVENT_RECOVERY:
  658. return "RECOVERY";
  659. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  660. return "FORCE_FW_ASSERT";
  661. case CNSS_DRIVER_EVENT_POWER_UP:
  662. return "POWER_UP";
  663. case CNSS_DRIVER_EVENT_POWER_DOWN:
  664. return "POWER_DOWN";
  665. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  666. return "IDLE_RESTART";
  667. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  668. return "IDLE_SHUTDOWN";
  669. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  670. return "IMS_WFC_CALL_IND";
  671. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  672. return "WLFW_TWC_CFG_IND";
  673. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  674. return "QDSS_TRACE_REQ_MEM";
  675. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  676. return "FW_MEM_FILE_SAVE";
  677. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  678. return "QDSS_TRACE_FREE";
  679. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  680. return "QDSS_TRACE_REQ_DATA";
  681. case CNSS_DRIVER_EVENT_MAX:
  682. return "EVENT_MAX";
  683. }
  684. return "UNKNOWN";
  685. };
  686. int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
  687. enum cnss_driver_event_type type,
  688. u32 flags, void *data)
  689. {
  690. struct cnss_driver_event *event;
  691. unsigned long irq_flags;
  692. int gfp = GFP_KERNEL;
  693. int ret = 0;
  694. if (!plat_priv)
  695. return -ENODEV;
  696. cnss_pr_dbg("Posting event: %s(%d)%s, state: 0x%lx flags: 0x%0x\n",
  697. cnss_driver_event_to_str(type), type,
  698. flags ? "-sync" : "", plat_priv->driver_state, flags);
  699. if (type >= CNSS_DRIVER_EVENT_MAX) {
  700. cnss_pr_err("Invalid Event type: %d, can't post", type);
  701. return -EINVAL;
  702. }
  703. if (in_interrupt() || irqs_disabled())
  704. gfp = GFP_ATOMIC;
  705. event = kzalloc(sizeof(*event), gfp);
  706. if (!event)
  707. return -ENOMEM;
  708. cnss_pm_stay_awake(plat_priv);
  709. event->type = type;
  710. event->data = data;
  711. init_completion(&event->complete);
  712. event->ret = CNSS_EVENT_PENDING;
  713. event->sync = !!(flags & CNSS_EVENT_SYNC);
  714. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  715. list_add_tail(&event->list, &plat_priv->event_list);
  716. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  717. queue_work(plat_priv->event_wq, &plat_priv->event_work);
  718. if (!(flags & CNSS_EVENT_SYNC))
  719. goto out;
  720. if (flags & CNSS_EVENT_UNKILLABLE)
  721. wait_for_completion(&event->complete);
  722. else if (flags & CNSS_EVENT_UNINTERRUPTIBLE)
  723. ret = wait_for_completion_killable(&event->complete);
  724. else
  725. ret = wait_for_completion_interruptible(&event->complete);
  726. cnss_pr_dbg("Completed event: %s(%d), state: 0x%lx, ret: %d/%d\n",
  727. cnss_driver_event_to_str(type), type,
  728. plat_priv->driver_state, ret, event->ret);
  729. spin_lock_irqsave(&plat_priv->event_lock, irq_flags);
  730. if (ret == -ERESTARTSYS && event->ret == CNSS_EVENT_PENDING) {
  731. event->sync = false;
  732. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  733. ret = -EINTR;
  734. goto out;
  735. }
  736. spin_unlock_irqrestore(&plat_priv->event_lock, irq_flags);
  737. ret = event->ret;
  738. kfree(event);
  739. out:
  740. cnss_pm_relax(plat_priv);
  741. return ret;
  742. }
  743. /**
  744. * cnss_get_timeout - Get timeout for corresponding type.
  745. * @plat_priv: Pointer to platform driver context.
  746. * @cnss_timeout_type: Timeout type.
  747. *
  748. * Return: Timeout in milliseconds.
  749. */
  750. unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
  751. enum cnss_timeout_type timeout_type)
  752. {
  753. unsigned int qmi_timeout = cnss_get_qmi_timeout(plat_priv);
  754. switch (timeout_type) {
  755. case CNSS_TIMEOUT_QMI:
  756. return qmi_timeout;
  757. case CNSS_TIMEOUT_POWER_UP:
  758. return (qmi_timeout << 2);
  759. case CNSS_TIMEOUT_IDLE_RESTART:
  760. /* In idle restart power up sequence, we have fw_boot_timer to
  761. * handle FW initialization failure.
  762. * It uses WLAN_MISSION_MODE_TIMEOUT, so setup 3x that time to
  763. * account for FW dump collection and FW re-initialization on
  764. * retry.
  765. */
  766. return (qmi_timeout + WLAN_MISSION_MODE_TIMEOUT * 3);
  767. case CNSS_TIMEOUT_CALIBRATION:
  768. /* Similar to mission mode, in CBC if FW init fails
  769. * fw recovery is tried. Thus return 2x the CBC timeout.
  770. */
  771. return (qmi_timeout + WLAN_COLD_BOOT_CAL_TIMEOUT * 2);
  772. case CNSS_TIMEOUT_WLAN_WATCHDOG:
  773. return ((qmi_timeout << 1) + WLAN_WD_TIMEOUT_MS);
  774. case CNSS_TIMEOUT_RDDM:
  775. return CNSS_RDDM_TIMEOUT_MS;
  776. case CNSS_TIMEOUT_RECOVERY:
  777. return RECOVERY_TIMEOUT;
  778. case CNSS_TIMEOUT_DAEMON_CONNECTION:
  779. return qmi_timeout + CNSS_DAEMON_CONNECT_TIMEOUT_MS;
  780. default:
  781. return qmi_timeout;
  782. }
  783. }
  784. unsigned int cnss_get_boot_timeout(struct device *dev)
  785. {
  786. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  787. if (!plat_priv) {
  788. cnss_pr_err("plat_priv is NULL\n");
  789. return 0;
  790. }
  791. return cnss_get_timeout(plat_priv, CNSS_TIMEOUT_QMI);
  792. }
  793. EXPORT_SYMBOL(cnss_get_boot_timeout);
  794. int cnss_power_up(struct device *dev)
  795. {
  796. int ret = 0;
  797. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  798. unsigned int timeout;
  799. if (!plat_priv) {
  800. cnss_pr_err("plat_priv is NULL\n");
  801. return -ENODEV;
  802. }
  803. cnss_pr_dbg("Powering up device\n");
  804. ret = cnss_driver_event_post(plat_priv,
  805. CNSS_DRIVER_EVENT_POWER_UP,
  806. CNSS_EVENT_SYNC, NULL);
  807. if (ret)
  808. goto out;
  809. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  810. goto out;
  811. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_POWER_UP);
  812. reinit_completion(&plat_priv->power_up_complete);
  813. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  814. msecs_to_jiffies(timeout));
  815. if (!ret) {
  816. cnss_pr_err("Timeout (%ums) waiting for power up to complete\n",
  817. timeout);
  818. ret = -EAGAIN;
  819. goto out;
  820. }
  821. return 0;
  822. out:
  823. return ret;
  824. }
  825. EXPORT_SYMBOL(cnss_power_up);
  826. int cnss_power_down(struct device *dev)
  827. {
  828. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  829. if (!plat_priv) {
  830. cnss_pr_err("plat_priv is NULL\n");
  831. return -ENODEV;
  832. }
  833. cnss_pr_dbg("Powering down device\n");
  834. return cnss_driver_event_post(plat_priv,
  835. CNSS_DRIVER_EVENT_POWER_DOWN,
  836. CNSS_EVENT_SYNC, NULL);
  837. }
  838. EXPORT_SYMBOL(cnss_power_down);
  839. int cnss_idle_restart(struct device *dev)
  840. {
  841. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  842. unsigned int timeout;
  843. int ret = 0;
  844. if (!plat_priv) {
  845. cnss_pr_err("plat_priv is NULL\n");
  846. return -ENODEV;
  847. }
  848. if (!mutex_trylock(&plat_priv->driver_ops_lock)) {
  849. cnss_pr_dbg("Another driver operation is in progress, ignore idle restart\n");
  850. return -EBUSY;
  851. }
  852. cnss_pr_dbg("Doing idle restart\n");
  853. reinit_completion(&plat_priv->power_up_complete);
  854. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  855. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  856. ret = -EINVAL;
  857. goto out;
  858. }
  859. ret = cnss_driver_event_post(plat_priv,
  860. CNSS_DRIVER_EVENT_IDLE_RESTART,
  861. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  862. if (ret)
  863. goto out;
  864. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  865. ret = cnss_bus_call_driver_probe(plat_priv);
  866. goto out;
  867. }
  868. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_IDLE_RESTART);
  869. ret = wait_for_completion_timeout(&plat_priv->power_up_complete,
  870. msecs_to_jiffies(timeout));
  871. if (plat_priv->power_up_error) {
  872. ret = plat_priv->power_up_error;
  873. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  874. cnss_pr_dbg("Power up error:%d, exiting\n",
  875. plat_priv->power_up_error);
  876. goto out;
  877. }
  878. if (!ret) {
  879. /* This exception occurs after attempting retry of FW recovery.
  880. * Thus we can safely power off the device.
  881. */
  882. cnss_fatal_err("Timeout (%ums) waiting for idle restart to complete\n",
  883. timeout);
  884. ret = -ETIMEDOUT;
  885. cnss_power_down(dev);
  886. CNSS_ASSERT(0);
  887. goto out;
  888. }
  889. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  890. cnss_pr_dbg("Reboot or shutdown is in progress, ignore idle restart\n");
  891. del_timer(&plat_priv->fw_boot_timer);
  892. ret = -EINVAL;
  893. goto out;
  894. }
  895. /* In non-DRV mode, remove MHI satellite configuration. Switching to
  896. * non-DRV is supported only once after device reboots and before wifi
  897. * is turned on. We do not allow switching back to DRV.
  898. * To bring device back into DRV, user needs to reboot device.
  899. */
  900. if (test_bit(DISABLE_DRV, &plat_priv->ctrl_params.quirks)) {
  901. cnss_pr_dbg("DRV is disabled\n");
  902. cnss_bus_disable_mhi_satellite_cfg(plat_priv);
  903. }
  904. mutex_unlock(&plat_priv->driver_ops_lock);
  905. return 0;
  906. out:
  907. mutex_unlock(&plat_priv->driver_ops_lock);
  908. return ret;
  909. }
  910. EXPORT_SYMBOL(cnss_idle_restart);
  911. int cnss_idle_shutdown(struct device *dev)
  912. {
  913. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  914. unsigned int timeout;
  915. int ret;
  916. if (!plat_priv) {
  917. cnss_pr_err("plat_priv is NULL\n");
  918. return -ENODEV;
  919. }
  920. if (test_bit(CNSS_IN_SUSPEND_RESUME, &plat_priv->driver_state)) {
  921. cnss_pr_dbg("System suspend or resume in progress, ignore idle shutdown\n");
  922. return -EAGAIN;
  923. }
  924. cnss_pr_dbg("Doing idle shutdown\n");
  925. if (!test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state) &&
  926. !test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  927. goto skip_wait;
  928. reinit_completion(&plat_priv->recovery_complete);
  929. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY);
  930. ret = wait_for_completion_timeout(&plat_priv->recovery_complete,
  931. msecs_to_jiffies(timeout));
  932. if (!ret) {
  933. cnss_pr_err("Timeout (%ums) waiting for recovery to complete\n",
  934. timeout);
  935. CNSS_ASSERT(0);
  936. }
  937. skip_wait:
  938. return cnss_driver_event_post(plat_priv,
  939. CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
  940. CNSS_EVENT_SYNC_UNINTERRUPTIBLE, NULL);
  941. }
  942. EXPORT_SYMBOL(cnss_idle_shutdown);
  943. static int cnss_get_resources(struct cnss_plat_data *plat_priv)
  944. {
  945. int ret = 0;
  946. ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
  947. if (ret) {
  948. cnss_pr_err("Failed to get vreg, err = %d\n", ret);
  949. goto out;
  950. }
  951. ret = cnss_get_clk(plat_priv);
  952. if (ret) {
  953. cnss_pr_err("Failed to get clocks, err = %d\n", ret);
  954. goto put_vreg;
  955. }
  956. ret = cnss_get_pinctrl(plat_priv);
  957. if (ret) {
  958. cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
  959. goto put_clk;
  960. }
  961. return 0;
  962. put_clk:
  963. cnss_put_clk(plat_priv);
  964. put_vreg:
  965. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  966. out:
  967. return ret;
  968. }
  969. static void cnss_put_resources(struct cnss_plat_data *plat_priv)
  970. {
  971. cnss_put_clk(plat_priv);
  972. cnss_put_vreg_type(plat_priv, CNSS_VREG_PRIM);
  973. }
  974. #if IS_ENABLED(CONFIG_ESOC) && IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  975. static int cnss_modem_notifier_nb(struct notifier_block *nb,
  976. unsigned long code,
  977. void *ss_handle)
  978. {
  979. struct cnss_plat_data *plat_priv =
  980. container_of(nb, struct cnss_plat_data, modem_nb);
  981. struct cnss_esoc_info *esoc_info;
  982. cnss_pr_dbg("Modem notifier: event %lu\n", code);
  983. if (!plat_priv)
  984. return NOTIFY_DONE;
  985. esoc_info = &plat_priv->esoc_info;
  986. if (code == SUBSYS_AFTER_POWERUP)
  987. esoc_info->modem_current_status = 1;
  988. else if (code == SUBSYS_BEFORE_SHUTDOWN)
  989. esoc_info->modem_current_status = 0;
  990. else
  991. return NOTIFY_DONE;
  992. if (!cnss_bus_call_driver_modem_status(plat_priv,
  993. esoc_info->modem_current_status))
  994. return NOTIFY_DONE;
  995. return NOTIFY_OK;
  996. }
  997. static int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  998. {
  999. int ret = 0;
  1000. struct device *dev;
  1001. struct cnss_esoc_info *esoc_info;
  1002. struct esoc_desc *esoc_desc;
  1003. const char *client_desc;
  1004. dev = &plat_priv->plat_dev->dev;
  1005. esoc_info = &plat_priv->esoc_info;
  1006. esoc_info->notify_modem_status =
  1007. of_property_read_bool(dev->of_node,
  1008. "qcom,notify-modem-status");
  1009. if (!esoc_info->notify_modem_status)
  1010. goto out;
  1011. ret = of_property_read_string_index(dev->of_node, "esoc-names", 0,
  1012. &client_desc);
  1013. if (ret) {
  1014. cnss_pr_dbg("esoc-names is not defined in DT, skip!\n");
  1015. } else {
  1016. esoc_desc = devm_register_esoc_client(dev, client_desc);
  1017. if (IS_ERR_OR_NULL(esoc_desc)) {
  1018. ret = PTR_RET(esoc_desc);
  1019. cnss_pr_err("Failed to register esoc_desc, err = %d\n",
  1020. ret);
  1021. goto out;
  1022. }
  1023. esoc_info->esoc_desc = esoc_desc;
  1024. }
  1025. plat_priv->modem_nb.notifier_call = cnss_modem_notifier_nb;
  1026. esoc_info->modem_current_status = 0;
  1027. esoc_info->modem_notify_handler =
  1028. subsys_notif_register_notifier(esoc_info->esoc_desc ?
  1029. esoc_info->esoc_desc->name :
  1030. "modem", &plat_priv->modem_nb);
  1031. if (IS_ERR(esoc_info->modem_notify_handler)) {
  1032. ret = PTR_ERR(esoc_info->modem_notify_handler);
  1033. cnss_pr_err("Failed to register esoc notifier, err = %d\n",
  1034. ret);
  1035. goto unreg_esoc;
  1036. }
  1037. return 0;
  1038. unreg_esoc:
  1039. if (esoc_info->esoc_desc)
  1040. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1041. out:
  1042. return ret;
  1043. }
  1044. static void cnss_unregister_esoc(struct cnss_plat_data *plat_priv)
  1045. {
  1046. struct device *dev;
  1047. struct cnss_esoc_info *esoc_info;
  1048. dev = &plat_priv->plat_dev->dev;
  1049. esoc_info = &plat_priv->esoc_info;
  1050. if (esoc_info->notify_modem_status)
  1051. subsys_notif_unregister_notifier
  1052. (esoc_info->modem_notify_handler,
  1053. &plat_priv->modem_nb);
  1054. if (esoc_info->esoc_desc)
  1055. devm_unregister_esoc_client(dev, esoc_info->esoc_desc);
  1056. }
  1057. #else
  1058. static inline int cnss_register_esoc(struct cnss_plat_data *plat_priv)
  1059. {
  1060. return 0;
  1061. }
  1062. static inline void cnss_unregister_esoc(struct cnss_plat_data *plat_priv) {}
  1063. #endif
  1064. int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1065. {
  1066. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1067. int ret = 0;
  1068. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1069. return 0;
  1070. enable_irq(sol_gpio->dev_sol_irq);
  1071. ret = enable_irq_wake(sol_gpio->dev_sol_irq);
  1072. if (ret)
  1073. cnss_pr_err("Failed to enable device SOL as wake IRQ, err = %d\n",
  1074. ret);
  1075. return ret;
  1076. }
  1077. int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv)
  1078. {
  1079. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1080. int ret = 0;
  1081. if (sol_gpio->dev_sol_gpio < 0 || sol_gpio->dev_sol_irq <= 0)
  1082. return 0;
  1083. ret = disable_irq_wake(sol_gpio->dev_sol_irq);
  1084. if (ret)
  1085. cnss_pr_err("Failed to disable device SOL as wake IRQ, err = %d\n",
  1086. ret);
  1087. disable_irq(sol_gpio->dev_sol_irq);
  1088. return ret;
  1089. }
  1090. int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv)
  1091. {
  1092. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1093. if (sol_gpio->dev_sol_gpio < 0)
  1094. return -EINVAL;
  1095. return gpio_get_value(sol_gpio->dev_sol_gpio);
  1096. }
  1097. static irqreturn_t cnss_dev_sol_handler(int irq, void *data)
  1098. {
  1099. struct cnss_plat_data *plat_priv = data;
  1100. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1101. sol_gpio->dev_sol_counter++;
  1102. cnss_pr_dbg("WLAN device SOL IRQ (%u) is asserted #%u\n",
  1103. irq, sol_gpio->dev_sol_counter);
  1104. /* Make sure abort current suspend */
  1105. cnss_pm_stay_awake(plat_priv);
  1106. cnss_pm_relax(plat_priv);
  1107. pm_system_wakeup();
  1108. cnss_bus_handle_dev_sol_irq(plat_priv);
  1109. return IRQ_HANDLED;
  1110. }
  1111. static int cnss_init_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1112. {
  1113. struct device *dev = &plat_priv->plat_dev->dev;
  1114. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1115. int ret = 0;
  1116. sol_gpio->dev_sol_gpio = of_get_named_gpio(dev->of_node,
  1117. "wlan-dev-sol-gpio", 0);
  1118. if (sol_gpio->dev_sol_gpio < 0)
  1119. goto out;
  1120. cnss_pr_dbg("Get device SOL GPIO (%d) from device node\n",
  1121. sol_gpio->dev_sol_gpio);
  1122. ret = gpio_request(sol_gpio->dev_sol_gpio, "wlan_dev_sol_gpio");
  1123. if (ret) {
  1124. cnss_pr_err("Failed to request device SOL GPIO, err = %d\n",
  1125. ret);
  1126. goto out;
  1127. }
  1128. gpio_direction_input(sol_gpio->dev_sol_gpio);
  1129. sol_gpio->dev_sol_irq = gpio_to_irq(sol_gpio->dev_sol_gpio);
  1130. ret = request_irq(sol_gpio->dev_sol_irq, cnss_dev_sol_handler,
  1131. IRQF_TRIGGER_FALLING, "wlan_dev_sol_irq", plat_priv);
  1132. if (ret) {
  1133. cnss_pr_err("Failed to request device SOL IRQ, err = %d\n", ret);
  1134. goto free_gpio;
  1135. }
  1136. return 0;
  1137. free_gpio:
  1138. gpio_free(sol_gpio->dev_sol_gpio);
  1139. out:
  1140. return ret;
  1141. }
  1142. static void cnss_deinit_dev_sol_gpio(struct cnss_plat_data *plat_priv)
  1143. {
  1144. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1145. if (sol_gpio->dev_sol_gpio < 0)
  1146. return;
  1147. free_irq(sol_gpio->dev_sol_irq, plat_priv);
  1148. gpio_free(sol_gpio->dev_sol_gpio);
  1149. }
  1150. int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value)
  1151. {
  1152. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1153. if (sol_gpio->host_sol_gpio < 0)
  1154. return -EINVAL;
  1155. if (value)
  1156. cnss_pr_dbg("Assert host SOL GPIO\n");
  1157. gpio_set_value(sol_gpio->host_sol_gpio, value);
  1158. return 0;
  1159. }
  1160. int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv)
  1161. {
  1162. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1163. if (sol_gpio->host_sol_gpio < 0)
  1164. return -EINVAL;
  1165. return gpio_get_value(sol_gpio->host_sol_gpio);
  1166. }
  1167. static int cnss_init_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1168. {
  1169. struct device *dev = &plat_priv->plat_dev->dev;
  1170. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1171. int ret = 0;
  1172. sol_gpio->host_sol_gpio = of_get_named_gpio(dev->of_node,
  1173. "wlan-host-sol-gpio", 0);
  1174. if (sol_gpio->host_sol_gpio < 0)
  1175. goto out;
  1176. cnss_pr_dbg("Get host SOL GPIO (%d) from device node\n",
  1177. sol_gpio->host_sol_gpio);
  1178. ret = gpio_request(sol_gpio->host_sol_gpio, "wlan_host_sol_gpio");
  1179. if (ret) {
  1180. cnss_pr_err("Failed to request host SOL GPIO, err = %d\n",
  1181. ret);
  1182. goto out;
  1183. }
  1184. gpio_direction_output(sol_gpio->host_sol_gpio, 0);
  1185. return 0;
  1186. out:
  1187. return ret;
  1188. }
  1189. static void cnss_deinit_host_sol_gpio(struct cnss_plat_data *plat_priv)
  1190. {
  1191. struct cnss_sol_gpio *sol_gpio = &plat_priv->sol_gpio;
  1192. if (sol_gpio->host_sol_gpio < 0)
  1193. return;
  1194. gpio_free(sol_gpio->host_sol_gpio);
  1195. }
  1196. static int cnss_init_sol_gpio(struct cnss_plat_data *plat_priv)
  1197. {
  1198. int ret;
  1199. ret = cnss_init_dev_sol_gpio(plat_priv);
  1200. if (ret)
  1201. goto out;
  1202. ret = cnss_init_host_sol_gpio(plat_priv);
  1203. if (ret)
  1204. goto deinit_dev_sol;
  1205. return 0;
  1206. deinit_dev_sol:
  1207. cnss_deinit_dev_sol_gpio(plat_priv);
  1208. out:
  1209. return ret;
  1210. }
  1211. static void cnss_deinit_sol_gpio(struct cnss_plat_data *plat_priv)
  1212. {
  1213. cnss_deinit_host_sol_gpio(plat_priv);
  1214. cnss_deinit_dev_sol_gpio(plat_priv);
  1215. }
  1216. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1217. static int cnss_subsys_powerup(const struct subsys_desc *subsys_desc)
  1218. {
  1219. struct cnss_plat_data *plat_priv;
  1220. int ret = 0;
  1221. if (!subsys_desc->dev) {
  1222. cnss_pr_err("dev from subsys_desc is NULL\n");
  1223. return -ENODEV;
  1224. }
  1225. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1226. if (!plat_priv) {
  1227. cnss_pr_err("plat_priv is NULL\n");
  1228. return -ENODEV;
  1229. }
  1230. if (!plat_priv->driver_state) {
  1231. cnss_pr_dbg("Powerup is ignored\n");
  1232. return 0;
  1233. }
  1234. ret = cnss_bus_dev_powerup(plat_priv);
  1235. if (ret)
  1236. __pm_relax(plat_priv->recovery_ws);
  1237. return ret;
  1238. }
  1239. static int cnss_subsys_shutdown(const struct subsys_desc *subsys_desc,
  1240. bool force_stop)
  1241. {
  1242. struct cnss_plat_data *plat_priv;
  1243. if (!subsys_desc->dev) {
  1244. cnss_pr_err("dev from subsys_desc is NULL\n");
  1245. return -ENODEV;
  1246. }
  1247. plat_priv = dev_get_drvdata(subsys_desc->dev);
  1248. if (!plat_priv) {
  1249. cnss_pr_err("plat_priv is NULL\n");
  1250. return -ENODEV;
  1251. }
  1252. if (!plat_priv->driver_state) {
  1253. cnss_pr_dbg("shutdown is ignored\n");
  1254. return 0;
  1255. }
  1256. return cnss_bus_dev_shutdown(plat_priv);
  1257. }
  1258. void cnss_device_crashed(struct device *dev)
  1259. {
  1260. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1261. struct cnss_subsys_info *subsys_info;
  1262. if (!plat_priv)
  1263. return;
  1264. subsys_info = &plat_priv->subsys_info;
  1265. if (subsys_info->subsys_device) {
  1266. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1267. subsys_set_crash_status(subsys_info->subsys_device, true);
  1268. subsystem_restart_dev(subsys_info->subsys_device);
  1269. }
  1270. }
  1271. EXPORT_SYMBOL(cnss_device_crashed);
  1272. static void cnss_subsys_crash_shutdown(const struct subsys_desc *subsys_desc)
  1273. {
  1274. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1275. if (!plat_priv) {
  1276. cnss_pr_err("plat_priv is NULL\n");
  1277. return;
  1278. }
  1279. cnss_bus_dev_crash_shutdown(plat_priv);
  1280. }
  1281. static int cnss_subsys_ramdump(int enable,
  1282. const struct subsys_desc *subsys_desc)
  1283. {
  1284. struct cnss_plat_data *plat_priv = dev_get_drvdata(subsys_desc->dev);
  1285. if (!plat_priv) {
  1286. cnss_pr_err("plat_priv is NULL\n");
  1287. return -ENODEV;
  1288. }
  1289. if (!enable)
  1290. return 0;
  1291. return cnss_bus_dev_ramdump(plat_priv);
  1292. }
  1293. static void cnss_recovery_work_handler(struct work_struct *work)
  1294. {
  1295. }
  1296. #else
  1297. static void cnss_recovery_work_handler(struct work_struct *work)
  1298. {
  1299. int ret;
  1300. struct cnss_plat_data *plat_priv =
  1301. container_of(work, struct cnss_plat_data, recovery_work);
  1302. if (!plat_priv->recovery_enabled)
  1303. panic("subsys-restart: Resetting the SoC wlan crashed\n");
  1304. cnss_bus_dev_shutdown(plat_priv);
  1305. cnss_bus_dev_ramdump(plat_priv);
  1306. msleep(POWER_RESET_MIN_DELAY_MS);
  1307. ret = cnss_bus_dev_powerup(plat_priv);
  1308. if (ret)
  1309. __pm_relax(plat_priv->recovery_ws);
  1310. return;
  1311. }
  1312. void cnss_device_crashed(struct device *dev)
  1313. {
  1314. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1315. if (!plat_priv)
  1316. return;
  1317. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1318. schedule_work(&plat_priv->recovery_work);
  1319. }
  1320. EXPORT_SYMBOL(cnss_device_crashed);
  1321. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  1322. void *cnss_get_virt_ramdump_mem(struct device *dev, unsigned long *size)
  1323. {
  1324. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1325. struct cnss_ramdump_info *ramdump_info;
  1326. if (!plat_priv)
  1327. return NULL;
  1328. ramdump_info = &plat_priv->ramdump_info;
  1329. *size = ramdump_info->ramdump_size;
  1330. return ramdump_info->ramdump_va;
  1331. }
  1332. EXPORT_SYMBOL(cnss_get_virt_ramdump_mem);
  1333. static const char *cnss_recovery_reason_to_str(enum cnss_recovery_reason reason)
  1334. {
  1335. switch (reason) {
  1336. case CNSS_REASON_DEFAULT:
  1337. return "DEFAULT";
  1338. case CNSS_REASON_LINK_DOWN:
  1339. return "LINK_DOWN";
  1340. case CNSS_REASON_RDDM:
  1341. return "RDDM";
  1342. case CNSS_REASON_TIMEOUT:
  1343. return "TIMEOUT";
  1344. }
  1345. return "UNKNOWN";
  1346. };
  1347. static int cnss_do_recovery(struct cnss_plat_data *plat_priv,
  1348. enum cnss_recovery_reason reason)
  1349. {
  1350. plat_priv->recovery_count++;
  1351. if (plat_priv->device_id == QCA6174_DEVICE_ID)
  1352. goto self_recovery;
  1353. if (test_bit(SKIP_RECOVERY, &plat_priv->ctrl_params.quirks)) {
  1354. cnss_pr_dbg("Skip device recovery\n");
  1355. return 0;
  1356. }
  1357. /* FW recovery sequence has multiple steps and firmware load requires
  1358. * linux PM in awake state. Thus hold the cnss wake source until
  1359. * WLAN MISSION enabled. CNSS_TIMEOUT_RECOVERY option should cover all
  1360. * time taken in this process.
  1361. */
  1362. pm_wakeup_ws_event(plat_priv->recovery_ws,
  1363. cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RECOVERY),
  1364. true);
  1365. switch (reason) {
  1366. case CNSS_REASON_LINK_DOWN:
  1367. if (!cnss_bus_check_link_status(plat_priv)) {
  1368. cnss_pr_dbg("Skip link down recovery as link is already up\n");
  1369. return 0;
  1370. }
  1371. if (test_bit(LINK_DOWN_SELF_RECOVERY,
  1372. &plat_priv->ctrl_params.quirks))
  1373. goto self_recovery;
  1374. if (!cnss_bus_recover_link_down(plat_priv)) {
  1375. /* clear recovery bit here to avoid skipping
  1376. * the recovery work for RDDM later
  1377. */
  1378. clear_bit(CNSS_DRIVER_RECOVERY,
  1379. &plat_priv->driver_state);
  1380. return 0;
  1381. }
  1382. break;
  1383. case CNSS_REASON_RDDM:
  1384. cnss_bus_collect_dump_info(plat_priv, false);
  1385. break;
  1386. case CNSS_REASON_DEFAULT:
  1387. case CNSS_REASON_TIMEOUT:
  1388. break;
  1389. default:
  1390. cnss_pr_err("Unsupported recovery reason: %s(%d)\n",
  1391. cnss_recovery_reason_to_str(reason), reason);
  1392. break;
  1393. }
  1394. cnss_bus_device_crashed(plat_priv);
  1395. return 0;
  1396. self_recovery:
  1397. cnss_pr_dbg("Going for self recovery\n");
  1398. cnss_bus_dev_shutdown(plat_priv);
  1399. if (test_bit(LINK_DOWN_SELF_RECOVERY, &plat_priv->ctrl_params.quirks))
  1400. clear_bit(LINK_DOWN_SELF_RECOVERY,
  1401. &plat_priv->ctrl_params.quirks);
  1402. cnss_bus_dev_powerup(plat_priv);
  1403. return 0;
  1404. }
  1405. static int cnss_driver_recovery_hdlr(struct cnss_plat_data *plat_priv,
  1406. void *data)
  1407. {
  1408. struct cnss_recovery_data *recovery_data = data;
  1409. int ret = 0;
  1410. cnss_pr_dbg("Driver recovery is triggered with reason: %s(%d)\n",
  1411. cnss_recovery_reason_to_str(recovery_data->reason),
  1412. recovery_data->reason);
  1413. if (!plat_priv->driver_state) {
  1414. cnss_pr_err("Improper driver state, ignore recovery\n");
  1415. ret = -EINVAL;
  1416. goto out;
  1417. }
  1418. if (test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {
  1419. cnss_pr_err("Reboot is in progress, ignore recovery\n");
  1420. ret = -EINVAL;
  1421. goto out;
  1422. }
  1423. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1424. cnss_pr_err("Recovery is already in progress\n");
  1425. CNSS_ASSERT(0);
  1426. ret = -EINVAL;
  1427. goto out;
  1428. }
  1429. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1430. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1431. cnss_pr_err("Driver unload or idle shutdown is in progress, ignore recovery\n");
  1432. ret = -EINVAL;
  1433. goto out;
  1434. }
  1435. switch (plat_priv->device_id) {
  1436. case QCA6174_DEVICE_ID:
  1437. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1438. test_bit(CNSS_DRIVER_IDLE_RESTART,
  1439. &plat_priv->driver_state)) {
  1440. cnss_pr_err("Driver load or idle restart is in progress, ignore recovery\n");
  1441. ret = -EINVAL;
  1442. goto out;
  1443. }
  1444. break;
  1445. default:
  1446. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1447. set_bit(CNSS_FW_BOOT_RECOVERY,
  1448. &plat_priv->driver_state);
  1449. }
  1450. break;
  1451. }
  1452. set_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state);
  1453. ret = cnss_do_recovery(plat_priv, recovery_data->reason);
  1454. out:
  1455. kfree(data);
  1456. return ret;
  1457. }
  1458. int cnss_self_recovery(struct device *dev,
  1459. enum cnss_recovery_reason reason)
  1460. {
  1461. cnss_schedule_recovery(dev, reason);
  1462. return 0;
  1463. }
  1464. EXPORT_SYMBOL(cnss_self_recovery);
  1465. void cnss_schedule_recovery(struct device *dev,
  1466. enum cnss_recovery_reason reason)
  1467. {
  1468. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1469. struct cnss_recovery_data *data;
  1470. int gfp = GFP_KERNEL;
  1471. if (!test_bit(CNSS_DEV_ERR_NOTIFY, &plat_priv->driver_state))
  1472. cnss_bus_update_status(plat_priv, CNSS_FW_DOWN);
  1473. if (test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1474. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1475. cnss_pr_dbg("Driver unload or idle shutdown is in progress, ignore schedule recovery\n");
  1476. return;
  1477. }
  1478. if (in_interrupt() || irqs_disabled())
  1479. gfp = GFP_ATOMIC;
  1480. data = kzalloc(sizeof(*data), gfp);
  1481. if (!data)
  1482. return;
  1483. data->reason = reason;
  1484. cnss_driver_event_post(plat_priv,
  1485. CNSS_DRIVER_EVENT_RECOVERY,
  1486. 0, data);
  1487. }
  1488. EXPORT_SYMBOL(cnss_schedule_recovery);
  1489. int cnss_force_fw_assert(struct device *dev)
  1490. {
  1491. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1492. if (!plat_priv) {
  1493. cnss_pr_err("plat_priv is NULL\n");
  1494. return -ENODEV;
  1495. }
  1496. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1497. cnss_pr_info("Forced FW assert is not supported\n");
  1498. return -EOPNOTSUPP;
  1499. }
  1500. if (cnss_bus_is_device_down(plat_priv)) {
  1501. cnss_pr_info("Device is already in bad state, ignore force assert\n");
  1502. return 0;
  1503. }
  1504. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1505. cnss_pr_info("Recovery is already in progress, ignore forced FW assert\n");
  1506. return 0;
  1507. }
  1508. if (in_interrupt() || irqs_disabled())
  1509. cnss_driver_event_post(plat_priv,
  1510. CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
  1511. 0, NULL);
  1512. else
  1513. cnss_bus_force_fw_assert_hdlr(plat_priv);
  1514. return 0;
  1515. }
  1516. EXPORT_SYMBOL(cnss_force_fw_assert);
  1517. int cnss_force_collect_rddm(struct device *dev)
  1518. {
  1519. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1520. unsigned int timeout;
  1521. int ret = 0;
  1522. if (!plat_priv) {
  1523. cnss_pr_err("plat_priv is NULL\n");
  1524. return -ENODEV;
  1525. }
  1526. if (plat_priv->device_id == QCA6174_DEVICE_ID) {
  1527. cnss_pr_info("Force collect rddm is not supported\n");
  1528. return -EOPNOTSUPP;
  1529. }
  1530. if (cnss_bus_is_device_down(plat_priv)) {
  1531. cnss_pr_info("Device is already in bad state, wait to collect rddm\n");
  1532. goto wait_rddm;
  1533. }
  1534. if (test_bit(CNSS_DRIVER_RECOVERY, &plat_priv->driver_state)) {
  1535. cnss_pr_info("Recovery is already in progress, wait to collect rddm\n");
  1536. goto wait_rddm;
  1537. }
  1538. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1539. test_bit(CNSS_DRIVER_UNLOADING, &plat_priv->driver_state) ||
  1540. test_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state) ||
  1541. test_bit(CNSS_DRIVER_IDLE_SHUTDOWN, &plat_priv->driver_state)) {
  1542. cnss_pr_info("Loading/Unloading/idle restart/shutdown is in progress, ignore forced collect rddm\n");
  1543. return 0;
  1544. }
  1545. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1546. if (ret)
  1547. return ret;
  1548. wait_rddm:
  1549. reinit_completion(&plat_priv->rddm_complete);
  1550. timeout = cnss_get_timeout(plat_priv, CNSS_TIMEOUT_RDDM);
  1551. ret = wait_for_completion_timeout(&plat_priv->rddm_complete,
  1552. msecs_to_jiffies(timeout));
  1553. if (!ret) {
  1554. cnss_pr_err("Timeout (%ums) waiting for RDDM to complete\n",
  1555. timeout);
  1556. ret = -ETIMEDOUT;
  1557. } else if (ret > 0) {
  1558. ret = 0;
  1559. }
  1560. return ret;
  1561. }
  1562. EXPORT_SYMBOL(cnss_force_collect_rddm);
  1563. int cnss_qmi_send_get(struct device *dev)
  1564. {
  1565. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1566. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1567. return 0;
  1568. return cnss_bus_qmi_send_get(plat_priv);
  1569. }
  1570. EXPORT_SYMBOL(cnss_qmi_send_get);
  1571. int cnss_qmi_send_put(struct device *dev)
  1572. {
  1573. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1574. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1575. return 0;
  1576. return cnss_bus_qmi_send_put(plat_priv);
  1577. }
  1578. EXPORT_SYMBOL(cnss_qmi_send_put);
  1579. int cnss_qmi_send(struct device *dev, int type, void *cmd,
  1580. int cmd_len, void *cb_ctx,
  1581. int (*cb)(void *ctx, void *event, int event_len))
  1582. {
  1583. struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
  1584. int ret;
  1585. if (!plat_priv)
  1586. return -ENODEV;
  1587. if (!test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state))
  1588. return -EINVAL;
  1589. plat_priv->get_info_cb = cb;
  1590. plat_priv->get_info_cb_ctx = cb_ctx;
  1591. ret = cnss_wlfw_get_info_send_sync(plat_priv, type, cmd, cmd_len);
  1592. if (ret) {
  1593. plat_priv->get_info_cb = NULL;
  1594. plat_priv->get_info_cb_ctx = NULL;
  1595. }
  1596. return ret;
  1597. }
  1598. EXPORT_SYMBOL(cnss_qmi_send);
  1599. static int cnss_cold_boot_cal_start_hdlr(struct cnss_plat_data *plat_priv)
  1600. {
  1601. int ret = 0;
  1602. u32 retry = 0, timeout;
  1603. if (test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state)) {
  1604. cnss_pr_dbg("Calibration complete. Ignore calibration req\n");
  1605. goto out;
  1606. } else if (test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state)) {
  1607. cnss_pr_dbg("Calibration in progress. Ignore new calibration req\n");
  1608. goto out;
  1609. } else if (test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  1610. cnss_pr_dbg("Calibration deferred as WLAN device disabled\n");
  1611. goto out;
  1612. }
  1613. if (test_bit(CNSS_DRIVER_LOADING, &plat_priv->driver_state) ||
  1614. test_bit(CNSS_DRIVER_PROBED, &plat_priv->driver_state) ||
  1615. test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  1616. cnss_pr_err("WLAN in mission mode before cold boot calibration\n");
  1617. CNSS_ASSERT(0);
  1618. return -EINVAL;
  1619. }
  1620. while (retry++ < CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1621. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  1622. break;
  1623. msleep(CNSS_CAL_START_PROBE_WAIT_MS);
  1624. if (retry == CNSS_CAL_START_PROBE_WAIT_RETRY_MAX) {
  1625. cnss_pr_err("Calibration start failed as PCI probe not complete\n");
  1626. CNSS_ASSERT(0);
  1627. ret = -EINVAL;
  1628. goto mark_cal_fail;
  1629. }
  1630. }
  1631. set_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1632. if (test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state)) {
  1633. timeout = cnss_get_timeout(plat_priv,
  1634. CNSS_TIMEOUT_CALIBRATION);
  1635. cnss_pr_dbg("Restarting calibration %ds timeout\n",
  1636. timeout / 1000);
  1637. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1638. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1639. msecs_to_jiffies(timeout));
  1640. }
  1641. reinit_completion(&plat_priv->cal_complete);
  1642. ret = cnss_bus_dev_powerup(plat_priv);
  1643. mark_cal_fail:
  1644. if (ret) {
  1645. complete(&plat_priv->cal_complete);
  1646. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1647. /* Set CBC done in driver state to mark attempt and note error
  1648. * since calibration cannot be retried at boot.
  1649. */
  1650. plat_priv->cal_done = CNSS_CAL_FAILURE;
  1651. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1652. }
  1653. out:
  1654. return ret;
  1655. }
  1656. static int cnss_cold_boot_cal_done_hdlr(struct cnss_plat_data *plat_priv,
  1657. void *data)
  1658. {
  1659. struct cnss_cal_info *cal_info = data;
  1660. if (!test_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state) ||
  1661. test_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state))
  1662. goto out;
  1663. switch (cal_info->cal_status) {
  1664. case CNSS_CAL_DONE:
  1665. cnss_pr_dbg("Calibration completed successfully\n");
  1666. plat_priv->cal_done = true;
  1667. break;
  1668. case CNSS_CAL_TIMEOUT:
  1669. case CNSS_CAL_FAILURE:
  1670. cnss_pr_dbg("Calibration failed. Status: %d, force shutdown\n",
  1671. cal_info->cal_status);
  1672. break;
  1673. default:
  1674. cnss_pr_err("Unknown calibration status: %u\n",
  1675. cal_info->cal_status);
  1676. break;
  1677. }
  1678. cnss_wlfw_wlan_mode_send_sync(plat_priv, CNSS_OFF);
  1679. cnss_bus_free_qdss_mem(plat_priv);
  1680. cnss_release_antenna_sharing(plat_priv);
  1681. cnss_bus_dev_shutdown(plat_priv);
  1682. msleep(POWER_RESET_MIN_DELAY_MS);
  1683. complete(&plat_priv->cal_complete);
  1684. clear_bit(CNSS_IN_COLD_BOOT_CAL, &plat_priv->driver_state);
  1685. set_bit(CNSS_COLD_BOOT_CAL_DONE, &plat_priv->driver_state);
  1686. if (cal_info->cal_status == CNSS_CAL_DONE) {
  1687. cnss_cal_mem_upload_to_file(plat_priv);
  1688. if (!test_bit(CNSS_DRIVER_REGISTER, &plat_priv->driver_state))
  1689. goto out;
  1690. cnss_pr_dbg("Schedule WLAN driver load\n");
  1691. if (cancel_delayed_work_sync(&plat_priv->wlan_reg_driver_work))
  1692. schedule_delayed_work(&plat_priv->wlan_reg_driver_work,
  1693. 0);
  1694. }
  1695. out:
  1696. kfree(data);
  1697. return 0;
  1698. }
  1699. static int cnss_power_up_hdlr(struct cnss_plat_data *plat_priv)
  1700. {
  1701. int ret;
  1702. ret = cnss_bus_dev_powerup(plat_priv);
  1703. if (ret)
  1704. clear_bit(CNSS_DRIVER_IDLE_RESTART, &plat_priv->driver_state);
  1705. return ret;
  1706. }
  1707. static int cnss_power_down_hdlr(struct cnss_plat_data *plat_priv)
  1708. {
  1709. cnss_bus_dev_shutdown(plat_priv);
  1710. return 0;
  1711. }
  1712. static int cnss_qdss_trace_req_mem_hdlr(struct cnss_plat_data *plat_priv)
  1713. {
  1714. int ret = 0;
  1715. ret = cnss_bus_alloc_qdss_mem(plat_priv);
  1716. if (ret < 0)
  1717. return ret;
  1718. return cnss_wlfw_qdss_trace_mem_info_send_sync(plat_priv);
  1719. }
  1720. static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
  1721. u32 mem_seg_len, u64 pa, u32 size)
  1722. {
  1723. int i = 0;
  1724. u64 offset = 0;
  1725. void *va = NULL;
  1726. u64 local_pa;
  1727. u32 local_size;
  1728. for (i = 0; i < mem_seg_len; i++) {
  1729. local_pa = (u64)fw_mem[i].pa;
  1730. local_size = (u32)fw_mem[i].size;
  1731. if (pa == local_pa && size <= local_size) {
  1732. va = fw_mem[i].va;
  1733. break;
  1734. }
  1735. if (pa > local_pa &&
  1736. pa < local_pa + local_size &&
  1737. pa + size <= local_pa + local_size) {
  1738. offset = pa - local_pa;
  1739. va = fw_mem[i].va + offset;
  1740. break;
  1741. }
  1742. }
  1743. return va;
  1744. }
  1745. static int cnss_fw_mem_file_save_hdlr(struct cnss_plat_data *plat_priv,
  1746. void *data)
  1747. {
  1748. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1749. struct cnss_fw_mem *fw_mem_seg;
  1750. int ret = 0L;
  1751. void *va = NULL;
  1752. u32 i, fw_mem_seg_len;
  1753. switch (event_data->mem_type) {
  1754. case QMI_WLFW_MEM_TYPE_DDR_V01:
  1755. if (!plat_priv->fw_mem_seg_len)
  1756. goto invalid_mem_save;
  1757. fw_mem_seg = plat_priv->fw_mem;
  1758. fw_mem_seg_len = plat_priv->fw_mem_seg_len;
  1759. break;
  1760. case QMI_WLFW_MEM_QDSS_V01:
  1761. if (!plat_priv->qdss_mem_seg_len)
  1762. goto invalid_mem_save;
  1763. fw_mem_seg = plat_priv->qdss_mem;
  1764. fw_mem_seg_len = plat_priv->qdss_mem_seg_len;
  1765. break;
  1766. default:
  1767. goto invalid_mem_save;
  1768. }
  1769. for (i = 0; i < event_data->mem_seg_len; i++) {
  1770. va = cnss_get_fw_mem_pa_to_va(fw_mem_seg, fw_mem_seg_len,
  1771. event_data->mem_seg[i].addr,
  1772. event_data->mem_seg[i].size);
  1773. if (!va) {
  1774. cnss_pr_err("Fail to find matching va of pa %pa for mem type: %d\n",
  1775. &event_data->mem_seg[i].addr,
  1776. event_data->mem_type);
  1777. ret = -EINVAL;
  1778. break;
  1779. }
  1780. ret = cnss_genl_send_msg(va, CNSS_GENL_MSG_TYPE_QDSS,
  1781. event_data->file_name,
  1782. event_data->mem_seg[i].size);
  1783. if (ret < 0) {
  1784. cnss_pr_err("Fail to save fw mem data: %d\n",
  1785. ret);
  1786. break;
  1787. }
  1788. }
  1789. kfree(data);
  1790. return ret;
  1791. invalid_mem_save:
  1792. cnss_pr_err("FW Mem type %d not allocated. Invalid save request\n",
  1793. event_data->mem_type);
  1794. kfree(data);
  1795. return -EINVAL;
  1796. }
  1797. static int cnss_qdss_trace_free_hdlr(struct cnss_plat_data *plat_priv)
  1798. {
  1799. cnss_bus_free_qdss_mem(plat_priv);
  1800. return 0;
  1801. }
  1802. static int cnss_qdss_trace_req_data_hdlr(struct cnss_plat_data *plat_priv,
  1803. void *data)
  1804. {
  1805. int ret = 0;
  1806. struct cnss_qmi_event_fw_mem_file_save_data *event_data = data;
  1807. if (!plat_priv)
  1808. return -ENODEV;
  1809. ret = cnss_wlfw_qdss_data_send_sync(plat_priv, event_data->file_name,
  1810. event_data->total_size);
  1811. kfree(data);
  1812. return ret;
  1813. }
  1814. static void cnss_driver_event_work(struct work_struct *work)
  1815. {
  1816. struct cnss_plat_data *plat_priv =
  1817. container_of(work, struct cnss_plat_data, event_work);
  1818. struct cnss_driver_event *event;
  1819. unsigned long flags;
  1820. int ret = 0;
  1821. if (!plat_priv) {
  1822. cnss_pr_err("plat_priv is NULL!\n");
  1823. return;
  1824. }
  1825. cnss_pm_stay_awake(plat_priv);
  1826. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1827. while (!list_empty(&plat_priv->event_list)) {
  1828. event = list_first_entry(&plat_priv->event_list,
  1829. struct cnss_driver_event, list);
  1830. list_del(&event->list);
  1831. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1832. cnss_pr_dbg("Processing driver event: %s%s(%d), state: 0x%lx\n",
  1833. cnss_driver_event_to_str(event->type),
  1834. event->sync ? "-sync" : "", event->type,
  1835. plat_priv->driver_state);
  1836. switch (event->type) {
  1837. case CNSS_DRIVER_EVENT_SERVER_ARRIVE:
  1838. ret = cnss_wlfw_server_arrive(plat_priv, event->data);
  1839. break;
  1840. case CNSS_DRIVER_EVENT_SERVER_EXIT:
  1841. ret = cnss_wlfw_server_exit(plat_priv);
  1842. break;
  1843. case CNSS_DRIVER_EVENT_REQUEST_MEM:
  1844. ret = cnss_bus_alloc_fw_mem(plat_priv);
  1845. if (ret)
  1846. break;
  1847. ret = cnss_wlfw_respond_mem_send_sync(plat_priv);
  1848. break;
  1849. case CNSS_DRIVER_EVENT_FW_MEM_READY:
  1850. ret = cnss_fw_mem_ready_hdlr(plat_priv);
  1851. break;
  1852. case CNSS_DRIVER_EVENT_FW_READY:
  1853. ret = cnss_fw_ready_hdlr(plat_priv);
  1854. break;
  1855. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START:
  1856. ret = cnss_cold_boot_cal_start_hdlr(plat_priv);
  1857. break;
  1858. case CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE:
  1859. ret = cnss_cold_boot_cal_done_hdlr(plat_priv,
  1860. event->data);
  1861. break;
  1862. case CNSS_DRIVER_EVENT_REGISTER_DRIVER:
  1863. ret = cnss_bus_register_driver_hdlr(plat_priv,
  1864. event->data);
  1865. break;
  1866. case CNSS_DRIVER_EVENT_UNREGISTER_DRIVER:
  1867. ret = cnss_bus_unregister_driver_hdlr(plat_priv);
  1868. break;
  1869. case CNSS_DRIVER_EVENT_RECOVERY:
  1870. ret = cnss_driver_recovery_hdlr(plat_priv,
  1871. event->data);
  1872. break;
  1873. case CNSS_DRIVER_EVENT_FORCE_FW_ASSERT:
  1874. ret = cnss_bus_force_fw_assert_hdlr(plat_priv);
  1875. break;
  1876. case CNSS_DRIVER_EVENT_IDLE_RESTART:
  1877. set_bit(CNSS_DRIVER_IDLE_RESTART,
  1878. &plat_priv->driver_state);
  1879. /* fall through */
  1880. case CNSS_DRIVER_EVENT_POWER_UP:
  1881. ret = cnss_power_up_hdlr(plat_priv);
  1882. break;
  1883. case CNSS_DRIVER_EVENT_IDLE_SHUTDOWN:
  1884. set_bit(CNSS_DRIVER_IDLE_SHUTDOWN,
  1885. &plat_priv->driver_state);
  1886. /* fall through */
  1887. case CNSS_DRIVER_EVENT_POWER_DOWN:
  1888. ret = cnss_power_down_hdlr(plat_priv);
  1889. break;
  1890. case CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND:
  1891. ret = cnss_process_wfc_call_ind_event(plat_priv,
  1892. event->data);
  1893. break;
  1894. case CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND:
  1895. ret = cnss_process_twt_cfg_ind_event(plat_priv,
  1896. event->data);
  1897. break;
  1898. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM:
  1899. ret = cnss_qdss_trace_req_mem_hdlr(plat_priv);
  1900. break;
  1901. case CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE:
  1902. ret = cnss_fw_mem_file_save_hdlr(plat_priv,
  1903. event->data);
  1904. break;
  1905. case CNSS_DRIVER_EVENT_QDSS_TRACE_FREE:
  1906. ret = cnss_qdss_trace_free_hdlr(plat_priv);
  1907. break;
  1908. case CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA:
  1909. ret = cnss_qdss_trace_req_data_hdlr(plat_priv,
  1910. event->data);
  1911. break;
  1912. default:
  1913. cnss_pr_err("Invalid driver event type: %d",
  1914. event->type);
  1915. kfree(event);
  1916. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1917. continue;
  1918. }
  1919. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1920. if (event->sync) {
  1921. event->ret = ret;
  1922. complete(&event->complete);
  1923. continue;
  1924. }
  1925. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1926. kfree(event);
  1927. spin_lock_irqsave(&plat_priv->event_lock, flags);
  1928. }
  1929. spin_unlock_irqrestore(&plat_priv->event_lock, flags);
  1930. cnss_pm_relax(plat_priv);
  1931. }
  1932. #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
  1933. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  1934. {
  1935. int ret = 0;
  1936. struct cnss_subsys_info *subsys_info;
  1937. subsys_info = &plat_priv->subsys_info;
  1938. subsys_info->subsys_desc.name = "wlan";
  1939. subsys_info->subsys_desc.owner = THIS_MODULE;
  1940. subsys_info->subsys_desc.powerup = cnss_subsys_powerup;
  1941. subsys_info->subsys_desc.shutdown = cnss_subsys_shutdown;
  1942. subsys_info->subsys_desc.ramdump = cnss_subsys_ramdump;
  1943. subsys_info->subsys_desc.crash_shutdown = cnss_subsys_crash_shutdown;
  1944. subsys_info->subsys_desc.dev = &plat_priv->plat_dev->dev;
  1945. subsys_info->subsys_device = subsys_register(&subsys_info->subsys_desc);
  1946. if (IS_ERR(subsys_info->subsys_device)) {
  1947. ret = PTR_ERR(subsys_info->subsys_device);
  1948. cnss_pr_err("Failed to register subsys, err = %d\n", ret);
  1949. goto out;
  1950. }
  1951. subsys_info->subsys_handle =
  1952. subsystem_get(subsys_info->subsys_desc.name);
  1953. if (!subsys_info->subsys_handle) {
  1954. cnss_pr_err("Failed to get subsys_handle!\n");
  1955. ret = -EINVAL;
  1956. goto unregister_subsys;
  1957. } else if (IS_ERR(subsys_info->subsys_handle)) {
  1958. ret = PTR_ERR(subsys_info->subsys_handle);
  1959. cnss_pr_err("Failed to do subsystem_get, err = %d\n", ret);
  1960. goto unregister_subsys;
  1961. }
  1962. return 0;
  1963. unregister_subsys:
  1964. subsys_unregister(subsys_info->subsys_device);
  1965. out:
  1966. return ret;
  1967. }
  1968. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  1969. {
  1970. struct cnss_subsys_info *subsys_info;
  1971. subsys_info = &plat_priv->subsys_info;
  1972. subsystem_put(subsys_info->subsys_handle);
  1973. subsys_unregister(subsys_info->subsys_device);
  1974. }
  1975. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  1976. {
  1977. struct cnss_subsys_info *subsys_info = &plat_priv->subsys_info;
  1978. return create_ramdump_device(subsys_info->subsys_desc.name,
  1979. subsys_info->subsys_desc.dev);
  1980. }
  1981. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  1982. void *ramdump_dev)
  1983. {
  1984. destroy_ramdump_device(ramdump_dev);
  1985. }
  1986. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  1987. {
  1988. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  1989. struct ramdump_segment segment;
  1990. memset(&segment, 0, sizeof(segment));
  1991. segment.v_address = (void __iomem *)ramdump_info->ramdump_va;
  1992. segment.size = ramdump_info->ramdump_size;
  1993. return qcom_ramdump(ramdump_info->ramdump_dev, &segment, 1);
  1994. }
  1995. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  1996. {
  1997. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  1998. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  1999. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2000. struct ramdump_segment *ramdump_segs, *s;
  2001. struct cnss_dump_meta_info meta_info = {0};
  2002. int i, ret = 0;
  2003. ramdump_segs = kcalloc(dump_data->nentries + 1,
  2004. sizeof(*ramdump_segs),
  2005. GFP_KERNEL);
  2006. if (!ramdump_segs)
  2007. return -ENOMEM;
  2008. s = ramdump_segs + 1;
  2009. for (i = 0; i < dump_data->nentries; i++) {
  2010. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2011. cnss_pr_err("Unsupported dump type: %d",
  2012. dump_seg->type);
  2013. continue;
  2014. }
  2015. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2016. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2017. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2018. }
  2019. meta_info.entry[dump_seg->type].entry_num++;
  2020. s->address = dump_seg->address;
  2021. s->v_address = (void __iomem *)dump_seg->v_address;
  2022. s->size = dump_seg->size;
  2023. s++;
  2024. dump_seg++;
  2025. }
  2026. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2027. meta_info.version = CNSS_RAMDUMP_VERSION;
  2028. meta_info.chipset = plat_priv->device_id;
  2029. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2030. ramdump_segs->v_address = (void __iomem *)(&meta_info);
  2031. ramdump_segs->size = sizeof(meta_info);
  2032. ret = qcom_elf_ramdump(info_v2->ramdump_dev, ramdump_segs,
  2033. dump_data->nentries + 1);
  2034. kfree(ramdump_segs);
  2035. return ret;
  2036. }
  2037. #else
  2038. static int cnss_panic_handler(struct notifier_block *nb, unsigned long action,
  2039. void *data)
  2040. {
  2041. struct cnss_plat_data *plat_priv =
  2042. container_of(nb, struct cnss_plat_data, panic_nb);
  2043. cnss_bus_dev_crash_shutdown(plat_priv);
  2044. return NOTIFY_DONE;
  2045. }
  2046. int cnss_register_subsys(struct cnss_plat_data *plat_priv)
  2047. {
  2048. int ret;
  2049. if (!plat_priv)
  2050. return -ENODEV;
  2051. plat_priv->panic_nb.notifier_call = cnss_panic_handler;
  2052. ret = atomic_notifier_chain_register(&panic_notifier_list,
  2053. &plat_priv->panic_nb);
  2054. if (ret) {
  2055. cnss_pr_err("Failed to register panic handler\n");
  2056. return -EINVAL;
  2057. }
  2058. return 0;
  2059. }
  2060. void cnss_unregister_subsys(struct cnss_plat_data *plat_priv)
  2061. {
  2062. int ret;
  2063. ret = atomic_notifier_chain_unregister(&panic_notifier_list,
  2064. &plat_priv->panic_nb);
  2065. if (ret)
  2066. cnss_pr_err("Failed to unregister panic handler\n");
  2067. }
  2068. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2069. static void *cnss_create_ramdump_device(struct cnss_plat_data *plat_priv)
  2070. {
  2071. return &plat_priv->plat_dev->dev;
  2072. }
  2073. static void cnss_destroy_ramdump_device(struct cnss_plat_data *plat_priv,
  2074. void *ramdump_dev)
  2075. {
  2076. }
  2077. #endif
  2078. #if IS_ENABLED(CONFIG_QCOM_RAMDUMP)
  2079. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2080. {
  2081. struct cnss_ramdump_info *ramdump_info = &plat_priv->ramdump_info;
  2082. struct qcom_dump_segment segment;
  2083. struct list_head head;
  2084. INIT_LIST_HEAD(&head);
  2085. memset(&segment, 0, sizeof(segment));
  2086. segment.va = ramdump_info->ramdump_va;
  2087. segment.size = ramdump_info->ramdump_size;
  2088. list_add(&segment.node, &head);
  2089. return qcom_dump(&head, ramdump_info->ramdump_dev);
  2090. }
  2091. #else
  2092. int cnss_do_ramdump(struct cnss_plat_data *plat_priv)
  2093. {
  2094. return 0;
  2095. }
  2096. /* Using completion event inside dynamically allocated ramdump_desc
  2097. * may result a race between freeing the event after setting it to
  2098. * complete inside dev coredump free callback and the thread that is
  2099. * waiting for completion.
  2100. */
  2101. DECLARE_COMPLETION(dump_done);
  2102. #define TIMEOUT_SAVE_DUMP_MS 30000
  2103. #define SIZEOF_ELF_STRUCT(__xhdr) \
  2104. static inline size_t sizeof_elf_##__xhdr(unsigned char class) \
  2105. { \
  2106. if (class == ELFCLASS32) \
  2107. return sizeof(struct elf32_##__xhdr); \
  2108. else \
  2109. return sizeof(struct elf64_##__xhdr); \
  2110. }
  2111. SIZEOF_ELF_STRUCT(phdr)
  2112. SIZEOF_ELF_STRUCT(hdr)
  2113. #define set_xhdr_property(__xhdr, arg, class, member, value) \
  2114. do { \
  2115. if (class == ELFCLASS32) \
  2116. ((struct elf32_##__xhdr *)arg)->member = value; \
  2117. else \
  2118. ((struct elf64_##__xhdr *)arg)->member = value; \
  2119. } while (0)
  2120. #define set_ehdr_property(arg, class, member, value) \
  2121. set_xhdr_property(hdr, arg, class, member, value)
  2122. #define set_phdr_property(arg, class, member, value) \
  2123. set_xhdr_property(phdr, arg, class, member, value)
  2124. /* These replace qcom_ramdump driver APIs called from common API
  2125. * cnss_do_elf_dump() by the ones defined here.
  2126. */
  2127. #define qcom_dump_segment cnss_qcom_dump_segment
  2128. #define qcom_elf_dump cnss_qcom_elf_dump
  2129. #define dump_enabled cnss_dump_enabled
  2130. struct cnss_qcom_dump_segment {
  2131. struct list_head node;
  2132. dma_addr_t da;
  2133. void *va;
  2134. size_t size;
  2135. };
  2136. struct cnss_qcom_ramdump_desc {
  2137. void *data;
  2138. struct completion dump_done;
  2139. };
  2140. static ssize_t cnss_qcom_devcd_readv(char *buffer, loff_t offset, size_t count,
  2141. void *data, size_t datalen)
  2142. {
  2143. struct cnss_qcom_ramdump_desc *desc = data;
  2144. return memory_read_from_buffer(buffer, count, &offset, desc->data,
  2145. datalen);
  2146. }
  2147. static void cnss_qcom_devcd_freev(void *data)
  2148. {
  2149. struct cnss_qcom_ramdump_desc *desc = data;
  2150. cnss_pr_dbg("Free dump data for dev coredump\n");
  2151. complete(&dump_done);
  2152. vfree(desc->data);
  2153. kfree(desc);
  2154. }
  2155. static int cnss_qcom_devcd_dump(struct device *dev, void *data, size_t datalen,
  2156. gfp_t gfp)
  2157. {
  2158. struct cnss_qcom_ramdump_desc *desc;
  2159. unsigned int timeout = TIMEOUT_SAVE_DUMP_MS;
  2160. int ret;
  2161. desc = kmalloc(sizeof(*desc), GFP_KERNEL);
  2162. if (!desc)
  2163. return -ENOMEM;
  2164. desc->data = data;
  2165. reinit_completion(&dump_done);
  2166. dev_coredumpm(dev, NULL, desc, datalen, gfp,
  2167. cnss_qcom_devcd_readv, cnss_qcom_devcd_freev);
  2168. ret = wait_for_completion_timeout(&dump_done,
  2169. msecs_to_jiffies(timeout));
  2170. if (!ret)
  2171. cnss_pr_err("Timeout waiting (%dms) for saving dump to file system\n",
  2172. timeout);
  2173. return ret ? 0 : -ETIMEDOUT;
  2174. }
  2175. /* Since the elf32 and elf64 identification is identical apart from
  2176. * the class, use elf32 by default.
  2177. */
  2178. static void init_elf_identification(struct elf32_hdr *ehdr, unsigned char class)
  2179. {
  2180. memcpy(ehdr->e_ident, ELFMAG, SELFMAG);
  2181. ehdr->e_ident[EI_CLASS] = class;
  2182. ehdr->e_ident[EI_DATA] = ELFDATA2LSB;
  2183. ehdr->e_ident[EI_VERSION] = EV_CURRENT;
  2184. ehdr->e_ident[EI_OSABI] = ELFOSABI_NONE;
  2185. }
  2186. int cnss_qcom_elf_dump(struct list_head *segs, struct device *dev,
  2187. unsigned char class)
  2188. {
  2189. struct cnss_qcom_dump_segment *segment;
  2190. void *phdr, *ehdr;
  2191. size_t data_size, offset;
  2192. int phnum = 0;
  2193. void *data;
  2194. void __iomem *ptr;
  2195. if (!segs || list_empty(segs))
  2196. return -EINVAL;
  2197. data_size = sizeof_elf_hdr(class);
  2198. list_for_each_entry(segment, segs, node) {
  2199. data_size += sizeof_elf_phdr(class) + segment->size;
  2200. phnum++;
  2201. }
  2202. data = vmalloc(data_size);
  2203. if (!data)
  2204. return -ENOMEM;
  2205. cnss_pr_dbg("Creating ELF file with size %d\n", data_size);
  2206. ehdr = data;
  2207. memset(ehdr, 0, sizeof_elf_hdr(class));
  2208. init_elf_identification(ehdr, class);
  2209. set_ehdr_property(ehdr, class, e_type, ET_CORE);
  2210. set_ehdr_property(ehdr, class, e_machine, EM_NONE);
  2211. set_ehdr_property(ehdr, class, e_version, EV_CURRENT);
  2212. set_ehdr_property(ehdr, class, e_phoff, sizeof_elf_hdr(class));
  2213. set_ehdr_property(ehdr, class, e_ehsize, sizeof_elf_hdr(class));
  2214. set_ehdr_property(ehdr, class, e_phentsize, sizeof_elf_phdr(class));
  2215. set_ehdr_property(ehdr, class, e_phnum, phnum);
  2216. phdr = data + sizeof_elf_hdr(class);
  2217. offset = sizeof_elf_hdr(class) + sizeof_elf_phdr(class) * phnum;
  2218. list_for_each_entry(segment, segs, node) {
  2219. memset(phdr, 0, sizeof_elf_phdr(class));
  2220. set_phdr_property(phdr, class, p_type, PT_LOAD);
  2221. set_phdr_property(phdr, class, p_offset, offset);
  2222. set_phdr_property(phdr, class, p_vaddr, segment->da);
  2223. set_phdr_property(phdr, class, p_paddr, segment->da);
  2224. set_phdr_property(phdr, class, p_filesz, segment->size);
  2225. set_phdr_property(phdr, class, p_memsz, segment->size);
  2226. set_phdr_property(phdr, class, p_flags, PF_R | PF_W | PF_X);
  2227. set_phdr_property(phdr, class, p_align, 0);
  2228. if (segment->va) {
  2229. memcpy(data + offset, segment->va, segment->size);
  2230. } else {
  2231. ptr = devm_ioremap(dev, segment->da, segment->size);
  2232. if (!ptr) {
  2233. cnss_pr_err("Invalid coredump segment (%pad, %zu)\n",
  2234. &segment->da, segment->size);
  2235. memset(data + offset, 0xff, segment->size);
  2236. } else {
  2237. memcpy_fromio(data + offset, ptr,
  2238. segment->size);
  2239. }
  2240. }
  2241. offset += segment->size;
  2242. phdr += sizeof_elf_phdr(class);
  2243. }
  2244. return cnss_qcom_devcd_dump(dev, data, data_size, GFP_KERNEL);
  2245. }
  2246. /* Saving dump to file system is always needed in this case. */
  2247. static bool cnss_dump_enabled(void)
  2248. {
  2249. return true;
  2250. }
  2251. #endif /* CONFIG_QCOM_RAMDUMP */
  2252. int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv)
  2253. {
  2254. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2255. struct cnss_dump_data *dump_data = &info_v2->dump_data;
  2256. struct cnss_dump_seg *dump_seg = info_v2->dump_data_vaddr;
  2257. struct qcom_dump_segment *seg;
  2258. struct cnss_dump_meta_info meta_info = {0};
  2259. struct list_head head;
  2260. int i, ret = 0;
  2261. if (!dump_enabled()) {
  2262. cnss_pr_info("Dump collection is not enabled\n");
  2263. return ret;
  2264. }
  2265. INIT_LIST_HEAD(&head);
  2266. for (i = 0; i < dump_data->nentries; i++) {
  2267. if (dump_seg->type >= CNSS_FW_DUMP_TYPE_MAX) {
  2268. cnss_pr_err("Unsupported dump type: %d",
  2269. dump_seg->type);
  2270. continue;
  2271. }
  2272. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2273. if (!seg)
  2274. continue;
  2275. if (meta_info.entry[dump_seg->type].entry_start == 0) {
  2276. meta_info.entry[dump_seg->type].type = dump_seg->type;
  2277. meta_info.entry[dump_seg->type].entry_start = i + 1;
  2278. }
  2279. meta_info.entry[dump_seg->type].entry_num++;
  2280. seg->da = dump_seg->address;
  2281. seg->va = dump_seg->v_address;
  2282. seg->size = dump_seg->size;
  2283. list_add_tail(&seg->node, &head);
  2284. dump_seg++;
  2285. }
  2286. seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
  2287. if (!seg)
  2288. goto do_elf_dump;
  2289. meta_info.magic = CNSS_RAMDUMP_MAGIC;
  2290. meta_info.version = CNSS_RAMDUMP_VERSION;
  2291. meta_info.chipset = plat_priv->device_id;
  2292. meta_info.total_entries = CNSS_FW_DUMP_TYPE_MAX;
  2293. seg->va = &meta_info;
  2294. seg->size = sizeof(meta_info);
  2295. list_add(&seg->node, &head);
  2296. do_elf_dump:
  2297. ret = qcom_elf_dump(&head, info_v2->ramdump_dev, ELF_CLASS);
  2298. while (!list_empty(&head)) {
  2299. seg = list_first_entry(&head, struct qcom_dump_segment, node);
  2300. list_del(&seg->node);
  2301. kfree(seg);
  2302. }
  2303. return ret;
  2304. }
  2305. #endif /* CONFIG_MSM_SUBSYSTEM_RESTART */
  2306. #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
  2307. static int cnss_init_dump_entry(struct cnss_plat_data *plat_priv)
  2308. {
  2309. struct cnss_ramdump_info *ramdump_info;
  2310. struct msm_dump_entry dump_entry;
  2311. ramdump_info = &plat_priv->ramdump_info;
  2312. ramdump_info->dump_data.addr = ramdump_info->ramdump_pa;
  2313. ramdump_info->dump_data.len = ramdump_info->ramdump_size;
  2314. ramdump_info->dump_data.version = CNSS_DUMP_FORMAT_VER;
  2315. ramdump_info->dump_data.magic = CNSS_DUMP_MAGIC_VER_V2;
  2316. strlcpy(ramdump_info->dump_data.name, CNSS_DUMP_NAME,
  2317. sizeof(ramdump_info->dump_data.name));
  2318. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2319. dump_entry.addr = virt_to_phys(&ramdump_info->dump_data);
  2320. return msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2321. &dump_entry);
  2322. }
  2323. static int cnss_register_ramdump_v1(struct cnss_plat_data *plat_priv)
  2324. {
  2325. int ret = 0;
  2326. struct device *dev;
  2327. struct cnss_ramdump_info *ramdump_info;
  2328. u32 ramdump_size = 0;
  2329. dev = &plat_priv->plat_dev->dev;
  2330. ramdump_info = &plat_priv->ramdump_info;
  2331. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2332. &ramdump_size) == 0) {
  2333. ramdump_info->ramdump_va =
  2334. dma_alloc_coherent(dev, ramdump_size,
  2335. &ramdump_info->ramdump_pa,
  2336. GFP_KERNEL);
  2337. if (ramdump_info->ramdump_va)
  2338. ramdump_info->ramdump_size = ramdump_size;
  2339. }
  2340. cnss_pr_dbg("ramdump va: %pK, pa: %pa\n",
  2341. ramdump_info->ramdump_va, &ramdump_info->ramdump_pa);
  2342. if (ramdump_info->ramdump_size == 0) {
  2343. cnss_pr_info("Ramdump will not be collected");
  2344. goto out;
  2345. }
  2346. ret = cnss_init_dump_entry(plat_priv);
  2347. if (ret) {
  2348. cnss_pr_err("Failed to setup dump table, err = %d\n", ret);
  2349. goto free_ramdump;
  2350. }
  2351. ramdump_info->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2352. if (!ramdump_info->ramdump_dev) {
  2353. cnss_pr_err("Failed to create ramdump device!");
  2354. ret = -ENOMEM;
  2355. goto free_ramdump;
  2356. }
  2357. return 0;
  2358. free_ramdump:
  2359. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2360. ramdump_info->ramdump_va, ramdump_info->ramdump_pa);
  2361. out:
  2362. return ret;
  2363. }
  2364. static void cnss_unregister_ramdump_v1(struct cnss_plat_data *plat_priv)
  2365. {
  2366. struct device *dev;
  2367. struct cnss_ramdump_info *ramdump_info;
  2368. dev = &plat_priv->plat_dev->dev;
  2369. ramdump_info = &plat_priv->ramdump_info;
  2370. if (ramdump_info->ramdump_dev)
  2371. cnss_destroy_ramdump_device(plat_priv,
  2372. ramdump_info->ramdump_dev);
  2373. if (ramdump_info->ramdump_va)
  2374. dma_free_coherent(dev, ramdump_info->ramdump_size,
  2375. ramdump_info->ramdump_va,
  2376. ramdump_info->ramdump_pa);
  2377. }
  2378. /**
  2379. * cnss_ignore_dump_data_reg_fail - Ignore Ramdump table register failure
  2380. * @ret: Error returned by msm_dump_data_register_nominidump
  2381. *
  2382. * For Lahaina GKI boot, we dont have support for mem dump feature. So
  2383. * ignore failure.
  2384. *
  2385. * Return: Same given error code if mem dump feature enabled, 0 otherwise
  2386. */
  2387. static int cnss_ignore_dump_data_reg_fail(int ret)
  2388. {
  2389. return ret;
  2390. }
  2391. static int cnss_register_ramdump_v2(struct cnss_plat_data *plat_priv)
  2392. {
  2393. int ret = 0;
  2394. struct cnss_ramdump_info_v2 *info_v2;
  2395. struct cnss_dump_data *dump_data;
  2396. struct msm_dump_entry dump_entry;
  2397. struct device *dev = &plat_priv->plat_dev->dev;
  2398. u32 ramdump_size = 0;
  2399. info_v2 = &plat_priv->ramdump_info_v2;
  2400. dump_data = &info_v2->dump_data;
  2401. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2402. &ramdump_size) == 0)
  2403. info_v2->ramdump_size = ramdump_size;
  2404. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2405. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2406. if (!info_v2->dump_data_vaddr)
  2407. return -ENOMEM;
  2408. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2409. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2410. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2411. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2412. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2413. sizeof(dump_data->name));
  2414. dump_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2415. dump_entry.addr = virt_to_phys(dump_data);
  2416. ret = msm_dump_data_register_nominidump(MSM_DUMP_TABLE_APPS,
  2417. &dump_entry);
  2418. if (ret) {
  2419. ret = cnss_ignore_dump_data_reg_fail(ret);
  2420. cnss_pr_err("Failed to setup dump table, %s (%d)\n",
  2421. ret ? "Error" : "Ignoring", ret);
  2422. goto free_ramdump;
  2423. }
  2424. info_v2->ramdump_dev = cnss_create_ramdump_device(plat_priv);
  2425. if (!info_v2->ramdump_dev) {
  2426. cnss_pr_err("Failed to create ramdump device!\n");
  2427. ret = -ENOMEM;
  2428. goto free_ramdump;
  2429. }
  2430. return 0;
  2431. free_ramdump:
  2432. kfree(info_v2->dump_data_vaddr);
  2433. info_v2->dump_data_vaddr = NULL;
  2434. return ret;
  2435. }
  2436. static void cnss_unregister_ramdump_v2(struct cnss_plat_data *plat_priv)
  2437. {
  2438. struct cnss_ramdump_info_v2 *info_v2;
  2439. info_v2 = &plat_priv->ramdump_info_v2;
  2440. if (info_v2->ramdump_dev)
  2441. cnss_destroy_ramdump_device(plat_priv, info_v2->ramdump_dev);
  2442. kfree(info_v2->dump_data_vaddr);
  2443. info_v2->dump_data_vaddr = NULL;
  2444. info_v2->dump_data_valid = false;
  2445. }
  2446. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2447. {
  2448. int ret = 0;
  2449. switch (plat_priv->device_id) {
  2450. case QCA6174_DEVICE_ID:
  2451. ret = cnss_register_ramdump_v1(plat_priv);
  2452. break;
  2453. case QCA6290_DEVICE_ID:
  2454. case QCA6390_DEVICE_ID:
  2455. case QCA6490_DEVICE_ID:
  2456. case KIWI_DEVICE_ID:
  2457. case MANGO_DEVICE_ID:
  2458. ret = cnss_register_ramdump_v2(plat_priv);
  2459. break;
  2460. default:
  2461. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2462. ret = -ENODEV;
  2463. break;
  2464. }
  2465. return ret;
  2466. }
  2467. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2468. {
  2469. switch (plat_priv->device_id) {
  2470. case QCA6174_DEVICE_ID:
  2471. cnss_unregister_ramdump_v1(plat_priv);
  2472. break;
  2473. case QCA6290_DEVICE_ID:
  2474. case QCA6390_DEVICE_ID:
  2475. case QCA6490_DEVICE_ID:
  2476. case KIWI_DEVICE_ID:
  2477. case MANGO_DEVICE_ID:
  2478. cnss_unregister_ramdump_v2(plat_priv);
  2479. break;
  2480. default:
  2481. cnss_pr_err("Unknown device ID: 0x%lx\n", plat_priv->device_id);
  2482. break;
  2483. }
  2484. }
  2485. #else
  2486. int cnss_register_ramdump(struct cnss_plat_data *plat_priv)
  2487. {
  2488. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2489. struct cnss_dump_data *dump_data = dump_data = &info_v2->dump_data;
  2490. struct device *dev = &plat_priv->plat_dev->dev;
  2491. u32 ramdump_size = 0;
  2492. if (of_property_read_u32(dev->of_node, "qcom,wlan-ramdump-dynamic",
  2493. &ramdump_size) == 0)
  2494. info_v2->ramdump_size = ramdump_size;
  2495. cnss_pr_dbg("Ramdump size 0x%lx\n", info_v2->ramdump_size);
  2496. info_v2->dump_data_vaddr = kzalloc(CNSS_DUMP_DESC_SIZE, GFP_KERNEL);
  2497. if (!info_v2->dump_data_vaddr)
  2498. return -ENOMEM;
  2499. dump_data->paddr = virt_to_phys(info_v2->dump_data_vaddr);
  2500. dump_data->version = CNSS_DUMP_FORMAT_VER_V2;
  2501. dump_data->magic = CNSS_DUMP_MAGIC_VER_V2;
  2502. dump_data->seg_version = CNSS_DUMP_SEG_VER;
  2503. strlcpy(dump_data->name, CNSS_DUMP_NAME,
  2504. sizeof(dump_data->name));
  2505. info_v2->ramdump_dev = dev;
  2506. return 0;
  2507. }
  2508. void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv)
  2509. {
  2510. struct cnss_ramdump_info_v2 *info_v2 = &plat_priv->ramdump_info_v2;
  2511. info_v2->ramdump_dev = NULL;
  2512. kfree(info_v2->dump_data_vaddr);
  2513. info_v2->dump_data_vaddr = NULL;
  2514. info_v2->dump_data_valid = false;
  2515. }
  2516. #endif /* CONFIG_QCOM_MEMORY_DUMP_V2 */
  2517. #if IS_ENABLED(CONFIG_QCOM_MINIDUMP)
  2518. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2519. phys_addr_t *pa, unsigned long attrs)
  2520. {
  2521. struct sg_table sgt;
  2522. int ret;
  2523. ret = dma_get_sgtable_attrs(dev, &sgt, va, dma, size, attrs);
  2524. if (ret) {
  2525. cnss_pr_err("Failed to get sgtable for va: 0x%pK, dma: %pa, size: 0x%zx, attrs: 0x%x\n",
  2526. va, &dma, size, attrs);
  2527. return -EINVAL;
  2528. }
  2529. *pa = page_to_phys(sg_page(sgt.sgl));
  2530. sg_free_table(&sgt);
  2531. return 0;
  2532. }
  2533. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2534. enum cnss_fw_dump_type type, int seg_no,
  2535. void *va, phys_addr_t pa, size_t size)
  2536. {
  2537. struct md_region md_entry;
  2538. int ret;
  2539. switch (type) {
  2540. case CNSS_FW_IMAGE:
  2541. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2542. seg_no);
  2543. break;
  2544. case CNSS_FW_RDDM:
  2545. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2546. seg_no);
  2547. break;
  2548. case CNSS_FW_REMOTE_HEAP:
  2549. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2550. seg_no);
  2551. break;
  2552. default:
  2553. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2554. return -EINVAL;
  2555. }
  2556. md_entry.phys_addr = pa;
  2557. md_entry.virt_addr = (uintptr_t)va;
  2558. md_entry.size = size;
  2559. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2560. cnss_pr_dbg("Mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2561. md_entry.name, va, &pa, size);
  2562. ret = msm_minidump_add_region(&md_entry);
  2563. if (ret < 0)
  2564. cnss_pr_err("Failed to add mini dump region, err = %d\n", ret);
  2565. return ret;
  2566. }
  2567. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2568. enum cnss_fw_dump_type type, int seg_no,
  2569. void *va, phys_addr_t pa, size_t size)
  2570. {
  2571. struct md_region md_entry;
  2572. int ret;
  2573. switch (type) {
  2574. case CNSS_FW_IMAGE:
  2575. snprintf(md_entry.name, sizeof(md_entry.name), "FBC_%X",
  2576. seg_no);
  2577. break;
  2578. case CNSS_FW_RDDM:
  2579. snprintf(md_entry.name, sizeof(md_entry.name), "RDDM_%X",
  2580. seg_no);
  2581. break;
  2582. case CNSS_FW_REMOTE_HEAP:
  2583. snprintf(md_entry.name, sizeof(md_entry.name), "RHEAP_%X",
  2584. seg_no);
  2585. break;
  2586. default:
  2587. cnss_pr_err("Unknown dump type ID: %d\n", type);
  2588. return -EINVAL;
  2589. }
  2590. md_entry.phys_addr = pa;
  2591. md_entry.virt_addr = (uintptr_t)va;
  2592. md_entry.size = size;
  2593. md_entry.id = MSM_DUMP_DATA_CNSS_WLAN;
  2594. cnss_pr_dbg("Remove mini dump region: %s, va: %pK, pa: %pa, size: 0x%zx\n",
  2595. md_entry.name, va, &pa, size);
  2596. ret = msm_minidump_remove_region(&md_entry);
  2597. if (ret)
  2598. cnss_pr_err("Failed to remove mini dump region, err = %d\n",
  2599. ret);
  2600. return ret;
  2601. }
  2602. #else
  2603. int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
  2604. phys_addr_t *pa, unsigned long attrs)
  2605. {
  2606. return 0;
  2607. }
  2608. int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
  2609. enum cnss_fw_dump_type type, int seg_no,
  2610. void *va, phys_addr_t pa, size_t size)
  2611. {
  2612. return 0;
  2613. }
  2614. int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
  2615. enum cnss_fw_dump_type type, int seg_no,
  2616. void *va, phys_addr_t pa, size_t size)
  2617. {
  2618. return 0;
  2619. }
  2620. #endif /* CONFIG_QCOM_MINIDUMP */
  2621. int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
  2622. const struct firmware **fw_entry,
  2623. const char *filename)
  2624. {
  2625. if (IS_ENABLED(CONFIG_CNSS_REQ_FW_DIRECT))
  2626. return request_firmware_direct(fw_entry, filename,
  2627. &plat_priv->plat_dev->dev);
  2628. else
  2629. return firmware_request_nowarn(fw_entry, filename,
  2630. &plat_priv->plat_dev->dev);
  2631. }
  2632. #if IS_ENABLED(CONFIG_INTERCONNECT)
  2633. /**
  2634. * cnss_register_bus_scale() - Setup interconnect voting data
  2635. * @plat_priv: Platform data structure
  2636. *
  2637. * For different interconnect path configured in device tree setup voting data
  2638. * for list of bandwidth requirements.
  2639. *
  2640. * Result: 0 for success. -EINVAL if not configured
  2641. */
  2642. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2643. {
  2644. int ret = -EINVAL;
  2645. u32 idx, i, j, cfg_arr_size, *cfg_arr = NULL;
  2646. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2647. struct device *dev = &plat_priv->plat_dev->dev;
  2648. INIT_LIST_HEAD(&plat_priv->icc.list_head);
  2649. ret = of_property_read_u32(dev->of_node,
  2650. "qcom,icc-path-count",
  2651. &plat_priv->icc.path_count);
  2652. if (ret) {
  2653. cnss_pr_dbg("Platform Bus Interconnect path not configured\n");
  2654. return 0;
  2655. }
  2656. ret = of_property_read_u32(plat_priv->plat_dev->dev.of_node,
  2657. "qcom,bus-bw-cfg-count",
  2658. &plat_priv->icc.bus_bw_cfg_count);
  2659. if (ret) {
  2660. cnss_pr_err("Failed to get Bus BW Config table size\n");
  2661. goto cleanup;
  2662. }
  2663. cfg_arr_size = plat_priv->icc.path_count *
  2664. plat_priv->icc.bus_bw_cfg_count * CNSS_ICC_VOTE_MAX;
  2665. cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
  2666. if (!cfg_arr) {
  2667. cnss_pr_err("Failed to alloc cfg table mem\n");
  2668. ret = -ENOMEM;
  2669. goto cleanup;
  2670. }
  2671. ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
  2672. "qcom,bus-bw-cfg", cfg_arr,
  2673. cfg_arr_size);
  2674. if (ret) {
  2675. cnss_pr_err("Invalid Bus BW Config Table\n");
  2676. goto cleanup;
  2677. }
  2678. cnss_pr_dbg("ICC Path_Count: %d BW_CFG_Count: %d\n",
  2679. plat_priv->icc.path_count, plat_priv->icc.bus_bw_cfg_count);
  2680. for (idx = 0; idx < plat_priv->icc.path_count; idx++) {
  2681. bus_bw_info = devm_kzalloc(dev, sizeof(*bus_bw_info),
  2682. GFP_KERNEL);
  2683. if (!bus_bw_info) {
  2684. ret = -ENOMEM;
  2685. goto out;
  2686. }
  2687. ret = of_property_read_string_index(dev->of_node,
  2688. "interconnect-names", idx,
  2689. &bus_bw_info->icc_name);
  2690. if (ret)
  2691. goto out;
  2692. bus_bw_info->icc_path =
  2693. of_icc_get(&plat_priv->plat_dev->dev,
  2694. bus_bw_info->icc_name);
  2695. if (IS_ERR(bus_bw_info->icc_path)) {
  2696. ret = PTR_ERR(bus_bw_info->icc_path);
  2697. if (ret != -EPROBE_DEFER) {
  2698. cnss_pr_err("Failed to get Interconnect path for %s. Err: %d\n",
  2699. bus_bw_info->icc_name, ret);
  2700. goto out;
  2701. }
  2702. }
  2703. bus_bw_info->cfg_table =
  2704. devm_kcalloc(dev, plat_priv->icc.bus_bw_cfg_count,
  2705. sizeof(*bus_bw_info->cfg_table),
  2706. GFP_KERNEL);
  2707. if (!bus_bw_info->cfg_table) {
  2708. ret = -ENOMEM;
  2709. goto out;
  2710. }
  2711. cnss_pr_dbg("ICC Vote CFG for path: %s\n",
  2712. bus_bw_info->icc_name);
  2713. for (i = 0, j = (idx * plat_priv->icc.bus_bw_cfg_count *
  2714. CNSS_ICC_VOTE_MAX);
  2715. i < plat_priv->icc.bus_bw_cfg_count;
  2716. i++, j += 2) {
  2717. bus_bw_info->cfg_table[i].avg_bw = cfg_arr[j];
  2718. bus_bw_info->cfg_table[i].peak_bw = cfg_arr[j + 1];
  2719. cnss_pr_dbg("ICC Vote BW: %d avg: %d peak: %d\n",
  2720. i, bus_bw_info->cfg_table[i].avg_bw,
  2721. bus_bw_info->cfg_table[i].peak_bw);
  2722. }
  2723. list_add_tail(&bus_bw_info->list,
  2724. &plat_priv->icc.list_head);
  2725. }
  2726. kfree(cfg_arr);
  2727. return 0;
  2728. out:
  2729. list_for_each_entry_safe(bus_bw_info, tmp,
  2730. &plat_priv->icc.list_head, list) {
  2731. list_del(&bus_bw_info->list);
  2732. }
  2733. cleanup:
  2734. kfree(cfg_arr);
  2735. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2736. return ret;
  2737. }
  2738. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv)
  2739. {
  2740. struct cnss_bus_bw_info *bus_bw_info, *tmp;
  2741. list_for_each_entry_safe(bus_bw_info, tmp,
  2742. &plat_priv->icc.list_head, list) {
  2743. list_del(&bus_bw_info->list);
  2744. if (bus_bw_info->icc_path)
  2745. icc_put(bus_bw_info->icc_path);
  2746. }
  2747. memset(&plat_priv->icc, 0, sizeof(plat_priv->icc));
  2748. }
  2749. #else
  2750. static int cnss_register_bus_scale(struct cnss_plat_data *plat_priv)
  2751. {
  2752. return 0;
  2753. }
  2754. static void cnss_unregister_bus_scale(struct cnss_plat_data *plat_priv) {}
  2755. #endif /* CONFIG_INTERCONNECT */
  2756. void cnss_daemon_connection_update_cb(void *cb_ctx, bool status)
  2757. {
  2758. struct cnss_plat_data *plat_priv = cb_ctx;
  2759. if (!plat_priv) {
  2760. cnss_pr_err("%s: Invalid context\n", __func__);
  2761. return;
  2762. }
  2763. if (status) {
  2764. cnss_pr_info("CNSS Daemon connected\n");
  2765. set_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2766. complete(&plat_priv->daemon_connected);
  2767. } else {
  2768. cnss_pr_info("CNSS Daemon disconnected\n");
  2769. reinit_completion(&plat_priv->daemon_connected);
  2770. clear_bit(CNSS_DAEMON_CONNECTED, &plat_priv->driver_state);
  2771. }
  2772. }
  2773. static ssize_t enable_hds_store(struct device *dev,
  2774. struct device_attribute *attr,
  2775. const char *buf, size_t count)
  2776. {
  2777. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2778. unsigned int enable_hds = 0;
  2779. if (!plat_priv)
  2780. return -ENODEV;
  2781. if (sscanf(buf, "%du", &enable_hds) != 1) {
  2782. cnss_pr_err("Invalid enable_hds sysfs command\n");
  2783. return -EINVAL;
  2784. }
  2785. if (enable_hds)
  2786. plat_priv->hds_enabled = true;
  2787. else
  2788. plat_priv->hds_enabled = false;
  2789. cnss_pr_dbg("%s HDS file download, count is %zu\n",
  2790. plat_priv->hds_enabled ? "Enable" : "Disable", count);
  2791. return count;
  2792. }
  2793. static ssize_t recovery_show(struct device *dev,
  2794. struct device_attribute *attr,
  2795. char *buf)
  2796. {
  2797. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2798. u32 buf_size = PAGE_SIZE;
  2799. u32 curr_len = 0;
  2800. u32 buf_written = 0;
  2801. if (!plat_priv)
  2802. return -ENODEV;
  2803. buf_written = scnprintf(buf, buf_size,
  2804. "Usage: echo [recovery_bitmap] > /sys/kernel/cnss/recovery\n"
  2805. "BIT0 -- wlan fw recovery\n"
  2806. "BIT1 -- wlan pcss recovery\n"
  2807. "---------------------------------\n");
  2808. curr_len += buf_written;
  2809. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  2810. "WLAN recovery %s[%d]\n",
  2811. plat_priv->recovery_enabled ? "Enabled" : "Disabled",
  2812. plat_priv->recovery_enabled);
  2813. curr_len += buf_written;
  2814. buf_written = scnprintf(buf + curr_len, buf_size - curr_len,
  2815. "WLAN PCSS recovery %s[%d]\n",
  2816. plat_priv->recovery_pcss_enabled ? "Enabled" : "Disabled",
  2817. plat_priv->recovery_pcss_enabled);
  2818. curr_len += buf_written;
  2819. /*
  2820. * Now size of curr_len is not over page size for sure,
  2821. * later if new item or none-fixed size item added, need
  2822. * add check to make sure curr_len is not over page size.
  2823. */
  2824. return curr_len;
  2825. }
  2826. static ssize_t time_sync_period_show(struct device *dev,
  2827. struct device_attribute *attr,
  2828. char *buf)
  2829. {
  2830. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2831. return scnprintf(buf, PAGE_SIZE, "%u ms\n",
  2832. plat_priv->ctrl_params.time_sync_period);
  2833. }
  2834. static ssize_t time_sync_period_store(struct device *dev,
  2835. struct device_attribute *attr,
  2836. const char *buf, size_t count)
  2837. {
  2838. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2839. unsigned int time_sync_period = 0;
  2840. if (!plat_priv)
  2841. return -ENODEV;
  2842. if (sscanf(buf, "%du", &time_sync_period) != 1) {
  2843. cnss_pr_err("Invalid time sync sysfs command\n");
  2844. return -EINVAL;
  2845. }
  2846. if (time_sync_period >= CNSS_MIN_TIME_SYNC_PERIOD)
  2847. cnss_bus_update_time_sync_period(plat_priv, time_sync_period);
  2848. return count;
  2849. }
  2850. static ssize_t recovery_store(struct device *dev,
  2851. struct device_attribute *attr,
  2852. const char *buf, size_t count)
  2853. {
  2854. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2855. unsigned int recovery = 0;
  2856. int ret;
  2857. if (!plat_priv)
  2858. return -ENODEV;
  2859. if (sscanf(buf, "%du", &recovery) != 1) {
  2860. cnss_pr_err("Invalid recovery sysfs command\n");
  2861. return -EINVAL;
  2862. }
  2863. plat_priv->recovery_enabled = !!(recovery & CNSS_WLAN_RECOVERY);
  2864. plat_priv->recovery_pcss_enabled = !!(recovery & CNSS_PCSS_RECOVERY);
  2865. cnss_pr_dbg("%s WLAN recovery, count is %zu\n",
  2866. plat_priv->recovery_enabled ? "Enable" : "Disable", count);
  2867. cnss_pr_dbg("%s PCSS recovery, count is %zu\n",
  2868. plat_priv->recovery_pcss_enabled ? "Enable" : "Disable", count);
  2869. ret = cnss_send_subsys_restart_level_msg(plat_priv);
  2870. if (ret < 0) {
  2871. cnss_pr_err("pcss recovery setting failed with ret %d\n", ret);
  2872. plat_priv->recovery_pcss_enabled = false;
  2873. return -EINVAL;
  2874. }
  2875. return count;
  2876. }
  2877. static ssize_t shutdown_store(struct device *dev,
  2878. struct device_attribute *attr,
  2879. const char *buf, size_t count)
  2880. {
  2881. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2882. if (plat_priv) {
  2883. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  2884. del_timer(&plat_priv->fw_boot_timer);
  2885. complete_all(&plat_priv->power_up_complete);
  2886. complete_all(&plat_priv->cal_complete);
  2887. }
  2888. cnss_pr_dbg("Received shutdown notification\n");
  2889. return count;
  2890. }
  2891. static ssize_t fs_ready_store(struct device *dev,
  2892. struct device_attribute *attr,
  2893. const char *buf, size_t count)
  2894. {
  2895. int fs_ready = 0;
  2896. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2897. if (sscanf(buf, "%du", &fs_ready) != 1)
  2898. return -EINVAL;
  2899. cnss_pr_dbg("File system is ready, fs_ready is %d, count is %zu\n",
  2900. fs_ready, count);
  2901. if (!plat_priv) {
  2902. cnss_pr_err("plat_priv is NULL\n");
  2903. return count;
  2904. }
  2905. if (test_bit(QMI_BYPASS, &plat_priv->ctrl_params.quirks)) {
  2906. cnss_pr_dbg("QMI is bypassed\n");
  2907. return count;
  2908. }
  2909. switch (plat_priv->device_id) {
  2910. case QCA6290_DEVICE_ID:
  2911. case QCA6390_DEVICE_ID:
  2912. case QCA6490_DEVICE_ID:
  2913. case KIWI_DEVICE_ID:
  2914. case MANGO_DEVICE_ID:
  2915. break;
  2916. default:
  2917. cnss_pr_err("Not supported for device ID 0x%lx\n",
  2918. plat_priv->device_id);
  2919. return count;
  2920. }
  2921. set_bit(CNSS_FS_READY, &plat_priv->driver_state);
  2922. if (fs_ready == FILE_SYSTEM_READY && plat_priv->cbc_enabled) {
  2923. cnss_driver_event_post(plat_priv,
  2924. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  2925. 0, NULL);
  2926. }
  2927. return count;
  2928. }
  2929. static ssize_t qdss_trace_start_store(struct device *dev,
  2930. struct device_attribute *attr,
  2931. const char *buf, size_t count)
  2932. {
  2933. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2934. wlfw_qdss_trace_start(plat_priv);
  2935. cnss_pr_dbg("Received QDSS start command\n");
  2936. return count;
  2937. }
  2938. static ssize_t qdss_trace_stop_store(struct device *dev,
  2939. struct device_attribute *attr,
  2940. const char *buf, size_t count)
  2941. {
  2942. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2943. u32 option = 0;
  2944. if (sscanf(buf, "%du", &option) != 1)
  2945. return -EINVAL;
  2946. wlfw_qdss_trace_stop(plat_priv, option);
  2947. cnss_pr_dbg("Received QDSS stop command\n");
  2948. return count;
  2949. }
  2950. static ssize_t qdss_conf_download_store(struct device *dev,
  2951. struct device_attribute *attr,
  2952. const char *buf, size_t count)
  2953. {
  2954. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2955. cnss_wlfw_qdss_dnld_send_sync(plat_priv);
  2956. cnss_pr_dbg("Received QDSS download config command\n");
  2957. return count;
  2958. }
  2959. static ssize_t hw_trace_override_store(struct device *dev,
  2960. struct device_attribute *attr,
  2961. const char *buf, size_t count)
  2962. {
  2963. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2964. int tmp = 0;
  2965. if (sscanf(buf, "%du", &tmp) != 1)
  2966. return -EINVAL;
  2967. plat_priv->hw_trc_override = tmp;
  2968. cnss_pr_dbg("Received QDSS hw_trc_override indication\n");
  2969. return count;
  2970. }
  2971. static ssize_t charger_mode_store(struct device *dev,
  2972. struct device_attribute *attr,
  2973. const char *buf, size_t count)
  2974. {
  2975. struct cnss_plat_data *plat_priv = dev_get_drvdata(dev);
  2976. int tmp = 0;
  2977. if (sscanf(buf, "%du", &tmp) != 1)
  2978. return -EINVAL;
  2979. plat_priv->charger_mode = tmp;
  2980. cnss_pr_dbg("Received Charger Mode: %d\n", tmp);
  2981. return count;
  2982. }
  2983. static DEVICE_ATTR_WO(fs_ready);
  2984. static DEVICE_ATTR_WO(shutdown);
  2985. static DEVICE_ATTR_RW(recovery);
  2986. static DEVICE_ATTR_WO(enable_hds);
  2987. static DEVICE_ATTR_WO(qdss_trace_start);
  2988. static DEVICE_ATTR_WO(qdss_trace_stop);
  2989. static DEVICE_ATTR_WO(qdss_conf_download);
  2990. static DEVICE_ATTR_WO(hw_trace_override);
  2991. static DEVICE_ATTR_WO(charger_mode);
  2992. static DEVICE_ATTR_RW(time_sync_period);
  2993. static struct attribute *cnss_attrs[] = {
  2994. &dev_attr_fs_ready.attr,
  2995. &dev_attr_shutdown.attr,
  2996. &dev_attr_recovery.attr,
  2997. &dev_attr_enable_hds.attr,
  2998. &dev_attr_qdss_trace_start.attr,
  2999. &dev_attr_qdss_trace_stop.attr,
  3000. &dev_attr_qdss_conf_download.attr,
  3001. &dev_attr_hw_trace_override.attr,
  3002. &dev_attr_charger_mode.attr,
  3003. &dev_attr_time_sync_period.attr,
  3004. NULL,
  3005. };
  3006. static struct attribute_group cnss_attr_group = {
  3007. .attrs = cnss_attrs,
  3008. };
  3009. static int cnss_create_sysfs_link(struct cnss_plat_data *plat_priv)
  3010. {
  3011. struct device *dev = &plat_priv->plat_dev->dev;
  3012. int ret;
  3013. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "cnss");
  3014. if (ret) {
  3015. cnss_pr_err("Failed to create cnss link, err = %d\n",
  3016. ret);
  3017. goto out;
  3018. }
  3019. /* This is only for backward compatibility. */
  3020. ret = sysfs_create_link(kernel_kobj, &dev->kobj, "shutdown_wlan");
  3021. if (ret) {
  3022. cnss_pr_err("Failed to create shutdown_wlan link, err = %d\n",
  3023. ret);
  3024. goto rm_cnss_link;
  3025. }
  3026. return 0;
  3027. rm_cnss_link:
  3028. sysfs_remove_link(kernel_kobj, "cnss");
  3029. out:
  3030. return ret;
  3031. }
  3032. static void cnss_remove_sysfs_link(struct cnss_plat_data *plat_priv)
  3033. {
  3034. sysfs_remove_link(kernel_kobj, "shutdown_wlan");
  3035. sysfs_remove_link(kernel_kobj, "cnss");
  3036. }
  3037. static int cnss_create_sysfs(struct cnss_plat_data *plat_priv)
  3038. {
  3039. int ret = 0;
  3040. ret = devm_device_add_group(&plat_priv->plat_dev->dev,
  3041. &cnss_attr_group);
  3042. if (ret) {
  3043. cnss_pr_err("Failed to create cnss device group, err = %d\n",
  3044. ret);
  3045. goto out;
  3046. }
  3047. cnss_create_sysfs_link(plat_priv);
  3048. return 0;
  3049. out:
  3050. return ret;
  3051. }
  3052. static void cnss_remove_sysfs(struct cnss_plat_data *plat_priv)
  3053. {
  3054. cnss_remove_sysfs_link(plat_priv);
  3055. devm_device_remove_group(&plat_priv->plat_dev->dev, &cnss_attr_group);
  3056. }
  3057. static int cnss_event_work_init(struct cnss_plat_data *plat_priv)
  3058. {
  3059. spin_lock_init(&plat_priv->event_lock);
  3060. plat_priv->event_wq = alloc_workqueue("cnss_driver_event",
  3061. WQ_UNBOUND, 1);
  3062. if (!plat_priv->event_wq) {
  3063. cnss_pr_err("Failed to create event workqueue!\n");
  3064. return -EFAULT;
  3065. }
  3066. INIT_WORK(&plat_priv->event_work, cnss_driver_event_work);
  3067. INIT_LIST_HEAD(&plat_priv->event_list);
  3068. return 0;
  3069. }
  3070. static void cnss_event_work_deinit(struct cnss_plat_data *plat_priv)
  3071. {
  3072. destroy_workqueue(plat_priv->event_wq);
  3073. }
  3074. static int cnss_reboot_notifier(struct notifier_block *nb,
  3075. unsigned long action,
  3076. void *data)
  3077. {
  3078. struct cnss_plat_data *plat_priv =
  3079. container_of(nb, struct cnss_plat_data, reboot_nb);
  3080. set_bit(CNSS_IN_REBOOT, &plat_priv->driver_state);
  3081. del_timer(&plat_priv->fw_boot_timer);
  3082. complete_all(&plat_priv->power_up_complete);
  3083. complete_all(&plat_priv->cal_complete);
  3084. cnss_pr_dbg("Reboot is in progress with action %d\n", action);
  3085. return NOTIFY_DONE;
  3086. }
  3087. #ifdef CONFIG_CNSS_HW_SECURE_DISABLE
  3088. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3089. {
  3090. struct Object client_env;
  3091. struct Object app_object;
  3092. u32 wifi_uid = HW_WIFI_UID;
  3093. union ObjectArg obj_arg[2] = {{{0, 0}}};
  3094. int ret;
  3095. u8 state = 0;
  3096. /* get rootObj */
  3097. ret = get_client_env_object(&client_env);
  3098. if (ret) {
  3099. cnss_pr_dbg("Failed to get client_env_object, ret: %d\n", ret);
  3100. goto end;
  3101. }
  3102. ret = IClientEnv_open(client_env, HW_STATE_UID, &app_object);
  3103. if (ret) {
  3104. cnss_pr_dbg("Failed to get app_object, ret: %d\n", ret);
  3105. if (ret == FEATURE_NOT_SUPPORTED) {
  3106. ret = 0; /* Do not Assert */
  3107. cnss_pr_dbg("Secure HW feature not supported\n");
  3108. }
  3109. goto exit_release_clientenv;
  3110. }
  3111. obj_arg[0].b = (struct ObjectBuf) {&wifi_uid, sizeof(u32)};
  3112. obj_arg[1].b = (struct ObjectBuf) {&state, sizeof(u8)};
  3113. ret = Object_invoke(app_object, HW_OP_GET_STATE, obj_arg,
  3114. ObjectCounts_pack(1, 1, 0, 0));
  3115. cnss_pr_dbg("SMC invoke ret: %d state: %d\n", ret, state);
  3116. if (ret) {
  3117. if (ret == PERIPHERAL_NOT_FOUND) {
  3118. ret = 0; /* Do not Assert */
  3119. cnss_pr_dbg("Secure HW mode is not updated. Peripheral not found\n");
  3120. }
  3121. goto exit_release_app_obj;
  3122. }
  3123. if (state == 1)
  3124. set_bit(CNSS_WLAN_HW_DISABLED,
  3125. &plat_priv->driver_state);
  3126. else
  3127. clear_bit(CNSS_WLAN_HW_DISABLED,
  3128. &plat_priv->driver_state);
  3129. exit_release_app_obj:
  3130. Object_release(app_object);
  3131. exit_release_clientenv:
  3132. Object_release(client_env);
  3133. end:
  3134. if (ret) {
  3135. cnss_pr_err("Unable to get HW disable status\n");
  3136. CNSS_ASSERT(0);
  3137. }
  3138. return ret;
  3139. }
  3140. #else
  3141. int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv)
  3142. {
  3143. return 0;
  3144. }
  3145. #endif
  3146. static int cnss_misc_init(struct cnss_plat_data *plat_priv)
  3147. {
  3148. int ret;
  3149. ret = cnss_init_sol_gpio(plat_priv);
  3150. if (ret)
  3151. return ret;
  3152. timer_setup(&plat_priv->fw_boot_timer,
  3153. cnss_bus_fw_boot_timeout_hdlr, 0);
  3154. ret = register_pm_notifier(&cnss_pm_notifier);
  3155. if (ret)
  3156. cnss_pr_err("Failed to register PM notifier, err = %d\n", ret);
  3157. plat_priv->reboot_nb.notifier_call = cnss_reboot_notifier;
  3158. ret = register_reboot_notifier(&plat_priv->reboot_nb);
  3159. if (ret)
  3160. cnss_pr_err("Failed to register reboot notifier, err = %d\n",
  3161. ret);
  3162. ret = device_init_wakeup(&plat_priv->plat_dev->dev, true);
  3163. if (ret)
  3164. cnss_pr_err("Failed to init platform device wakeup source, err = %d\n",
  3165. ret);
  3166. INIT_WORK(&plat_priv->recovery_work, cnss_recovery_work_handler);
  3167. init_completion(&plat_priv->power_up_complete);
  3168. init_completion(&plat_priv->cal_complete);
  3169. init_completion(&plat_priv->rddm_complete);
  3170. init_completion(&plat_priv->recovery_complete);
  3171. init_completion(&plat_priv->daemon_connected);
  3172. mutex_init(&plat_priv->dev_lock);
  3173. mutex_init(&plat_priv->driver_ops_lock);
  3174. plat_priv->recovery_ws =
  3175. wakeup_source_register(&plat_priv->plat_dev->dev,
  3176. "CNSS_FW_RECOVERY");
  3177. if (!plat_priv->recovery_ws)
  3178. cnss_pr_err("Failed to setup FW recovery wake source\n");
  3179. ret = cnss_plat_ipc_register(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3180. cnss_daemon_connection_update_cb,
  3181. plat_priv);
  3182. if (ret)
  3183. cnss_pr_err("QMI IPC connection call back register failed, err = %d\n",
  3184. ret);
  3185. plat_priv->sram_dump = kcalloc(SRAM_DUMP_SIZE, 1, GFP_KERNEL);
  3186. return 0;
  3187. }
  3188. static void cnss_misc_deinit(struct cnss_plat_data *plat_priv)
  3189. {
  3190. cnss_plat_ipc_unregister(CNSS_PLAT_IPC_DAEMON_QMI_CLIENT_V01,
  3191. plat_priv);
  3192. complete_all(&plat_priv->recovery_complete);
  3193. complete_all(&plat_priv->rddm_complete);
  3194. complete_all(&plat_priv->cal_complete);
  3195. complete_all(&plat_priv->power_up_complete);
  3196. complete_all(&plat_priv->daemon_connected);
  3197. device_init_wakeup(&plat_priv->plat_dev->dev, false);
  3198. unregister_reboot_notifier(&plat_priv->reboot_nb);
  3199. unregister_pm_notifier(&cnss_pm_notifier);
  3200. del_timer(&plat_priv->fw_boot_timer);
  3201. wakeup_source_unregister(plat_priv->recovery_ws);
  3202. cnss_deinit_sol_gpio(plat_priv);
  3203. kfree(plat_priv->sram_dump);
  3204. }
  3205. static void cnss_init_control_params(struct cnss_plat_data *plat_priv)
  3206. {
  3207. plat_priv->ctrl_params.quirks = CNSS_QUIRKS_DEFAULT;
  3208. plat_priv->cbc_enabled = !IS_ENABLED(CONFIG_CNSS_EMULATION) &&
  3209. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3210. "qcom,wlan-cbc-enabled");
  3211. plat_priv->ctrl_params.mhi_timeout = CNSS_MHI_TIMEOUT_DEFAULT;
  3212. plat_priv->ctrl_params.mhi_m2_timeout = CNSS_MHI_M2_TIMEOUT_DEFAULT;
  3213. plat_priv->ctrl_params.qmi_timeout = CNSS_QMI_TIMEOUT_DEFAULT;
  3214. plat_priv->ctrl_params.bdf_type = CNSS_BDF_TYPE_DEFAULT;
  3215. plat_priv->ctrl_params.time_sync_period = CNSS_TIME_SYNC_PERIOD_DEFAULT;
  3216. /* Set adsp_pc_enabled default value to true as ADSP pc is always
  3217. * enabled by default
  3218. */
  3219. plat_priv->adsp_pc_enabled = true;
  3220. }
  3221. static void cnss_get_pm_domain_info(struct cnss_plat_data *plat_priv)
  3222. {
  3223. struct device *dev = &plat_priv->plat_dev->dev;
  3224. plat_priv->use_pm_domain =
  3225. of_property_read_bool(dev->of_node, "use-pm-domain");
  3226. cnss_pr_dbg("use-pm-domain is %d\n", plat_priv->use_pm_domain);
  3227. }
  3228. static void cnss_get_wlaon_pwr_ctrl_info(struct cnss_plat_data *plat_priv)
  3229. {
  3230. struct device *dev = &plat_priv->plat_dev->dev;
  3231. plat_priv->set_wlaon_pwr_ctrl =
  3232. of_property_read_bool(dev->of_node, "qcom,set-wlaon-pwr-ctrl");
  3233. cnss_pr_dbg("set_wlaon_pwr_ctrl is %d\n",
  3234. plat_priv->set_wlaon_pwr_ctrl);
  3235. }
  3236. static bool cnss_use_fw_path_with_prefix(struct cnss_plat_data *plat_priv)
  3237. {
  3238. return (of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3239. "qcom,converged-dt") ||
  3240. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3241. "qcom,same-dt-multi-dev") ||
  3242. of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3243. "qcom,multi-wlan-exchg"));
  3244. }
  3245. static const struct platform_device_id cnss_platform_id_table[] = {
  3246. { .name = "qca6174", .driver_data = QCA6174_DEVICE_ID, },
  3247. { .name = "qca6290", .driver_data = QCA6290_DEVICE_ID, },
  3248. { .name = "qca6390", .driver_data = QCA6390_DEVICE_ID, },
  3249. { .name = "qca6490", .driver_data = QCA6490_DEVICE_ID, },
  3250. { .name = "kiwi", .driver_data = KIWI_DEVICE_ID, },
  3251. { .name = "mango", .driver_data = MANGO_DEVICE_ID, },
  3252. { .name = "qcaconv", .driver_data = 0, },
  3253. { },
  3254. };
  3255. static const struct of_device_id cnss_of_match_table[] = {
  3256. {
  3257. .compatible = "qcom,cnss",
  3258. .data = (void *)&cnss_platform_id_table[0]},
  3259. {
  3260. .compatible = "qcom,cnss-qca6290",
  3261. .data = (void *)&cnss_platform_id_table[1]},
  3262. {
  3263. .compatible = "qcom,cnss-qca6390",
  3264. .data = (void *)&cnss_platform_id_table[2]},
  3265. {
  3266. .compatible = "qcom,cnss-qca6490",
  3267. .data = (void *)&cnss_platform_id_table[3]},
  3268. {
  3269. .compatible = "qcom,cnss-kiwi",
  3270. .data = (void *)&cnss_platform_id_table[4]},
  3271. {
  3272. .compatible = "qcom,cnss-mango",
  3273. .data = (void *)&cnss_platform_id_table[5]},
  3274. {
  3275. .compatible = "qcom,cnss-qca-converged",
  3276. .data = (void *)&cnss_platform_id_table[6]},
  3277. { },
  3278. };
  3279. MODULE_DEVICE_TABLE(of, cnss_of_match_table);
  3280. static inline bool
  3281. cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
  3282. {
  3283. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3284. "use-nv-mac");
  3285. }
  3286. static int cnss_get_dev_cfg_node(struct cnss_plat_data *plat_priv)
  3287. {
  3288. struct device_node *child;
  3289. u32 id, i;
  3290. int id_n, device_identifier_gpio, ret;
  3291. u8 gpio_value;
  3292. if (!plat_priv->is_converged_dt)
  3293. return 0;
  3294. /* Parses the wlan_sw_ctrl gpio which is used to identify device */
  3295. ret = cnss_get_wlan_sw_ctrl(plat_priv);
  3296. if (ret) {
  3297. cnss_pr_dbg("Failed to parse wlan_sw_ctrl gpio, error:%d", ret);
  3298. return ret;
  3299. }
  3300. device_identifier_gpio = plat_priv->pinctrl_info.wlan_sw_ctrl_gpio;
  3301. gpio_value = gpio_get_value(device_identifier_gpio);
  3302. cnss_pr_dbg("Value of Device Identifier GPIO: %d\n", gpio_value);
  3303. for_each_available_child_of_node(plat_priv->plat_dev->dev.of_node,
  3304. child) {
  3305. if (strcmp(child->name, "chip_cfg"))
  3306. continue;
  3307. id_n = of_property_count_u32_elems(child, "supported-ids");
  3308. if (id_n <= 0) {
  3309. cnss_pr_err("Device id is NOT set\n");
  3310. return -EINVAL;
  3311. }
  3312. for (i = 0; i < id_n; i++) {
  3313. ret = of_property_read_u32_index(child,
  3314. "supported-ids",
  3315. i, &id);
  3316. if (ret) {
  3317. cnss_pr_err("Failed to read supported ids\n");
  3318. return -EINVAL;
  3319. }
  3320. if (gpio_value && id == QCA6490_DEVICE_ID) {
  3321. plat_priv->plat_dev->dev.of_node = child;
  3322. plat_priv->device_id = QCA6490_DEVICE_ID;
  3323. cnss_utils_update_device_type(CNSS_HSP_DEVICE_TYPE);
  3324. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3325. child->name, i, id);
  3326. return 0;
  3327. } else if (!gpio_value && id == KIWI_DEVICE_ID) {
  3328. plat_priv->plat_dev->dev.of_node = child;
  3329. plat_priv->device_id = KIWI_DEVICE_ID;
  3330. cnss_utils_update_device_type(CNSS_HMT_DEVICE_TYPE);
  3331. cnss_pr_dbg("got node[%s@%d] for device[0x%x]\n",
  3332. child->name, i, id);
  3333. return 0;
  3334. }
  3335. }
  3336. }
  3337. return -EINVAL;
  3338. }
  3339. static inline bool
  3340. cnss_is_converged_dt(struct cnss_plat_data *plat_priv)
  3341. {
  3342. return of_property_read_bool(plat_priv->plat_dev->dev.of_node,
  3343. "qcom,converged-dt");
  3344. }
  3345. static int cnss_wlan_device_init(struct cnss_plat_data *plat_priv)
  3346. {
  3347. int ret = 0;
  3348. int retry = 0;
  3349. if (test_bit(SKIP_DEVICE_BOOT, &plat_priv->ctrl_params.quirks))
  3350. return 0;
  3351. retry:
  3352. ret = cnss_power_on_device(plat_priv);
  3353. if (ret)
  3354. goto end;
  3355. ret = cnss_bus_init(plat_priv);
  3356. if (ret) {
  3357. if ((ret != -EPROBE_DEFER) &&
  3358. retry++ < POWER_ON_RETRY_MAX_TIMES) {
  3359. cnss_power_off_device(plat_priv);
  3360. cnss_pr_dbg("Retry cnss_bus_init #%d\n", retry);
  3361. msleep(POWER_ON_RETRY_DELAY_MS * retry);
  3362. goto retry;
  3363. }
  3364. goto power_off;
  3365. }
  3366. return 0;
  3367. power_off:
  3368. cnss_power_off_device(plat_priv);
  3369. end:
  3370. return ret;
  3371. }
  3372. int cnss_wlan_hw_enable(void)
  3373. {
  3374. struct cnss_plat_data *plat_priv = cnss_get_plat_priv(NULL);
  3375. int ret = 0;
  3376. clear_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state);
  3377. if (test_bit(CNSS_PCI_PROBE_DONE, &plat_priv->driver_state))
  3378. goto register_driver;
  3379. ret = cnss_wlan_device_init(plat_priv);
  3380. if (ret) {
  3381. CNSS_ASSERT(0);
  3382. return ret;
  3383. }
  3384. if (test_bit(CNSS_FS_READY, &plat_priv->driver_state))
  3385. cnss_driver_event_post(plat_priv,
  3386. CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
  3387. 0, NULL);
  3388. register_driver:
  3389. if (plat_priv->driver_ops)
  3390. ret = cnss_wlan_register_driver(plat_priv->driver_ops);
  3391. return ret;
  3392. }
  3393. EXPORT_SYMBOL(cnss_wlan_hw_enable);
  3394. static int cnss_probe(struct platform_device *plat_dev)
  3395. {
  3396. int ret = 0;
  3397. struct cnss_plat_data *plat_priv;
  3398. const struct of_device_id *of_id;
  3399. const struct platform_device_id *device_id;
  3400. if (cnss_get_plat_priv(plat_dev)) {
  3401. cnss_pr_err("Driver is already initialized!\n");
  3402. ret = -EEXIST;
  3403. goto out;
  3404. }
  3405. of_id = of_match_device(cnss_of_match_table, &plat_dev->dev);
  3406. if (!of_id || !of_id->data) {
  3407. cnss_pr_err("Failed to find of match device!\n");
  3408. ret = -ENODEV;
  3409. goto out;
  3410. }
  3411. device_id = of_id->data;
  3412. plat_priv = devm_kzalloc(&plat_dev->dev, sizeof(*plat_priv),
  3413. GFP_KERNEL);
  3414. if (!plat_priv) {
  3415. ret = -ENOMEM;
  3416. goto out;
  3417. }
  3418. plat_priv->plat_dev = plat_dev;
  3419. plat_priv->device_id = device_id->driver_data;
  3420. plat_priv->is_converged_dt = cnss_is_converged_dt(plat_priv);
  3421. plat_priv->use_fw_path_with_prefix =
  3422. cnss_use_fw_path_with_prefix(plat_priv);
  3423. ret = cnss_get_dev_cfg_node(plat_priv);
  3424. if (ret) {
  3425. cnss_pr_err("Failed to get device cfg node, err = %d\n", ret);
  3426. goto reset_plat_dev;
  3427. }
  3428. plat_priv->bus_type = cnss_get_bus_type(plat_priv->device_id);
  3429. plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
  3430. plat_priv->driver_mode = CNSS_DRIVER_MODE_MAX;
  3431. cnss_set_plat_priv(plat_dev, plat_priv);
  3432. platform_set_drvdata(plat_dev, plat_priv);
  3433. INIT_LIST_HEAD(&plat_priv->vreg_list);
  3434. INIT_LIST_HEAD(&plat_priv->clk_list);
  3435. cnss_get_pm_domain_info(plat_priv);
  3436. cnss_get_wlaon_pwr_ctrl_info(plat_priv);
  3437. cnss_power_misc_params_init(plat_priv);
  3438. cnss_get_tcs_info(plat_priv);
  3439. cnss_get_cpr_info(plat_priv);
  3440. cnss_aop_mbox_init(plat_priv);
  3441. cnss_init_control_params(plat_priv);
  3442. ret = cnss_get_resources(plat_priv);
  3443. if (ret)
  3444. goto reset_ctx;
  3445. ret = cnss_register_esoc(plat_priv);
  3446. if (ret)
  3447. goto free_res;
  3448. ret = cnss_register_bus_scale(plat_priv);
  3449. if (ret)
  3450. goto unreg_esoc;
  3451. ret = cnss_create_sysfs(plat_priv);
  3452. if (ret)
  3453. goto unreg_bus_scale;
  3454. ret = cnss_event_work_init(plat_priv);
  3455. if (ret)
  3456. goto remove_sysfs;
  3457. ret = cnss_qmi_init(plat_priv);
  3458. if (ret)
  3459. goto deinit_event_work;
  3460. ret = cnss_dms_init(plat_priv);
  3461. if (ret)
  3462. goto deinit_qmi;
  3463. ret = cnss_debugfs_create(plat_priv);
  3464. if (ret)
  3465. goto deinit_dms;
  3466. ret = cnss_misc_init(plat_priv);
  3467. if (ret)
  3468. goto destroy_debugfs;
  3469. ret = cnss_wlan_hw_disable_check(plat_priv);
  3470. if (ret)
  3471. goto deinit_misc;
  3472. /* Make sure all platform related init are done before
  3473. * device power on and bus init.
  3474. */
  3475. if (!test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
  3476. ret = cnss_wlan_device_init(plat_priv);
  3477. if (ret)
  3478. goto deinit_misc;
  3479. } else {
  3480. cnss_pr_info("WLAN HW Disabled. Defer PCI enumeration\n");
  3481. }
  3482. cnss_register_coex_service(plat_priv);
  3483. cnss_register_ims_service(plat_priv);
  3484. ret = cnss_genl_init();
  3485. if (ret < 0)
  3486. cnss_pr_err("CNSS genl init failed %d\n", ret);
  3487. cnss_pr_info("Platform driver probed successfully.\n");
  3488. return 0;
  3489. deinit_misc:
  3490. cnss_misc_deinit(plat_priv);
  3491. destroy_debugfs:
  3492. cnss_debugfs_destroy(plat_priv);
  3493. deinit_dms:
  3494. cnss_dms_deinit(plat_priv);
  3495. deinit_qmi:
  3496. cnss_qmi_deinit(plat_priv);
  3497. deinit_event_work:
  3498. cnss_event_work_deinit(plat_priv);
  3499. remove_sysfs:
  3500. cnss_remove_sysfs(plat_priv);
  3501. unreg_bus_scale:
  3502. cnss_unregister_bus_scale(plat_priv);
  3503. unreg_esoc:
  3504. cnss_unregister_esoc(plat_priv);
  3505. free_res:
  3506. cnss_put_resources(plat_priv);
  3507. reset_ctx:
  3508. platform_set_drvdata(plat_dev, NULL);
  3509. reset_plat_dev:
  3510. cnss_set_plat_priv(plat_dev, NULL);
  3511. out:
  3512. return ret;
  3513. }
  3514. static int cnss_remove(struct platform_device *plat_dev)
  3515. {
  3516. struct cnss_plat_data *plat_priv = platform_get_drvdata(plat_dev);
  3517. cnss_genl_exit();
  3518. cnss_unregister_ims_service(plat_priv);
  3519. cnss_unregister_coex_service(plat_priv);
  3520. cnss_bus_deinit(plat_priv);
  3521. cnss_misc_deinit(plat_priv);
  3522. cnss_debugfs_destroy(plat_priv);
  3523. cnss_dms_deinit(plat_priv);
  3524. cnss_qmi_deinit(plat_priv);
  3525. cnss_event_work_deinit(plat_priv);
  3526. cnss_remove_sysfs(plat_priv);
  3527. cnss_unregister_bus_scale(plat_priv);
  3528. cnss_unregister_esoc(plat_priv);
  3529. cnss_put_resources(plat_priv);
  3530. if (!IS_ERR_OR_NULL(plat_priv->mbox_chan))
  3531. mbox_free_channel(plat_priv->mbox_chan);
  3532. platform_set_drvdata(plat_dev, NULL);
  3533. plat_env = NULL;
  3534. return 0;
  3535. }
  3536. static struct platform_driver cnss_platform_driver = {
  3537. .probe = cnss_probe,
  3538. .remove = cnss_remove,
  3539. .driver = {
  3540. .name = "cnss2",
  3541. .of_match_table = cnss_of_match_table,
  3542. #ifdef CONFIG_CNSS_ASYNC
  3543. .probe_type = PROBE_PREFER_ASYNCHRONOUS,
  3544. #endif
  3545. },
  3546. };
  3547. static bool cnss_check_compatible_node(void)
  3548. {
  3549. struct device_node *dn = NULL;
  3550. for_each_matching_node(dn, cnss_of_match_table) {
  3551. if (of_device_is_available(dn)) {
  3552. cnss_allow_driver_loading = true;
  3553. return true;
  3554. }
  3555. }
  3556. return false;
  3557. }
  3558. /**
  3559. * cnss_is_valid_dt_node_found - Check if valid device tree node present
  3560. *
  3561. * Valid device tree node means a node with "compatible" property from the
  3562. * device match table and "status" property is not disabled.
  3563. *
  3564. * Return: true if valid device tree node found, false if not found
  3565. */
  3566. static bool cnss_is_valid_dt_node_found(void)
  3567. {
  3568. struct device_node *dn = NULL;
  3569. for_each_matching_node(dn, cnss_of_match_table) {
  3570. if (of_device_is_available(dn))
  3571. break;
  3572. }
  3573. if (dn)
  3574. return true;
  3575. return false;
  3576. }
  3577. static int __init cnss_initialize(void)
  3578. {
  3579. int ret = 0;
  3580. if (!cnss_is_valid_dt_node_found())
  3581. return -ENODEV;
  3582. if (!cnss_check_compatible_node())
  3583. return ret;
  3584. cnss_debug_init();
  3585. ret = platform_driver_register(&cnss_platform_driver);
  3586. if (ret)
  3587. cnss_debug_deinit();
  3588. return ret;
  3589. }
  3590. static void __exit cnss_exit(void)
  3591. {
  3592. platform_driver_unregister(&cnss_platform_driver);
  3593. cnss_debug_deinit();
  3594. }
  3595. module_init(cnss_initialize);
  3596. module_exit(cnss_exit);
  3597. MODULE_LICENSE("GPL v2");
  3598. MODULE_DESCRIPTION("CNSS2 Platform Driver");