dsi_clk.h 9.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef _DSI_CLK_H_
  6. #define _DSI_CLK_H_
  7. #include <linux/device.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/types.h>
  10. #include <linux/clk.h>
  11. #include <drm/drmP.h>
  12. #define MAX_STRING_LEN 32
  13. #define MAX_DSI_CTRL 2
  14. enum dsi_clk_state {
  15. DSI_CLK_OFF,
  16. DSI_CLK_ON,
  17. DSI_CLK_EARLY_GATE,
  18. };
  19. enum clk_req_client {
  20. DSI_CLK_REQ_MDP_CLIENT = 0,
  21. DSI_CLK_REQ_DSI_CLIENT,
  22. };
  23. enum dsi_link_clk_type {
  24. DSI_LINK_ESC_CLK,
  25. DSI_LINK_BYTE_CLK,
  26. DSI_LINK_PIX_CLK,
  27. DSI_LINK_BYTE_INTF_CLK,
  28. DSI_LINK_CLK_MAX,
  29. };
  30. enum dsi_link_clk_op_type {
  31. DSI_LINK_CLK_SET_RATE = BIT(0),
  32. DSI_LINK_CLK_PREPARE = BIT(1),
  33. DSI_LINK_CLK_ENABLE = BIT(2),
  34. DSI_LINK_CLK_START = BIT(0) | BIT(1) | BIT(2),
  35. };
  36. enum dsi_clk_type {
  37. DSI_CORE_CLK = BIT(0),
  38. DSI_LINK_CLK = BIT(1),
  39. DSI_ALL_CLKS = (BIT(0) | BIT(1)),
  40. DSI_CLKS_MAX = BIT(2),
  41. };
  42. enum dsi_lclk_type {
  43. DSI_LINK_NONE = 0,
  44. DSI_LINK_LP_CLK = BIT(0),
  45. DSI_LINK_HS_CLK = BIT(1),
  46. };
  47. struct dsi_clk_ctrl_info {
  48. enum dsi_clk_type clk_type;
  49. enum dsi_clk_state clk_state;
  50. enum clk_req_client client;
  51. };
  52. struct clk_ctrl_cb {
  53. void *priv;
  54. int (*dsi_clk_cb)(void *priv, struct dsi_clk_ctrl_info clk_ctrl_info);
  55. };
  56. /**
  57. * struct dsi_core_clk_info - Core clock information for DSI hardware
  58. * @mdp_core_clk: Handle to MDP core clock.
  59. * @iface_clk: Handle to MDP interface clock.
  60. * @core_mmss_clk: Handle to MMSS core clock.
  61. * @bus_clk: Handle to bus clock.
  62. * @mnoc_clk: Handle to MMSS NOC clock.
  63. * @drm: Pointer to drm device node
  64. */
  65. struct dsi_core_clk_info {
  66. struct clk *mdp_core_clk;
  67. struct clk *iface_clk;
  68. struct clk *core_mmss_clk;
  69. struct clk *bus_clk;
  70. struct clk *mnoc_clk;
  71. struct drm_device *drm;
  72. };
  73. /**
  74. * struct dsi_link_hs_clk_info - Set of high speed link clocks for DSI HW
  75. * @byte_clk: Handle to DSI byte_clk.
  76. * @pixel_clk: Handle to DSI pixel_clk.
  77. * @byte_intf_clk: Handle to DSI byte intf. clock.
  78. */
  79. struct dsi_link_hs_clk_info {
  80. struct clk *byte_clk;
  81. struct clk *pixel_clk;
  82. struct clk *byte_intf_clk;
  83. };
  84. /**
  85. * struct dsi_link_lp_clk_info - Set of low power link clocks for DSI HW.
  86. * @esc_clk: Handle to DSI escape clock.
  87. */
  88. struct dsi_link_lp_clk_info {
  89. struct clk *esc_clk;
  90. };
  91. /**
  92. * struct link_clk_freq - Clock frequency information for Link clocks
  93. * @byte_clk_rate: Frequency of DSI byte_clk in KHz.
  94. * @pixel_clk_rate: Frequency of DSI pixel_clk in KHz.
  95. * @esc_clk_rate: Frequency of DSI escape clock in KHz.
  96. */
  97. struct link_clk_freq {
  98. u32 byte_clk_rate;
  99. u32 pix_clk_rate;
  100. u32 esc_clk_rate;
  101. };
  102. /**
  103. * typedef *pre_clockoff_cb() - Callback before clock is turned off
  104. * @priv: private data pointer.
  105. * @clk_type: clock which is being turned off.
  106. * @l_type: specifies if the clock is HS or LP type. Valid only for link clocks.
  107. * @new_state: next state for the clock.
  108. *
  109. * @return: error code.
  110. */
  111. typedef int (*pre_clockoff_cb)(void *priv,
  112. enum dsi_clk_type clk_type,
  113. enum dsi_lclk_type l_type,
  114. enum dsi_clk_state new_state);
  115. /**
  116. * typedef *post_clockoff_cb() - Callback after clock is turned off
  117. * @priv: private data pointer.
  118. * @clk_type: clock which was turned off.
  119. * @l_type: specifies if the clock is HS or LP type. Valid only for link clocks.
  120. * @curr_state: current state for the clock.
  121. *
  122. * @return: error code.
  123. */
  124. typedef int (*post_clockoff_cb)(void *priv,
  125. enum dsi_clk_type clk_type,
  126. enum dsi_lclk_type l_type,
  127. enum dsi_clk_state curr_state);
  128. /**
  129. * typedef *post_clockon_cb() - Callback after clock is turned on
  130. * @priv: private data pointer.
  131. * @clk_type: clock which was turned on.
  132. * @l_type: specifies if the clock is HS or LP type. Valid only for link clocks.
  133. * @curr_state: current state for the clock.
  134. *
  135. * @return: error code.
  136. */
  137. typedef int (*post_clockon_cb)(void *priv,
  138. enum dsi_clk_type clk_type,
  139. enum dsi_lclk_type l_type,
  140. enum dsi_clk_state curr_state);
  141. /**
  142. * typedef *pre_clockon_cb() - Callback before clock is turned on
  143. * @priv: private data pointer.
  144. * @clk_type: clock which is being turned on.
  145. * @l_type: specifies if the clock is HS or LP type.Valid only for link clocks.
  146. * @new_state: next state for the clock.
  147. *
  148. * @return: error code.
  149. */
  150. typedef int (*pre_clockon_cb)(void *priv,
  151. enum dsi_clk_type clk_type,
  152. enum dsi_lclk_type l_type,
  153. enum dsi_clk_state new_state);
  154. /**
  155. * struct dsi_clk_info - clock information for DSI hardware.
  156. * @name: client name.
  157. * @c_clks[MAX_DSI_CTRL] array of core clock configurations
  158. * @l_lp_clks[MAX_DSI_CTRL] array of low power(esc) clock configurations
  159. * @l_hs_clks[MAX_DSI_CTRL] array of high speed clock configurations
  160. * @ctrl_index[MAX_DSI_CTRL] array of DSI controller indexes mapped
  161. * to core and link clock configurations
  162. * @pre_clkoff_cb callback before clock is turned off
  163. * @post_clkoff_cb callback after clock is turned off
  164. * @post_clkon_cb callback after clock is turned on
  165. * @pre_clkon_cb callback before clock is turned on
  166. * @priv_data pointer to private data
  167. * @master_ndx master DSI controller index
  168. * @dsi_ctrl_count number of DSI controllers
  169. */
  170. struct dsi_clk_info {
  171. char name[MAX_STRING_LEN];
  172. struct dsi_core_clk_info c_clks[MAX_DSI_CTRL];
  173. struct dsi_link_lp_clk_info l_lp_clks[MAX_DSI_CTRL];
  174. struct dsi_link_hs_clk_info l_hs_clks[MAX_DSI_CTRL];
  175. u32 ctrl_index[MAX_DSI_CTRL];
  176. pre_clockoff_cb pre_clkoff_cb;
  177. post_clockoff_cb post_clkoff_cb;
  178. post_clockon_cb post_clkon_cb;
  179. pre_clockon_cb pre_clkon_cb;
  180. void *priv_data;
  181. u32 master_ndx;
  182. u32 dsi_ctrl_count;
  183. };
  184. /**
  185. * struct dsi_clk_link_set - Pair of clock handles to describe link clocks
  186. * @byte_clk: Handle to DSi byte_clk.
  187. * @pixel_clk: Handle to DSI pixel_clk.
  188. */
  189. struct dsi_clk_link_set {
  190. struct clk *byte_clk;
  191. struct clk *pixel_clk;
  192. };
  193. /**
  194. * dsi_display_clk_mngr_update_splash_status() - Update splash stattus
  195. * @clk_mngr: Structure containing DSI clock information
  196. * @status: Splash status
  197. */
  198. void dsi_display_clk_mngr_update_splash_status(void *clk_mgr, bool status);
  199. /**
  200. * dsi_display_clk_mgr_register() - Register DSI clock manager
  201. * @info: Structure containing DSI clock information
  202. */
  203. void *dsi_display_clk_mngr_register(struct dsi_clk_info *info);
  204. /**
  205. * dsi_display_clk_mngr_deregister() - Deregister DSI clock manager
  206. * @clk_mngr: DSI clock manager pointer
  207. */
  208. int dsi_display_clk_mngr_deregister(void *clk_mngr);
  209. /**
  210. * dsi_register_clk_handle() - Register clock handle with DSI clock manager
  211. * @clk_mngr: DSI clock manager pointer
  212. * @client: DSI clock client pointer.
  213. */
  214. void *dsi_register_clk_handle(void *clk_mngr, char *client);
  215. /**
  216. * dsi_deregister_clk_handle() - Deregister clock handle from DSI clock manager
  217. * @client: DSI clock client pointer.
  218. *
  219. * return: error code in case of failure or 0 for success.
  220. */
  221. int dsi_deregister_clk_handle(void *client);
  222. /**
  223. * dsi_display_link_clk_force_update_ctrl() - force to set link clks
  224. * @handle: Handle of desired DSI clock client.
  225. *
  226. * return: error code in case of failure or 0 for success.
  227. */
  228. int dsi_display_link_clk_force_update_ctrl(void *handle);
  229. /**
  230. * dsi_display_clk_ctrl() - set frequencies for link clks
  231. * @handle: Handle of desired DSI clock client.
  232. * @clk_type: Clock which is being controlled.
  233. * @clk_state: Desired state of clock
  234. *
  235. * return: error code in case of failure or 0 for success.
  236. */
  237. int dsi_display_clk_ctrl(void *handle, u32 clk_type, u32 clk_state);
  238. /**
  239. * dsi_clk_set_link_frequencies() - set frequencies for link clks
  240. * @client: DSI clock client pointer.
  241. * @freq: Structure containing link clock frequencies.
  242. * @index: Index of the DSI controller.
  243. *
  244. * return: error code in case of failure or 0 for success.
  245. */
  246. int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq,
  247. u32 index);
  248. /**
  249. * dsi_clk_set_pixel_clk_rate() - set frequency for pixel_clk
  250. * @client: DSI clock client pointer.
  251. * @pixel_clk: Pixel_clk rate in Hz.
  252. * @index: Index of the DSI controller.
  253. * return: error code in case of failure or 0 for success.
  254. */
  255. int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index);
  256. /**
  257. * dsi_clk_set_byte_clk_rate() - set frequency for byte clock
  258. * @client: DSI clock client pointer.
  259. * @byte_clk: Pixel clock rate in Hz.
  260. * @index: Index of the DSI controller.
  261. * return: error code in case of failure or 0 for success.
  262. */
  263. int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index);
  264. /**
  265. * dsi_clk_update_parent() - update parent clocks for specified clock
  266. * @parent: link clock pair which are set as parent.
  267. * @child: link clock pair whose parent has to be set.
  268. */
  269. int dsi_clk_update_parent(struct dsi_clk_link_set *parent,
  270. struct dsi_clk_link_set *child);
  271. /**
  272. * dsi_clk_prepare_enable() - prepare and enable dsi src clocks
  273. * @clk: list of src clocks.
  274. *
  275. * @return: Zero on success and err no on failure
  276. */
  277. int dsi_clk_prepare_enable(struct dsi_clk_link_set *clk);
  278. /**
  279. * dsi_clk_disable_unprepare() - disable and unprepare dsi src clocks
  280. * @clk: list of src clocks.
  281. */
  282. void dsi_clk_disable_unprepare(struct dsi_clk_link_set *clk);
  283. #endif /* _DSI_CLK_H_ */