hal_api_mon.h 39 KB

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  1. /*
  2. * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_MON_H_
  19. #define _HAL_API_MON_H_
  20. #include "qdf_types.h"
  21. #include "hal_internal.h"
  22. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  23. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  24. #define HAL_RX_MASk(block, field) block##_##field##_MASK
  25. #define HAL_RX_GET(_ptr, block, field) \
  26. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  27. HAL_RX_MASk(block, field)) >> \
  28. HAL_RX_LSB(block, field))
  29. #define HAL_RX_PHY_DATA_RADAR 0x01
  30. #define HAL_SU_MU_CODING_LDPC 0x01
  31. #define HAL_RX_FCS_LEN (4)
  32. #define KEY_EXTIV 0x20
  33. #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000
  34. #define HAL_RX_USER_TLV32_TYPE_LSB 1
  35. #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE
  36. #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000
  37. #define HAL_RX_USER_TLV32_LEN_LSB 10
  38. #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00
  39. #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000
  40. #define HAL_RX_USER_TLV32_USERID_LSB 26
  41. #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000
  42. #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1)
  43. #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask))
  44. #define HAL_RX_TLV32_HDR_SIZE 4
  45. #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \
  46. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  47. HAL_RX_USER_TLV32_TYPE_MASK) >> \
  48. HAL_RX_USER_TLV32_TYPE_LSB)
  49. #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \
  50. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  51. HAL_RX_USER_TLV32_LEN_MASK) >> \
  52. HAL_RX_USER_TLV32_LEN_LSB)
  53. #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \
  54. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  55. HAL_RX_USER_TLV32_USERID_MASK) >> \
  56. HAL_RX_USER_TLV32_USERID_LSB)
  57. #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
  58. #define HAL_TLV_STATUS_PPDU_DONE 1
  59. #define HAL_TLV_STATUS_BUF_DONE 2
  60. #define HAL_MAX_UL_MU_USERS 8
  61. #define HAL_RX_PKT_TYPE_11A 0
  62. #define HAL_RX_PKT_TYPE_11B 1
  63. #define HAL_RX_PKT_TYPE_11N 2
  64. #define HAL_RX_PKT_TYPE_11AC 3
  65. #define HAL_RX_PKT_TYPE_11AX 4
  66. #define HAL_RX_RECEPTION_TYPE_SU 0
  67. #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1
  68. #define HAL_RX_RECEPTION_TYPE_OFDMA 2
  69. #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3
  70. /* Multiply rate by 2 to avoid float point
  71. * and get rate in units of 500kbps
  72. */
  73. #define HAL_11B_RATE_0MCS 11*2
  74. #define HAL_11B_RATE_1MCS 5.5*2
  75. #define HAL_11B_RATE_2MCS 2*2
  76. #define HAL_11B_RATE_3MCS 1*2
  77. #define HAL_11B_RATE_4MCS 11*2
  78. #define HAL_11B_RATE_5MCS 5.5*2
  79. #define HAL_11B_RATE_6MCS 2*2
  80. #define HAL_11A_RATE_0MCS 48*2
  81. #define HAL_11A_RATE_1MCS 24*2
  82. #define HAL_11A_RATE_2MCS 12*2
  83. #define HAL_11A_RATE_3MCS 6*2
  84. #define HAL_11A_RATE_4MCS 54*2
  85. #define HAL_11A_RATE_5MCS 36*2
  86. #define HAL_11A_RATE_6MCS 18*2
  87. #define HAL_11A_RATE_7MCS 9*2
  88. #define HE_GI_0_8 0
  89. #define HE_GI_1_6 1
  90. #define HE_GI_3_2 2
  91. #define HT_SGI_PRESENT 0x80
  92. #define HE_LTF_1_X 0
  93. #define HE_LTF_2_X 1
  94. #define HE_LTF_4_X 2
  95. #define VHT_SIG_SU_NSS_MASK 0x7
  96. #define HAL_TID_INVALID 31
  97. #define HAL_AST_IDX_INVALID 0xFFFF
  98. #ifdef GET_MSDU_AGGREGATION
  99. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
  100. {\
  101. struct rx_msdu_end *rx_msdu_end;\
  102. bool first_msdu, last_msdu; \
  103. rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
  104. first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\
  105. last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\
  106. if (first_msdu && last_msdu)\
  107. rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
  108. else\
  109. rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
  110. } \
  111. #else
  112. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
  113. #endif
  114. enum {
  115. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  116. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  117. HAL_HW_RX_DECAP_FORMAT_ETH2,
  118. HAL_HW_RX_DECAP_FORMAT_8023,
  119. };
  120. enum {
  121. DP_PPDU_STATUS_START,
  122. DP_PPDU_STATUS_DONE,
  123. };
  124. static inline
  125. uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void)
  126. {
  127. /* return the HW_RX_DESC size */
  128. return sizeof(struct rx_pkt_tlvs);
  129. }
  130. static inline
  131. uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data)
  132. {
  133. return data;
  134. }
  135. static inline
  136. uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr)
  137. {
  138. struct rx_attention *rx_attn;
  139. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  140. rx_attn = &rx_desc->attn_tlv.rx_attn;
  141. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  142. }
  143. static inline
  144. uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr)
  145. {
  146. struct rx_attention *rx_attn;
  147. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  148. rx_attn = &rx_desc->attn_tlv.rx_attn;
  149. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  150. }
  151. static inline
  152. uint32_t
  153. HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) {
  154. struct rx_msdu_start *rx_msdu_start;
  155. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  156. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  157. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  158. }
  159. static inline
  160. uint8_t *
  161. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  162. uint8_t *rx_pkt_hdr;
  163. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  164. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  165. return rx_pkt_hdr;
  166. }
  167. static inline
  168. uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr)
  169. {
  170. struct rx_mpdu_info *rx_mpdu_info;
  171. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  172. rx_mpdu_info =
  173. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  174. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  175. }
  176. /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */
  177. static inline
  178. uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr)
  179. {
  180. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  181. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  182. return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
  183. }
  184. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  185. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  186. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  187. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  188. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  189. #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \
  190. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  191. (((struct reo_entrance_ring *)reo_ent_desc) \
  192. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  193. #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \
  194. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  195. (((struct reo_entrance_ring *)reo_ent_desc) \
  196. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  197. #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \
  198. (HAL_RX_BUF_COOKIE_GET(& \
  199. (((struct reo_entrance_ring *)reo_ent_desc) \
  200. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  201. /**
  202. * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and
  203. * cookie from the REO entrance ring element
  204. *
  205. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  206. * the current descriptor
  207. * @ buf_info: structure to return the buffer information
  208. * @ msdu_cnt: pointer to msdu count in MPDU
  209. * Return: void
  210. */
  211. static inline
  212. void hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
  213. struct hal_buf_info *buf_info,
  214. void **pp_buf_addr_info,
  215. uint32_t *msdu_cnt
  216. )
  217. {
  218. struct reo_entrance_ring *reo_ent_ring =
  219. (struct reo_entrance_ring *)rx_desc;
  220. struct buffer_addr_info *buf_addr_info;
  221. struct rx_mpdu_desc_info *rx_mpdu_desc_info_details;
  222. uint32_t loop_cnt;
  223. rx_mpdu_desc_info_details =
  224. &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
  225. *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details,
  226. RX_MPDU_DESC_INFO_0, MSDU_COUNT);
  227. loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT);
  228. buf_addr_info =
  229. &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
  230. buf_info->paddr =
  231. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  232. ((uint64_t)
  233. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  234. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  235. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  236. "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d\n",
  237. __func__, __LINE__, reo_ent_ring, buf_addr_info,
  238. (unsigned long long)buf_info->paddr, loop_cnt);
  239. *pp_buf_addr_info = (void *)buf_addr_info;
  240. }
  241. static inline
  242. void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
  243. struct hal_buf_info *buf_info, void **pp_buf_addr_info)
  244. {
  245. struct rx_msdu_link *msdu_link =
  246. (struct rx_msdu_link *)rx_msdu_link_desc;
  247. struct buffer_addr_info *buf_addr_info;
  248. buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info;
  249. buf_info->paddr =
  250. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  251. ((uint64_t)
  252. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  253. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  254. *pp_buf_addr_info = (void *)buf_addr_info;
  255. }
  256. /**
  257. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  258. *
  259. * @ soc : HAL version of the SOC pointer
  260. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  261. * @ buf_addr_info : void pointer to the buffer_addr_info
  262. *
  263. * Return: void
  264. */
  265. static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc,
  266. void *src_srng_desc, void *buf_addr_info)
  267. {
  268. struct buffer_addr_info *wbm_srng_buffer_addr_info =
  269. (struct buffer_addr_info *)src_srng_desc;
  270. uint64_t paddr;
  271. struct buffer_addr_info *p_buffer_addr_info =
  272. (struct buffer_addr_info *)buf_addr_info;
  273. paddr =
  274. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  275. ((uint64_t)
  276. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  277. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  278. "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx\n",
  279. __func__, __LINE__, src_srng_desc, (unsigned long long)paddr,
  280. (unsigned long long)p_buffer_addr_info->sw_buffer_cookie);
  281. /* Structure copy !!! */
  282. *wbm_srng_buffer_addr_info =
  283. *((struct buffer_addr_info *)buf_addr_info);
  284. }
  285. static inline
  286. uint32 hal_get_rx_msdu_link_desc_size(void)
  287. {
  288. return sizeof(struct rx_msdu_link);
  289. }
  290. enum {
  291. HAL_PKT_TYPE_OFDM = 0,
  292. HAL_PKT_TYPE_CCK,
  293. HAL_PKT_TYPE_HT,
  294. HAL_PKT_TYPE_VHT,
  295. HAL_PKT_TYPE_HE,
  296. };
  297. enum {
  298. HAL_SGI_0_8_US,
  299. HAL_SGI_0_4_US,
  300. HAL_SGI_1_6_US,
  301. HAL_SGI_3_2_US,
  302. };
  303. enum {
  304. HAL_FULL_RX_BW_20,
  305. HAL_FULL_RX_BW_40,
  306. HAL_FULL_RX_BW_80,
  307. HAL_FULL_RX_BW_160,
  308. };
  309. enum {
  310. HAL_RX_TYPE_SU,
  311. HAL_RX_TYPE_MU_MIMO,
  312. HAL_RX_TYPE_MU_OFDMA,
  313. HAL_RX_TYPE_MU_OFDMA_MIMO,
  314. };
  315. /**
  316. * enum
  317. * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL
  318. * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL
  319. */
  320. enum {
  321. HAL_RX_MON_PPDU_START = 0,
  322. HAL_RX_MON_PPDU_END,
  323. };
  324. /**
  325. * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status
  326. *
  327. * @ hw_desc_addr: Start address of Rx HW TLVs
  328. * @ rs: Status for monitor mode
  329. *
  330. * Return: void
  331. */
  332. static inline
  333. void hal_rx_mon_hw_desc_get_mpdu_status(void *hw_desc_addr,
  334. struct mon_rx_status *rs)
  335. {
  336. struct rx_msdu_start *rx_msdu_start;
  337. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  338. uint32_t reg_value;
  339. static uint32_t sgi_hw_to_cdp[] = {
  340. CDP_SGI_0_8_US,
  341. CDP_SGI_0_4_US,
  342. CDP_SGI_1_6_US,
  343. CDP_SGI_3_2_US,
  344. };
  345. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  346. HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
  347. rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
  348. RX_MSDU_START_5, USER_RSSI);
  349. rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
  350. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
  351. rs->sgi = sgi_hw_to_cdp[reg_value];
  352. #if !defined(QCA_WIFI_QCA6290_11AX)
  353. rs->nr_ant = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, NSS);
  354. #endif
  355. reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
  356. rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
  357. /* TODO: rs->beamformed should be set for SU beamforming also */
  358. hal_rx_dump_pkt_tlvs((uint8_t *)rx_desc, QDF_TRACE_LEVEL_DEBUG);
  359. }
  360. struct hal_rx_ppdu_user_info {
  361. };
  362. struct hal_rx_ppdu_common_info {
  363. uint32_t ppdu_id;
  364. uint32_t last_ppdu_id;
  365. uint32_t ppdu_timestamp;
  366. uint32_t mpdu_cnt_fcs_ok;
  367. uint32_t mpdu_cnt_fcs_err;
  368. };
  369. struct hal_rx_msdu_payload_info {
  370. uint8_t *first_msdu_payload;
  371. uint32_t payload_len;
  372. };
  373. struct hal_rx_ppdu_info {
  374. struct hal_rx_ppdu_common_info com_info;
  375. struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS];
  376. struct mon_rx_status rx_status;
  377. struct hal_rx_msdu_payload_info msdu_info;
  378. /* status ring PPDU start and end state */
  379. uint32_t rx_state;
  380. };
  381. static inline uint32_t
  382. hal_get_rx_status_buf_size(void) {
  383. /* RX status buffer size is hard coded for now */
  384. return 2048;
  385. }
  386. static inline uint8_t*
  387. hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
  388. uint32_t tlv_len, tlv_tag;
  389. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
  390. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  391. /* The actual length of PPDU_END is the combined length of many PHY
  392. * TLVs that follow. Skip the TLV header and
  393. * rx_rxpcu_classification_overview that follows the header to get to
  394. * next TLV.
  395. */
  396. if (tlv_tag == WIFIRX_PPDU_END_E)
  397. tlv_len = sizeof(struct rx_rxpcu_classification_overview);
  398. return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len +
  399. HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
  400. }
  401. #ifdef QCA_WIFI_QCA6290_11AX
  402. /**
  403. * hal_rx_proc_phyrx_other_receive_info_tlv() - process other receive info TLV
  404. * @rx_tlv_hdr: pointer to TLV header
  405. * @ppdu_info: pointer to ppdu_info
  406. *
  407. * Return: None
  408. */
  409. static void hal_rx_proc_phyrx_other_receive_info_tlv(void *rx_tlv_hdr,
  410. struct hal_rx_ppdu_info *ppdu_info)
  411. {
  412. uint32_t tlv_tag, tlv_len;
  413. uint32_t temp_len, other_tlv_len, other_tlv_tag;
  414. void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  415. void *other_tlv_hdr = NULL;
  416. void *other_tlv = NULL;
  417. uint32_t ru_details_channel_0;
  418. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  419. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  420. temp_len = 0;
  421. other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
  422. other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
  423. other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
  424. temp_len += other_tlv_len;
  425. other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  426. switch (other_tlv_tag) {
  427. case WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E:
  428. ru_details_channel_0 =
  429. HAL_RX_GET(other_tlv,
  430. PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0,
  431. RU_DETAILS_CHANNEL_0);
  432. qdf_mem_copy(ppdu_info->rx_status.he_RU,
  433. &ru_details_channel_0,
  434. sizeof(ppdu_info->rx_status.he_RU));
  435. if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_20)
  436. ppdu_info->rx_status.he_sig_b_common_known |=
  437. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  438. if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_40)
  439. ppdu_info->rx_status.he_sig_b_common_known |=
  440. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU1;
  441. if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_80)
  442. ppdu_info->rx_status.he_sig_b_common_known |=
  443. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU2;
  444. if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_160)
  445. ppdu_info->rx_status.he_sig_b_common_known |=
  446. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU3;
  447. break;
  448. default:
  449. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  450. "%s unhandled TLV type: %d, TLV len:%d",
  451. __func__, other_tlv_tag, other_tlv_len);
  452. break;
  453. }
  454. }
  455. #else
  456. static inline void
  457. hal_rx_proc_phyrx_other_receive_info_tlv(void *rx_tlv_hdr,
  458. struct hal_rx_ppdu_info *ppdu_info)
  459. {
  460. }
  461. #endif /* QCA_WIFI_QCA6290_11AX */
  462. /**
  463. * hal_rx_status_get_tlv_info() - process receive info TLV
  464. * @rx_tlv_hdr: pointer to TLV header
  465. * @ppdu_info: pointer to ppdu_info
  466. *
  467. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  468. */
  469. static inline uint32_t
  470. hal_rx_status_get_tlv_info(void *rx_tlv_hdr, struct hal_rx_ppdu_info *ppdu_info)
  471. {
  472. uint32_t tlv_tag, user_id, tlv_len, value;
  473. uint8_t group_id = 0;
  474. uint8_t he_dcm = 0;
  475. uint8_t he_stbc = 0;
  476. uint16_t he_gi = 0;
  477. uint16_t he_ltf = 0;
  478. void *rx_tlv;
  479. bool unhandled = false;
  480. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  481. user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
  482. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  483. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  484. switch (tlv_tag) {
  485. case WIFIRX_PPDU_START_E:
  486. ppdu_info->com_info.ppdu_id =
  487. HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
  488. PHY_PPDU_ID);
  489. /* channel number is set in PHY meta data */
  490. ppdu_info->rx_status.chan_num =
  491. HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  492. SW_PHY_META_DATA);
  493. ppdu_info->com_info.ppdu_timestamp =
  494. HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
  495. PPDU_START_TIMESTAMP);
  496. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  497. break;
  498. case WIFIRX_PPDU_START_USER_INFO_E:
  499. break;
  500. case WIFIRX_PPDU_END_E:
  501. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  502. "[%s][%d] ppdu_end_e len=%d",
  503. __func__, __LINE__, tlv_len);
  504. /* This is followed by sub-TLVs of PPDU_END */
  505. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  506. break;
  507. case WIFIRXPCU_PPDU_END_INFO_E:
  508. ppdu_info->rx_status.tsft =
  509. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
  510. WB_TIMESTAMP_UPPER_32);
  511. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  512. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
  513. WB_TIMESTAMP_LOWER_32);
  514. ppdu_info->rx_status.duration =
  515. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_8,
  516. RX_PPDU_DURATION);
  517. break;
  518. case WIFIRX_PPDU_END_USER_STATS_E:
  519. {
  520. unsigned long tid = 0;
  521. uint16_t seq = 0;
  522. ppdu_info->rx_status.ast_index =
  523. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
  524. AST_INDEX);
  525. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
  526. RECEIVED_QOS_DATA_TID_BITMAP);
  527. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, sizeof(tid)*8);
  528. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  529. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  530. ppdu_info->rx_status.tcp_msdu_count =
  531. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  532. TCP_MSDU_COUNT) +
  533. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  534. TCP_ACK_MSDU_COUNT);
  535. ppdu_info->rx_status.udp_msdu_count =
  536. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  537. UDP_MSDU_COUNT);
  538. ppdu_info->rx_status.other_msdu_count =
  539. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  540. OTHER_MSDU_COUNT);
  541. ppdu_info->rx_status.frame_control_info_valid =
  542. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  543. DATA_SEQUENCE_CONTROL_INFO_VALID);
  544. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
  545. FIRST_DATA_SEQ_CTRL);
  546. if (ppdu_info->rx_status.frame_control_info_valid)
  547. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  548. ppdu_info->rx_status.preamble_type =
  549. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  550. HT_CONTROL_FIELD_PKT_TYPE);
  551. switch (ppdu_info->rx_status.preamble_type) {
  552. case HAL_RX_PKT_TYPE_11N:
  553. ppdu_info->rx_status.ht_flags = 1;
  554. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  555. break;
  556. case HAL_RX_PKT_TYPE_11AC:
  557. ppdu_info->rx_status.vht_flags = 1;
  558. break;
  559. case HAL_RX_PKT_TYPE_11AX:
  560. ppdu_info->rx_status.he_flags = 1;
  561. break;
  562. default:
  563. break;
  564. }
  565. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  566. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  567. MPDU_CNT_FCS_OK);
  568. ppdu_info->com_info.mpdu_cnt_fcs_err =
  569. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
  570. MPDU_CNT_FCS_ERR);
  571. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  572. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  573. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  574. else
  575. ppdu_info->rx_status.rs_flags &=
  576. (~IEEE80211_AMPDU_FLAG);
  577. break;
  578. }
  579. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  580. break;
  581. case WIFIRX_PPDU_END_STATUS_DONE_E:
  582. return HAL_TLV_STATUS_PPDU_DONE;
  583. case WIFIDUMMY_E:
  584. return HAL_TLV_STATUS_BUF_DONE;
  585. case WIFIPHYRX_HT_SIG_E:
  586. {
  587. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  588. HAL_RX_OFFSET(PHYRX_HT_SIG_0,
  589. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  590. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
  591. FEC_CODING);
  592. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  593. 1 : 0;
  594. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  595. HT_SIG_INFO_0, MCS);
  596. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  597. HT_SIG_INFO_0, CBW);
  598. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  599. HT_SIG_INFO_1, SHORT_GI);
  600. break;
  601. }
  602. case WIFIPHYRX_L_SIG_B_E:
  603. {
  604. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  605. HAL_RX_OFFSET(PHYRX_L_SIG_B_0,
  606. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  607. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
  608. switch (value) {
  609. case 1:
  610. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  611. break;
  612. case 2:
  613. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  614. break;
  615. case 3:
  616. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  617. break;
  618. case 4:
  619. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  620. break;
  621. case 5:
  622. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  623. break;
  624. case 6:
  625. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  626. break;
  627. case 7:
  628. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  629. break;
  630. default:
  631. break;
  632. }
  633. ppdu_info->rx_status.cck_flag = 1;
  634. break;
  635. }
  636. case WIFIPHYRX_L_SIG_A_E:
  637. {
  638. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  639. HAL_RX_OFFSET(PHYRX_L_SIG_A_0,
  640. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  641. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
  642. switch (value) {
  643. case 8:
  644. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  645. break;
  646. case 9:
  647. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  648. break;
  649. case 10:
  650. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  651. break;
  652. case 11:
  653. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  654. break;
  655. case 12:
  656. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  657. break;
  658. case 13:
  659. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  660. break;
  661. case 14:
  662. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  663. break;
  664. case 15:
  665. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  666. break;
  667. default:
  668. break;
  669. }
  670. ppdu_info->rx_status.ofdm_flag = 1;
  671. break;
  672. }
  673. case WIFIPHYRX_VHT_SIG_A_E:
  674. {
  675. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  676. HAL_RX_OFFSET(PHYRX_VHT_SIG_A_0,
  677. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  678. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
  679. SU_MU_CODING);
  680. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  681. 1 : 0;
  682. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, GROUP_ID);
  683. ppdu_info->rx_status.vht_flag_values5 = group_id;
  684. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  685. VHT_SIG_A_INFO_1, MCS);
  686. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  687. VHT_SIG_A_INFO_1, GI_SETTING);
  688. #if !defined(QCA_WIFI_QCA6290_11AX)
  689. ppdu_info->rx_status.is_stbc = HAL_RX_GET(vht_sig_a_info,
  690. VHT_SIG_A_INFO_0, STBC);
  691. value = HAL_RX_GET(vht_sig_a_info,
  692. VHT_SIG_A_INFO_0, N_STS);
  693. if (ppdu_info->rx_status.is_stbc && (value > 0))
  694. value = ((value + 1) >> 1) - 1;
  695. ppdu_info->rx_status.nss = ((value & VHT_SIG_SU_NSS_MASK) + 1);
  696. #else
  697. ppdu_info->rx_status.nss = 0;
  698. #endif
  699. ppdu_info->rx_status.vht_flag_values3[0] =
  700. (((ppdu_info->rx_status.mcs) << 4)
  701. | ppdu_info->rx_status.nss);
  702. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  703. VHT_SIG_A_INFO_0, BANDWIDTH);
  704. ppdu_info->rx_status.vht_flag_values2 =
  705. ppdu_info->rx_status.bw;
  706. ppdu_info->rx_status.vht_flag_values4 =
  707. HAL_RX_GET(vht_sig_a_info,
  708. VHT_SIG_A_INFO_1, SU_MU_CODING);
  709. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  710. VHT_SIG_A_INFO_1, BEAMFORMED);
  711. break;
  712. }
  713. case WIFIPHYRX_HE_SIG_A_SU_E:
  714. {
  715. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  716. HAL_RX_OFFSET(PHYRX_HE_SIG_A_SU_0,
  717. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  718. ppdu_info->rx_status.he_flags = 1;
  719. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  720. FORMAT_INDICATION);
  721. if (value == 0) {
  722. ppdu_info->rx_status.he_data1 =
  723. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  724. } else {
  725. ppdu_info->rx_status.he_data1 =
  726. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  727. }
  728. /* data1 */
  729. ppdu_info->rx_status.he_data1 |=
  730. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  731. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  732. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  733. QDF_MON_STATUS_HE_MCS_KNOWN |
  734. QDF_MON_STATUS_HE_DCM_KNOWN |
  735. QDF_MON_STATUS_HE_CODING_KNOWN |
  736. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  737. QDF_MON_STATUS_HE_STBC_KNOWN |
  738. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  739. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  740. /* data2 */
  741. ppdu_info->rx_status.he_data2 =
  742. QDF_MON_STATUS_HE_GI_KNOWN;
  743. ppdu_info->rx_status.he_data2 |=
  744. QDF_MON_STATUS_TXBF_KNOWN |
  745. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  746. QDF_MON_STATUS_TXOP_KNOWN |
  747. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  748. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  749. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  750. /* data3 */
  751. value = HAL_RX_GET(he_sig_a_su_info,
  752. HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
  753. ppdu_info->rx_status.he_data3 = value;
  754. value = HAL_RX_GET(he_sig_a_su_info,
  755. HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
  756. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  757. ppdu_info->rx_status.he_data3 |= value;
  758. value = HAL_RX_GET(he_sig_a_su_info,
  759. HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
  760. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  761. ppdu_info->rx_status.he_data3 |= value;
  762. value = HAL_RX_GET(he_sig_a_su_info,
  763. HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
  764. ppdu_info->rx_status.mcs = value;
  765. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  766. ppdu_info->rx_status.he_data3 |= value;
  767. value = HAL_RX_GET(he_sig_a_su_info,
  768. HE_SIG_A_SU_INFO_0, DCM);
  769. he_dcm = value;
  770. value = value << QDF_MON_STATUS_DCM_SHIFT;
  771. ppdu_info->rx_status.he_data3 |= value;
  772. value = HAL_RX_GET(he_sig_a_su_info,
  773. HE_SIG_A_SU_INFO_1, CODING);
  774. value = value << QDF_MON_STATUS_CODING_SHIFT;
  775. ppdu_info->rx_status.he_data3 |= value;
  776. value = HAL_RX_GET(he_sig_a_su_info,
  777. HE_SIG_A_SU_INFO_1,
  778. LDPC_EXTRA_SYMBOL);
  779. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  780. ppdu_info->rx_status.he_data3 |= value;
  781. value = HAL_RX_GET(he_sig_a_su_info,
  782. HE_SIG_A_SU_INFO_1, STBC);
  783. he_stbc = value;
  784. value = value << QDF_MON_STATUS_STBC_SHIFT;
  785. ppdu_info->rx_status.he_data3 |= value;
  786. /* data4 */
  787. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  788. SPATIAL_REUSE);
  789. ppdu_info->rx_status.he_data4 = value;
  790. /* data5 */
  791. value = HAL_RX_GET(he_sig_a_su_info,
  792. HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
  793. ppdu_info->rx_status.he_data5 = value;
  794. ppdu_info->rx_status.bw = value;
  795. value = HAL_RX_GET(he_sig_a_su_info,
  796. HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
  797. switch (value) {
  798. case 0:
  799. he_gi = HE_GI_0_8;
  800. he_ltf = HE_LTF_1_X;
  801. break;
  802. case 1:
  803. he_gi = HE_GI_0_8;
  804. he_ltf = HE_LTF_2_X;
  805. break;
  806. case 2:
  807. he_gi = HE_GI_1_6;
  808. he_ltf = HE_LTF_2_X;
  809. break;
  810. case 3:
  811. if (he_dcm && he_stbc) {
  812. he_gi = HE_GI_0_8;
  813. he_ltf = HE_LTF_4_X;
  814. } else {
  815. he_gi = HE_GI_3_2;
  816. he_ltf = HE_LTF_4_X;
  817. }
  818. break;
  819. }
  820. ppdu_info->rx_status.sgi = he_gi;
  821. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  822. ppdu_info->rx_status.he_data5 |= value;
  823. value = he_ltf << QDF_MON_STATUS_HE_LTF_SHIFT;
  824. ppdu_info->rx_status.he_data5 |= value;
  825. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  826. PACKET_EXTENSION_A_FACTOR);
  827. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  828. ppdu_info->rx_status.he_data5 |= value;
  829. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
  830. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  831. ppdu_info->rx_status.he_data5 |= value;
  832. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  833. PACKET_EXTENSION_PE_DISAMBIGUITY);
  834. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  835. ppdu_info->rx_status.he_data5 |= value;
  836. /* data6 */
  837. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  838. value++;
  839. ppdu_info->rx_status.nss = value;
  840. ppdu_info->rx_status.he_data6 = value;
  841. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  842. DOPPLER_INDICATION);
  843. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  844. ppdu_info->rx_status.he_data6 |= value;
  845. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  846. TXOP_DURATION);
  847. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  848. ppdu_info->rx_status.he_data6 |= value;
  849. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  850. HE_SIG_A_SU_INFO_1, TXBF);
  851. break;
  852. }
  853. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  854. {
  855. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  856. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_DL_0,
  857. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  858. ppdu_info->rx_status.he_mu_flags = 1;
  859. /* HE Flags */
  860. /*data1*/
  861. ppdu_info->rx_status.he_data1 =
  862. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  863. ppdu_info->rx_status.he_data1 |=
  864. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  865. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  866. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  867. QDF_MON_STATUS_HE_STBC_KNOWN |
  868. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  869. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  870. /* data2 */
  871. ppdu_info->rx_status.he_data2 =
  872. QDF_MON_STATUS_HE_GI_KNOWN;
  873. ppdu_info->rx_status.he_data2 |=
  874. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  875. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  876. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  877. QDF_MON_STATUS_TXOP_KNOWN |
  878. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  879. /*data3*/
  880. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  881. HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
  882. ppdu_info->rx_status.he_data3 = value;
  883. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  884. HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
  885. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  886. ppdu_info->rx_status.he_data3 |= value;
  887. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  888. HE_SIG_A_MU_DL_INFO_1,
  889. LDPC_EXTRA_SYMBOL);
  890. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  891. ppdu_info->rx_status.he_data3 |= value;
  892. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  893. HE_SIG_A_MU_DL_INFO_1, STBC);
  894. he_stbc = value;
  895. value = value << QDF_MON_STATUS_STBC_SHIFT;
  896. ppdu_info->rx_status.he_data3 |= value;
  897. /*data4*/
  898. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  899. SPATIAL_REUSE);
  900. ppdu_info->rx_status.he_data4 = value;
  901. /*data5*/
  902. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  903. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  904. ppdu_info->rx_status.he_data5 = value;
  905. ppdu_info->rx_status.bw = value;
  906. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  907. HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
  908. switch (value) {
  909. case 0:
  910. he_gi = HE_GI_0_8;
  911. he_ltf = HE_LTF_4_X;
  912. break;
  913. case 1:
  914. he_gi = HE_GI_0_8;
  915. he_ltf = HE_LTF_2_X;
  916. break;
  917. case 2:
  918. he_gi = HE_GI_1_6;
  919. he_ltf = HE_LTF_2_X;
  920. break;
  921. case 3:
  922. he_gi = HE_GI_3_2;
  923. he_ltf = HE_LTF_4_X;
  924. break;
  925. }
  926. ppdu_info->rx_status.sgi = he_gi;
  927. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  928. ppdu_info->rx_status.he_data5 |= value;
  929. value = he_ltf << QDF_MON_STATUS_HE_LTF_SHIFT;
  930. ppdu_info->rx_status.he_data5 |= value;
  931. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  932. PACKET_EXTENSION_A_FACTOR);
  933. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  934. ppdu_info->rx_status.he_data5 |= value;
  935. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  936. PACKET_EXTENSION_PE_DISAMBIGUITY);
  937. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  938. ppdu_info->rx_status.he_data5 |= value;
  939. /*data6*/
  940. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  941. DOPPLER_INDICATION);
  942. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  943. ppdu_info->rx_status.he_data6 |= value;
  944. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  945. TXOP_DURATION);
  946. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  947. ppdu_info->rx_status.he_data6 |= value;
  948. /* HE-MU Flags */
  949. /* HE-MU-flags1 */
  950. ppdu_info->rx_status.he_flags1 =
  951. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  952. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  953. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  954. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  955. QDF_MON_STATUS_RU_0_KNOWN;
  956. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  957. HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
  958. ppdu_info->rx_status.he_flags1 |= value;
  959. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  960. HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
  961. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  962. ppdu_info->rx_status.he_flags1 |= value;
  963. /* HE-MU-flags2 */
  964. ppdu_info->rx_status.he_flags2 =
  965. QDF_MON_STATUS_BW_KNOWN;
  966. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  967. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  968. ppdu_info->rx_status.he_flags2 |= value;
  969. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  970. HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
  971. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  972. ppdu_info->rx_status.he_flags2 |= value;
  973. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  974. HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
  975. value = value - 1;
  976. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  977. ppdu_info->rx_status.he_flags2 |= value;
  978. break;
  979. }
  980. case WIFIPHYRX_HE_SIG_B1_MU_E:
  981. {
  982. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  983. HAL_RX_OFFSET(PHYRX_HE_SIG_B1_MU_0,
  984. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  985. ppdu_info->rx_status.he_sig_b_common_known |=
  986. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  987. /* TODO: Check on the availability of other fields in
  988. * sig_b_common
  989. */
  990. value = HAL_RX_GET(he_sig_b1_mu_info,
  991. HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
  992. ppdu_info->rx_status.he_RU[0] = value;
  993. break;
  994. }
  995. case WIFIPHYRX_HE_SIG_B2_MU_E:
  996. {
  997. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  998. HAL_RX_OFFSET(PHYRX_HE_SIG_B2_MU_0,
  999. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  1000. /*
  1001. * Not all "HE" fields can be updated from
  1002. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1003. * to populate rest of the "HE" fields for MU scenarios.
  1004. */
  1005. /* HE-data1 */
  1006. ppdu_info->rx_status.he_data1 |=
  1007. QDF_MON_STATUS_HE_MCS_KNOWN |
  1008. QDF_MON_STATUS_HE_CODING_KNOWN;
  1009. /* HE-data2 */
  1010. /* HE-data3 */
  1011. value = HAL_RX_GET(he_sig_b2_mu_info,
  1012. HE_SIG_B2_MU_INFO_0, STA_MCS);
  1013. ppdu_info->rx_status.mcs = value;
  1014. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1015. ppdu_info->rx_status.he_data3 |= value;
  1016. value = HAL_RX_GET(he_sig_b2_mu_info,
  1017. HE_SIG_B2_MU_INFO_0, STA_CODING);
  1018. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1019. ppdu_info->rx_status.he_data3 |= value;
  1020. /* HE-data4 */
  1021. value = HAL_RX_GET(he_sig_b2_mu_info,
  1022. HE_SIG_B2_MU_INFO_0, STA_ID);
  1023. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1024. ppdu_info->rx_status.he_data4 |= value;
  1025. /* HE-data5 */
  1026. /* HE-data6 */
  1027. value = HAL_RX_GET(he_sig_b2_mu_info,
  1028. HE_SIG_B2_MU_INFO_0, NSTS);
  1029. /* value n indicates n+1 spatial streams */
  1030. value++;
  1031. ppdu_info->rx_status.nss = value;
  1032. ppdu_info->rx_status.he_data6 |= value;
  1033. break;
  1034. }
  1035. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  1036. {
  1037. uint8_t *he_sig_b2_ofdma_info =
  1038. (uint8_t *)rx_tlv +
  1039. HAL_RX_OFFSET(PHYRX_HE_SIG_B2_OFDMA_0,
  1040. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  1041. /*
  1042. * Not all "HE" fields can be updated from
  1043. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1044. * to populate rest of "HE" fields for MU OFDMA scenarios.
  1045. */
  1046. /* HE-data1 */
  1047. ppdu_info->rx_status.he_data1 |=
  1048. QDF_MON_STATUS_HE_MCS_KNOWN |
  1049. QDF_MON_STATUS_HE_DCM_KNOWN |
  1050. QDF_MON_STATUS_HE_CODING_KNOWN;
  1051. /* HE-data2 */
  1052. ppdu_info->rx_status.he_data2 |=
  1053. QDF_MON_STATUS_TXBF_KNOWN;
  1054. /* HE-data3 */
  1055. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1056. HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
  1057. ppdu_info->rx_status.mcs = value;
  1058. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1059. ppdu_info->rx_status.he_data3 |= value;
  1060. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1061. HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
  1062. he_dcm = value;
  1063. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1064. ppdu_info->rx_status.he_data3 |= value;
  1065. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1066. HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
  1067. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1068. ppdu_info->rx_status.he_data3 |= value;
  1069. /* HE-data4 */
  1070. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1071. HE_SIG_B2_OFDMA_INFO_0, STA_ID);
  1072. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1073. ppdu_info->rx_status.he_data4 |= value;
  1074. /* HE-data5 */
  1075. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1076. HE_SIG_B2_OFDMA_INFO_0, TXBF);
  1077. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1078. ppdu_info->rx_status.he_data5 |= value;
  1079. /* HE-data6 */
  1080. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1081. HE_SIG_B2_OFDMA_INFO_0, NSTS);
  1082. /* value n indicates n+1 spatial streams */
  1083. value++;
  1084. ppdu_info->rx_status.nss = value;
  1085. ppdu_info->rx_status.he_data6 |= value;
  1086. break;
  1087. }
  1088. case WIFIPHYRX_RSSI_LEGACY_E:
  1089. {
  1090. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1091. HAL_RX_OFFSET(PHYRX_RSSI_LEGACY_3,
  1092. RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS);
  1093. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1094. PHYRX_RSSI_LEGACY_35, RSSI_COMB);
  1095. ppdu_info->rx_status.bw = HAL_RX_GET(rx_tlv,
  1096. #if !defined(QCA_WIFI_QCA6290_11AX)
  1097. PHYRX_RSSI_LEGACY_35, RECEIVE_BANDWIDTH);
  1098. #else
  1099. PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
  1100. #endif
  1101. ppdu_info->rx_status.he_re = 0;
  1102. ppdu_info->rx_status.reception_type = HAL_RX_GET(rx_tlv,
  1103. PHYRX_RSSI_LEGACY_0, RECEPTION_TYPE);
  1104. value = HAL_RX_GET(rssi_info_tlv,
  1105. RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
  1106. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1107. "RSSI_PRI20_CHAIN0: %d\n", value);
  1108. value = HAL_RX_GET(rssi_info_tlv,
  1109. RECEIVE_RSSI_INFO_0, RSSI_EXT20_CHAIN0);
  1110. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1111. "RSSI_EXT20_CHAIN0: %d\n", value);
  1112. value = HAL_RX_GET(rssi_info_tlv,
  1113. RECEIVE_RSSI_INFO_0, RSSI_EXT40_LOW20_CHAIN0);
  1114. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1115. "RSSI_EXT40_LOW20_CHAIN0: %d\n", value);
  1116. value = HAL_RX_GET(rssi_info_tlv,
  1117. RECEIVE_RSSI_INFO_0, RSSI_EXT40_HIGH20_CHAIN0);
  1118. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1119. "RSSI_EXT40_HIGH20_CHAIN0: %d\n", value);
  1120. value = HAL_RX_GET(rssi_info_tlv,
  1121. RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW20_CHAIN0);
  1122. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1123. "RSSI_EXT80_LOW20_CHAIN0: %d\n", value);
  1124. value = HAL_RX_GET(rssi_info_tlv,
  1125. RECEIVE_RSSI_INFO_1, RSSI_EXT80_LOW_HIGH20_CHAIN0);
  1126. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1127. "RSSI_EXT80_LOW_HIGH20_CHAIN0: %d\n", value);
  1128. value = HAL_RX_GET(rssi_info_tlv,
  1129. RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH_LOW20_CHAIN0);
  1130. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1131. "RSSI_EXT80_HIGH_LOW20_CHAIN0: %d\n", value);
  1132. value = HAL_RX_GET(rssi_info_tlv,
  1133. RECEIVE_RSSI_INFO_1, RSSI_EXT80_HIGH20_CHAIN0);
  1134. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1135. "RSSI_EXT80_HIGH20_CHAIN0: %d\n", value);
  1136. break;
  1137. }
  1138. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  1139. hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr, ppdu_info);
  1140. break;
  1141. case WIFIRX_HEADER_E:
  1142. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1143. ppdu_info->msdu_info.payload_len = tlv_len;
  1144. break;
  1145. case WIFIRX_MPDU_START_E:
  1146. {
  1147. uint8_t *rx_mpdu_start =
  1148. (uint8_t *)rx_tlv + HAL_RX_OFFSET(RX_MPDU_START_0,
  1149. RX_MPDU_INFO_RX_MPDU_INFO_DETAILS);
  1150. uint32_t ppdu_id = HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0,
  1151. PHY_PPDU_ID);
  1152. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1153. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1154. ppdu_info->rx_status.ppdu_len =
  1155. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1156. MPDU_LENGTH);
  1157. } else {
  1158. ppdu_info->rx_status.ppdu_len +=
  1159. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1160. MPDU_LENGTH);
  1161. }
  1162. break;
  1163. }
  1164. case 0:
  1165. return HAL_TLV_STATUS_PPDU_DONE;
  1166. default:
  1167. unhandled = true;
  1168. break;
  1169. }
  1170. if (!unhandled)
  1171. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1172. "%s TLV type: %d, TLV len:%d %s",
  1173. __func__, tlv_tag, tlv_len,
  1174. unhandled == true ? "unhandled" : "");
  1175. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, rx_tlv, tlv_len);
  1176. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1177. }
  1178. static inline
  1179. uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc)
  1180. {
  1181. return HAL_RX_TLV32_HDR_SIZE;
  1182. }
  1183. static inline QDF_STATUS
  1184. hal_get_rx_status_done(uint8_t *rx_tlv)
  1185. {
  1186. uint32_t tlv_tag;
  1187. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  1188. if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E)
  1189. return QDF_STATUS_SUCCESS;
  1190. else
  1191. return QDF_STATUS_E_EMPTY;
  1192. }
  1193. static inline QDF_STATUS
  1194. hal_clear_rx_status_done(uint8_t *rx_tlv)
  1195. {
  1196. *(uint32_t *)rx_tlv = 0;
  1197. return QDF_STATUS_SUCCESS;
  1198. }
  1199. #endif