c3fae0027c
Added qcn6432 target header files based on E3R47 under qcn6432 to make fw-api project compatible to host. Change-Id: I3bdf6298281323f4f0fe75aed04db93cd698ee1f CRs-Fixed: 3463782
671 baris
29 KiB
C
671 baris
29 KiB
C
/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _TX_FES_STATUS_1K_BA_H_
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#define _TX_FES_STATUS_1K_BA_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34
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#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17
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struct tx_fes_status_1k_ba {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t ack_ba_status_type : 1, // [0:0]
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ba_type : 1, // [1:1]
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ba_tid : 4, // [5:2]
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unexpected_ack_or_ba : 1, // [6:6]
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response_timeout : 1, // [7:7]
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ack_frame_rssi : 8, // [15:8]
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ssn : 12, // [27:16]
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reserved_0b : 4; // [31:28]
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uint32_t sw_peer_id : 16, // [15:0]
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reserved_1a : 16; // [31:16]
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uint32_t ba_bitmap_31_0 : 32; // [31:0]
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uint32_t ba_bitmap_63_32 : 32; // [31:0]
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uint32_t ba_bitmap_95_64 : 32; // [31:0]
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uint32_t ba_bitmap_127_96 : 32; // [31:0]
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uint32_t ba_bitmap_159_128 : 32; // [31:0]
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uint32_t ba_bitmap_191_160 : 32; // [31:0]
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uint32_t ba_bitmap_223_192 : 32; // [31:0]
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uint32_t ba_bitmap_255_224 : 32; // [31:0]
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uint32_t ba_bitmap_287_256 : 32; // [31:0]
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uint32_t ba_bitmap_319_288 : 32; // [31:0]
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uint32_t ba_bitmap_351_320 : 32; // [31:0]
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uint32_t ba_bitmap_383_352 : 32; // [31:0]
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uint32_t ba_bitmap_415_384 : 32; // [31:0]
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uint32_t ba_bitmap_447_416 : 32; // [31:0]
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uint32_t ba_bitmap_479_448 : 32; // [31:0]
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uint32_t ba_bitmap_511_480 : 32; // [31:0]
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uint32_t ba_bitmap_543_512 : 32; // [31:0]
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uint32_t ba_bitmap_575_544 : 32; // [31:0]
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uint32_t ba_bitmap_607_576 : 32; // [31:0]
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uint32_t ba_bitmap_639_608 : 32; // [31:0]
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uint32_t ba_bitmap_671_640 : 32; // [31:0]
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uint32_t ba_bitmap_703_672 : 32; // [31:0]
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uint32_t ba_bitmap_735_704 : 32; // [31:0]
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uint32_t ba_bitmap_767_736 : 32; // [31:0]
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uint32_t ba_bitmap_799_768 : 32; // [31:0]
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uint32_t ba_bitmap_831_800 : 32; // [31:0]
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uint32_t ba_bitmap_863_832 : 32; // [31:0]
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uint32_t ba_bitmap_895_864 : 32; // [31:0]
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uint32_t ba_bitmap_927_896 : 32; // [31:0]
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uint32_t ba_bitmap_959_928 : 32; // [31:0]
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uint32_t ba_bitmap_991_960 : 32; // [31:0]
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uint32_t ba_bitmap_1023_992 : 32; // [31:0]
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#else
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uint32_t reserved_0b : 4, // [31:28]
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ssn : 12, // [27:16]
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ack_frame_rssi : 8, // [15:8]
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response_timeout : 1, // [7:7]
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unexpected_ack_or_ba : 1, // [6:6]
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ba_tid : 4, // [5:2]
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ba_type : 1, // [1:1]
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ack_ba_status_type : 1; // [0:0]
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uint32_t reserved_1a : 16, // [31:16]
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sw_peer_id : 16; // [15:0]
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uint32_t ba_bitmap_31_0 : 32; // [31:0]
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uint32_t ba_bitmap_63_32 : 32; // [31:0]
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uint32_t ba_bitmap_95_64 : 32; // [31:0]
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uint32_t ba_bitmap_127_96 : 32; // [31:0]
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uint32_t ba_bitmap_159_128 : 32; // [31:0]
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uint32_t ba_bitmap_191_160 : 32; // [31:0]
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uint32_t ba_bitmap_223_192 : 32; // [31:0]
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uint32_t ba_bitmap_255_224 : 32; // [31:0]
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uint32_t ba_bitmap_287_256 : 32; // [31:0]
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uint32_t ba_bitmap_319_288 : 32; // [31:0]
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uint32_t ba_bitmap_351_320 : 32; // [31:0]
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uint32_t ba_bitmap_383_352 : 32; // [31:0]
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uint32_t ba_bitmap_415_384 : 32; // [31:0]
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uint32_t ba_bitmap_447_416 : 32; // [31:0]
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uint32_t ba_bitmap_479_448 : 32; // [31:0]
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uint32_t ba_bitmap_511_480 : 32; // [31:0]
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uint32_t ba_bitmap_543_512 : 32; // [31:0]
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uint32_t ba_bitmap_575_544 : 32; // [31:0]
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uint32_t ba_bitmap_607_576 : 32; // [31:0]
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uint32_t ba_bitmap_639_608 : 32; // [31:0]
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uint32_t ba_bitmap_671_640 : 32; // [31:0]
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uint32_t ba_bitmap_703_672 : 32; // [31:0]
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uint32_t ba_bitmap_735_704 : 32; // [31:0]
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uint32_t ba_bitmap_767_736 : 32; // [31:0]
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uint32_t ba_bitmap_799_768 : 32; // [31:0]
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uint32_t ba_bitmap_831_800 : 32; // [31:0]
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uint32_t ba_bitmap_863_832 : 32; // [31:0]
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uint32_t ba_bitmap_895_864 : 32; // [31:0]
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uint32_t ba_bitmap_927_896 : 32; // [31:0]
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uint32_t ba_bitmap_959_928 : 32; // [31:0]
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uint32_t ba_bitmap_991_960 : 32; // [31:0]
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uint32_t ba_bitmap_1023_992 : 32; // [31:0]
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#endif
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};
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/* Description ACK_BA_STATUS_TYPE
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Consumer: SW
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Producer: RXPCU
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<enum 1 1K_BA_type> This TLV represents an BA reception.
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<legal 1>
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*/
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#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0
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#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0
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#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001
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/* Description BA_TYPE
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<enum 1 1K_BA_TYPE_bitmap>
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<legal 1>
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*/
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#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1
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#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1
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#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002
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/* Description BA_TID
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The TID field copied from the BA frame
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2
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#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5
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#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c
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/* Description UNEXPECTED_ACK_OR_BA
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Set when RXPCU received a BA for which there was no " RXPCU_USER_SETUP_EXT
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TLV' received.
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This can happen when a BA for unexpected TID is received.
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This message enables SW to still pass this BA information
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on to the right TQM queue.
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6
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#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6
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#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040
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/* Description RESPONSE_TIMEOUT
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When set, there was delay in RXPCU (likely due to AST fetch
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delay) that resulted in TXPCU not being able to send the
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RX_RESPONSE_REQUIRED_INFO TLV within a certain timeout
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from the falling edge of the frame. This status TLV is still
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generated but RXPCU will NOT have generated the RX_RESPONSE_REQUIRED
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TLV.
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7
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#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7
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#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080
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/* Description ACK_FRAME_RSSI
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RSSI of the received ACK, BA or M-BA frame.
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8
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#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15
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#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00
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/* Description SSN
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Consumer: TQM/FW
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Producer: SW/RXPCU
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Field only valid in case of the Ack_ba_status_type indicating:
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BA_type
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The starting Sequence number of the (B)ACK bitmap <legal
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all>
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*/
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#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_SSN_LSB 16
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#define TX_FES_STATUS_1K_BA_SSN_MSB 27
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#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000
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/* Description RESERVED_0B
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<legal 0>
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*/
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#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28
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#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31
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#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000
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/* Description SW_PEER_ID
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The sw_peer_id for which the bitmap is requested.
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SW could use this info to link this TLV back to the right
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TQM queue (if needed)
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32
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#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47
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#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000
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/* Description RESERVED_1A
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<legal 0>
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*/
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#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000
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#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48
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#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63
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#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000
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/* Description BA_BITMAP_31_0
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Consumer: TQM/FW
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Producer: SW/RXPCU
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Ba_bitmap_31_0
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff
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/* Description BA_BITMAP_63_32
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Consumer: TQM/FW
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Producer: SW/RXPCU
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Ba_bitmap_63_32
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000
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/* Description BA_BITMAP_95_64
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Consumer: TQM/FW
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Producer: SW/RXPCU
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Ba_bitmap_95_64
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff
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/* Description BA_BITMAP_127_96
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Consumer: TQM/FW
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Producer: SW/RXPCU
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Ba_bitmap_127_96
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000
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/* Description BA_BITMAP_159_128
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Consumer: TQM/FW
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Producer: SW/RXPCU
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Ba_bitmap_159_128
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff
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/* Description BA_BITMAP_191_160
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Consumer: TQM/FW
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Producer: SW/RXPCU
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Ba_bitmap_191_160
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000
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/* Description BA_BITMAP_223_192
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Consumer: TQM/FW
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Producer: SW/RXPCU
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Ba_bitmap_223_192
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff
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/* Description BA_BITMAP_255_224
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Consumer: TQM/FW
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Producer: SW/RXPCU
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Ba_bitmap_255_224
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000
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/* Description BA_BITMAP_287_256
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Ba_bitmap_287_256
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff
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/* Description BA_BITMAP_319_288
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Ba_bitmap_319_288
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000
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/* Description BA_BITMAP_351_320
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Ba_bitmap_351_320
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<legal all>
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*/
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff
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/* Description BA_BITMAP_383_352
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Ba_bitmap_383_352
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<legal all>
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|
*/
|
|
|
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63
|
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000
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|
|
|
|
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/* Description BA_BITMAP_415_384
|
|
|
|
Ba_bitmap_415_384
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038
|
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31
|
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#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_447_416
|
|
|
|
Ba_bitmap_447_416
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description BA_BITMAP_479_448
|
|
|
|
Ba_bitmap_479_448
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_511_480
|
|
|
|
Ba_bitmap_511_480
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description BA_BITMAP_543_512
|
|
|
|
Ba_bitmap_543_512
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_575_544
|
|
|
|
Ba_bitmap_575_544
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description BA_BITMAP_607_576
|
|
|
|
Ba_bitmap_607_576
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_639_608
|
|
|
|
Ba_bitmap_639_608
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description BA_BITMAP_671_640
|
|
|
|
Ba_bitmap_671_640
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_703_672
|
|
|
|
Ba_bitmap_703_672
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description BA_BITMAP_735_704
|
|
|
|
Ba_bitmap_735_704
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_767_736
|
|
|
|
Ba_bitmap_767_736
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description BA_BITMAP_799_768
|
|
|
|
Ba_bitmap_799_768
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_831_800
|
|
|
|
Ba_bitmap_831_800
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description BA_BITMAP_863_832
|
|
|
|
Ba_bitmap_863_832
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_895_864
|
|
|
|
Ba_bitmap_895_864
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description BA_BITMAP_927_896
|
|
|
|
Ba_bitmap_927_896
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_959_928
|
|
|
|
Ba_bitmap_959_928
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000
|
|
|
|
|
|
/* Description BA_BITMAP_991_960
|
|
|
|
Ba_bitmap_991_960
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff
|
|
|
|
|
|
/* Description BA_BITMAP_1023_992
|
|
|
|
Ba_bitmap_1023_992
|
|
<legal all>
|
|
*/
|
|
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63
|
|
#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000
|
|
|
|
|
|
|
|
#endif // TX_FES_STATUS_1K_BA
|