dp_tx.c 177 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "htt.h"
  20. #include "dp_htt.h"
  21. #include "hal_hw_headers.h"
  22. #include "dp_tx.h"
  23. #include "dp_tx_desc.h"
  24. #include "dp_peer.h"
  25. #include "dp_types.h"
  26. #include "hal_tx.h"
  27. #include "qdf_mem.h"
  28. #include "qdf_nbuf.h"
  29. #include "qdf_net_types.h"
  30. #include "qdf_module.h"
  31. #include <wlan_cfg.h>
  32. #include "dp_ipa.h"
  33. #if defined(MESH_MODE_SUPPORT) || defined(FEATURE_PERPKT_INFO)
  34. #include "if_meta_hdr.h"
  35. #endif
  36. #include "enet.h"
  37. #include "dp_internal.h"
  38. #ifdef ATH_SUPPORT_IQUE
  39. #include "dp_txrx_me.h"
  40. #endif
  41. #include "dp_hist.h"
  42. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  43. #include <wlan_dp_swlm.h>
  44. #endif
  45. #ifdef WIFI_MONITOR_SUPPORT
  46. #include <dp_mon.h>
  47. #endif
  48. #ifdef FEATURE_WDS
  49. #include "dp_txrx_wds.h"
  50. #endif
  51. #include "cdp_txrx_cmn_reg.h"
  52. #ifdef CONFIG_SAWF
  53. #include <dp_sawf.h>
  54. #endif
  55. /* Flag to skip CCE classify when mesh or tid override enabled */
  56. #define DP_TX_SKIP_CCE_CLASSIFY \
  57. (DP_TXRX_HLOS_TID_OVERRIDE_ENABLED | DP_TX_MESH_ENABLED)
  58. /* TODO Add support in TSO */
  59. #define DP_DESC_NUM_FRAG(x) 0
  60. /* disable TQM_BYPASS */
  61. #define TQM_BYPASS_WAR 0
  62. /* invalid peer id for reinject*/
  63. #define DP_INVALID_PEER 0XFFFE
  64. #define DP_RETRY_COUNT 7
  65. #ifdef WLAN_PEER_JITTER
  66. #define DP_AVG_JITTER_WEIGHT_DENOM 4
  67. #define DP_AVG_DELAY_WEIGHT_DENOM 3
  68. #endif
  69. #ifdef QCA_DP_TX_FW_METADATA_V2
  70. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  71. HTT_TX_TCL_METADATA_V2_PDEV_ID_SET(_var, _val)
  72. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  73. HTT_TX_TCL_METADATA_V2_VALID_HTT_SET(_var, _val)
  74. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  75. HTT_TX_TCL_METADATA_TYPE_V2_SET(_var, _val)
  76. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  77. HTT_TX_TCL_METADATA_V2_HOST_INSPECTED_SET(_var, _val)
  78. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  79. HTT_TX_TCL_METADATA_V2_PEER_ID_SET(_var, _val)
  80. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  81. HTT_TX_TCL_METADATA_V2_VDEV_ID_SET(_var, _val)
  82. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  83. HTT_TCL_METADATA_V2_TYPE_PEER_BASED
  84. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  85. HTT_TCL_METADATA_V2_TYPE_VDEV_BASED
  86. #else
  87. #define DP_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)\
  88. HTT_TX_TCL_METADATA_PDEV_ID_SET(_var, _val)
  89. #define DP_TX_TCL_METADATA_VALID_HTT_SET(_var, _val) \
  90. HTT_TX_TCL_METADATA_VALID_HTT_SET(_var, _val)
  91. #define DP_TX_TCL_METADATA_TYPE_SET(_var, _val) \
  92. HTT_TX_TCL_METADATA_TYPE_SET(_var, _val)
  93. #define DP_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val) \
  94. HTT_TX_TCL_METADATA_HOST_INSPECTED_SET(_var, _val)
  95. #define DP_TX_TCL_METADATA_PEER_ID_SET(_var, _val) \
  96. HTT_TX_TCL_METADATA_PEER_ID_SET(_var, _val)
  97. #define DP_TX_TCL_METADATA_VDEV_ID_SET(_var, _val) \
  98. HTT_TX_TCL_METADATA_VDEV_ID_SET(_var, _val)
  99. #define DP_TCL_METADATA_TYPE_PEER_BASED \
  100. HTT_TCL_METADATA_TYPE_PEER_BASED
  101. #define DP_TCL_METADATA_TYPE_VDEV_BASED \
  102. HTT_TCL_METADATA_TYPE_VDEV_BASED
  103. #endif
  104. /*mapping between hal encrypt type and cdp_sec_type*/
  105. uint8_t sec_type_map[MAX_CDP_SEC_TYPE] = {HAL_TX_ENCRYPT_TYPE_NO_CIPHER,
  106. HAL_TX_ENCRYPT_TYPE_WEP_128,
  107. HAL_TX_ENCRYPT_TYPE_WEP_104,
  108. HAL_TX_ENCRYPT_TYPE_WEP_40,
  109. HAL_TX_ENCRYPT_TYPE_TKIP_WITH_MIC,
  110. HAL_TX_ENCRYPT_TYPE_TKIP_NO_MIC,
  111. HAL_TX_ENCRYPT_TYPE_AES_CCMP_128,
  112. HAL_TX_ENCRYPT_TYPE_WAPI,
  113. HAL_TX_ENCRYPT_TYPE_AES_CCMP_256,
  114. HAL_TX_ENCRYPT_TYPE_AES_GCMP_128,
  115. HAL_TX_ENCRYPT_TYPE_AES_GCMP_256,
  116. HAL_TX_ENCRYPT_TYPE_WAPI_GCM_SM4};
  117. qdf_export_symbol(sec_type_map);
  118. #ifdef WLAN_FEATURE_DP_TX_DESC_HISTORY
  119. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  120. {
  121. enum dp_tx_event_type type;
  122. if (flags & DP_TX_DESC_FLAG_FLUSH)
  123. type = DP_TX_DESC_FLUSH;
  124. else if (flags & DP_TX_DESC_FLAG_TX_COMP_ERR)
  125. type = DP_TX_COMP_UNMAP_ERR;
  126. else if (flags & DP_TX_DESC_FLAG_COMPLETED_TX)
  127. type = DP_TX_COMP_UNMAP;
  128. else
  129. type = DP_TX_DESC_UNMAP;
  130. return type;
  131. }
  132. static inline void
  133. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  134. qdf_nbuf_t skb, uint32_t sw_cookie,
  135. enum dp_tx_event_type type)
  136. {
  137. struct dp_tx_tcl_history *tx_tcl_history = &soc->tx_tcl_history;
  138. struct dp_tx_comp_history *tx_comp_history = &soc->tx_comp_history;
  139. struct dp_tx_desc_event *entry;
  140. uint32_t idx;
  141. uint16_t slot;
  142. switch (type) {
  143. case DP_TX_COMP_UNMAP:
  144. case DP_TX_COMP_UNMAP_ERR:
  145. case DP_TX_COMP_MSDU_EXT:
  146. if (qdf_unlikely(!tx_comp_history->allocated))
  147. return;
  148. dp_get_frag_hist_next_atomic_idx(&tx_comp_history->index, &idx,
  149. &slot,
  150. DP_TX_COMP_HIST_SLOT_SHIFT,
  151. DP_TX_COMP_HIST_PER_SLOT_MAX,
  152. DP_TX_COMP_HISTORY_SIZE);
  153. entry = &tx_comp_history->entry[slot][idx];
  154. break;
  155. case DP_TX_DESC_MAP:
  156. case DP_TX_DESC_UNMAP:
  157. case DP_TX_DESC_COOKIE:
  158. case DP_TX_DESC_FLUSH:
  159. if (qdf_unlikely(!tx_tcl_history->allocated))
  160. return;
  161. dp_get_frag_hist_next_atomic_idx(&tx_tcl_history->index, &idx,
  162. &slot,
  163. DP_TX_TCL_HIST_SLOT_SHIFT,
  164. DP_TX_TCL_HIST_PER_SLOT_MAX,
  165. DP_TX_TCL_HISTORY_SIZE);
  166. entry = &tx_tcl_history->entry[slot][idx];
  167. break;
  168. default:
  169. dp_info_rl("Invalid dp_tx_event_type: %d", type);
  170. return;
  171. }
  172. entry->skb = skb;
  173. entry->paddr = paddr;
  174. entry->sw_cookie = sw_cookie;
  175. entry->type = type;
  176. entry->ts = qdf_get_log_timestamp();
  177. }
  178. static inline void
  179. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  180. struct qdf_tso_seg_elem_t *tso_seg,
  181. qdf_nbuf_t skb, uint32_t sw_cookie,
  182. enum dp_tx_event_type type)
  183. {
  184. int i;
  185. for (i = 1; i < tso_seg->seg.num_frags; i++) {
  186. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[i].paddr,
  187. skb, sw_cookie, type);
  188. }
  189. if (!tso_seg->next)
  190. dp_tx_desc_history_add(soc, tso_seg->seg.tso_frags[0].paddr,
  191. skb, 0xFFFFFFFF, type);
  192. }
  193. static inline void
  194. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  195. qdf_nbuf_t skb, uint32_t sw_cookie,
  196. enum dp_tx_event_type type)
  197. {
  198. struct qdf_tso_seg_elem_t *curr_seg = tso_info.tso_seg_list;
  199. uint32_t num_segs = tso_info.num_segs;
  200. while (num_segs) {
  201. dp_tx_tso_seg_history_add(soc, curr_seg, skb, sw_cookie, type);
  202. curr_seg = curr_seg->next;
  203. num_segs--;
  204. }
  205. }
  206. #else
  207. static inline enum dp_tx_event_type dp_tx_get_event_type(uint32_t flags)
  208. {
  209. return DP_TX_DESC_INVAL_EVT;
  210. }
  211. static inline void
  212. dp_tx_desc_history_add(struct dp_soc *soc, dma_addr_t paddr,
  213. qdf_nbuf_t skb, uint32_t sw_cookie,
  214. enum dp_tx_event_type type)
  215. {
  216. }
  217. static inline void
  218. dp_tx_tso_seg_history_add(struct dp_soc *soc,
  219. struct qdf_tso_seg_elem_t *tso_seg,
  220. qdf_nbuf_t skb, uint32_t sw_cookie,
  221. enum dp_tx_event_type type)
  222. {
  223. }
  224. static inline void
  225. dp_tx_tso_history_add(struct dp_soc *soc, struct qdf_tso_info_t tso_info,
  226. qdf_nbuf_t skb, uint32_t sw_cookie,
  227. enum dp_tx_event_type type)
  228. {
  229. }
  230. #endif /* WLAN_FEATURE_DP_TX_DESC_HISTORY */
  231. static int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc);
  232. /**
  233. * dp_is_tput_high() - Check if throughput is high
  234. *
  235. * @soc - core txrx main context
  236. *
  237. * The current function is based of the RTPM tput policy variable where RTPM is
  238. * avoided based on throughput.
  239. */
  240. static inline int dp_is_tput_high(struct dp_soc *soc)
  241. {
  242. return dp_get_rtpm_tput_policy_requirement(soc);
  243. }
  244. #if defined(FEATURE_TSO)
  245. /**
  246. * dp_tx_tso_unmap_segment() - Unmap TSO segment
  247. *
  248. * @soc - core txrx main context
  249. * @seg_desc - tso segment descriptor
  250. * @num_seg_desc - tso number segment descriptor
  251. */
  252. static void dp_tx_tso_unmap_segment(
  253. struct dp_soc *soc,
  254. struct qdf_tso_seg_elem_t *seg_desc,
  255. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  256. {
  257. TSO_DEBUG("%s: Unmap the tso segment", __func__);
  258. if (qdf_unlikely(!seg_desc)) {
  259. DP_TRACE(ERROR, "%s %d TSO desc is NULL!",
  260. __func__, __LINE__);
  261. qdf_assert(0);
  262. } else if (qdf_unlikely(!num_seg_desc)) {
  263. DP_TRACE(ERROR, "%s %d TSO num desc is NULL!",
  264. __func__, __LINE__);
  265. qdf_assert(0);
  266. } else {
  267. bool is_last_seg;
  268. /* no tso segment left to do dma unmap */
  269. if (num_seg_desc->num_seg.tso_cmn_num_seg < 1)
  270. return;
  271. is_last_seg = (num_seg_desc->num_seg.tso_cmn_num_seg == 1) ?
  272. true : false;
  273. qdf_nbuf_unmap_tso_segment(soc->osdev,
  274. seg_desc, is_last_seg);
  275. num_seg_desc->num_seg.tso_cmn_num_seg--;
  276. }
  277. }
  278. /**
  279. * dp_tx_tso_desc_release() - Release the tso segment and tso_cmn_num_seg
  280. * back to the freelist
  281. *
  282. * @soc - soc device handle
  283. * @tx_desc - Tx software descriptor
  284. */
  285. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  286. struct dp_tx_desc_s *tx_desc)
  287. {
  288. TSO_DEBUG("%s: Free the tso descriptor", __func__);
  289. if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_desc)) {
  290. dp_tx_err("SO desc is NULL!");
  291. qdf_assert(0);
  292. } else if (qdf_unlikely(!tx_desc->msdu_ext_desc->tso_num_desc)) {
  293. dp_tx_err("TSO num desc is NULL!");
  294. qdf_assert(0);
  295. } else {
  296. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  297. (struct qdf_tso_num_seg_elem_t *)tx_desc->
  298. msdu_ext_desc->tso_num_desc;
  299. /* Add the tso num segment into the free list */
  300. if (tso_num_desc->num_seg.tso_cmn_num_seg == 0) {
  301. dp_tso_num_seg_free(soc, tx_desc->pool_id,
  302. tx_desc->msdu_ext_desc->
  303. tso_num_desc);
  304. tx_desc->msdu_ext_desc->tso_num_desc = NULL;
  305. DP_STATS_INC(tx_desc->pdev, tso_stats.tso_comp, 1);
  306. }
  307. /* Add the tso segment into the free list*/
  308. dp_tx_tso_desc_free(soc,
  309. tx_desc->pool_id, tx_desc->msdu_ext_desc->
  310. tso_desc);
  311. tx_desc->msdu_ext_desc->tso_desc = NULL;
  312. }
  313. }
  314. #else
  315. static void dp_tx_tso_unmap_segment(
  316. struct dp_soc *soc,
  317. struct qdf_tso_seg_elem_t *seg_desc,
  318. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  319. {
  320. }
  321. static void dp_tx_tso_desc_release(struct dp_soc *soc,
  322. struct dp_tx_desc_s *tx_desc)
  323. {
  324. }
  325. #endif
  326. /**
  327. * dp_tx_desc_release() - Release Tx Descriptor
  328. * @tx_desc : Tx Descriptor
  329. * @desc_pool_id: Descriptor Pool ID
  330. *
  331. * Deallocate all resources attached to Tx descriptor and free the Tx
  332. * descriptor.
  333. *
  334. * Return:
  335. */
  336. void
  337. dp_tx_desc_release(struct dp_tx_desc_s *tx_desc, uint8_t desc_pool_id)
  338. {
  339. struct dp_pdev *pdev = tx_desc->pdev;
  340. struct dp_soc *soc;
  341. uint8_t comp_status = 0;
  342. qdf_assert(pdev);
  343. soc = pdev->soc;
  344. dp_tx_outstanding_dec(pdev);
  345. if (tx_desc->msdu_ext_desc) {
  346. if (tx_desc->frm_type == dp_tx_frm_tso)
  347. dp_tx_tso_desc_release(soc, tx_desc);
  348. if (tx_desc->flags & DP_TX_DESC_FLAG_ME)
  349. dp_tx_me_free_buf(tx_desc->pdev,
  350. tx_desc->msdu_ext_desc->me_buffer);
  351. dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
  352. }
  353. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
  354. qdf_atomic_dec(&soc->num_tx_exception);
  355. if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
  356. tx_desc->buffer_src)
  357. comp_status = hal_tx_comp_get_release_reason(&tx_desc->comp,
  358. soc->hal_soc);
  359. else
  360. comp_status = HAL_TX_COMP_RELEASE_REASON_FW;
  361. dp_tx_debug("Tx Completion Release desc %d status %d outstanding %d",
  362. tx_desc->id, comp_status,
  363. qdf_atomic_read(&pdev->num_tx_outstanding));
  364. dp_tx_desc_free(soc, tx_desc, desc_pool_id);
  365. return;
  366. }
  367. /**
  368. * dp_tx_htt_metadata_prepare() - Prepare HTT metadata for special frames
  369. * @vdev: DP vdev Handle
  370. * @nbuf: skb
  371. * @msdu_info: msdu_info required to create HTT metadata
  372. *
  373. * Prepares and fills HTT metadata in the frame pre-header for special frames
  374. * that should be transmitted using varying transmit parameters.
  375. * There are 2 VDEV modes that currently needs this special metadata -
  376. * 1) Mesh Mode
  377. * 2) DSRC Mode
  378. *
  379. * Return: HTT metadata size
  380. *
  381. */
  382. static uint8_t dp_tx_prepare_htt_metadata(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  383. struct dp_tx_msdu_info_s *msdu_info)
  384. {
  385. uint32_t *meta_data = msdu_info->meta_data;
  386. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  387. (struct htt_tx_msdu_desc_ext2_t *) meta_data;
  388. uint8_t htt_desc_size;
  389. /* Size rounded of multiple of 8 bytes */
  390. uint8_t htt_desc_size_aligned;
  391. uint8_t *hdr = NULL;
  392. /*
  393. * Metadata - HTT MSDU Extension header
  394. */
  395. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  396. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  397. if (vdev->mesh_vdev || msdu_info->is_tx_sniffer ||
  398. HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_KEY_FLAGS_GET(msdu_info->
  399. meta_data[0]) ||
  400. msdu_info->exception_fw) {
  401. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) <
  402. htt_desc_size_aligned)) {
  403. nbuf = qdf_nbuf_realloc_headroom(nbuf,
  404. htt_desc_size_aligned);
  405. if (!nbuf) {
  406. /*
  407. * qdf_nbuf_realloc_headroom won't do skb_clone
  408. * as skb_realloc_headroom does. so, no free is
  409. * needed here.
  410. */
  411. DP_STATS_INC(vdev,
  412. tx_i.dropped.headroom_insufficient,
  413. 1);
  414. qdf_print(" %s[%d] skb_realloc_headroom failed",
  415. __func__, __LINE__);
  416. return 0;
  417. }
  418. }
  419. /* Fill and add HTT metaheader */
  420. hdr = qdf_nbuf_push_head(nbuf, htt_desc_size_aligned);
  421. if (!hdr) {
  422. dp_tx_err("Error in filling HTT metadata");
  423. return 0;
  424. }
  425. qdf_mem_copy(hdr, desc_ext, htt_desc_size);
  426. } else if (vdev->opmode == wlan_op_mode_ocb) {
  427. /* Todo - Add support for DSRC */
  428. }
  429. return htt_desc_size_aligned;
  430. }
  431. /**
  432. * dp_tx_prepare_tso_ext_desc() - Prepare MSDU extension descriptor for TSO
  433. * @tso_seg: TSO segment to process
  434. * @ext_desc: Pointer to MSDU extension descriptor
  435. *
  436. * Return: void
  437. */
  438. #if defined(FEATURE_TSO)
  439. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  440. void *ext_desc)
  441. {
  442. uint8_t num_frag;
  443. uint32_t tso_flags;
  444. /*
  445. * Set tso_en, tcp_flags(NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN),
  446. * tcp_flag_mask
  447. *
  448. * Checksum enable flags are set in TCL descriptor and not in Extension
  449. * Descriptor (H/W ignores checksum_en flags in MSDU ext descriptor)
  450. */
  451. tso_flags = *(uint32_t *) &tso_seg->tso_flags;
  452. hal_tx_ext_desc_set_tso_flags(ext_desc, tso_flags);
  453. hal_tx_ext_desc_set_msdu_length(ext_desc, tso_seg->tso_flags.l2_len,
  454. tso_seg->tso_flags.ip_len);
  455. hal_tx_ext_desc_set_tcp_seq(ext_desc, tso_seg->tso_flags.tcp_seq_num);
  456. hal_tx_ext_desc_set_ip_id(ext_desc, tso_seg->tso_flags.ip_id);
  457. for (num_frag = 0; num_frag < tso_seg->num_frags; num_frag++) {
  458. uint32_t lo = 0;
  459. uint32_t hi = 0;
  460. qdf_assert_always((tso_seg->tso_frags[num_frag].paddr) &&
  461. (tso_seg->tso_frags[num_frag].length));
  462. qdf_dmaaddr_to_32s(
  463. tso_seg->tso_frags[num_frag].paddr, &lo, &hi);
  464. hal_tx_ext_desc_set_buffer(ext_desc, num_frag, lo, hi,
  465. tso_seg->tso_frags[num_frag].length);
  466. }
  467. return;
  468. }
  469. #else
  470. static void dp_tx_prepare_tso_ext_desc(struct qdf_tso_seg_t *tso_seg,
  471. void *ext_desc)
  472. {
  473. return;
  474. }
  475. #endif
  476. #if defined(FEATURE_TSO)
  477. /**
  478. * dp_tx_free_tso_seg_list() - Loop through the tso segments
  479. * allocated and free them
  480. *
  481. * @soc: soc handle
  482. * @free_seg: list of tso segments
  483. * @msdu_info: msdu descriptor
  484. *
  485. * Return - void
  486. */
  487. static void dp_tx_free_tso_seg_list(
  488. struct dp_soc *soc,
  489. struct qdf_tso_seg_elem_t *free_seg,
  490. struct dp_tx_msdu_info_s *msdu_info)
  491. {
  492. struct qdf_tso_seg_elem_t *next_seg;
  493. while (free_seg) {
  494. next_seg = free_seg->next;
  495. dp_tx_tso_desc_free(soc,
  496. msdu_info->tx_queue.desc_pool_id,
  497. free_seg);
  498. free_seg = next_seg;
  499. }
  500. }
  501. /**
  502. * dp_tx_free_tso_num_seg_list() - Loop through the tso num segments
  503. * allocated and free them
  504. *
  505. * @soc: soc handle
  506. * @free_num_seg: list of tso number segments
  507. * @msdu_info: msdu descriptor
  508. * Return - void
  509. */
  510. static void dp_tx_free_tso_num_seg_list(
  511. struct dp_soc *soc,
  512. struct qdf_tso_num_seg_elem_t *free_num_seg,
  513. struct dp_tx_msdu_info_s *msdu_info)
  514. {
  515. struct qdf_tso_num_seg_elem_t *next_num_seg;
  516. while (free_num_seg) {
  517. next_num_seg = free_num_seg->next;
  518. dp_tso_num_seg_free(soc,
  519. msdu_info->tx_queue.desc_pool_id,
  520. free_num_seg);
  521. free_num_seg = next_num_seg;
  522. }
  523. }
  524. /**
  525. * dp_tx_unmap_tso_seg_list() - Loop through the tso segments
  526. * do dma unmap for each segment
  527. *
  528. * @soc: soc handle
  529. * @free_seg: list of tso segments
  530. * @num_seg_desc: tso number segment descriptor
  531. *
  532. * Return - void
  533. */
  534. static void dp_tx_unmap_tso_seg_list(
  535. struct dp_soc *soc,
  536. struct qdf_tso_seg_elem_t *free_seg,
  537. struct qdf_tso_num_seg_elem_t *num_seg_desc)
  538. {
  539. struct qdf_tso_seg_elem_t *next_seg;
  540. if (qdf_unlikely(!num_seg_desc)) {
  541. DP_TRACE(ERROR, "TSO number seg desc is NULL!");
  542. return;
  543. }
  544. while (free_seg) {
  545. next_seg = free_seg->next;
  546. dp_tx_tso_unmap_segment(soc, free_seg, num_seg_desc);
  547. free_seg = next_seg;
  548. }
  549. }
  550. #ifdef FEATURE_TSO_STATS
  551. /**
  552. * dp_tso_get_stats_idx: Retrieve the tso packet id
  553. * @pdev - pdev handle
  554. *
  555. * Return: id
  556. */
  557. static uint32_t dp_tso_get_stats_idx(struct dp_pdev *pdev)
  558. {
  559. uint32_t stats_idx;
  560. stats_idx = (((uint32_t)qdf_atomic_inc_return(&pdev->tso_idx))
  561. % CDP_MAX_TSO_PACKETS);
  562. return stats_idx;
  563. }
  564. #else
  565. static int dp_tso_get_stats_idx(struct dp_pdev *pdev)
  566. {
  567. return 0;
  568. }
  569. #endif /* FEATURE_TSO_STATS */
  570. /**
  571. * dp_tx_free_remaining_tso_desc() - do dma unmap for tso segments if any,
  572. * free the tso segments descriptor and
  573. * tso num segments descriptor
  574. *
  575. * @soc: soc handle
  576. * @msdu_info: msdu descriptor
  577. * @tso_seg_unmap: flag to show if dma unmap is necessary
  578. *
  579. * Return - void
  580. */
  581. static void dp_tx_free_remaining_tso_desc(struct dp_soc *soc,
  582. struct dp_tx_msdu_info_s *msdu_info,
  583. bool tso_seg_unmap)
  584. {
  585. struct qdf_tso_info_t *tso_info = &msdu_info->u.tso_info;
  586. struct qdf_tso_seg_elem_t *free_seg = tso_info->tso_seg_list;
  587. struct qdf_tso_num_seg_elem_t *tso_num_desc =
  588. tso_info->tso_num_seg_list;
  589. /* do dma unmap for each segment */
  590. if (tso_seg_unmap)
  591. dp_tx_unmap_tso_seg_list(soc, free_seg, tso_num_desc);
  592. /* free all tso number segment descriptor though looks only have 1 */
  593. dp_tx_free_tso_num_seg_list(soc, tso_num_desc, msdu_info);
  594. /* free all tso segment descriptor */
  595. dp_tx_free_tso_seg_list(soc, free_seg, msdu_info);
  596. }
  597. /**
  598. * dp_tx_prepare_tso() - Given a jumbo msdu, prepare the TSO info
  599. * @vdev: virtual device handle
  600. * @msdu: network buffer
  601. * @msdu_info: meta data associated with the msdu
  602. *
  603. * Return: QDF_STATUS_SUCCESS success
  604. */
  605. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  606. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  607. {
  608. struct qdf_tso_seg_elem_t *tso_seg;
  609. int num_seg = qdf_nbuf_get_tso_num_seg(msdu);
  610. struct dp_soc *soc = vdev->pdev->soc;
  611. struct dp_pdev *pdev = vdev->pdev;
  612. struct qdf_tso_info_t *tso_info;
  613. struct qdf_tso_num_seg_elem_t *tso_num_seg;
  614. tso_info = &msdu_info->u.tso_info;
  615. tso_info->curr_seg = NULL;
  616. tso_info->tso_seg_list = NULL;
  617. tso_info->num_segs = num_seg;
  618. msdu_info->frm_type = dp_tx_frm_tso;
  619. tso_info->tso_num_seg_list = NULL;
  620. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  621. while (num_seg) {
  622. tso_seg = dp_tx_tso_desc_alloc(
  623. soc, msdu_info->tx_queue.desc_pool_id);
  624. if (tso_seg) {
  625. tso_seg->next = tso_info->tso_seg_list;
  626. tso_info->tso_seg_list = tso_seg;
  627. num_seg--;
  628. } else {
  629. dp_err_rl("Failed to alloc tso seg desc");
  630. DP_STATS_INC_PKT(vdev->pdev,
  631. tso_stats.tso_no_mem_dropped, 1,
  632. qdf_nbuf_len(msdu));
  633. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  634. return QDF_STATUS_E_NOMEM;
  635. }
  636. }
  637. TSO_DEBUG(" %s: num_seg: %d", __func__, num_seg);
  638. tso_num_seg = dp_tso_num_seg_alloc(soc,
  639. msdu_info->tx_queue.desc_pool_id);
  640. if (tso_num_seg) {
  641. tso_num_seg->next = tso_info->tso_num_seg_list;
  642. tso_info->tso_num_seg_list = tso_num_seg;
  643. } else {
  644. DP_TRACE(ERROR, "%s: Failed to alloc - Number of segs desc",
  645. __func__);
  646. dp_tx_free_remaining_tso_desc(soc, msdu_info, false);
  647. return QDF_STATUS_E_NOMEM;
  648. }
  649. msdu_info->num_seg =
  650. qdf_nbuf_get_tso_info(soc->osdev, msdu, tso_info);
  651. TSO_DEBUG(" %s: msdu_info->num_seg: %d", __func__,
  652. msdu_info->num_seg);
  653. if (!(msdu_info->num_seg)) {
  654. /*
  655. * Free allocated TSO seg desc and number seg desc,
  656. * do unmap for segments if dma map has done.
  657. */
  658. DP_TRACE(ERROR, "%s: Failed to get tso info", __func__);
  659. dp_tx_free_remaining_tso_desc(soc, msdu_info, true);
  660. return QDF_STATUS_E_INVAL;
  661. }
  662. dp_tx_tso_history_add(soc, msdu_info->u.tso_info,
  663. msdu, 0, DP_TX_DESC_MAP);
  664. tso_info->curr_seg = tso_info->tso_seg_list;
  665. tso_info->msdu_stats_idx = dp_tso_get_stats_idx(pdev);
  666. dp_tso_packet_update(pdev, tso_info->msdu_stats_idx,
  667. msdu, msdu_info->num_seg);
  668. dp_tso_segment_stats_update(pdev, tso_info->tso_seg_list,
  669. tso_info->msdu_stats_idx);
  670. dp_stats_tso_segment_histogram_update(pdev, msdu_info->num_seg);
  671. return QDF_STATUS_SUCCESS;
  672. }
  673. #else
  674. static QDF_STATUS dp_tx_prepare_tso(struct dp_vdev *vdev,
  675. qdf_nbuf_t msdu, struct dp_tx_msdu_info_s *msdu_info)
  676. {
  677. return QDF_STATUS_E_NOMEM;
  678. }
  679. #endif
  680. QDF_COMPILE_TIME_ASSERT(dp_tx_htt_metadata_len_check,
  681. (DP_TX_MSDU_INFO_META_DATA_DWORDS * 4 >=
  682. sizeof(struct htt_tx_msdu_desc_ext2_t)));
  683. /**
  684. * dp_tx_prepare_ext_desc() - Allocate and prepare MSDU extension descriptor
  685. * @vdev: DP Vdev handle
  686. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  687. * @desc_pool_id: Descriptor Pool ID
  688. *
  689. * Return:
  690. */
  691. static
  692. struct dp_tx_ext_desc_elem_s *dp_tx_prepare_ext_desc(struct dp_vdev *vdev,
  693. struct dp_tx_msdu_info_s *msdu_info, uint8_t desc_pool_id)
  694. {
  695. uint8_t i;
  696. uint8_t cached_ext_desc[HAL_TX_EXT_DESC_WITH_META_DATA];
  697. struct dp_tx_seg_info_s *seg_info;
  698. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  699. struct dp_soc *soc = vdev->pdev->soc;
  700. /* Allocate an extension descriptor */
  701. msdu_ext_desc = dp_tx_ext_desc_alloc(soc, desc_pool_id);
  702. qdf_mem_zero(&cached_ext_desc[0], HAL_TX_EXT_DESC_WITH_META_DATA);
  703. if (!msdu_ext_desc) {
  704. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  705. return NULL;
  706. }
  707. if (msdu_info->exception_fw &&
  708. qdf_unlikely(vdev->mesh_vdev)) {
  709. qdf_mem_copy(&cached_ext_desc[HAL_TX_EXTENSION_DESC_LEN_BYTES],
  710. &msdu_info->meta_data[0],
  711. sizeof(struct htt_tx_msdu_desc_ext2_t));
  712. qdf_atomic_inc(&soc->num_tx_exception);
  713. msdu_ext_desc->flags |= DP_TX_EXT_DESC_FLAG_METADATA_VALID;
  714. }
  715. switch (msdu_info->frm_type) {
  716. case dp_tx_frm_sg:
  717. case dp_tx_frm_me:
  718. case dp_tx_frm_raw:
  719. seg_info = msdu_info->u.sg_info.curr_seg;
  720. /* Update the buffer pointers in MSDU Extension Descriptor */
  721. for (i = 0; i < seg_info->frag_cnt; i++) {
  722. hal_tx_ext_desc_set_buffer(&cached_ext_desc[0], i,
  723. seg_info->frags[i].paddr_lo,
  724. seg_info->frags[i].paddr_hi,
  725. seg_info->frags[i].len);
  726. }
  727. break;
  728. case dp_tx_frm_tso:
  729. dp_tx_prepare_tso_ext_desc(&msdu_info->u.tso_info.curr_seg->seg,
  730. &cached_ext_desc[0]);
  731. break;
  732. default:
  733. break;
  734. }
  735. QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  736. cached_ext_desc, HAL_TX_EXT_DESC_WITH_META_DATA);
  737. hal_tx_ext_desc_sync(&cached_ext_desc[0],
  738. msdu_ext_desc->vaddr);
  739. return msdu_ext_desc;
  740. }
  741. /**
  742. * dp_tx_trace_pkt() - Trace TX packet at DP layer
  743. *
  744. * @skb: skb to be traced
  745. * @msdu_id: msdu_id of the packet
  746. * @vdev_id: vdev_id of the packet
  747. *
  748. * Return: None
  749. */
  750. #ifdef DP_DISABLE_TX_PKT_TRACE
  751. static void dp_tx_trace_pkt(struct dp_soc *soc,
  752. qdf_nbuf_t skb, uint16_t msdu_id,
  753. uint8_t vdev_id)
  754. {
  755. }
  756. #else
  757. static void dp_tx_trace_pkt(struct dp_soc *soc,
  758. qdf_nbuf_t skb, uint16_t msdu_id,
  759. uint8_t vdev_id)
  760. {
  761. if (dp_is_tput_high(soc))
  762. return;
  763. QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK;
  764. QDF_NBUF_CB_TX_DP_TRACE(skb) = 1;
  765. DPTRACE(qdf_dp_trace_ptr(skb,
  766. QDF_DP_TRACE_LI_DP_TX_PACKET_PTR_RECORD,
  767. QDF_TRACE_DEFAULT_PDEV_ID,
  768. qdf_nbuf_data_addr(skb),
  769. sizeof(qdf_nbuf_data(skb)),
  770. msdu_id, vdev_id, 0));
  771. qdf_dp_trace_log_pkt(vdev_id, skb, QDF_TX, QDF_TRACE_DEFAULT_PDEV_ID);
  772. DPTRACE(qdf_dp_trace_data_pkt(skb, QDF_TRACE_DEFAULT_PDEV_ID,
  773. QDF_DP_TRACE_LI_DP_TX_PACKET_RECORD,
  774. msdu_id, QDF_TX));
  775. }
  776. #endif
  777. #ifdef WLAN_DP_FEATURE_MARK_ICMP_REQ_TO_FW
  778. /**
  779. * dp_tx_is_nbuf_marked_exception() - Check if the packet has been marked as
  780. * exception by the upper layer (OS_IF)
  781. * @soc: DP soc handle
  782. * @nbuf: packet to be transmitted
  783. *
  784. * Returns: 1 if the packet is marked as exception,
  785. * 0, if the packet is not marked as exception.
  786. */
  787. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  788. qdf_nbuf_t nbuf)
  789. {
  790. return QDF_NBUF_CB_TX_PACKET_TO_FW(nbuf);
  791. }
  792. #else
  793. static inline int dp_tx_is_nbuf_marked_exception(struct dp_soc *soc,
  794. qdf_nbuf_t nbuf)
  795. {
  796. return 0;
  797. }
  798. #endif
  799. #ifdef DP_TRAFFIC_END_INDICATION
  800. /**
  801. * dp_tx_get_traffic_end_indication_pkt() - Allocate and prepare packet to send
  802. * as indication to fw to inform that
  803. * data stream has ended
  804. * @vdev: DP vdev handle
  805. * @nbuf: original buffer from network stack
  806. *
  807. * Return: NULL on failure,
  808. * nbuf on success
  809. */
  810. static inline qdf_nbuf_t
  811. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  812. qdf_nbuf_t nbuf)
  813. {
  814. /* Packet length should be enough to copy upto L3 header */
  815. uint8_t end_nbuf_len = 64;
  816. uint8_t htt_desc_size_aligned;
  817. uint8_t htt_desc_size;
  818. qdf_nbuf_t end_nbuf;
  819. if (qdf_unlikely(QDF_NBUF_CB_GET_PACKET_TYPE(nbuf) ==
  820. QDF_NBUF_CB_PACKET_TYPE_END_INDICATION)) {
  821. htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext2_t);
  822. htt_desc_size_aligned = (htt_desc_size + 7) & ~0x7;
  823. end_nbuf = qdf_nbuf_queue_remove(&vdev->end_ind_pkt_q);
  824. if (!end_nbuf) {
  825. end_nbuf = qdf_nbuf_alloc(NULL,
  826. (htt_desc_size_aligned +
  827. end_nbuf_len),
  828. htt_desc_size_aligned,
  829. 8, false);
  830. if (!end_nbuf) {
  831. dp_err("Packet allocation failed");
  832. goto out;
  833. }
  834. } else {
  835. qdf_nbuf_reset(end_nbuf, htt_desc_size_aligned, 8);
  836. }
  837. qdf_mem_copy(qdf_nbuf_data(end_nbuf), qdf_nbuf_data(nbuf),
  838. end_nbuf_len);
  839. qdf_nbuf_set_pktlen(end_nbuf, end_nbuf_len);
  840. return end_nbuf;
  841. }
  842. out:
  843. return NULL;
  844. }
  845. /**
  846. * dp_tx_send_traffic_end_indication_pkt() - Send indication packet to FW
  847. * via exception path.
  848. * @vdev: DP vdev handle
  849. * @end_nbuf: skb to send as indication
  850. * @msdu_info: msdu_info of original nbuf
  851. * @peer_id: peer id
  852. *
  853. * Return: None
  854. */
  855. static inline void
  856. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  857. qdf_nbuf_t end_nbuf,
  858. struct dp_tx_msdu_info_s *msdu_info,
  859. uint16_t peer_id)
  860. {
  861. struct dp_tx_msdu_info_s e_msdu_info = {0};
  862. qdf_nbuf_t nbuf;
  863. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  864. (struct htt_tx_msdu_desc_ext2_t *)(e_msdu_info.meta_data);
  865. e_msdu_info.tx_queue = msdu_info->tx_queue;
  866. e_msdu_info.tid = msdu_info->tid;
  867. e_msdu_info.exception_fw = 1;
  868. desc_ext->host_tx_desc_pool = 1;
  869. desc_ext->traffic_end_indication = 1;
  870. nbuf = dp_tx_send_msdu_single(vdev, end_nbuf, &e_msdu_info,
  871. peer_id, NULL);
  872. if (nbuf) {
  873. dp_err("Traffic end indication packet tx failed");
  874. qdf_nbuf_free(nbuf);
  875. }
  876. }
  877. /**
  878. * dp_tx_traffic_end_indication_set_desc_flag() - Set tx descriptor flag to
  879. * mark it traffic end indication
  880. * packet.
  881. * @tx_desc: Tx descriptor pointer
  882. * @msdu_info: msdu_info structure pointer
  883. *
  884. * Return: None
  885. */
  886. static inline void
  887. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  888. struct dp_tx_msdu_info_s *msdu_info)
  889. {
  890. struct htt_tx_msdu_desc_ext2_t *desc_ext =
  891. (struct htt_tx_msdu_desc_ext2_t *)(msdu_info->meta_data);
  892. if (qdf_unlikely(desc_ext->traffic_end_indication))
  893. tx_desc->flags |= DP_TX_DESC_FLAG_TRAFFIC_END_IND;
  894. }
  895. /**
  896. * dp_tx_traffic_end_indication_enq_ind_pkt() - Enqueue the packet instead of
  897. * freeing which are associated
  898. * with traffic end indication
  899. * flagged descriptor.
  900. * @soc: dp soc handle
  901. * @desc: Tx descriptor pointer
  902. * @nbuf: buffer pointer
  903. *
  904. * Return: True if packet gets enqueued else false
  905. */
  906. static bool
  907. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  908. struct dp_tx_desc_s *desc,
  909. qdf_nbuf_t nbuf)
  910. {
  911. struct dp_vdev *vdev = NULL;
  912. if (qdf_unlikely((desc->flags &
  913. DP_TX_DESC_FLAG_TRAFFIC_END_IND) != 0)) {
  914. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  915. DP_MOD_ID_TX_COMP);
  916. if (vdev) {
  917. qdf_nbuf_queue_add(&vdev->end_ind_pkt_q, nbuf);
  918. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_COMP);
  919. return true;
  920. }
  921. }
  922. return false;
  923. }
  924. /**
  925. * dp_tx_traffic_end_indication_is_enabled() - get the feature
  926. * enable/disable status
  927. * @vdev: dp vdev handle
  928. *
  929. * Return: True if feature is enable else false
  930. */
  931. static inline bool
  932. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  933. {
  934. return qdf_unlikely(vdev->traffic_end_ind_en);
  935. }
  936. static inline qdf_nbuf_t
  937. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  938. struct dp_tx_msdu_info_s *msdu_info,
  939. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  940. {
  941. if (dp_tx_traffic_end_indication_is_enabled(vdev))
  942. end_nbuf = dp_tx_get_traffic_end_indication_pkt(vdev, nbuf);
  943. nbuf = dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  944. if (qdf_unlikely(end_nbuf))
  945. dp_tx_send_traffic_end_indication_pkt(vdev, end_nbuf,
  946. msdu_info, peer_id);
  947. return nbuf;
  948. }
  949. #else
  950. static inline qdf_nbuf_t
  951. dp_tx_get_traffic_end_indication_pkt(struct dp_vdev *vdev,
  952. qdf_nbuf_t nbuf)
  953. {
  954. return NULL;
  955. }
  956. static inline void
  957. dp_tx_send_traffic_end_indication_pkt(struct dp_vdev *vdev,
  958. qdf_nbuf_t end_nbuf,
  959. struct dp_tx_msdu_info_s *msdu_info,
  960. uint16_t peer_id)
  961. {}
  962. static inline void
  963. dp_tx_traffic_end_indication_set_desc_flag(struct dp_tx_desc_s *tx_desc,
  964. struct dp_tx_msdu_info_s *msdu_info)
  965. {}
  966. static inline bool
  967. dp_tx_traffic_end_indication_enq_ind_pkt(struct dp_soc *soc,
  968. struct dp_tx_desc_s *desc,
  969. qdf_nbuf_t nbuf)
  970. {
  971. return false;
  972. }
  973. static inline bool
  974. dp_tx_traffic_end_indication_is_enabled(struct dp_vdev *vdev)
  975. {
  976. return false;
  977. }
  978. static inline qdf_nbuf_t
  979. dp_tx_send_msdu_single_wrapper(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  980. struct dp_tx_msdu_info_s *msdu_info,
  981. uint16_t peer_id, qdf_nbuf_t end_nbuf)
  982. {
  983. return dp_tx_send_msdu_single(vdev, nbuf, msdu_info, peer_id, NULL);
  984. }
  985. #endif
  986. #if defined(QCA_SUPPORT_WDS_EXTENDED)
  987. static bool
  988. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  989. struct cdp_tx_exception_metadata *tx_exc_metadata)
  990. {
  991. if (soc->features.wds_ext_ast_override_enable &&
  992. tx_exc_metadata && tx_exc_metadata->is_wds_extended)
  993. return true;
  994. return false;
  995. }
  996. #else
  997. static bool
  998. dp_tx_is_wds_ast_override_en(struct dp_soc *soc,
  999. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1000. {
  1001. return false;
  1002. }
  1003. #endif
  1004. /**
  1005. * dp_tx_desc_prepare_single - Allocate and prepare Tx descriptor
  1006. * @vdev: DP vdev handle
  1007. * @nbuf: skb
  1008. * @desc_pool_id: Descriptor pool ID
  1009. * @meta_data: Metadata to the fw
  1010. * @tx_exc_metadata: Handle that holds exception path metadata
  1011. * Allocate and prepare Tx descriptor with msdu information.
  1012. *
  1013. * Return: Pointer to Tx Descriptor on success,
  1014. * NULL on failure
  1015. */
  1016. static
  1017. struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
  1018. qdf_nbuf_t nbuf, uint8_t desc_pool_id,
  1019. struct dp_tx_msdu_info_s *msdu_info,
  1020. struct cdp_tx_exception_metadata *tx_exc_metadata)
  1021. {
  1022. uint8_t align_pad;
  1023. uint8_t is_exception = 0;
  1024. uint8_t htt_hdr_size;
  1025. struct dp_tx_desc_s *tx_desc;
  1026. struct dp_pdev *pdev = vdev->pdev;
  1027. struct dp_soc *soc = pdev->soc;
  1028. if (dp_tx_limit_check(vdev))
  1029. return NULL;
  1030. /* Allocate software Tx descriptor */
  1031. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1032. if (qdf_unlikely(!tx_desc)) {
  1033. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1034. DP_STATS_INC(vdev, tx_i.dropped.desc_na_exc_alloc_fail.num, 1);
  1035. return NULL;
  1036. }
  1037. dp_tx_outstanding_inc(pdev);
  1038. /* Initialize the SW tx descriptor */
  1039. tx_desc->nbuf = nbuf;
  1040. tx_desc->frm_type = dp_tx_frm_std;
  1041. tx_desc->tx_encap_type = ((tx_exc_metadata &&
  1042. (tx_exc_metadata->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE)) ?
  1043. tx_exc_metadata->tx_encap_type : vdev->tx_encap_type);
  1044. tx_desc->vdev_id = vdev->vdev_id;
  1045. tx_desc->pdev = pdev;
  1046. tx_desc->msdu_ext_desc = NULL;
  1047. tx_desc->pkt_offset = 0;
  1048. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1049. tx_desc->shinfo_addr = skb_end_pointer(nbuf);
  1050. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1051. if (qdf_unlikely(vdev->multipass_en)) {
  1052. if (!dp_tx_multipass_process(soc, vdev, nbuf, msdu_info))
  1053. goto failure;
  1054. }
  1055. /* Packets marked by upper layer (OS-IF) to be sent to FW */
  1056. if (dp_tx_is_nbuf_marked_exception(soc, nbuf))
  1057. is_exception = 1;
  1058. /* for BE chipsets if wds extension was enbled will not mark FW
  1059. * in desc will mark ast index based search for ast index.
  1060. */
  1061. if (dp_tx_is_wds_ast_override_en(soc, tx_exc_metadata))
  1062. return tx_desc;
  1063. /*
  1064. * For special modes (vdev_type == ocb or mesh), data frames should be
  1065. * transmitted using varying transmit parameters (tx spec) which include
  1066. * transmit rate, power, priority, channel, channel bandwidth , nss etc.
  1067. * These are filled in HTT MSDU descriptor and sent in frame pre-header.
  1068. * These frames are sent as exception packets to firmware.
  1069. *
  1070. * HW requirement is that metadata should always point to a
  1071. * 8-byte aligned address. So we add alignment pad to start of buffer.
  1072. * HTT Metadata should be ensured to be multiple of 8-bytes,
  1073. * to get 8-byte aligned start address along with align_pad added
  1074. *
  1075. * |-----------------------------|
  1076. * | |
  1077. * |-----------------------------| <-----Buffer Pointer Address given
  1078. * | | ^ in HW descriptor (aligned)
  1079. * | HTT Metadata | |
  1080. * | | |
  1081. * | | | Packet Offset given in descriptor
  1082. * | | |
  1083. * |-----------------------------| |
  1084. * | Alignment Pad | v
  1085. * |-----------------------------| <----- Actual buffer start address
  1086. * | SKB Data | (Unaligned)
  1087. * | |
  1088. * | |
  1089. * | |
  1090. * | |
  1091. * | |
  1092. * |-----------------------------|
  1093. */
  1094. if (qdf_unlikely((msdu_info->exception_fw)) ||
  1095. (vdev->opmode == wlan_op_mode_ocb) ||
  1096. (tx_exc_metadata &&
  1097. tx_exc_metadata->is_tx_sniffer)) {
  1098. align_pad = ((unsigned long) qdf_nbuf_data(nbuf)) & 0x7;
  1099. if (qdf_unlikely(qdf_nbuf_headroom(nbuf) < align_pad)) {
  1100. DP_STATS_INC(vdev,
  1101. tx_i.dropped.headroom_insufficient, 1);
  1102. goto failure;
  1103. }
  1104. if (qdf_nbuf_push_head(nbuf, align_pad) == NULL) {
  1105. dp_tx_err("qdf_nbuf_push_head failed");
  1106. goto failure;
  1107. }
  1108. htt_hdr_size = dp_tx_prepare_htt_metadata(vdev, nbuf,
  1109. msdu_info);
  1110. if (htt_hdr_size == 0)
  1111. goto failure;
  1112. tx_desc->length = qdf_nbuf_headlen(nbuf);
  1113. tx_desc->pkt_offset = align_pad + htt_hdr_size;
  1114. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1115. dp_tx_traffic_end_indication_set_desc_flag(tx_desc,
  1116. msdu_info);
  1117. is_exception = 1;
  1118. tx_desc->length -= tx_desc->pkt_offset;
  1119. }
  1120. #if !TQM_BYPASS_WAR
  1121. if (is_exception || tx_exc_metadata)
  1122. #endif
  1123. {
  1124. /* Temporary WAR due to TQM VP issues */
  1125. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1126. qdf_atomic_inc(&soc->num_tx_exception);
  1127. }
  1128. return tx_desc;
  1129. failure:
  1130. dp_tx_desc_release(tx_desc, desc_pool_id);
  1131. return NULL;
  1132. }
  1133. /**
  1134. * dp_tx_prepare_desc() - Allocate and prepare Tx descriptor for multisegment frame
  1135. * @vdev: DP vdev handle
  1136. * @nbuf: skb
  1137. * @msdu_info: Info to be setup in MSDU descriptor and MSDU extension descriptor
  1138. * @desc_pool_id : Descriptor Pool ID
  1139. *
  1140. * Allocate and prepare Tx descriptor with msdu and fragment descritor
  1141. * information. For frames with fragments, allocate and prepare
  1142. * an MSDU extension descriptor
  1143. *
  1144. * Return: Pointer to Tx Descriptor on success,
  1145. * NULL on failure
  1146. */
  1147. static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
  1148. qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info,
  1149. uint8_t desc_pool_id)
  1150. {
  1151. struct dp_tx_desc_s *tx_desc;
  1152. struct dp_tx_ext_desc_elem_s *msdu_ext_desc;
  1153. struct dp_pdev *pdev = vdev->pdev;
  1154. struct dp_soc *soc = pdev->soc;
  1155. if (dp_tx_limit_check(vdev))
  1156. return NULL;
  1157. /* Allocate software Tx descriptor */
  1158. tx_desc = dp_tx_desc_alloc(soc, desc_pool_id);
  1159. if (!tx_desc) {
  1160. DP_STATS_INC(vdev, tx_i.dropped.desc_na.num, 1);
  1161. return NULL;
  1162. }
  1163. dp_tx_tso_seg_history_add(soc, msdu_info->u.tso_info.curr_seg,
  1164. nbuf, tx_desc->id, DP_TX_DESC_COOKIE);
  1165. dp_tx_outstanding_inc(pdev);
  1166. /* Initialize the SW tx descriptor */
  1167. tx_desc->nbuf = nbuf;
  1168. tx_desc->frm_type = msdu_info->frm_type;
  1169. tx_desc->tx_encap_type = vdev->tx_encap_type;
  1170. tx_desc->vdev_id = vdev->vdev_id;
  1171. tx_desc->pdev = pdev;
  1172. tx_desc->pkt_offset = 0;
  1173. dp_tx_trace_pkt(soc, nbuf, tx_desc->id, vdev->vdev_id);
  1174. /* Handle scattered frames - TSO/SG/ME */
  1175. /* Allocate and prepare an extension descriptor for scattered frames */
  1176. msdu_ext_desc = dp_tx_prepare_ext_desc(vdev, msdu_info, desc_pool_id);
  1177. if (!msdu_ext_desc) {
  1178. dp_tx_info("Tx Extension Descriptor Alloc Fail");
  1179. goto failure;
  1180. }
  1181. #if TQM_BYPASS_WAR
  1182. /* Temporary WAR due to TQM VP issues */
  1183. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1184. qdf_atomic_inc(&soc->num_tx_exception);
  1185. #endif
  1186. if (qdf_unlikely(msdu_info->exception_fw))
  1187. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  1188. tx_desc->msdu_ext_desc = msdu_ext_desc;
  1189. tx_desc->flags |= DP_TX_DESC_FLAG_FRAG;
  1190. msdu_ext_desc->tso_desc = msdu_info->u.tso_info.curr_seg;
  1191. msdu_ext_desc->tso_num_desc = msdu_info->u.tso_info.tso_num_seg_list;
  1192. tx_desc->dma_addr = msdu_ext_desc->paddr;
  1193. if (msdu_ext_desc->flags & DP_TX_EXT_DESC_FLAG_METADATA_VALID)
  1194. tx_desc->length = HAL_TX_EXT_DESC_WITH_META_DATA;
  1195. else
  1196. tx_desc->length = HAL_TX_EXTENSION_DESC_LEN_BYTES;
  1197. return tx_desc;
  1198. failure:
  1199. dp_tx_desc_release(tx_desc, desc_pool_id);
  1200. return NULL;
  1201. }
  1202. /**
  1203. * dp_tx_prepare_raw() - Prepare RAW packet TX
  1204. * @vdev: DP vdev handle
  1205. * @nbuf: buffer pointer
  1206. * @seg_info: Pointer to Segment info Descriptor to be prepared
  1207. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension
  1208. * descriptor
  1209. *
  1210. * Return:
  1211. */
  1212. static qdf_nbuf_t dp_tx_prepare_raw(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1213. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  1214. {
  1215. qdf_nbuf_t curr_nbuf = NULL;
  1216. uint16_t total_len = 0;
  1217. qdf_dma_addr_t paddr;
  1218. int32_t i;
  1219. int32_t mapped_buf_num = 0;
  1220. struct dp_tx_sg_info_s *sg_info = &msdu_info->u.sg_info;
  1221. qdf_dot3_qosframe_t *qos_wh = (qdf_dot3_qosframe_t *) nbuf->data;
  1222. DP_STATS_INC_PKT(vdev, tx_i.raw.raw_pkt, 1, qdf_nbuf_len(nbuf));
  1223. /* Continue only if frames are of DATA type */
  1224. if (!DP_FRAME_IS_DATA(qos_wh)) {
  1225. DP_STATS_INC(vdev, tx_i.raw.invalid_raw_pkt_datatype, 1);
  1226. dp_tx_debug("Pkt. recd is of not data type");
  1227. goto error;
  1228. }
  1229. /* SWAR for HW: Enable WEP bit in the AMSDU frames for RAW mode */
  1230. if (vdev->raw_mode_war &&
  1231. (qos_wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) &&
  1232. (qos_wh->i_qos[0] & IEEE80211_QOS_AMSDU))
  1233. qos_wh->i_fc[1] |= IEEE80211_FC1_WEP;
  1234. for (curr_nbuf = nbuf, i = 0; curr_nbuf;
  1235. curr_nbuf = qdf_nbuf_next(curr_nbuf), i++) {
  1236. /*
  1237. * Number of nbuf's must not exceed the size of the frags
  1238. * array in seg_info.
  1239. */
  1240. if (i >= DP_TX_MAX_NUM_FRAGS) {
  1241. dp_err_rl("nbuf cnt exceeds the max number of segs");
  1242. DP_STATS_INC(vdev, tx_i.raw.num_frags_overflow_err, 1);
  1243. goto error;
  1244. }
  1245. if (QDF_STATUS_SUCCESS !=
  1246. qdf_nbuf_map_nbytes_single(vdev->osdev,
  1247. curr_nbuf,
  1248. QDF_DMA_TO_DEVICE,
  1249. curr_nbuf->len)) {
  1250. dp_tx_err("%s dma map error ", __func__);
  1251. DP_STATS_INC(vdev, tx_i.raw.dma_map_error, 1);
  1252. goto error;
  1253. }
  1254. /* Update the count of mapped nbuf's */
  1255. mapped_buf_num++;
  1256. paddr = qdf_nbuf_get_frag_paddr(curr_nbuf, 0);
  1257. seg_info->frags[i].paddr_lo = paddr;
  1258. seg_info->frags[i].paddr_hi = ((uint64_t)paddr >> 32);
  1259. seg_info->frags[i].len = qdf_nbuf_len(curr_nbuf);
  1260. seg_info->frags[i].vaddr = (void *) curr_nbuf;
  1261. total_len += qdf_nbuf_len(curr_nbuf);
  1262. }
  1263. seg_info->frag_cnt = i;
  1264. seg_info->total_len = total_len;
  1265. seg_info->next = NULL;
  1266. sg_info->curr_seg = seg_info;
  1267. msdu_info->frm_type = dp_tx_frm_raw;
  1268. msdu_info->num_seg = 1;
  1269. return nbuf;
  1270. error:
  1271. i = 0;
  1272. while (nbuf) {
  1273. curr_nbuf = nbuf;
  1274. if (i < mapped_buf_num) {
  1275. qdf_nbuf_unmap_nbytes_single(vdev->osdev, curr_nbuf,
  1276. QDF_DMA_TO_DEVICE,
  1277. curr_nbuf->len);
  1278. i++;
  1279. }
  1280. nbuf = qdf_nbuf_next(nbuf);
  1281. qdf_nbuf_free(curr_nbuf);
  1282. }
  1283. return NULL;
  1284. }
  1285. /**
  1286. * dp_tx_raw_prepare_unset() - unmap the chain of nbufs belonging to RAW frame.
  1287. * @soc: DP soc handle
  1288. * @nbuf: Buffer pointer
  1289. *
  1290. * unmap the chain of nbufs that belong to this RAW frame.
  1291. *
  1292. * Return: None
  1293. */
  1294. static void dp_tx_raw_prepare_unset(struct dp_soc *soc,
  1295. qdf_nbuf_t nbuf)
  1296. {
  1297. qdf_nbuf_t cur_nbuf = nbuf;
  1298. do {
  1299. qdf_nbuf_unmap_nbytes_single(soc->osdev, cur_nbuf,
  1300. QDF_DMA_TO_DEVICE,
  1301. cur_nbuf->len);
  1302. cur_nbuf = qdf_nbuf_next(cur_nbuf);
  1303. } while (cur_nbuf);
  1304. }
  1305. #ifdef VDEV_PEER_PROTOCOL_COUNT
  1306. void dp_vdev_peer_stats_update_protocol_cnt_tx(struct dp_vdev *vdev_hdl,
  1307. qdf_nbuf_t nbuf)
  1308. {
  1309. qdf_nbuf_t nbuf_local;
  1310. struct dp_vdev *vdev_local = vdev_hdl;
  1311. do {
  1312. if (qdf_likely(!((vdev_local)->peer_protocol_count_track)))
  1313. break;
  1314. nbuf_local = nbuf;
  1315. if (qdf_unlikely(((vdev_local)->tx_encap_type) ==
  1316. htt_cmn_pkt_type_raw))
  1317. break;
  1318. else if (qdf_unlikely(qdf_nbuf_is_nonlinear((nbuf_local))))
  1319. break;
  1320. else if (qdf_nbuf_is_tso((nbuf_local)))
  1321. break;
  1322. dp_vdev_peer_stats_update_protocol_cnt((vdev_local),
  1323. (nbuf_local),
  1324. NULL, 1, 0);
  1325. } while (0);
  1326. }
  1327. #endif
  1328. #ifdef WLAN_DP_FEATURE_SW_LATENCY_MGR
  1329. /**
  1330. * dp_tx_update_stats() - Update soc level tx stats
  1331. * @soc: DP soc handle
  1332. * @tx_desc: TX descriptor reference
  1333. * @ring_id: TCL ring id
  1334. *
  1335. * Returns: none
  1336. */
  1337. void dp_tx_update_stats(struct dp_soc *soc,
  1338. struct dp_tx_desc_s *tx_desc,
  1339. uint8_t ring_id)
  1340. {
  1341. uint32_t stats_len = 0;
  1342. if (tx_desc->frm_type == dp_tx_frm_tso)
  1343. stats_len = tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1344. else
  1345. stats_len = qdf_nbuf_len(tx_desc->nbuf);
  1346. DP_STATS_INC_PKT(soc, tx.egress[ring_id], 1, stats_len);
  1347. }
  1348. int
  1349. dp_tx_attempt_coalescing(struct dp_soc *soc, struct dp_vdev *vdev,
  1350. struct dp_tx_desc_s *tx_desc,
  1351. uint8_t tid,
  1352. struct dp_tx_msdu_info_s *msdu_info,
  1353. uint8_t ring_id)
  1354. {
  1355. struct dp_swlm *swlm = &soc->swlm;
  1356. union swlm_data swlm_query_data;
  1357. struct dp_swlm_tcl_data tcl_data;
  1358. QDF_STATUS status;
  1359. int ret;
  1360. if (!swlm->is_enabled)
  1361. return msdu_info->skip_hp_update;
  1362. tcl_data.nbuf = tx_desc->nbuf;
  1363. tcl_data.tid = tid;
  1364. tcl_data.ring_id = ring_id;
  1365. if (tx_desc->frm_type == dp_tx_frm_tso) {
  1366. tcl_data.pkt_len =
  1367. tx_desc->msdu_ext_desc->tso_desc->seg.total_len;
  1368. } else {
  1369. tcl_data.pkt_len = qdf_nbuf_len(tx_desc->nbuf);
  1370. }
  1371. tcl_data.num_ll_connections = vdev->num_latency_critical_conn;
  1372. swlm_query_data.tcl_data = &tcl_data;
  1373. status = dp_swlm_tcl_pre_check(soc, &tcl_data);
  1374. if (QDF_IS_STATUS_ERROR(status)) {
  1375. dp_swlm_tcl_reset_session_data(soc, ring_id);
  1376. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1377. return 0;
  1378. }
  1379. ret = dp_swlm_query_policy(soc, TCL_DATA, swlm_query_data);
  1380. if (ret) {
  1381. DP_STATS_INC(swlm, tcl[ring_id].coalesce_success, 1);
  1382. } else {
  1383. DP_STATS_INC(swlm, tcl[ring_id].coalesce_fail, 1);
  1384. }
  1385. return ret;
  1386. }
  1387. void
  1388. dp_tx_ring_access_end(struct dp_soc *soc, hal_ring_handle_t hal_ring_hdl,
  1389. int coalesce)
  1390. {
  1391. if (coalesce)
  1392. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1393. else
  1394. dp_tx_hal_ring_access_end(soc, hal_ring_hdl);
  1395. }
  1396. static inline void
  1397. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1398. {
  1399. if (((i + 1) < msdu_info->num_seg))
  1400. msdu_info->skip_hp_update = 1;
  1401. else
  1402. msdu_info->skip_hp_update = 0;
  1403. }
  1404. static inline void
  1405. dp_flush_tcp_hp(struct dp_soc *soc, uint8_t ring_id)
  1406. {
  1407. hal_ring_handle_t hal_ring_hdl =
  1408. dp_tx_get_hal_ring_hdl(soc, ring_id);
  1409. if (dp_tx_hal_ring_access_start(soc, hal_ring_hdl)) {
  1410. dp_err("Fillmore: SRNG access start failed");
  1411. return;
  1412. }
  1413. dp_tx_ring_access_end_wrapper(soc, hal_ring_hdl, 0);
  1414. }
  1415. static inline void
  1416. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1417. QDF_STATUS status,
  1418. struct dp_tx_msdu_info_s *msdu_info)
  1419. {
  1420. if (QDF_IS_STATUS_ERROR(status) && !msdu_info->skip_hp_update) {
  1421. dp_flush_tcp_hp(soc,
  1422. (msdu_info->tx_queue.ring_id & DP_TX_QUEUE_MASK));
  1423. }
  1424. }
  1425. #else
  1426. static inline void
  1427. dp_tx_is_hp_update_required(uint32_t i, struct dp_tx_msdu_info_s *msdu_info)
  1428. {
  1429. }
  1430. static inline void
  1431. dp_tx_check_and_flush_hp(struct dp_soc *soc,
  1432. QDF_STATUS status,
  1433. struct dp_tx_msdu_info_s *msdu_info)
  1434. {
  1435. }
  1436. #endif
  1437. #ifdef FEATURE_RUNTIME_PM
  1438. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1439. {
  1440. int ret;
  1441. ret = qdf_atomic_read(&soc->rtpm_high_tput_flag) &&
  1442. (hif_rtpm_get_state() <= HIF_RTPM_STATE_ON);
  1443. return ret;
  1444. }
  1445. /**
  1446. * dp_tx_ring_access_end_wrapper() - Wrapper for ring access end
  1447. * @soc: Datapath soc handle
  1448. * @hal_ring_hdl: HAL ring handle
  1449. * @coalesce: Coalesce the current write or not
  1450. *
  1451. * Wrapper for HAL ring access end for data transmission for
  1452. * FEATURE_RUNTIME_PM
  1453. *
  1454. * Returns: none
  1455. */
  1456. void
  1457. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1458. hal_ring_handle_t hal_ring_hdl,
  1459. int coalesce)
  1460. {
  1461. int ret;
  1462. /*
  1463. * Avoid runtime get and put APIs under high throughput scenarios.
  1464. */
  1465. if (dp_get_rtpm_tput_policy_requirement(soc)) {
  1466. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1467. return;
  1468. }
  1469. ret = hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_DP);
  1470. if (QDF_IS_STATUS_SUCCESS(ret)) {
  1471. if (hif_system_pm_state_check(soc->hif_handle)) {
  1472. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1473. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1474. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1475. } else {
  1476. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1477. }
  1478. hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_DP);
  1479. } else {
  1480. dp_runtime_get(soc);
  1481. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1482. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1483. qdf_atomic_inc(&soc->tx_pending_rtpm);
  1484. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1485. dp_runtime_put(soc);
  1486. }
  1487. }
  1488. #else
  1489. #ifdef DP_POWER_SAVE
  1490. void
  1491. dp_tx_ring_access_end_wrapper(struct dp_soc *soc,
  1492. hal_ring_handle_t hal_ring_hdl,
  1493. int coalesce)
  1494. {
  1495. if (hif_system_pm_state_check(soc->hif_handle)) {
  1496. dp_tx_hal_ring_access_end_reap(soc, hal_ring_hdl);
  1497. hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
  1498. hal_srng_inc_flush_cnt(hal_ring_hdl);
  1499. } else {
  1500. dp_tx_ring_access_end(soc, hal_ring_hdl, coalesce);
  1501. }
  1502. }
  1503. #endif
  1504. static inline int dp_get_rtpm_tput_policy_requirement(struct dp_soc *soc)
  1505. {
  1506. return 0;
  1507. }
  1508. #endif
  1509. /**
  1510. * dp_tx_get_tid() - Obtain TID to be used for this frame
  1511. * @vdev: DP vdev handle
  1512. * @nbuf: skb
  1513. *
  1514. * Extract the DSCP or PCP information from frame and map into TID value.
  1515. *
  1516. * Return: void
  1517. */
  1518. static void dp_tx_get_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1519. struct dp_tx_msdu_info_s *msdu_info)
  1520. {
  1521. uint8_t tos = 0, dscp_tid_override = 0;
  1522. uint8_t *hdr_ptr, *L3datap;
  1523. uint8_t is_mcast = 0;
  1524. qdf_ether_header_t *eh = NULL;
  1525. qdf_ethervlan_header_t *evh = NULL;
  1526. uint16_t ether_type;
  1527. qdf_llc_t *llcHdr;
  1528. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  1529. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1530. if (qdf_likely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1531. eh = (qdf_ether_header_t *)nbuf->data;
  1532. hdr_ptr = (uint8_t *)(eh->ether_dhost);
  1533. L3datap = hdr_ptr + sizeof(qdf_ether_header_t);
  1534. } else {
  1535. qdf_dot3_qosframe_t *qos_wh =
  1536. (qdf_dot3_qosframe_t *) nbuf->data;
  1537. msdu_info->tid = qos_wh->i_fc[0] & DP_FC0_SUBTYPE_QOS ?
  1538. qos_wh->i_qos[0] & DP_QOS_TID : 0;
  1539. return;
  1540. }
  1541. is_mcast = DP_FRAME_IS_MULTICAST(hdr_ptr);
  1542. ether_type = eh->ether_type;
  1543. llcHdr = (qdf_llc_t *)(nbuf->data + sizeof(qdf_ether_header_t));
  1544. /*
  1545. * Check if packet is dot3 or eth2 type.
  1546. */
  1547. if (DP_FRAME_IS_LLC(ether_type) && DP_FRAME_IS_SNAP(llcHdr)) {
  1548. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE +
  1549. sizeof(*llcHdr));
  1550. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1551. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t) +
  1552. sizeof(*llcHdr);
  1553. ether_type = (uint16_t)*(nbuf->data + 2*QDF_MAC_ADDR_SIZE
  1554. + sizeof(*llcHdr) +
  1555. sizeof(qdf_net_vlanhdr_t));
  1556. } else {
  1557. L3datap = hdr_ptr + sizeof(qdf_ether_header_t) +
  1558. sizeof(*llcHdr);
  1559. }
  1560. } else {
  1561. if (ether_type == htons(ETHERTYPE_VLAN)) {
  1562. evh = (qdf_ethervlan_header_t *) eh;
  1563. ether_type = evh->ether_type;
  1564. L3datap = hdr_ptr + sizeof(qdf_ethervlan_header_t);
  1565. }
  1566. }
  1567. /*
  1568. * Find priority from IP TOS DSCP field
  1569. */
  1570. if (qdf_nbuf_is_ipv4_pkt(nbuf)) {
  1571. qdf_net_iphdr_t *ip = (qdf_net_iphdr_t *) L3datap;
  1572. if (qdf_nbuf_is_ipv4_dhcp_pkt(nbuf)) {
  1573. /* Only for unicast frames */
  1574. if (!is_mcast) {
  1575. /* send it on VO queue */
  1576. msdu_info->tid = DP_VO_TID;
  1577. }
  1578. } else {
  1579. /*
  1580. * IP frame: exclude ECN bits 0-1 and map DSCP bits 2-7
  1581. * from TOS byte.
  1582. */
  1583. tos = ip->ip_tos;
  1584. dscp_tid_override = 1;
  1585. }
  1586. } else if (qdf_nbuf_is_ipv6_pkt(nbuf)) {
  1587. /* TODO
  1588. * use flowlabel
  1589. *igmpmld cases to be handled in phase 2
  1590. */
  1591. unsigned long ver_pri_flowlabel;
  1592. unsigned long pri;
  1593. ver_pri_flowlabel = *(unsigned long *) L3datap;
  1594. pri = (ntohl(ver_pri_flowlabel) & IPV6_FLOWINFO_PRIORITY) >>
  1595. DP_IPV6_PRIORITY_SHIFT;
  1596. tos = pri;
  1597. dscp_tid_override = 1;
  1598. } else if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf))
  1599. msdu_info->tid = DP_VO_TID;
  1600. else if (qdf_nbuf_is_ipv4_arp_pkt(nbuf)) {
  1601. /* Only for unicast frames */
  1602. if (!is_mcast) {
  1603. /* send ucast arp on VO queue */
  1604. msdu_info->tid = DP_VO_TID;
  1605. }
  1606. }
  1607. /*
  1608. * Assign all MCAST packets to BE
  1609. */
  1610. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  1611. if (is_mcast) {
  1612. tos = 0;
  1613. dscp_tid_override = 1;
  1614. }
  1615. }
  1616. if (dscp_tid_override == 1) {
  1617. tos = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  1618. msdu_info->tid = pdev->dscp_tid_map[vdev->dscp_tid_map_id][tos];
  1619. }
  1620. if (msdu_info->tid >= CDP_MAX_DATA_TIDS)
  1621. msdu_info->tid = CDP_MAX_DATA_TIDS - 1;
  1622. return;
  1623. }
  1624. /**
  1625. * dp_tx_classify_tid() - Obtain TID to be used for this frame
  1626. * @vdev: DP vdev handle
  1627. * @nbuf: skb
  1628. *
  1629. * Software based TID classification is required when more than 2 DSCP-TID
  1630. * mapping tables are needed.
  1631. * Hardware supports 2 DSCP-TID mapping tables for HKv1 and 48 for HKv2.
  1632. *
  1633. * Return: void
  1634. */
  1635. static inline void dp_tx_classify_tid(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  1636. struct dp_tx_msdu_info_s *msdu_info)
  1637. {
  1638. DP_TX_TID_OVERRIDE(msdu_info, nbuf);
  1639. /*
  1640. * skip_sw_tid_classification flag will set in below cases-
  1641. * 1. vdev->dscp_tid_map_id < pdev->soc->num_hw_dscp_tid_map
  1642. * 2. hlos_tid_override enabled for vdev
  1643. * 3. mesh mode enabled for vdev
  1644. */
  1645. if (qdf_likely(vdev->skip_sw_tid_classification)) {
  1646. /* Update tid in msdu_info from skb priority */
  1647. if (qdf_unlikely(vdev->skip_sw_tid_classification
  1648. & DP_TXRX_HLOS_TID_OVERRIDE_ENABLED)) {
  1649. uint32_t tid = qdf_nbuf_get_priority(nbuf);
  1650. if (tid == DP_TX_INVALID_QOS_TAG)
  1651. return;
  1652. msdu_info->tid = tid;
  1653. return;
  1654. }
  1655. return;
  1656. }
  1657. dp_tx_get_tid(vdev, nbuf, msdu_info);
  1658. }
  1659. #ifdef FEATURE_WLAN_TDLS
  1660. /**
  1661. * dp_tx_update_tdls_flags() - Update descriptor flags for TDLS frame
  1662. * @soc: datapath SOC
  1663. * @vdev: datapath vdev
  1664. * @tx_desc: TX descriptor
  1665. *
  1666. * Return: None
  1667. */
  1668. static void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1669. struct dp_vdev *vdev,
  1670. struct dp_tx_desc_s *tx_desc)
  1671. {
  1672. if (vdev) {
  1673. if (vdev->is_tdls_frame) {
  1674. tx_desc->flags |= DP_TX_DESC_FLAG_TDLS_FRAME;
  1675. vdev->is_tdls_frame = false;
  1676. }
  1677. }
  1678. }
  1679. static uint8_t dp_htt_tx_comp_get_status(struct dp_soc *soc, char *htt_desc)
  1680. {
  1681. uint8_t tx_status = HTT_TX_FW2WBM_TX_STATUS_MAX;
  1682. switch (soc->arch_id) {
  1683. case CDP_ARCH_TYPE_LI:
  1684. tx_status = HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(htt_desc[0]);
  1685. break;
  1686. case CDP_ARCH_TYPE_BE:
  1687. tx_status = HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(htt_desc[0]);
  1688. break;
  1689. default:
  1690. dp_err("Incorrect CDP_ARCH %d", soc->arch_id);
  1691. QDF_BUG(0);
  1692. }
  1693. return tx_status;
  1694. }
  1695. /**
  1696. * dp_non_std_htt_tx_comp_free_buff() - Free the non std tx packet buffer
  1697. * @soc: dp_soc handle
  1698. * @tx_desc: TX descriptor
  1699. * @vdev: datapath vdev handle
  1700. *
  1701. * Return: None
  1702. */
  1703. static void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1704. struct dp_tx_desc_s *tx_desc)
  1705. {
  1706. uint8_t tx_status = 0;
  1707. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  1708. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1709. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id,
  1710. DP_MOD_ID_TDLS);
  1711. if (qdf_unlikely(!vdev)) {
  1712. dp_err_rl("vdev is null!");
  1713. goto error;
  1714. }
  1715. hal_tx_comp_get_htt_desc(&tx_desc->comp, htt_tx_status);
  1716. tx_status = dp_htt_tx_comp_get_status(soc, htt_tx_status);
  1717. dp_debug("vdev_id: %d tx_status: %d", tx_desc->vdev_id, tx_status);
  1718. if (vdev->tx_non_std_data_callback.func) {
  1719. qdf_nbuf_set_next(nbuf, NULL);
  1720. vdev->tx_non_std_data_callback.func(
  1721. vdev->tx_non_std_data_callback.ctxt,
  1722. nbuf, tx_status);
  1723. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1724. return;
  1725. } else {
  1726. dp_err_rl("callback func is null");
  1727. }
  1728. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  1729. error:
  1730. qdf_nbuf_unmap_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE);
  1731. qdf_nbuf_free(nbuf);
  1732. }
  1733. /**
  1734. * dp_tx_msdu_single_map() - do nbuf map
  1735. * @vdev: DP vdev handle
  1736. * @tx_desc: DP TX descriptor pointer
  1737. * @nbuf: skb pointer
  1738. *
  1739. * For TDLS frame, use qdf_nbuf_map_single() to align with the unmap
  1740. * operation done in other component.
  1741. *
  1742. * Return: QDF_STATUS
  1743. */
  1744. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1745. struct dp_tx_desc_s *tx_desc,
  1746. qdf_nbuf_t nbuf)
  1747. {
  1748. if (qdf_likely(!(tx_desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME)))
  1749. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1750. nbuf,
  1751. QDF_DMA_TO_DEVICE,
  1752. nbuf->len);
  1753. else
  1754. return qdf_nbuf_map_single(vdev->osdev, nbuf,
  1755. QDF_DMA_TO_DEVICE);
  1756. }
  1757. #else
  1758. static inline void dp_tx_update_tdls_flags(struct dp_soc *soc,
  1759. struct dp_vdev *vdev,
  1760. struct dp_tx_desc_s *tx_desc)
  1761. {
  1762. }
  1763. static inline void dp_non_std_htt_tx_comp_free_buff(struct dp_soc *soc,
  1764. struct dp_tx_desc_s *tx_desc)
  1765. {
  1766. }
  1767. static inline QDF_STATUS dp_tx_msdu_single_map(struct dp_vdev *vdev,
  1768. struct dp_tx_desc_s *tx_desc,
  1769. qdf_nbuf_t nbuf)
  1770. {
  1771. return qdf_nbuf_map_nbytes_single(vdev->osdev,
  1772. nbuf,
  1773. QDF_DMA_TO_DEVICE,
  1774. nbuf->len);
  1775. }
  1776. #endif
  1777. static inline
  1778. qdf_dma_addr_t dp_tx_nbuf_map_regular(struct dp_vdev *vdev,
  1779. struct dp_tx_desc_s *tx_desc,
  1780. qdf_nbuf_t nbuf)
  1781. {
  1782. QDF_STATUS ret = QDF_STATUS_E_FAILURE;
  1783. ret = dp_tx_msdu_single_map(vdev, tx_desc, nbuf);
  1784. if (qdf_unlikely(QDF_IS_STATUS_ERROR(ret)))
  1785. return 0;
  1786. return qdf_nbuf_mapped_paddr_get(nbuf);
  1787. }
  1788. static inline
  1789. void dp_tx_nbuf_unmap_regular(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1790. {
  1791. qdf_nbuf_unmap_nbytes_single_paddr(soc->osdev,
  1792. desc->nbuf,
  1793. desc->dma_addr,
  1794. QDF_DMA_TO_DEVICE,
  1795. desc->length);
  1796. }
  1797. #ifdef QCA_DP_TX_RMNET_OPTIMIZATION
  1798. static inline bool
  1799. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1800. {
  1801. struct net_device *ingress_dev;
  1802. skb_frag_t *frag;
  1803. uint16_t buf_len = 0;
  1804. uint16_t linear_data_len = 0;
  1805. uint8_t *payload_addr = NULL;
  1806. ingress_dev = dev_get_by_index(dev_net(nbuf->dev), nbuf->skb_iif);
  1807. if ((ingress_dev->priv_flags & IFF_PHONY_HEADROOM)) {
  1808. dev_put(ingress_dev);
  1809. frag = &(skb_shinfo(nbuf)->frags[0]);
  1810. buf_len = skb_frag_size(frag);
  1811. payload_addr = (uint8_t *)skb_frag_address(frag);
  1812. linear_data_len = skb_headlen(nbuf);
  1813. buf_len += linear_data_len;
  1814. payload_addr = payload_addr - linear_data_len;
  1815. memcpy(payload_addr, nbuf->data, linear_data_len);
  1816. msdu_info->frm_type = dp_tx_frm_rmnet;
  1817. msdu_info->buf_len = buf_len;
  1818. msdu_info->payload_addr = payload_addr;
  1819. return true;
  1820. }
  1821. dev_put(ingress_dev);
  1822. return false;
  1823. }
  1824. static inline
  1825. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1826. struct dp_tx_desc_s *tx_desc)
  1827. {
  1828. qdf_dma_addr_t paddr;
  1829. paddr = (qdf_dma_addr_t)qdf_mem_virt_to_phys(msdu_info->payload_addr);
  1830. tx_desc->length = msdu_info->buf_len;
  1831. qdf_nbuf_dma_clean_range((void *)msdu_info->payload_addr,
  1832. (void *)(msdu_info->payload_addr +
  1833. msdu_info->buf_len));
  1834. tx_desc->flags |= DP_TX_DESC_FLAG_RMNET;
  1835. return paddr;
  1836. }
  1837. #else
  1838. static inline bool
  1839. is_nbuf_frm_rmnet(qdf_nbuf_t nbuf, struct dp_tx_msdu_info_s *msdu_info)
  1840. {
  1841. return false;
  1842. }
  1843. static inline
  1844. qdf_dma_addr_t dp_tx_rmnet_nbuf_map(struct dp_tx_msdu_info_s *msdu_info,
  1845. struct dp_tx_desc_s *tx_desc)
  1846. {
  1847. return 0;
  1848. }
  1849. #endif
  1850. #if defined(QCA_DP_TX_NBUF_NO_MAP_UNMAP) && !defined(BUILD_X86)
  1851. static inline
  1852. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1853. struct dp_tx_desc_s *tx_desc,
  1854. qdf_nbuf_t nbuf)
  1855. {
  1856. if (qdf_likely(tx_desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  1857. qdf_nbuf_dma_clean_range((void *)nbuf->data,
  1858. (void *)(nbuf->data + nbuf->len));
  1859. return (qdf_dma_addr_t)qdf_mem_virt_to_phys(nbuf->data);
  1860. } else {
  1861. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1862. }
  1863. }
  1864. static inline
  1865. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1866. struct dp_tx_desc_s *desc)
  1867. {
  1868. if (qdf_unlikely(!(desc->flags &
  1869. (DP_TX_DESC_FLAG_SIMPLE | DP_TX_DESC_FLAG_RMNET))))
  1870. return dp_tx_nbuf_unmap_regular(soc, desc);
  1871. }
  1872. #else
  1873. static inline
  1874. qdf_dma_addr_t dp_tx_nbuf_map(struct dp_vdev *vdev,
  1875. struct dp_tx_desc_s *tx_desc,
  1876. qdf_nbuf_t nbuf)
  1877. {
  1878. return dp_tx_nbuf_map_regular(vdev, tx_desc, nbuf);
  1879. }
  1880. static inline
  1881. void dp_tx_nbuf_unmap(struct dp_soc *soc,
  1882. struct dp_tx_desc_s *desc)
  1883. {
  1884. return dp_tx_nbuf_unmap_regular(soc, desc);
  1885. }
  1886. #endif
  1887. #if defined(WLAN_TX_PKT_CAPTURE_ENH) || defined(FEATURE_PERPKT_INFO)
  1888. static inline
  1889. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1890. {
  1891. dp_tx_nbuf_unmap(soc, desc);
  1892. desc->flags |= DP_TX_DESC_FLAG_UNMAP_DONE;
  1893. }
  1894. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1895. {
  1896. if (qdf_likely(!(desc->flags & DP_TX_DESC_FLAG_UNMAP_DONE)))
  1897. dp_tx_nbuf_unmap(soc, desc);
  1898. }
  1899. #else
  1900. static inline
  1901. void dp_tx_enh_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1902. {
  1903. }
  1904. static inline void dp_tx_unmap(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  1905. {
  1906. dp_tx_nbuf_unmap(soc, desc);
  1907. }
  1908. #endif
  1909. #ifdef MESH_MODE_SUPPORT
  1910. /**
  1911. * dp_tx_update_mesh_flags() - Update descriptor flags for mesh VAP
  1912. * @soc: datapath SOC
  1913. * @vdev: datapath vdev
  1914. * @tx_desc: TX descriptor
  1915. *
  1916. * Return: None
  1917. */
  1918. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1919. struct dp_vdev *vdev,
  1920. struct dp_tx_desc_s *tx_desc)
  1921. {
  1922. if (qdf_unlikely(vdev->mesh_vdev))
  1923. tx_desc->flags |= DP_TX_DESC_FLAG_MESH_MODE;
  1924. }
  1925. /**
  1926. * dp_mesh_tx_comp_free_buff() - Free the mesh tx packet buffer
  1927. * @soc: dp_soc handle
  1928. * @tx_desc: TX descriptor
  1929. * @delayed_free: delay the nbuf free
  1930. *
  1931. * Return: nbuf to be freed late
  1932. */
  1933. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1934. struct dp_tx_desc_s *tx_desc,
  1935. bool delayed_free)
  1936. {
  1937. qdf_nbuf_t nbuf = tx_desc->nbuf;
  1938. struct dp_vdev *vdev = NULL;
  1939. vdev = dp_vdev_get_ref_by_id(soc, tx_desc->vdev_id, DP_MOD_ID_MESH);
  1940. if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW) {
  1941. if (vdev)
  1942. DP_STATS_INC(vdev, tx_i.mesh.completion_fw, 1);
  1943. if (delayed_free)
  1944. return nbuf;
  1945. qdf_nbuf_free(nbuf);
  1946. } else {
  1947. if (vdev && vdev->osif_tx_free_ext) {
  1948. vdev->osif_tx_free_ext((nbuf));
  1949. } else {
  1950. if (delayed_free)
  1951. return nbuf;
  1952. qdf_nbuf_free(nbuf);
  1953. }
  1954. }
  1955. if (vdev)
  1956. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  1957. return NULL;
  1958. }
  1959. #else
  1960. static inline void dp_tx_update_mesh_flags(struct dp_soc *soc,
  1961. struct dp_vdev *vdev,
  1962. struct dp_tx_desc_s *tx_desc)
  1963. {
  1964. }
  1965. static inline qdf_nbuf_t dp_mesh_tx_comp_free_buff(struct dp_soc *soc,
  1966. struct dp_tx_desc_s *tx_desc,
  1967. bool delayed_free)
  1968. {
  1969. return NULL;
  1970. }
  1971. #endif
  1972. /**
  1973. * dp_tx_frame_is_drop() - checks if the packet is loopback
  1974. * @vdev: DP vdev handle
  1975. * @nbuf: skb
  1976. *
  1977. * Return: 1 if frame needs to be dropped else 0
  1978. */
  1979. int dp_tx_frame_is_drop(struct dp_vdev *vdev, uint8_t *srcmac, uint8_t *dstmac)
  1980. {
  1981. struct dp_pdev *pdev = NULL;
  1982. struct dp_ast_entry *src_ast_entry = NULL;
  1983. struct dp_ast_entry *dst_ast_entry = NULL;
  1984. struct dp_soc *soc = NULL;
  1985. qdf_assert(vdev);
  1986. pdev = vdev->pdev;
  1987. qdf_assert(pdev);
  1988. soc = pdev->soc;
  1989. dst_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1990. (soc, dstmac, vdev->pdev->pdev_id);
  1991. src_ast_entry = dp_peer_ast_hash_find_by_pdevid
  1992. (soc, srcmac, vdev->pdev->pdev_id);
  1993. if (dst_ast_entry && src_ast_entry) {
  1994. if (dst_ast_entry->peer_id ==
  1995. src_ast_entry->peer_id)
  1996. return 1;
  1997. }
  1998. return 0;
  1999. }
  2000. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  2001. defined(WLAN_MCAST_MLO)
  2002. /* MLO peer id for reinject*/
  2003. #define DP_MLO_MCAST_REINJECT_PEER_ID 0XFFFD
  2004. /* MLO vdev id inc offset */
  2005. #define DP_MLO_VDEV_ID_OFFSET 0x80
  2006. static inline void
  2007. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2008. {
  2009. if (!(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)) {
  2010. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2011. qdf_atomic_inc(&soc->num_tx_exception);
  2012. }
  2013. }
  2014. static inline void
  2015. dp_tx_update_mcast_param(uint16_t peer_id,
  2016. uint16_t *htt_tcl_metadata,
  2017. struct dp_vdev *vdev,
  2018. struct dp_tx_msdu_info_s *msdu_info)
  2019. {
  2020. if (peer_id == DP_MLO_MCAST_REINJECT_PEER_ID) {
  2021. *htt_tcl_metadata = 0;
  2022. DP_TX_TCL_METADATA_TYPE_SET(
  2023. *htt_tcl_metadata,
  2024. HTT_TCL_METADATA_V2_TYPE_GLOBAL_SEQ_BASED);
  2025. HTT_TX_TCL_METADATA_GLBL_SEQ_NO_SET(*htt_tcl_metadata,
  2026. msdu_info->gsn);
  2027. msdu_info->vdev_id = vdev->vdev_id + DP_MLO_VDEV_ID_OFFSET;
  2028. if (qdf_unlikely(vdev->nawds_enabled))
  2029. HTT_TX_TCL_METADATA_GLBL_SEQ_HOST_INSPECTED_SET(
  2030. *htt_tcl_metadata, 1);
  2031. } else {
  2032. msdu_info->vdev_id = vdev->vdev_id;
  2033. }
  2034. }
  2035. #else
  2036. static inline void
  2037. dp_tx_bypass_reinjection(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  2038. {
  2039. }
  2040. static inline void
  2041. dp_tx_update_mcast_param(uint16_t peer_id,
  2042. uint16_t *htt_tcl_metadata,
  2043. struct dp_vdev *vdev,
  2044. struct dp_tx_msdu_info_s *msdu_info)
  2045. {
  2046. }
  2047. #endif
  2048. #ifdef DP_TX_SW_DROP_STATS_INC
  2049. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2050. qdf_nbuf_t nbuf,
  2051. enum cdp_tx_sw_drop drop_code)
  2052. {
  2053. /* EAPOL Drop stats */
  2054. if (qdf_nbuf_is_ipv4_eapol_pkt(nbuf)) {
  2055. switch (drop_code) {
  2056. case TX_DESC_ERR:
  2057. DP_STATS_INC(pdev, eap_drop_stats.tx_desc_err, 1);
  2058. break;
  2059. case TX_HAL_RING_ACCESS_ERR:
  2060. DP_STATS_INC(pdev,
  2061. eap_drop_stats.tx_hal_ring_access_err, 1);
  2062. break;
  2063. case TX_DMA_MAP_ERR:
  2064. DP_STATS_INC(pdev, eap_drop_stats.tx_dma_map_err, 1);
  2065. break;
  2066. case TX_HW_ENQUEUE:
  2067. DP_STATS_INC(pdev, eap_drop_stats.tx_hw_enqueue, 1);
  2068. break;
  2069. case TX_SW_ENQUEUE:
  2070. DP_STATS_INC(pdev, eap_drop_stats.tx_sw_enqueue, 1);
  2071. break;
  2072. default:
  2073. dp_info_rl("Invalid eapol_drop code: %d", drop_code);
  2074. break;
  2075. }
  2076. }
  2077. }
  2078. #else
  2079. static void tx_sw_drop_stats_inc(struct dp_pdev *pdev,
  2080. qdf_nbuf_t nbuf,
  2081. enum cdp_tx_sw_drop drop_code)
  2082. {
  2083. }
  2084. #endif
  2085. /**
  2086. * dp_tx_send_msdu_single() - Setup descriptor and enqueue single MSDU to TCL
  2087. * @vdev: DP vdev handle
  2088. * @nbuf: skb
  2089. * @tid: TID from HLOS for overriding default DSCP-TID mapping
  2090. * @meta_data: Metadata to the fw
  2091. * @tx_q: Tx queue to be used for this Tx frame
  2092. * @peer_id: peer_id of the peer in case of NAWDS frames
  2093. * @tx_exc_metadata: Handle that holds exception path metadata
  2094. *
  2095. * Return: NULL on success,
  2096. * nbuf when it fails to send
  2097. */
  2098. qdf_nbuf_t
  2099. dp_tx_send_msdu_single(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2100. struct dp_tx_msdu_info_s *msdu_info, uint16_t peer_id,
  2101. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2102. {
  2103. struct dp_pdev *pdev = vdev->pdev;
  2104. struct dp_soc *soc = pdev->soc;
  2105. struct dp_tx_desc_s *tx_desc;
  2106. QDF_STATUS status;
  2107. struct dp_tx_queue *tx_q = &(msdu_info->tx_queue);
  2108. uint16_t htt_tcl_metadata = 0;
  2109. enum cdp_tx_sw_drop drop_code = TX_MAX_DROP;
  2110. uint8_t tid = msdu_info->tid;
  2111. struct cdp_tid_tx_stats *tid_stats = NULL;
  2112. qdf_dma_addr_t paddr;
  2113. /* Setup Tx descriptor for an MSDU, and MSDU extension descriptor */
  2114. tx_desc = dp_tx_prepare_desc_single(vdev, nbuf, tx_q->desc_pool_id,
  2115. msdu_info, tx_exc_metadata);
  2116. if (!tx_desc) {
  2117. dp_err_rl("Tx_desc prepare Fail vdev_id %d vdev %pK queue %d",
  2118. vdev->vdev_id, vdev, tx_q->desc_pool_id);
  2119. drop_code = TX_DESC_ERR;
  2120. goto fail_return;
  2121. }
  2122. dp_tx_update_tdls_flags(soc, vdev, tx_desc);
  2123. if (qdf_unlikely(peer_id == DP_INVALID_PEER)) {
  2124. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2125. DP_TX_TCL_METADATA_HOST_INSPECTED_SET(htt_tcl_metadata, 1);
  2126. } else if (qdf_unlikely(peer_id != HTT_INVALID_PEER)) {
  2127. DP_TX_TCL_METADATA_TYPE_SET(htt_tcl_metadata,
  2128. DP_TCL_METADATA_TYPE_PEER_BASED);
  2129. DP_TX_TCL_METADATA_PEER_ID_SET(htt_tcl_metadata,
  2130. peer_id);
  2131. dp_tx_bypass_reinjection(soc, tx_desc);
  2132. } else
  2133. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2134. if (msdu_info->exception_fw)
  2135. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2136. dp_tx_desc_update_fast_comp_flag(soc, tx_desc,
  2137. !pdev->enhanced_stats_en);
  2138. dp_tx_update_mesh_flags(soc, vdev, tx_desc);
  2139. if (qdf_unlikely(msdu_info->frm_type == dp_tx_frm_rmnet))
  2140. paddr = dp_tx_rmnet_nbuf_map(msdu_info, tx_desc);
  2141. else
  2142. paddr = dp_tx_nbuf_map(vdev, tx_desc, nbuf);
  2143. if (!paddr) {
  2144. /* Handle failure */
  2145. dp_err("qdf_nbuf_map failed");
  2146. DP_STATS_INC(vdev, tx_i.dropped.dma_error, 1);
  2147. drop_code = TX_DMA_MAP_ERR;
  2148. goto release_desc;
  2149. }
  2150. tx_desc->dma_addr = paddr;
  2151. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2152. tx_desc->id, DP_TX_DESC_MAP);
  2153. dp_tx_update_mcast_param(peer_id, &htt_tcl_metadata, vdev, msdu_info);
  2154. /* Enqueue the Tx MSDU descriptor to HW for transmit */
  2155. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2156. htt_tcl_metadata,
  2157. tx_exc_metadata, msdu_info);
  2158. if (status != QDF_STATUS_SUCCESS) {
  2159. dp_tx_err_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2160. tx_desc, tx_q->ring_id);
  2161. dp_tx_desc_history_add(soc, tx_desc->dma_addr, nbuf,
  2162. tx_desc->id, DP_TX_DESC_UNMAP);
  2163. dp_tx_nbuf_unmap(soc, tx_desc);
  2164. drop_code = TX_HW_ENQUEUE;
  2165. goto release_desc;
  2166. }
  2167. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2168. return NULL;
  2169. release_desc:
  2170. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2171. fail_return:
  2172. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2173. tx_sw_drop_stats_inc(pdev, nbuf, drop_code);
  2174. tid_stats = &pdev->stats.tid_stats.
  2175. tid_tx_stats[tx_q->ring_id][tid];
  2176. tid_stats->swdrop_cnt[drop_code]++;
  2177. return nbuf;
  2178. }
  2179. /**
  2180. * dp_tx_comp_free_buf() - Free nbuf associated with the Tx Descriptor
  2181. * @soc: Soc handle
  2182. * @desc: software Tx descriptor to be processed
  2183. * @delayed_free: defer freeing of nbuf
  2184. *
  2185. * Return: nbuf to be freed later
  2186. */
  2187. qdf_nbuf_t dp_tx_comp_free_buf(struct dp_soc *soc, struct dp_tx_desc_s *desc,
  2188. bool delayed_free)
  2189. {
  2190. qdf_nbuf_t nbuf = desc->nbuf;
  2191. enum dp_tx_event_type type = dp_tx_get_event_type(desc->flags);
  2192. /* nbuf already freed in vdev detach path */
  2193. if (!nbuf)
  2194. return NULL;
  2195. /* If it is TDLS mgmt, don't unmap or free the frame */
  2196. if (desc->flags & DP_TX_DESC_FLAG_TDLS_FRAME) {
  2197. dp_non_std_htt_tx_comp_free_buff(soc, desc);
  2198. return NULL;
  2199. }
  2200. /* 0 : MSDU buffer, 1 : MLE */
  2201. if (desc->msdu_ext_desc) {
  2202. /* TSO free */
  2203. if (hal_tx_ext_desc_get_tso_enable(
  2204. desc->msdu_ext_desc->vaddr)) {
  2205. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  2206. desc->id, DP_TX_COMP_MSDU_EXT);
  2207. dp_tx_tso_seg_history_add(soc,
  2208. desc->msdu_ext_desc->tso_desc,
  2209. desc->nbuf, desc->id, type);
  2210. /* unmap eash TSO seg before free the nbuf */
  2211. dp_tx_tso_unmap_segment(soc,
  2212. desc->msdu_ext_desc->tso_desc,
  2213. desc->msdu_ext_desc->
  2214. tso_num_desc);
  2215. goto nbuf_free;
  2216. }
  2217. if (qdf_unlikely(desc->frm_type == dp_tx_frm_sg)) {
  2218. void *msdu_ext_desc = desc->msdu_ext_desc->vaddr;
  2219. qdf_dma_addr_t iova;
  2220. uint32_t frag_len;
  2221. uint32_t i;
  2222. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf,
  2223. QDF_DMA_TO_DEVICE,
  2224. qdf_nbuf_headlen(nbuf));
  2225. for (i = 1; i < DP_TX_MAX_NUM_FRAGS; i++) {
  2226. hal_tx_ext_desc_get_frag_info(msdu_ext_desc, i,
  2227. &iova,
  2228. &frag_len);
  2229. if (!iova || !frag_len)
  2230. break;
  2231. qdf_mem_unmap_page(soc->osdev, iova, frag_len,
  2232. QDF_DMA_TO_DEVICE);
  2233. }
  2234. goto nbuf_free;
  2235. }
  2236. }
  2237. /* If it's ME frame, dont unmap the cloned nbuf's */
  2238. if ((desc->flags & DP_TX_DESC_FLAG_ME) && qdf_nbuf_is_cloned(nbuf))
  2239. goto nbuf_free;
  2240. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf, desc->id, type);
  2241. dp_tx_unmap(soc, desc);
  2242. if (desc->flags & DP_TX_DESC_FLAG_MESH_MODE)
  2243. return dp_mesh_tx_comp_free_buff(soc, desc, delayed_free);
  2244. if (dp_tx_traffic_end_indication_enq_ind_pkt(soc, desc, nbuf))
  2245. return NULL;
  2246. nbuf_free:
  2247. if (delayed_free)
  2248. return nbuf;
  2249. qdf_nbuf_free(nbuf);
  2250. return NULL;
  2251. }
  2252. /**
  2253. * dp_tx_sg_unmap_buf() - Unmap scatter gather fragments
  2254. * @soc: DP soc handle
  2255. * @nbuf: skb
  2256. * @msdu_info: MSDU info
  2257. *
  2258. * Return: None
  2259. */
  2260. static inline void
  2261. dp_tx_sg_unmap_buf(struct dp_soc *soc, qdf_nbuf_t nbuf,
  2262. struct dp_tx_msdu_info_s *msdu_info)
  2263. {
  2264. uint32_t cur_idx;
  2265. struct dp_tx_seg_info_s *seg = msdu_info->u.sg_info.curr_seg;
  2266. qdf_nbuf_unmap_nbytes_single(soc->osdev, nbuf, QDF_DMA_TO_DEVICE,
  2267. qdf_nbuf_headlen(nbuf));
  2268. for (cur_idx = 1; cur_idx < seg->frag_cnt; cur_idx++)
  2269. qdf_mem_unmap_page(soc->osdev, (qdf_dma_addr_t)
  2270. (seg->frags[cur_idx].paddr_lo | ((uint64_t)
  2271. seg->frags[cur_idx].paddr_hi) << 32),
  2272. seg->frags[cur_idx].len,
  2273. QDF_DMA_TO_DEVICE);
  2274. }
  2275. /**
  2276. * dp_tx_send_msdu_multiple() - Enqueue multiple MSDUs
  2277. * @vdev: DP vdev handle
  2278. * @nbuf: skb
  2279. * @msdu_info: MSDU info to be setup in MSDU extension descriptor
  2280. *
  2281. * Prepare descriptors for multiple MSDUs (TSO segments) and enqueue to TCL
  2282. *
  2283. * Return: NULL on success,
  2284. * nbuf when it fails to send
  2285. */
  2286. #if QDF_LOCK_STATS
  2287. noinline
  2288. #else
  2289. #endif
  2290. qdf_nbuf_t dp_tx_send_msdu_multiple(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2291. struct dp_tx_msdu_info_s *msdu_info)
  2292. {
  2293. uint32_t i;
  2294. struct dp_pdev *pdev = vdev->pdev;
  2295. struct dp_soc *soc = pdev->soc;
  2296. struct dp_tx_desc_s *tx_desc;
  2297. bool is_cce_classified = false;
  2298. QDF_STATUS status;
  2299. uint16_t htt_tcl_metadata = 0;
  2300. struct dp_tx_queue *tx_q = &msdu_info->tx_queue;
  2301. struct cdp_tid_tx_stats *tid_stats = NULL;
  2302. uint8_t prep_desc_fail = 0, hw_enq_fail = 0;
  2303. if (msdu_info->frm_type == dp_tx_frm_me)
  2304. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2305. i = 0;
  2306. /* Print statement to track i and num_seg */
  2307. /*
  2308. * For each segment (maps to 1 MSDU) , prepare software and hardware
  2309. * descriptors using information in msdu_info
  2310. */
  2311. while (i < msdu_info->num_seg) {
  2312. /*
  2313. * Setup Tx descriptor for an MSDU, and MSDU extension
  2314. * descriptor
  2315. */
  2316. tx_desc = dp_tx_prepare_desc(vdev, nbuf, msdu_info,
  2317. tx_q->desc_pool_id);
  2318. if (!tx_desc) {
  2319. if (msdu_info->frm_type == dp_tx_frm_me) {
  2320. prep_desc_fail++;
  2321. dp_tx_me_free_buf(pdev,
  2322. (void *)(msdu_info->u.sg_info
  2323. .curr_seg->frags[0].vaddr));
  2324. if (prep_desc_fail == msdu_info->num_seg) {
  2325. /*
  2326. * Unmap is needed only if descriptor
  2327. * preparation failed for all segments.
  2328. */
  2329. qdf_nbuf_unmap(soc->osdev,
  2330. msdu_info->u.sg_info.
  2331. curr_seg->nbuf,
  2332. QDF_DMA_TO_DEVICE);
  2333. }
  2334. /*
  2335. * Free the nbuf for the current segment
  2336. * and make it point to the next in the list.
  2337. * For me, there are as many segments as there
  2338. * are no of clients.
  2339. */
  2340. qdf_nbuf_free(msdu_info->u.sg_info
  2341. .curr_seg->nbuf);
  2342. if (msdu_info->u.sg_info.curr_seg->next) {
  2343. msdu_info->u.sg_info.curr_seg =
  2344. msdu_info->u.sg_info
  2345. .curr_seg->next;
  2346. nbuf = msdu_info->u.sg_info
  2347. .curr_seg->nbuf;
  2348. }
  2349. i++;
  2350. continue;
  2351. }
  2352. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2353. dp_tx_tso_seg_history_add(
  2354. soc,
  2355. msdu_info->u.tso_info.curr_seg,
  2356. nbuf, 0, DP_TX_DESC_UNMAP);
  2357. dp_tx_tso_unmap_segment(soc,
  2358. msdu_info->u.tso_info.
  2359. curr_seg,
  2360. msdu_info->u.tso_info.
  2361. tso_num_seg_list);
  2362. if (msdu_info->u.tso_info.curr_seg->next) {
  2363. msdu_info->u.tso_info.curr_seg =
  2364. msdu_info->u.tso_info.curr_seg->next;
  2365. i++;
  2366. continue;
  2367. }
  2368. }
  2369. if (msdu_info->frm_type == dp_tx_frm_sg)
  2370. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2371. goto done;
  2372. }
  2373. if (msdu_info->frm_type == dp_tx_frm_me) {
  2374. tx_desc->msdu_ext_desc->me_buffer =
  2375. (struct dp_tx_me_buf_t *)msdu_info->
  2376. u.sg_info.curr_seg->frags[0].vaddr;
  2377. tx_desc->flags |= DP_TX_DESC_FLAG_ME;
  2378. }
  2379. if (is_cce_classified)
  2380. tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
  2381. htt_tcl_metadata = vdev->htt_tcl_metadata;
  2382. if (msdu_info->exception_fw) {
  2383. DP_TX_TCL_METADATA_VALID_HTT_SET(htt_tcl_metadata, 1);
  2384. }
  2385. dp_tx_is_hp_update_required(i, msdu_info);
  2386. /*
  2387. * For frames with multiple segments (TSO, ME), jump to next
  2388. * segment.
  2389. */
  2390. if (msdu_info->frm_type == dp_tx_frm_tso) {
  2391. if (msdu_info->u.tso_info.curr_seg->next) {
  2392. msdu_info->u.tso_info.curr_seg =
  2393. msdu_info->u.tso_info.curr_seg->next;
  2394. /*
  2395. * If this is a jumbo nbuf, then increment the
  2396. * number of nbuf users for each additional
  2397. * segment of the msdu. This will ensure that
  2398. * the skb is freed only after receiving tx
  2399. * completion for all segments of an nbuf
  2400. */
  2401. qdf_nbuf_inc_users(nbuf);
  2402. /* Check with MCL if this is needed */
  2403. /* nbuf = msdu_info->u.tso_info.curr_seg->nbuf;
  2404. */
  2405. }
  2406. }
  2407. dp_tx_update_mcast_param(DP_INVALID_PEER,
  2408. &htt_tcl_metadata,
  2409. vdev,
  2410. msdu_info);
  2411. /*
  2412. * Enqueue the Tx MSDU descriptor to HW for transmit
  2413. */
  2414. status = soc->arch_ops.tx_hw_enqueue(soc, vdev, tx_desc,
  2415. htt_tcl_metadata,
  2416. NULL, msdu_info);
  2417. dp_tx_check_and_flush_hp(soc, status, msdu_info);
  2418. if (status != QDF_STATUS_SUCCESS) {
  2419. dp_info_rl("Tx_hw_enqueue Fail tx_desc %pK queue %d",
  2420. tx_desc, tx_q->ring_id);
  2421. dp_tx_get_tid(vdev, nbuf, msdu_info);
  2422. tid_stats = &pdev->stats.tid_stats.
  2423. tid_tx_stats[tx_q->ring_id][msdu_info->tid];
  2424. tid_stats->swdrop_cnt[TX_HW_ENQUEUE]++;
  2425. if (msdu_info->frm_type == dp_tx_frm_me) {
  2426. hw_enq_fail++;
  2427. if (hw_enq_fail == msdu_info->num_seg) {
  2428. /*
  2429. * Unmap is needed only if enqueue
  2430. * failed for all segments.
  2431. */
  2432. qdf_nbuf_unmap(soc->osdev,
  2433. msdu_info->u.sg_info.
  2434. curr_seg->nbuf,
  2435. QDF_DMA_TO_DEVICE);
  2436. }
  2437. /*
  2438. * Free the nbuf for the current segment
  2439. * and make it point to the next in the list.
  2440. * For me, there are as many segments as there
  2441. * are no of clients.
  2442. */
  2443. qdf_nbuf_free(msdu_info->u.sg_info
  2444. .curr_seg->nbuf);
  2445. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2446. if (msdu_info->u.sg_info.curr_seg->next) {
  2447. msdu_info->u.sg_info.curr_seg =
  2448. msdu_info->u.sg_info
  2449. .curr_seg->next;
  2450. nbuf = msdu_info->u.sg_info
  2451. .curr_seg->nbuf;
  2452. } else
  2453. break;
  2454. i++;
  2455. continue;
  2456. }
  2457. /*
  2458. * For TSO frames, the nbuf users increment done for
  2459. * the current segment has to be reverted, since the
  2460. * hw enqueue for this segment failed
  2461. */
  2462. if (msdu_info->frm_type == dp_tx_frm_tso &&
  2463. msdu_info->u.tso_info.curr_seg) {
  2464. /*
  2465. * unmap and free current,
  2466. * retransmit remaining segments
  2467. */
  2468. dp_tx_comp_free_buf(soc, tx_desc, false);
  2469. i++;
  2470. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2471. continue;
  2472. }
  2473. if (msdu_info->frm_type == dp_tx_frm_sg)
  2474. dp_tx_sg_unmap_buf(soc, nbuf, msdu_info);
  2475. dp_tx_desc_release(tx_desc, tx_q->desc_pool_id);
  2476. goto done;
  2477. }
  2478. /*
  2479. * TODO
  2480. * if tso_info structure can be modified to have curr_seg
  2481. * as first element, following 2 blocks of code (for TSO and SG)
  2482. * can be combined into 1
  2483. */
  2484. /*
  2485. * For Multicast-Unicast converted packets,
  2486. * each converted frame (for a client) is represented as
  2487. * 1 segment
  2488. */
  2489. if ((msdu_info->frm_type == dp_tx_frm_sg) ||
  2490. (msdu_info->frm_type == dp_tx_frm_me)) {
  2491. if (msdu_info->u.sg_info.curr_seg->next) {
  2492. msdu_info->u.sg_info.curr_seg =
  2493. msdu_info->u.sg_info.curr_seg->next;
  2494. nbuf = msdu_info->u.sg_info.curr_seg->nbuf;
  2495. } else
  2496. break;
  2497. }
  2498. i++;
  2499. }
  2500. nbuf = NULL;
  2501. done:
  2502. return nbuf;
  2503. }
  2504. /**
  2505. * dp_tx_prepare_sg()- Extract SG info from NBUF and prepare msdu_info
  2506. * for SG frames
  2507. * @vdev: DP vdev handle
  2508. * @nbuf: skb
  2509. * @seg_info: Pointer to Segment info Descriptor to be prepared
  2510. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2511. *
  2512. * Return: NULL on success,
  2513. * nbuf when it fails to send
  2514. */
  2515. static qdf_nbuf_t dp_tx_prepare_sg(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2516. struct dp_tx_seg_info_s *seg_info, struct dp_tx_msdu_info_s *msdu_info)
  2517. {
  2518. uint32_t cur_frag, nr_frags, i;
  2519. qdf_dma_addr_t paddr;
  2520. struct dp_tx_sg_info_s *sg_info;
  2521. sg_info = &msdu_info->u.sg_info;
  2522. nr_frags = qdf_nbuf_get_nr_frags(nbuf);
  2523. if (QDF_STATUS_SUCCESS !=
  2524. qdf_nbuf_map_nbytes_single(vdev->osdev, nbuf,
  2525. QDF_DMA_TO_DEVICE,
  2526. qdf_nbuf_headlen(nbuf))) {
  2527. dp_tx_err("dma map error");
  2528. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2529. qdf_nbuf_free(nbuf);
  2530. return NULL;
  2531. }
  2532. paddr = qdf_nbuf_mapped_paddr_get(nbuf);
  2533. seg_info->frags[0].paddr_lo = paddr;
  2534. seg_info->frags[0].paddr_hi = ((uint64_t) paddr) >> 32;
  2535. seg_info->frags[0].len = qdf_nbuf_headlen(nbuf);
  2536. seg_info->frags[0].vaddr = (void *) nbuf;
  2537. for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
  2538. if (QDF_STATUS_SUCCESS != qdf_nbuf_frag_map(vdev->osdev,
  2539. nbuf, 0,
  2540. QDF_DMA_TO_DEVICE,
  2541. cur_frag)) {
  2542. dp_tx_err("frag dma map error");
  2543. DP_STATS_INC(vdev, tx_i.sg.dma_map_error, 1);
  2544. goto map_err;
  2545. }
  2546. paddr = qdf_nbuf_get_tx_frag_paddr(nbuf);
  2547. seg_info->frags[cur_frag + 1].paddr_lo = paddr;
  2548. seg_info->frags[cur_frag + 1].paddr_hi =
  2549. ((uint64_t) paddr) >> 32;
  2550. seg_info->frags[cur_frag + 1].len =
  2551. qdf_nbuf_get_frag_size(nbuf, cur_frag);
  2552. }
  2553. seg_info->frag_cnt = (cur_frag + 1);
  2554. seg_info->total_len = qdf_nbuf_len(nbuf);
  2555. seg_info->next = NULL;
  2556. sg_info->curr_seg = seg_info;
  2557. msdu_info->frm_type = dp_tx_frm_sg;
  2558. msdu_info->num_seg = 1;
  2559. return nbuf;
  2560. map_err:
  2561. /* restore paddr into nbuf before calling unmap */
  2562. qdf_nbuf_mapped_paddr_set(nbuf,
  2563. (qdf_dma_addr_t)(seg_info->frags[0].paddr_lo |
  2564. ((uint64_t)
  2565. seg_info->frags[0].paddr_hi) << 32));
  2566. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  2567. QDF_DMA_TO_DEVICE,
  2568. seg_info->frags[0].len);
  2569. for (i = 1; i <= cur_frag; i++) {
  2570. qdf_mem_unmap_page(vdev->osdev, (qdf_dma_addr_t)
  2571. (seg_info->frags[i].paddr_lo | ((uint64_t)
  2572. seg_info->frags[i].paddr_hi) << 32),
  2573. seg_info->frags[i].len,
  2574. QDF_DMA_TO_DEVICE);
  2575. }
  2576. qdf_nbuf_free(nbuf);
  2577. return NULL;
  2578. }
  2579. /**
  2580. * dp_tx_add_tx_sniffer_meta_data()- Add tx_sniffer meta hdr info
  2581. * @vdev: DP vdev handle
  2582. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2583. * @ppdu_cookie: PPDU cookie that should be replayed in the ppdu completions
  2584. *
  2585. * Return: NULL on failure,
  2586. * nbuf when extracted successfully
  2587. */
  2588. static
  2589. void dp_tx_add_tx_sniffer_meta_data(struct dp_vdev *vdev,
  2590. struct dp_tx_msdu_info_s *msdu_info,
  2591. uint16_t ppdu_cookie)
  2592. {
  2593. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2594. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2595. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2596. HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET
  2597. (msdu_info->meta_data[5], 1);
  2598. HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET
  2599. (msdu_info->meta_data[5], 1);
  2600. HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET
  2601. (msdu_info->meta_data[6], ppdu_cookie);
  2602. msdu_info->exception_fw = 1;
  2603. msdu_info->is_tx_sniffer = 1;
  2604. }
  2605. #ifdef MESH_MODE_SUPPORT
  2606. /**
  2607. * dp_tx_extract_mesh_meta_data()- Extract mesh meta hdr info from nbuf
  2608. and prepare msdu_info for mesh frames.
  2609. * @vdev: DP vdev handle
  2610. * @nbuf: skb
  2611. * @msdu_info: MSDU info to be setup in MSDU descriptor and MSDU extension desc.
  2612. *
  2613. * Return: NULL on failure,
  2614. * nbuf when extracted successfully
  2615. */
  2616. static
  2617. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2618. struct dp_tx_msdu_info_s *msdu_info)
  2619. {
  2620. struct meta_hdr_s *mhdr;
  2621. struct htt_tx_msdu_desc_ext2_t *meta_data =
  2622. (struct htt_tx_msdu_desc_ext2_t *)&msdu_info->meta_data[0];
  2623. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  2624. if (CB_FTYPE_MESH_TX_INFO != qdf_nbuf_get_tx_ftype(nbuf)) {
  2625. msdu_info->exception_fw = 0;
  2626. goto remove_meta_hdr;
  2627. }
  2628. msdu_info->exception_fw = 1;
  2629. qdf_mem_zero(meta_data, sizeof(struct htt_tx_msdu_desc_ext2_t));
  2630. meta_data->host_tx_desc_pool = 1;
  2631. meta_data->update_peer_cache = 1;
  2632. meta_data->learning_frame = 1;
  2633. if (!(mhdr->flags & METAHDR_FLAG_AUTO_RATE)) {
  2634. meta_data->power = mhdr->power;
  2635. meta_data->mcs_mask = 1 << mhdr->rate_info[0].mcs;
  2636. meta_data->nss_mask = 1 << mhdr->rate_info[0].nss;
  2637. meta_data->pream_type = mhdr->rate_info[0].preamble_type;
  2638. meta_data->retry_limit = mhdr->rate_info[0].max_tries;
  2639. meta_data->dyn_bw = 1;
  2640. meta_data->valid_pwr = 1;
  2641. meta_data->valid_mcs_mask = 1;
  2642. meta_data->valid_nss_mask = 1;
  2643. meta_data->valid_preamble_type = 1;
  2644. meta_data->valid_retries = 1;
  2645. meta_data->valid_bw_info = 1;
  2646. }
  2647. if (mhdr->flags & METAHDR_FLAG_NOENCRYPT) {
  2648. meta_data->encrypt_type = 0;
  2649. meta_data->valid_encrypt_type = 1;
  2650. meta_data->learning_frame = 0;
  2651. }
  2652. meta_data->valid_key_flags = 1;
  2653. meta_data->key_flags = (mhdr->keyix & 0x3);
  2654. remove_meta_hdr:
  2655. if (qdf_nbuf_pull_head(nbuf, sizeof(struct meta_hdr_s)) == NULL) {
  2656. dp_tx_err("qdf_nbuf_pull_head failed");
  2657. qdf_nbuf_free(nbuf);
  2658. return NULL;
  2659. }
  2660. msdu_info->tid = qdf_nbuf_get_priority(nbuf);
  2661. dp_tx_info("Meta hdr %0x %0x %0x %0x %0x %0x"
  2662. " tid %d to_fw %d",
  2663. msdu_info->meta_data[0],
  2664. msdu_info->meta_data[1],
  2665. msdu_info->meta_data[2],
  2666. msdu_info->meta_data[3],
  2667. msdu_info->meta_data[4],
  2668. msdu_info->meta_data[5],
  2669. msdu_info->tid, msdu_info->exception_fw);
  2670. return nbuf;
  2671. }
  2672. #else
  2673. static
  2674. qdf_nbuf_t dp_tx_extract_mesh_meta_data(struct dp_vdev *vdev, qdf_nbuf_t nbuf,
  2675. struct dp_tx_msdu_info_s *msdu_info)
  2676. {
  2677. return nbuf;
  2678. }
  2679. #endif
  2680. /**
  2681. * dp_check_exc_metadata() - Checks if parameters are valid
  2682. * @tx_exc - holds all exception path parameters
  2683. *
  2684. * Returns true when all the parameters are valid else false
  2685. *
  2686. */
  2687. static bool dp_check_exc_metadata(struct cdp_tx_exception_metadata *tx_exc)
  2688. {
  2689. bool invalid_tid = (tx_exc->tid >= DP_MAX_TIDS && tx_exc->tid !=
  2690. HTT_INVALID_TID);
  2691. bool invalid_encap_type =
  2692. (tx_exc->tx_encap_type > htt_cmn_pkt_num_types &&
  2693. tx_exc->tx_encap_type != CDP_INVALID_TX_ENCAP_TYPE);
  2694. bool invalid_sec_type = (tx_exc->sec_type > cdp_num_sec_types &&
  2695. tx_exc->sec_type != CDP_INVALID_SEC_TYPE);
  2696. bool invalid_cookie = (tx_exc->is_tx_sniffer == 1 &&
  2697. tx_exc->ppdu_cookie == 0);
  2698. if (tx_exc->is_intrabss_fwd)
  2699. return true;
  2700. if (invalid_tid || invalid_encap_type || invalid_sec_type ||
  2701. invalid_cookie) {
  2702. return false;
  2703. }
  2704. return true;
  2705. }
  2706. #ifdef ATH_SUPPORT_IQUE
  2707. /**
  2708. * dp_tx_mcast_enhance() - Multicast enhancement on TX
  2709. * @vdev: vdev handle
  2710. * @nbuf: skb
  2711. *
  2712. * Return: true on success,
  2713. * false on failure
  2714. */
  2715. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2716. {
  2717. qdf_ether_header_t *eh;
  2718. /* Mcast to Ucast Conversion*/
  2719. if (qdf_likely(!vdev->mcast_enhancement_en))
  2720. return true;
  2721. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2722. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) &&
  2723. !DP_FRAME_IS_BROADCAST((eh)->ether_dhost)) {
  2724. dp_verbose_debug("Mcast frm for ME %pK", vdev);
  2725. qdf_nbuf_set_next(nbuf, NULL);
  2726. DP_STATS_INC_PKT(vdev, tx_i.mcast_en.mcast_pkt, 1,
  2727. qdf_nbuf_len(nbuf));
  2728. if (dp_tx_prepare_send_me(vdev, nbuf) ==
  2729. QDF_STATUS_SUCCESS) {
  2730. return false;
  2731. }
  2732. if (qdf_unlikely(vdev->igmp_mcast_enhanc_en > 0)) {
  2733. if (dp_tx_prepare_send_igmp_me(vdev, nbuf) ==
  2734. QDF_STATUS_SUCCESS) {
  2735. return false;
  2736. }
  2737. }
  2738. }
  2739. return true;
  2740. }
  2741. #else
  2742. static inline bool dp_tx_mcast_enhance(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2743. {
  2744. return true;
  2745. }
  2746. #endif
  2747. #ifdef QCA_SUPPORT_WDS_EXTENDED
  2748. /**
  2749. * dp_tx_mcast_drop() - Drop mcast frame if drop_tx_mcast is set in WDS_EXT
  2750. * @vdev: vdev handle
  2751. * @nbuf: skb
  2752. *
  2753. * Return: true if frame is dropped, false otherwise
  2754. */
  2755. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2756. {
  2757. /* Drop tx mcast and WDS Extended feature check */
  2758. if (qdf_unlikely((vdev->drop_tx_mcast) && (vdev->wds_ext_enabled))) {
  2759. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  2760. qdf_nbuf_data(nbuf);
  2761. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  2762. DP_STATS_INC(vdev, tx_i.dropped.tx_mcast_drop, 1);
  2763. return true;
  2764. }
  2765. }
  2766. return false;
  2767. }
  2768. #else
  2769. static inline bool dp_tx_mcast_drop(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  2770. {
  2771. return false;
  2772. }
  2773. #endif
  2774. /**
  2775. * dp_tx_per_pkt_vdev_id_check() - vdev id check for frame
  2776. * @nbuf: qdf_nbuf_t
  2777. * @vdev: struct dp_vdev *
  2778. *
  2779. * Allow packet for processing only if it is for peer client which is
  2780. * connected with same vap. Drop packet if client is connected to
  2781. * different vap.
  2782. *
  2783. * Return: QDF_STATUS
  2784. */
  2785. static inline QDF_STATUS
  2786. dp_tx_per_pkt_vdev_id_check(qdf_nbuf_t nbuf, struct dp_vdev *vdev)
  2787. {
  2788. struct dp_ast_entry *dst_ast_entry = NULL;
  2789. qdf_ether_header_t *eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2790. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost) ||
  2791. DP_FRAME_IS_BROADCAST((eh)->ether_dhost))
  2792. return QDF_STATUS_SUCCESS;
  2793. qdf_spin_lock_bh(&vdev->pdev->soc->ast_lock);
  2794. dst_ast_entry = dp_peer_ast_hash_find_by_vdevid(vdev->pdev->soc,
  2795. eh->ether_dhost,
  2796. vdev->vdev_id);
  2797. /* If there is no ast entry, return failure */
  2798. if (qdf_unlikely(!dst_ast_entry)) {
  2799. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2800. return QDF_STATUS_E_FAILURE;
  2801. }
  2802. qdf_spin_unlock_bh(&vdev->pdev->soc->ast_lock);
  2803. return QDF_STATUS_SUCCESS;
  2804. }
  2805. /**
  2806. * dp_tx_nawds_handler() - NAWDS handler
  2807. *
  2808. * @soc: DP soc handle
  2809. * @vdev_id: id of DP vdev handle
  2810. * @msdu_info: msdu_info required to create HTT metadata
  2811. * @nbuf: skb
  2812. *
  2813. * This API transfers the multicast frames with the peer id
  2814. * on NAWDS enabled peer.
  2815. * Return: none
  2816. */
  2817. static inline
  2818. void dp_tx_nawds_handler(struct dp_soc *soc, struct dp_vdev *vdev,
  2819. struct dp_tx_msdu_info_s *msdu_info,
  2820. qdf_nbuf_t nbuf, uint16_t sa_peer_id)
  2821. {
  2822. struct dp_peer *peer = NULL;
  2823. qdf_nbuf_t nbuf_clone = NULL;
  2824. uint16_t peer_id = DP_INVALID_PEER;
  2825. struct dp_txrx_peer *txrx_peer;
  2826. /* This check avoids pkt forwarding which is entered
  2827. * in the ast table but still doesn't have valid peerid.
  2828. */
  2829. if (sa_peer_id == HTT_INVALID_PEER)
  2830. return;
  2831. qdf_spin_lock_bh(&vdev->peer_list_lock);
  2832. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  2833. txrx_peer = dp_get_txrx_peer(peer);
  2834. if (!txrx_peer)
  2835. continue;
  2836. if (!txrx_peer->bss_peer && txrx_peer->nawds_enabled) {
  2837. peer_id = peer->peer_id;
  2838. if (!dp_peer_is_primary_link_peer(peer))
  2839. continue;
  2840. /* Multicast packets needs to be
  2841. * dropped in case of intra bss forwarding
  2842. */
  2843. if (sa_peer_id == txrx_peer->peer_id) {
  2844. dp_tx_debug("multicast packet");
  2845. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  2846. tx.nawds_mcast_drop,
  2847. 1);
  2848. continue;
  2849. }
  2850. nbuf_clone = qdf_nbuf_clone(nbuf);
  2851. if (!nbuf_clone) {
  2852. QDF_TRACE(QDF_MODULE_ID_DP,
  2853. QDF_TRACE_LEVEL_ERROR,
  2854. FL("nbuf clone failed"));
  2855. break;
  2856. }
  2857. nbuf_clone = dp_tx_send_msdu_single(vdev, nbuf_clone,
  2858. msdu_info, peer_id,
  2859. NULL);
  2860. if (nbuf_clone) {
  2861. dp_tx_debug("pkt send failed");
  2862. qdf_nbuf_free(nbuf_clone);
  2863. } else {
  2864. if (peer_id != DP_INVALID_PEER)
  2865. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  2866. tx.nawds_mcast,
  2867. 1, qdf_nbuf_len(nbuf));
  2868. }
  2869. }
  2870. }
  2871. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  2872. }
  2873. /**
  2874. * dp_tx_send_exception() - Transmit a frame on a given VAP in exception path
  2875. * @soc: DP soc handle
  2876. * @vdev_id: id of DP vdev handle
  2877. * @nbuf: skb
  2878. * @tx_exc_metadata: Handle that holds exception path meta data
  2879. *
  2880. * Entry point for Core Tx layer (DP_TX) invoked from
  2881. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  2882. *
  2883. * Return: NULL on success,
  2884. * nbuf when it fails to send
  2885. */
  2886. qdf_nbuf_t
  2887. dp_tx_send_exception(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  2888. qdf_nbuf_t nbuf,
  2889. struct cdp_tx_exception_metadata *tx_exc_metadata)
  2890. {
  2891. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  2892. qdf_ether_header_t *eh = NULL;
  2893. struct dp_tx_msdu_info_s msdu_info;
  2894. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  2895. DP_MOD_ID_TX_EXCEPTION);
  2896. if (qdf_unlikely(!vdev))
  2897. goto fail;
  2898. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  2899. if (!tx_exc_metadata)
  2900. goto fail;
  2901. msdu_info.tid = tx_exc_metadata->tid;
  2902. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  2903. dp_verbose_debug("skb "QDF_MAC_ADDR_FMT,
  2904. QDF_MAC_ADDR_REF(nbuf->data));
  2905. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_len(nbuf));
  2906. if (qdf_unlikely(!dp_check_exc_metadata(tx_exc_metadata))) {
  2907. dp_tx_err("Invalid parameters in exception path");
  2908. goto fail;
  2909. }
  2910. /* for peer based metadata check if peer is valid */
  2911. if (tx_exc_metadata->peer_id != CDP_INVALID_PEER) {
  2912. struct dp_peer *peer = NULL;
  2913. peer = dp_peer_get_ref_by_id(vdev->pdev->soc,
  2914. tx_exc_metadata->peer_id,
  2915. DP_MOD_ID_TX_EXCEPTION);
  2916. if (qdf_unlikely(!peer)) {
  2917. DP_STATS_INC(vdev,
  2918. tx_i.dropped.invalid_peer_id_in_exc_path,
  2919. 1);
  2920. goto fail;
  2921. }
  2922. dp_peer_unref_delete(peer, DP_MOD_ID_TX_EXCEPTION);
  2923. }
  2924. /* Basic sanity checks for unsupported packets */
  2925. /* MESH mode */
  2926. if (qdf_unlikely(vdev->mesh_vdev)) {
  2927. dp_tx_err("Mesh mode is not supported in exception path");
  2928. goto fail;
  2929. }
  2930. /*
  2931. * Classify the frame and call corresponding
  2932. * "prepare" function which extracts the segment (TSO)
  2933. * and fragmentation information (for TSO , SG, ME, or Raw)
  2934. * into MSDU_INFO structure which is later used to fill
  2935. * SW and HW descriptors.
  2936. */
  2937. if (qdf_nbuf_is_tso(nbuf)) {
  2938. dp_verbose_debug("TSO frame %pK", vdev);
  2939. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  2940. qdf_nbuf_len(nbuf));
  2941. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  2942. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  2943. qdf_nbuf_len(nbuf));
  2944. goto fail;
  2945. }
  2946. goto send_multiple;
  2947. }
  2948. /* SG */
  2949. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  2950. struct dp_tx_seg_info_s seg_info = {0};
  2951. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info, &msdu_info);
  2952. if (!nbuf)
  2953. goto fail;
  2954. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  2955. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  2956. qdf_nbuf_len(nbuf));
  2957. goto send_multiple;
  2958. }
  2959. if (qdf_likely(tx_exc_metadata->is_tx_sniffer)) {
  2960. DP_STATS_INC_PKT(vdev, tx_i.sniffer_rcvd, 1,
  2961. qdf_nbuf_len(nbuf));
  2962. dp_tx_add_tx_sniffer_meta_data(vdev, &msdu_info,
  2963. tx_exc_metadata->ppdu_cookie);
  2964. }
  2965. /*
  2966. * Get HW Queue to use for this frame.
  2967. * TCL supports upto 4 DMA rings, out of which 3 rings are
  2968. * dedicated for data and 1 for command.
  2969. * "queue_id" maps to one hardware ring.
  2970. * With each ring, we also associate a unique Tx descriptor pool
  2971. * to minimize lock contention for these resources.
  2972. */
  2973. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  2974. if (qdf_likely(tx_exc_metadata->is_intrabss_fwd)) {
  2975. if (qdf_unlikely(vdev->nawds_enabled)) {
  2976. /*
  2977. * This is a multicast packet
  2978. */
  2979. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  2980. tx_exc_metadata->peer_id);
  2981. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  2982. 1, qdf_nbuf_len(nbuf));
  2983. }
  2984. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2985. DP_INVALID_PEER, NULL);
  2986. } else {
  2987. /*
  2988. * Check exception descriptors
  2989. */
  2990. if (dp_tx_exception_limit_check(vdev))
  2991. goto fail;
  2992. /* Single linear frame */
  2993. /*
  2994. * If nbuf is a simple linear frame, use send_single function to
  2995. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  2996. * SRNG. There is no need to setup a MSDU extension descriptor.
  2997. */
  2998. nbuf = dp_tx_send_msdu_single(vdev, nbuf, &msdu_info,
  2999. tx_exc_metadata->peer_id,
  3000. tx_exc_metadata);
  3001. }
  3002. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3003. return nbuf;
  3004. send_multiple:
  3005. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3006. fail:
  3007. if (vdev)
  3008. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3009. dp_verbose_debug("pkt send failed");
  3010. return nbuf;
  3011. }
  3012. /**
  3013. * dp_tx_send_exception_vdev_id_check() - Transmit a frame on a given VAP
  3014. * in exception path in special case to avoid regular exception path chk.
  3015. * @soc: DP soc handle
  3016. * @vdev_id: id of DP vdev handle
  3017. * @nbuf: skb
  3018. * @tx_exc_metadata: Handle that holds exception path meta data
  3019. *
  3020. * Entry point for Core Tx layer (DP_TX) invoked from
  3021. * hard_start_xmit in OSIF/HDD to transmit frames through fw
  3022. *
  3023. * Return: NULL on success,
  3024. * nbuf when it fails to send
  3025. */
  3026. qdf_nbuf_t
  3027. dp_tx_send_exception_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3028. uint8_t vdev_id, qdf_nbuf_t nbuf,
  3029. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3030. {
  3031. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3032. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  3033. DP_MOD_ID_TX_EXCEPTION);
  3034. if (qdf_unlikely(!vdev))
  3035. goto fail;
  3036. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3037. == QDF_STATUS_E_FAILURE)) {
  3038. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3039. goto fail;
  3040. }
  3041. /* Unref count as it will again be taken inside dp_tx_exception */
  3042. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3043. return dp_tx_send_exception(soc_hdl, vdev_id, nbuf, tx_exc_metadata);
  3044. fail:
  3045. if (vdev)
  3046. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TX_EXCEPTION);
  3047. dp_verbose_debug("pkt send failed");
  3048. return nbuf;
  3049. }
  3050. /**
  3051. * dp_tx_send_mesh() - Transmit mesh frame on a given VAP
  3052. * @soc: DP soc handle
  3053. * @vdev_id: DP vdev handle
  3054. * @nbuf: skb
  3055. *
  3056. * Entry point for Core Tx layer (DP_TX) invoked from
  3057. * hard_start_xmit in OSIF/HDD
  3058. *
  3059. * Return: NULL on success,
  3060. * nbuf when it fails to send
  3061. */
  3062. #ifdef MESH_MODE_SUPPORT
  3063. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3064. qdf_nbuf_t nbuf)
  3065. {
  3066. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3067. struct meta_hdr_s *mhdr;
  3068. qdf_nbuf_t nbuf_mesh = NULL;
  3069. qdf_nbuf_t nbuf_clone = NULL;
  3070. struct dp_vdev *vdev;
  3071. uint8_t no_enc_frame = 0;
  3072. nbuf_mesh = qdf_nbuf_unshare(nbuf);
  3073. if (!nbuf_mesh) {
  3074. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3075. "qdf_nbuf_unshare failed");
  3076. return nbuf;
  3077. }
  3078. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_MESH);
  3079. if (!vdev) {
  3080. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3081. "vdev is NULL for vdev_id %d", vdev_id);
  3082. return nbuf;
  3083. }
  3084. nbuf = nbuf_mesh;
  3085. mhdr = (struct meta_hdr_s *)qdf_nbuf_data(nbuf);
  3086. if ((vdev->sec_type != cdp_sec_type_none) &&
  3087. (mhdr->flags & METAHDR_FLAG_NOENCRYPT))
  3088. no_enc_frame = 1;
  3089. if (mhdr->flags & METAHDR_FLAG_NOQOS)
  3090. qdf_nbuf_set_priority(nbuf, HTT_TX_EXT_TID_NON_QOS_MCAST_BCAST);
  3091. if ((mhdr->flags & METAHDR_FLAG_INFO_UPDATED) &&
  3092. !no_enc_frame) {
  3093. nbuf_clone = qdf_nbuf_clone(nbuf);
  3094. if (!nbuf_clone) {
  3095. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3096. "qdf_nbuf_clone failed");
  3097. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3098. return nbuf;
  3099. }
  3100. qdf_nbuf_set_tx_ftype(nbuf_clone, CB_FTYPE_MESH_TX_INFO);
  3101. }
  3102. if (nbuf_clone) {
  3103. if (!dp_tx_send(soc_hdl, vdev_id, nbuf_clone)) {
  3104. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3105. } else {
  3106. qdf_nbuf_free(nbuf_clone);
  3107. }
  3108. }
  3109. if (no_enc_frame)
  3110. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_MESH_TX_INFO);
  3111. else
  3112. qdf_nbuf_set_tx_ftype(nbuf, CB_FTYPE_INVALID);
  3113. nbuf = dp_tx_send(soc_hdl, vdev_id, nbuf);
  3114. if ((!nbuf) && no_enc_frame) {
  3115. DP_STATS_INC(vdev, tx_i.mesh.exception_fw, 1);
  3116. }
  3117. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_MESH);
  3118. return nbuf;
  3119. }
  3120. #else
  3121. qdf_nbuf_t dp_tx_send_mesh(struct cdp_soc_t *soc, uint8_t vdev_id,
  3122. qdf_nbuf_t nbuf)
  3123. {
  3124. return dp_tx_send(soc, vdev_id, nbuf);
  3125. }
  3126. #endif
  3127. #ifdef QCA_DP_TX_NBUF_AND_NBUF_DATA_PREFETCH
  3128. static inline
  3129. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3130. {
  3131. if (nbuf) {
  3132. qdf_prefetch(&nbuf->len);
  3133. qdf_prefetch(&nbuf->data);
  3134. }
  3135. }
  3136. #else
  3137. static inline
  3138. void dp_tx_prefetch_nbuf_data(qdf_nbuf_t nbuf)
  3139. {
  3140. }
  3141. #endif
  3142. #ifdef DP_UMAC_HW_RESET_SUPPORT
  3143. /*
  3144. * dp_tx_drop() - Drop the frame on a given VAP
  3145. * @soc: DP soc handle
  3146. * @vdev_id: id of DP vdev handle
  3147. * @nbuf: skb
  3148. *
  3149. * Drop all the incoming packets
  3150. *
  3151. * Return: nbuf
  3152. *
  3153. */
  3154. qdf_nbuf_t dp_tx_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3155. qdf_nbuf_t nbuf)
  3156. {
  3157. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3158. struct dp_vdev *vdev = NULL;
  3159. vdev = soc->vdev_id_map[vdev_id];
  3160. if (qdf_unlikely(!vdev))
  3161. return nbuf;
  3162. DP_STATS_INC(vdev, tx_i.dropped.drop_ingress, 1);
  3163. return nbuf;
  3164. }
  3165. /*
  3166. * dp_tx_exc_drop() - Drop the frame on a given VAP
  3167. * @soc: DP soc handle
  3168. * @vdev_id: id of DP vdev handle
  3169. * @nbuf: skb
  3170. * @tx_exc_metadata: Handle that holds exception path meta data
  3171. *
  3172. * Drop all the incoming packets
  3173. *
  3174. * Return: nbuf
  3175. *
  3176. */
  3177. qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3178. qdf_nbuf_t nbuf,
  3179. struct cdp_tx_exception_metadata *tx_exc_metadata)
  3180. {
  3181. return dp_tx_drop(soc_hdl, vdev_id, nbuf);
  3182. }
  3183. #endif
  3184. /*
  3185. * dp_tx_send() - Transmit a frame on a given VAP
  3186. * @soc: DP soc handle
  3187. * @vdev_id: id of DP vdev handle
  3188. * @nbuf: skb
  3189. *
  3190. * Entry point for Core Tx layer (DP_TX) invoked from
  3191. * hard_start_xmit in OSIF/HDD or from dp_rx_process for intravap forwarding
  3192. * cases
  3193. *
  3194. * Return: NULL on success,
  3195. * nbuf when it fails to send
  3196. */
  3197. qdf_nbuf_t dp_tx_send(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  3198. qdf_nbuf_t nbuf)
  3199. {
  3200. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3201. uint16_t peer_id = HTT_INVALID_PEER;
  3202. /*
  3203. * doing a memzero is causing additional function call overhead
  3204. * so doing static stack clearing
  3205. */
  3206. struct dp_tx_msdu_info_s msdu_info = {0};
  3207. struct dp_vdev *vdev = NULL;
  3208. qdf_nbuf_t end_nbuf = NULL;
  3209. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3210. return nbuf;
  3211. /*
  3212. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3213. * this in per packet path.
  3214. *
  3215. * As in this path vdev memory is already protected with netdev
  3216. * tx lock
  3217. */
  3218. vdev = soc->vdev_id_map[vdev_id];
  3219. if (qdf_unlikely(!vdev))
  3220. return nbuf;
  3221. /*
  3222. * Set Default Host TID value to invalid TID
  3223. * (TID override disabled)
  3224. */
  3225. msdu_info.tid = HTT_TX_EXT_TID_INVALID;
  3226. DP_STATS_INC_PKT(vdev, tx_i.rcvd, 1, qdf_nbuf_headlen(nbuf));
  3227. if (qdf_unlikely(vdev->mesh_vdev)) {
  3228. qdf_nbuf_t nbuf_mesh = dp_tx_extract_mesh_meta_data(vdev, nbuf,
  3229. &msdu_info);
  3230. if (!nbuf_mesh) {
  3231. dp_verbose_debug("Extracting mesh metadata failed");
  3232. return nbuf;
  3233. }
  3234. nbuf = nbuf_mesh;
  3235. }
  3236. /*
  3237. * Get HW Queue to use for this frame.
  3238. * TCL supports upto 4 DMA rings, out of which 3 rings are
  3239. * dedicated for data and 1 for command.
  3240. * "queue_id" maps to one hardware ring.
  3241. * With each ring, we also associate a unique Tx descriptor pool
  3242. * to minimize lock contention for these resources.
  3243. */
  3244. dp_tx_get_queue(vdev, nbuf, &msdu_info.tx_queue);
  3245. DP_STATS_INC(vdev, tx_i.rcvd_per_core[msdu_info.tx_queue.desc_pool_id],
  3246. 1);
  3247. /*
  3248. * TCL H/W supports 2 DSCP-TID mapping tables.
  3249. * Table 1 - Default DSCP-TID mapping table
  3250. * Table 2 - 1 DSCP-TID override table
  3251. *
  3252. * If we need a different DSCP-TID mapping for this vap,
  3253. * call tid_classify to extract DSCP/ToS from frame and
  3254. * map to a TID and store in msdu_info. This is later used
  3255. * to fill in TCL Input descriptor (per-packet TID override).
  3256. */
  3257. dp_tx_classify_tid(vdev, nbuf, &msdu_info);
  3258. /*
  3259. * Classify the frame and call corresponding
  3260. * "prepare" function which extracts the segment (TSO)
  3261. * and fragmentation information (for TSO , SG, ME, or Raw)
  3262. * into MSDU_INFO structure which is later used to fill
  3263. * SW and HW descriptors.
  3264. */
  3265. if (qdf_nbuf_is_tso(nbuf)) {
  3266. dp_verbose_debug("TSO frame %pK", vdev);
  3267. DP_STATS_INC_PKT(vdev->pdev, tso_stats.num_tso_pkts, 1,
  3268. qdf_nbuf_len(nbuf));
  3269. if (dp_tx_prepare_tso(vdev, nbuf, &msdu_info)) {
  3270. DP_STATS_INC_PKT(vdev->pdev, tso_stats.dropped_host, 1,
  3271. qdf_nbuf_len(nbuf));
  3272. return nbuf;
  3273. }
  3274. goto send_multiple;
  3275. }
  3276. /* SG */
  3277. if (qdf_unlikely(qdf_nbuf_is_nonlinear(nbuf))) {
  3278. if (qdf_nbuf_get_nr_frags(nbuf) > DP_TX_MAX_NUM_FRAGS - 1) {
  3279. if (qdf_unlikely(qdf_nbuf_linearize(nbuf)))
  3280. return nbuf;
  3281. } else {
  3282. struct dp_tx_seg_info_s seg_info = {0};
  3283. if (qdf_unlikely(is_nbuf_frm_rmnet(nbuf, &msdu_info)))
  3284. goto send_single;
  3285. nbuf = dp_tx_prepare_sg(vdev, nbuf, &seg_info,
  3286. &msdu_info);
  3287. if (!nbuf)
  3288. return NULL;
  3289. dp_verbose_debug("non-TSO SG frame %pK", vdev);
  3290. DP_STATS_INC_PKT(vdev, tx_i.sg.sg_pkt, 1,
  3291. qdf_nbuf_len(nbuf));
  3292. goto send_multiple;
  3293. }
  3294. }
  3295. if (qdf_unlikely(!dp_tx_mcast_enhance(vdev, nbuf)))
  3296. return NULL;
  3297. if (qdf_unlikely(dp_tx_mcast_drop(vdev, nbuf)))
  3298. return nbuf;
  3299. /* RAW */
  3300. if (qdf_unlikely(vdev->tx_encap_type == htt_cmn_pkt_type_raw)) {
  3301. struct dp_tx_seg_info_s seg_info = {0};
  3302. nbuf = dp_tx_prepare_raw(vdev, nbuf, &seg_info, &msdu_info);
  3303. if (!nbuf)
  3304. return NULL;
  3305. dp_verbose_debug("Raw frame %pK", vdev);
  3306. goto send_multiple;
  3307. }
  3308. if (qdf_unlikely(vdev->nawds_enabled)) {
  3309. qdf_ether_header_t *eh = (qdf_ether_header_t *)
  3310. qdf_nbuf_data(nbuf);
  3311. if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
  3312. uint16_t sa_peer_id = DP_INVALID_PEER;
  3313. if (!soc->ast_offload_support) {
  3314. struct dp_ast_entry *ast_entry = NULL;
  3315. qdf_spin_lock_bh(&soc->ast_lock);
  3316. ast_entry = dp_peer_ast_hash_find_by_pdevid
  3317. (soc,
  3318. (uint8_t *)(eh->ether_shost),
  3319. vdev->pdev->pdev_id);
  3320. if (ast_entry)
  3321. sa_peer_id = ast_entry->peer_id;
  3322. qdf_spin_unlock_bh(&soc->ast_lock);
  3323. }
  3324. dp_tx_nawds_handler(soc, vdev, &msdu_info, nbuf,
  3325. sa_peer_id);
  3326. }
  3327. peer_id = DP_INVALID_PEER;
  3328. DP_STATS_INC_PKT(vdev, tx_i.nawds_mcast,
  3329. 1, qdf_nbuf_len(nbuf));
  3330. }
  3331. send_single:
  3332. /* Single linear frame */
  3333. /*
  3334. * If nbuf is a simple linear frame, use send_single function to
  3335. * prepare direct-buffer type TCL descriptor and enqueue to TCL
  3336. * SRNG. There is no need to setup a MSDU extension descriptor.
  3337. */
  3338. dp_tx_prefetch_nbuf_data(nbuf);
  3339. nbuf = dp_tx_send_msdu_single_wrapper(vdev, nbuf, &msdu_info,
  3340. peer_id, end_nbuf);
  3341. return nbuf;
  3342. send_multiple:
  3343. nbuf = dp_tx_send_msdu_multiple(vdev, nbuf, &msdu_info);
  3344. if (qdf_unlikely(nbuf && msdu_info.frm_type == dp_tx_frm_raw))
  3345. dp_tx_raw_prepare_unset(vdev->pdev->soc, nbuf);
  3346. return nbuf;
  3347. }
  3348. /**
  3349. * dp_tx_send_vdev_id_check() - Transmit a frame on a given VAP in special
  3350. * case to vaoid check in perpkt path.
  3351. * @soc: DP soc handle
  3352. * @vdev_id: id of DP vdev handle
  3353. * @nbuf: skb
  3354. *
  3355. * Entry point for Core Tx layer (DP_TX) invoked from
  3356. * hard_start_xmit in OSIF/HDD to transmit packet through dp_tx_send
  3357. * with special condition to avoid per pkt check in dp_tx_send
  3358. *
  3359. * Return: NULL on success,
  3360. * nbuf when it fails to send
  3361. */
  3362. qdf_nbuf_t dp_tx_send_vdev_id_check(struct cdp_soc_t *soc_hdl,
  3363. uint8_t vdev_id, qdf_nbuf_t nbuf)
  3364. {
  3365. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  3366. struct dp_vdev *vdev = NULL;
  3367. if (qdf_unlikely(vdev_id >= MAX_VDEV_CNT))
  3368. return nbuf;
  3369. /*
  3370. * dp_vdev_get_ref_by_id does does a atomic operation avoid using
  3371. * this in per packet path.
  3372. *
  3373. * As in this path vdev memory is already protected with netdev
  3374. * tx lock
  3375. */
  3376. vdev = soc->vdev_id_map[vdev_id];
  3377. if (qdf_unlikely(!vdev))
  3378. return nbuf;
  3379. if (qdf_unlikely(dp_tx_per_pkt_vdev_id_check(nbuf, vdev)
  3380. == QDF_STATUS_E_FAILURE)) {
  3381. DP_STATS_INC(vdev, tx_i.dropped.fail_per_pkt_vdev_id_check, 1);
  3382. return nbuf;
  3383. }
  3384. return dp_tx_send(soc_hdl, vdev_id, nbuf);
  3385. }
  3386. #ifdef UMAC_SUPPORT_PROXY_ARP
  3387. /**
  3388. * dp_tx_proxy_arp() - Tx proxy arp handler
  3389. * @vdev: datapath vdev handle
  3390. * @buf: sk buffer
  3391. *
  3392. * Return: status
  3393. */
  3394. static inline
  3395. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3396. {
  3397. if (vdev->osif_proxy_arp)
  3398. return vdev->osif_proxy_arp(vdev->osif_vdev, nbuf);
  3399. /*
  3400. * when UMAC_SUPPORT_PROXY_ARP is defined, we expect
  3401. * osif_proxy_arp has a valid function pointer assigned
  3402. * to it
  3403. */
  3404. dp_tx_err("valid function pointer for osif_proxy_arp is expected!!\n");
  3405. return QDF_STATUS_NOT_INITIALIZED;
  3406. }
  3407. #else
  3408. /**
  3409. * dp_tx_proxy_arp() - Tx proxy arp handler
  3410. * @vdev: datapath vdev handle
  3411. * @buf: sk buffer
  3412. *
  3413. * This function always return 0 when UMAC_SUPPORT_PROXY_ARP
  3414. * is not defined.
  3415. *
  3416. * Return: status
  3417. */
  3418. static inline
  3419. int dp_tx_proxy_arp(struct dp_vdev *vdev, qdf_nbuf_t nbuf)
  3420. {
  3421. return QDF_STATUS_SUCCESS;
  3422. }
  3423. #endif
  3424. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
  3425. #ifdef WLAN_MCAST_MLO
  3426. static bool
  3427. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3428. struct dp_tx_desc_s *tx_desc,
  3429. qdf_nbuf_t nbuf,
  3430. uint8_t reinject_reason)
  3431. {
  3432. if (reinject_reason == HTT_TX_FW2WBM_REINJECT_REASON_MLO_MCAST) {
  3433. if (soc->arch_ops.dp_tx_mcast_handler)
  3434. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, nbuf);
  3435. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3436. return true;
  3437. }
  3438. return false;
  3439. }
  3440. #else /* WLAN_MCAST_MLO */
  3441. static inline bool
  3442. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3443. struct dp_tx_desc_s *tx_desc,
  3444. qdf_nbuf_t nbuf,
  3445. uint8_t reinject_reason)
  3446. {
  3447. return false;
  3448. }
  3449. #endif /* WLAN_MCAST_MLO */
  3450. #else
  3451. static inline bool
  3452. dp_tx_reinject_mlo_hdl(struct dp_soc *soc, struct dp_vdev *vdev,
  3453. struct dp_tx_desc_s *tx_desc,
  3454. qdf_nbuf_t nbuf,
  3455. uint8_t reinject_reason)
  3456. {
  3457. return false;
  3458. }
  3459. #endif
  3460. /**
  3461. * dp_tx_reinject_handler() - Tx Reinject Handler
  3462. * @soc: datapath soc handle
  3463. * @vdev: datapath vdev handle
  3464. * @tx_desc: software descriptor head pointer
  3465. * @status : Tx completion status from HTT descriptor
  3466. * @reinject_reason : reinject reason from HTT descriptor
  3467. *
  3468. * This function reinjects frames back to Target.
  3469. * Todo - Host queue needs to be added
  3470. *
  3471. * Return: none
  3472. */
  3473. void dp_tx_reinject_handler(struct dp_soc *soc,
  3474. struct dp_vdev *vdev,
  3475. struct dp_tx_desc_s *tx_desc,
  3476. uint8_t *status,
  3477. uint8_t reinject_reason)
  3478. {
  3479. struct dp_peer *peer = NULL;
  3480. uint32_t peer_id = HTT_INVALID_PEER;
  3481. qdf_nbuf_t nbuf = tx_desc->nbuf;
  3482. qdf_nbuf_t nbuf_copy = NULL;
  3483. struct dp_tx_msdu_info_s msdu_info;
  3484. #ifdef WDS_VENDOR_EXTENSION
  3485. int is_mcast = 0, is_ucast = 0;
  3486. int num_peers_3addr = 0;
  3487. qdf_ether_header_t *eth_hdr = (qdf_ether_header_t *)(qdf_nbuf_data(nbuf));
  3488. struct ieee80211_frame_addr4 *wh = (struct ieee80211_frame_addr4 *)(qdf_nbuf_data(nbuf));
  3489. #endif
  3490. struct dp_txrx_peer *txrx_peer;
  3491. qdf_assert(vdev);
  3492. dp_tx_debug("Tx reinject path");
  3493. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  3494. qdf_nbuf_len(tx_desc->nbuf));
  3495. if (dp_tx_reinject_mlo_hdl(soc, vdev, tx_desc, nbuf, reinject_reason))
  3496. return;
  3497. #ifdef WDS_VENDOR_EXTENSION
  3498. if (qdf_unlikely(vdev->tx_encap_type != htt_cmn_pkt_type_raw)) {
  3499. is_mcast = (IS_MULTICAST(wh->i_addr1)) ? 1 : 0;
  3500. } else {
  3501. is_mcast = (IS_MULTICAST(eth_hdr->ether_dhost)) ? 1 : 0;
  3502. }
  3503. is_ucast = !is_mcast;
  3504. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3505. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3506. txrx_peer = dp_get_txrx_peer(peer);
  3507. if (!txrx_peer || txrx_peer->bss_peer)
  3508. continue;
  3509. /* Detect wds peers that use 3-addr framing for mcast.
  3510. * if there are any, the bss_peer is used to send the
  3511. * the mcast frame using 3-addr format. all wds enabled
  3512. * peers that use 4-addr framing for mcast frames will
  3513. * be duplicated and sent as 4-addr frames below.
  3514. */
  3515. if (!txrx_peer->wds_enabled ||
  3516. !txrx_peer->wds_ecm.wds_tx_mcast_4addr) {
  3517. num_peers_3addr = 1;
  3518. break;
  3519. }
  3520. }
  3521. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3522. #endif
  3523. if (qdf_unlikely(vdev->mesh_vdev)) {
  3524. DP_TX_FREE_SINGLE_BUF(vdev->pdev->soc, tx_desc->nbuf);
  3525. } else {
  3526. qdf_spin_lock_bh(&vdev->peer_list_lock);
  3527. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3528. txrx_peer = dp_get_txrx_peer(peer);
  3529. if (!txrx_peer)
  3530. continue;
  3531. if ((txrx_peer->peer_id != HTT_INVALID_PEER) &&
  3532. #ifdef WDS_VENDOR_EXTENSION
  3533. /*
  3534. * . if 3-addr STA, then send on BSS Peer
  3535. * . if Peer WDS enabled and accept 4-addr mcast,
  3536. * send mcast on that peer only
  3537. * . if Peer WDS enabled and accept 4-addr ucast,
  3538. * send ucast on that peer only
  3539. */
  3540. ((txrx_peer->bss_peer && num_peers_3addr && is_mcast) ||
  3541. (txrx_peer->wds_enabled &&
  3542. ((is_mcast && txrx_peer->wds_ecm.wds_tx_mcast_4addr) ||
  3543. (is_ucast &&
  3544. txrx_peer->wds_ecm.wds_tx_ucast_4addr))))) {
  3545. #else
  3546. (txrx_peer->bss_peer &&
  3547. (dp_tx_proxy_arp(vdev, nbuf) == QDF_STATUS_SUCCESS))) {
  3548. #endif
  3549. peer_id = DP_INVALID_PEER;
  3550. nbuf_copy = qdf_nbuf_copy(nbuf);
  3551. if (!nbuf_copy) {
  3552. dp_tx_debug("nbuf copy failed");
  3553. break;
  3554. }
  3555. qdf_mem_zero(&msdu_info, sizeof(msdu_info));
  3556. dp_tx_get_queue(vdev, nbuf,
  3557. &msdu_info.tx_queue);
  3558. nbuf_copy = dp_tx_send_msdu_single(vdev,
  3559. nbuf_copy,
  3560. &msdu_info,
  3561. peer_id,
  3562. NULL);
  3563. if (nbuf_copy) {
  3564. dp_tx_debug("pkt send failed");
  3565. qdf_nbuf_free(nbuf_copy);
  3566. }
  3567. }
  3568. }
  3569. qdf_spin_unlock_bh(&vdev->peer_list_lock);
  3570. qdf_nbuf_unmap_nbytes_single(vdev->osdev, nbuf,
  3571. QDF_DMA_TO_DEVICE, nbuf->len);
  3572. qdf_nbuf_free(nbuf);
  3573. }
  3574. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3575. }
  3576. /**
  3577. * dp_tx_inspect_handler() - Tx Inspect Handler
  3578. * @soc: datapath soc handle
  3579. * @vdev: datapath vdev handle
  3580. * @tx_desc: software descriptor head pointer
  3581. * @status : Tx completion status from HTT descriptor
  3582. *
  3583. * Handles Tx frames sent back to Host for inspection
  3584. * (ProxyARP)
  3585. *
  3586. * Return: none
  3587. */
  3588. void dp_tx_inspect_handler(struct dp_soc *soc,
  3589. struct dp_vdev *vdev,
  3590. struct dp_tx_desc_s *tx_desc,
  3591. uint8_t *status)
  3592. {
  3593. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3594. "%s Tx inspect path",
  3595. __func__);
  3596. DP_STATS_INC_PKT(vdev, tx_i.inspect_pkts, 1,
  3597. qdf_nbuf_len(tx_desc->nbuf));
  3598. DP_TX_FREE_SINGLE_BUF(soc, tx_desc->nbuf);
  3599. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  3600. }
  3601. #ifdef MESH_MODE_SUPPORT
  3602. /**
  3603. * dp_tx_comp_fill_tx_completion_stats() - Fill per packet Tx completion stats
  3604. * in mesh meta header
  3605. * @tx_desc: software descriptor head pointer
  3606. * @ts: pointer to tx completion stats
  3607. * Return: none
  3608. */
  3609. static
  3610. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3611. struct hal_tx_completion_status *ts)
  3612. {
  3613. qdf_nbuf_t netbuf = tx_desc->nbuf;
  3614. if (!tx_desc->msdu_ext_desc) {
  3615. if (qdf_nbuf_pull_head(netbuf, tx_desc->pkt_offset) == NULL) {
  3616. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  3617. "netbuf %pK offset %d",
  3618. netbuf, tx_desc->pkt_offset);
  3619. return;
  3620. }
  3621. }
  3622. }
  3623. #else
  3624. static
  3625. void dp_tx_comp_fill_tx_completion_stats(struct dp_tx_desc_s *tx_desc,
  3626. struct hal_tx_completion_status *ts)
  3627. {
  3628. }
  3629. #endif
  3630. #ifdef CONFIG_SAWF
  3631. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3632. struct dp_vdev *vdev,
  3633. struct dp_txrx_peer *txrx_peer,
  3634. struct dp_tx_desc_s *tx_desc,
  3635. struct hal_tx_completion_status *ts,
  3636. uint8_t tid)
  3637. {
  3638. dp_sawf_tx_compl_update_peer_stats(soc, vdev, txrx_peer, tx_desc,
  3639. ts, tid);
  3640. }
  3641. static void dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3642. uint32_t nw_delay,
  3643. uint32_t sw_delay,
  3644. uint32_t hw_delay)
  3645. {
  3646. dp_peer_tid_delay_avg(tx_delay,
  3647. nw_delay,
  3648. sw_delay,
  3649. hw_delay);
  3650. }
  3651. #else
  3652. static void dp_tx_update_peer_sawf_stats(struct dp_soc *soc,
  3653. struct dp_vdev *vdev,
  3654. struct dp_txrx_peer *txrx_peer,
  3655. struct dp_tx_desc_s *tx_desc,
  3656. struct hal_tx_completion_status *ts,
  3657. uint8_t tid)
  3658. {
  3659. }
  3660. static inline void
  3661. dp_tx_compute_delay_avg(struct cdp_delay_tx_stats *tx_delay,
  3662. uint32_t nw_delay, uint32_t sw_delay,
  3663. uint32_t hw_delay)
  3664. {
  3665. }
  3666. #endif
  3667. #ifdef QCA_PEER_EXT_STATS
  3668. #ifdef WLAN_CONFIG_TX_DELAY
  3669. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3670. struct dp_tx_desc_s *tx_desc,
  3671. struct hal_tx_completion_status *ts,
  3672. struct dp_vdev *vdev)
  3673. {
  3674. struct dp_soc *soc = vdev->pdev->soc;
  3675. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3676. int64_t timestamp_ingress, timestamp_hw_enqueue;
  3677. uint32_t sw_enqueue_delay, fwhw_transmit_delay = 0;
  3678. if (!ts->valid)
  3679. return;
  3680. timestamp_ingress = qdf_nbuf_get_timestamp_us(tx_desc->nbuf);
  3681. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3682. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3683. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3684. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3685. if (!soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3686. &fwhw_transmit_delay))
  3687. dp_hist_update_stats(&tx_delay->hwtx_delay,
  3688. fwhw_transmit_delay);
  3689. dp_tx_compute_delay_avg(tx_delay, 0, sw_enqueue_delay,
  3690. fwhw_transmit_delay);
  3691. }
  3692. #else
  3693. /*
  3694. * dp_tx_compute_tid_delay() - Compute per TID delay
  3695. * @stats: Per TID delay stats
  3696. * @tx_desc: Software Tx descriptor
  3697. * @ts: Tx completion status
  3698. * @vdev: vdev
  3699. *
  3700. * Compute the software enqueue and hw enqueue delays and
  3701. * update the respective histograms
  3702. *
  3703. * Return: void
  3704. */
  3705. static void dp_tx_compute_tid_delay(struct cdp_delay_tid_stats *stats,
  3706. struct dp_tx_desc_s *tx_desc,
  3707. struct hal_tx_completion_status *ts,
  3708. struct dp_vdev *vdev)
  3709. {
  3710. struct cdp_delay_tx_stats *tx_delay = &stats->tx_delay;
  3711. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3712. uint32_t sw_enqueue_delay, fwhw_transmit_delay;
  3713. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  3714. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  3715. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  3716. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  3717. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  3718. timestamp_hw_enqueue);
  3719. /*
  3720. * Update the Tx software enqueue delay and HW enque-Completion delay.
  3721. */
  3722. dp_hist_update_stats(&tx_delay->tx_swq_delay, sw_enqueue_delay);
  3723. dp_hist_update_stats(&tx_delay->hwtx_delay, fwhw_transmit_delay);
  3724. }
  3725. #endif
  3726. /*
  3727. * dp_tx_update_peer_delay_stats() - Update the peer delay stats
  3728. * @txrx_peer: DP peer context
  3729. * @tx_desc: Tx software descriptor
  3730. * @tid: Transmission ID
  3731. * @ring_id: Rx CPU context ID/CPU_ID
  3732. *
  3733. * Update the peer extended stats. These are enhanced other
  3734. * delay stats per msdu level.
  3735. *
  3736. * Return: void
  3737. */
  3738. static void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3739. struct dp_tx_desc_s *tx_desc,
  3740. struct hal_tx_completion_status *ts,
  3741. uint8_t ring_id)
  3742. {
  3743. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3744. struct dp_soc *soc = NULL;
  3745. struct dp_peer_delay_stats *delay_stats = NULL;
  3746. uint8_t tid;
  3747. soc = pdev->soc;
  3748. if (qdf_likely(!wlan_cfg_is_peer_ext_stats_enabled(soc->wlan_cfg_ctx)))
  3749. return;
  3750. tid = ts->tid;
  3751. delay_stats = txrx_peer->delay_stats;
  3752. qdf_assert(delay_stats);
  3753. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3754. /*
  3755. * For non-TID packets use the TID 9
  3756. */
  3757. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3758. tid = CDP_MAX_DATA_TIDS - 1;
  3759. dp_tx_compute_tid_delay(&delay_stats->delay_tid_stats[tid][ring_id],
  3760. tx_desc, ts, txrx_peer->vdev);
  3761. }
  3762. #else
  3763. static inline
  3764. void dp_tx_update_peer_delay_stats(struct dp_txrx_peer *txrx_peer,
  3765. struct dp_tx_desc_s *tx_desc,
  3766. struct hal_tx_completion_status *ts,
  3767. uint8_t ring_id)
  3768. {
  3769. }
  3770. #endif
  3771. #ifdef WLAN_PEER_JITTER
  3772. /*
  3773. * dp_tx_jitter_get_avg_jitter() - compute the average jitter
  3774. * @curr_delay: Current delay
  3775. * @prev_Delay: Previous delay
  3776. * @avg_jitter: Average Jitter
  3777. * Return: Newly Computed Average Jitter
  3778. */
  3779. static uint32_t dp_tx_jitter_get_avg_jitter(uint32_t curr_delay,
  3780. uint32_t prev_delay,
  3781. uint32_t avg_jitter)
  3782. {
  3783. uint32_t curr_jitter;
  3784. int32_t jitter_diff;
  3785. curr_jitter = qdf_abs(curr_delay - prev_delay);
  3786. if (!avg_jitter)
  3787. return curr_jitter;
  3788. jitter_diff = curr_jitter - avg_jitter;
  3789. if (jitter_diff < 0)
  3790. avg_jitter = avg_jitter -
  3791. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3792. else
  3793. avg_jitter = avg_jitter +
  3794. (qdf_abs(jitter_diff) >> DP_AVG_JITTER_WEIGHT_DENOM);
  3795. return avg_jitter;
  3796. }
  3797. /*
  3798. * dp_tx_jitter_get_avg_delay() - compute the average delay
  3799. * @curr_delay: Current delay
  3800. * @avg_Delay: Average delay
  3801. * Return: Newly Computed Average Delay
  3802. */
  3803. static uint32_t dp_tx_jitter_get_avg_delay(uint32_t curr_delay,
  3804. uint32_t avg_delay)
  3805. {
  3806. int32_t delay_diff;
  3807. if (!avg_delay)
  3808. return curr_delay;
  3809. delay_diff = curr_delay - avg_delay;
  3810. if (delay_diff < 0)
  3811. avg_delay = avg_delay - (qdf_abs(delay_diff) >>
  3812. DP_AVG_DELAY_WEIGHT_DENOM);
  3813. else
  3814. avg_delay = avg_delay + (qdf_abs(delay_diff) >>
  3815. DP_AVG_DELAY_WEIGHT_DENOM);
  3816. return avg_delay;
  3817. }
  3818. #ifdef WLAN_CONFIG_TX_DELAY
  3819. /*
  3820. * dp_tx_compute_cur_delay() - get the current delay
  3821. * @soc: soc handle
  3822. * @vdev: vdev structure for data path state
  3823. * @ts: Tx completion status
  3824. * @curr_delay: current delay
  3825. * @tx_desc: tx descriptor
  3826. * Return: void
  3827. */
  3828. static
  3829. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3830. struct dp_vdev *vdev,
  3831. struct hal_tx_completion_status *ts,
  3832. uint32_t *curr_delay,
  3833. struct dp_tx_desc_s *tx_desc)
  3834. {
  3835. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3836. if (soc->arch_ops.dp_tx_compute_hw_delay)
  3837. status = soc->arch_ops.dp_tx_compute_hw_delay(soc, vdev, ts,
  3838. curr_delay);
  3839. return status;
  3840. }
  3841. #else
  3842. static
  3843. QDF_STATUS dp_tx_compute_cur_delay(struct dp_soc *soc,
  3844. struct dp_vdev *vdev,
  3845. struct hal_tx_completion_status *ts,
  3846. uint32_t *curr_delay,
  3847. struct dp_tx_desc_s *tx_desc)
  3848. {
  3849. int64_t current_timestamp, timestamp_hw_enqueue;
  3850. current_timestamp = qdf_ktime_to_us(qdf_ktime_real_get());
  3851. timestamp_hw_enqueue = qdf_ktime_to_us(tx_desc->timestamp);
  3852. *curr_delay = (uint32_t)(current_timestamp - timestamp_hw_enqueue);
  3853. return QDF_STATUS_SUCCESS;
  3854. }
  3855. #endif
  3856. /* dp_tx_compute_tid_jitter() - compute per tid per ring jitter
  3857. * @jiiter - per tid per ring jitter stats
  3858. * @ts: Tx completion status
  3859. * @vdev - vdev structure for data path state
  3860. * @tx_desc - tx descriptor
  3861. * Return: void
  3862. */
  3863. static void dp_tx_compute_tid_jitter(struct cdp_peer_tid_stats *jitter,
  3864. struct hal_tx_completion_status *ts,
  3865. struct dp_vdev *vdev,
  3866. struct dp_tx_desc_s *tx_desc)
  3867. {
  3868. uint32_t curr_delay, avg_delay, avg_jitter, prev_delay;
  3869. struct dp_soc *soc = vdev->pdev->soc;
  3870. QDF_STATUS status = QDF_STATUS_E_FAILURE;
  3871. if (ts->status != HAL_TX_TQM_RR_FRAME_ACKED) {
  3872. jitter->tx_drop += 1;
  3873. return;
  3874. }
  3875. status = dp_tx_compute_cur_delay(soc, vdev, ts, &curr_delay,
  3876. tx_desc);
  3877. if (QDF_IS_STATUS_SUCCESS(status)) {
  3878. avg_delay = jitter->tx_avg_delay;
  3879. avg_jitter = jitter->tx_avg_jitter;
  3880. prev_delay = jitter->tx_prev_delay;
  3881. avg_jitter = dp_tx_jitter_get_avg_jitter(curr_delay,
  3882. prev_delay,
  3883. avg_jitter);
  3884. avg_delay = dp_tx_jitter_get_avg_delay(curr_delay, avg_delay);
  3885. jitter->tx_avg_delay = avg_delay;
  3886. jitter->tx_avg_jitter = avg_jitter;
  3887. jitter->tx_prev_delay = curr_delay;
  3888. jitter->tx_total_success += 1;
  3889. } else if (status == QDF_STATUS_E_FAILURE) {
  3890. jitter->tx_avg_err += 1;
  3891. }
  3892. }
  3893. /* dp_tx_update_peer_jitter_stats() - Update the peer jitter stats
  3894. * @txrx_peer: DP peer context
  3895. * @tx_desc: Tx software descriptor
  3896. * @ts: Tx completion status
  3897. * @ring_id: Rx CPU context ID/CPU_ID
  3898. * Return: void
  3899. */
  3900. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3901. struct dp_tx_desc_s *tx_desc,
  3902. struct hal_tx_completion_status *ts,
  3903. uint8_t ring_id)
  3904. {
  3905. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  3906. struct dp_soc *soc = pdev->soc;
  3907. struct cdp_peer_tid_stats *jitter_stats = NULL;
  3908. uint8_t tid;
  3909. struct cdp_peer_tid_stats *rx_tid = NULL;
  3910. if (qdf_likely(!wlan_cfg_is_peer_jitter_stats_enabled(soc->wlan_cfg_ctx)))
  3911. return;
  3912. tid = ts->tid;
  3913. jitter_stats = txrx_peer->jitter_stats;
  3914. qdf_assert_always(jitter_stats);
  3915. qdf_assert(ring < CDP_MAX_TXRX_CTX);
  3916. /*
  3917. * For non-TID packets use the TID 9
  3918. */
  3919. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  3920. tid = CDP_MAX_DATA_TIDS - 1;
  3921. rx_tid = &jitter_stats[tid * CDP_MAX_TXRX_CTX + ring_id];
  3922. dp_tx_compute_tid_jitter(rx_tid,
  3923. ts, txrx_peer->vdev, tx_desc);
  3924. }
  3925. #else
  3926. static void dp_tx_update_peer_jitter_stats(struct dp_txrx_peer *txrx_peer,
  3927. struct dp_tx_desc_s *tx_desc,
  3928. struct hal_tx_completion_status *ts,
  3929. uint8_t ring_id)
  3930. {
  3931. }
  3932. #endif
  3933. #ifdef HW_TX_DELAY_STATS_ENABLE
  3934. /**
  3935. * dp_update_tx_delay_stats() - update the delay stats
  3936. * @vdev: vdev handle
  3937. * @delay: delay in ms or us based on the flag delay_in_us
  3938. * @tid: tid value
  3939. * @mode: type of tx delay mode
  3940. * @ring id: ring number
  3941. * @delay_in_us: flag to indicate whether the delay is in ms or us
  3942. *
  3943. * Return: none
  3944. */
  3945. static inline
  3946. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3947. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3948. {
  3949. struct cdp_tid_tx_stats *tstats =
  3950. &vdev->stats.tid_tx_stats[ring_id][tid];
  3951. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3952. delay_in_us);
  3953. }
  3954. #else
  3955. static inline
  3956. void dp_update_tx_delay_stats(struct dp_vdev *vdev, uint32_t delay, uint8_t tid,
  3957. uint8_t mode, uint8_t ring_id, bool delay_in_us)
  3958. {
  3959. struct cdp_tid_tx_stats *tstats =
  3960. &vdev->pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  3961. dp_update_delay_stats(tstats, NULL, delay, tid, mode, ring_id,
  3962. delay_in_us);
  3963. }
  3964. #endif
  3965. /**
  3966. * dp_tx_compute_delay() - Compute and fill in all timestamps
  3967. * to pass in correct fields
  3968. *
  3969. * @vdev: pdev handle
  3970. * @tx_desc: tx descriptor
  3971. * @tid: tid value
  3972. * @ring_id: TCL or WBM ring number for transmit path
  3973. * Return: none
  3974. */
  3975. void dp_tx_compute_delay(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
  3976. uint8_t tid, uint8_t ring_id)
  3977. {
  3978. int64_t current_timestamp, timestamp_ingress, timestamp_hw_enqueue;
  3979. uint32_t sw_enqueue_delay, fwhw_transmit_delay, interframe_delay;
  3980. uint32_t fwhw_transmit_delay_us;
  3981. if (qdf_likely(!vdev->pdev->delay_stats_flag) &&
  3982. qdf_likely(!dp_is_vdev_tx_delay_stats_enabled(vdev)))
  3983. return;
  3984. if (dp_is_vdev_tx_delay_stats_enabled(vdev)) {
  3985. fwhw_transmit_delay_us =
  3986. qdf_ktime_to_us(qdf_ktime_real_get()) -
  3987. qdf_ktime_to_us(tx_desc->timestamp);
  3988. /*
  3989. * Delay between packet enqueued to HW and Tx completion in us
  3990. */
  3991. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay_us, tid,
  3992. CDP_DELAY_STATS_FW_HW_TRANSMIT,
  3993. ring_id, true);
  3994. /*
  3995. * For MCL, only enqueue to completion delay is required
  3996. * so return if the vdev flag is enabled.
  3997. */
  3998. return;
  3999. }
  4000. current_timestamp = qdf_ktime_to_ms(qdf_ktime_real_get());
  4001. timestamp_hw_enqueue = qdf_ktime_to_ms(tx_desc->timestamp);
  4002. fwhw_transmit_delay = (uint32_t)(current_timestamp -
  4003. timestamp_hw_enqueue);
  4004. /*
  4005. * Delay between packet enqueued to HW and Tx completion in ms
  4006. */
  4007. dp_update_tx_delay_stats(vdev, fwhw_transmit_delay, tid,
  4008. CDP_DELAY_STATS_FW_HW_TRANSMIT, ring_id,
  4009. false);
  4010. timestamp_ingress = qdf_nbuf_get_timestamp(tx_desc->nbuf);
  4011. sw_enqueue_delay = (uint32_t)(timestamp_hw_enqueue - timestamp_ingress);
  4012. interframe_delay = (uint32_t)(timestamp_ingress -
  4013. vdev->prev_tx_enq_tstamp);
  4014. /*
  4015. * Delay in software enqueue
  4016. */
  4017. dp_update_tx_delay_stats(vdev, sw_enqueue_delay, tid,
  4018. CDP_DELAY_STATS_SW_ENQ, ring_id,
  4019. false);
  4020. /*
  4021. * Update interframe delay stats calculated at hardstart receive point.
  4022. * Value of vdev->prev_tx_enq_tstamp will be 0 for 1st frame, so
  4023. * interframe delay will not be calculate correctly for 1st frame.
  4024. * On the other side, this will help in avoiding extra per packet check
  4025. * of !vdev->prev_tx_enq_tstamp.
  4026. */
  4027. dp_update_tx_delay_stats(vdev, interframe_delay, tid,
  4028. CDP_DELAY_STATS_TX_INTERFRAME, ring_id,
  4029. false);
  4030. vdev->prev_tx_enq_tstamp = timestamp_ingress;
  4031. }
  4032. #ifdef DISABLE_DP_STATS
  4033. static
  4034. inline void dp_update_no_ack_stats(qdf_nbuf_t nbuf,
  4035. struct dp_txrx_peer *txrx_peer)
  4036. {
  4037. }
  4038. #else
  4039. static inline void
  4040. dp_update_no_ack_stats(qdf_nbuf_t nbuf, struct dp_txrx_peer *txrx_peer)
  4041. {
  4042. enum qdf_proto_subtype subtype = QDF_PROTO_INVALID;
  4043. DPTRACE(qdf_dp_track_noack_check(nbuf, &subtype));
  4044. if (subtype != QDF_PROTO_INVALID)
  4045. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.no_ack_count[subtype],
  4046. 1);
  4047. }
  4048. #endif
  4049. #ifndef QCA_ENHANCED_STATS_SUPPORT
  4050. #ifdef DP_PEER_EXTENDED_API
  4051. static inline uint8_t
  4052. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4053. {
  4054. return txrx_peer->mpdu_retry_threshold;
  4055. }
  4056. #else
  4057. static inline uint8_t
  4058. dp_tx_get_mpdu_retry_threshold(struct dp_txrx_peer *txrx_peer)
  4059. {
  4060. return 0;
  4061. }
  4062. #endif
  4063. /**
  4064. * dp_tx_update_peer_extd_stats()- Update Tx extended path stats for peer
  4065. *
  4066. * @ts: Tx compltion status
  4067. * @txrx_peer: datapath txrx_peer handle
  4068. *
  4069. * Return: void
  4070. */
  4071. static inline void
  4072. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4073. struct dp_txrx_peer *txrx_peer)
  4074. {
  4075. uint8_t mcs, pkt_type, dst_mcs_idx;
  4076. uint8_t retry_threshold = dp_tx_get_mpdu_retry_threshold(txrx_peer);
  4077. mcs = ts->mcs;
  4078. pkt_type = ts->pkt_type;
  4079. /* do HW to SW pkt type conversion */
  4080. pkt_type = (pkt_type >= HAL_DOT11_MAX ? DOT11_MAX :
  4081. hal_2_dp_pkt_type_map[pkt_type]);
  4082. dst_mcs_idx = dp_get_mcs_array_index_by_pkt_type_mcs(pkt_type, mcs);
  4083. if (MCS_INVALID_ARRAY_INDEX != dst_mcs_idx)
  4084. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4085. tx.pkt_type[pkt_type].mcs_count[dst_mcs_idx],
  4086. 1);
  4087. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.sgi_count[ts->sgi], 1);
  4088. DP_PEER_EXTD_STATS_INC(txrx_peer, tx.bw[ts->bw], 1);
  4089. DP_PEER_EXTD_STATS_UPD(txrx_peer, tx.last_ack_rssi, ts->ack_frame_rssi);
  4090. DP_PEER_EXTD_STATS_INC(txrx_peer,
  4091. tx.wme_ac_type[TID_TO_WME_AC(ts->tid)], 1);
  4092. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.stbc, 1, ts->stbc);
  4093. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.ldpc, 1, ts->ldpc);
  4094. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries, 1, ts->transmit_cnt > 1);
  4095. if (ts->first_msdu) {
  4096. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.retries_mpdu, 1,
  4097. ts->transmit_cnt > 1);
  4098. if (!retry_threshold)
  4099. return;
  4100. DP_PEER_EXTD_STATS_INCC(txrx_peer, tx.mpdu_success_with_retries,
  4101. qdf_do_div(ts->transmit_cnt,
  4102. retry_threshold),
  4103. ts->transmit_cnt > retry_threshold);
  4104. }
  4105. }
  4106. #else
  4107. static inline void
  4108. dp_tx_update_peer_extd_stats(struct hal_tx_completion_status *ts,
  4109. struct dp_txrx_peer *txrx_peer)
  4110. {
  4111. }
  4112. #endif
  4113. /**
  4114. * dp_tx_update_peer_stats() - Update peer stats from Tx completion indications
  4115. * per wbm ring
  4116. *
  4117. * @tx_desc: software descriptor head pointer
  4118. * @ts: Tx completion status
  4119. * @peer: peer handle
  4120. * @ring_id: ring number
  4121. *
  4122. * Return: None
  4123. */
  4124. static inline void
  4125. dp_tx_update_peer_stats(struct dp_tx_desc_s *tx_desc,
  4126. struct hal_tx_completion_status *ts,
  4127. struct dp_txrx_peer *txrx_peer, uint8_t ring_id)
  4128. {
  4129. struct dp_pdev *pdev = txrx_peer->vdev->pdev;
  4130. uint8_t tid = ts->tid;
  4131. uint32_t length;
  4132. struct cdp_tid_tx_stats *tid_stats;
  4133. if (!pdev)
  4134. return;
  4135. if (qdf_unlikely(tid >= CDP_MAX_DATA_TIDS))
  4136. tid = CDP_MAX_DATA_TIDS - 1;
  4137. tid_stats = &pdev->stats.tid_stats.tid_tx_stats[ring_id][tid];
  4138. if (ts->release_src != HAL_TX_COMP_RELEASE_SOURCE_TQM) {
  4139. dp_err_rl("Release source:%d is not from TQM", ts->release_src);
  4140. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.release_src_not_tqm, 1);
  4141. return;
  4142. }
  4143. length = qdf_nbuf_len(tx_desc->nbuf);
  4144. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4145. if (qdf_unlikely(pdev->delay_stats_flag) ||
  4146. qdf_unlikely(dp_is_vdev_tx_delay_stats_enabled(txrx_peer->vdev)))
  4147. dp_tx_compute_delay(txrx_peer->vdev, tx_desc, tid, ring_id);
  4148. if (ts->status < CDP_MAX_TX_TQM_STATUS) {
  4149. tid_stats->tqm_status_cnt[ts->status]++;
  4150. }
  4151. if (qdf_likely(ts->status == HAL_TX_TQM_RR_FRAME_ACKED)) {
  4152. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.retry_count, 1,
  4153. ts->transmit_cnt > 1);
  4154. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.multiple_retry_count,
  4155. 1, ts->transmit_cnt > 2);
  4156. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.ofdma, 1, ts->ofdma);
  4157. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.amsdu_cnt, 1,
  4158. ts->msdu_part_of_amsdu);
  4159. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.non_amsdu_cnt, 1,
  4160. !ts->msdu_part_of_amsdu);
  4161. txrx_peer->stats.per_pkt_stats.tx.last_tx_ts =
  4162. qdf_system_ticks();
  4163. dp_tx_update_peer_extd_stats(ts, txrx_peer);
  4164. return;
  4165. }
  4166. /*
  4167. * tx_failed is ideally supposed to be updated from HTT ppdu
  4168. * completion stats. But in IPQ807X/IPQ6018 chipsets owing to
  4169. * hw limitation there are no completions for failed cases.
  4170. * Hence updating tx_failed from data path. Please note that
  4171. * if tx_failed is fixed to be from ppdu, then this has to be
  4172. * removed
  4173. */
  4174. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4175. DP_PEER_PER_PKT_STATS_INCC(txrx_peer, tx.failed_retry_count, 1,
  4176. ts->transmit_cnt > DP_RETRY_COUNT);
  4177. dp_update_no_ack_stats(tx_desc->nbuf, txrx_peer);
  4178. if (ts->status == HAL_TX_TQM_RR_REM_CMD_AGED) {
  4179. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.age_out, 1);
  4180. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_REM) {
  4181. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.dropped.fw_rem, 1,
  4182. length);
  4183. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_NOTX) {
  4184. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_notx, 1);
  4185. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TX) {
  4186. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_rem_tx, 1);
  4187. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON1) {
  4188. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason1, 1);
  4189. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON2) {
  4190. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason2, 1);
  4191. } else if (ts->status == HAL_TX_TQM_RR_FW_REASON3) {
  4192. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.fw_reason3, 1);
  4193. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE) {
  4194. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4195. tx.dropped.fw_rem_queue_disable, 1);
  4196. } else if (ts->status == HAL_TX_TQM_RR_REM_CMD_TILL_NONMATCHING) {
  4197. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4198. tx.dropped.fw_rem_no_match, 1);
  4199. } else if (ts->status == HAL_TX_TQM_RR_DROP_THRESHOLD) {
  4200. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4201. tx.dropped.drop_threshold, 1);
  4202. } else if (ts->status == HAL_TX_TQM_RR_LINK_DESC_UNAVAILABLE) {
  4203. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4204. tx.dropped.drop_link_desc_na, 1);
  4205. } else if (ts->status == HAL_TX_TQM_RR_DROP_OR_INVALID_MSDU) {
  4206. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4207. tx.dropped.invalid_drop, 1);
  4208. } else if (ts->status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4209. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  4210. tx.dropped.mcast_vdev_drop, 1);
  4211. } else {
  4212. DP_PEER_PER_PKT_STATS_INC(txrx_peer, tx.dropped.invalid_rr, 1);
  4213. }
  4214. }
  4215. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4216. /**
  4217. * dp_tx_flow_pool_lock() - take flow pool lock
  4218. * @soc: core txrx main context
  4219. * @tx_desc: tx desc
  4220. *
  4221. * Return: None
  4222. */
  4223. static inline
  4224. void dp_tx_flow_pool_lock(struct dp_soc *soc,
  4225. struct dp_tx_desc_s *tx_desc)
  4226. {
  4227. struct dp_tx_desc_pool_s *pool;
  4228. uint8_t desc_pool_id;
  4229. desc_pool_id = tx_desc->pool_id;
  4230. pool = &soc->tx_desc[desc_pool_id];
  4231. qdf_spin_lock_bh(&pool->flow_pool_lock);
  4232. }
  4233. /**
  4234. * dp_tx_flow_pool_unlock() - release flow pool lock
  4235. * @soc: core txrx main context
  4236. * @tx_desc: tx desc
  4237. *
  4238. * Return: None
  4239. */
  4240. static inline
  4241. void dp_tx_flow_pool_unlock(struct dp_soc *soc,
  4242. struct dp_tx_desc_s *tx_desc)
  4243. {
  4244. struct dp_tx_desc_pool_s *pool;
  4245. uint8_t desc_pool_id;
  4246. desc_pool_id = tx_desc->pool_id;
  4247. pool = &soc->tx_desc[desc_pool_id];
  4248. qdf_spin_unlock_bh(&pool->flow_pool_lock);
  4249. }
  4250. #else
  4251. static inline
  4252. void dp_tx_flow_pool_lock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4253. {
  4254. }
  4255. static inline
  4256. void dp_tx_flow_pool_unlock(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
  4257. {
  4258. }
  4259. #endif
  4260. /**
  4261. * dp_tx_notify_completion() - Notify tx completion for this desc
  4262. * @soc: core txrx main context
  4263. * @vdev: datapath vdev handle
  4264. * @tx_desc: tx desc
  4265. * @netbuf: buffer
  4266. * @status: tx status
  4267. *
  4268. * Return: none
  4269. */
  4270. static inline void dp_tx_notify_completion(struct dp_soc *soc,
  4271. struct dp_vdev *vdev,
  4272. struct dp_tx_desc_s *tx_desc,
  4273. qdf_nbuf_t netbuf,
  4274. uint8_t status)
  4275. {
  4276. void *osif_dev;
  4277. ol_txrx_completion_fp tx_compl_cbk = NULL;
  4278. uint16_t flag = BIT(QDF_TX_RX_STATUS_DOWNLOAD_SUCC);
  4279. qdf_assert(tx_desc);
  4280. if (!vdev ||
  4281. !vdev->osif_vdev) {
  4282. return;
  4283. }
  4284. osif_dev = vdev->osif_vdev;
  4285. tx_compl_cbk = vdev->tx_comp;
  4286. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4287. flag |= BIT(QDF_TX_RX_STATUS_OK);
  4288. if (tx_compl_cbk)
  4289. tx_compl_cbk(netbuf, osif_dev, flag);
  4290. }
  4291. /** dp_tx_sojourn_stats_process() - Collect sojourn stats
  4292. * @pdev: pdev handle
  4293. * @tid: tid value
  4294. * @txdesc_ts: timestamp from txdesc
  4295. * @ppdu_id: ppdu id
  4296. *
  4297. * Return: none
  4298. */
  4299. #ifdef FEATURE_PERPKT_INFO
  4300. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4301. struct dp_txrx_peer *txrx_peer,
  4302. uint8_t tid,
  4303. uint64_t txdesc_ts,
  4304. uint32_t ppdu_id)
  4305. {
  4306. uint64_t delta_ms;
  4307. struct cdp_tx_sojourn_stats *sojourn_stats;
  4308. struct dp_peer *primary_link_peer = NULL;
  4309. struct dp_soc *link_peer_soc = NULL;
  4310. if (qdf_unlikely(!pdev->enhanced_stats_en))
  4311. return;
  4312. if (qdf_unlikely(tid == HTT_INVALID_TID ||
  4313. tid >= CDP_DATA_TID_MAX))
  4314. return;
  4315. if (qdf_unlikely(!pdev->sojourn_buf))
  4316. return;
  4317. primary_link_peer = dp_get_primary_link_peer_by_id(pdev->soc,
  4318. txrx_peer->peer_id,
  4319. DP_MOD_ID_TX_COMP);
  4320. if (qdf_unlikely(!primary_link_peer))
  4321. return;
  4322. sojourn_stats = (struct cdp_tx_sojourn_stats *)
  4323. qdf_nbuf_data(pdev->sojourn_buf);
  4324. link_peer_soc = primary_link_peer->vdev->pdev->soc;
  4325. sojourn_stats->cookie = (void *)
  4326. dp_monitor_peer_get_peerstats_ctx(link_peer_soc,
  4327. primary_link_peer);
  4328. delta_ms = qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4329. txdesc_ts;
  4330. qdf_ewma_tx_lag_add(&txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid],
  4331. delta_ms);
  4332. sojourn_stats->sum_sojourn_msdu[tid] = delta_ms;
  4333. sojourn_stats->num_msdus[tid] = 1;
  4334. sojourn_stats->avg_sojourn_msdu[tid].internal =
  4335. txrx_peer->stats.per_pkt_stats.tx.avg_sojourn_msdu[tid].internal;
  4336. dp_wdi_event_handler(WDI_EVENT_TX_SOJOURN_STAT, pdev->soc,
  4337. pdev->sojourn_buf, HTT_INVALID_PEER,
  4338. WDI_NO_VAL, pdev->pdev_id);
  4339. sojourn_stats->sum_sojourn_msdu[tid] = 0;
  4340. sojourn_stats->num_msdus[tid] = 0;
  4341. sojourn_stats->avg_sojourn_msdu[tid].internal = 0;
  4342. dp_peer_unref_delete(primary_link_peer, DP_MOD_ID_TX_COMP);
  4343. }
  4344. #else
  4345. static inline void dp_tx_sojourn_stats_process(struct dp_pdev *pdev,
  4346. struct dp_txrx_peer *txrx_peer,
  4347. uint8_t tid,
  4348. uint64_t txdesc_ts,
  4349. uint32_t ppdu_id)
  4350. {
  4351. }
  4352. #endif
  4353. #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
  4354. /**
  4355. * dp_send_completion_to_pkt_capture() - send tx completion to packet capture
  4356. * @soc: dp_soc handle
  4357. * @desc: Tx Descriptor
  4358. * @ts: HAL Tx completion descriptor contents
  4359. *
  4360. * This function is used to send tx completion to packet capture
  4361. */
  4362. void dp_send_completion_to_pkt_capture(struct dp_soc *soc,
  4363. struct dp_tx_desc_s *desc,
  4364. struct hal_tx_completion_status *ts)
  4365. {
  4366. dp_wdi_event_handler(WDI_EVENT_PKT_CAPTURE_TX_DATA, soc,
  4367. desc, ts->peer_id,
  4368. WDI_NO_VAL, desc->pdev->pdev_id);
  4369. }
  4370. #endif
  4371. /**
  4372. * dp_tx_comp_process_desc() - Process tx descriptor and free associated nbuf
  4373. * @soc: DP Soc handle
  4374. * @tx_desc: software Tx descriptor
  4375. * @ts : Tx completion status from HAL/HTT descriptor
  4376. *
  4377. * Return: none
  4378. */
  4379. void
  4380. dp_tx_comp_process_desc(struct dp_soc *soc,
  4381. struct dp_tx_desc_s *desc,
  4382. struct hal_tx_completion_status *ts,
  4383. struct dp_txrx_peer *txrx_peer)
  4384. {
  4385. uint64_t time_latency = 0;
  4386. uint16_t peer_id = DP_INVALID_PEER_ID;
  4387. /*
  4388. * m_copy/tx_capture modes are not supported for
  4389. * scatter gather packets
  4390. */
  4391. if (qdf_unlikely(!!desc->pdev->latency_capture_enable)) {
  4392. time_latency = (qdf_ktime_to_ms(qdf_ktime_real_get()) -
  4393. qdf_ktime_to_ms(desc->timestamp));
  4394. }
  4395. dp_send_completion_to_pkt_capture(soc, desc, ts);
  4396. if (dp_tx_pkt_tracepoints_enabled())
  4397. qdf_trace_dp_packet(desc->nbuf, QDF_TX,
  4398. desc->msdu_ext_desc ?
  4399. desc->msdu_ext_desc->tso_desc : NULL,
  4400. qdf_ktime_to_ms(desc->timestamp));
  4401. if (!(desc->msdu_ext_desc)) {
  4402. dp_tx_enh_unmap(soc, desc);
  4403. if (txrx_peer)
  4404. peer_id = txrx_peer->peer_id;
  4405. if (QDF_STATUS_SUCCESS ==
  4406. dp_monitor_tx_add_to_comp_queue(soc, desc, ts, peer_id)) {
  4407. return;
  4408. }
  4409. if (QDF_STATUS_SUCCESS ==
  4410. dp_get_completion_indication_for_stack(soc,
  4411. desc->pdev,
  4412. txrx_peer, ts,
  4413. desc->nbuf,
  4414. time_latency)) {
  4415. dp_send_completion_to_stack(soc,
  4416. desc->pdev,
  4417. ts->peer_id,
  4418. ts->ppdu_id,
  4419. desc->nbuf);
  4420. return;
  4421. }
  4422. }
  4423. desc->flags |= DP_TX_DESC_FLAG_COMPLETED_TX;
  4424. dp_tx_comp_free_buf(soc, desc, false);
  4425. }
  4426. #ifdef DISABLE_DP_STATS
  4427. /**
  4428. * dp_tx_update_connectivity_stats() - update tx connectivity stats
  4429. * @soc: core txrx main context
  4430. * @tx_desc: tx desc
  4431. * @status: tx status
  4432. *
  4433. * Return: none
  4434. */
  4435. static inline
  4436. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4437. struct dp_vdev *vdev,
  4438. struct dp_tx_desc_s *tx_desc,
  4439. uint8_t status)
  4440. {
  4441. }
  4442. #else
  4443. static inline
  4444. void dp_tx_update_connectivity_stats(struct dp_soc *soc,
  4445. struct dp_vdev *vdev,
  4446. struct dp_tx_desc_s *tx_desc,
  4447. uint8_t status)
  4448. {
  4449. void *osif_dev;
  4450. ol_txrx_stats_rx_fp stats_cbk;
  4451. uint8_t pkt_type;
  4452. qdf_assert(tx_desc);
  4453. if (!vdev ||
  4454. !vdev->osif_vdev ||
  4455. !vdev->stats_cb)
  4456. return;
  4457. osif_dev = vdev->osif_vdev;
  4458. stats_cbk = vdev->stats_cb;
  4459. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_HOST_FW_SENT, &pkt_type);
  4460. if (status == HAL_TX_TQM_RR_FRAME_ACKED)
  4461. stats_cbk(tx_desc->nbuf, osif_dev, PKT_TYPE_TX_ACK_CNT,
  4462. &pkt_type);
  4463. }
  4464. #endif
  4465. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  4466. /* Mask for bit29 ~ bit31 */
  4467. #define DP_TX_TS_BIT29_31_MASK 0xE0000000
  4468. /* Timestamp value (unit us) if bit29 is set */
  4469. #define DP_TX_TS_BIT29_SET_VALUE BIT(29)
  4470. /**
  4471. * dp_tx_adjust_enqueue_buffer_ts() - adjust the enqueue buffer_timestamp
  4472. * @ack_ts: OTA ack timestamp, unit us.
  4473. * @enqueue_ts: TCL enqueue TX data to TQM timestamp, unit us.
  4474. * @base_delta_ts: base timestamp delta for ack_ts and enqueue_ts
  4475. *
  4476. * this function will restore the bit29 ~ bit31 3 bits value for
  4477. * buffer_timestamp in wbm2sw ring entry, currently buffer_timestamp only
  4478. * can support 0x7FFF * 1024 us (29 bits), but if the timestamp is >
  4479. * 0x7FFF * 1024 us, bit29~ bit31 will be lost.
  4480. *
  4481. * Return: the adjusted buffer_timestamp value
  4482. */
  4483. static inline
  4484. uint32_t dp_tx_adjust_enqueue_buffer_ts(uint32_t ack_ts,
  4485. uint32_t enqueue_ts,
  4486. uint32_t base_delta_ts)
  4487. {
  4488. uint32_t ack_buffer_ts;
  4489. uint32_t ack_buffer_ts_bit29_31;
  4490. uint32_t adjusted_enqueue_ts;
  4491. /* corresponding buffer_timestamp value when receive OTA Ack */
  4492. ack_buffer_ts = ack_ts - base_delta_ts;
  4493. ack_buffer_ts_bit29_31 = ack_buffer_ts & DP_TX_TS_BIT29_31_MASK;
  4494. /* restore the bit29 ~ bit31 value */
  4495. adjusted_enqueue_ts = ack_buffer_ts_bit29_31 | enqueue_ts;
  4496. /*
  4497. * if actual enqueue_ts value occupied 29 bits only, this enqueue_ts
  4498. * value + real UL delay overflow 29 bits, then 30th bit (bit-29)
  4499. * should not be marked, otherwise extra 0x20000000 us is added to
  4500. * enqueue_ts.
  4501. */
  4502. if (qdf_unlikely(adjusted_enqueue_ts > ack_buffer_ts))
  4503. adjusted_enqueue_ts -= DP_TX_TS_BIT29_SET_VALUE;
  4504. return adjusted_enqueue_ts;
  4505. }
  4506. QDF_STATUS
  4507. dp_tx_compute_hw_delay_us(struct hal_tx_completion_status *ts,
  4508. uint32_t delta_tsf,
  4509. uint32_t *delay_us)
  4510. {
  4511. uint32_t buffer_ts;
  4512. uint32_t delay;
  4513. if (!delay_us)
  4514. return QDF_STATUS_E_INVAL;
  4515. /* Tx_rate_stats_info_valid is 0 and tsf is invalid then */
  4516. if (!ts->valid)
  4517. return QDF_STATUS_E_INVAL;
  4518. /* buffer_timestamp is in units of 1024 us and is [31:13] of
  4519. * WBM_RELEASE_RING_4. After left shift 10 bits, it's
  4520. * valid up to 29 bits.
  4521. */
  4522. buffer_ts = ts->buffer_timestamp << 10;
  4523. buffer_ts = dp_tx_adjust_enqueue_buffer_ts(ts->tsf,
  4524. buffer_ts, delta_tsf);
  4525. delay = ts->tsf - buffer_ts - delta_tsf;
  4526. if (qdf_unlikely(delay & 0x80000000)) {
  4527. dp_err_rl("delay = 0x%x (-ve)\n"
  4528. "release_src = %d\n"
  4529. "ppdu_id = 0x%x\n"
  4530. "peer_id = 0x%x\n"
  4531. "tid = 0x%x\n"
  4532. "release_reason = %d\n"
  4533. "tsf = %u (0x%x)\n"
  4534. "buffer_timestamp = %u (0x%x)\n"
  4535. "delta_tsf = %u (0x%x)\n",
  4536. delay, ts->release_src, ts->ppdu_id, ts->peer_id,
  4537. ts->tid, ts->status, ts->tsf, ts->tsf,
  4538. ts->buffer_timestamp, ts->buffer_timestamp,
  4539. delta_tsf, delta_tsf);
  4540. delay = 0;
  4541. goto end;
  4542. }
  4543. delay &= 0x1FFFFFFF; /* mask 29 BITS */
  4544. if (delay > 0x1000000) {
  4545. dp_info_rl("----------------------\n"
  4546. "Tx completion status:\n"
  4547. "----------------------\n"
  4548. "release_src = %d\n"
  4549. "ppdu_id = 0x%x\n"
  4550. "release_reason = %d\n"
  4551. "tsf = %u (0x%x)\n"
  4552. "buffer_timestamp = %u (0x%x)\n"
  4553. "delta_tsf = %u (0x%x)\n",
  4554. ts->release_src, ts->ppdu_id, ts->status,
  4555. ts->tsf, ts->tsf, ts->buffer_timestamp,
  4556. ts->buffer_timestamp, delta_tsf, delta_tsf);
  4557. return QDF_STATUS_E_FAILURE;
  4558. }
  4559. end:
  4560. *delay_us = delay;
  4561. return QDF_STATUS_SUCCESS;
  4562. }
  4563. void dp_set_delta_tsf(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4564. uint32_t delta_tsf)
  4565. {
  4566. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4567. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4568. DP_MOD_ID_CDP);
  4569. if (!vdev) {
  4570. dp_err_rl("vdev %d does not exist", vdev_id);
  4571. return;
  4572. }
  4573. vdev->delta_tsf = delta_tsf;
  4574. dp_debug("vdev id %u delta_tsf %u", vdev_id, delta_tsf);
  4575. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4576. }
  4577. #endif
  4578. #ifdef WLAN_FEATURE_TSF_UPLINK_DELAY
  4579. QDF_STATUS dp_set_tsf_ul_delay_report(struct cdp_soc_t *soc_hdl,
  4580. uint8_t vdev_id, bool enable)
  4581. {
  4582. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4583. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  4584. DP_MOD_ID_CDP);
  4585. if (!vdev) {
  4586. dp_err_rl("vdev %d does not exist", vdev_id);
  4587. return QDF_STATUS_E_FAILURE;
  4588. }
  4589. qdf_atomic_set(&vdev->ul_delay_report, enable);
  4590. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4591. return QDF_STATUS_SUCCESS;
  4592. }
  4593. QDF_STATUS dp_get_uplink_delay(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  4594. uint32_t *val)
  4595. {
  4596. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  4597. struct dp_vdev *vdev;
  4598. uint32_t delay_accum;
  4599. uint32_t pkts_accum;
  4600. vdev = dp_vdev_get_ref_by_id(soc, vdev_id, DP_MOD_ID_CDP);
  4601. if (!vdev) {
  4602. dp_err_rl("vdev %d does not exist", vdev_id);
  4603. return QDF_STATUS_E_FAILURE;
  4604. }
  4605. if (!qdf_atomic_read(&vdev->ul_delay_report)) {
  4606. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4607. return QDF_STATUS_E_FAILURE;
  4608. }
  4609. /* Average uplink delay based on current accumulated values */
  4610. delay_accum = qdf_atomic_read(&vdev->ul_delay_accum);
  4611. pkts_accum = qdf_atomic_read(&vdev->ul_pkts_accum);
  4612. *val = delay_accum / pkts_accum;
  4613. dp_debug("uplink_delay %u delay_accum %u pkts_accum %u", *val,
  4614. delay_accum, pkts_accum);
  4615. /* Reset accumulated values to 0 */
  4616. qdf_atomic_set(&vdev->ul_delay_accum, 0);
  4617. qdf_atomic_set(&vdev->ul_pkts_accum, 0);
  4618. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_CDP);
  4619. return QDF_STATUS_SUCCESS;
  4620. }
  4621. static void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4622. struct hal_tx_completion_status *ts)
  4623. {
  4624. uint32_t ul_delay;
  4625. if (qdf_unlikely(!vdev)) {
  4626. dp_info_rl("vdev is null or delete in progress");
  4627. return;
  4628. }
  4629. if (!qdf_atomic_read(&vdev->ul_delay_report))
  4630. return;
  4631. if (QDF_IS_STATUS_ERROR(dp_tx_compute_hw_delay_us(ts,
  4632. vdev->delta_tsf,
  4633. &ul_delay)))
  4634. return;
  4635. ul_delay /= 1000; /* in unit of ms */
  4636. qdf_atomic_add(ul_delay, &vdev->ul_delay_accum);
  4637. qdf_atomic_inc(&vdev->ul_pkts_accum);
  4638. }
  4639. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY */
  4640. static inline
  4641. void dp_tx_update_uplink_delay(struct dp_soc *soc, struct dp_vdev *vdev,
  4642. struct hal_tx_completion_status *ts)
  4643. {
  4644. }
  4645. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY */
  4646. /**
  4647. * dp_tx_comp_process_tx_status() - Parse and Dump Tx completion status info
  4648. * @soc: DP soc handle
  4649. * @tx_desc: software descriptor head pointer
  4650. * @ts: Tx completion status
  4651. * @txrx_peer: txrx peer handle
  4652. * @ring_id: ring number
  4653. *
  4654. * Return: none
  4655. */
  4656. void dp_tx_comp_process_tx_status(struct dp_soc *soc,
  4657. struct dp_tx_desc_s *tx_desc,
  4658. struct hal_tx_completion_status *ts,
  4659. struct dp_txrx_peer *txrx_peer,
  4660. uint8_t ring_id)
  4661. {
  4662. uint32_t length;
  4663. qdf_ether_header_t *eh;
  4664. struct dp_vdev *vdev = NULL;
  4665. qdf_nbuf_t nbuf = tx_desc->nbuf;
  4666. enum qdf_dp_tx_rx_status dp_status;
  4667. if (!nbuf) {
  4668. dp_info_rl("invalid tx descriptor. nbuf NULL");
  4669. goto out;
  4670. }
  4671. eh = (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  4672. length = qdf_nbuf_len(nbuf);
  4673. dp_status = dp_tx_hw_to_qdf(ts->status);
  4674. DPTRACE(qdf_dp_trace_ptr(tx_desc->nbuf,
  4675. QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD,
  4676. QDF_TRACE_DEFAULT_PDEV_ID,
  4677. qdf_nbuf_data_addr(nbuf),
  4678. sizeof(qdf_nbuf_data(nbuf)),
  4679. tx_desc->id, ts->status, dp_status));
  4680. dp_tx_comp_debug("-------------------- \n"
  4681. "Tx Completion Stats: \n"
  4682. "-------------------- \n"
  4683. "ack_frame_rssi = %d \n"
  4684. "first_msdu = %d \n"
  4685. "last_msdu = %d \n"
  4686. "msdu_part_of_amsdu = %d \n"
  4687. "rate_stats valid = %d \n"
  4688. "bw = %d \n"
  4689. "pkt_type = %d \n"
  4690. "stbc = %d \n"
  4691. "ldpc = %d \n"
  4692. "sgi = %d \n"
  4693. "mcs = %d \n"
  4694. "ofdma = %d \n"
  4695. "tones_in_ru = %d \n"
  4696. "tsf = %d \n"
  4697. "ppdu_id = %d \n"
  4698. "transmit_cnt = %d \n"
  4699. "tid = %d \n"
  4700. "peer_id = %d\n"
  4701. "tx_status = %d\n",
  4702. ts->ack_frame_rssi, ts->first_msdu,
  4703. ts->last_msdu, ts->msdu_part_of_amsdu,
  4704. ts->valid, ts->bw, ts->pkt_type, ts->stbc,
  4705. ts->ldpc, ts->sgi, ts->mcs, ts->ofdma,
  4706. ts->tones_in_ru, ts->tsf, ts->ppdu_id,
  4707. ts->transmit_cnt, ts->tid, ts->peer_id,
  4708. ts->status);
  4709. /* Update SoC level stats */
  4710. DP_STATS_INCC(soc, tx.dropped_fw_removed, 1,
  4711. (ts->status == HAL_TX_TQM_RR_REM_CMD_REM));
  4712. if (!txrx_peer) {
  4713. dp_info_rl("peer is null or deletion in progress");
  4714. DP_STATS_INC_PKT(soc, tx.tx_invalid_peer, 1, length);
  4715. goto out;
  4716. }
  4717. vdev = txrx_peer->vdev;
  4718. dp_tx_update_connectivity_stats(soc, vdev, tx_desc, ts->status);
  4719. dp_tx_update_uplink_delay(soc, vdev, ts);
  4720. /* check tx complete notification */
  4721. if (qdf_nbuf_tx_notify_comp_get(nbuf))
  4722. dp_tx_notify_completion(soc, vdev, tx_desc,
  4723. nbuf, ts->status);
  4724. /* Update per-packet stats for mesh mode */
  4725. if (qdf_unlikely(vdev->mesh_vdev) &&
  4726. !(tx_desc->flags & DP_TX_DESC_FLAG_TO_FW))
  4727. dp_tx_comp_fill_tx_completion_stats(tx_desc, ts);
  4728. /* Update peer level stats */
  4729. if (qdf_unlikely(txrx_peer->bss_peer &&
  4730. vdev->opmode == wlan_op_mode_ap)) {
  4731. if (ts->status != HAL_TX_TQM_RR_REM_CMD_REM) {
  4732. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.mcast, 1,
  4733. length);
  4734. if (txrx_peer->vdev->tx_encap_type ==
  4735. htt_cmn_pkt_type_ethernet &&
  4736. QDF_IS_ADDR_BROADCAST(eh->ether_dhost)) {
  4737. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4738. tx.bcast, 1,
  4739. length);
  4740. }
  4741. }
  4742. } else {
  4743. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.ucast, 1, length);
  4744. if (ts->status == HAL_TX_TQM_RR_FRAME_ACKED) {
  4745. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer, tx.tx_success,
  4746. 1, length);
  4747. if (qdf_unlikely(txrx_peer->in_twt)) {
  4748. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  4749. tx.tx_success_twt,
  4750. 1, length);
  4751. }
  4752. }
  4753. }
  4754. dp_tx_update_peer_stats(tx_desc, ts, txrx_peer, ring_id);
  4755. dp_tx_update_peer_delay_stats(txrx_peer, tx_desc, ts, ring_id);
  4756. dp_tx_update_peer_jitter_stats(txrx_peer, tx_desc, ts, ring_id);
  4757. dp_tx_update_peer_sawf_stats(soc, vdev, txrx_peer, tx_desc,
  4758. ts, ts->tid);
  4759. dp_tx_send_pktlog(soc, vdev->pdev, tx_desc, nbuf, dp_status);
  4760. #ifdef QCA_SUPPORT_RDK_STATS
  4761. if (soc->peerstats_enabled)
  4762. dp_tx_sojourn_stats_process(vdev->pdev, txrx_peer, ts->tid,
  4763. qdf_ktime_to_ms(tx_desc->timestamp),
  4764. ts->ppdu_id);
  4765. #endif
  4766. out:
  4767. return;
  4768. }
  4769. #if defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT) && \
  4770. defined(QCA_ENHANCED_STATS_SUPPORT)
  4771. /*
  4772. * dp_tx_update_peer_basic_stats(): Update peer basic stats
  4773. * @txrx_peer: Datapath txrx_peer handle
  4774. * @length: Length of the packet
  4775. * @tx_status: Tx status from TQM/FW
  4776. * @update: enhanced flag value present in dp_pdev
  4777. *
  4778. * Return: none
  4779. */
  4780. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4781. uint32_t length, uint8_t tx_status,
  4782. bool update)
  4783. {
  4784. if (update || (!txrx_peer->hw_txrx_stats_en)) {
  4785. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4786. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4787. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4788. }
  4789. }
  4790. #elif defined(QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT)
  4791. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4792. uint32_t length, uint8_t tx_status,
  4793. bool update)
  4794. {
  4795. if (!txrx_peer->hw_txrx_stats_en) {
  4796. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4797. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4798. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4799. }
  4800. }
  4801. #else
  4802. void dp_tx_update_peer_basic_stats(struct dp_txrx_peer *txrx_peer,
  4803. uint32_t length, uint8_t tx_status,
  4804. bool update)
  4805. {
  4806. DP_PEER_STATS_FLAT_INC_PKT(txrx_peer, comp_pkt, 1, length);
  4807. if (tx_status != HAL_TX_TQM_RR_FRAME_ACKED)
  4808. DP_PEER_STATS_FLAT_INC(txrx_peer, tx_failed, 1);
  4809. }
  4810. #endif
  4811. /*
  4812. * dp_tx_prefetch_next_nbuf_data(): Prefetch nbuf and nbuf data
  4813. * @nbuf: skb buffer
  4814. *
  4815. * Return: none
  4816. */
  4817. #ifdef QCA_DP_RX_NBUF_AND_NBUF_DATA_PREFETCH
  4818. static inline
  4819. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4820. {
  4821. qdf_nbuf_t nbuf = NULL;
  4822. if (next)
  4823. nbuf = next->nbuf;
  4824. if (nbuf)
  4825. qdf_prefetch(nbuf);
  4826. }
  4827. #else
  4828. static inline
  4829. void dp_tx_prefetch_next_nbuf_data(struct dp_tx_desc_s *next)
  4830. {
  4831. }
  4832. #endif
  4833. /**
  4834. * dp_tx_mcast_reinject_handler() - Tx reinjected multicast packets handler
  4835. * @soc: core txrx main context
  4836. * @desc: software descriptor
  4837. *
  4838. * Return: true when packet is reinjected
  4839. */
  4840. #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) && \
  4841. defined(WLAN_MCAST_MLO)
  4842. static inline bool
  4843. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4844. {
  4845. struct dp_vdev *vdev = NULL;
  4846. if (desc->tx_status == HAL_TX_TQM_RR_MULTICAST_DROP) {
  4847. if (!soc->arch_ops.dp_tx_mcast_handler ||
  4848. !soc->arch_ops.dp_tx_is_mcast_primary)
  4849. return false;
  4850. vdev = dp_vdev_get_ref_by_id(soc, desc->vdev_id,
  4851. DP_MOD_ID_REINJECT);
  4852. if (qdf_unlikely(!vdev)) {
  4853. dp_tx_comp_info_rl("Unable to get vdev ref %d",
  4854. desc->id);
  4855. return false;
  4856. }
  4857. if (!(soc->arch_ops.dp_tx_is_mcast_primary(soc, vdev))) {
  4858. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4859. return false;
  4860. }
  4861. DP_STATS_INC_PKT(vdev, tx_i.reinject_pkts, 1,
  4862. qdf_nbuf_len(desc->nbuf));
  4863. soc->arch_ops.dp_tx_mcast_handler(soc, vdev, desc->nbuf);
  4864. dp_tx_desc_release(desc, desc->pool_id);
  4865. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_REINJECT);
  4866. return true;
  4867. }
  4868. return false;
  4869. }
  4870. #else
  4871. static inline bool
  4872. dp_tx_mcast_reinject_handler(struct dp_soc *soc, struct dp_tx_desc_s *desc)
  4873. {
  4874. return false;
  4875. }
  4876. #endif
  4877. #ifdef QCA_DP_TX_NBUF_LIST_FREE
  4878. static inline void
  4879. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4880. {
  4881. qdf_nbuf_queue_head_init(nbuf_queue_head);
  4882. }
  4883. static inline void
  4884. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4885. struct dp_tx_desc_s *desc)
  4886. {
  4887. qdf_nbuf_t nbuf = NULL;
  4888. nbuf = desc->nbuf;
  4889. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_FAST))
  4890. qdf_nbuf_dev_queue_head(nbuf_queue_head, nbuf);
  4891. else
  4892. qdf_nbuf_free(nbuf);
  4893. }
  4894. static inline void
  4895. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4896. {
  4897. qdf_nbuf_dev_kfree_list(nbuf_queue_head);
  4898. }
  4899. #else
  4900. static inline void
  4901. dp_tx_nbuf_queue_head_init(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4902. {
  4903. }
  4904. static inline void
  4905. dp_tx_nbuf_dev_queue_free(qdf_nbuf_queue_head_t *nbuf_queue_head,
  4906. struct dp_tx_desc_s *desc)
  4907. {
  4908. qdf_nbuf_free(desc->nbuf);
  4909. }
  4910. static inline void
  4911. dp_tx_nbuf_dev_kfree_list(qdf_nbuf_queue_head_t *nbuf_queue_head)
  4912. {
  4913. }
  4914. #endif
  4915. /**
  4916. * dp_tx_comp_process_desc_list() - Tx complete software descriptor handler
  4917. * @soc: core txrx main context
  4918. * @comp_head: software descriptor head pointer
  4919. * @ring_id: ring number
  4920. *
  4921. * This function will process batch of descriptors reaped by dp_tx_comp_handler
  4922. * and release the software descriptors after processing is complete
  4923. *
  4924. * Return: none
  4925. */
  4926. void
  4927. dp_tx_comp_process_desc_list(struct dp_soc *soc,
  4928. struct dp_tx_desc_s *comp_head, uint8_t ring_id)
  4929. {
  4930. struct dp_tx_desc_s *desc;
  4931. struct dp_tx_desc_s *next;
  4932. struct hal_tx_completion_status ts;
  4933. struct dp_txrx_peer *txrx_peer = NULL;
  4934. uint16_t peer_id = DP_INVALID_PEER;
  4935. dp_txrx_ref_handle txrx_ref_handle = NULL;
  4936. qdf_nbuf_queue_head_t h;
  4937. desc = comp_head;
  4938. dp_tx_nbuf_queue_head_init(&h);
  4939. while (desc) {
  4940. next = desc->next;
  4941. dp_tx_prefetch_next_nbuf_data(next);
  4942. if (peer_id != desc->peer_id) {
  4943. if (txrx_peer)
  4944. dp_txrx_peer_unref_delete(txrx_ref_handle,
  4945. DP_MOD_ID_TX_COMP);
  4946. peer_id = desc->peer_id;
  4947. txrx_peer =
  4948. dp_txrx_peer_get_ref_by_id(soc, peer_id,
  4949. &txrx_ref_handle,
  4950. DP_MOD_ID_TX_COMP);
  4951. }
  4952. if (dp_tx_mcast_reinject_handler(soc, desc)) {
  4953. desc = next;
  4954. continue;
  4955. }
  4956. if (desc->flags & DP_TX_DESC_FLAG_PPEDS) {
  4957. if (qdf_likely(txrx_peer))
  4958. dp_tx_update_peer_basic_stats(txrx_peer,
  4959. desc->length,
  4960. desc->tx_status,
  4961. false);
  4962. dp_tx_nbuf_dev_queue_free(&h, desc);
  4963. dp_ppeds_tx_desc_free(soc, desc);
  4964. desc = next;
  4965. continue;
  4966. }
  4967. if (qdf_likely(desc->flags & DP_TX_DESC_FLAG_SIMPLE)) {
  4968. struct dp_pdev *pdev = desc->pdev;
  4969. if (qdf_likely(txrx_peer))
  4970. dp_tx_update_peer_basic_stats(txrx_peer,
  4971. desc->length,
  4972. desc->tx_status,
  4973. false);
  4974. qdf_assert(pdev);
  4975. dp_tx_outstanding_dec(pdev);
  4976. /*
  4977. * Calling a QDF WRAPPER here is creating significant
  4978. * performance impact so avoided the wrapper call here
  4979. */
  4980. dp_tx_desc_history_add(soc, desc->dma_addr, desc->nbuf,
  4981. desc->id, DP_TX_COMP_UNMAP);
  4982. dp_tx_nbuf_unmap(soc, desc);
  4983. dp_tx_nbuf_dev_queue_free(&h, desc);
  4984. dp_tx_desc_free(soc, desc, desc->pool_id);
  4985. desc = next;
  4986. continue;
  4987. }
  4988. hal_tx_comp_get_status(&desc->comp, &ts, soc->hal_soc);
  4989. dp_tx_comp_process_tx_status(soc, desc, &ts, txrx_peer,
  4990. ring_id);
  4991. dp_tx_comp_process_desc(soc, desc, &ts, txrx_peer);
  4992. dp_tx_desc_release(desc, desc->pool_id);
  4993. desc = next;
  4994. }
  4995. dp_tx_nbuf_dev_kfree_list(&h);
  4996. if (txrx_peer)
  4997. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_TX_COMP);
  4998. }
  4999. #ifdef WLAN_FEATURE_RX_SOFTIRQ_TIME_LIMIT
  5000. static inline
  5001. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  5002. int max_reap_limit)
  5003. {
  5004. bool limit_hit = false;
  5005. limit_hit =
  5006. (num_reaped >= max_reap_limit) ? true : false;
  5007. if (limit_hit)
  5008. DP_STATS_INC(soc, tx.tx_comp_loop_pkt_limit_hit, 1);
  5009. return limit_hit;
  5010. }
  5011. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5012. {
  5013. return soc->wlan_cfg_ctx->tx_comp_enable_eol_data_check;
  5014. }
  5015. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5016. {
  5017. struct wlan_cfg_dp_soc_ctxt *cfg = soc->wlan_cfg_ctx;
  5018. return cfg->tx_comp_loop_pkt_limit;
  5019. }
  5020. #else
  5021. static inline
  5022. bool dp_tx_comp_loop_pkt_limit_hit(struct dp_soc *soc, int num_reaped,
  5023. int max_reap_limit)
  5024. {
  5025. return false;
  5026. }
  5027. static inline bool dp_tx_comp_enable_eol_data_check(struct dp_soc *soc)
  5028. {
  5029. return false;
  5030. }
  5031. static inline int dp_tx_comp_get_loop_pkt_limit(struct dp_soc *soc)
  5032. {
  5033. return 0;
  5034. }
  5035. #endif
  5036. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  5037. static inline int
  5038. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5039. int *max_reap_limit)
  5040. {
  5041. return soc->arch_ops.dp_srng_test_and_update_nf_params(soc, dp_srng,
  5042. max_reap_limit);
  5043. }
  5044. #else
  5045. static inline int
  5046. dp_srng_test_and_update_nf_params(struct dp_soc *soc, struct dp_srng *dp_srng,
  5047. int *max_reap_limit)
  5048. {
  5049. return 0;
  5050. }
  5051. #endif
  5052. #ifdef DP_TX_TRACKING
  5053. void dp_tx_desc_check_corruption(struct dp_tx_desc_s *tx_desc)
  5054. {
  5055. if ((tx_desc->magic != DP_TX_MAGIC_PATTERN_INUSE) &&
  5056. (tx_desc->magic != DP_TX_MAGIC_PATTERN_FREE)) {
  5057. dp_err_rl("tx_desc %u is corrupted", tx_desc->id);
  5058. qdf_trigger_self_recovery(NULL, QDF_TX_DESC_LEAK);
  5059. }
  5060. }
  5061. #endif
  5062. uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
  5063. hal_ring_handle_t hal_ring_hdl, uint8_t ring_id,
  5064. uint32_t quota)
  5065. {
  5066. void *tx_comp_hal_desc;
  5067. void *last_prefetched_hw_desc = NULL;
  5068. struct dp_tx_desc_s *last_prefetched_sw_desc = NULL;
  5069. hal_soc_handle_t hal_soc;
  5070. uint8_t buffer_src;
  5071. struct dp_tx_desc_s *tx_desc = NULL;
  5072. struct dp_tx_desc_s *head_desc = NULL;
  5073. struct dp_tx_desc_s *tail_desc = NULL;
  5074. uint32_t num_processed = 0;
  5075. uint32_t count;
  5076. uint32_t num_avail_for_reap = 0;
  5077. bool force_break = false;
  5078. struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
  5079. int max_reap_limit, ring_near_full;
  5080. uint32_t num_entries;
  5081. DP_HIST_INIT();
  5082. num_entries = hal_srng_get_num_entries(soc->hal_soc, hal_ring_hdl);
  5083. more_data:
  5084. hal_soc = soc->hal_soc;
  5085. /* Re-initialize local variables to be re-used */
  5086. head_desc = NULL;
  5087. tail_desc = NULL;
  5088. count = 0;
  5089. max_reap_limit = dp_tx_comp_get_loop_pkt_limit(soc);
  5090. ring_near_full = dp_srng_test_and_update_nf_params(soc, tx_comp_ring,
  5091. &max_reap_limit);
  5092. if (qdf_unlikely(dp_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  5093. dp_err("HAL RING Access Failed -- %pK", hal_ring_hdl);
  5094. return 0;
  5095. }
  5096. if (!num_avail_for_reap)
  5097. num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
  5098. hal_ring_hdl, 0);
  5099. if (num_avail_for_reap >= quota)
  5100. num_avail_for_reap = quota;
  5101. dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
  5102. last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
  5103. hal_ring_hdl,
  5104. num_avail_for_reap);
  5105. /* Find head descriptor from completion ring */
  5106. while (qdf_likely(num_avail_for_reap--)) {
  5107. tx_comp_hal_desc = dp_srng_dst_get_next(soc, hal_ring_hdl);
  5108. if (qdf_unlikely(!tx_comp_hal_desc))
  5109. break;
  5110. buffer_src = hal_tx_comp_get_buffer_source(hal_soc,
  5111. tx_comp_hal_desc);
  5112. /* If this buffer was not released by TQM or FW, then it is not
  5113. * Tx completion indication, assert */
  5114. if (qdf_unlikely(buffer_src !=
  5115. HAL_TX_COMP_RELEASE_SOURCE_TQM) &&
  5116. (qdf_unlikely(buffer_src !=
  5117. HAL_TX_COMP_RELEASE_SOURCE_FW))) {
  5118. uint8_t wbm_internal_error;
  5119. dp_err_rl(
  5120. "Tx comp release_src != TQM | FW but from %d",
  5121. buffer_src);
  5122. hal_dump_comp_desc(tx_comp_hal_desc);
  5123. DP_STATS_INC(soc, tx.invalid_release_source, 1);
  5124. /* When WBM sees NULL buffer_addr_info in any of
  5125. * ingress rings it sends an error indication,
  5126. * with wbm_internal_error=1, to a specific ring.
  5127. * The WBM2SW ring used to indicate these errors is
  5128. * fixed in HW, and that ring is being used as Tx
  5129. * completion ring. These errors are not related to
  5130. * Tx completions, and should just be ignored
  5131. */
  5132. wbm_internal_error = hal_get_wbm_internal_error(
  5133. hal_soc,
  5134. tx_comp_hal_desc);
  5135. if (wbm_internal_error) {
  5136. dp_err_rl("Tx comp wbm_internal_error!!");
  5137. DP_STATS_INC(soc, tx.wbm_internal_error[WBM_INT_ERROR_ALL], 1);
  5138. if (HAL_TX_COMP_RELEASE_SOURCE_REO ==
  5139. buffer_src)
  5140. dp_handle_wbm_internal_error(
  5141. soc,
  5142. tx_comp_hal_desc,
  5143. hal_tx_comp_get_buffer_type(
  5144. tx_comp_hal_desc));
  5145. } else {
  5146. dp_err_rl("Tx comp wbm_internal_error false");
  5147. DP_STATS_INC(soc, tx.non_wbm_internal_err, 1);
  5148. }
  5149. continue;
  5150. }
  5151. soc->arch_ops.tx_comp_get_params_from_hal_desc(soc,
  5152. tx_comp_hal_desc,
  5153. &tx_desc);
  5154. if (qdf_unlikely(!tx_desc)) {
  5155. dp_err("unable to retrieve tx_desc!");
  5156. hal_dump_comp_desc(tx_comp_hal_desc);
  5157. DP_STATS_INC(soc, tx.invalid_tx_comp_desc, 1);
  5158. QDF_BUG(0);
  5159. continue;
  5160. }
  5161. tx_desc->buffer_src = buffer_src;
  5162. if (tx_desc->flags & DP_TX_DESC_FLAG_PPEDS)
  5163. goto add_to_pool2;
  5164. /*
  5165. * If the release source is FW, process the HTT status
  5166. */
  5167. if (qdf_unlikely(buffer_src ==
  5168. HAL_TX_COMP_RELEASE_SOURCE_FW)) {
  5169. uint8_t htt_tx_status[HAL_TX_COMP_HTT_STATUS_LEN];
  5170. hal_tx_comp_get_htt_desc(tx_comp_hal_desc,
  5171. htt_tx_status);
  5172. /* Collect hw completion contents */
  5173. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5174. &tx_desc->comp, 1);
  5175. soc->arch_ops.dp_tx_process_htt_completion(
  5176. soc,
  5177. tx_desc,
  5178. htt_tx_status,
  5179. ring_id);
  5180. } else {
  5181. tx_desc->tx_status =
  5182. hal_tx_comp_get_tx_status(tx_comp_hal_desc);
  5183. tx_desc->buffer_src = buffer_src;
  5184. /*
  5185. * If the fast completion mode is enabled extended
  5186. * metadata from descriptor is not copied
  5187. */
  5188. if (qdf_likely(tx_desc->flags &
  5189. DP_TX_DESC_FLAG_SIMPLE))
  5190. goto add_to_pool;
  5191. /*
  5192. * If the descriptor is already freed in vdev_detach,
  5193. * continue to next descriptor
  5194. */
  5195. if (qdf_unlikely
  5196. ((tx_desc->vdev_id == DP_INVALID_VDEV_ID) &&
  5197. !tx_desc->flags)) {
  5198. dp_tx_comp_info_rl("Descriptor freed in vdev_detach %d",
  5199. tx_desc->id);
  5200. DP_STATS_INC(soc, tx.tx_comp_exception, 1);
  5201. dp_tx_desc_check_corruption(tx_desc);
  5202. continue;
  5203. }
  5204. if (qdf_unlikely(tx_desc->pdev->is_pdev_down)) {
  5205. dp_tx_comp_info_rl("pdev in down state %d",
  5206. tx_desc->id);
  5207. tx_desc->flags |= DP_TX_DESC_FLAG_TX_COMP_ERR;
  5208. dp_tx_comp_free_buf(soc, tx_desc, false);
  5209. dp_tx_desc_release(tx_desc, tx_desc->pool_id);
  5210. goto next_desc;
  5211. }
  5212. if (!(tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED) ||
  5213. !(tx_desc->flags & DP_TX_DESC_FLAG_QUEUED_TX)) {
  5214. dp_tx_comp_alert("Txdesc invalid, flgs = %x,id = %d",
  5215. tx_desc->flags, tx_desc->id);
  5216. qdf_assert_always(0);
  5217. }
  5218. /* Collect hw completion contents */
  5219. hal_tx_comp_desc_sync(tx_comp_hal_desc,
  5220. &tx_desc->comp, 1);
  5221. add_to_pool:
  5222. DP_HIST_PACKET_COUNT_INC(tx_desc->pdev->pdev_id);
  5223. add_to_pool2:
  5224. /* First ring descriptor on the cycle */
  5225. if (!head_desc) {
  5226. head_desc = tx_desc;
  5227. tail_desc = tx_desc;
  5228. }
  5229. tail_desc->next = tx_desc;
  5230. tx_desc->next = NULL;
  5231. tail_desc = tx_desc;
  5232. }
  5233. next_desc:
  5234. num_processed += !(count & DP_TX_NAPI_BUDGET_DIV_MASK);
  5235. /*
  5236. * Processed packet count is more than given quota
  5237. * stop to processing
  5238. */
  5239. count++;
  5240. dp_tx_prefetch_hw_sw_nbuf_desc(soc, hal_soc,
  5241. num_avail_for_reap,
  5242. hal_ring_hdl,
  5243. &last_prefetched_hw_desc,
  5244. &last_prefetched_sw_desc);
  5245. if (dp_tx_comp_loop_pkt_limit_hit(soc, count, max_reap_limit))
  5246. break;
  5247. }
  5248. dp_srng_access_end(int_ctx, soc, hal_ring_hdl);
  5249. /* Process the reaped descriptors */
  5250. if (head_desc)
  5251. dp_tx_comp_process_desc_list(soc, head_desc, ring_id);
  5252. DP_STATS_INC(soc, tx.tx_comp[ring_id], count);
  5253. /*
  5254. * If we are processing in near-full condition, there are 3 scenario
  5255. * 1) Ring entries has reached critical state
  5256. * 2) Ring entries are still near high threshold
  5257. * 3) Ring entries are below the safe level
  5258. *
  5259. * One more loop will move the state to normal processing and yield
  5260. */
  5261. if (ring_near_full)
  5262. goto more_data;
  5263. if (dp_tx_comp_enable_eol_data_check(soc)) {
  5264. if (num_processed >= quota)
  5265. force_break = true;
  5266. if (!force_break &&
  5267. hal_srng_dst_peek_sync_locked(soc->hal_soc,
  5268. hal_ring_hdl)) {
  5269. DP_STATS_INC(soc, tx.hp_oos2, 1);
  5270. if (!hif_exec_should_yield(soc->hif_handle,
  5271. int_ctx->dp_intr_id))
  5272. goto more_data;
  5273. num_avail_for_reap =
  5274. hal_srng_dst_num_valid_locked(soc->hal_soc,
  5275. hal_ring_hdl,
  5276. true);
  5277. if (qdf_unlikely(num_entries &&
  5278. (num_avail_for_reap >=
  5279. num_entries >> 1))) {
  5280. DP_STATS_INC(soc, tx.near_full, 1);
  5281. goto more_data;
  5282. }
  5283. }
  5284. }
  5285. DP_TX_HIST_STATS_PER_PDEV();
  5286. return num_processed;
  5287. }
  5288. #ifdef FEATURE_WLAN_TDLS
  5289. qdf_nbuf_t dp_tx_non_std(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
  5290. enum ol_tx_spec tx_spec, qdf_nbuf_t msdu_list)
  5291. {
  5292. struct dp_soc *soc = cdp_soc_t_to_dp_soc(soc_hdl);
  5293. struct dp_vdev *vdev = dp_vdev_get_ref_by_id(soc, vdev_id,
  5294. DP_MOD_ID_TDLS);
  5295. if (!vdev) {
  5296. dp_err("vdev handle for id %d is NULL", vdev_id);
  5297. return NULL;
  5298. }
  5299. if (tx_spec & OL_TX_SPEC_NO_FREE)
  5300. vdev->is_tdls_frame = true;
  5301. dp_vdev_unref_delete(soc, vdev, DP_MOD_ID_TDLS);
  5302. return dp_tx_send(soc_hdl, vdev_id, msdu_list);
  5303. }
  5304. #endif
  5305. /**
  5306. * dp_tx_vdev_attach() - attach vdev to dp tx
  5307. * @vdev: virtual device instance
  5308. *
  5309. * Return: QDF_STATUS_SUCCESS: success
  5310. * QDF_STATUS_E_RESOURCES: Error return
  5311. */
  5312. QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
  5313. {
  5314. int pdev_id;
  5315. /*
  5316. * Fill HTT TCL Metadata with Vdev ID and MAC ID
  5317. */
  5318. DP_TX_TCL_METADATA_TYPE_SET(vdev->htt_tcl_metadata,
  5319. DP_TCL_METADATA_TYPE_VDEV_BASED);
  5320. DP_TX_TCL_METADATA_VDEV_ID_SET(vdev->htt_tcl_metadata,
  5321. vdev->vdev_id);
  5322. pdev_id =
  5323. dp_get_target_pdev_id_for_host_pdev_id(vdev->pdev->soc,
  5324. vdev->pdev->pdev_id);
  5325. DP_TX_TCL_METADATA_PDEV_ID_SET(vdev->htt_tcl_metadata, pdev_id);
  5326. /*
  5327. * Set HTT Extension Valid bit to 0 by default
  5328. */
  5329. DP_TX_TCL_METADATA_VALID_HTT_SET(vdev->htt_tcl_metadata, 0);
  5330. dp_tx_vdev_update_search_flags(vdev);
  5331. return QDF_STATUS_SUCCESS;
  5332. }
  5333. #ifndef FEATURE_WDS
  5334. static inline bool dp_tx_da_search_override(struct dp_vdev *vdev)
  5335. {
  5336. return false;
  5337. }
  5338. #endif
  5339. /**
  5340. * dp_tx_vdev_update_search_flags() - Update vdev flags as per opmode
  5341. * @vdev: virtual device instance
  5342. *
  5343. * Return: void
  5344. *
  5345. */
  5346. void dp_tx_vdev_update_search_flags(struct dp_vdev *vdev)
  5347. {
  5348. struct dp_soc *soc = vdev->pdev->soc;
  5349. /*
  5350. * Enable both AddrY (SA based search) and AddrX (Da based search)
  5351. * for TDLS link
  5352. *
  5353. * Enable AddrY (SA based search) only for non-WDS STA and
  5354. * ProxySTA VAP (in HKv1) modes.
  5355. *
  5356. * In all other VAP modes, only DA based search should be
  5357. * enabled
  5358. */
  5359. if (vdev->opmode == wlan_op_mode_sta &&
  5360. vdev->tdls_link_connected)
  5361. vdev->hal_desc_addr_search_flags =
  5362. (HAL_TX_DESC_ADDRX_EN | HAL_TX_DESC_ADDRY_EN);
  5363. else if ((vdev->opmode == wlan_op_mode_sta) &&
  5364. !dp_tx_da_search_override(vdev))
  5365. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRY_EN;
  5366. else
  5367. vdev->hal_desc_addr_search_flags = HAL_TX_DESC_ADDRX_EN;
  5368. if (vdev->opmode == wlan_op_mode_sta && !vdev->tdls_link_connected)
  5369. vdev->search_type = soc->sta_mode_search_policy;
  5370. else
  5371. vdev->search_type = HAL_TX_ADDR_SEARCH_DEFAULT;
  5372. }
  5373. static inline bool
  5374. dp_is_tx_desc_flush_match(struct dp_pdev *pdev,
  5375. struct dp_vdev *vdev,
  5376. struct dp_tx_desc_s *tx_desc)
  5377. {
  5378. if (!(tx_desc && (tx_desc->flags & DP_TX_DESC_FLAG_ALLOCATED)))
  5379. return false;
  5380. /*
  5381. * if vdev is given, then only check whether desc
  5382. * vdev match. if vdev is NULL, then check whether
  5383. * desc pdev match.
  5384. */
  5385. return vdev ? (tx_desc->vdev_id == vdev->vdev_id) :
  5386. (tx_desc->pdev == pdev);
  5387. }
  5388. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5389. /**
  5390. * dp_tx_desc_flush() - release resources associated
  5391. * to TX Desc
  5392. *
  5393. * @dp_pdev: Handle to DP pdev structure
  5394. * @vdev: virtual device instance
  5395. * NULL: no specific Vdev is required and check all allcated TX desc
  5396. * on this pdev.
  5397. * Non-NULL: only check the allocated TX Desc associated to this Vdev.
  5398. *
  5399. * @force_free:
  5400. * true: flush the TX desc.
  5401. * false: only reset the Vdev in each allocated TX desc
  5402. * that associated to current Vdev.
  5403. *
  5404. * This function will go through the TX desc pool to flush
  5405. * the outstanding TX data or reset Vdev to NULL in associated TX
  5406. * Desc.
  5407. */
  5408. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5409. bool force_free)
  5410. {
  5411. uint8_t i;
  5412. uint32_t j;
  5413. uint32_t num_desc, page_id, offset;
  5414. uint16_t num_desc_per_page;
  5415. struct dp_soc *soc = pdev->soc;
  5416. struct dp_tx_desc_s *tx_desc = NULL;
  5417. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5418. if (!vdev && !force_free) {
  5419. dp_err("Reset TX desc vdev, Vdev param is required!");
  5420. return;
  5421. }
  5422. for (i = 0; i < MAX_TXDESC_POOLS; i++) {
  5423. tx_desc_pool = &soc->tx_desc[i];
  5424. if (!(tx_desc_pool->pool_size) ||
  5425. IS_TX_DESC_POOL_STATUS_INACTIVE(tx_desc_pool) ||
  5426. !(tx_desc_pool->desc_pages.cacheable_pages))
  5427. continue;
  5428. /*
  5429. * Add flow pool lock protection in case pool is freed
  5430. * due to all tx_desc is recycled when handle TX completion.
  5431. * this is not necessary when do force flush as:
  5432. * a. double lock will happen if dp_tx_desc_release is
  5433. * also trying to acquire it.
  5434. * b. dp interrupt has been disabled before do force TX desc
  5435. * flush in dp_pdev_deinit().
  5436. */
  5437. if (!force_free)
  5438. qdf_spin_lock_bh(&tx_desc_pool->flow_pool_lock);
  5439. num_desc = tx_desc_pool->pool_size;
  5440. num_desc_per_page =
  5441. tx_desc_pool->desc_pages.num_element_per_page;
  5442. for (j = 0; j < num_desc; j++) {
  5443. page_id = j / num_desc_per_page;
  5444. offset = j % num_desc_per_page;
  5445. if (qdf_unlikely(!(tx_desc_pool->
  5446. desc_pages.cacheable_pages)))
  5447. break;
  5448. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5449. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5450. /*
  5451. * Free TX desc if force free is
  5452. * required, otherwise only reset vdev
  5453. * in this TX desc.
  5454. */
  5455. if (force_free) {
  5456. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5457. dp_tx_comp_free_buf(soc, tx_desc,
  5458. false);
  5459. dp_tx_desc_release(tx_desc, i);
  5460. } else {
  5461. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5462. }
  5463. }
  5464. }
  5465. if (!force_free)
  5466. qdf_spin_unlock_bh(&tx_desc_pool->flow_pool_lock);
  5467. }
  5468. }
  5469. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5470. /**
  5471. * dp_tx_desc_reset_vdev() - reset vdev to NULL in TX Desc
  5472. *
  5473. * @soc: Handle to DP soc structure
  5474. * @tx_desc: pointer of one TX desc
  5475. * @desc_pool_id: TX Desc pool id
  5476. */
  5477. static inline void
  5478. dp_tx_desc_reset_vdev(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
  5479. uint8_t desc_pool_id)
  5480. {
  5481. TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
  5482. tx_desc->vdev_id = DP_INVALID_VDEV_ID;
  5483. TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
  5484. }
  5485. void dp_tx_desc_flush(struct dp_pdev *pdev, struct dp_vdev *vdev,
  5486. bool force_free)
  5487. {
  5488. uint8_t i, num_pool;
  5489. uint32_t j;
  5490. uint32_t num_desc, page_id, offset;
  5491. uint16_t num_desc_per_page;
  5492. struct dp_soc *soc = pdev->soc;
  5493. struct dp_tx_desc_s *tx_desc = NULL;
  5494. struct dp_tx_desc_pool_s *tx_desc_pool = NULL;
  5495. if (!vdev && !force_free) {
  5496. dp_err("Reset TX desc vdev, Vdev param is required!");
  5497. return;
  5498. }
  5499. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5500. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5501. for (i = 0; i < num_pool; i++) {
  5502. tx_desc_pool = &soc->tx_desc[i];
  5503. if (!tx_desc_pool->desc_pages.cacheable_pages)
  5504. continue;
  5505. num_desc_per_page =
  5506. tx_desc_pool->desc_pages.num_element_per_page;
  5507. for (j = 0; j < num_desc; j++) {
  5508. page_id = j / num_desc_per_page;
  5509. offset = j % num_desc_per_page;
  5510. tx_desc = dp_tx_desc_find(soc, i, page_id, offset);
  5511. if (dp_is_tx_desc_flush_match(pdev, vdev, tx_desc)) {
  5512. if (force_free) {
  5513. tx_desc->flags |= DP_TX_DESC_FLAG_FLUSH;
  5514. dp_tx_comp_free_buf(soc, tx_desc,
  5515. false);
  5516. dp_tx_desc_release(tx_desc, i);
  5517. } else {
  5518. dp_tx_desc_reset_vdev(soc, tx_desc,
  5519. i);
  5520. }
  5521. }
  5522. }
  5523. }
  5524. }
  5525. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5526. /**
  5527. * dp_tx_vdev_detach() - detach vdev from dp tx
  5528. * @vdev: virtual device instance
  5529. *
  5530. * Return: QDF_STATUS_SUCCESS: success
  5531. * QDF_STATUS_E_RESOURCES: Error return
  5532. */
  5533. QDF_STATUS dp_tx_vdev_detach(struct dp_vdev *vdev)
  5534. {
  5535. struct dp_pdev *pdev = vdev->pdev;
  5536. /* Reset TX desc associated to this Vdev as NULL */
  5537. dp_tx_desc_flush(pdev, vdev, false);
  5538. return QDF_STATUS_SUCCESS;
  5539. }
  5540. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  5541. /* Pools will be allocated dynamically */
  5542. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5543. int num_desc)
  5544. {
  5545. uint8_t i;
  5546. for (i = 0; i < num_pool; i++) {
  5547. qdf_spinlock_create(&soc->tx_desc[i].flow_pool_lock);
  5548. soc->tx_desc[i].status = FLOW_POOL_INACTIVE;
  5549. }
  5550. return QDF_STATUS_SUCCESS;
  5551. }
  5552. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5553. uint32_t num_desc)
  5554. {
  5555. return QDF_STATUS_SUCCESS;
  5556. }
  5557. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5558. {
  5559. }
  5560. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5561. {
  5562. uint8_t i;
  5563. for (i = 0; i < num_pool; i++)
  5564. qdf_spinlock_destroy(&soc->tx_desc[i].flow_pool_lock);
  5565. }
  5566. #else /* QCA_LL_TX_FLOW_CONTROL_V2! */
  5567. static QDF_STATUS dp_tx_alloc_static_pools(struct dp_soc *soc, int num_pool,
  5568. uint32_t num_desc)
  5569. {
  5570. uint8_t i, count;
  5571. /* Allocate software Tx descriptor pools */
  5572. for (i = 0; i < num_pool; i++) {
  5573. if (dp_tx_desc_pool_alloc(soc, i, num_desc)) {
  5574. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5575. FL("Tx Desc Pool alloc %d failed %pK"),
  5576. i, soc);
  5577. goto fail;
  5578. }
  5579. }
  5580. return QDF_STATUS_SUCCESS;
  5581. fail:
  5582. for (count = 0; count < i; count++)
  5583. dp_tx_desc_pool_free(soc, count);
  5584. return QDF_STATUS_E_NOMEM;
  5585. }
  5586. static QDF_STATUS dp_tx_init_static_pools(struct dp_soc *soc, int num_pool,
  5587. uint32_t num_desc)
  5588. {
  5589. uint8_t i;
  5590. for (i = 0; i < num_pool; i++) {
  5591. if (dp_tx_desc_pool_init(soc, i, num_desc)) {
  5592. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  5593. FL("Tx Desc Pool init %d failed %pK"),
  5594. i, soc);
  5595. return QDF_STATUS_E_NOMEM;
  5596. }
  5597. }
  5598. return QDF_STATUS_SUCCESS;
  5599. }
  5600. static void dp_tx_deinit_static_pools(struct dp_soc *soc, int num_pool)
  5601. {
  5602. uint8_t i;
  5603. for (i = 0; i < num_pool; i++)
  5604. dp_tx_desc_pool_deinit(soc, i);
  5605. }
  5606. static void dp_tx_delete_static_pools(struct dp_soc *soc, int num_pool)
  5607. {
  5608. uint8_t i;
  5609. for (i = 0; i < num_pool; i++)
  5610. dp_tx_desc_pool_free(soc, i);
  5611. }
  5612. #endif /* !QCA_LL_TX_FLOW_CONTROL_V2 */
  5613. /**
  5614. * dp_tx_tso_cmn_desc_pool_deinit() - de-initialize TSO descriptors
  5615. * @soc: core txrx main context
  5616. * @num_pool: number of pools
  5617. *
  5618. */
  5619. void dp_tx_tso_cmn_desc_pool_deinit(struct dp_soc *soc, uint8_t num_pool)
  5620. {
  5621. dp_tx_tso_desc_pool_deinit(soc, num_pool);
  5622. dp_tx_tso_num_seg_pool_deinit(soc, num_pool);
  5623. }
  5624. /**
  5625. * dp_tx_tso_cmn_desc_pool_free() - free TSO descriptors
  5626. * @soc: core txrx main context
  5627. * @num_pool: number of pools
  5628. *
  5629. */
  5630. void dp_tx_tso_cmn_desc_pool_free(struct dp_soc *soc, uint8_t num_pool)
  5631. {
  5632. dp_tx_tso_desc_pool_free(soc, num_pool);
  5633. dp_tx_tso_num_seg_pool_free(soc, num_pool);
  5634. }
  5635. /**
  5636. * dp_soc_tx_desc_sw_pools_free() - free all TX descriptors
  5637. * @soc: core txrx main context
  5638. *
  5639. * This function frees all tx related descriptors as below
  5640. * 1. Regular TX descriptors (static pools)
  5641. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5642. * 3. TSO descriptors
  5643. *
  5644. */
  5645. void dp_soc_tx_desc_sw_pools_free(struct dp_soc *soc)
  5646. {
  5647. uint8_t num_pool;
  5648. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5649. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5650. dp_tx_ext_desc_pool_free(soc, num_pool);
  5651. dp_tx_delete_static_pools(soc, num_pool);
  5652. }
  5653. /**
  5654. * dp_soc_tx_desc_sw_pools_deinit() - de-initialize all TX descriptors
  5655. * @soc: core txrx main context
  5656. *
  5657. * This function de-initializes all tx related descriptors as below
  5658. * 1. Regular TX descriptors (static pools)
  5659. * 2. extension TX descriptors (used for ME, RAW, TSO etc...)
  5660. * 3. TSO descriptors
  5661. *
  5662. */
  5663. void dp_soc_tx_desc_sw_pools_deinit(struct dp_soc *soc)
  5664. {
  5665. uint8_t num_pool;
  5666. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5667. dp_tx_flow_control_deinit(soc);
  5668. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5669. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5670. dp_tx_deinit_static_pools(soc, num_pool);
  5671. }
  5672. /**
  5673. * dp_tso_attach() - TSO attach handler
  5674. * @txrx_soc: Opaque Dp handle
  5675. *
  5676. * Reserve TSO descriptor buffers
  5677. *
  5678. * Return: QDF_STATUS_E_FAILURE on failure or
  5679. * QDF_STATUS_SUCCESS on success
  5680. */
  5681. QDF_STATUS dp_tx_tso_cmn_desc_pool_alloc(struct dp_soc *soc,
  5682. uint8_t num_pool,
  5683. uint32_t num_desc)
  5684. {
  5685. if (dp_tx_tso_desc_pool_alloc(soc, num_pool, num_desc)) {
  5686. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5687. return QDF_STATUS_E_FAILURE;
  5688. }
  5689. if (dp_tx_tso_num_seg_pool_alloc(soc, num_pool, num_desc)) {
  5690. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5691. num_pool, soc);
  5692. return QDF_STATUS_E_FAILURE;
  5693. }
  5694. return QDF_STATUS_SUCCESS;
  5695. }
  5696. /**
  5697. * dp_tx_tso_cmn_desc_pool_init() - TSO cmn desc pool init
  5698. * @soc: DP soc handle
  5699. * @num_pool: Number of pools
  5700. * @num_desc: Number of descriptors
  5701. *
  5702. * Initialize TSO descriptor pools
  5703. *
  5704. * Return: QDF_STATUS_E_FAILURE on failure or
  5705. * QDF_STATUS_SUCCESS on success
  5706. */
  5707. QDF_STATUS dp_tx_tso_cmn_desc_pool_init(struct dp_soc *soc,
  5708. uint8_t num_pool,
  5709. uint32_t num_desc)
  5710. {
  5711. if (dp_tx_tso_desc_pool_init(soc, num_pool, num_desc)) {
  5712. dp_err("TSO Desc Pool alloc %d failed %pK", num_pool, soc);
  5713. return QDF_STATUS_E_FAILURE;
  5714. }
  5715. if (dp_tx_tso_num_seg_pool_init(soc, num_pool, num_desc)) {
  5716. dp_err("TSO Num of seg Pool alloc %d failed %pK",
  5717. num_pool, soc);
  5718. return QDF_STATUS_E_FAILURE;
  5719. }
  5720. return QDF_STATUS_SUCCESS;
  5721. }
  5722. /**
  5723. * dp_soc_tx_desc_sw_pools_alloc() - Allocate tx descriptor pool memory
  5724. * @soc: core txrx main context
  5725. *
  5726. * This function allocates memory for following descriptor pools
  5727. * 1. regular sw tx descriptor pools (static pools)
  5728. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5729. * 3. TSO descriptor pools
  5730. *
  5731. * Return: QDF_STATUS_SUCCESS: success
  5732. * QDF_STATUS_E_RESOURCES: Error return
  5733. */
  5734. QDF_STATUS dp_soc_tx_desc_sw_pools_alloc(struct dp_soc *soc)
  5735. {
  5736. uint8_t num_pool;
  5737. uint32_t num_desc;
  5738. uint32_t num_ext_desc;
  5739. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5740. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5741. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5742. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  5743. "%s Tx Desc Alloc num_pool = %d, descs = %d",
  5744. __func__, num_pool, num_desc);
  5745. if ((num_pool > MAX_TXDESC_POOLS) ||
  5746. (num_desc > WLAN_CFG_NUM_TX_DESC_MAX))
  5747. goto fail1;
  5748. if (dp_tx_alloc_static_pools(soc, num_pool, num_desc))
  5749. goto fail1;
  5750. if (dp_tx_ext_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5751. goto fail2;
  5752. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5753. return QDF_STATUS_SUCCESS;
  5754. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5755. goto fail3;
  5756. return QDF_STATUS_SUCCESS;
  5757. fail3:
  5758. dp_tx_ext_desc_pool_free(soc, num_pool);
  5759. fail2:
  5760. dp_tx_delete_static_pools(soc, num_pool);
  5761. fail1:
  5762. return QDF_STATUS_E_RESOURCES;
  5763. }
  5764. /**
  5765. * dp_soc_tx_desc_sw_pools_init() - Initialise TX descriptor pools
  5766. * @soc: core txrx main context
  5767. *
  5768. * This function initializes the following TX descriptor pools
  5769. * 1. regular sw tx descriptor pools (static pools)
  5770. * 2. TX extension descriptor pools (ME, RAW, TSO etc...)
  5771. * 3. TSO descriptor pools
  5772. *
  5773. * Return: QDF_STATUS_SUCCESS: success
  5774. * QDF_STATUS_E_RESOURCES: Error return
  5775. */
  5776. QDF_STATUS dp_soc_tx_desc_sw_pools_init(struct dp_soc *soc)
  5777. {
  5778. uint8_t num_pool;
  5779. uint32_t num_desc;
  5780. uint32_t num_ext_desc;
  5781. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5782. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5783. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5784. if (dp_tx_init_static_pools(soc, num_pool, num_desc))
  5785. goto fail1;
  5786. if (dp_tx_ext_desc_pool_init(soc, num_pool, num_ext_desc))
  5787. goto fail2;
  5788. if (wlan_cfg_is_tso_desc_attach_defer(soc->wlan_cfg_ctx))
  5789. return QDF_STATUS_SUCCESS;
  5790. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5791. goto fail3;
  5792. dp_tx_flow_control_init(soc);
  5793. soc->process_tx_status = CONFIG_PROCESS_TX_STATUS;
  5794. return QDF_STATUS_SUCCESS;
  5795. fail3:
  5796. dp_tx_ext_desc_pool_deinit(soc, num_pool);
  5797. fail2:
  5798. dp_tx_deinit_static_pools(soc, num_pool);
  5799. fail1:
  5800. return QDF_STATUS_E_RESOURCES;
  5801. }
  5802. /**
  5803. * dp_tso_soc_attach() - Allocate and initialize TSO descriptors
  5804. * @txrx_soc: dp soc handle
  5805. *
  5806. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5807. * QDF_STATUS_E_FAILURE
  5808. */
  5809. QDF_STATUS dp_tso_soc_attach(struct cdp_soc_t *txrx_soc)
  5810. {
  5811. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5812. uint8_t num_pool;
  5813. uint32_t num_desc;
  5814. uint32_t num_ext_desc;
  5815. num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5816. num_desc = wlan_cfg_get_num_tx_desc(soc->wlan_cfg_ctx);
  5817. num_ext_desc = wlan_cfg_get_num_tx_ext_desc(soc->wlan_cfg_ctx);
  5818. if (dp_tx_tso_cmn_desc_pool_alloc(soc, num_pool, num_ext_desc))
  5819. return QDF_STATUS_E_FAILURE;
  5820. if (dp_tx_tso_cmn_desc_pool_init(soc, num_pool, num_ext_desc))
  5821. return QDF_STATUS_E_FAILURE;
  5822. return QDF_STATUS_SUCCESS;
  5823. }
  5824. /**
  5825. * dp_tso_soc_detach() - de-initialize and free the TSO descriptors
  5826. * @txrx_soc: dp soc handle
  5827. *
  5828. * Return: QDF_STATUS - QDF_STATUS_SUCCESS
  5829. */
  5830. QDF_STATUS dp_tso_soc_detach(struct cdp_soc_t *txrx_soc)
  5831. {
  5832. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  5833. uint8_t num_pool = wlan_cfg_get_num_tx_desc_pool(soc->wlan_cfg_ctx);
  5834. dp_tx_tso_cmn_desc_pool_deinit(soc, num_pool);
  5835. dp_tx_tso_cmn_desc_pool_free(soc, num_pool);
  5836. return QDF_STATUS_SUCCESS;
  5837. }
  5838. #ifdef CONFIG_DP_PKT_ADD_TIMESTAMP
  5839. void dp_pkt_add_timestamp(struct dp_vdev *vdev,
  5840. enum qdf_pkt_timestamp_index index, uint64_t time,
  5841. qdf_nbuf_t nbuf)
  5842. {
  5843. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled())) {
  5844. uint64_t tsf_time;
  5845. if (vdev->get_tsf_time) {
  5846. vdev->get_tsf_time(vdev->osif_vdev, time, &tsf_time);
  5847. qdf_add_dp_pkt_timestamp(nbuf, index, tsf_time);
  5848. }
  5849. }
  5850. }
  5851. void dp_pkt_get_timestamp(uint64_t *time)
  5852. {
  5853. if (qdf_unlikely(qdf_is_dp_pkt_timestamp_enabled()))
  5854. *time = qdf_get_log_timestamp();
  5855. }
  5856. #endif