wcd938x.c 136 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/slab.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/device.h>
  10. #include <linux/delay.h>
  11. #include <linux/kernel.h>
  12. #include <linux/component.h>
  13. #include <sound/soc.h>
  14. #include <sound/tlv.h>
  15. #include <soc/soundwire.h>
  16. #include <linux/regmap.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <asoc/wcdcal-hwdep.h>
  20. #include <asoc/msm-cdc-pinctrl.h>
  21. #include <asoc/msm-cdc-supply.h>
  22. #include <bindings/audio-codec-port-types.h>
  23. #include <linux/qti-regmap-debugfs.h>
  24. #include "wcd938x-registers.h"
  25. #include "wcd938x.h"
  26. #include "internal.h"
  27. #include "asoc/bolero-slave-internal.h"
  28. #define NUM_SWRS_DT_PARAMS 5
  29. #define WCD938X_VARIANT_ENTRY_SIZE 32
  30. #define WCD938X_VERSION_1_0 1
  31. #define WCD938X_VERSION_ENTRY_SIZE 32
  32. #define EAR_RX_PATH_AUX 1
  33. #define ADC_MODE_VAL_HIFI 0x01
  34. #define ADC_MODE_VAL_LO_HIF 0x02
  35. #define ADC_MODE_VAL_NORMAL 0x03
  36. #define ADC_MODE_VAL_LP 0x05
  37. #define ADC_MODE_VAL_ULP1 0x09
  38. #define ADC_MODE_VAL_ULP2 0x0B
  39. #define NUM_ATTEMPTS 5
  40. #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
  41. #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone"
  42. #define DAPM_MICBIAS3_STANDALONE "MIC BIAS3 Standalone"
  43. #define DAPM_MICBIAS4_STANDALONE "MIC BIAS4 Standalone"
  44. #define WCD938X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  45. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  46. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  47. SNDRV_PCM_RATE_384000)
  48. /* Fractional Rates */
  49. #define WCD938X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  50. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  51. #define WCD938X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  52. SNDRV_PCM_FMTBIT_S24_LE |\
  53. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  54. enum {
  55. CODEC_TX = 0,
  56. CODEC_RX,
  57. };
  58. enum {
  59. WCD_ADC1 = 0,
  60. WCD_ADC2,
  61. WCD_ADC3,
  62. WCD_ADC4,
  63. ALLOW_BUCK_DISABLE,
  64. HPH_COMP_DELAY,
  65. HPH_PA_DELAY,
  66. AMIC2_BCS_ENABLE,
  67. WCD_SUPPLIES_LPM_MODE,
  68. WCD_ADC1_MODE,
  69. WCD_ADC2_MODE,
  70. WCD_ADC3_MODE,
  71. WCD_ADC4_MODE,
  72. };
  73. enum {
  74. ADC_MODE_INVALID = 0,
  75. ADC_MODE_HIFI,
  76. ADC_MODE_LO_HIF,
  77. ADC_MODE_NORMAL,
  78. ADC_MODE_LP,
  79. ADC_MODE_ULP1,
  80. ADC_MODE_ULP2,
  81. };
  82. static u8 tx_mode_bit[] = {
  83. [ADC_MODE_INVALID] = 0x00,
  84. [ADC_MODE_HIFI] = 0x01,
  85. [ADC_MODE_LO_HIF] = 0x02,
  86. [ADC_MODE_NORMAL] = 0x04,
  87. [ADC_MODE_LP] = 0x08,
  88. [ADC_MODE_ULP1] = 0x10,
  89. [ADC_MODE_ULP2] = 0x20,
  90. };
  91. static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
  92. static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
  93. static int wcd938x_handle_post_irq(void *data);
  94. static int wcd938x_reset(struct device *dev);
  95. static int wcd938x_reset_low(struct device *dev);
  96. static int wcd938x_get_adc_mode(int val);
  97. static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
  98. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
  99. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
  100. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
  101. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
  102. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
  103. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
  104. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
  105. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
  106. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
  107. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
  108. REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
  109. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
  110. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
  111. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
  112. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
  113. REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
  114. REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
  115. REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
  116. REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
  117. REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
  118. };
  119. static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
  120. .name = "wcd938x",
  121. .irqs = wcd938x_irqs,
  122. .num_irqs = ARRAY_SIZE(wcd938x_irqs),
  123. .num_regs = 3,
  124. .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
  125. .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
  126. .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
  127. .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
  128. .use_ack = 1,
  129. .runtime_pm = false,
  130. .handle_post_irq = wcd938x_handle_post_irq,
  131. .irq_drv_data = NULL,
  132. };
  133. static int wcd938x_handle_post_irq(void *data)
  134. {
  135. struct wcd938x_priv *wcd938x = data;
  136. u32 sts1 = 0, sts2 = 0, sts3 = 0;
  137. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_0, &sts1);
  138. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_1, &sts2);
  139. regmap_read(wcd938x->regmap, WCD938X_DIGITAL_INTR_STATUS_2, &sts3);
  140. wcd938x->tx_swr_dev->slave_irq_pending =
  141. ((sts1 || sts2 || sts3) ? true : false);
  142. return IRQ_HANDLED;
  143. }
  144. static int wcd938x_swr_slv_get_current_bank(struct swr_device *dev, u8 devnum)
  145. {
  146. int ret = 0;
  147. int bank = 0;
  148. ret = swr_read(dev, devnum, SWR_SCP_CONTROL, &bank, 1);
  149. if (ret)
  150. return -EINVAL;
  151. return ((bank & 0x40) ? 1: 0);
  152. }
  153. static int wcd938x_get_clk_rate(int mode)
  154. {
  155. int rate;
  156. switch (mode) {
  157. case ADC_MODE_ULP2:
  158. rate = SWR_CLK_RATE_0P6MHZ;
  159. break;
  160. case ADC_MODE_ULP1:
  161. rate = SWR_CLK_RATE_1P2MHZ;
  162. break;
  163. case ADC_MODE_LP:
  164. rate = SWR_CLK_RATE_4P8MHZ;
  165. break;
  166. case ADC_MODE_NORMAL:
  167. case ADC_MODE_LO_HIF:
  168. case ADC_MODE_HIFI:
  169. case ADC_MODE_INVALID:
  170. default:
  171. rate = SWR_CLK_RATE_9P6MHZ;
  172. break;
  173. }
  174. return rate;
  175. }
  176. static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component,
  177. int rate, int bank)
  178. {
  179. u8 mask = (bank ? 0xF0 : 0x0F);
  180. u8 val = 0;
  181. switch (rate) {
  182. case SWR_CLK_RATE_0P6MHZ:
  183. val = (bank ? 0x60 : 0x06);
  184. break;
  185. case SWR_CLK_RATE_1P2MHZ:
  186. val = (bank ? 0x50 : 0x05);
  187. break;
  188. case SWR_CLK_RATE_2P4MHZ:
  189. val = (bank ? 0x30 : 0x03);
  190. break;
  191. case SWR_CLK_RATE_4P8MHZ:
  192. val = (bank ? 0x10 : 0x01);
  193. break;
  194. case SWR_CLK_RATE_9P6MHZ:
  195. default:
  196. val = 0x00;
  197. break;
  198. }
  199. snd_soc_component_update_bits(component,
  200. WCD938X_DIGITAL_SWR_TX_CLK_RATE,
  201. mask, val);
  202. return 0;
  203. }
  204. static int wcd938x_init_reg(struct snd_soc_component *component)
  205. {
  206. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
  207. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x80, 0x80);
  208. /* 1 msec delay as per HW requirement */
  209. usleep_range(1000, 1010);
  210. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x40, 0x40);
  211. /* 1 msec delay as per HW requirement */
  212. usleep_range(1000, 1010);
  213. snd_soc_component_update_bits(component, WCD938X_LDORXTX_CONFIG,
  214. 0x10, 0x00);
  215. snd_soc_component_update_bits(component, WCD938X_BIAS_VBG_FINE_ADJ,
  216. 0xF0, 0x80);
  217. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x80, 0x80);
  218. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x40);
  219. /* 10 msec delay as per HW requirement */
  220. usleep_range(10000, 10010);
  221. snd_soc_component_update_bits(component, WCD938X_ANA_BIAS, 0x40, 0x00);
  222. snd_soc_component_update_bits(component,
  223. WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
  224. 0xF0, 0x00);
  225. snd_soc_component_update_bits(component,
  226. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
  227. 0x1F, 0x15);
  228. snd_soc_component_update_bits(component,
  229. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
  230. 0x1F, 0x15);
  231. snd_soc_component_update_bits(component, WCD938X_HPH_REFBUFF_UHQA_CTL,
  232. 0xC0, 0x80);
  233. snd_soc_component_update_bits(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
  234. 0x02, 0x02);
  235. snd_soc_component_update_bits(component,
  236. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
  237. 0xFF, 0x14);
  238. snd_soc_component_update_bits(component,
  239. WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
  240. 0x1F, 0x08);
  241. snd_soc_component_update_bits(component,
  242. WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
  243. snd_soc_component_update_bits(component,
  244. WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
  245. snd_soc_component_update_bits(component,
  246. WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
  247. snd_soc_component_update_bits(component,
  248. WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
  249. snd_soc_component_update_bits(component,
  250. WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
  251. snd_soc_component_update_bits(component,
  252. WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
  253. snd_soc_component_update_bits(component,
  254. WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
  255. snd_soc_component_update_bits(component,
  256. WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
  257. snd_soc_component_update_bits(component,
  258. WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
  259. snd_soc_component_update_bits(component,
  260. WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
  261. snd_soc_component_update_bits(component, WCD938X_SLEEP_CTL, 0x0E,
  262. ((snd_soc_component_read(component,
  263. WCD938X_DIGITAL_EFUSE_REG_30) & 0x07) << 1));
  264. snd_soc_component_update_bits(component,
  265. WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
  266. return 0;
  267. }
  268. static int wcd938x_set_port_params(struct snd_soc_component *component,
  269. u8 slv_prt_type, u8 *port_id, u8 *num_ch,
  270. u8 *ch_mask, u32 *ch_rate,
  271. u8 *port_type, u8 path)
  272. {
  273. int i, j;
  274. u8 num_ports = 0;
  275. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  276. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  277. switch (path) {
  278. case CODEC_RX:
  279. map = &wcd938x->rx_port_mapping;
  280. num_ports = wcd938x->num_rx_ports;
  281. break;
  282. case CODEC_TX:
  283. map = &wcd938x->tx_port_mapping;
  284. num_ports = wcd938x->num_tx_ports;
  285. break;
  286. default:
  287. dev_err_ratelimited(component->dev, "%s Invalid path selected %u\n",
  288. __func__, path);
  289. return -EINVAL;
  290. }
  291. for (i = 0; i <= num_ports; i++) {
  292. for (j = 0; j < MAX_CH_PER_PORT; j++) {
  293. if ((*map)[i][j].slave_port_type == slv_prt_type)
  294. goto found;
  295. }
  296. }
  297. found:
  298. if (i > num_ports || j == MAX_CH_PER_PORT) {
  299. dev_err_ratelimited(component->dev, "%s Failed to find slave port for type %u\n",
  300. __func__, slv_prt_type);
  301. return -EINVAL;
  302. }
  303. *port_id = i;
  304. *num_ch = (*map)[i][j].num_ch;
  305. *ch_mask = (*map)[i][j].ch_mask;
  306. *ch_rate = (*map)[i][j].ch_rate;
  307. *port_type = (*map)[i][j].master_port_type;
  308. return 0;
  309. }
  310. /* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,*UC0*
  311. <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC1*
  312. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC2*
  313. <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>; *UC3 */
  314. static int wcd938x_parse_port_params(struct device *dev,
  315. char *prop, u8 path)
  316. {
  317. u32 *dt_array, map_size, max_uc;
  318. int ret = 0;
  319. u32 cnt = 0;
  320. u32 i, j;
  321. struct swr_port_params (*map)[SWR_UC_MAX][SWR_NUM_PORTS];
  322. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  323. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  324. switch (path) {
  325. case CODEC_TX:
  326. map = &wcd938x->tx_port_params;
  327. map_uc = &wcd938x->swr_tx_port_params;
  328. break;
  329. default:
  330. ret = -EINVAL;
  331. goto err_port_map;
  332. }
  333. if (!of_find_property(dev->of_node, prop,
  334. &map_size)) {
  335. dev_err(dev, "missing port mapping prop %s\n", prop);
  336. ret = -EINVAL;
  337. goto err_port_map;
  338. }
  339. max_uc = map_size / (SWR_NUM_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  340. if (max_uc != SWR_UC_MAX) {
  341. dev_err(dev, "%s: port params not provided for all usecases\n",
  342. __func__);
  343. ret = -EINVAL;
  344. goto err_port_map;
  345. }
  346. dt_array = kzalloc(map_size, GFP_KERNEL);
  347. if (!dt_array) {
  348. ret = -ENOMEM;
  349. goto err_alloc;
  350. }
  351. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  352. SWR_NUM_PORTS * SWR_PORT_PARAMS * max_uc);
  353. if (ret) {
  354. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  355. __func__, prop);
  356. goto err_pdata_fail;
  357. }
  358. for (i = 0; i < max_uc; i++) {
  359. for (j = 0; j < SWR_NUM_PORTS; j++) {
  360. cnt = (i * SWR_NUM_PORTS + j) * SWR_PORT_PARAMS;
  361. (*map)[i][j].offset1 = dt_array[cnt];
  362. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  363. }
  364. (*map_uc)[i].pp = &(*map)[i][0];
  365. }
  366. kfree(dt_array);
  367. return 0;
  368. err_pdata_fail:
  369. kfree(dt_array);
  370. err_alloc:
  371. err_port_map:
  372. return ret;
  373. }
  374. static int wcd938x_parse_port_mapping(struct device *dev,
  375. char *prop, u8 path)
  376. {
  377. u32 *dt_array, map_size, map_length;
  378. u32 port_num = 0, ch_mask, ch_rate, old_port_num = 0;
  379. u32 slave_port_type, master_port_type;
  380. u32 i, ch_iter = 0;
  381. int ret = 0;
  382. u8 *num_ports = NULL;
  383. struct codec_port_info (*map)[MAX_PORT][MAX_CH_PER_PORT];
  384. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  385. switch (path) {
  386. case CODEC_RX:
  387. map = &wcd938x->rx_port_mapping;
  388. num_ports = &wcd938x->num_rx_ports;
  389. break;
  390. case CODEC_TX:
  391. map = &wcd938x->tx_port_mapping;
  392. num_ports = &wcd938x->num_tx_ports;
  393. break;
  394. default:
  395. dev_err(dev, "%s Invalid path selected %u\n",
  396. __func__, path);
  397. return -EINVAL;
  398. }
  399. if (!of_find_property(dev->of_node, prop,
  400. &map_size)) {
  401. dev_err(dev, "missing port mapping prop %s\n", prop);
  402. ret = -EINVAL;
  403. goto err_port_map;
  404. }
  405. map_length = map_size / (NUM_SWRS_DT_PARAMS * sizeof(u32));
  406. dt_array = kzalloc(map_size, GFP_KERNEL);
  407. if (!dt_array) {
  408. ret = -ENOMEM;
  409. goto err_alloc;
  410. }
  411. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  412. NUM_SWRS_DT_PARAMS * map_length);
  413. if (ret) {
  414. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  415. __func__, prop);
  416. goto err_pdata_fail;
  417. }
  418. for (i = 0; i < map_length; i++) {
  419. port_num = dt_array[NUM_SWRS_DT_PARAMS * i];
  420. slave_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 1];
  421. ch_mask = dt_array[NUM_SWRS_DT_PARAMS * i + 2];
  422. ch_rate = dt_array[NUM_SWRS_DT_PARAMS * i + 3];
  423. master_port_type = dt_array[NUM_SWRS_DT_PARAMS * i + 4];
  424. if (port_num != old_port_num)
  425. ch_iter = 0;
  426. (*map)[port_num][ch_iter].slave_port_type = slave_port_type;
  427. (*map)[port_num][ch_iter].ch_mask = ch_mask;
  428. (*map)[port_num][ch_iter].master_port_type = master_port_type;
  429. (*map)[port_num][ch_iter].num_ch = __sw_hweight8(ch_mask);
  430. (*map)[port_num][ch_iter++].ch_rate = ch_rate;
  431. old_port_num = port_num;
  432. }
  433. *num_ports = port_num;
  434. kfree(dt_array);
  435. return 0;
  436. err_pdata_fail:
  437. kfree(dt_array);
  438. err_alloc:
  439. err_port_map:
  440. return ret;
  441. }
  442. static int wcd938x_tx_connect_port(struct snd_soc_component *component,
  443. u8 slv_port_type, int clk_rate,
  444. u8 enable)
  445. {
  446. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  447. u8 port_id, num_ch, ch_mask;
  448. u8 ch_type = 0;
  449. u32 ch_rate;
  450. int slave_ch_idx;
  451. u8 num_port = 1;
  452. int ret = 0;
  453. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  454. &num_ch, &ch_mask, &ch_rate,
  455. &ch_type, CODEC_TX);
  456. if (ret)
  457. return ret;
  458. if (clk_rate)
  459. ch_rate = clk_rate;
  460. slave_ch_idx = wcd938x_slave_get_slave_ch_val(slv_port_type);
  461. if (slave_ch_idx != -EINVAL)
  462. ch_type = wcd938x->tx_master_ch_map[slave_ch_idx];
  463. dev_dbg(component->dev, "%s slv_ch_idx: %d, mstr_ch_type: %d\n",
  464. __func__, slave_ch_idx, ch_type);
  465. if (enable)
  466. ret = swr_connect_port(wcd938x->tx_swr_dev, &port_id,
  467. num_port, &ch_mask, &ch_rate,
  468. &num_ch, &ch_type);
  469. else
  470. ret = swr_disconnect_port(wcd938x->tx_swr_dev, &port_id,
  471. num_port, &ch_mask, &ch_type);
  472. return ret;
  473. }
  474. static int wcd938x_rx_connect_port(struct snd_soc_component *component,
  475. u8 slv_port_type, u8 enable)
  476. {
  477. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  478. u8 port_id, num_ch, ch_mask, port_type;
  479. u32 ch_rate;
  480. u8 num_port = 1;
  481. int ret = 0;
  482. ret = wcd938x_set_port_params(component, slv_port_type, &port_id,
  483. &num_ch, &ch_mask, &ch_rate,
  484. &port_type, CODEC_RX);
  485. if (ret)
  486. return ret;
  487. if (enable)
  488. ret = swr_connect_port(wcd938x->rx_swr_dev, &port_id,
  489. num_port, &ch_mask, &ch_rate,
  490. &num_ch, &port_type);
  491. else
  492. ret = swr_disconnect_port(wcd938x->rx_swr_dev, &port_id,
  493. num_port, &ch_mask, &port_type);
  494. return ret;
  495. }
  496. static int wcd938x_rx_clk_enable(struct snd_soc_component *component)
  497. {
  498. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  499. if (wcd938x->rx_clk_cnt == 0) {
  500. snd_soc_component_update_bits(component,
  501. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
  502. snd_soc_component_update_bits(component,
  503. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x01);
  504. snd_soc_component_update_bits(component,
  505. WCD938X_DIGITAL_CDC_RX0_CTL, 0x40, 0x00);
  506. snd_soc_component_update_bits(component,
  507. WCD938X_DIGITAL_CDC_RX1_CTL, 0x40, 0x00);
  508. snd_soc_component_update_bits(component,
  509. WCD938X_DIGITAL_CDC_RX2_CTL, 0x40, 0x00);
  510. snd_soc_component_update_bits(component,
  511. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
  512. snd_soc_component_update_bits(component,
  513. WCD938X_AUX_AUXPA, 0x10, 0x10);
  514. }
  515. wcd938x->rx_clk_cnt++;
  516. return 0;
  517. }
  518. static int wcd938x_rx_clk_disable(struct snd_soc_component *component)
  519. {
  520. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  521. wcd938x->rx_clk_cnt--;
  522. if (wcd938x->rx_clk_cnt == 0) {
  523. snd_soc_component_update_bits(component,
  524. WCD938X_ANA_RX_SUPPLIES, 0x40, 0x00);
  525. snd_soc_component_update_bits(component,
  526. WCD938X_ANA_RX_SUPPLIES, 0x80, 0x00);
  527. snd_soc_component_update_bits(component,
  528. WCD938X_ANA_RX_SUPPLIES, 0x01, 0x00);
  529. snd_soc_component_update_bits(component,
  530. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
  531. snd_soc_component_update_bits(component,
  532. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
  533. }
  534. return 0;
  535. }
  536. /*
  537. * wcd938x_soc_get_mbhc: get wcd938x_mbhc handle of corresponding component
  538. * @component: handle to snd_soc_component *
  539. *
  540. * return wcd938x_mbhc handle or error code in case of failure
  541. */
  542. struct wcd938x_mbhc *wcd938x_soc_get_mbhc(struct snd_soc_component *component)
  543. {
  544. struct wcd938x_priv *wcd938x;
  545. if (!component) {
  546. pr_err_ratelimited("%s: Invalid params, NULL component\n", __func__);
  547. return NULL;
  548. }
  549. wcd938x = snd_soc_component_get_drvdata(component);
  550. if (!wcd938x) {
  551. pr_err_ratelimited("%s: wcd938x is NULL\n", __func__);
  552. return NULL;
  553. }
  554. return wcd938x->mbhc;
  555. }
  556. EXPORT_SYMBOL(wcd938x_soc_get_mbhc);
  557. static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
  558. struct snd_kcontrol *kcontrol,
  559. int event)
  560. {
  561. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  562. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  563. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  564. w->name, event);
  565. switch (event) {
  566. case SND_SOC_DAPM_PRE_PMU:
  567. wcd938x_rx_clk_enable(component);
  568. snd_soc_component_update_bits(component,
  569. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  570. snd_soc_component_update_bits(component,
  571. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  572. snd_soc_component_update_bits(component,
  573. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  574. break;
  575. case SND_SOC_DAPM_POST_PMU:
  576. snd_soc_component_update_bits(component,
  577. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x02);
  578. if (wcd938x->comp1_enable) {
  579. snd_soc_component_update_bits(component,
  580. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x02, 0x02);
  581. /* 5msec compander delay as per HW requirement */
  582. if (!wcd938x->comp2_enable ||
  583. (snd_soc_component_read(component,
  584. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
  585. usleep_range(5000, 5010);
  586. snd_soc_component_update_bits(component,
  587. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  588. } else {
  589. snd_soc_component_update_bits(component,
  590. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  591. 0x02, 0x00);
  592. snd_soc_component_update_bits(component,
  593. WCD938X_HPH_L_EN, 0x20, 0x20);
  594. }
  595. break;
  596. case SND_SOC_DAPM_POST_PMD:
  597. snd_soc_component_update_bits(component,
  598. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  599. 0x0F, 0x01);
  600. break;
  601. }
  602. return 0;
  603. }
  604. static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
  605. struct snd_kcontrol *kcontrol,
  606. int event)
  607. {
  608. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  609. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  610. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  611. w->name, event);
  612. switch (event) {
  613. case SND_SOC_DAPM_PRE_PMU:
  614. wcd938x_rx_clk_enable(component);
  615. snd_soc_component_update_bits(component,
  616. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
  617. snd_soc_component_update_bits(component,
  618. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x08, 0x08);
  619. snd_soc_component_update_bits(component,
  620. WCD938X_HPH_RDAC_CLK_CTL1, 0x80, 0x00);
  621. break;
  622. case SND_SOC_DAPM_POST_PMU:
  623. snd_soc_component_update_bits(component,
  624. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x02);
  625. if (wcd938x->comp2_enable) {
  626. snd_soc_component_update_bits(component,
  627. WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x01, 0x01);
  628. /* 5msec compander delay as per HW requirement */
  629. if (!wcd938x->comp1_enable ||
  630. (snd_soc_component_read(component,
  631. WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
  632. usleep_range(5000, 5010);
  633. snd_soc_component_update_bits(component,
  634. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00);
  635. } else {
  636. snd_soc_component_update_bits(component,
  637. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  638. 0x01, 0x00);
  639. snd_soc_component_update_bits(component,
  640. WCD938X_HPH_R_EN, 0x20, 0x20);
  641. }
  642. break;
  643. case SND_SOC_DAPM_POST_PMD:
  644. snd_soc_component_update_bits(component,
  645. WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
  646. 0x0F, 0x01);
  647. break;
  648. }
  649. return 0;
  650. }
  651. static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
  652. struct snd_kcontrol *kcontrol,
  653. int event)
  654. {
  655. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  656. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  657. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  658. w->name, event);
  659. switch (event) {
  660. case SND_SOC_DAPM_PRE_PMU:
  661. wcd938x_rx_clk_enable(component);
  662. wcd938x->ear_rx_path =
  663. snd_soc_component_read(
  664. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  665. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  666. snd_soc_component_update_bits(component,
  667. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x00);
  668. snd_soc_component_update_bits(component,
  669. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  670. snd_soc_component_update_bits(component,
  671. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  672. snd_soc_component_update_bits(component,
  673. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  674. } else {
  675. snd_soc_component_update_bits(component,
  676. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x04);
  677. snd_soc_component_update_bits(component,
  678. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
  679. if (wcd938x->comp1_enable)
  680. snd_soc_component_update_bits(component,
  681. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  682. 0x02, 0x02);
  683. }
  684. /* 5 msec delay as per HW requirement */
  685. usleep_range(5000, 5010);
  686. if (wcd938x->flyback_cur_det_disable == 0)
  687. snd_soc_component_update_bits(component,
  688. WCD938X_FLYBACK_EN,
  689. 0x04, 0x00);
  690. wcd938x->flyback_cur_det_disable++;
  691. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  692. WCD_CLSH_EVENT_PRE_DAC,
  693. WCD_CLSH_STATE_EAR,
  694. wcd938x->hph_mode);
  695. break;
  696. case SND_SOC_DAPM_POST_PMD:
  697. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  698. snd_soc_component_update_bits(component,
  699. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x00);
  700. snd_soc_component_update_bits(component,
  701. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  702. } else {
  703. snd_soc_component_update_bits(component,
  704. WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x04, 0x00);
  705. snd_soc_component_update_bits(component,
  706. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
  707. if (wcd938x->comp1_enable)
  708. snd_soc_component_update_bits(component,
  709. WCD938X_DIGITAL_CDC_COMP_CTL_0,
  710. 0x02, 0x00);
  711. }
  712. snd_soc_component_update_bits(component,
  713. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  714. snd_soc_component_update_bits(component,
  715. WCD938X_EAR_EAR_DAC_CON, 0x80, 0x80);
  716. break;
  717. };
  718. return 0;
  719. }
  720. static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
  721. struct snd_kcontrol *kcontrol,
  722. int event)
  723. {
  724. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  725. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  726. int ret = 0;
  727. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  728. w->name, event);
  729. switch (event) {
  730. case SND_SOC_DAPM_PRE_PMU:
  731. wcd938x_rx_clk_enable(component);
  732. snd_soc_component_update_bits(component,
  733. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x04);
  734. snd_soc_component_update_bits(component,
  735. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x04);
  736. snd_soc_component_update_bits(component,
  737. WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x01, 0x01);
  738. if (wcd938x->flyback_cur_det_disable == 0)
  739. snd_soc_component_update_bits(component,
  740. WCD938X_FLYBACK_EN,
  741. 0x04, 0x00);
  742. wcd938x->flyback_cur_det_disable++;
  743. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  744. WCD_CLSH_EVENT_PRE_DAC,
  745. WCD_CLSH_STATE_AUX,
  746. wcd938x->hph_mode);
  747. break;
  748. case SND_SOC_DAPM_POST_PMD:
  749. snd_soc_component_update_bits(component,
  750. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x04, 0x00);
  751. break;
  752. };
  753. return ret;
  754. }
  755. static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
  756. struct snd_kcontrol *kcontrol,
  757. int event)
  758. {
  759. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  760. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  761. int ret = 0;
  762. int hph_mode = wcd938x->hph_mode;
  763. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  764. w->name, event);
  765. switch (event) {
  766. case SND_SOC_DAPM_PRE_PMU:
  767. if (wcd938x->ldoh)
  768. snd_soc_component_update_bits(component,
  769. WCD938X_LDOH_MODE,
  770. 0x80, 0x80);
  771. if (wcd938x->update_wcd_event)
  772. wcd938x->update_wcd_event(wcd938x->handle,
  773. SLV_BOLERO_EVT_RX_MUTE,
  774. (WCD_RX2 << 0x10 | 0x1));
  775. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  776. wcd938x->rx_swr_dev->dev_num,
  777. true);
  778. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  779. WCD_CLSH_EVENT_PRE_DAC,
  780. WCD_CLSH_STATE_HPHR,
  781. hph_mode);
  782. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  783. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  784. hph_mode == CLS_H_ULP) {
  785. snd_soc_component_update_bits(component,
  786. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  787. }
  788. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  789. 0x10, 0x10);
  790. wcd_clsh_set_hph_mode(component, hph_mode);
  791. /* 100 usec delay as per HW requirement */
  792. usleep_range(100, 110);
  793. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  794. snd_soc_component_update_bits(component,
  795. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x03);
  796. break;
  797. case SND_SOC_DAPM_POST_PMU:
  798. /*
  799. * 7ms sleep is required if compander is enabled as per
  800. * HW requirement. If compander is disabled, then
  801. * 20ms delay is required.
  802. */
  803. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  804. if (!wcd938x->comp2_enable)
  805. usleep_range(20000, 20100);
  806. else
  807. usleep_range(7000, 7100);
  808. if (hph_mode == CLS_H_LP ||
  809. hph_mode == CLS_H_LOHIFI ||
  810. hph_mode == CLS_H_ULP)
  811. snd_soc_component_update_bits(component,
  812. WCD938X_HPH_REFBUFF_LP_CTL, 0x01,
  813. 0x00);
  814. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  815. }
  816. snd_soc_component_update_bits(component,
  817. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  818. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  819. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  820. snd_soc_component_update_bits(component,
  821. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  822. if (wcd938x->update_wcd_event)
  823. wcd938x->update_wcd_event(wcd938x->handle,
  824. SLV_BOLERO_EVT_RX_MUTE,
  825. (WCD_RX2 << 0x10));
  826. wcd_enable_irq(&wcd938x->irq_info,
  827. WCD938X_IRQ_HPHR_PDM_WD_INT);
  828. break;
  829. case SND_SOC_DAPM_PRE_PMD:
  830. if (wcd938x->update_wcd_event)
  831. wcd938x->update_wcd_event(wcd938x->handle,
  832. SLV_BOLERO_EVT_RX_MUTE,
  833. (WCD_RX2 << 0x10 | 0x1));
  834. wcd_disable_irq(&wcd938x->irq_info,
  835. WCD938X_IRQ_HPHR_PDM_WD_INT);
  836. if (wcd938x->update_wcd_event && wcd938x->comp2_enable)
  837. wcd938x->update_wcd_event(wcd938x->handle,
  838. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  839. (WCD_RX2 << 0x10));
  840. /*
  841. * 7ms sleep is required if compander is enabled as per
  842. * HW requirement. If compander is disabled, then
  843. * 20ms delay is required.
  844. */
  845. if (!wcd938x->comp2_enable)
  846. usleep_range(20000, 20100);
  847. else
  848. usleep_range(7000, 7100);
  849. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  850. 0x40, 0x00);
  851. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  852. WCD_EVENT_PRE_HPHR_PA_OFF,
  853. &wcd938x->mbhc->wcd_mbhc);
  854. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  855. break;
  856. case SND_SOC_DAPM_POST_PMD:
  857. /*
  858. * 7ms sleep is required if compander is enabled as per
  859. * HW requirement. If compander is disabled, then
  860. * 20ms delay is required.
  861. */
  862. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  863. if (!wcd938x->comp2_enable)
  864. usleep_range(20000, 20100);
  865. else
  866. usleep_range(7000, 7100);
  867. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  868. }
  869. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  870. WCD_EVENT_POST_HPHR_PA_OFF,
  871. &wcd938x->mbhc->wcd_mbhc);
  872. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  873. 0x10, 0x00);
  874. snd_soc_component_update_bits(component,
  875. WCD938X_DIGITAL_PDM_WD_CTL1, 0x07, 0x00);
  876. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  877. WCD_CLSH_EVENT_POST_PA,
  878. WCD_CLSH_STATE_HPHR,
  879. hph_mode);
  880. if (wcd938x->ldoh)
  881. snd_soc_component_update_bits(component,
  882. WCD938X_LDOH_MODE,
  883. 0x80, 0x00);
  884. break;
  885. };
  886. return ret;
  887. }
  888. static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
  889. struct snd_kcontrol *kcontrol,
  890. int event)
  891. {
  892. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  893. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  894. int ret = 0;
  895. int hph_mode = wcd938x->hph_mode;
  896. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  897. w->name, event);
  898. switch (event) {
  899. case SND_SOC_DAPM_PRE_PMU:
  900. if (wcd938x->ldoh)
  901. snd_soc_component_update_bits(component,
  902. WCD938X_LDOH_MODE,
  903. 0x80, 0x80);
  904. if (wcd938x->update_wcd_event)
  905. wcd938x->update_wcd_event(wcd938x->handle,
  906. SLV_BOLERO_EVT_RX_MUTE,
  907. (WCD_RX1 << 0x10 | 0x01));
  908. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  909. wcd938x->rx_swr_dev->dev_num,
  910. true);
  911. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  912. WCD_CLSH_EVENT_PRE_DAC,
  913. WCD_CLSH_STATE_HPHL,
  914. hph_mode);
  915. wcd_clsh_set_hph_mode(component, CLS_H_HIFI);
  916. if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
  917. hph_mode == CLS_H_ULP) {
  918. snd_soc_component_update_bits(component,
  919. WCD938X_HPH_REFBUFF_LP_CTL, 0x01, 0x01);
  920. }
  921. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  922. 0x20, 0x20);
  923. wcd_clsh_set_hph_mode(component, hph_mode);
  924. /* 100 usec delay as per HW requirement */
  925. usleep_range(100, 110);
  926. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  927. snd_soc_component_update_bits(component,
  928. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x03);
  929. break;
  930. case SND_SOC_DAPM_POST_PMU:
  931. /*
  932. * 7ms sleep is required if compander is enabled as per
  933. * HW requirement. If compander is disabled, then
  934. * 20ms delay is required.
  935. */
  936. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  937. if (!wcd938x->comp1_enable)
  938. usleep_range(20000, 20100);
  939. else
  940. usleep_range(7000, 7100);
  941. if (hph_mode == CLS_H_LP ||
  942. hph_mode == CLS_H_LOHIFI ||
  943. hph_mode == CLS_H_ULP)
  944. snd_soc_component_update_bits(component,
  945. WCD938X_HPH_REFBUFF_LP_CTL,
  946. 0x01, 0x00);
  947. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  948. }
  949. snd_soc_component_update_bits(component,
  950. WCD938X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02);
  951. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  952. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  953. snd_soc_component_update_bits(component,
  954. WCD938X_ANA_RX_SUPPLIES, 0x02, 0x02);
  955. if (wcd938x->update_wcd_event)
  956. wcd938x->update_wcd_event(wcd938x->handle,
  957. SLV_BOLERO_EVT_RX_MUTE,
  958. (WCD_RX1 << 0x10));
  959. wcd_enable_irq(&wcd938x->irq_info,
  960. WCD938X_IRQ_HPHL_PDM_WD_INT);
  961. break;
  962. case SND_SOC_DAPM_PRE_PMD:
  963. if (wcd938x->update_wcd_event)
  964. wcd938x->update_wcd_event(wcd938x->handle,
  965. SLV_BOLERO_EVT_RX_MUTE,
  966. (WCD_RX1 << 0x10 | 0x1));
  967. wcd_disable_irq(&wcd938x->irq_info,
  968. WCD938X_IRQ_HPHL_PDM_WD_INT);
  969. if (wcd938x->update_wcd_event && wcd938x->comp1_enable)
  970. wcd938x->update_wcd_event(wcd938x->handle,
  971. SLV_BOLERO_EVT_RX_COMPANDER_SOFT_RST,
  972. (WCD_RX1 << 0x10));
  973. /*
  974. * 7ms sleep is required if compander is enabled as per
  975. * HW requirement. If compander is disabled, then
  976. * 20ms delay is required.
  977. */
  978. if (!wcd938x->comp1_enable)
  979. usleep_range(20000, 20100);
  980. else
  981. usleep_range(7000, 7100);
  982. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  983. 0x80, 0x00);
  984. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  985. WCD_EVENT_PRE_HPHL_PA_OFF,
  986. &wcd938x->mbhc->wcd_mbhc);
  987. set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  988. break;
  989. case SND_SOC_DAPM_POST_PMD:
  990. /*
  991. * 7ms sleep is required if compander is enabled as per
  992. * HW requirement. If compander is disabled, then
  993. * 20ms delay is required.
  994. */
  995. if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
  996. if (!wcd938x->comp1_enable)
  997. usleep_range(21000, 21100);
  998. else
  999. usleep_range(7000, 7100);
  1000. clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
  1001. }
  1002. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1003. WCD_EVENT_POST_HPHL_PA_OFF,
  1004. &wcd938x->mbhc->wcd_mbhc);
  1005. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  1006. 0x20, 0x00);
  1007. snd_soc_component_update_bits(component,
  1008. WCD938X_DIGITAL_PDM_WD_CTL0, 0x07, 0x00);
  1009. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1010. WCD_CLSH_EVENT_POST_PA,
  1011. WCD_CLSH_STATE_HPHL,
  1012. hph_mode);
  1013. if (wcd938x->ldoh)
  1014. snd_soc_component_update_bits(component,
  1015. WCD938X_LDOH_MODE,
  1016. 0x80, 0x00);
  1017. break;
  1018. };
  1019. return ret;
  1020. }
  1021. static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
  1022. struct snd_kcontrol *kcontrol,
  1023. int event)
  1024. {
  1025. struct snd_soc_component *component =
  1026. snd_soc_dapm_to_component(w->dapm);
  1027. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1028. int hph_mode = wcd938x->hph_mode;
  1029. int ret = 0;
  1030. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1031. w->name, event);
  1032. switch (event) {
  1033. case SND_SOC_DAPM_PRE_PMU:
  1034. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1035. wcd938x->rx_swr_dev->dev_num,
  1036. true);
  1037. snd_soc_component_update_bits(component,
  1038. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x01);
  1039. break;
  1040. case SND_SOC_DAPM_POST_PMU:
  1041. /* 1 msec delay as per HW requirement */
  1042. usleep_range(1000, 1010);
  1043. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1044. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1045. snd_soc_component_update_bits(component,
  1046. WCD938X_ANA_RX_SUPPLIES,
  1047. 0x02, 0x02);
  1048. if (wcd938x->update_wcd_event)
  1049. wcd938x->update_wcd_event(wcd938x->handle,
  1050. SLV_BOLERO_EVT_RX_MUTE,
  1051. (WCD_RX3 << 0x10));
  1052. wcd_enable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  1053. break;
  1054. case SND_SOC_DAPM_PRE_PMD:
  1055. wcd_disable_irq(&wcd938x->irq_info,
  1056. WCD938X_IRQ_AUX_PDM_WD_INT);
  1057. if (wcd938x->update_wcd_event)
  1058. wcd938x->update_wcd_event(wcd938x->handle,
  1059. SLV_BOLERO_EVT_RX_MUTE,
  1060. (WCD_RX3 << 0x10 | 0x1));
  1061. break;
  1062. case SND_SOC_DAPM_POST_PMD:
  1063. /* 1 msec delay as per HW requirement */
  1064. usleep_range(1000, 1010);
  1065. snd_soc_component_update_bits(component,
  1066. WCD938X_DIGITAL_PDM_WD_CTL2, 0x01, 0x00);
  1067. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1068. WCD_CLSH_EVENT_POST_PA,
  1069. WCD_CLSH_STATE_AUX,
  1070. hph_mode);
  1071. wcd938x->flyback_cur_det_disable--;
  1072. if (wcd938x->flyback_cur_det_disable == 0)
  1073. snd_soc_component_update_bits(component,
  1074. WCD938X_FLYBACK_EN,
  1075. 0x04, 0x04);
  1076. break;
  1077. };
  1078. return ret;
  1079. }
  1080. static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
  1081. struct snd_kcontrol *kcontrol,
  1082. int event)
  1083. {
  1084. struct snd_soc_component *component =
  1085. snd_soc_dapm_to_component(w->dapm);
  1086. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1087. int hph_mode = wcd938x->hph_mode;
  1088. int ret = 0;
  1089. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1090. w->name, event);
  1091. switch (event) {
  1092. case SND_SOC_DAPM_PRE_PMU:
  1093. ret = swr_slvdev_datapath_control(wcd938x->rx_swr_dev,
  1094. wcd938x->rx_swr_dev->dev_num,
  1095. true);
  1096. /*
  1097. * Enable watchdog interrupt for HPHL or AUX
  1098. * depending on mux value
  1099. */
  1100. wcd938x->ear_rx_path =
  1101. snd_soc_component_read(
  1102. component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
  1103. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1104. snd_soc_component_update_bits(component,
  1105. WCD938X_DIGITAL_PDM_WD_CTL2,
  1106. 0x01, 0x01);
  1107. else
  1108. snd_soc_component_update_bits(component,
  1109. WCD938X_DIGITAL_PDM_WD_CTL0,
  1110. 0x07, 0x03);
  1111. if (!wcd938x->comp1_enable)
  1112. snd_soc_component_update_bits(component,
  1113. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80);
  1114. break;
  1115. case SND_SOC_DAPM_POST_PMU:
  1116. /* 6 msec delay as per HW requirement */
  1117. usleep_range(6000, 6010);
  1118. if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
  1119. hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
  1120. snd_soc_component_update_bits(component,
  1121. WCD938X_ANA_RX_SUPPLIES,
  1122. 0x02, 0x02);
  1123. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1124. if (wcd938x->update_wcd_event)
  1125. wcd938x->update_wcd_event(wcd938x->handle,
  1126. SLV_BOLERO_EVT_RX_MUTE,
  1127. (WCD_RX3 << 0x10));
  1128. wcd_enable_irq(&wcd938x->irq_info,
  1129. WCD938X_IRQ_AUX_PDM_WD_INT);
  1130. } else {
  1131. if (wcd938x->update_wcd_event)
  1132. wcd938x->update_wcd_event(wcd938x->handle,
  1133. SLV_BOLERO_EVT_RX_MUTE,
  1134. (WCD_RX1 << 0x10));
  1135. wcd_enable_irq(&wcd938x->irq_info,
  1136. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1137. }
  1138. break;
  1139. case SND_SOC_DAPM_PRE_PMD:
  1140. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
  1141. wcd_disable_irq(&wcd938x->irq_info,
  1142. WCD938X_IRQ_AUX_PDM_WD_INT);
  1143. if (wcd938x->update_wcd_event)
  1144. wcd938x->update_wcd_event(wcd938x->handle,
  1145. SLV_BOLERO_EVT_RX_MUTE,
  1146. (WCD_RX3 << 0x10 | 0x1));
  1147. } else {
  1148. wcd_disable_irq(&wcd938x->irq_info,
  1149. WCD938X_IRQ_HPHL_PDM_WD_INT);
  1150. if (wcd938x->update_wcd_event)
  1151. wcd938x->update_wcd_event(wcd938x->handle,
  1152. SLV_BOLERO_EVT_RX_MUTE,
  1153. (WCD_RX1 << 0x10 | 0x1));
  1154. }
  1155. break;
  1156. case SND_SOC_DAPM_POST_PMD:
  1157. if (!wcd938x->comp1_enable)
  1158. snd_soc_component_update_bits(component,
  1159. WCD938X_ANA_EAR_COMPANDER_CTL, 0x80, 0x00);
  1160. /* 7 msec delay as per HW requirement */
  1161. usleep_range(7000, 7010);
  1162. if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
  1163. snd_soc_component_update_bits(component,
  1164. WCD938X_DIGITAL_PDM_WD_CTL2,
  1165. 0x01, 0x00);
  1166. else
  1167. snd_soc_component_update_bits(component,
  1168. WCD938X_DIGITAL_PDM_WD_CTL0,
  1169. 0x07, 0x00);
  1170. wcd_cls_h_fsm(component, &wcd938x->clsh_info,
  1171. WCD_CLSH_EVENT_POST_PA,
  1172. WCD_CLSH_STATE_EAR,
  1173. hph_mode);
  1174. wcd938x->flyback_cur_det_disable--;
  1175. if (wcd938x->flyback_cur_det_disable == 0)
  1176. snd_soc_component_update_bits(component,
  1177. WCD938X_FLYBACK_EN,
  1178. 0x04, 0x04);
  1179. break;
  1180. };
  1181. return ret;
  1182. }
  1183. static int wcd938x_enable_clsh(struct snd_soc_dapm_widget *w,
  1184. struct snd_kcontrol *kcontrol,
  1185. int event)
  1186. {
  1187. struct snd_soc_component *component =
  1188. snd_soc_dapm_to_component(w->dapm);
  1189. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1190. int mode = wcd938x->hph_mode;
  1191. int ret = 0;
  1192. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1193. w->name, event);
  1194. if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP ||
  1195. mode == CLS_H_HIFI || mode == CLS_H_LP) {
  1196. wcd938x_rx_connect_port(component, CLSH,
  1197. SND_SOC_DAPM_EVENT_ON(event));
  1198. }
  1199. if (SND_SOC_DAPM_EVENT_OFF(event))
  1200. ret = swr_slvdev_datapath_control(
  1201. wcd938x->rx_swr_dev,
  1202. wcd938x->rx_swr_dev->dev_num,
  1203. false);
  1204. return ret;
  1205. }
  1206. static int wcd938x_enable_rx1(struct snd_soc_dapm_widget *w,
  1207. struct snd_kcontrol *kcontrol,
  1208. int event)
  1209. {
  1210. struct snd_soc_component *component =
  1211. snd_soc_dapm_to_component(w->dapm);
  1212. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1213. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1214. w->name, event);
  1215. switch (event) {
  1216. case SND_SOC_DAPM_PRE_PMU:
  1217. wcd938x_rx_connect_port(component, HPH_L, true);
  1218. if (wcd938x->comp1_enable)
  1219. wcd938x_rx_connect_port(component, COMP_L, true);
  1220. break;
  1221. case SND_SOC_DAPM_POST_PMD:
  1222. wcd938x_rx_connect_port(component, HPH_L, false);
  1223. if (wcd938x->comp1_enable)
  1224. wcd938x_rx_connect_port(component, COMP_L, false);
  1225. wcd938x_rx_clk_disable(component);
  1226. snd_soc_component_update_bits(component,
  1227. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1228. 0x01, 0x00);
  1229. break;
  1230. };
  1231. return 0;
  1232. }
  1233. static int wcd938x_enable_rx2(struct snd_soc_dapm_widget *w,
  1234. struct snd_kcontrol *kcontrol, int event)
  1235. {
  1236. struct snd_soc_component *component =
  1237. snd_soc_dapm_to_component(w->dapm);
  1238. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1239. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1240. w->name, event);
  1241. switch (event) {
  1242. case SND_SOC_DAPM_PRE_PMU:
  1243. wcd938x_rx_connect_port(component, HPH_R, true);
  1244. if (wcd938x->comp2_enable)
  1245. wcd938x_rx_connect_port(component, COMP_R, true);
  1246. break;
  1247. case SND_SOC_DAPM_POST_PMD:
  1248. wcd938x_rx_connect_port(component, HPH_R, false);
  1249. if (wcd938x->comp2_enable)
  1250. wcd938x_rx_connect_port(component, COMP_R, false);
  1251. wcd938x_rx_clk_disable(component);
  1252. snd_soc_component_update_bits(component,
  1253. WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
  1254. 0x02, 0x00);
  1255. break;
  1256. };
  1257. return 0;
  1258. }
  1259. static int wcd938x_enable_rx3(struct snd_soc_dapm_widget *w,
  1260. struct snd_kcontrol *kcontrol,
  1261. int event)
  1262. {
  1263. struct snd_soc_component *component =
  1264. snd_soc_dapm_to_component(w->dapm);
  1265. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1266. w->name, event);
  1267. switch (event) {
  1268. case SND_SOC_DAPM_PRE_PMU:
  1269. wcd938x_rx_connect_port(component, LO, true);
  1270. break;
  1271. case SND_SOC_DAPM_POST_PMD:
  1272. wcd938x_rx_connect_port(component, LO, false);
  1273. /* 6 msec delay as per HW requirement */
  1274. usleep_range(6000, 6010);
  1275. wcd938x_rx_clk_disable(component);
  1276. snd_soc_component_update_bits(component,
  1277. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x04, 0x00);
  1278. break;
  1279. }
  1280. return 0;
  1281. }
  1282. static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
  1283. struct snd_kcontrol *kcontrol,
  1284. int event)
  1285. {
  1286. struct snd_soc_component *component =
  1287. snd_soc_dapm_to_component(w->dapm);
  1288. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1289. u16 dmic_clk_reg, dmic_clk_en_reg;
  1290. s32 *dmic_clk_cnt;
  1291. u8 dmic_ctl_shift = 0;
  1292. u8 dmic_clk_shift = 0;
  1293. u8 dmic_clk_mask = 0;
  1294. u16 dmic2_left_en = 0;
  1295. int ret = 0;
  1296. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1297. w->name, event);
  1298. switch (w->shift) {
  1299. case 0:
  1300. case 1:
  1301. dmic_clk_cnt = &(wcd938x->dmic_0_1_clk_cnt);
  1302. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1303. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
  1304. dmic_clk_mask = 0x0F;
  1305. dmic_clk_shift = 0x00;
  1306. dmic_ctl_shift = 0x00;
  1307. break;
  1308. case 2:
  1309. dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1310. case 3:
  1311. dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
  1312. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
  1313. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
  1314. dmic_clk_mask = 0xF0;
  1315. dmic_clk_shift = 0x04;
  1316. dmic_ctl_shift = 0x01;
  1317. break;
  1318. case 4:
  1319. case 5:
  1320. dmic_clk_cnt = &(wcd938x->dmic_4_5_clk_cnt);
  1321. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1322. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
  1323. dmic_clk_mask = 0x0F;
  1324. dmic_clk_shift = 0x00;
  1325. dmic_ctl_shift = 0x02;
  1326. break;
  1327. case 6:
  1328. case 7:
  1329. dmic_clk_cnt = &(wcd938x->dmic_6_7_clk_cnt);
  1330. dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
  1331. dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
  1332. dmic_clk_mask = 0xF0;
  1333. dmic_clk_shift = 0x04;
  1334. dmic_ctl_shift = 0x03;
  1335. break;
  1336. default:
  1337. dev_err_ratelimited(component->dev, "%s: Invalid DMIC Selection\n",
  1338. __func__);
  1339. return -EINVAL;
  1340. };
  1341. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n",
  1342. __func__, event, (w->shift +1), *dmic_clk_cnt);
  1343. switch (event) {
  1344. case SND_SOC_DAPM_PRE_PMU:
  1345. snd_soc_component_update_bits(component,
  1346. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1347. (0x01 << dmic_ctl_shift), 0x00);
  1348. /* 250us sleep as per HW requirement */
  1349. usleep_range(250, 260);
  1350. if (dmic2_left_en)
  1351. snd_soc_component_update_bits(component,
  1352. dmic2_left_en, 0x80, 0x80);
  1353. /* Setting DMIC clock rate to 2.4MHz */
  1354. snd_soc_component_update_bits(component,
  1355. dmic_clk_reg, dmic_clk_mask,
  1356. (0x03 << dmic_clk_shift));
  1357. snd_soc_component_update_bits(component,
  1358. dmic_clk_en_reg, 0x08, 0x08);
  1359. /* enable clock scaling */
  1360. snd_soc_component_update_bits(component,
  1361. WCD938X_DIGITAL_CDC_DMIC_CTL, 0x06, 0x06);
  1362. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1363. wcd938x->tx_swr_dev->dev_num,
  1364. true);
  1365. break;
  1366. case SND_SOC_DAPM_POST_PMD:
  1367. wcd938x_tx_connect_port(component, DMIC0 + (w->shift), 0,
  1368. false);
  1369. snd_soc_component_update_bits(component,
  1370. WCD938X_DIGITAL_CDC_AMIC_CTL,
  1371. (0x01 << dmic_ctl_shift),
  1372. (0x01 << dmic_ctl_shift));
  1373. if (dmic2_left_en)
  1374. snd_soc_component_update_bits(component,
  1375. dmic2_left_en, 0x80, 0x00);
  1376. snd_soc_component_update_bits(component,
  1377. dmic_clk_en_reg, 0x08, 0x00);
  1378. break;
  1379. };
  1380. return ret;
  1381. }
  1382. /*
  1383. * wcd938x_get_micb_vout_ctl_val: converts micbias from volts to register value
  1384. * @micb_mv: micbias in mv
  1385. *
  1386. * return register value converted
  1387. */
  1388. int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
  1389. {
  1390. /* min micbias voltage is 1V and maximum is 2.85V */
  1391. if (micb_mv < 1000 || micb_mv > 2850) {
  1392. pr_err_ratelimited("%s: unsupported micbias voltage\n", __func__);
  1393. return -EINVAL;
  1394. }
  1395. return (micb_mv - 1000) / 50;
  1396. }
  1397. EXPORT_SYMBOL(wcd938x_get_micb_vout_ctl_val);
  1398. /*
  1399. * wcd938x_mbhc_micb_adjust_voltage: adjust specific micbias voltage
  1400. * @component: handle to snd_soc_component *
  1401. * @req_volt: micbias voltage to be set
  1402. * @micb_num: micbias to be set, e.g. micbias1 or micbias2
  1403. *
  1404. * return 0 if adjustment is success or error code in case of failure
  1405. */
  1406. int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
  1407. int req_volt, int micb_num)
  1408. {
  1409. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1410. int cur_vout_ctl, req_vout_ctl;
  1411. int micb_reg, micb_val, micb_en;
  1412. int ret = 0;
  1413. switch (micb_num) {
  1414. case MIC_BIAS_1:
  1415. micb_reg = WCD938X_ANA_MICB1;
  1416. break;
  1417. case MIC_BIAS_2:
  1418. micb_reg = WCD938X_ANA_MICB2;
  1419. break;
  1420. case MIC_BIAS_3:
  1421. micb_reg = WCD938X_ANA_MICB3;
  1422. break;
  1423. case MIC_BIAS_4:
  1424. micb_reg = WCD938X_ANA_MICB4;
  1425. break;
  1426. default:
  1427. return -EINVAL;
  1428. }
  1429. mutex_lock(&wcd938x->micb_lock);
  1430. /*
  1431. * If requested micbias voltage is same as current micbias
  1432. * voltage, then just return. Otherwise, adjust voltage as
  1433. * per requested value. If micbias is already enabled, then
  1434. * to avoid slow micbias ramp-up or down enable pull-up
  1435. * momentarily, change the micbias value and then re-enable
  1436. * micbias.
  1437. */
  1438. micb_val = snd_soc_component_read(component, micb_reg);
  1439. micb_en = (micb_val & 0xC0) >> 6;
  1440. cur_vout_ctl = micb_val & 0x3F;
  1441. req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
  1442. if (req_vout_ctl < 0) {
  1443. ret = -EINVAL;
  1444. goto exit;
  1445. }
  1446. if (cur_vout_ctl == req_vout_ctl) {
  1447. ret = 0;
  1448. goto exit;
  1449. }
  1450. dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
  1451. __func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
  1452. req_volt, micb_en);
  1453. if (micb_en == 0x1)
  1454. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x80);
  1455. snd_soc_component_update_bits(component, micb_reg, 0x3F, req_vout_ctl);
  1456. if (micb_en == 0x1) {
  1457. snd_soc_component_update_bits(component, micb_reg, 0xC0, 0x40);
  1458. /*
  1459. * Add 2ms delay as per HW requirement after enabling
  1460. * micbias
  1461. */
  1462. usleep_range(2000, 2100);
  1463. }
  1464. exit:
  1465. mutex_unlock(&wcd938x->micb_lock);
  1466. return ret;
  1467. }
  1468. EXPORT_SYMBOL(wcd938x_mbhc_micb_adjust_voltage);
  1469. static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
  1470. struct snd_kcontrol *kcontrol,
  1471. int event)
  1472. {
  1473. struct snd_soc_component *component =
  1474. snd_soc_dapm_to_component(w->dapm);
  1475. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1476. int ret = 0;
  1477. int bank = 0;
  1478. u8 mode = 0;
  1479. int i = 0;
  1480. int rate = 0;
  1481. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1482. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1483. /* power mode is applicable only to analog mics */
  1484. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1485. /* Get channel rate */
  1486. rate = wcd938x_get_clk_rate(wcd938x->tx_mode[w->shift - ADC1]);
  1487. }
  1488. switch (event) {
  1489. case SND_SOC_DAPM_PRE_PMU:
  1490. /* Check AMIC2 is connected to ADC2 to take an action on BCS */
  1491. if (w->shift == ADC2 && !(snd_soc_component_read(component,
  1492. WCD938X_TX_NEW_AMIC_MUX_CFG) & 0x80)) {
  1493. if (!wcd938x->bcs_dis) {
  1494. wcd938x_tx_connect_port(component, MBHC,
  1495. SWR_CLK_RATE_4P8MHZ, true);
  1496. set_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1497. }
  1498. }
  1499. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1500. set_bit(w->shift - ADC1, &wcd938x->status_mask);
  1501. wcd938x_tx_connect_port(component, w->shift, rate,
  1502. true);
  1503. } else {
  1504. wcd938x_tx_connect_port(component, w->shift,
  1505. SWR_CLK_RATE_2P4MHZ, true);
  1506. }
  1507. break;
  1508. case SND_SOC_DAPM_POST_PMD:
  1509. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1510. if (strnstr(w->name, "ADC1", sizeof("ADC1"))) {
  1511. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  1512. clear_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  1513. } else if (strnstr(w->name, "ADC2", sizeof("ADC2"))) {
  1514. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  1515. clear_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  1516. } else if (strnstr(w->name, "ADC3", sizeof("ADC3"))) {
  1517. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  1518. clear_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  1519. } else if (strnstr(w->name, "ADC4", sizeof("ADC4"))) {
  1520. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  1521. clear_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  1522. }
  1523. }
  1524. if (strnstr(w->name, "ADC", sizeof("ADC"))) {
  1525. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1526. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1527. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1528. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1529. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1530. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1531. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1532. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1533. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1534. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1535. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1536. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1537. if (mode != 0) {
  1538. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1539. if (mode & (1 << i)) {
  1540. i++;
  1541. break;
  1542. }
  1543. }
  1544. }
  1545. rate = wcd938x_get_clk_rate(i);
  1546. if (wcd938x->adc_count) {
  1547. rate = (wcd938x->adc_count * rate);
  1548. if (rate > SWR_CLK_RATE_9P6MHZ)
  1549. rate = SWR_CLK_RATE_9P6MHZ;
  1550. }
  1551. wcd938x_set_swr_clk_rate(component, rate, bank);
  1552. }
  1553. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1554. wcd938x->tx_swr_dev->dev_num,
  1555. false);
  1556. if (strnstr(w->name, "ADC", sizeof("ADC")))
  1557. wcd938x_set_swr_clk_rate(component, rate, !bank);
  1558. break;
  1559. };
  1560. return ret;
  1561. }
  1562. static int wcd938x_get_adc_mode(int val)
  1563. {
  1564. int ret = 0;
  1565. switch (val) {
  1566. case ADC_MODE_INVALID:
  1567. ret = ADC_MODE_VAL_NORMAL;
  1568. break;
  1569. case ADC_MODE_HIFI:
  1570. ret = ADC_MODE_VAL_HIFI;
  1571. break;
  1572. case ADC_MODE_LO_HIF:
  1573. ret = ADC_MODE_VAL_LO_HIF;
  1574. break;
  1575. case ADC_MODE_NORMAL:
  1576. ret = ADC_MODE_VAL_NORMAL;
  1577. break;
  1578. case ADC_MODE_LP:
  1579. ret = ADC_MODE_VAL_LP;
  1580. break;
  1581. case ADC_MODE_ULP1:
  1582. ret = ADC_MODE_VAL_ULP1;
  1583. break;
  1584. case ADC_MODE_ULP2:
  1585. ret = ADC_MODE_VAL_ULP2;
  1586. break;
  1587. default:
  1588. ret = -EINVAL;
  1589. pr_err_ratelimited("%s: invalid ADC mode value %d\n", __func__, val);
  1590. break;
  1591. }
  1592. return ret;
  1593. }
  1594. int wcd938x_tx_channel_config(struct snd_soc_component *component,
  1595. int channel, int mode)
  1596. {
  1597. int reg = WCD938X_ANA_TX_CH2, mask = 0, val = 0;
  1598. int ret = 0;
  1599. switch (channel) {
  1600. case 0:
  1601. reg = WCD938X_ANA_TX_CH2;
  1602. mask = 0x40;
  1603. break;
  1604. case 1:
  1605. reg = WCD938X_ANA_TX_CH2;
  1606. mask = 0x20;
  1607. break;
  1608. case 2:
  1609. reg = WCD938X_ANA_TX_CH4;
  1610. mask = 0x40;
  1611. break;
  1612. case 3:
  1613. reg = WCD938X_ANA_TX_CH4;
  1614. mask = 0x20;
  1615. break;
  1616. default:
  1617. pr_err_ratelimited("%s: Invalid channel num %d\n", __func__, channel);
  1618. ret = -EINVAL;
  1619. break;
  1620. }
  1621. if (!mode)
  1622. val = 0x00;
  1623. else
  1624. val = mask;
  1625. if (!ret)
  1626. snd_soc_component_update_bits(component, reg, mask, val);
  1627. return ret;
  1628. }
  1629. static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
  1630. struct snd_kcontrol *kcontrol,
  1631. int event){
  1632. struct snd_soc_component *component =
  1633. snd_soc_dapm_to_component(w->dapm);
  1634. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1635. int clk_rate = 0, ret = 0;
  1636. int mode = 0, i = 0, bank = 0;
  1637. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1638. w->name, event);
  1639. bank = (wcd938x_swr_slv_get_current_bank(wcd938x->tx_swr_dev,
  1640. wcd938x->tx_swr_dev->dev_num) ? 0 : 1);
  1641. switch (event) {
  1642. case SND_SOC_DAPM_PRE_PMU:
  1643. wcd938x->adc_count++;
  1644. if (test_bit(WCD_ADC1, &wcd938x->status_mask) ||
  1645. test_bit(WCD_ADC1_MODE, &wcd938x->status_mask))
  1646. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
  1647. if (test_bit(WCD_ADC2, &wcd938x->status_mask) ||
  1648. test_bit(WCD_ADC2_MODE, &wcd938x->status_mask))
  1649. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
  1650. if (test_bit(WCD_ADC3, &wcd938x->status_mask) ||
  1651. test_bit(WCD_ADC3_MODE, &wcd938x->status_mask))
  1652. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
  1653. if (test_bit(WCD_ADC4, &wcd938x->status_mask) ||
  1654. test_bit(WCD_ADC4_MODE, &wcd938x->status_mask))
  1655. mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
  1656. if (mode != 0) {
  1657. for (i = 0; i < ADC_MODE_ULP2; i++) {
  1658. if (mode & (1 << i)) {
  1659. i++;
  1660. break;
  1661. }
  1662. }
  1663. }
  1664. clk_rate = wcd938x_get_clk_rate(i);
  1665. /* clk_rate depends on number of paths getting enabled */
  1666. clk_rate = (wcd938x->adc_count * clk_rate);
  1667. if (clk_rate > SWR_CLK_RATE_9P6MHZ)
  1668. clk_rate = SWR_CLK_RATE_9P6MHZ;
  1669. wcd938x_set_swr_clk_rate(component, clk_rate, bank);
  1670. ret = swr_slvdev_datapath_control(wcd938x->tx_swr_dev,
  1671. wcd938x->tx_swr_dev->dev_num,
  1672. true);
  1673. wcd938x_set_swr_clk_rate(component, clk_rate, !bank);
  1674. break;
  1675. case SND_SOC_DAPM_POST_PMD:
  1676. wcd938x->adc_count--;
  1677. if (wcd938x->adc_count < 0)
  1678. wcd938x->adc_count = 0;
  1679. wcd938x_tx_connect_port(component, ADC1 + w->shift, 0, false);
  1680. if (w->shift + ADC1 == ADC2 &&
  1681. test_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask)) {
  1682. wcd938x_tx_connect_port(component, MBHC, 0,
  1683. false);
  1684. clear_bit(AMIC2_BCS_ENABLE, &wcd938x->status_mask);
  1685. }
  1686. break;
  1687. };
  1688. return ret;
  1689. }
  1690. void wcd938x_disable_bcs_before_slow_insert(struct snd_soc_component *component,
  1691. bool bcs_disable)
  1692. {
  1693. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1694. if (wcd938x->update_wcd_event) {
  1695. if (bcs_disable)
  1696. wcd938x->update_wcd_event(wcd938x->handle,
  1697. SLV_BOLERO_EVT_BCS_CLK_OFF, 0);
  1698. else
  1699. wcd938x->update_wcd_event(wcd938x->handle,
  1700. SLV_BOLERO_EVT_BCS_CLK_OFF, 1);
  1701. }
  1702. }
  1703. static int wcd938x_enable_req(struct snd_soc_dapm_widget *w,
  1704. struct snd_kcontrol *kcontrol, int event)
  1705. {
  1706. struct snd_soc_component *component =
  1707. snd_soc_dapm_to_component(w->dapm);
  1708. struct wcd938x_priv *wcd938x =
  1709. snd_soc_component_get_drvdata(component);
  1710. int ret = 0;
  1711. u8 mode = 0;
  1712. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  1713. w->name, event);
  1714. switch (event) {
  1715. case SND_SOC_DAPM_PRE_PMU:
  1716. snd_soc_component_update_bits(component,
  1717. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x08);
  1718. snd_soc_component_update_bits(component,
  1719. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1720. snd_soc_component_update_bits(component,
  1721. WCD938X_DIGITAL_CDC_REQ_CTL, 0x02, 0x02);
  1722. snd_soc_component_update_bits(component,
  1723. WCD938X_DIGITAL_CDC_REQ_CTL, 0x01, 0x00);
  1724. ret = wcd938x_tx_channel_config(component, w->shift, 1);
  1725. mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
  1726. if (mode < 0) {
  1727. dev_info_ratelimited(component->dev,
  1728. "%s: invalid mode, setting to normal mode\n",
  1729. __func__);
  1730. mode = ADC_MODE_VAL_NORMAL;
  1731. }
  1732. switch (w->shift) {
  1733. case 0:
  1734. snd_soc_component_update_bits(component,
  1735. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1736. mode);
  1737. snd_soc_component_update_bits(component,
  1738. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x10);
  1739. break;
  1740. case 1:
  1741. snd_soc_component_update_bits(component,
  1742. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1743. mode << 4);
  1744. snd_soc_component_update_bits(component,
  1745. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20);
  1746. break;
  1747. case 2:
  1748. snd_soc_component_update_bits(component,
  1749. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1750. mode);
  1751. snd_soc_component_update_bits(component,
  1752. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
  1753. break;
  1754. case 3:
  1755. snd_soc_component_update_bits(component,
  1756. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1757. mode << 4);
  1758. snd_soc_component_update_bits(component,
  1759. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80);
  1760. break;
  1761. default:
  1762. break;
  1763. }
  1764. ret |= wcd938x_tx_channel_config(component, w->shift, 0);
  1765. break;
  1766. case SND_SOC_DAPM_POST_PMD:
  1767. switch (w->shift) {
  1768. case 0:
  1769. snd_soc_component_update_bits(component,
  1770. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x0F,
  1771. 0x00);
  1772. snd_soc_component_update_bits(component,
  1773. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x10, 0x00);
  1774. break;
  1775. case 1:
  1776. snd_soc_component_update_bits(component,
  1777. WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0xF0,
  1778. 0x00);
  1779. snd_soc_component_update_bits(component,
  1780. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x00);
  1781. break;
  1782. case 2:
  1783. snd_soc_component_update_bits(component,
  1784. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x0F,
  1785. 0x00);
  1786. snd_soc_component_update_bits(component,
  1787. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00);
  1788. break;
  1789. case 3:
  1790. snd_soc_component_update_bits(component,
  1791. WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0xF0,
  1792. 0x00);
  1793. snd_soc_component_update_bits(component,
  1794. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00);
  1795. break;
  1796. default:
  1797. break;
  1798. }
  1799. if (wcd938x->adc_count == 0) {
  1800. snd_soc_component_update_bits(component,
  1801. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
  1802. snd_soc_component_update_bits(component,
  1803. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x08, 0x00);
  1804. }
  1805. break;
  1806. };
  1807. return ret;
  1808. }
  1809. int wcd938x_micbias_control(struct snd_soc_component *component,
  1810. int micb_num, int req, bool is_dapm)
  1811. {
  1812. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  1813. int micb_index = micb_num - 1;
  1814. u16 micb_reg;
  1815. int pre_off_event = 0, post_off_event = 0;
  1816. int post_on_event = 0, post_dapm_off = 0;
  1817. int post_dapm_on = 0;
  1818. int ret = 0;
  1819. if ((micb_index < 0) || (micb_index > WCD938X_MAX_MICBIAS - 1)) {
  1820. dev_err_ratelimited(component->dev,
  1821. "%s: Invalid micbias index, micb_ind:%d\n",
  1822. __func__, micb_index);
  1823. return -EINVAL;
  1824. }
  1825. if (NULL == wcd938x) {
  1826. dev_err_ratelimited(component->dev,
  1827. "%s: wcd938x private data is NULL\n", __func__);
  1828. return -EINVAL;
  1829. }
  1830. switch (micb_num) {
  1831. case MIC_BIAS_1:
  1832. micb_reg = WCD938X_ANA_MICB1;
  1833. break;
  1834. case MIC_BIAS_2:
  1835. micb_reg = WCD938X_ANA_MICB2;
  1836. pre_off_event = WCD_EVENT_PRE_MICBIAS_2_OFF;
  1837. post_off_event = WCD_EVENT_POST_MICBIAS_2_OFF;
  1838. post_on_event = WCD_EVENT_POST_MICBIAS_2_ON;
  1839. post_dapm_on = WCD_EVENT_POST_DAPM_MICBIAS_2_ON;
  1840. post_dapm_off = WCD_EVENT_POST_DAPM_MICBIAS_2_OFF;
  1841. break;
  1842. case MIC_BIAS_3:
  1843. micb_reg = WCD938X_ANA_MICB3;
  1844. break;
  1845. case MIC_BIAS_4:
  1846. micb_reg = WCD938X_ANA_MICB4;
  1847. break;
  1848. default:
  1849. dev_err_ratelimited(component->dev, "%s: Invalid micbias number: %d\n",
  1850. __func__, micb_num);
  1851. return -EINVAL;
  1852. };
  1853. mutex_lock(&wcd938x->micb_lock);
  1854. switch (req) {
  1855. case MICB_PULLUP_ENABLE:
  1856. if (!wcd938x->dev_up) {
  1857. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1858. __func__, req);
  1859. ret = -ENODEV;
  1860. goto done;
  1861. }
  1862. wcd938x->pullup_ref[micb_index]++;
  1863. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  1864. (wcd938x->micb_ref[micb_index] == 0))
  1865. snd_soc_component_update_bits(component, micb_reg,
  1866. 0xC0, 0x80);
  1867. break;
  1868. case MICB_PULLUP_DISABLE:
  1869. if (wcd938x->pullup_ref[micb_index] > 0)
  1870. wcd938x->pullup_ref[micb_index]--;
  1871. if (!wcd938x->dev_up) {
  1872. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1873. __func__, req);
  1874. ret = -ENODEV;
  1875. goto done;
  1876. }
  1877. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  1878. (wcd938x->micb_ref[micb_index] == 0))
  1879. snd_soc_component_update_bits(component, micb_reg,
  1880. 0xC0, 0x00);
  1881. break;
  1882. case MICB_ENABLE:
  1883. if (!wcd938x->dev_up) {
  1884. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1885. __func__, req);
  1886. ret = -ENODEV;
  1887. goto done;
  1888. }
  1889. wcd938x->micb_ref[micb_index]++;
  1890. if (wcd938x->micb_ref[micb_index] == 1) {
  1891. snd_soc_component_update_bits(component,
  1892. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0, 0xF0);
  1893. snd_soc_component_update_bits(component,
  1894. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  1895. snd_soc_component_update_bits(component,
  1896. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  1897. snd_soc_component_update_bits(component,
  1898. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  1899. snd_soc_component_update_bits(component,
  1900. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  1901. snd_soc_component_update_bits(component,
  1902. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  1903. snd_soc_component_update_bits(component,
  1904. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  1905. snd_soc_component_update_bits(component,
  1906. micb_reg, 0xC0, 0x40);
  1907. if (post_on_event)
  1908. blocking_notifier_call_chain(
  1909. &wcd938x->mbhc->notifier,
  1910. post_on_event,
  1911. &wcd938x->mbhc->wcd_mbhc);
  1912. }
  1913. if (is_dapm && post_dapm_on && wcd938x->mbhc)
  1914. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1915. post_dapm_on,
  1916. &wcd938x->mbhc->wcd_mbhc);
  1917. break;
  1918. case MICB_DISABLE:
  1919. if (wcd938x->micb_ref[micb_index] > 0)
  1920. wcd938x->micb_ref[micb_index]--;
  1921. if (!wcd938x->dev_up) {
  1922. dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
  1923. __func__, req);
  1924. ret = -ENODEV;
  1925. goto done;
  1926. }
  1927. if ((wcd938x->micb_ref[micb_index] == 0) &&
  1928. (wcd938x->pullup_ref[micb_index] > 0))
  1929. snd_soc_component_update_bits(component, micb_reg,
  1930. 0xC0, 0x80);
  1931. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  1932. (wcd938x->pullup_ref[micb_index] == 0)) {
  1933. if (pre_off_event && wcd938x->mbhc)
  1934. blocking_notifier_call_chain(
  1935. &wcd938x->mbhc->notifier,
  1936. pre_off_event,
  1937. &wcd938x->mbhc->wcd_mbhc);
  1938. snd_soc_component_update_bits(component, micb_reg,
  1939. 0xC0, 0x00);
  1940. if (post_off_event && wcd938x->mbhc)
  1941. blocking_notifier_call_chain(
  1942. &wcd938x->mbhc->notifier,
  1943. post_off_event,
  1944. &wcd938x->mbhc->wcd_mbhc);
  1945. }
  1946. if (is_dapm && post_dapm_off && wcd938x->mbhc)
  1947. blocking_notifier_call_chain(&wcd938x->mbhc->notifier,
  1948. post_dapm_off,
  1949. &wcd938x->mbhc->wcd_mbhc);
  1950. break;
  1951. };
  1952. dev_dbg(component->dev,
  1953. "%s: micb_num:%d, micb_ref: %d, pullup_ref: %d\n",
  1954. __func__, micb_num, wcd938x->micb_ref[micb_index],
  1955. wcd938x->pullup_ref[micb_index]);
  1956. done:
  1957. mutex_unlock(&wcd938x->micb_lock);
  1958. return ret;
  1959. }
  1960. EXPORT_SYMBOL(wcd938x_micbias_control);
  1961. static int wcd938x_get_logical_addr(struct swr_device *swr_dev)
  1962. {
  1963. int ret = 0;
  1964. uint8_t devnum = 0;
  1965. int num_retry = NUM_ATTEMPTS;
  1966. do {
  1967. /* retry after 1ms */
  1968. usleep_range(1000, 1010);
  1969. ret = swr_get_logical_dev_num(swr_dev, swr_dev->addr, &devnum);
  1970. } while (ret && --num_retry);
  1971. if (ret)
  1972. dev_err_ratelimited(&swr_dev->dev,
  1973. "%s get devnum %d for dev addr %llx failed\n",
  1974. __func__, devnum, swr_dev->addr);
  1975. swr_dev->dev_num = devnum;
  1976. return 0;
  1977. }
  1978. static bool get_usbc_hs_status(struct snd_soc_component *component,
  1979. struct wcd_mbhc_config *mbhc_cfg)
  1980. {
  1981. if (mbhc_cfg->enable_usbc_analog) {
  1982. if (!(snd_soc_component_read(component, WCD938X_ANA_MBHC_MECH)
  1983. & 0x20))
  1984. return true;
  1985. }
  1986. return false;
  1987. }
  1988. int wcd938x_swr_dmic_register_notifier(struct snd_soc_component *component,
  1989. struct notifier_block *nblock,
  1990. bool enable)
  1991. {
  1992. struct wcd938x_priv *wcd938x_priv;
  1993. if(NULL == component) {
  1994. pr_err_ratelimited("%s: wcd938x component is NULL\n", __func__);
  1995. return -EINVAL;
  1996. }
  1997. wcd938x_priv = snd_soc_component_get_drvdata(component);
  1998. wcd938x_priv->notify_swr_dmic = enable;
  1999. if (enable)
  2000. return blocking_notifier_chain_register(&wcd938x_priv->notifier,
  2001. nblock);
  2002. else
  2003. return blocking_notifier_chain_unregister(
  2004. &wcd938x_priv->notifier, nblock);
  2005. }
  2006. EXPORT_SYMBOL(wcd938x_swr_dmic_register_notifier);
  2007. static int wcd938x_event_notify(struct notifier_block *block,
  2008. unsigned long val,
  2009. void *data)
  2010. {
  2011. u16 event = (val & 0xffff);
  2012. int ret = 0;
  2013. struct wcd938x_priv *wcd938x = dev_get_drvdata((struct device *)data);
  2014. struct snd_soc_component *component = wcd938x->component;
  2015. struct wcd_mbhc *mbhc;
  2016. switch (event) {
  2017. case BOLERO_SLV_EVT_TX_CH_HOLD_CLEAR:
  2018. if (test_bit(WCD_ADC1, &wcd938x->status_mask)) {
  2019. snd_soc_component_update_bits(component,
  2020. WCD938X_ANA_TX_CH2, 0x40, 0x00);
  2021. set_bit(WCD_ADC1_MODE, &wcd938x->status_mask);
  2022. clear_bit(WCD_ADC1, &wcd938x->status_mask);
  2023. }
  2024. if (test_bit(WCD_ADC2, &wcd938x->status_mask)) {
  2025. snd_soc_component_update_bits(component,
  2026. WCD938X_ANA_TX_CH2, 0x20, 0x00);
  2027. set_bit(WCD_ADC2_MODE, &wcd938x->status_mask);
  2028. clear_bit(WCD_ADC2, &wcd938x->status_mask);
  2029. }
  2030. if (test_bit(WCD_ADC3, &wcd938x->status_mask)) {
  2031. snd_soc_component_update_bits(component,
  2032. WCD938X_ANA_TX_CH4, 0x40, 0x00);
  2033. set_bit(WCD_ADC3_MODE, &wcd938x->status_mask);
  2034. clear_bit(WCD_ADC3, &wcd938x->status_mask);
  2035. }
  2036. if (test_bit(WCD_ADC4, &wcd938x->status_mask)) {
  2037. snd_soc_component_update_bits(component,
  2038. WCD938X_ANA_TX_CH4, 0x20, 0x00);
  2039. set_bit(WCD_ADC4_MODE, &wcd938x->status_mask);
  2040. clear_bit(WCD_ADC4, &wcd938x->status_mask);
  2041. }
  2042. break;
  2043. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  2044. snd_soc_component_update_bits(component, WCD938X_ANA_HPH,
  2045. 0xC0, 0x00);
  2046. snd_soc_component_update_bits(component, WCD938X_ANA_EAR,
  2047. 0x80, 0x00);
  2048. snd_soc_component_update_bits(component, WCD938X_AUX_AUXPA,
  2049. 0x80, 0x00);
  2050. break;
  2051. case BOLERO_SLV_EVT_SSR_DOWN:
  2052. wcd938x->dev_up = false;
  2053. if(wcd938x->notify_swr_dmic)
  2054. blocking_notifier_call_chain(&wcd938x->notifier,
  2055. WCD938X_EVT_SSR_DOWN,
  2056. NULL);
  2057. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true;
  2058. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2059. wcd938x->usbc_hs_status = get_usbc_hs_status(component,
  2060. mbhc->mbhc_cfg);
  2061. wcd938x_mbhc_ssr_down(wcd938x->mbhc, component);
  2062. wcd938x_reset_low(wcd938x->dev);
  2063. break;
  2064. case BOLERO_SLV_EVT_SSR_UP:
  2065. wcd938x_reset(wcd938x->dev);
  2066. /* allow reset to take effect */
  2067. usleep_range(10000, 10010);
  2068. wcd938x_get_logical_addr(wcd938x->tx_swr_dev);
  2069. wcd938x_get_logical_addr(wcd938x->rx_swr_dev);
  2070. wcd938x_init_reg(component);
  2071. regcache_mark_dirty(wcd938x->regmap);
  2072. regcache_sync(wcd938x->regmap);
  2073. /* Initialize MBHC module */
  2074. mbhc = &wcd938x->mbhc->wcd_mbhc;
  2075. ret = wcd938x_mbhc_post_ssr_init(wcd938x->mbhc, component);
  2076. if (ret) {
  2077. dev_err_ratelimited(component->dev, "%s: mbhc initialization failed\n",
  2078. __func__);
  2079. } else {
  2080. wcd938x_mbhc_hs_detect(component, mbhc->mbhc_cfg);
  2081. }
  2082. wcd938x->mbhc->wcd_mbhc.deinit_in_progress = false;
  2083. wcd938x->dev_up = true;
  2084. if(wcd938x->notify_swr_dmic)
  2085. blocking_notifier_call_chain(&wcd938x->notifier,
  2086. WCD938X_EVT_SSR_UP,
  2087. NULL);
  2088. if (wcd938x->usbc_hs_status)
  2089. mdelay(500);
  2090. break;
  2091. case BOLERO_SLV_EVT_CLK_NOTIFY:
  2092. snd_soc_component_update_bits(component,
  2093. WCD938X_DIGITAL_TOP_CLK_CFG, 0x06,
  2094. ((val >> 0x10) << 0x01));
  2095. break;
  2096. default:
  2097. dev_dbg(component->dev, "%s: invalid event %d\n", __func__, event);
  2098. break;
  2099. }
  2100. return 0;
  2101. }
  2102. static int __wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2103. int event)
  2104. {
  2105. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2106. int micb_num;
  2107. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2108. __func__, w->name, event);
  2109. if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
  2110. micb_num = MIC_BIAS_1;
  2111. else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
  2112. micb_num = MIC_BIAS_2;
  2113. else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
  2114. micb_num = MIC_BIAS_3;
  2115. else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
  2116. micb_num = MIC_BIAS_4;
  2117. else
  2118. return -EINVAL;
  2119. switch (event) {
  2120. case SND_SOC_DAPM_PRE_PMU:
  2121. wcd938x_micbias_control(component, micb_num,
  2122. MICB_ENABLE, true);
  2123. break;
  2124. case SND_SOC_DAPM_POST_PMU:
  2125. /* 1 msec delay as per HW requirement */
  2126. usleep_range(1000, 1100);
  2127. break;
  2128. case SND_SOC_DAPM_POST_PMD:
  2129. wcd938x_micbias_control(component, micb_num,
  2130. MICB_DISABLE, true);
  2131. break;
  2132. };
  2133. return 0;
  2134. }
  2135. static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
  2136. struct snd_kcontrol *kcontrol,
  2137. int event)
  2138. {
  2139. return __wcd938x_codec_enable_micbias(w, event);
  2140. }
  2141. static int __wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2142. int event)
  2143. {
  2144. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  2145. int micb_num;
  2146. dev_dbg(component->dev, "%s: wname: %s, event: %d\n",
  2147. __func__, w->name, event);
  2148. if (strnstr(w->name, "VA MIC BIAS1", sizeof("VA MIC BIAS1")))
  2149. micb_num = MIC_BIAS_1;
  2150. else if (strnstr(w->name, "VA MIC BIAS2", sizeof("VA MIC BIAS2")))
  2151. micb_num = MIC_BIAS_2;
  2152. else if (strnstr(w->name, "VA MIC BIAS3", sizeof("VA MIC BIAS3")))
  2153. micb_num = MIC_BIAS_3;
  2154. else if (strnstr(w->name, "VA MIC BIAS4", sizeof("VA MIC BIAS4")))
  2155. micb_num = MIC_BIAS_4;
  2156. else
  2157. return -EINVAL;
  2158. switch (event) {
  2159. case SND_SOC_DAPM_PRE_PMU:
  2160. wcd938x_micbias_control(component, micb_num,
  2161. MICB_PULLUP_ENABLE, true);
  2162. break;
  2163. case SND_SOC_DAPM_POST_PMU:
  2164. /* 1 msec delay as per HW requirement */
  2165. usleep_range(1000, 1100);
  2166. break;
  2167. case SND_SOC_DAPM_POST_PMD:
  2168. wcd938x_micbias_control(component, micb_num,
  2169. MICB_PULLUP_DISABLE, true);
  2170. break;
  2171. };
  2172. return 0;
  2173. }
  2174. static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
  2175. struct snd_kcontrol *kcontrol,
  2176. int event)
  2177. {
  2178. return __wcd938x_codec_enable_micbias_pullup(w, event);
  2179. }
  2180. static int wcd938x_wakeup(void *handle, bool enable)
  2181. {
  2182. struct wcd938x_priv *priv;
  2183. int ret = 0;
  2184. if (!handle) {
  2185. pr_err_ratelimited("%s: NULL handle\n", __func__);
  2186. return -EINVAL;
  2187. }
  2188. priv = (struct wcd938x_priv *)handle;
  2189. if (!priv->tx_swr_dev) {
  2190. pr_err_ratelimited("%s: tx swr dev is NULL\n", __func__);
  2191. return -EINVAL;
  2192. }
  2193. mutex_lock(&priv->wakeup_lock);
  2194. if (enable)
  2195. ret = swr_device_wakeup_vote(priv->tx_swr_dev);
  2196. else
  2197. ret = swr_device_wakeup_unvote(priv->tx_swr_dev);
  2198. mutex_unlock(&priv->wakeup_lock);
  2199. return ret;
  2200. }
  2201. static int wcd938x_codec_force_enable_micbias(struct snd_soc_dapm_widget *w,
  2202. struct snd_kcontrol *kcontrol,
  2203. int event)
  2204. {
  2205. int ret = 0;
  2206. struct snd_soc_component *component =
  2207. snd_soc_dapm_to_component(w->dapm);
  2208. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2209. switch (event) {
  2210. case SND_SOC_DAPM_PRE_PMU:
  2211. wcd938x_wakeup(wcd938x, true);
  2212. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_PRE_PMU);
  2213. wcd938x_wakeup(wcd938x, false);
  2214. break;
  2215. case SND_SOC_DAPM_POST_PMD:
  2216. wcd938x_wakeup(wcd938x, true);
  2217. ret = __wcd938x_codec_enable_micbias(w, SND_SOC_DAPM_POST_PMD);
  2218. wcd938x_wakeup(wcd938x, false);
  2219. break;
  2220. }
  2221. return ret;
  2222. }
  2223. static int wcd938x_enable_micbias(struct wcd938x_priv *wcd938x,
  2224. int micb_num, int req)
  2225. {
  2226. int micb_index = micb_num - 1;
  2227. u16 micb_reg;
  2228. if (NULL == wcd938x) {
  2229. pr_err_ratelimited("%s: wcd938x private data is NULL\n", __func__);
  2230. return -EINVAL;
  2231. }
  2232. switch (micb_num) {
  2233. case MIC_BIAS_1:
  2234. micb_reg = WCD938X_ANA_MICB1;
  2235. break;
  2236. case MIC_BIAS_2:
  2237. micb_reg = WCD938X_ANA_MICB2;
  2238. break;
  2239. case MIC_BIAS_3:
  2240. micb_reg = WCD938X_ANA_MICB3;
  2241. break;
  2242. case MIC_BIAS_4:
  2243. micb_reg = WCD938X_ANA_MICB4;
  2244. break;
  2245. default:
  2246. pr_err_ratelimited("%s: Invalid micbias number: %d\n", __func__, micb_num);
  2247. return -EINVAL;
  2248. };
  2249. pr_debug("%s: req: %d micb_num: %d micb_ref: %d pullup_ref: %d\n",
  2250. __func__, req, micb_num, wcd938x->micb_ref[micb_index],
  2251. wcd938x->pullup_ref[micb_index]);
  2252. mutex_lock(&wcd938x->micb_lock);
  2253. switch (req) {
  2254. case MICB_ENABLE:
  2255. wcd938x->micb_ref[micb_index]++;
  2256. if (wcd938x->micb_ref[micb_index] == 1) {
  2257. regmap_update_bits(wcd938x->regmap,
  2258. WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xE0, 0xE0);
  2259. regmap_update_bits(wcd938x->regmap,
  2260. WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
  2261. regmap_update_bits(wcd938x->regmap,
  2262. WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x01, 0x01);
  2263. regmap_update_bits(wcd938x->regmap,
  2264. WCD938X_MICB1_TEST_CTL_2, 0x01, 0x01);
  2265. regmap_update_bits(wcd938x->regmap,
  2266. WCD938X_MICB2_TEST_CTL_2, 0x01, 0x01);
  2267. regmap_update_bits(wcd938x->regmap,
  2268. WCD938X_MICB3_TEST_CTL_2, 0x01, 0x01);
  2269. regmap_update_bits(wcd938x->regmap,
  2270. WCD938X_MICB4_TEST_CTL_2, 0x01, 0x01);
  2271. regmap_update_bits(wcd938x->regmap,
  2272. micb_reg, 0xC0, 0x40);
  2273. regmap_update_bits(wcd938x->regmap, micb_reg, 0x3F, 0x10);
  2274. }
  2275. break;
  2276. case MICB_PULLUP_ENABLE:
  2277. wcd938x->pullup_ref[micb_index]++;
  2278. if ((wcd938x->pullup_ref[micb_index] == 1) &&
  2279. (wcd938x->micb_ref[micb_index] == 0))
  2280. regmap_update_bits(wcd938x->regmap, micb_reg,
  2281. 0xC0, 0x80);
  2282. break;
  2283. case MICB_PULLUP_DISABLE:
  2284. if (wcd938x->pullup_ref[micb_index] > 0)
  2285. wcd938x->pullup_ref[micb_index]--;
  2286. if ((wcd938x->pullup_ref[micb_index] == 0) &&
  2287. (wcd938x->micb_ref[micb_index] == 0))
  2288. regmap_update_bits(wcd938x->regmap, micb_reg,
  2289. 0xC0, 0x00);
  2290. break;
  2291. case MICB_DISABLE:
  2292. if (wcd938x->micb_ref[micb_index] > 0)
  2293. wcd938x->micb_ref[micb_index]--;
  2294. if ((wcd938x->micb_ref[micb_index] == 0) &&
  2295. (wcd938x->pullup_ref[micb_index] > 0))
  2296. regmap_update_bits(wcd938x->regmap, micb_reg,
  2297. 0xC0, 0x80);
  2298. else if ((wcd938x->micb_ref[micb_index] == 0) &&
  2299. (wcd938x->pullup_ref[micb_index] == 0))
  2300. regmap_update_bits(wcd938x->regmap, micb_reg,
  2301. 0xC0, 0x00);
  2302. break;
  2303. };
  2304. mutex_unlock(&wcd938x->micb_lock);
  2305. return 0;
  2306. }
  2307. int wcd938x_codec_force_enable_micbias_v2(struct snd_soc_component *component,
  2308. int event, int micb_num)
  2309. {
  2310. struct wcd938x_priv *wcd938x_priv = NULL;
  2311. int ret = 0;
  2312. int micb_index = micb_num - 1;
  2313. if(NULL == component) {
  2314. pr_err_ratelimited("%s: wcd938x component is NULL\n", __func__);
  2315. return -EINVAL;
  2316. }
  2317. if(event != SND_SOC_DAPM_PRE_PMU && event != SND_SOC_DAPM_POST_PMD) {
  2318. pr_err_ratelimited("%s: invalid event: %d\n", __func__, event);
  2319. return -EINVAL;
  2320. }
  2321. if(micb_num < MIC_BIAS_1 || micb_num > MIC_BIAS_4) {
  2322. pr_err_ratelimited("%s: invalid mic bias num: %d\n", __func__, micb_num);
  2323. return -EINVAL;
  2324. }
  2325. wcd938x_priv = snd_soc_component_get_drvdata(component);
  2326. if (!wcd938x_priv->dev_up) {
  2327. if ((wcd938x_priv->pullup_ref[micb_index] > 0) &&
  2328. (event == SND_SOC_DAPM_POST_PMD)) {
  2329. wcd938x_priv->pullup_ref[micb_index]--;
  2330. ret = -ENODEV;
  2331. goto done;
  2332. }
  2333. }
  2334. switch (event) {
  2335. case SND_SOC_DAPM_PRE_PMU:
  2336. wcd938x_wakeup(wcd938x_priv, true);
  2337. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_ENABLE);
  2338. wcd938x_wakeup(wcd938x_priv, false);
  2339. break;
  2340. case SND_SOC_DAPM_POST_PMD:
  2341. wcd938x_wakeup(wcd938x_priv, true);
  2342. wcd938x_enable_micbias(wcd938x_priv, micb_num, MICB_PULLUP_DISABLE);
  2343. wcd938x_wakeup(wcd938x_priv, false);
  2344. break;
  2345. }
  2346. done:
  2347. return ret;
  2348. }
  2349. EXPORT_SYMBOL(wcd938x_codec_force_enable_micbias_v2);
  2350. static inline int wcd938x_tx_path_get(const char *wname,
  2351. unsigned int *path_num)
  2352. {
  2353. int ret = 0;
  2354. char *widget_name = NULL;
  2355. char *w_name = NULL;
  2356. char *path_num_char = NULL;
  2357. char *path_name = NULL;
  2358. widget_name = kstrndup(wname, 9, GFP_KERNEL);
  2359. if (!widget_name)
  2360. return -EINVAL;
  2361. w_name = widget_name;
  2362. path_name = strsep(&widget_name, " ");
  2363. if (!path_name) {
  2364. pr_err_ratelimited("%s: Invalid widget name = %s\n",
  2365. __func__, widget_name);
  2366. ret = -EINVAL;
  2367. goto err;
  2368. }
  2369. path_num_char = strpbrk(path_name, "0123");
  2370. if (!path_num_char) {
  2371. pr_err_ratelimited("%s: tx path index not found\n",
  2372. __func__);
  2373. ret = -EINVAL;
  2374. goto err;
  2375. }
  2376. ret = kstrtouint(path_num_char, 10, path_num);
  2377. if (ret < 0)
  2378. pr_err_ratelimited("%s: Invalid tx path = %s\n",
  2379. __func__, w_name);
  2380. err:
  2381. kfree(w_name);
  2382. return ret;
  2383. }
  2384. static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
  2385. struct snd_ctl_elem_value *ucontrol)
  2386. {
  2387. struct snd_soc_component *component =
  2388. snd_soc_kcontrol_component(kcontrol);
  2389. struct wcd938x_priv *wcd938x = NULL;
  2390. int ret = 0;
  2391. unsigned int path = 0;
  2392. if (!component)
  2393. return -EINVAL;
  2394. wcd938x = snd_soc_component_get_drvdata(component);
  2395. if (!wcd938x)
  2396. return -EINVAL;
  2397. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2398. if (ret < 0)
  2399. return ret;
  2400. ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
  2401. return 0;
  2402. }
  2403. static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
  2404. struct snd_ctl_elem_value *ucontrol)
  2405. {
  2406. struct snd_soc_component *component =
  2407. snd_soc_kcontrol_component(kcontrol);
  2408. struct wcd938x_priv *wcd938x = NULL;
  2409. u32 mode_val;
  2410. unsigned int path = 0;
  2411. int ret = 0;
  2412. if (!component)
  2413. return -EINVAL;
  2414. wcd938x = snd_soc_component_get_drvdata(component);
  2415. if (!wcd938x)
  2416. return -EINVAL;
  2417. ret = wcd938x_tx_path_get(kcontrol->id.name, &path);
  2418. if (ret)
  2419. return ret;
  2420. mode_val = ucontrol->value.enumerated.item[0];
  2421. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2422. wcd938x->tx_mode[path] = mode_val;
  2423. return 0;
  2424. }
  2425. static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
  2426. struct snd_ctl_elem_value *ucontrol)
  2427. {
  2428. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2429. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2430. ucontrol->value.integer.value[0] = wcd938x->hph_mode;
  2431. return 0;
  2432. }
  2433. static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
  2434. struct snd_ctl_elem_value *ucontrol)
  2435. {
  2436. struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
  2437. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2438. u32 mode_val;
  2439. mode_val = ucontrol->value.enumerated.item[0];
  2440. dev_dbg(component->dev, "%s: mode: %d\n", __func__, mode_val);
  2441. if (wcd938x->variant == WCD9380) {
  2442. if (mode_val == CLS_H_HIFI || mode_val == CLS_AB_HIFI) {
  2443. dev_info_ratelimited(component->dev,
  2444. "%s:Invalid HPH Mode, default to CLS_H_ULP\n",
  2445. __func__);
  2446. mode_val = CLS_H_ULP;
  2447. }
  2448. }
  2449. if (mode_val == CLS_H_NORMAL) {
  2450. dev_info_ratelimited(component->dev,
  2451. "%s:Invalid HPH Mode, default to class_AB\n",
  2452. __func__);
  2453. mode_val = CLS_H_ULP;
  2454. }
  2455. wcd938x->hph_mode = mode_val;
  2456. return 0;
  2457. }
  2458. static int wcd938x_ear_pa_gain_get(struct snd_kcontrol *kcontrol,
  2459. struct snd_ctl_elem_value *ucontrol)
  2460. {
  2461. u8 ear_pa_gain = 0;
  2462. struct snd_soc_component *component =
  2463. snd_soc_kcontrol_component(kcontrol);
  2464. ear_pa_gain = snd_soc_component_read(component,
  2465. WCD938X_ANA_EAR_COMPANDER_CTL);
  2466. ear_pa_gain = (ear_pa_gain & 0x7C) >> 2;
  2467. ucontrol->value.integer.value[0] = ear_pa_gain;
  2468. dev_dbg(component->dev, "%s: ear_pa_gain = 0x%x\n", __func__,
  2469. ear_pa_gain);
  2470. return 0;
  2471. }
  2472. static int wcd938x_ear_pa_gain_put(struct snd_kcontrol *kcontrol,
  2473. struct snd_ctl_elem_value *ucontrol)
  2474. {
  2475. u8 ear_pa_gain = 0;
  2476. struct snd_soc_component *component =
  2477. snd_soc_kcontrol_component(kcontrol);
  2478. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2479. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  2480. __func__, ucontrol->value.integer.value[0]);
  2481. ear_pa_gain = ucontrol->value.integer.value[0] << 2;
  2482. if (!wcd938x->comp1_enable) {
  2483. snd_soc_component_update_bits(component,
  2484. WCD938X_ANA_EAR_COMPANDER_CTL,
  2485. 0x7C, ear_pa_gain);
  2486. }
  2487. return 0;
  2488. }
  2489. /* wcd938x_codec_get_dev_num - returns swr device number
  2490. * @component: Codec instance
  2491. *
  2492. * Return: swr device number on success or negative error
  2493. * code on failure.
  2494. */
  2495. int wcd938x_codec_get_dev_num(struct snd_soc_component *component)
  2496. {
  2497. struct wcd938x_priv *wcd938x;
  2498. if (!component)
  2499. return -EINVAL;
  2500. wcd938x = snd_soc_component_get_drvdata(component);
  2501. if (!wcd938x || !wcd938x->rx_swr_dev) {
  2502. pr_err_ratelimited("%s: wcd938x component is NULL\n", __func__);
  2503. return -EINVAL;
  2504. }
  2505. return wcd938x->rx_swr_dev->dev_num;
  2506. }
  2507. EXPORT_SYMBOL(wcd938x_codec_get_dev_num);
  2508. static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
  2509. struct snd_ctl_elem_value *ucontrol)
  2510. {
  2511. struct snd_soc_component *component =
  2512. snd_soc_kcontrol_component(kcontrol);
  2513. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2514. bool hphr;
  2515. struct soc_multi_mixer_control *mc;
  2516. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2517. hphr = mc->shift;
  2518. ucontrol->value.integer.value[0] = hphr ? wcd938x->comp2_enable :
  2519. wcd938x->comp1_enable;
  2520. return 0;
  2521. }
  2522. static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
  2523. struct snd_ctl_elem_value *ucontrol)
  2524. {
  2525. struct snd_soc_component *component =
  2526. snd_soc_kcontrol_component(kcontrol);
  2527. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2528. int value = ucontrol->value.integer.value[0];
  2529. bool hphr;
  2530. struct soc_multi_mixer_control *mc;
  2531. mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
  2532. hphr = mc->shift;
  2533. if (hphr)
  2534. wcd938x->comp2_enable = value;
  2535. else
  2536. wcd938x->comp1_enable = value;
  2537. return 0;
  2538. }
  2539. static int wcd938x_codec_enable_vdd_buck(struct snd_soc_dapm_widget *w,
  2540. struct snd_kcontrol *kcontrol,
  2541. int event)
  2542. {
  2543. struct snd_soc_component *component =
  2544. snd_soc_dapm_to_component(w->dapm);
  2545. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2546. struct wcd938x_pdata *pdata = NULL;
  2547. int ret = 0;
  2548. pdata = dev_get_platdata(wcd938x->dev);
  2549. if (!pdata) {
  2550. dev_err_ratelimited(component->dev, "%s: pdata is NULL\n", __func__);
  2551. return -EINVAL;
  2552. }
  2553. if (!msm_cdc_is_ondemand_supply(wcd938x->dev,
  2554. wcd938x->supplies,
  2555. pdata->regulator,
  2556. pdata->num_supplies,
  2557. "cdc-vdd-buck"))
  2558. return 0;
  2559. dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
  2560. w->name, event);
  2561. switch (event) {
  2562. case SND_SOC_DAPM_PRE_PMU:
  2563. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  2564. dev_dbg(component->dev,
  2565. "%s: buck already in enabled state\n",
  2566. __func__);
  2567. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2568. return 0;
  2569. }
  2570. ret = msm_cdc_enable_ondemand_supply(wcd938x->dev,
  2571. wcd938x->supplies,
  2572. pdata->regulator,
  2573. pdata->num_supplies,
  2574. "cdc-vdd-buck");
  2575. if (ret == -EINVAL) {
  2576. dev_err_ratelimited(component->dev, "%s: vdd buck is not enabled\n",
  2577. __func__);
  2578. return ret;
  2579. }
  2580. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2581. /*
  2582. * 200us sleep is required after LDO is enabled as per
  2583. * HW requirement
  2584. */
  2585. usleep_range(200, 250);
  2586. break;
  2587. case SND_SOC_DAPM_POST_PMD:
  2588. set_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  2589. break;
  2590. }
  2591. return 0;
  2592. }
  2593. static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
  2594. struct snd_ctl_elem_value *ucontrol)
  2595. {
  2596. struct snd_soc_component *component =
  2597. snd_soc_kcontrol_component(kcontrol);
  2598. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2599. ucontrol->value.integer.value[0] = wcd938x->ldoh;
  2600. return 0;
  2601. }
  2602. static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
  2603. struct snd_ctl_elem_value *ucontrol)
  2604. {
  2605. struct snd_soc_component *component =
  2606. snd_soc_kcontrol_component(kcontrol);
  2607. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2608. wcd938x->ldoh = ucontrol->value.integer.value[0];
  2609. return 0;
  2610. }
  2611. const char * const tx_master_ch_text[] = {
  2612. "ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
  2613. "SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
  2614. "SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
  2615. "SWRM_TX3_CH4", "SWRM_PCM_IN",
  2616. };
  2617. const struct soc_enum tx_master_ch_enum =
  2618. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_ch_text),
  2619. tx_master_ch_text);
  2620. static void wcd938x_tx_get_slave_ch_type_idx(const char *wname, int *ch_idx)
  2621. {
  2622. u8 ch_type = 0;
  2623. if (strnstr(wname, "ADC1", sizeof("ADC1")))
  2624. ch_type = ADC1;
  2625. else if (strnstr(wname, "ADC2", sizeof("ADC2")))
  2626. ch_type = ADC2;
  2627. else if (strnstr(wname, "ADC3", sizeof("ADC3")))
  2628. ch_type = ADC3;
  2629. else if (strnstr(wname, "ADC4", sizeof("ADC4")))
  2630. ch_type = ADC4;
  2631. else if (strnstr(wname, "DMIC0", sizeof("DMIC0")))
  2632. ch_type = DMIC0;
  2633. else if (strnstr(wname, "DMIC1", sizeof("DMIC1")))
  2634. ch_type = DMIC1;
  2635. else if (strnstr(wname, "MBHC", sizeof("MBHC")))
  2636. ch_type = MBHC;
  2637. else if (strnstr(wname, "DMIC2", sizeof("DMIC2")))
  2638. ch_type = DMIC2;
  2639. else if (strnstr(wname, "DMIC3", sizeof("DMIC3")))
  2640. ch_type = DMIC3;
  2641. else if (strnstr(wname, "DMIC4", sizeof("DMIC4")))
  2642. ch_type = DMIC4;
  2643. else if (strnstr(wname, "DMIC5", sizeof("DMIC5")))
  2644. ch_type = DMIC5;
  2645. else if (strnstr(wname, "DMIC6", sizeof("DMIC6")))
  2646. ch_type = DMIC6;
  2647. else if (strnstr(wname, "DMIC7", sizeof("DMIC7")))
  2648. ch_type = DMIC7;
  2649. else
  2650. pr_err_ratelimited("%s: port name: %s is not listed\n", __func__, wname);
  2651. if (ch_type)
  2652. *ch_idx = wcd938x_slave_get_slave_ch_val(ch_type);
  2653. else
  2654. *ch_idx = -EINVAL;
  2655. }
  2656. static int wcd938x_tx_master_ch_get(struct snd_kcontrol *kcontrol,
  2657. struct snd_ctl_elem_value *ucontrol)
  2658. {
  2659. struct snd_soc_component *component =
  2660. snd_soc_kcontrol_component(kcontrol);
  2661. struct wcd938x_priv *wcd938x = NULL;
  2662. int slave_ch_idx = -EINVAL;
  2663. if (component == NULL)
  2664. return -EINVAL;
  2665. wcd938x = snd_soc_component_get_drvdata(component);
  2666. if (wcd938x == NULL)
  2667. return -EINVAL;
  2668. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2669. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2670. return -EINVAL;
  2671. ucontrol->value.integer.value[0] = wcd938x_slave_get_master_ch_val(
  2672. wcd938x->tx_master_ch_map[slave_ch_idx]);
  2673. return 0;
  2674. }
  2675. static int wcd938x_tx_master_ch_put(struct snd_kcontrol *kcontrol,
  2676. struct snd_ctl_elem_value *ucontrol)
  2677. {
  2678. struct snd_soc_component *component =
  2679. snd_soc_kcontrol_component(kcontrol);
  2680. struct wcd938x_priv *wcd938x = NULL;
  2681. int slave_ch_idx = -EINVAL, idx = 0;
  2682. if (component == NULL)
  2683. return -EINVAL;
  2684. wcd938x = snd_soc_component_get_drvdata(component);
  2685. if (wcd938x == NULL)
  2686. return -EINVAL;
  2687. wcd938x_tx_get_slave_ch_type_idx(kcontrol->id.name, &slave_ch_idx);
  2688. if (slave_ch_idx < 0 || slave_ch_idx >= WCD938X_MAX_SLAVE_CH_TYPES)
  2689. return -EINVAL;
  2690. dev_dbg(component->dev, "%s: slave_ch_idx: %d", __func__, slave_ch_idx);
  2691. dev_dbg(component->dev, "%s: ucontrol->value.enumerated.item[0] = %ld\n",
  2692. __func__, ucontrol->value.enumerated.item[0]);
  2693. idx = ucontrol->value.enumerated.item[0];
  2694. if (idx < 0 || idx >= ARRAY_SIZE(swr_master_ch_map))
  2695. return -EINVAL;
  2696. wcd938x->tx_master_ch_map[slave_ch_idx] = wcd938x_slave_get_master_ch(idx);
  2697. return 0;
  2698. }
  2699. static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
  2700. struct snd_ctl_elem_value *ucontrol)
  2701. {
  2702. struct snd_soc_component *component =
  2703. snd_soc_kcontrol_component(kcontrol);
  2704. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2705. ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
  2706. return 0;
  2707. }
  2708. static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
  2709. struct snd_ctl_elem_value *ucontrol)
  2710. {
  2711. struct snd_soc_component *component =
  2712. snd_soc_kcontrol_component(kcontrol);
  2713. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  2714. wcd938x->bcs_dis = ucontrol->value.integer.value[0];
  2715. return 0;
  2716. }
  2717. static const char * const tx_mode_mux_text_wcd9380[] = {
  2718. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2719. };
  2720. static const struct soc_enum tx_mode_mux_enum_wcd9380 =
  2721. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text_wcd9380),
  2722. tx_mode_mux_text_wcd9380);
  2723. static const char * const tx_mode_mux_text[] = {
  2724. "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
  2725. "ADC_ULP1", "ADC_ULP2",
  2726. };
  2727. static const struct soc_enum tx_mode_mux_enum =
  2728. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_mode_mux_text),
  2729. tx_mode_mux_text);
  2730. static const char * const rx_hph_mode_mux_text_wcd9380[] = {
  2731. "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
  2732. "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
  2733. "CLS_AB_LOHIFI",
  2734. };
  2735. static const char * const wcd938x_ear_pa_gain_text[] = {
  2736. "G_6_DB", "G_4P5_DB", "G_3_DB", "G_1P5_DB", "G_0_DB",
  2737. "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB",
  2738. "G_M6_DB", "G_7P5_DB", "G_M9_DB",
  2739. "G_M10P5_DB", "G_M12_DB", "G_M13P5_DB",
  2740. "G_M15_DB", "G_M16P5_DB", "G_M18_DB",
  2741. };
  2742. static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
  2743. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
  2744. rx_hph_mode_mux_text_wcd9380);
  2745. static SOC_ENUM_SINGLE_EXT_DECL(wcd938x_ear_pa_gain_enum,
  2746. wcd938x_ear_pa_gain_text);
  2747. static const char * const rx_hph_mode_mux_text[] = {
  2748. "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
  2749. "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
  2750. };
  2751. static const struct soc_enum rx_hph_mode_mux_enum =
  2752. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
  2753. rx_hph_mode_mux_text);
  2754. static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
  2755. SOC_ENUM_EXT("EAR PA GAIN", wcd938x_ear_pa_gain_enum,
  2756. wcd938x_ear_pa_gain_get, wcd938x_ear_pa_gain_put),
  2757. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
  2758. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2759. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum_wcd9380,
  2760. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2761. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum_wcd9380,
  2762. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2763. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum_wcd9380,
  2764. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2765. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum_wcd9380,
  2766. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2767. };
  2768. static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
  2769. SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
  2770. wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
  2771. SOC_ENUM_EXT("TX0 MODE", tx_mode_mux_enum,
  2772. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2773. SOC_ENUM_EXT("TX1 MODE", tx_mode_mux_enum,
  2774. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2775. SOC_ENUM_EXT("TX2 MODE", tx_mode_mux_enum,
  2776. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2777. SOC_ENUM_EXT("TX3 MODE", tx_mode_mux_enum,
  2778. wcd938x_tx_mode_get, wcd938x_tx_mode_put),
  2779. };
  2780. static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
  2781. SOC_SINGLE_EXT("HPHL_COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  2782. wcd938x_get_compander, wcd938x_set_compander),
  2783. SOC_SINGLE_EXT("HPHR_COMP Switch", SND_SOC_NOPM, 1, 1, 0,
  2784. wcd938x_get_compander, wcd938x_set_compander),
  2785. SOC_SINGLE_EXT("LDOH Enable", SND_SOC_NOPM, 0, 1, 0,
  2786. wcd938x_ldoh_get, wcd938x_ldoh_put),
  2787. SOC_SINGLE_EXT("ADC2_BCS Disable", SND_SOC_NOPM, 0, 1, 0,
  2788. wcd938x_bcs_get, wcd938x_bcs_put),
  2789. SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 20, 1, line_gain),
  2790. SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 20, 1, line_gain),
  2791. SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0,
  2792. analog_gain),
  2793. SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0,
  2794. analog_gain),
  2795. SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0,
  2796. analog_gain),
  2797. SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0,
  2798. analog_gain),
  2799. SOC_ENUM_EXT("ADC1 ChMap", tx_master_ch_enum,
  2800. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2801. SOC_ENUM_EXT("ADC2 ChMap", tx_master_ch_enum,
  2802. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2803. SOC_ENUM_EXT("ADC3 ChMap", tx_master_ch_enum,
  2804. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2805. SOC_ENUM_EXT("ADC4 ChMap", tx_master_ch_enum,
  2806. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2807. SOC_ENUM_EXT("DMIC0 ChMap", tx_master_ch_enum,
  2808. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2809. SOC_ENUM_EXT("DMIC1 ChMap", tx_master_ch_enum,
  2810. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2811. SOC_ENUM_EXT("MBHC ChMap", tx_master_ch_enum,
  2812. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2813. SOC_ENUM_EXT("DMIC2 ChMap", tx_master_ch_enum,
  2814. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2815. SOC_ENUM_EXT("DMIC3 ChMap", tx_master_ch_enum,
  2816. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2817. SOC_ENUM_EXT("DMIC4 ChMap", tx_master_ch_enum,
  2818. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2819. SOC_ENUM_EXT("DMIC5 ChMap", tx_master_ch_enum,
  2820. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2821. SOC_ENUM_EXT("DMIC6 ChMap", tx_master_ch_enum,
  2822. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2823. SOC_ENUM_EXT("DMIC7 ChMap", tx_master_ch_enum,
  2824. wcd938x_tx_master_ch_get, wcd938x_tx_master_ch_put),
  2825. };
  2826. static const struct snd_kcontrol_new adc1_switch[] = {
  2827. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2828. };
  2829. static const struct snd_kcontrol_new adc2_switch[] = {
  2830. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2831. };
  2832. static const struct snd_kcontrol_new adc3_switch[] = {
  2833. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2834. };
  2835. static const struct snd_kcontrol_new adc4_switch[] = {
  2836. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2837. };
  2838. static const struct snd_kcontrol_new amic1_switch[] = {
  2839. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2840. };
  2841. static const struct snd_kcontrol_new amic2_switch[] = {
  2842. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2843. };
  2844. static const struct snd_kcontrol_new amic3_switch[] = {
  2845. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2846. };
  2847. static const struct snd_kcontrol_new amic4_switch[] = {
  2848. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2849. };
  2850. static const struct snd_kcontrol_new amic5_switch[] = {
  2851. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2852. };
  2853. static const struct snd_kcontrol_new amic6_switch[] = {
  2854. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2855. };
  2856. static const struct snd_kcontrol_new amic7_switch[] = {
  2857. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2858. };
  2859. static const struct snd_kcontrol_new va_amic1_switch[] = {
  2860. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2861. };
  2862. static const struct snd_kcontrol_new va_amic2_switch[] = {
  2863. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2864. };
  2865. static const struct snd_kcontrol_new va_amic3_switch[] = {
  2866. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2867. };
  2868. static const struct snd_kcontrol_new va_amic4_switch[] = {
  2869. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2870. };
  2871. static const struct snd_kcontrol_new va_amic5_switch[] = {
  2872. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2873. };
  2874. static const struct snd_kcontrol_new va_amic6_switch[] = {
  2875. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2876. };
  2877. static const struct snd_kcontrol_new va_amic7_switch[] = {
  2878. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2879. };
  2880. static const struct snd_kcontrol_new dmic1_switch[] = {
  2881. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2882. };
  2883. static const struct snd_kcontrol_new dmic2_switch[] = {
  2884. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2885. };
  2886. static const struct snd_kcontrol_new dmic3_switch[] = {
  2887. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2888. };
  2889. static const struct snd_kcontrol_new dmic4_switch[] = {
  2890. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2891. };
  2892. static const struct snd_kcontrol_new dmic5_switch[] = {
  2893. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2894. };
  2895. static const struct snd_kcontrol_new dmic6_switch[] = {
  2896. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2897. };
  2898. static const struct snd_kcontrol_new dmic7_switch[] = {
  2899. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2900. };
  2901. static const struct snd_kcontrol_new dmic8_switch[] = {
  2902. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2903. };
  2904. static const struct snd_kcontrol_new ear_rdac_switch[] = {
  2905. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2906. };
  2907. static const struct snd_kcontrol_new aux_rdac_switch[] = {
  2908. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2909. };
  2910. static const struct snd_kcontrol_new hphl_rdac_switch[] = {
  2911. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2912. };
  2913. static const struct snd_kcontrol_new hphr_rdac_switch[] = {
  2914. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  2915. };
  2916. static const char * const adc2_mux_text[] = {
  2917. "INP2", "INP3"
  2918. };
  2919. static const struct soc_enum adc2_enum =
  2920. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
  2921. ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
  2922. static const struct snd_kcontrol_new tx_adc2_mux =
  2923. SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
  2924. static const char * const adc3_mux_text[] = {
  2925. "INP4", "INP6"
  2926. };
  2927. static const struct soc_enum adc3_enum =
  2928. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
  2929. ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
  2930. static const struct snd_kcontrol_new tx_adc3_mux =
  2931. SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
  2932. static const char * const adc4_mux_text[] = {
  2933. "INP5", "INP7"
  2934. };
  2935. static const struct soc_enum adc4_enum =
  2936. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
  2937. ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
  2938. static const struct snd_kcontrol_new tx_adc4_mux =
  2939. SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
  2940. static const char * const rdac3_mux_text[] = {
  2941. "RX1", "RX3"
  2942. };
  2943. static const char * const hdr12_mux_text[] = {
  2944. "NO_HDR12", "HDR12"
  2945. };
  2946. static const struct soc_enum hdr12_enum =
  2947. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
  2948. ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
  2949. static const struct snd_kcontrol_new tx_hdr12_mux =
  2950. SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
  2951. static const char * const hdr34_mux_text[] = {
  2952. "NO_HDR34", "HDR34"
  2953. };
  2954. static const struct soc_enum hdr34_enum =
  2955. SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
  2956. ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
  2957. static const struct snd_kcontrol_new tx_hdr34_mux =
  2958. SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
  2959. static const struct soc_enum rdac3_enum =
  2960. SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
  2961. ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
  2962. static const struct snd_kcontrol_new rx_rdac3_mux =
  2963. SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
  2964. static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
  2965. /*input widgets*/
  2966. SND_SOC_DAPM_INPUT("AMIC1"),
  2967. SND_SOC_DAPM_INPUT("AMIC2"),
  2968. SND_SOC_DAPM_INPUT("AMIC3"),
  2969. SND_SOC_DAPM_INPUT("AMIC4"),
  2970. SND_SOC_DAPM_INPUT("AMIC5"),
  2971. SND_SOC_DAPM_INPUT("AMIC6"),
  2972. SND_SOC_DAPM_INPUT("AMIC7"),
  2973. SND_SOC_DAPM_INPUT("VA AMIC1"),
  2974. SND_SOC_DAPM_INPUT("VA AMIC2"),
  2975. SND_SOC_DAPM_INPUT("VA AMIC3"),
  2976. SND_SOC_DAPM_INPUT("VA AMIC4"),
  2977. SND_SOC_DAPM_INPUT("VA AMIC5"),
  2978. SND_SOC_DAPM_INPUT("VA AMIC6"),
  2979. SND_SOC_DAPM_INPUT("VA AMIC7"),
  2980. SND_SOC_DAPM_INPUT("IN1_HPHL"),
  2981. SND_SOC_DAPM_INPUT("IN2_HPHR"),
  2982. SND_SOC_DAPM_INPUT("IN3_AUX"),
  2983. /*
  2984. * These dummy widgets are null connected to WCD938x dapm input and
  2985. * output widgets which are not actual path endpoints. This ensures
  2986. * dapm doesnt set these dapm input and output widgets as endpoints.
  2987. */
  2988. SND_SOC_DAPM_INPUT("WCD_TX_DUMMY"),
  2989. SND_SOC_DAPM_OUTPUT("WCD_RX_DUMMY"),
  2990. /*tx widgets*/
  2991. SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
  2992. wcd938x_codec_enable_adc,
  2993. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2994. SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
  2995. wcd938x_codec_enable_adc,
  2996. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  2997. SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
  2998. wcd938x_codec_enable_adc,
  2999. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3000. SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
  3001. wcd938x_codec_enable_adc,
  3002. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3003. SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
  3004. wcd938x_codec_enable_dmic,
  3005. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3006. SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
  3007. wcd938x_codec_enable_dmic,
  3008. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3009. SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
  3010. wcd938x_codec_enable_dmic,
  3011. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3012. SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
  3013. wcd938x_codec_enable_dmic,
  3014. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3015. SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
  3016. wcd938x_codec_enable_dmic,
  3017. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3018. SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
  3019. wcd938x_codec_enable_dmic,
  3020. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3021. SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
  3022. wcd938x_codec_enable_dmic,
  3023. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3024. SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
  3025. wcd938x_codec_enable_dmic,
  3026. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3027. SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
  3028. NULL, 0, wcd938x_enable_req,
  3029. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3030. SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
  3031. NULL, 0, wcd938x_enable_req,
  3032. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3033. SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
  3034. NULL, 0, wcd938x_enable_req,
  3035. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3036. SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0,
  3037. NULL, 0, wcd938x_enable_req,
  3038. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3039. SND_SOC_DAPM_MIXER_E("AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3040. amic1_switch, ARRAY_SIZE(amic1_switch), NULL,
  3041. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3042. SND_SOC_DAPM_MIXER_E("AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3043. amic2_switch, ARRAY_SIZE(amic2_switch), NULL,
  3044. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3045. SND_SOC_DAPM_MIXER_E("AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3046. amic3_switch, ARRAY_SIZE(amic3_switch), NULL,
  3047. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3048. SND_SOC_DAPM_MIXER_E("AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3049. amic4_switch, ARRAY_SIZE(amic4_switch), NULL,
  3050. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3051. SND_SOC_DAPM_MIXER_E("AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3052. amic5_switch, ARRAY_SIZE(amic5_switch), NULL,
  3053. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3054. SND_SOC_DAPM_MIXER_E("AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3055. amic6_switch, ARRAY_SIZE(amic6_switch), NULL,
  3056. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3057. SND_SOC_DAPM_MIXER_E("AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3058. amic7_switch, ARRAY_SIZE(amic7_switch), NULL,
  3059. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3060. SND_SOC_DAPM_MIXER_E("VA_AMIC1_MIXER", SND_SOC_NOPM, 0, 0,
  3061. va_amic1_switch, ARRAY_SIZE(va_amic1_switch), NULL,
  3062. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3063. SND_SOC_DAPM_MIXER_E("VA_AMIC2_MIXER", SND_SOC_NOPM, 0, 0,
  3064. va_amic2_switch, ARRAY_SIZE(va_amic2_switch), NULL,
  3065. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3066. SND_SOC_DAPM_MIXER_E("VA_AMIC3_MIXER", SND_SOC_NOPM, 0, 0,
  3067. va_amic3_switch, ARRAY_SIZE(va_amic3_switch), NULL,
  3068. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3069. SND_SOC_DAPM_MIXER_E("VA_AMIC4_MIXER", SND_SOC_NOPM, 0, 0,
  3070. va_amic4_switch, ARRAY_SIZE(va_amic4_switch), NULL,
  3071. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3072. SND_SOC_DAPM_MIXER_E("VA_AMIC5_MIXER", SND_SOC_NOPM, 0, 0,
  3073. va_amic5_switch, ARRAY_SIZE(va_amic5_switch), NULL,
  3074. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3075. SND_SOC_DAPM_MIXER_E("VA_AMIC6_MIXER", SND_SOC_NOPM, 0, 0,
  3076. va_amic6_switch, ARRAY_SIZE(va_amic6_switch), NULL,
  3077. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3078. SND_SOC_DAPM_MIXER_E("VA_AMIC7_MIXER", SND_SOC_NOPM, 0, 0,
  3079. va_amic7_switch, ARRAY_SIZE(va_amic7_switch), NULL,
  3080. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3081. SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
  3082. &tx_adc2_mux),
  3083. SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0,
  3084. &tx_adc3_mux),
  3085. SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0,
  3086. &tx_adc4_mux),
  3087. SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0,
  3088. &tx_hdr12_mux),
  3089. SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0,
  3090. &tx_hdr34_mux),
  3091. /*tx mixers*/
  3092. SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, ADC1, 0,
  3093. adc1_switch, ARRAY_SIZE(adc1_switch),
  3094. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3095. SND_SOC_DAPM_POST_PMD),
  3096. SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, ADC2, 0,
  3097. adc2_switch, ARRAY_SIZE(adc2_switch),
  3098. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3099. SND_SOC_DAPM_POST_PMD),
  3100. SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, ADC3, 0, adc3_switch,
  3101. ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
  3102. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3103. SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, ADC4, 0, adc4_switch,
  3104. ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
  3105. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3106. SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, DMIC1,
  3107. 0, dmic1_switch, ARRAY_SIZE(dmic1_switch),
  3108. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3109. SND_SOC_DAPM_POST_PMD),
  3110. SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, DMIC2,
  3111. 0, dmic2_switch, ARRAY_SIZE(dmic2_switch),
  3112. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3113. SND_SOC_DAPM_POST_PMD),
  3114. SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, DMIC3,
  3115. 0, dmic3_switch, ARRAY_SIZE(dmic3_switch),
  3116. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3117. SND_SOC_DAPM_POST_PMD),
  3118. SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, DMIC4,
  3119. 0, dmic4_switch, ARRAY_SIZE(dmic4_switch),
  3120. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3121. SND_SOC_DAPM_POST_PMD),
  3122. SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, DMIC5,
  3123. 0, dmic5_switch, ARRAY_SIZE(dmic5_switch),
  3124. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3125. SND_SOC_DAPM_POST_PMD),
  3126. SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, DMIC6,
  3127. 0, dmic6_switch, ARRAY_SIZE(dmic6_switch),
  3128. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3129. SND_SOC_DAPM_POST_PMD),
  3130. SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, DMIC7,
  3131. 0, dmic7_switch, ARRAY_SIZE(dmic7_switch),
  3132. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3133. SND_SOC_DAPM_POST_PMD),
  3134. SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, DMIC8,
  3135. 0, dmic8_switch, ARRAY_SIZE(dmic8_switch),
  3136. wcd938x_tx_swr_ctrl, SND_SOC_DAPM_PRE_PMU |
  3137. SND_SOC_DAPM_POST_PMD),
  3138. /* micbias widgets*/
  3139. SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3140. wcd938x_codec_enable_micbias,
  3141. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3142. SND_SOC_DAPM_POST_PMD),
  3143. SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3144. wcd938x_codec_enable_micbias,
  3145. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3146. SND_SOC_DAPM_POST_PMD),
  3147. SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3148. wcd938x_codec_enable_micbias,
  3149. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3150. SND_SOC_DAPM_POST_PMD),
  3151. SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3152. wcd938x_codec_enable_micbias,
  3153. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3154. SND_SOC_DAPM_POST_PMD),
  3155. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0,
  3156. wcd938x_codec_force_enable_micbias,
  3157. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3158. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS2_STANDALONE, SND_SOC_NOPM, 0, 0,
  3159. wcd938x_codec_force_enable_micbias,
  3160. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3161. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS3_STANDALONE, SND_SOC_NOPM, 0, 0,
  3162. wcd938x_codec_force_enable_micbias,
  3163. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3164. SND_SOC_DAPM_SUPPLY(DAPM_MICBIAS4_STANDALONE, SND_SOC_NOPM, 0, 0,
  3165. wcd938x_codec_force_enable_micbias,
  3166. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3167. SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0,
  3168. wcd938x_codec_enable_vdd_buck,
  3169. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3170. SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0,
  3171. wcd938x_enable_clsh,
  3172. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  3173. /*rx widgets*/
  3174. SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
  3175. wcd938x_codec_enable_ear_pa,
  3176. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3177. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3178. SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
  3179. wcd938x_codec_enable_aux_pa,
  3180. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3181. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3182. SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
  3183. wcd938x_codec_enable_hphl_pa,
  3184. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3185. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3186. SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
  3187. wcd938x_codec_enable_hphr_pa,
  3188. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3189. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3190. SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
  3191. wcd938x_codec_hphl_dac_event,
  3192. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3193. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3194. SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
  3195. wcd938x_codec_hphr_dac_event,
  3196. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3197. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3198. SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
  3199. wcd938x_codec_ear_dac_event,
  3200. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3201. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3202. SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
  3203. wcd938x_codec_aux_dac_event,
  3204. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3205. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  3206. SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
  3207. SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0,
  3208. wcd938x_enable_rx1, SND_SOC_DAPM_PRE_PMU |
  3209. SND_SOC_DAPM_POST_PMD),
  3210. SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0,
  3211. wcd938x_enable_rx2, SND_SOC_DAPM_PRE_PMU |
  3212. SND_SOC_DAPM_POST_PMD),
  3213. SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0,
  3214. wcd938x_enable_rx3, SND_SOC_DAPM_PRE_PMU |
  3215. SND_SOC_DAPM_POST_PMD),
  3216. /* rx mixer widgets*/
  3217. SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
  3218. ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
  3219. SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
  3220. aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
  3221. SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
  3222. hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
  3223. SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
  3224. hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
  3225. /*output widgets tx*/
  3226. SND_SOC_DAPM_OUTPUT("WCD_TX_OUTPUT"),
  3227. /*output widgets rx*/
  3228. SND_SOC_DAPM_OUTPUT("EAR"),
  3229. SND_SOC_DAPM_OUTPUT("AUX"),
  3230. SND_SOC_DAPM_OUTPUT("HPHL"),
  3231. SND_SOC_DAPM_OUTPUT("HPHR"),
  3232. /* micbias pull up widgets*/
  3233. SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, 0, 0,
  3234. wcd938x_codec_enable_micbias_pullup,
  3235. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3236. SND_SOC_DAPM_POST_PMD),
  3237. SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, 0, 0,
  3238. wcd938x_codec_enable_micbias_pullup,
  3239. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3240. SND_SOC_DAPM_POST_PMD),
  3241. SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, 0, 0,
  3242. wcd938x_codec_enable_micbias_pullup,
  3243. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3244. SND_SOC_DAPM_POST_PMD),
  3245. SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, 0, 0,
  3246. wcd938x_codec_enable_micbias_pullup,
  3247. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  3248. SND_SOC_DAPM_POST_PMD),
  3249. };
  3250. static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
  3251. {"WCD_TX_DUMMY", NULL, "WCD_TX_OUTPUT"},
  3252. {"WCD_TX_OUTPUT", NULL, "ADC1_MIXER"},
  3253. {"ADC1_MIXER", "Switch", "ADC1 REQ"},
  3254. {"ADC1 REQ", NULL, "ADC1"},
  3255. {"ADC1", NULL, "AMIC1_MIXER"},
  3256. {"AMIC1_MIXER", "Switch", "AMIC1"},
  3257. {"AMIC1_MIXER", NULL, "VA_AMIC1_MIXER"},
  3258. {"VA_AMIC1_MIXER", "Switch", "VA AMIC1"},
  3259. {"WCD_TX_OUTPUT", NULL, "ADC2_MIXER"},
  3260. {"ADC2_MIXER", "Switch", "ADC2 REQ"},
  3261. {"ADC2 REQ", NULL, "ADC2"},
  3262. {"ADC2", NULL, "HDR12 MUX"},
  3263. {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
  3264. {"HDR12 MUX", "HDR12", "AMIC1_MIXER"},
  3265. {"ADC2 MUX", "INP3", "AMIC3_MIXER"},
  3266. {"AMIC3_MIXER", "Switch", "AMIC3"},
  3267. {"AMIC3_MIXER", NULL, "VA_AMIC3_MIXER"},
  3268. {"VA_AMIC3_MIXER", "Switch", "VA AMIC3"},
  3269. {"ADC2 MUX", "INP2", "AMIC2_MIXER"},
  3270. {"AMIC2_MIXER", "Switch", "AMIC2"},
  3271. {"AMIC2_MIXER", NULL, "VA_AMIC2_MIXER"},
  3272. {"VA_AMIC2_MIXER", "Switch", "VA AMIC2"},
  3273. {"WCD_TX_OUTPUT", NULL, "ADC3_MIXER"},
  3274. {"ADC3_MIXER", "Switch", "ADC3 REQ"},
  3275. {"ADC3 REQ", NULL, "ADC3"},
  3276. {"ADC3", NULL, "HDR34 MUX"},
  3277. {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
  3278. {"HDR34 MUX", "HDR34", "AMIC5_MIXER"},
  3279. {"ADC3 MUX", "INP4", "AMIC4_MIXER"},
  3280. {"AMIC4_MIXER", "Switch", "AMIC4"},
  3281. {"AMIC4_MIXER", NULL, "VA_AMIC4_MIXER"},
  3282. {"VA_AMIC4_MIXER", "Switch", "VA AMIC4"},
  3283. {"ADC3 MUX", "INP6", "AMIC6_MIXER"},
  3284. {"AMIC6_MIXER", "Switch", "AMIC6"},
  3285. {"AMIC6_MIXER", NULL, "VA_AMIC6_MIXER"},
  3286. {"VA_AMIC6_MIXER", "Switch", "VA AMIC6"},
  3287. {"WCD_TX_OUTPUT", NULL, "ADC4_MIXER"},
  3288. {"ADC4_MIXER", "Switch", "ADC4 REQ"},
  3289. {"ADC4 REQ", NULL, "ADC4"},
  3290. {"ADC4", NULL, "ADC4 MUX"},
  3291. {"ADC4 MUX", "INP5", "AMIC5_MIXER"},
  3292. {"AMIC5_MIXER", "Switch", "AMIC5"},
  3293. {"AMIC5_MIXER", NULL, "VA_AMIC5_MIXER"},
  3294. {"VA_AMIC5_MIXER", "Switch", "VA AMIC5"},
  3295. {"ADC4 MUX", "INP7", "AMIC7_MIXER"},
  3296. {"AMIC7_MIXER", "Switch", "AMIC7"},
  3297. {"AMIC7_MIXER", NULL, "VA_AMIC7_MIXER"},
  3298. {"VA_AMIC7_MIXER", "Switch", "VA AMIC7"},
  3299. {"WCD_TX_OUTPUT", NULL, "DMIC1_MIXER"},
  3300. {"DMIC1_MIXER", "Switch", "DMIC1"},
  3301. {"WCD_TX_OUTPUT", NULL, "DMIC2_MIXER"},
  3302. {"DMIC2_MIXER", "Switch", "DMIC2"},
  3303. {"WCD_TX_OUTPUT", NULL, "DMIC3_MIXER"},
  3304. {"DMIC3_MIXER", "Switch", "DMIC3"},
  3305. {"WCD_TX_OUTPUT", NULL, "DMIC4_MIXER"},
  3306. {"DMIC4_MIXER", "Switch", "DMIC4"},
  3307. {"WCD_TX_OUTPUT", NULL, "DMIC5_MIXER"},
  3308. {"DMIC5_MIXER", "Switch", "DMIC5"},
  3309. {"WCD_TX_OUTPUT", NULL, "DMIC6_MIXER"},
  3310. {"DMIC6_MIXER", "Switch", "DMIC6"},
  3311. {"WCD_TX_OUTPUT", NULL, "DMIC7_MIXER"},
  3312. {"DMIC7_MIXER", "Switch", "DMIC7"},
  3313. {"WCD_TX_OUTPUT", NULL, "DMIC8_MIXER"},
  3314. {"DMIC8_MIXER", "Switch", "DMIC8"},
  3315. {"IN1_HPHL", NULL, "WCD_RX_DUMMY"},
  3316. {"IN1_HPHL", NULL, "VDD_BUCK"},
  3317. {"IN1_HPHL", NULL, "CLS_H_PORT"},
  3318. {"RX1", NULL, "IN1_HPHL"},
  3319. {"RDAC1", NULL, "RX1"},
  3320. {"HPHL_RDAC", "Switch", "RDAC1"},
  3321. {"HPHL PGA", NULL, "HPHL_RDAC"},
  3322. {"HPHL", NULL, "HPHL PGA"},
  3323. {"IN2_HPHR", NULL, "WCD_RX_DUMMY"},
  3324. {"IN2_HPHR", NULL, "VDD_BUCK"},
  3325. {"IN2_HPHR", NULL, "CLS_H_PORT"},
  3326. {"RX2", NULL, "IN2_HPHR"},
  3327. {"RDAC2", NULL, "RX2"},
  3328. {"HPHR_RDAC", "Switch", "RDAC2"},
  3329. {"HPHR PGA", NULL, "HPHR_RDAC"},
  3330. {"HPHR", NULL, "HPHR PGA"},
  3331. {"IN3_AUX", NULL, "WCD_RX_DUMMY"},
  3332. {"IN3_AUX", NULL, "VDD_BUCK"},
  3333. {"IN3_AUX", NULL, "CLS_H_PORT"},
  3334. {"RX3", NULL, "IN3_AUX"},
  3335. {"RDAC4", NULL, "RX3"},
  3336. {"AUX_RDAC", "Switch", "RDAC4"},
  3337. {"AUX PGA", NULL, "AUX_RDAC"},
  3338. {"AUX", NULL, "AUX PGA"},
  3339. {"RDAC3_MUX", "RX3", "RX3"},
  3340. {"RDAC3_MUX", "RX1", "RX1"},
  3341. {"RDAC3", NULL, "RDAC3_MUX"},
  3342. {"EAR_RDAC", "Switch", "RDAC3"},
  3343. {"EAR PGA", NULL, "EAR_RDAC"},
  3344. {"EAR", NULL, "EAR PGA"},
  3345. };
  3346. static ssize_t wcd938x_version_read(struct snd_info_entry *entry,
  3347. void *file_private_data,
  3348. struct file *file,
  3349. char __user *buf, size_t count,
  3350. loff_t pos)
  3351. {
  3352. struct wcd938x_priv *priv;
  3353. char buffer[WCD938X_VERSION_ENTRY_SIZE];
  3354. int len = 0;
  3355. priv = (struct wcd938x_priv *) entry->private_data;
  3356. if (!priv) {
  3357. pr_err_ratelimited("%s: wcd938x priv is null\n", __func__);
  3358. return -EINVAL;
  3359. }
  3360. switch (priv->version) {
  3361. case WCD938X_VERSION_1_0:
  3362. len = snprintf(buffer, sizeof(buffer), "WCD938X_1_0\n");
  3363. break;
  3364. default:
  3365. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3366. }
  3367. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3368. }
  3369. static struct snd_info_entry_ops wcd938x_info_ops = {
  3370. .read = wcd938x_version_read,
  3371. };
  3372. static ssize_t wcd938x_variant_read(struct snd_info_entry *entry,
  3373. void *file_private_data,
  3374. struct file *file,
  3375. char __user *buf, size_t count,
  3376. loff_t pos)
  3377. {
  3378. struct wcd938x_priv *priv;
  3379. char buffer[WCD938X_VARIANT_ENTRY_SIZE];
  3380. int len = 0;
  3381. priv = (struct wcd938x_priv *) entry->private_data;
  3382. if (!priv) {
  3383. pr_err_ratelimited("%s: wcd938x priv is null\n", __func__);
  3384. return -EINVAL;
  3385. }
  3386. switch (priv->variant) {
  3387. case WCD9380:
  3388. len = snprintf(buffer, sizeof(buffer), "WCD9380\n");
  3389. break;
  3390. case WCD9385:
  3391. len = snprintf(buffer, sizeof(buffer), "WCD9385\n");
  3392. break;
  3393. default:
  3394. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  3395. }
  3396. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  3397. }
  3398. static struct snd_info_entry_ops wcd938x_variant_ops = {
  3399. .read = wcd938x_variant_read,
  3400. };
  3401. /*
  3402. * wcd938x_get_codec_variant
  3403. * @component: component instance
  3404. *
  3405. * Return: codec variant or -EINVAL in error.
  3406. */
  3407. int wcd938x_get_codec_variant(struct snd_soc_component *component)
  3408. {
  3409. struct wcd938x_priv *priv = NULL;
  3410. if (!component)
  3411. return -EINVAL;
  3412. priv = snd_soc_component_get_drvdata(component);
  3413. if (!priv) {
  3414. dev_err(component->dev,
  3415. "%s:wcd938x not probed\n", __func__);
  3416. return 0;
  3417. }
  3418. return priv->variant;
  3419. }
  3420. EXPORT_SYMBOL(wcd938x_get_codec_variant);
  3421. /*
  3422. * wcd938x_info_create_codec_entry - creates wcd938x module
  3423. * @codec_root: The parent directory
  3424. * @component: component instance
  3425. *
  3426. * Creates wcd938x module, variant and version entry under the given
  3427. * parent directory.
  3428. *
  3429. * Return: 0 on success or negative error code on failure.
  3430. */
  3431. int wcd938x_info_create_codec_entry(struct snd_info_entry *codec_root,
  3432. struct snd_soc_component *component)
  3433. {
  3434. struct snd_info_entry *version_entry;
  3435. struct snd_info_entry *variant_entry;
  3436. struct wcd938x_priv *priv;
  3437. struct snd_soc_card *card;
  3438. if (!codec_root || !component)
  3439. return -EINVAL;
  3440. priv = snd_soc_component_get_drvdata(component);
  3441. if (priv->entry) {
  3442. dev_dbg(priv->dev,
  3443. "%s:wcd938x module already created\n", __func__);
  3444. return 0;
  3445. }
  3446. card = component->card;
  3447. priv->entry = snd_info_create_module_entry(codec_root->module,
  3448. "wcd938x", codec_root);
  3449. if (!priv->entry) {
  3450. dev_dbg(component->dev, "%s: failed to create wcd938x entry\n",
  3451. __func__);
  3452. return -ENOMEM;
  3453. }
  3454. priv->entry->mode = S_IFDIR | 0555;
  3455. if (snd_info_register(priv->entry) < 0) {
  3456. snd_info_free_entry(priv->entry);
  3457. return -ENOMEM;
  3458. }
  3459. version_entry = snd_info_create_card_entry(card->snd_card,
  3460. "version",
  3461. priv->entry);
  3462. if (!version_entry) {
  3463. dev_dbg(component->dev, "%s: failed to create wcd938x version entry\n",
  3464. __func__);
  3465. snd_info_free_entry(priv->entry);
  3466. return -ENOMEM;
  3467. }
  3468. version_entry->private_data = priv;
  3469. version_entry->size = WCD938X_VERSION_ENTRY_SIZE;
  3470. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  3471. version_entry->c.ops = &wcd938x_info_ops;
  3472. if (snd_info_register(version_entry) < 0) {
  3473. snd_info_free_entry(version_entry);
  3474. snd_info_free_entry(priv->entry);
  3475. return -ENOMEM;
  3476. }
  3477. priv->version_entry = version_entry;
  3478. variant_entry = snd_info_create_card_entry(card->snd_card,
  3479. "variant",
  3480. priv->entry);
  3481. if (!variant_entry) {
  3482. dev_dbg(component->dev, "%s: failed to create wcd938x variant entry\n",
  3483. __func__);
  3484. snd_info_free_entry(version_entry);
  3485. snd_info_free_entry(priv->entry);
  3486. return -ENOMEM;
  3487. }
  3488. variant_entry->private_data = priv;
  3489. variant_entry->size = WCD938X_VARIANT_ENTRY_SIZE;
  3490. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  3491. variant_entry->c.ops = &wcd938x_variant_ops;
  3492. if (snd_info_register(variant_entry) < 0) {
  3493. snd_info_free_entry(variant_entry);
  3494. snd_info_free_entry(version_entry);
  3495. snd_info_free_entry(priv->entry);
  3496. return -ENOMEM;
  3497. }
  3498. priv->variant_entry = variant_entry;
  3499. return 0;
  3500. }
  3501. EXPORT_SYMBOL(wcd938x_info_create_codec_entry);
  3502. static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x,
  3503. struct wcd938x_pdata *pdata)
  3504. {
  3505. int vout_ctl_1 = 0, vout_ctl_2 = 0, vout_ctl_3 = 0, vout_ctl_4 = 0;
  3506. int rc = 0;
  3507. if (!pdata) {
  3508. dev_err(wcd938x->dev, "%s: NULL pdata\n", __func__);
  3509. return -ENODEV;
  3510. }
  3511. /* set micbias voltage */
  3512. vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb1_mv);
  3513. vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb2_mv);
  3514. vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb3_mv);
  3515. vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(pdata->micbias.micb4_mv);
  3516. if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 ||
  3517. vout_ctl_4 < 0) {
  3518. rc = -EINVAL;
  3519. goto done;
  3520. }
  3521. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1, 0x3F,
  3522. vout_ctl_1);
  3523. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2, 0x3F,
  3524. vout_ctl_2);
  3525. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3, 0x3F,
  3526. vout_ctl_3);
  3527. regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4, 0x3F,
  3528. vout_ctl_4);
  3529. done:
  3530. return rc;
  3531. }
  3532. static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
  3533. {
  3534. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3535. struct snd_soc_dapm_context *dapm =
  3536. snd_soc_component_get_dapm(component);
  3537. int variant;
  3538. int ret = -EINVAL;
  3539. dev_info(component->dev, "%s()\n", __func__);
  3540. wcd938x = snd_soc_component_get_drvdata(component);
  3541. if (!wcd938x)
  3542. return -EINVAL;
  3543. wcd938x->component = component;
  3544. snd_soc_component_init_regmap(component, wcd938x->regmap);
  3545. devm_regmap_qti_debugfs_register(&wcd938x->tx_swr_dev->dev, wcd938x->regmap);
  3546. variant = (snd_soc_component_read(component,
  3547. WCD938X_DIGITAL_EFUSE_REG_0) & 0x1E) >> 1;
  3548. wcd938x->variant = variant;
  3549. wcd938x->fw_data = devm_kzalloc(component->dev,
  3550. sizeof(*(wcd938x->fw_data)),
  3551. GFP_KERNEL);
  3552. if (!wcd938x->fw_data) {
  3553. dev_err(component->dev, "Failed to allocate fw_data\n");
  3554. ret = -ENOMEM;
  3555. goto err;
  3556. }
  3557. set_bit(WCD9XXX_MBHC_CAL, wcd938x->fw_data->cal_bit);
  3558. ret = wcd_cal_create_hwdep(wcd938x->fw_data,
  3559. WCD9XXX_CODEC_HWDEP_NODE, component);
  3560. if (ret < 0) {
  3561. dev_err(component->dev, "%s hwdep failed %d\n", __func__, ret);
  3562. goto err_hwdep;
  3563. }
  3564. ret = wcd938x_mbhc_init(&wcd938x->mbhc, component, wcd938x->fw_data);
  3565. if (ret) {
  3566. pr_err("%s: mbhc initialization failed\n", __func__);
  3567. goto err_hwdep;
  3568. }
  3569. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Playback");
  3570. snd_soc_dapm_ignore_suspend(dapm, "WCD938X_AIF Capture");
  3571. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  3572. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  3573. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  3574. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  3575. snd_soc_dapm_ignore_suspend(dapm, "AMIC5");
  3576. snd_soc_dapm_ignore_suspend(dapm, "AMIC6");
  3577. snd_soc_dapm_ignore_suspend(dapm, "AMIC7");
  3578. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC1");
  3579. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC2");
  3580. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC3");
  3581. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC4");
  3582. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC5");
  3583. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC6");
  3584. snd_soc_dapm_ignore_suspend(dapm, "VA AMIC7");
  3585. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_OUTPUT");
  3586. snd_soc_dapm_ignore_suspend(dapm, "IN1_HPHL");
  3587. snd_soc_dapm_ignore_suspend(dapm, "IN2_HPHR");
  3588. snd_soc_dapm_ignore_suspend(dapm, "IN3_AUX");
  3589. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  3590. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  3591. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  3592. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  3593. snd_soc_dapm_ignore_suspend(dapm, "WCD_TX_DUMMY");
  3594. snd_soc_dapm_ignore_suspend(dapm, "WCD_RX_DUMMY");
  3595. snd_soc_dapm_sync(dapm);
  3596. wcd_cls_h_init(&wcd938x->clsh_info);
  3597. wcd938x_init_reg(component);
  3598. if (wcd938x->variant == WCD9380) {
  3599. ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
  3600. ARRAY_SIZE(wcd9380_snd_controls));
  3601. if (ret < 0) {
  3602. dev_err(component->dev,
  3603. "%s: Failed to add snd ctrls for variant: %d\n",
  3604. __func__, wcd938x->variant);
  3605. goto err_hwdep;
  3606. }
  3607. }
  3608. if (wcd938x->variant == WCD9385) {
  3609. ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
  3610. ARRAY_SIZE(wcd9385_snd_controls));
  3611. if (ret < 0) {
  3612. dev_err(component->dev,
  3613. "%s: Failed to add snd ctrls for variant: %d\n",
  3614. __func__, wcd938x->variant);
  3615. goto err_hwdep;
  3616. }
  3617. }
  3618. wcd938x->version = WCD938X_VERSION_1_0;
  3619. /* Register event notifier */
  3620. wcd938x->nblock.notifier_call = wcd938x_event_notify;
  3621. if (wcd938x->register_notifier) {
  3622. ret = wcd938x->register_notifier(wcd938x->handle,
  3623. &wcd938x->nblock,
  3624. true);
  3625. if (ret) {
  3626. dev_err(component->dev,
  3627. "%s: Failed to register notifier %d\n",
  3628. __func__, ret);
  3629. return ret;
  3630. }
  3631. }
  3632. return ret;
  3633. err_hwdep:
  3634. wcd938x->fw_data = NULL;
  3635. err:
  3636. return ret;
  3637. }
  3638. static void wcd938x_soc_codec_remove(struct snd_soc_component *component)
  3639. {
  3640. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3641. if (!wcd938x) {
  3642. dev_err(component->dev, "%s: wcd938x is already NULL\n",
  3643. __func__);
  3644. return;
  3645. }
  3646. if (wcd938x->register_notifier)
  3647. wcd938x->register_notifier(wcd938x->handle,
  3648. &wcd938x->nblock,
  3649. false);
  3650. }
  3651. static int wcd938x_soc_codec_suspend(struct snd_soc_component *component)
  3652. {
  3653. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3654. if (!wcd938x)
  3655. return 0;
  3656. wcd938x->dapm_bias_off = true;
  3657. return 0;
  3658. }
  3659. static int wcd938x_soc_codec_resume(struct snd_soc_component *component)
  3660. {
  3661. struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
  3662. if (!wcd938x)
  3663. return 0;
  3664. wcd938x->dapm_bias_off = false;
  3665. return 0;
  3666. }
  3667. static struct snd_soc_component_driver soc_codec_dev_wcd938x = {
  3668. .name = WCD938X_DRV_NAME,
  3669. .probe = wcd938x_soc_codec_probe,
  3670. .remove = wcd938x_soc_codec_remove,
  3671. .controls = wcd938x_snd_controls,
  3672. .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
  3673. .dapm_widgets = wcd938x_dapm_widgets,
  3674. .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
  3675. .dapm_routes = wcd938x_audio_map,
  3676. .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
  3677. .suspend = wcd938x_soc_codec_suspend,
  3678. .resume = wcd938x_soc_codec_resume,
  3679. };
  3680. static int wcd938x_reset(struct device *dev)
  3681. {
  3682. struct wcd938x_priv *wcd938x = NULL;
  3683. int rc = 0;
  3684. int value = 0;
  3685. if (!dev)
  3686. return -ENODEV;
  3687. wcd938x = dev_get_drvdata(dev);
  3688. if (!wcd938x)
  3689. return -EINVAL;
  3690. if (!wcd938x->rst_np) {
  3691. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  3692. __func__);
  3693. return -EINVAL;
  3694. }
  3695. value = msm_cdc_pinctrl_get_state(wcd938x->rst_np);
  3696. if (value > 0)
  3697. return 0;
  3698. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3699. if (rc) {
  3700. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  3701. __func__);
  3702. return rc;
  3703. }
  3704. /* 20us sleep required after pulling the reset gpio to LOW */
  3705. usleep_range(20, 30);
  3706. rc = msm_cdc_pinctrl_select_active_state(wcd938x->rst_np);
  3707. if (rc) {
  3708. dev_err_ratelimited(dev, "%s: wcd active state request fail!\n",
  3709. __func__);
  3710. return rc;
  3711. }
  3712. /* 20us sleep required after pulling the reset gpio to HIGH */
  3713. usleep_range(20, 30);
  3714. return rc;
  3715. }
  3716. static int wcd938x_read_of_property_u32(struct device *dev, const char *name,
  3717. u32 *val)
  3718. {
  3719. int rc = 0;
  3720. rc = of_property_read_u32(dev->of_node, name, val);
  3721. if (rc)
  3722. dev_err(dev, "%s: Looking up %s property in node %s failed\n",
  3723. __func__, name, dev->of_node->full_name);
  3724. return rc;
  3725. }
  3726. static void wcd938x_dt_parse_micbias_info(struct device *dev,
  3727. struct wcd938x_micbias_setting *mb)
  3728. {
  3729. u32 prop_val = 0;
  3730. int rc = 0;
  3731. /* MB1 */
  3732. if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
  3733. NULL)) {
  3734. rc = wcd938x_read_of_property_u32(dev,
  3735. "qcom,cdc-micbias1-mv",
  3736. &prop_val);
  3737. if (!rc)
  3738. mb->micb1_mv = prop_val;
  3739. } else {
  3740. dev_info(dev, "%s: Micbias1 DT property not found\n",
  3741. __func__);
  3742. }
  3743. /* MB2 */
  3744. if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
  3745. NULL)) {
  3746. rc = wcd938x_read_of_property_u32(dev,
  3747. "qcom,cdc-micbias2-mv",
  3748. &prop_val);
  3749. if (!rc)
  3750. mb->micb2_mv = prop_val;
  3751. } else {
  3752. dev_info(dev, "%s: Micbias2 DT property not found\n",
  3753. __func__);
  3754. }
  3755. /* MB3 */
  3756. if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
  3757. NULL)) {
  3758. rc = wcd938x_read_of_property_u32(dev,
  3759. "qcom,cdc-micbias3-mv",
  3760. &prop_val);
  3761. if (!rc)
  3762. mb->micb3_mv = prop_val;
  3763. } else {
  3764. dev_info(dev, "%s: Micbias3 DT property not found\n",
  3765. __func__);
  3766. }
  3767. /* MB4 */
  3768. if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
  3769. NULL)) {
  3770. rc = wcd938x_read_of_property_u32(dev,
  3771. "qcom,cdc-micbias4-mv",
  3772. &prop_val);
  3773. if (!rc)
  3774. mb->micb4_mv = prop_val;
  3775. } else {
  3776. dev_info(dev, "%s: Micbias4 DT property not found\n",
  3777. __func__);
  3778. }
  3779. }
  3780. static int wcd938x_reset_low(struct device *dev)
  3781. {
  3782. struct wcd938x_priv *wcd938x = NULL;
  3783. int rc = 0;
  3784. if (!dev)
  3785. return -ENODEV;
  3786. wcd938x = dev_get_drvdata(dev);
  3787. if (!wcd938x)
  3788. return -EINVAL;
  3789. if (!wcd938x->rst_np) {
  3790. dev_err_ratelimited(dev, "%s: reset gpio device node not specified\n",
  3791. __func__);
  3792. return -EINVAL;
  3793. }
  3794. rc = msm_cdc_pinctrl_select_sleep_state(wcd938x->rst_np);
  3795. if (rc) {
  3796. dev_err_ratelimited(dev, "%s: wcd sleep state request fail!\n",
  3797. __func__);
  3798. return rc;
  3799. }
  3800. /* 20us sleep required after pulling the reset gpio to LOW */
  3801. usleep_range(20, 30);
  3802. return rc;
  3803. }
  3804. struct wcd938x_pdata *wcd938x_populate_dt_data(struct device *dev)
  3805. {
  3806. struct wcd938x_pdata *pdata = NULL;
  3807. pdata = devm_kzalloc(dev, sizeof(struct wcd938x_pdata),
  3808. GFP_KERNEL);
  3809. if (!pdata)
  3810. return NULL;
  3811. pdata->rst_np = of_parse_phandle(dev->of_node,
  3812. "qcom,wcd-rst-gpio-node", 0);
  3813. if (!pdata->rst_np) {
  3814. dev_err_ratelimited(dev, "%s: Looking up %s property in node %s failed\n",
  3815. __func__, "qcom,wcd-rst-gpio-node",
  3816. dev->of_node->full_name);
  3817. return NULL;
  3818. }
  3819. /* Parse power supplies */
  3820. msm_cdc_get_power_supplies(dev, &pdata->regulator,
  3821. &pdata->num_supplies);
  3822. if (!pdata->regulator || (pdata->num_supplies <= 0)) {
  3823. dev_err_ratelimited(dev, "%s: no power supplies defined for codec\n",
  3824. __func__);
  3825. return NULL;
  3826. }
  3827. pdata->rx_slave = of_parse_phandle(dev->of_node, "qcom,rx-slave", 0);
  3828. pdata->tx_slave = of_parse_phandle(dev->of_node, "qcom,tx-slave", 0);
  3829. wcd938x_dt_parse_micbias_info(dev, &pdata->micbias);
  3830. return pdata;
  3831. }
  3832. static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
  3833. {
  3834. pr_err_ratelimited("%s: Watchdog interrupt for irq =%d triggered\n",
  3835. __func__, irq);
  3836. return IRQ_HANDLED;
  3837. }
  3838. static struct snd_soc_dai_driver wcd938x_dai[] = {
  3839. {
  3840. .name = "wcd938x_cdc",
  3841. .playback = {
  3842. .stream_name = "WCD938X_AIF Playback",
  3843. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3844. .formats = WCD938X_FORMATS,
  3845. .rate_max = 384000,
  3846. .rate_min = 8000,
  3847. .channels_min = 1,
  3848. .channels_max = 4,
  3849. },
  3850. .capture = {
  3851. .stream_name = "WCD938X_AIF Capture",
  3852. .rates = WCD938X_RATES | WCD938X_FRAC_RATES,
  3853. .formats = WCD938X_FORMATS,
  3854. .rate_max = 384000,
  3855. .rate_min = 8000,
  3856. .channels_min = 1,
  3857. .channels_max = 4,
  3858. },
  3859. },
  3860. };
  3861. static int wcd938x_bind(struct device *dev)
  3862. {
  3863. int ret = 0, i = 0;
  3864. struct wcd938x_pdata *pdata = dev_get_platdata(dev);
  3865. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3866. /*
  3867. * Add 5msec delay to provide sufficient time for
  3868. * soundwire auto enumeration of slave devices as
  3869. * as per HW requirement.
  3870. */
  3871. usleep_range(5000, 5010);
  3872. ret = component_bind_all(dev, wcd938x);
  3873. if (ret) {
  3874. dev_err_ratelimited(dev, "%s: Slave bind failed, ret = %d\n",
  3875. __func__, ret);
  3876. return ret;
  3877. }
  3878. wcd938x->rx_swr_dev = get_matching_swr_slave_device(pdata->rx_slave);
  3879. if (!wcd938x->rx_swr_dev) {
  3880. dev_err_ratelimited(dev, "%s: Could not find RX swr slave device\n",
  3881. __func__);
  3882. ret = -ENODEV;
  3883. goto err;
  3884. }
  3885. wcd938x->tx_swr_dev = get_matching_swr_slave_device(pdata->tx_slave);
  3886. if (!wcd938x->tx_swr_dev) {
  3887. dev_err_ratelimited(dev, "%s: Could not find TX swr slave device\n",
  3888. __func__);
  3889. ret = -ENODEV;
  3890. goto err;
  3891. }
  3892. swr_init_port_params(wcd938x->tx_swr_dev, SWR_NUM_PORTS,
  3893. wcd938x->swr_tx_port_params);
  3894. wcd938x->regmap = devm_regmap_init_swr(wcd938x->tx_swr_dev,
  3895. &wcd938x_regmap_config);
  3896. if (!wcd938x->regmap) {
  3897. dev_err_ratelimited(dev, "%s: Regmap init failed\n",
  3898. __func__);
  3899. goto err;
  3900. }
  3901. /* Set all interupts as edge triggered */
  3902. for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++)
  3903. regmap_write(wcd938x->regmap,
  3904. (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
  3905. wcd938x_regmap_irq_chip.irq_drv_data = wcd938x;
  3906. wcd938x->irq_info.wcd_regmap_irq_chip = &wcd938x_regmap_irq_chip;
  3907. wcd938x->irq_info.codec_name = "WCD938X";
  3908. wcd938x->irq_info.regmap = wcd938x->regmap;
  3909. wcd938x->irq_info.dev = dev;
  3910. ret = wcd_irq_init(&wcd938x->irq_info, &wcd938x->virq);
  3911. if (ret) {
  3912. dev_err_ratelimited(wcd938x->dev, "%s: IRQ init failed: %d\n",
  3913. __func__, ret);
  3914. goto err;
  3915. }
  3916. wcd938x->tx_swr_dev->slave_irq = wcd938x->virq;
  3917. ret = wcd938x_set_micbias_data(wcd938x, pdata);
  3918. if (ret < 0) {
  3919. dev_err_ratelimited(dev, "%s: bad micbias pdata\n", __func__);
  3920. goto err_irq;
  3921. }
  3922. /* Request for watchdog interrupt */
  3923. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT,
  3924. "HPHR PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3925. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT,
  3926. "HPHL PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3927. wcd_request_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT,
  3928. "AUX PDM WD INT", wcd938x_wd_handle_irq, NULL);
  3929. /* Disable watchdog interrupt for HPH and AUX */
  3930. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT);
  3931. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT);
  3932. wcd_disable_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT);
  3933. ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
  3934. wcd938x_dai, ARRAY_SIZE(wcd938x_dai));
  3935. if (ret) {
  3936. dev_err_ratelimited(dev, "%s: Codec registration failed\n",
  3937. __func__);
  3938. goto err_irq;
  3939. }
  3940. wcd938x->dev_up = true;
  3941. return ret;
  3942. err_irq:
  3943. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3944. err:
  3945. component_unbind_all(dev, wcd938x);
  3946. return ret;
  3947. }
  3948. static void wcd938x_unbind(struct device *dev)
  3949. {
  3950. struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
  3951. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHR_PDM_WD_INT, NULL);
  3952. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_HPHL_PDM_WD_INT, NULL);
  3953. wcd_free_irq(&wcd938x->irq_info, WCD938X_IRQ_AUX_PDM_WD_INT, NULL);
  3954. wcd_irq_exit(&wcd938x->irq_info, wcd938x->virq);
  3955. snd_soc_unregister_component(dev);
  3956. component_unbind_all(dev, wcd938x);
  3957. }
  3958. static const struct of_device_id wcd938x_dt_match[] = {
  3959. { .compatible = "qcom,wcd938x-codec", .data = "wcd938x"},
  3960. {}
  3961. };
  3962. static const struct component_master_ops wcd938x_comp_ops = {
  3963. .bind = wcd938x_bind,
  3964. .unbind = wcd938x_unbind,
  3965. };
  3966. static int wcd938x_compare_of(struct device *dev, void *data)
  3967. {
  3968. return dev->of_node == data;
  3969. }
  3970. static void wcd938x_release_of(struct device *dev, void *data)
  3971. {
  3972. of_node_put(data);
  3973. }
  3974. static int wcd938x_add_slave_components(struct device *dev,
  3975. struct component_match **matchptr)
  3976. {
  3977. struct device_node *np, *rx_node, *tx_node;
  3978. np = dev->of_node;
  3979. rx_node = of_parse_phandle(np, "qcom,rx-slave", 0);
  3980. if (!rx_node) {
  3981. dev_err_ratelimited(dev, "%s: Rx-slave node not defined\n", __func__);
  3982. return -ENODEV;
  3983. }
  3984. of_node_get(rx_node);
  3985. component_match_add_release(dev, matchptr,
  3986. wcd938x_release_of,
  3987. wcd938x_compare_of,
  3988. rx_node);
  3989. tx_node = of_parse_phandle(np, "qcom,tx-slave", 0);
  3990. if (!tx_node) {
  3991. dev_err_ratelimited(dev, "%s: Tx-slave node not defined\n", __func__);
  3992. return -ENODEV;
  3993. }
  3994. of_node_get(tx_node);
  3995. component_match_add_release(dev, matchptr,
  3996. wcd938x_release_of,
  3997. wcd938x_compare_of,
  3998. tx_node);
  3999. return 0;
  4000. }
  4001. static int wcd938x_probe(struct platform_device *pdev)
  4002. {
  4003. struct component_match *match = NULL;
  4004. struct wcd938x_priv *wcd938x = NULL;
  4005. struct wcd938x_pdata *pdata = NULL;
  4006. struct wcd_ctrl_platform_data *plat_data = NULL;
  4007. struct device *dev = &pdev->dev;
  4008. int ret;
  4009. wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
  4010. GFP_KERNEL);
  4011. if (!wcd938x)
  4012. return -ENOMEM;
  4013. dev_set_drvdata(dev, wcd938x);
  4014. wcd938x->dev = dev;
  4015. pdata = wcd938x_populate_dt_data(dev);
  4016. if (!pdata) {
  4017. dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
  4018. return -EINVAL;
  4019. }
  4020. dev->platform_data = pdata;
  4021. wcd938x->rst_np = pdata->rst_np;
  4022. ret = msm_cdc_init_supplies(dev, &wcd938x->supplies,
  4023. pdata->regulator, pdata->num_supplies);
  4024. if (!wcd938x->supplies) {
  4025. dev_err(dev, "%s: Cannot init wcd supplies\n",
  4026. __func__);
  4027. return ret;
  4028. }
  4029. plat_data = dev_get_platdata(dev->parent);
  4030. if (!plat_data) {
  4031. dev_err(dev, "%s: platform data from parent is NULL\n",
  4032. __func__);
  4033. return -EINVAL;
  4034. }
  4035. wcd938x->handle = (void *)plat_data->handle;
  4036. if (!wcd938x->handle) {
  4037. dev_err(dev, "%s: handle is NULL\n", __func__);
  4038. return -EINVAL;
  4039. }
  4040. wcd938x->update_wcd_event = plat_data->update_wcd_event;
  4041. if (!wcd938x->update_wcd_event) {
  4042. dev_err(dev, "%s: update_wcd_event api is null!\n",
  4043. __func__);
  4044. return -EINVAL;
  4045. }
  4046. wcd938x->register_notifier = plat_data->register_notifier;
  4047. if (!wcd938x->register_notifier) {
  4048. dev_err(dev, "%s: register_notifier api is null!\n",
  4049. __func__);
  4050. return -EINVAL;
  4051. }
  4052. ret = msm_cdc_enable_static_supplies(&pdev->dev, wcd938x->supplies,
  4053. pdata->regulator,
  4054. pdata->num_supplies);
  4055. if (ret) {
  4056. dev_err(dev, "%s: wcd static supply enable failed!\n",
  4057. __func__);
  4058. return ret;
  4059. }
  4060. ret = wcd938x_parse_port_mapping(dev, "qcom,rx_swr_ch_map",
  4061. CODEC_RX);
  4062. ret |= wcd938x_parse_port_mapping(dev, "qcom,tx_swr_ch_map",
  4063. CODEC_TX);
  4064. if (ret) {
  4065. dev_err(dev, "Failed to read port mapping\n");
  4066. goto err;
  4067. }
  4068. ret = wcd938x_parse_port_params(dev, "qcom,swr-tx-port-params",
  4069. CODEC_TX);
  4070. if (ret) {
  4071. dev_err(dev, "Failed to read port params\n");
  4072. goto err;
  4073. }
  4074. mutex_init(&wcd938x->wakeup_lock);
  4075. mutex_init(&wcd938x->micb_lock);
  4076. ret = wcd938x_add_slave_components(dev, &match);
  4077. if (ret)
  4078. goto err_lock_init;
  4079. wcd938x_reset(dev);
  4080. wcd938x->wakeup = wcd938x_wakeup;
  4081. return component_master_add_with_match(dev,
  4082. &wcd938x_comp_ops, match);
  4083. err_lock_init:
  4084. mutex_destroy(&wcd938x->micb_lock);
  4085. mutex_destroy(&wcd938x->wakeup_lock);
  4086. err:
  4087. return ret;
  4088. }
  4089. static int wcd938x_remove(struct platform_device *pdev)
  4090. {
  4091. struct wcd938x_priv *wcd938x = NULL;
  4092. wcd938x = platform_get_drvdata(pdev);
  4093. component_master_del(&pdev->dev, &wcd938x_comp_ops);
  4094. mutex_destroy(&wcd938x->micb_lock);
  4095. mutex_destroy(&wcd938x->wakeup_lock);
  4096. dev_set_drvdata(&pdev->dev, NULL);
  4097. return 0;
  4098. }
  4099. #ifdef CONFIG_PM_SLEEP
  4100. static int wcd938x_suspend(struct device *dev)
  4101. {
  4102. struct wcd938x_priv *wcd938x = NULL;
  4103. int ret = 0;
  4104. struct wcd938x_pdata *pdata = NULL;
  4105. if (!dev)
  4106. return -ENODEV;
  4107. wcd938x = dev_get_drvdata(dev);
  4108. if (!wcd938x)
  4109. return -EINVAL;
  4110. pdata = dev_get_platdata(wcd938x->dev);
  4111. if (!pdata) {
  4112. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4113. return -EINVAL;
  4114. }
  4115. if (test_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask)) {
  4116. ret = msm_cdc_disable_ondemand_supply(wcd938x->dev,
  4117. wcd938x->supplies,
  4118. pdata->regulator,
  4119. pdata->num_supplies,
  4120. "cdc-vdd-buck");
  4121. if (ret == -EINVAL) {
  4122. dev_err_ratelimited(dev, "%s: vdd buck is not disabled\n",
  4123. __func__);
  4124. return 0;
  4125. }
  4126. clear_bit(ALLOW_BUCK_DISABLE, &wcd938x->status_mask);
  4127. }
  4128. if (wcd938x->dapm_bias_off) {
  4129. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4130. wcd938x->supplies,
  4131. pdata->regulator,
  4132. pdata->num_supplies,
  4133. true);
  4134. set_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4135. }
  4136. return 0;
  4137. }
  4138. static int wcd938x_resume(struct device *dev)
  4139. {
  4140. struct wcd938x_priv *wcd938x = NULL;
  4141. struct wcd938x_pdata *pdata = NULL;
  4142. if (!dev)
  4143. return -ENODEV;
  4144. wcd938x = dev_get_drvdata(dev);
  4145. if (!wcd938x)
  4146. return -EINVAL;
  4147. pdata = dev_get_platdata(wcd938x->dev);
  4148. if (!pdata) {
  4149. dev_err_ratelimited(dev, "%s: pdata is NULL\n", __func__);
  4150. return -EINVAL;
  4151. }
  4152. if (test_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask)) {
  4153. msm_cdc_set_supplies_lpm_mode(wcd938x->dev,
  4154. wcd938x->supplies,
  4155. pdata->regulator,
  4156. pdata->num_supplies,
  4157. false);
  4158. clear_bit(WCD_SUPPLIES_LPM_MODE, &wcd938x->status_mask);
  4159. }
  4160. return 0;
  4161. }
  4162. static const struct dev_pm_ops wcd938x_dev_pm_ops = {
  4163. .suspend_late = wcd938x_suspend,
  4164. .resume_early = wcd938x_resume,
  4165. };
  4166. #endif
  4167. static struct platform_driver wcd938x_codec_driver = {
  4168. .probe = wcd938x_probe,
  4169. .remove = wcd938x_remove,
  4170. .driver = {
  4171. .name = "wcd938x_codec",
  4172. .owner = THIS_MODULE,
  4173. .of_match_table = of_match_ptr(wcd938x_dt_match),
  4174. #ifdef CONFIG_PM_SLEEP
  4175. .pm = &wcd938x_dev_pm_ops,
  4176. #endif
  4177. .suppress_bind_attrs = true,
  4178. },
  4179. };
  4180. module_platform_driver(wcd938x_codec_driver);
  4181. MODULE_DESCRIPTION("WCD938X Codec driver");
  4182. MODULE_LICENSE("GPL v2");