hal_api_mon.h 14 KB

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  1. /*
  2. * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_API_MON_H_
  19. #define _HAL_API_MON_H_
  20. #include "qdf_types.h"
  21. #include "hal_internal.h"
  22. #include <target_type.h>
  23. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  24. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  25. #define HAL_RX_MASk(block, field) block##_##field##_MASK
  26. #define HAL_RX_GET(_ptr, block, field) \
  27. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  28. HAL_RX_MASk(block, field)) >> \
  29. HAL_RX_LSB(block, field))
  30. #define HAL_RX_PHY_DATA_RADAR 0x01
  31. #define HAL_SU_MU_CODING_LDPC 0x01
  32. #define HAL_RX_FCS_LEN (4)
  33. #define KEY_EXTIV 0x20
  34. #define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000
  35. #define HAL_RX_USER_TLV32_TYPE_LSB 1
  36. #define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE
  37. #define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000
  38. #define HAL_RX_USER_TLV32_LEN_LSB 10
  39. #define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00
  40. #define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000
  41. #define HAL_RX_USER_TLV32_USERID_LSB 26
  42. #define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000
  43. #define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1)
  44. #define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask))
  45. #define HAL_RX_TLV32_HDR_SIZE 4
  46. #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \
  47. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  48. HAL_RX_USER_TLV32_TYPE_MASK) >> \
  49. HAL_RX_USER_TLV32_TYPE_LSB)
  50. #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \
  51. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  52. HAL_RX_USER_TLV32_LEN_MASK) >> \
  53. HAL_RX_USER_TLV32_LEN_LSB)
  54. #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \
  55. ((*((uint32_t *)(rx_status_tlv_ptr)) & \
  56. HAL_RX_USER_TLV32_USERID_MASK) >> \
  57. HAL_RX_USER_TLV32_USERID_LSB)
  58. #define HAL_TLV_STATUS_PPDU_NOT_DONE 0
  59. #define HAL_TLV_STATUS_PPDU_DONE 1
  60. #define HAL_TLV_STATUS_BUF_DONE 2
  61. #define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3
  62. #define HAL_MAX_UL_MU_USERS 8
  63. #define HAL_RX_PKT_TYPE_11A 0
  64. #define HAL_RX_PKT_TYPE_11B 1
  65. #define HAL_RX_PKT_TYPE_11N 2
  66. #define HAL_RX_PKT_TYPE_11AC 3
  67. #define HAL_RX_PKT_TYPE_11AX 4
  68. #define HAL_RX_RECEPTION_TYPE_SU 0
  69. #define HAL_RX_RECEPTION_TYPE_MU_MIMO 1
  70. #define HAL_RX_RECEPTION_TYPE_OFDMA 2
  71. #define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3
  72. /* Multiply rate by 2 to avoid float point
  73. * and get rate in units of 500kbps
  74. */
  75. #define HAL_11B_RATE_0MCS 11*2
  76. #define HAL_11B_RATE_1MCS 5.5*2
  77. #define HAL_11B_RATE_2MCS 2*2
  78. #define HAL_11B_RATE_3MCS 1*2
  79. #define HAL_11B_RATE_4MCS 11*2
  80. #define HAL_11B_RATE_5MCS 5.5*2
  81. #define HAL_11B_RATE_6MCS 2*2
  82. #define HAL_11A_RATE_0MCS 48*2
  83. #define HAL_11A_RATE_1MCS 24*2
  84. #define HAL_11A_RATE_2MCS 12*2
  85. #define HAL_11A_RATE_3MCS 6*2
  86. #define HAL_11A_RATE_4MCS 54*2
  87. #define HAL_11A_RATE_5MCS 36*2
  88. #define HAL_11A_RATE_6MCS 18*2
  89. #define HAL_11A_RATE_7MCS 9*2
  90. #define HE_GI_0_8 0
  91. #define HE_GI_1_6 1
  92. #define HE_GI_3_2 2
  93. #define HT_SGI_PRESENT 0x80
  94. #define HE_LTF_1_X 0
  95. #define HE_LTF_2_X 1
  96. #define HE_LTF_4_X 2
  97. #define VHT_SIG_SU_NSS_MASK 0x7
  98. #define HAL_TID_INVALID 31
  99. #define HAL_AST_IDX_INVALID 0xFFFF
  100. #ifdef GET_MSDU_AGGREGATION
  101. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
  102. {\
  103. struct rx_msdu_end *rx_msdu_end;\
  104. bool first_msdu, last_msdu; \
  105. rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
  106. first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\
  107. last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\
  108. if (first_msdu && last_msdu)\
  109. rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
  110. else\
  111. rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
  112. } \
  113. #else
  114. #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
  115. #endif
  116. #define HAL_MAC_ADDR_LEN 6
  117. enum {
  118. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  119. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  120. HAL_HW_RX_DECAP_FORMAT_ETH2,
  121. HAL_HW_RX_DECAP_FORMAT_8023,
  122. };
  123. enum {
  124. DP_PPDU_STATUS_START,
  125. DP_PPDU_STATUS_DONE,
  126. };
  127. static inline
  128. uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void)
  129. {
  130. /* return the HW_RX_DESC size */
  131. return sizeof(struct rx_pkt_tlvs);
  132. }
  133. static inline
  134. uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data)
  135. {
  136. return data;
  137. }
  138. static inline
  139. uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr)
  140. {
  141. struct rx_attention *rx_attn;
  142. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  143. rx_attn = &rx_desc->attn_tlv.rx_attn;
  144. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
  145. }
  146. static inline
  147. uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr)
  148. {
  149. struct rx_attention *rx_attn;
  150. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  151. rx_attn = &rx_desc->attn_tlv.rx_attn;
  152. return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
  153. }
  154. static inline
  155. uint32_t
  156. HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) {
  157. struct rx_msdu_start *rx_msdu_start;
  158. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  159. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  160. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  161. }
  162. static inline
  163. uint8_t *
  164. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  165. uint8_t *rx_pkt_hdr;
  166. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  167. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  168. return rx_pkt_hdr;
  169. }
  170. /*
  171. * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU
  172. * start TLV of Hardware TLV descriptor
  173. * @hw_desc_addr: Hardware desciptor address
  174. *
  175. * Return: bool: if TLV tag match
  176. */
  177. static inline
  178. bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr)
  179. {
  180. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  181. uint32_t tlv_tag;
  182. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(
  183. &rx_desc->mpdu_start_tlv);
  184. return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
  185. }
  186. static inline
  187. uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr)
  188. {
  189. struct rx_mpdu_info *rx_mpdu_info;
  190. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  191. rx_mpdu_info =
  192. &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  193. return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
  194. }
  195. /* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */
  196. static inline
  197. uint32_t hal_rx_desc_is_first_msdu(void *hw_desc_addr)
  198. {
  199. struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
  200. struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
  201. return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
  202. }
  203. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  204. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  205. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  206. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  207. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  208. #define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \
  209. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  210. (((struct reo_entrance_ring *)reo_ent_desc) \
  211. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  212. #define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \
  213. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  214. (((struct reo_entrance_ring *)reo_ent_desc) \
  215. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  216. #define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \
  217. (HAL_RX_BUF_COOKIE_GET(& \
  218. (((struct reo_entrance_ring *)reo_ent_desc) \
  219. ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
  220. /**
  221. * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and
  222. * cookie from the REO entrance ring element
  223. *
  224. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  225. * the current descriptor
  226. * @ buf_info: structure to return the buffer information
  227. * @ msdu_cnt: pointer to msdu count in MPDU
  228. * Return: void
  229. */
  230. static inline
  231. void hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
  232. struct hal_buf_info *buf_info,
  233. void **pp_buf_addr_info,
  234. uint32_t *msdu_cnt
  235. )
  236. {
  237. struct reo_entrance_ring *reo_ent_ring =
  238. (struct reo_entrance_ring *)rx_desc;
  239. struct buffer_addr_info *buf_addr_info;
  240. struct rx_mpdu_desc_info *rx_mpdu_desc_info_details;
  241. uint32_t loop_cnt;
  242. rx_mpdu_desc_info_details =
  243. &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
  244. *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details,
  245. RX_MPDU_DESC_INFO_0, MSDU_COUNT);
  246. loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT);
  247. buf_addr_info =
  248. &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
  249. buf_info->paddr =
  250. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  251. ((uint64_t)
  252. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  253. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  254. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  255. "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d",
  256. __func__, __LINE__, reo_ent_ring, buf_addr_info,
  257. (unsigned long long)buf_info->paddr, loop_cnt);
  258. *pp_buf_addr_info = (void *)buf_addr_info;
  259. }
  260. static inline
  261. void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
  262. struct hal_buf_info *buf_info, void **pp_buf_addr_info)
  263. {
  264. struct rx_msdu_link *msdu_link =
  265. (struct rx_msdu_link *)rx_msdu_link_desc;
  266. struct buffer_addr_info *buf_addr_info;
  267. buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info;
  268. buf_info->paddr =
  269. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  270. ((uint64_t)
  271. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  272. buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
  273. *pp_buf_addr_info = (void *)buf_addr_info;
  274. }
  275. /**
  276. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  277. *
  278. * @ soc : HAL version of the SOC pointer
  279. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  280. * @ buf_addr_info : void pointer to the buffer_addr_info
  281. *
  282. * Return: void
  283. */
  284. static inline void hal_rx_mon_msdu_link_desc_set(struct hal_soc *soc,
  285. void *src_srng_desc, void *buf_addr_info)
  286. {
  287. struct buffer_addr_info *wbm_srng_buffer_addr_info =
  288. (struct buffer_addr_info *)src_srng_desc;
  289. uint64_t paddr;
  290. struct buffer_addr_info *p_buffer_addr_info =
  291. (struct buffer_addr_info *)buf_addr_info;
  292. paddr =
  293. (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
  294. ((uint64_t)
  295. (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
  296. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  297. "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx",
  298. __func__, __LINE__, src_srng_desc, (unsigned long long)paddr,
  299. (unsigned long long)p_buffer_addr_info->sw_buffer_cookie);
  300. /* Structure copy !!! */
  301. *wbm_srng_buffer_addr_info =
  302. *((struct buffer_addr_info *)buf_addr_info);
  303. }
  304. static inline
  305. uint32 hal_get_rx_msdu_link_desc_size(void)
  306. {
  307. return sizeof(struct rx_msdu_link);
  308. }
  309. enum {
  310. HAL_PKT_TYPE_OFDM = 0,
  311. HAL_PKT_TYPE_CCK,
  312. HAL_PKT_TYPE_HT,
  313. HAL_PKT_TYPE_VHT,
  314. HAL_PKT_TYPE_HE,
  315. };
  316. enum {
  317. HAL_SGI_0_8_US,
  318. HAL_SGI_0_4_US,
  319. HAL_SGI_1_6_US,
  320. HAL_SGI_3_2_US,
  321. };
  322. enum {
  323. HAL_FULL_RX_BW_20,
  324. HAL_FULL_RX_BW_40,
  325. HAL_FULL_RX_BW_80,
  326. HAL_FULL_RX_BW_160,
  327. };
  328. enum {
  329. HAL_RX_TYPE_SU,
  330. HAL_RX_TYPE_MU_MIMO,
  331. HAL_RX_TYPE_MU_OFDMA,
  332. HAL_RX_TYPE_MU_OFDMA_MIMO,
  333. };
  334. /**
  335. * enum
  336. * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL
  337. * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL
  338. */
  339. enum {
  340. HAL_RX_MON_PPDU_START = 0,
  341. HAL_RX_MON_PPDU_END,
  342. };
  343. struct hal_rx_ppdu_user_info {
  344. };
  345. struct hal_rx_ppdu_common_info {
  346. uint32_t ppdu_id;
  347. uint32_t ppdu_timestamp;
  348. uint32_t mpdu_cnt_fcs_ok;
  349. uint32_t mpdu_cnt_fcs_err;
  350. };
  351. struct hal_rx_msdu_payload_info {
  352. uint8_t *first_msdu_payload;
  353. uint32_t payload_len;
  354. };
  355. /**
  356. * struct hal_rx_nac_info - struct for neighbour info
  357. * @fc_valid: flag indicate if it has valid frame control information
  358. * @to_ds_flag: flag indicate to_ds bit
  359. * @mac_addr2_valid: flag indicate if mac_addr2 is valid
  360. * @mac_addr2: mac address2 in wh
  361. */
  362. struct hal_rx_nac_info {
  363. uint8_t fc_valid;
  364. uint8_t to_ds_flag;
  365. uint8_t mac_addr2_valid;
  366. uint8_t mac_addr2[HAL_MAC_ADDR_LEN];
  367. };
  368. struct hal_rx_ppdu_info {
  369. struct hal_rx_ppdu_common_info com_info;
  370. struct hal_rx_ppdu_user_info user_info[HAL_MAX_UL_MU_USERS];
  371. struct mon_rx_status rx_status;
  372. struct hal_rx_msdu_payload_info msdu_info;
  373. struct hal_rx_nac_info nac_info;
  374. /* status ring PPDU start and end state */
  375. uint32_t rx_state;
  376. };
  377. static inline uint32_t
  378. hal_get_rx_status_buf_size(void) {
  379. /* RX status buffer size is hard coded for now */
  380. return 2048;
  381. }
  382. static inline uint8_t*
  383. hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
  384. uint32_t tlv_len, tlv_tag;
  385. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
  386. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  387. /* The actual length of PPDU_END is the combined length of many PHY
  388. * TLVs that follow. Skip the TLV header and
  389. * rx_rxpcu_classification_overview that follows the header to get to
  390. * next TLV.
  391. */
  392. if (tlv_tag == WIFIRX_PPDU_END_E)
  393. tlv_len = sizeof(struct rx_rxpcu_classification_overview);
  394. return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len +
  395. HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
  396. }
  397. /**
  398. * hal_rx_proc_phyrx_other_receive_info_tlv()
  399. * - process other receive info TLV
  400. * @rx_tlv_hdr: pointer to TLV header
  401. * @ppdu_info: pointer to ppdu_info
  402. *
  403. * Return: None
  404. */
  405. static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
  406. void *rx_tlv_hdr,
  407. struct hal_rx_ppdu_info
  408. *ppdu_info)
  409. {
  410. hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr,
  411. (void *)ppdu_info);
  412. }
  413. /**
  414. * hal_rx_status_get_tlv_info() - process receive info TLV
  415. * @rx_tlv_hdr: pointer to TLV header
  416. * @ppdu_info: pointer to ppdu_info
  417. *
  418. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  419. */
  420. static inline uint32_t
  421. hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info,
  422. struct hal_soc *hal_soc)
  423. {
  424. return hal_soc->ops->hal_rx_status_get_tlv_info(rx_tlv_hdr,
  425. ppdu_info, hal_soc);
  426. }
  427. static inline
  428. uint32_t hal_get_rx_status_done_tlv_size(void *hal_soc)
  429. {
  430. return HAL_RX_TLV32_HDR_SIZE;
  431. }
  432. static inline QDF_STATUS
  433. hal_get_rx_status_done(uint8_t *rx_tlv)
  434. {
  435. uint32_t tlv_tag;
  436. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
  437. if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E)
  438. return QDF_STATUS_SUCCESS;
  439. else
  440. return QDF_STATUS_E_EMPTY;
  441. }
  442. static inline QDF_STATUS
  443. hal_clear_rx_status_done(uint8_t *rx_tlv)
  444. {
  445. *(uint32_t *)rx_tlv = 0;
  446. return QDF_STATUS_SUCCESS;
  447. }
  448. #endif