swr-wcd-ctrl.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/irq.h>
  5. #include <linux/kernel.h>
  6. #include <linux/init.h>
  7. #include <linux/slab.h>
  8. #include <linux/io.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/delay.h>
  12. #include <linux/kthread.h>
  13. #include <linux/clk.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/of.h>
  16. #include <linux/debugfs.h>
  17. #include <linux/uaccess.h>
  18. #include <soc/soundwire.h>
  19. #include <soc/swr-wcd.h>
  20. #include <dsp/msm-audio-event-notify.h>
  21. #include "swrm_registers.h"
  22. #include "swr-wcd-ctrl.h"
  23. #define SWR_BROADCAST_CMD_ID 0x0F
  24. #define SWR_AUTO_SUSPEND_DELAY 3 /* delay in sec */
  25. #define SWR_DEV_ID_MASK 0xFFFFFFFF
  26. #define SWR_REG_VAL_PACK(data, dev, id, reg) \
  27. ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
  28. /* pm runtime auto suspend timer in msecs */
  29. static int auto_suspend_timer = SWR_AUTO_SUSPEND_DELAY * 1000;
  30. module_param(auto_suspend_timer, int, 0664);
  31. MODULE_PARM_DESC(auto_suspend_timer, "timer for auto suspend");
  32. static u8 mstr_ports[] = {100, 101, 102, 103, 104, 105, 106, 107};
  33. static u8 mstr_port_type[] = {SWR_DAC_PORT, SWR_COMP_PORT, SWR_BOOST_PORT,
  34. SWR_DAC_PORT, SWR_COMP_PORT, SWR_BOOST_PORT,
  35. SWR_VISENSE_PORT, SWR_VISENSE_PORT};
  36. struct usecase uc[] = {
  37. {0, 0, 0}, /* UC0: no ports */
  38. {1, 1, 2400}, /* UC1: Spkr */
  39. {1, 4, 600}, /* UC2: Compander */
  40. {1, 2, 300}, /* UC3: Smart Boost */
  41. {1, 2, 1200}, /* UC4: VI Sense */
  42. {4, 9, 4500}, /* UC5: Spkr + Comp + SB + VI */
  43. {8, 18, 9000}, /* UC6: 2*(Spkr + Comp + SB + VI) */
  44. {2, 2, 4800}, /* UC7: 2*Spkr */
  45. {2, 5, 3000}, /* UC8: Spkr + Comp */
  46. {4, 10, 6000}, /* UC9: 2*(Spkr + Comp) */
  47. {3, 7, 3300}, /* UC10: Spkr + Comp + SB */
  48. {6, 14, 6600}, /* UC11: 2*(Spkr + Comp + SB) */
  49. {2, 3, 2700}, /* UC12: Spkr + SB */
  50. {4, 6, 5400}, /* UC13: 2*(Spkr + SB) */
  51. {3, 5, 3900}, /* UC14: Spkr + SB + VI */
  52. {6, 10, 7800}, /* UC15: 2*(Spkr + SB + VI) */
  53. {2, 3, 3600}, /* UC16: Spkr + VI */
  54. {4, 6, 7200}, /* UC17: 2*(Spkr + VI) */
  55. {3, 7, 4200}, /* UC18: Spkr + Comp + VI */
  56. {6, 14, 8400}, /* UC19: 2*(Spkr + Comp + VI) */
  57. };
  58. #define MAX_USECASE ARRAY_SIZE(uc)
  59. struct port_params pp[MAX_USECASE][SWR_MSTR_PORT_LEN] = {
  60. /* UC 0 */
  61. {
  62. {0, 0, 0},
  63. },
  64. /* UC 1 */
  65. {
  66. {7, 1, 0},
  67. },
  68. /* UC 2 */
  69. {
  70. {31, 2, 0},
  71. },
  72. /* UC 3 */
  73. {
  74. {63, 12, 31},
  75. },
  76. /* UC 4 */
  77. {
  78. {15, 7, 0},
  79. },
  80. /* UC 5 */
  81. {
  82. {7, 1, 0},
  83. {31, 2, 0},
  84. {63, 12, 31},
  85. {15, 7, 0},
  86. },
  87. /* UC 6 */
  88. {
  89. {7, 1, 0},
  90. {31, 2, 0},
  91. {63, 12, 31},
  92. {15, 7, 0},
  93. {7, 6, 0},
  94. {31, 18, 0},
  95. {63, 13, 31},
  96. {15, 10, 0},
  97. },
  98. /* UC 7 */
  99. {
  100. {7, 1, 0},
  101. {7, 6, 0},
  102. },
  103. /* UC 8 */
  104. {
  105. {7, 1, 0},
  106. {31, 2, 0},
  107. },
  108. /* UC 9 */
  109. {
  110. {7, 1, 0},
  111. {31, 2, 0},
  112. {7, 6, 0},
  113. {31, 18, 0},
  114. },
  115. /* UC 10 */
  116. {
  117. {7, 1, 0},
  118. {31, 2, 0},
  119. {63, 12, 31},
  120. },
  121. /* UC 11 */
  122. {
  123. {7, 1, 0},
  124. {31, 2, 0},
  125. {63, 12, 31},
  126. {7, 6, 0},
  127. {31, 18, 0},
  128. {63, 13, 31},
  129. },
  130. /* UC 12 */
  131. {
  132. {7, 1, 0},
  133. {63, 12, 31},
  134. },
  135. /* UC 13 */
  136. {
  137. {7, 1, 0},
  138. {63, 12, 31},
  139. {7, 6, 0},
  140. {63, 13, 31},
  141. },
  142. /* UC 14 */
  143. {
  144. {7, 1, 0},
  145. {63, 12, 31},
  146. {15, 7, 0},
  147. },
  148. /* UC 15 */
  149. {
  150. {7, 1, 0},
  151. {63, 12, 31},
  152. {15, 7, 0},
  153. {7, 6, 0},
  154. {63, 13, 31},
  155. {15, 10, 0},
  156. },
  157. /* UC 16 */
  158. {
  159. {7, 1, 0},
  160. {15, 7, 0},
  161. },
  162. /* UC 17 */
  163. {
  164. {7, 1, 0},
  165. {15, 7, 0},
  166. {7, 6, 0},
  167. {15, 10, 0},
  168. },
  169. /* UC 18 */
  170. {
  171. {7, 1, 0},
  172. {31, 2, 0},
  173. {15, 7, 0},
  174. },
  175. /* UC 19 */
  176. {
  177. {7, 1, 0},
  178. {31, 2, 0},
  179. {15, 7, 0},
  180. {7, 6, 0},
  181. {31, 18, 0},
  182. {15, 10, 0},
  183. },
  184. };
  185. enum {
  186. SWR_NOT_PRESENT, /* Device is detached/not present on the bus */
  187. SWR_ATTACHED_OK, /* Device is attached */
  188. SWR_ALERT, /* Device alters master for any interrupts */
  189. SWR_RESERVED, /* Reserved */
  190. };
  191. #define SWRM_MAX_PORT_REG 40
  192. #define SWRM_MAX_INIT_REG 8
  193. #define SWR_MSTR_MAX_REG_ADDR 0x1740
  194. #define SWR_MSTR_START_REG_ADDR 0x00
  195. #define SWR_MSTR_MAX_BUF_LEN 32
  196. #define BYTES_PER_LINE 12
  197. #define SWR_MSTR_RD_BUF_LEN 8
  198. #define SWR_MSTR_WR_BUF_LEN 32
  199. static void swrm_copy_data_port_config(struct swr_master *master,
  200. u8 inactive_bank);
  201. static struct swr_mstr_ctrl *dbgswrm;
  202. static struct dentry *debugfs_swrm_dent;
  203. static struct dentry *debugfs_peek;
  204. static struct dentry *debugfs_poke;
  205. static struct dentry *debugfs_reg_dump;
  206. static unsigned int read_data;
  207. static bool swrm_is_msm_variant(int val)
  208. {
  209. return (val == SWRM_VERSION_1_3);
  210. }
  211. static int swrm_debug_open(struct inode *inode, struct file *file)
  212. {
  213. file->private_data = inode->i_private;
  214. return 0;
  215. }
  216. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  217. {
  218. char *token;
  219. int base, cnt;
  220. token = strsep(&buf, " ");
  221. for (cnt = 0; cnt < num_of_par; cnt++) {
  222. if (token) {
  223. if ((token[1] == 'x') || (token[1] == 'X'))
  224. base = 16;
  225. else
  226. base = 10;
  227. if (kstrtou32(token, base, &param1[cnt]) != 0)
  228. return -EINVAL;
  229. token = strsep(&buf, " ");
  230. } else
  231. return -EINVAL;
  232. }
  233. return 0;
  234. }
  235. static ssize_t swrm_reg_show(char __user *ubuf, size_t count,
  236. loff_t *ppos)
  237. {
  238. int i, reg_val, len;
  239. ssize_t total = 0;
  240. char tmp_buf[SWR_MSTR_MAX_BUF_LEN];
  241. if (!ubuf || !ppos)
  242. return 0;
  243. for (i = (((int) *ppos / BYTES_PER_LINE) + SWR_MSTR_START_REG_ADDR);
  244. i <= SWR_MSTR_MAX_REG_ADDR; i += 4) {
  245. reg_val = dbgswrm->read(dbgswrm->handle, i);
  246. len = snprintf(tmp_buf, 25, "0x%.3x: 0x%.2x\n", i, reg_val);
  247. if (len < 0) {
  248. pr_err("%s: fail to fill the buffer\n", __func__);
  249. total = -EFAULT;
  250. goto copy_err;
  251. }
  252. if ((total + len) >= count - 1)
  253. break;
  254. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  255. pr_err("%s: fail to copy reg dump\n", __func__);
  256. total = -EFAULT;
  257. goto copy_err;
  258. }
  259. *ppos += len;
  260. total += len;
  261. }
  262. copy_err:
  263. return total;
  264. }
  265. static ssize_t swrm_debug_read(struct file *file, char __user *ubuf,
  266. size_t count, loff_t *ppos)
  267. {
  268. char lbuf[SWR_MSTR_RD_BUF_LEN];
  269. char *access_str;
  270. ssize_t ret_cnt;
  271. if (!count || !file || !ppos || !ubuf)
  272. return -EINVAL;
  273. access_str = file->private_data;
  274. if (*ppos < 0)
  275. return -EINVAL;
  276. if (!strcmp(access_str, "swrm_peek")) {
  277. snprintf(lbuf, sizeof(lbuf), "0x%x\n", read_data);
  278. ret_cnt = simple_read_from_buffer(ubuf, count, ppos, lbuf,
  279. strnlen(lbuf, 7));
  280. } else if (!strcmp(access_str, "swrm_reg_dump")) {
  281. ret_cnt = swrm_reg_show(ubuf, count, ppos);
  282. } else {
  283. pr_err("%s: %s not permitted to read\n", __func__, access_str);
  284. ret_cnt = -EPERM;
  285. }
  286. return ret_cnt;
  287. }
  288. static ssize_t swrm_debug_write(struct file *filp,
  289. const char __user *ubuf, size_t cnt, loff_t *ppos)
  290. {
  291. char lbuf[SWR_MSTR_WR_BUF_LEN];
  292. int rc;
  293. u32 param[5];
  294. char *access_str;
  295. if (!filp || !ppos || !ubuf)
  296. return -EINVAL;
  297. access_str = filp->private_data;
  298. if (cnt > sizeof(lbuf) - 1)
  299. return -EINVAL;
  300. rc = copy_from_user(lbuf, ubuf, cnt);
  301. if (rc)
  302. return -EFAULT;
  303. lbuf[cnt] = '\0';
  304. if (!strcmp(access_str, "swrm_poke")) {
  305. /* write */
  306. rc = get_parameters(lbuf, param, 2);
  307. if ((param[0] <= SWR_MSTR_MAX_REG_ADDR) &&
  308. (param[1] <= 0xFFFFFFFF) &&
  309. (rc == 0))
  310. rc = dbgswrm->write(dbgswrm->handle, param[0],
  311. param[1]);
  312. else
  313. rc = -EINVAL;
  314. } else if (!strcmp(access_str, "swrm_peek")) {
  315. /* read */
  316. rc = get_parameters(lbuf, param, 1);
  317. if ((param[0] <= SWR_MSTR_MAX_REG_ADDR) && (rc == 0))
  318. read_data = dbgswrm->read(dbgswrm->handle, param[0]);
  319. else
  320. rc = -EINVAL;
  321. }
  322. if (rc == 0)
  323. rc = cnt;
  324. else
  325. pr_err("%s: rc = %d\n", __func__, rc);
  326. return rc;
  327. }
  328. static const struct file_operations swrm_debug_ops = {
  329. .open = swrm_debug_open,
  330. .write = swrm_debug_write,
  331. .read = swrm_debug_read,
  332. };
  333. static int swrm_set_ch_map(struct swr_mstr_ctrl *swrm, void *data)
  334. {
  335. struct swr_mstr_port *pinfo = (struct swr_mstr_port *)data;
  336. swrm->mstr_port = kzalloc(sizeof(struct swr_mstr_port), GFP_KERNEL);
  337. if (swrm->mstr_port == NULL)
  338. return -ENOMEM;
  339. swrm->mstr_port->num_port = pinfo->num_port;
  340. swrm->mstr_port->port = kzalloc((pinfo->num_port * sizeof(u8)),
  341. GFP_KERNEL);
  342. if (!swrm->mstr_port->port) {
  343. kfree(swrm->mstr_port);
  344. swrm->mstr_port = NULL;
  345. return -ENOMEM;
  346. }
  347. memcpy(swrm->mstr_port->port, pinfo->port, pinfo->num_port);
  348. return 0;
  349. }
  350. static bool swrm_is_port_en(struct swr_master *mstr)
  351. {
  352. return !!(mstr->num_port);
  353. }
  354. static int swrm_clk_request(struct swr_mstr_ctrl *swrm, bool enable)
  355. {
  356. if (!swrm->clk || !swrm->handle)
  357. return -EINVAL;
  358. if (enable) {
  359. swrm->clk_ref_count++;
  360. if (swrm->clk_ref_count == 1) {
  361. swrm->clk(swrm->handle, true);
  362. swrm->state = SWR_MSTR_UP;
  363. }
  364. } else if (--swrm->clk_ref_count == 0) {
  365. swrm->clk(swrm->handle, false);
  366. swrm->state = SWR_MSTR_DOWN;
  367. } else if (swrm->clk_ref_count < 0) {
  368. pr_err("%s: swrm clk count mismatch\n", __func__);
  369. swrm->clk_ref_count = 0;
  370. }
  371. return 0;
  372. }
  373. static int swrm_get_port_config(struct swr_master *master)
  374. {
  375. u32 ch_rate = 0;
  376. u32 num_ch = 0;
  377. int i, uc_idx;
  378. u32 portcount = 0;
  379. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  380. if (master->port[i].port_en) {
  381. ch_rate += master->port[i].ch_rate;
  382. num_ch += master->port[i].num_ch;
  383. portcount++;
  384. }
  385. }
  386. for (i = 0; i < ARRAY_SIZE(uc); i++) {
  387. if ((uc[i].num_port == portcount) &&
  388. (uc[i].num_ch == num_ch) &&
  389. (uc[i].chrate == ch_rate)) {
  390. uc_idx = i;
  391. break;
  392. }
  393. }
  394. if (i >= ARRAY_SIZE(uc)) {
  395. dev_err(&master->dev,
  396. "%s: usecase port:%d, num_ch:%d, chrate:%d not found\n",
  397. __func__, master->num_port, num_ch, ch_rate);
  398. return -EINVAL;
  399. }
  400. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  401. if (master->port[i].port_en) {
  402. master->port[i].sinterval = pp[uc_idx][i].si;
  403. master->port[i].offset1 = pp[uc_idx][i].off1;
  404. master->port[i].offset2 = pp[uc_idx][i].off2;
  405. }
  406. }
  407. return 0;
  408. }
  409. static int swrm_get_master_port(u8 *mstr_port_id, u8 slv_port_id)
  410. {
  411. int i;
  412. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  413. if (mstr_ports[i] == slv_port_id) {
  414. *mstr_port_id = i;
  415. return 0;
  416. }
  417. }
  418. return -EINVAL;
  419. }
  420. static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
  421. u8 dev_addr, u16 reg_addr)
  422. {
  423. u32 val;
  424. u8 id = *cmd_id;
  425. if (id != SWR_BROADCAST_CMD_ID) {
  426. if (id < 14)
  427. id += 1;
  428. else
  429. id = 0;
  430. *cmd_id = id;
  431. }
  432. val = SWR_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
  433. return val;
  434. }
  435. static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data,
  436. u8 dev_addr, u8 cmd_id, u16 reg_addr,
  437. u32 len)
  438. {
  439. u32 val;
  440. int ret = 0;
  441. val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
  442. ret = swrm->write(swrm->handle, SWRM_CMD_FIFO_RD_CMD, val);
  443. if (ret < 0) {
  444. dev_err(swrm->dev, "%s: reg 0x%x write failed, err:%d\n",
  445. __func__, val, ret);
  446. goto err;
  447. }
  448. *cmd_data = swrm->read(swrm->handle, SWRM_CMD_FIFO_RD_FIFO_ADDR);
  449. dev_dbg(swrm->dev,
  450. "%s: reg: 0x%x, cmd_id: 0x%x, dev_id: 0x%x, cmd_data: 0x%x\n",
  451. __func__, reg_addr, cmd_id, dev_addr, *cmd_data);
  452. err:
  453. return ret;
  454. }
  455. static int swrm_cmd_fifo_wr_cmd(struct swr_mstr_ctrl *swrm, u8 cmd_data,
  456. u8 dev_addr, u8 cmd_id, u16 reg_addr)
  457. {
  458. u32 val;
  459. int ret = 0;
  460. if (!cmd_id)
  461. val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
  462. dev_addr, reg_addr);
  463. else
  464. val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
  465. dev_addr, reg_addr);
  466. dev_dbg(swrm->dev,
  467. "%s: reg: 0x%x, cmd_id: 0x%x, dev_id: 0x%x, cmd_data: 0x%x\n",
  468. __func__, reg_addr, cmd_id, dev_addr, cmd_data);
  469. ret = swrm->write(swrm->handle, SWRM_CMD_FIFO_WR_CMD, val);
  470. if (ret < 0) {
  471. dev_err(swrm->dev, "%s: reg 0x%x write failed, err:%d\n",
  472. __func__, val, ret);
  473. goto err;
  474. }
  475. if (cmd_id == 0xF) {
  476. /*
  477. * sleep for 10ms for MSM soundwire variant to allow broadcast
  478. * command to complete.
  479. */
  480. if (swrm_is_msm_variant(swrm->version))
  481. usleep_range(10000, 10100);
  482. else
  483. wait_for_completion_timeout(&swrm->broadcast,
  484. (2 * HZ/10));
  485. }
  486. err:
  487. return ret;
  488. }
  489. static int swrm_read(struct swr_master *master, u8 dev_num, u16 reg_addr,
  490. void *buf, u32 len)
  491. {
  492. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  493. int ret = 0;
  494. int val;
  495. u8 *reg_val = (u8 *)buf;
  496. if (!swrm) {
  497. dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
  498. return -EINVAL;
  499. }
  500. if (dev_num)
  501. ret = swrm_cmd_fifo_rd_cmd(swrm, &val, dev_num, 0, reg_addr,
  502. len);
  503. else
  504. val = swrm->read(swrm->handle, reg_addr);
  505. if (!ret)
  506. *reg_val = (u8)val;
  507. pm_runtime_mark_last_busy(&swrm->pdev->dev);
  508. return ret;
  509. }
  510. static int swrm_write(struct swr_master *master, u8 dev_num, u16 reg_addr,
  511. const void *buf)
  512. {
  513. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  514. int ret = 0;
  515. u8 reg_val = *(u8 *)buf;
  516. if (!swrm) {
  517. dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
  518. return -EINVAL;
  519. }
  520. if (dev_num)
  521. ret = swrm_cmd_fifo_wr_cmd(swrm, reg_val, dev_num, 0, reg_addr);
  522. else
  523. ret = swrm->write(swrm->handle, reg_addr, reg_val);
  524. pm_runtime_mark_last_busy(&swrm->pdev->dev);
  525. return ret;
  526. }
  527. static int swrm_bulk_write(struct swr_master *master, u8 dev_num, void *reg,
  528. const void *buf, size_t len)
  529. {
  530. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  531. int ret = 0;
  532. int i;
  533. u32 *val;
  534. u32 *swr_fifo_reg;
  535. if (!swrm || !swrm->handle) {
  536. dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
  537. return -EINVAL;
  538. }
  539. if (len <= 0)
  540. return -EINVAL;
  541. if (dev_num) {
  542. swr_fifo_reg = kcalloc(len, sizeof(u32), GFP_KERNEL);
  543. if (!swr_fifo_reg) {
  544. ret = -ENOMEM;
  545. goto err;
  546. }
  547. val = kcalloc(len, sizeof(u32), GFP_KERNEL);
  548. if (!val) {
  549. ret = -ENOMEM;
  550. goto mem_fail;
  551. }
  552. for (i = 0; i < len; i++) {
  553. val[i] = swrm_get_packed_reg_val(&swrm->wcmd_id,
  554. ((u8 *)buf)[i],
  555. dev_num,
  556. ((u16 *)reg)[i]);
  557. swr_fifo_reg[i] = SWRM_CMD_FIFO_WR_CMD;
  558. }
  559. ret = swrm->bulk_write(swrm->handle, swr_fifo_reg, val, len);
  560. if (ret) {
  561. dev_err(&master->dev, "%s: bulk write failed\n",
  562. __func__);
  563. ret = -EINVAL;
  564. }
  565. } else {
  566. dev_err(&master->dev,
  567. "%s: No support of Bulk write for master regs\n",
  568. __func__);
  569. ret = -EINVAL;
  570. goto err;
  571. }
  572. kfree(val);
  573. mem_fail:
  574. kfree(swr_fifo_reg);
  575. err:
  576. pm_runtime_mark_last_busy(&swrm->pdev->dev);
  577. return ret;
  578. }
  579. static u8 get_inactive_bank_num(struct swr_mstr_ctrl *swrm)
  580. {
  581. return (swrm->read(swrm->handle, SWRM_MCP_STATUS) &
  582. SWRM_MCP_STATUS_BANK_NUM_MASK) ? 0 : 1;
  583. }
  584. static void enable_bank_switch(struct swr_mstr_ctrl *swrm, u8 bank,
  585. u8 row, u8 col)
  586. {
  587. /* apply div2 setting for inactive bank before bank switch */
  588. swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00,
  589. SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank));
  590. swrm_cmd_fifo_wr_cmd(swrm, ((row << 3) | col), 0xF, 0xF,
  591. SWRS_SCP_FRAME_CTRL_BANK(bank));
  592. }
  593. static struct swr_port_info *swrm_get_port(struct swr_master *master,
  594. u8 port_id)
  595. {
  596. int i;
  597. struct swr_port_info *port = NULL;
  598. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  599. port = &master->port[i];
  600. if (port->slave_port_id == port_id) {
  601. dev_dbg(&master->dev, "%s: port_id: %d, index: %d\n",
  602. __func__, port_id, i);
  603. return port;
  604. }
  605. }
  606. return NULL;
  607. }
  608. static struct swr_port_info *swrm_get_avail_port(struct swr_master *master)
  609. {
  610. int i;
  611. struct swr_port_info *port = NULL;
  612. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  613. port = &master->port[i];
  614. if (port->port_en)
  615. continue;
  616. dev_dbg(&master->dev, "%s: port_id: %d, index: %d\n",
  617. __func__, port->slave_port_id, i);
  618. return port;
  619. }
  620. return NULL;
  621. }
  622. static struct swr_port_info *swrm_get_enabled_port(struct swr_master *master,
  623. u8 port_id)
  624. {
  625. int i;
  626. struct swr_port_info *port = NULL;
  627. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  628. port = &master->port[i];
  629. if ((port->slave_port_id == port_id) && (port->port_en == true))
  630. break;
  631. }
  632. if (i == SWR_MSTR_PORT_LEN)
  633. port = NULL;
  634. return port;
  635. }
  636. static bool swrm_remove_from_group(struct swr_master *master)
  637. {
  638. struct swr_device *swr_dev;
  639. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  640. bool is_removed = false;
  641. if (!swrm)
  642. goto end;
  643. mutex_lock(&swrm->mlock);
  644. if ((swrm->num_rx_chs > 1) &&
  645. (swrm->num_rx_chs == swrm->num_cfg_devs)) {
  646. list_for_each_entry(swr_dev, &master->devices,
  647. dev_list) {
  648. swr_dev->group_id = SWR_GROUP_NONE;
  649. master->gr_sid = 0;
  650. }
  651. is_removed = true;
  652. }
  653. mutex_unlock(&swrm->mlock);
  654. end:
  655. return is_removed;
  656. }
  657. static void swrm_cleanup_disabled_data_ports(struct swr_master *master,
  658. u8 bank)
  659. {
  660. u32 value;
  661. struct swr_port_info *port;
  662. int i;
  663. int port_type;
  664. struct swrm_mports *mport, *mport_next = NULL;
  665. int port_disable_cnt = 0;
  666. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  667. if (!swrm) {
  668. pr_err("%s: swrm is null\n", __func__);
  669. return;
  670. }
  671. dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
  672. master->num_port);
  673. mport = list_first_entry_or_null(&swrm->mport_list,
  674. struct swrm_mports,
  675. list);
  676. if (!mport) {
  677. dev_err(swrm->dev, "%s: list is empty\n", __func__);
  678. return;
  679. }
  680. for (i = 0; i < master->num_port; i++) {
  681. port = swrm_get_port(master, mstr_ports[mport->id]);
  682. if (!port || port->ch_en)
  683. goto inc_loop;
  684. port_disable_cnt++;
  685. port_type = mstr_port_type[mport->id];
  686. value = ((port->ch_en)
  687. << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
  688. value |= ((port->offset2)
  689. << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
  690. value |= ((port->offset1)
  691. << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
  692. value |= port->sinterval;
  693. swrm->write(swrm->handle,
  694. SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank),
  695. value);
  696. swrm_cmd_fifo_wr_cmd(swrm, 0x00, port->dev_num, 0x00,
  697. SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank));
  698. dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
  699. __func__, mport->id,
  700. (SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank)), value);
  701. inc_loop:
  702. mport_next = list_next_entry(mport, list);
  703. if (port && !port->ch_en) {
  704. list_del(&mport->list);
  705. kfree(mport);
  706. }
  707. if (!mport_next) {
  708. dev_err(swrm->dev, "%s: end of list\n", __func__);
  709. break;
  710. }
  711. mport = mport_next;
  712. }
  713. master->num_port -= port_disable_cnt;
  714. dev_dbg(swrm->dev, "%s:disable ports: %d, active ports (rem): %d\n",
  715. __func__, port_disable_cnt, master->num_port);
  716. }
  717. static int swrm_slvdev_datapath_control(struct swr_master *master,
  718. bool enable)
  719. {
  720. u8 bank;
  721. u32 value, n_col;
  722. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  723. int mask = (SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK |
  724. SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK |
  725. SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_BMSK);
  726. u8 inactive_bank;
  727. if (!swrm) {
  728. pr_err("%s: swrm is null\n", __func__);
  729. return 0;
  730. }
  731. bank = get_inactive_bank_num(swrm);
  732. dev_dbg(swrm->dev, "%s: enable: %d, cfg_devs: %d\n",
  733. __func__, enable, swrm->num_cfg_devs);
  734. if (enable) {
  735. /* set Row = 48 and col = 16 */
  736. n_col = SWR_MAX_COL;
  737. } else {
  738. /*
  739. * Do not change to 48x2 if number of channels configured
  740. * as stereo and if disable datapath is called for the
  741. * first slave device
  742. */
  743. if (swrm->num_cfg_devs > 0)
  744. n_col = SWR_MAX_COL;
  745. else
  746. n_col = SWR_MIN_COL;
  747. /*
  748. * All ports are already disabled, no need to perform
  749. * bank-switch and copy operation. This case can arise
  750. * when speaker channels are enabled in stereo mode with
  751. * BROADCAST and disabled in GROUP_NONE
  752. */
  753. if (master->num_port == 0)
  754. return 0;
  755. }
  756. value = swrm->read(swrm->handle, SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank));
  757. value &= (~mask);
  758. value |= ((0 << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
  759. (n_col << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
  760. (0 << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
  761. swrm->write(swrm->handle, SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank), value);
  762. dev_dbg(swrm->dev, "%s: regaddr: 0x%x, value: 0x%x\n", __func__,
  763. SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank), value);
  764. enable_bank_switch(swrm, bank, SWR_MAX_ROW, n_col);
  765. inactive_bank = bank ? 0 : 1;
  766. if (enable)
  767. swrm_copy_data_port_config(master, inactive_bank);
  768. else
  769. swrm_cleanup_disabled_data_ports(master, inactive_bank);
  770. if (!swrm_is_port_en(master)) {
  771. dev_dbg(&master->dev, "%s: pm_runtime auto suspend triggered\n",
  772. __func__);
  773. pm_runtime_mark_last_busy(&swrm->pdev->dev);
  774. pm_runtime_put_autosuspend(&swrm->pdev->dev);
  775. }
  776. return 0;
  777. }
  778. static void swrm_apply_port_config(struct swr_master *master)
  779. {
  780. u8 bank;
  781. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  782. if (!swrm) {
  783. pr_err("%s: Invalid handle to swr controller\n",
  784. __func__);
  785. return;
  786. }
  787. bank = get_inactive_bank_num(swrm);
  788. dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n",
  789. __func__, bank, master->num_port);
  790. swrm_copy_data_port_config(master, bank);
  791. }
  792. static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
  793. {
  794. u32 value;
  795. struct swr_port_info *port;
  796. int i;
  797. int port_type;
  798. struct swrm_mports *mport;
  799. u32 reg[SWRM_MAX_PORT_REG];
  800. u32 val[SWRM_MAX_PORT_REG];
  801. int len = 0;
  802. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  803. if (!swrm) {
  804. pr_err("%s: swrm is null\n", __func__);
  805. return;
  806. }
  807. dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
  808. master->num_port);
  809. mport = list_first_entry_or_null(&swrm->mport_list,
  810. struct swrm_mports,
  811. list);
  812. if (!mport) {
  813. dev_err(swrm->dev, "%s: list is empty\n", __func__);
  814. return;
  815. }
  816. for (i = 0; i < master->num_port; i++) {
  817. port = swrm_get_enabled_port(master, mstr_ports[mport->id]);
  818. if (!port)
  819. continue;
  820. port_type = mstr_port_type[mport->id];
  821. if (!port->dev_num || (port->dev_num > master->num_dev)) {
  822. dev_dbg(swrm->dev, "%s: invalid device id = %d\n",
  823. __func__, port->dev_num);
  824. continue;
  825. }
  826. value = ((port->ch_en)
  827. << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
  828. value |= ((port->offset2)
  829. << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
  830. value |= ((port->offset1)
  831. << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
  832. value |= port->sinterval;
  833. reg[len] = SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank);
  834. val[len++] = value;
  835. dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
  836. __func__, mport->id,
  837. (SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank)), value);
  838. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  839. val[len++] = SWR_REG_VAL_PACK(port->ch_en, port->dev_num, 0x00,
  840. SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank));
  841. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  842. val[len++] = SWR_REG_VAL_PACK(port->sinterval,
  843. port->dev_num, 0x00,
  844. SWRS_DP_SAMPLE_CONTROL_1_BANK(port_type, bank));
  845. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  846. val[len++] = SWR_REG_VAL_PACK(port->offset1,
  847. port->dev_num, 0x00,
  848. SWRS_DP_OFFSET_CONTROL_1_BANK(port_type, bank));
  849. if (port_type != 0) {
  850. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  851. val[len++] = SWR_REG_VAL_PACK(port->offset2,
  852. port->dev_num, 0x00,
  853. SWRS_DP_OFFSET_CONTROL_2_BANK(port_type,
  854. bank));
  855. }
  856. mport = list_next_entry(mport, list);
  857. if (!mport) {
  858. dev_err(swrm->dev, "%s: end of list\n", __func__);
  859. break;
  860. }
  861. }
  862. swrm->bulk_write(swrm->handle, reg, val, len);
  863. }
  864. static int swrm_connect_port(struct swr_master *master,
  865. struct swr_params *portinfo)
  866. {
  867. int i;
  868. struct swr_port_info *port;
  869. int ret = 0;
  870. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  871. struct swrm_mports *mport;
  872. struct list_head *ptr, *next;
  873. dev_dbg(&master->dev, "%s: enter\n", __func__);
  874. if (!portinfo)
  875. return -EINVAL;
  876. if (!swrm) {
  877. dev_err(&master->dev,
  878. "%s: Invalid handle to swr controller\n",
  879. __func__);
  880. return -EINVAL;
  881. }
  882. mutex_lock(&swrm->mlock);
  883. if (!swrm_is_port_en(master))
  884. pm_runtime_get_sync(&swrm->pdev->dev);
  885. for (i = 0; i < portinfo->num_port; i++) {
  886. mport = kzalloc(sizeof(struct swrm_mports), GFP_KERNEL);
  887. if (!mport) {
  888. ret = -ENOMEM;
  889. goto mem_fail;
  890. }
  891. ret = swrm_get_master_port(&mport->id,
  892. portinfo->port_id[i]);
  893. if (ret < 0) {
  894. dev_err(&master->dev,
  895. "%s: mstr portid for slv port %d not found\n",
  896. __func__, portinfo->port_id[i]);
  897. goto port_fail;
  898. }
  899. port = swrm_get_avail_port(master);
  900. if (!port) {
  901. dev_err(&master->dev,
  902. "%s: avail ports not found!\n", __func__);
  903. goto port_fail;
  904. }
  905. list_add(&mport->list, &swrm->mport_list);
  906. port->dev_num = portinfo->dev_num;
  907. port->slave_port_id = portinfo->port_id[i];
  908. port->num_ch = portinfo->num_ch[i];
  909. port->ch_rate = portinfo->ch_rate[i];
  910. port->ch_en = portinfo->ch_en[i];
  911. port->port_en = true;
  912. dev_dbg(&master->dev,
  913. "%s: mstr port %d, slv port %d ch_rate %d num_ch %d\n",
  914. __func__, mport->id, port->slave_port_id, port->ch_rate,
  915. port->num_ch);
  916. }
  917. master->num_port += portinfo->num_port;
  918. if (master->num_port >= SWR_MSTR_PORT_LEN)
  919. master->num_port = SWR_MSTR_PORT_LEN;
  920. swrm_get_port_config(master);
  921. swr_port_response(master, portinfo->tid);
  922. swrm->num_cfg_devs += 1;
  923. dev_dbg(&master->dev, "%s: cfg_devs: %d, rx_chs: %d\n",
  924. __func__, swrm->num_cfg_devs, swrm->num_rx_chs);
  925. if (swrm->num_rx_chs > 1) {
  926. if (swrm->num_rx_chs == swrm->num_cfg_devs)
  927. swrm_apply_port_config(master);
  928. } else {
  929. swrm_apply_port_config(master);
  930. }
  931. mutex_unlock(&swrm->mlock);
  932. return 0;
  933. port_fail:
  934. kfree(mport);
  935. mem_fail:
  936. list_for_each_safe(ptr, next, &swrm->mport_list) {
  937. mport = list_entry(ptr, struct swrm_mports, list);
  938. for (i = 0; i < portinfo->num_port; i++) {
  939. if (portinfo->port_id[i] == mstr_ports[mport->id]) {
  940. port = swrm_get_port(master,
  941. portinfo->port_id[i]);
  942. if (port)
  943. port->ch_en = false;
  944. list_del(&mport->list);
  945. kfree(mport);
  946. break;
  947. }
  948. }
  949. }
  950. mutex_unlock(&swrm->mlock);
  951. return ret;
  952. }
  953. static int swrm_disconnect_port(struct swr_master *master,
  954. struct swr_params *portinfo)
  955. {
  956. int i;
  957. struct swr_port_info *port;
  958. u8 bank;
  959. u32 value;
  960. int ret = 0;
  961. u8 mport_id = 0;
  962. int port_type = 0;
  963. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  964. if (!swrm) {
  965. dev_err(&master->dev,
  966. "%s: Invalid handle to swr controller\n",
  967. __func__);
  968. return -EINVAL;
  969. }
  970. if (!portinfo) {
  971. dev_err(&master->dev, "%s: portinfo is NULL\n", __func__);
  972. return -EINVAL;
  973. }
  974. mutex_lock(&swrm->mlock);
  975. bank = get_inactive_bank_num(swrm);
  976. for (i = 0; i < portinfo->num_port; i++) {
  977. ret = swrm_get_master_port(&mport_id,
  978. portinfo->port_id[i]);
  979. if (ret < 0) {
  980. dev_err(&master->dev,
  981. "%s: mstr portid for slv port %d not found\n",
  982. __func__, portinfo->port_id[i]);
  983. mutex_unlock(&swrm->mlock);
  984. return -EINVAL;
  985. }
  986. port = swrm_get_enabled_port(master, portinfo->port_id[i]);
  987. if (!port) {
  988. dev_dbg(&master->dev, "%s: port %d already disabled\n",
  989. __func__, portinfo->port_id[i]);
  990. continue;
  991. }
  992. port_type = mstr_port_type[mport_id];
  993. port->dev_num = portinfo->dev_num;
  994. port->port_en = false;
  995. port->ch_en = 0;
  996. value = port->ch_en << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT;
  997. value |= (port->offset2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
  998. value |= (port->offset1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
  999. value |= port->sinterval;
  1000. swrm->write(swrm->handle,
  1001. SWRM_DP_PORT_CTRL_BANK((mport_id+1), bank),
  1002. value);
  1003. swrm_cmd_fifo_wr_cmd(swrm, 0x00, port->dev_num, 0x00,
  1004. SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank));
  1005. }
  1006. swr_port_response(master, portinfo->tid);
  1007. swrm->num_cfg_devs -= 1;
  1008. dev_dbg(&master->dev, "%s: cfg_devs: %d, rx_chs: %d, active ports: %d\n",
  1009. __func__, swrm->num_cfg_devs, swrm->num_rx_chs,
  1010. master->num_port);
  1011. mutex_unlock(&swrm->mlock);
  1012. return 0;
  1013. }
  1014. static int swrm_check_slave_change_status(struct swr_mstr_ctrl *swrm,
  1015. int status, u8 *devnum)
  1016. {
  1017. int i;
  1018. int new_sts = status;
  1019. int ret = SWR_NOT_PRESENT;
  1020. if (status != swrm->slave_status) {
  1021. for (i = 0; i < (swrm->master.num_dev + 1); i++) {
  1022. if ((status & SWRM_MCP_SLV_STATUS_MASK) !=
  1023. (swrm->slave_status & SWRM_MCP_SLV_STATUS_MASK)) {
  1024. ret = (status & SWRM_MCP_SLV_STATUS_MASK);
  1025. *devnum = i;
  1026. break;
  1027. }
  1028. status >>= 2;
  1029. swrm->slave_status >>= 2;
  1030. }
  1031. swrm->slave_status = new_sts;
  1032. }
  1033. return ret;
  1034. }
  1035. static irqreturn_t swr_mstr_interrupt(int irq, void *dev)
  1036. {
  1037. struct swr_mstr_ctrl *swrm = dev;
  1038. u32 value, intr_sts;
  1039. int status, chg_sts, i;
  1040. u8 devnum = 0;
  1041. int ret = IRQ_HANDLED;
  1042. mutex_lock(&swrm->reslock);
  1043. swrm_clk_request(swrm, true);
  1044. mutex_unlock(&swrm->reslock);
  1045. intr_sts = swrm->read(swrm->handle, SWRM_INTERRUPT_STATUS);
  1046. intr_sts &= SWRM_INTERRUPT_STATUS_RMSK;
  1047. for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
  1048. value = intr_sts & (1 << i);
  1049. if (!value)
  1050. continue;
  1051. swrm->write(swrm->handle, SWRM_INTERRUPT_CLEAR, value);
  1052. switch (value) {
  1053. case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
  1054. dev_dbg(swrm->dev, "SWR slave pend irq\n");
  1055. break;
  1056. case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
  1057. dev_dbg(swrm->dev, "SWR new slave attached\n");
  1058. break;
  1059. case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
  1060. status = swrm->read(swrm->handle, SWRM_MCP_SLV_STATUS);
  1061. if (status == swrm->slave_status) {
  1062. dev_dbg(swrm->dev,
  1063. "%s: No change in slave status: %d\n",
  1064. __func__, status);
  1065. break;
  1066. }
  1067. chg_sts = swrm_check_slave_change_status(swrm, status,
  1068. &devnum);
  1069. switch (chg_sts) {
  1070. case SWR_NOT_PRESENT:
  1071. dev_dbg(swrm->dev, "device %d got detached\n",
  1072. devnum);
  1073. break;
  1074. case SWR_ATTACHED_OK:
  1075. dev_dbg(swrm->dev, "device %d got attached\n",
  1076. devnum);
  1077. break;
  1078. case SWR_ALERT:
  1079. dev_dbg(swrm->dev,
  1080. "device %d has pending interrupt\n",
  1081. devnum);
  1082. break;
  1083. }
  1084. break;
  1085. case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
  1086. dev_err_ratelimited(swrm->dev, "SWR bus clash detected\n");
  1087. break;
  1088. case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
  1089. dev_dbg(swrm->dev, "SWR read FIFO overflow\n");
  1090. break;
  1091. case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
  1092. dev_dbg(swrm->dev, "SWR read FIFO underflow\n");
  1093. break;
  1094. case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
  1095. dev_dbg(swrm->dev, "SWR write FIFO overflow\n");
  1096. break;
  1097. case SWRM_INTERRUPT_STATUS_CMD_ERROR:
  1098. value = swrm->read(swrm->handle, SWRM_CMD_FIFO_STATUS);
  1099. dev_err_ratelimited(swrm->dev,
  1100. "SWR CMD error, fifo status 0x%x, flushing fifo\n",
  1101. value);
  1102. swrm->write(swrm->handle, SWRM_CMD_FIFO_CMD, 0x1);
  1103. break;
  1104. case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
  1105. dev_dbg(swrm->dev, "SWR Port collision detected\n");
  1106. break;
  1107. case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
  1108. dev_dbg(swrm->dev, "SWR read enable valid mismatch\n");
  1109. break;
  1110. case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
  1111. complete(&swrm->broadcast);
  1112. dev_dbg(swrm->dev, "SWR cmd id finished\n");
  1113. break;
  1114. case SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED:
  1115. break;
  1116. case SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED:
  1117. break;
  1118. case SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL:
  1119. break;
  1120. case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED:
  1121. complete(&swrm->reset);
  1122. break;
  1123. case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED:
  1124. break;
  1125. default:
  1126. dev_err_ratelimited(swrm->dev, "SWR unknown interrupt\n");
  1127. ret = IRQ_NONE;
  1128. break;
  1129. }
  1130. }
  1131. mutex_lock(&swrm->reslock);
  1132. swrm_clk_request(swrm, false);
  1133. mutex_unlock(&swrm->reslock);
  1134. return ret;
  1135. }
  1136. static int swrm_get_device_status(struct swr_mstr_ctrl *swrm, u8 devnum)
  1137. {
  1138. u32 val;
  1139. swrm->slave_status = swrm->read(swrm->handle, SWRM_MCP_SLV_STATUS);
  1140. val = (swrm->slave_status >> (devnum * 2));
  1141. val &= SWRM_MCP_SLV_STATUS_MASK;
  1142. return val;
  1143. }
  1144. static int swrm_get_logical_dev_num(struct swr_master *mstr, u64 dev_id,
  1145. u8 *dev_num)
  1146. {
  1147. int i;
  1148. u64 id = 0;
  1149. int ret = -EINVAL;
  1150. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
  1151. struct swr_device *swr_dev;
  1152. u32 num_dev = 0;
  1153. if (!swrm) {
  1154. pr_err("%s: Invalid handle to swr controller\n",
  1155. __func__);
  1156. return ret;
  1157. }
  1158. if (swrm->num_dev)
  1159. num_dev = swrm->num_dev;
  1160. else
  1161. num_dev = mstr->num_dev;
  1162. pm_runtime_get_sync(&swrm->pdev->dev);
  1163. for (i = 1; i < (num_dev + 1); i++) {
  1164. id = ((u64)(swrm->read(swrm->handle,
  1165. SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i))) << 32);
  1166. id |= swrm->read(swrm->handle,
  1167. SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i));
  1168. /*
  1169. * As pm_runtime_get_sync() brings all slaves out of reset
  1170. * update logical device number for all slaves.
  1171. */
  1172. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  1173. if (swr_dev->addr == (id & SWR_DEV_ID_MASK)) {
  1174. u32 status = swrm_get_device_status(swrm, i);
  1175. if ((status == 0x01) || (status == 0x02)) {
  1176. swr_dev->dev_num = i;
  1177. if ((id & SWR_DEV_ID_MASK) == dev_id) {
  1178. *dev_num = i;
  1179. ret = 0;
  1180. }
  1181. dev_dbg(swrm->dev, "%s: devnum %d is assigned for dev addr %lx\n",
  1182. __func__, i, swr_dev->addr);
  1183. }
  1184. }
  1185. }
  1186. }
  1187. if (ret)
  1188. dev_err(swrm->dev, "%s: device 0x%llx is not ready\n",
  1189. __func__, dev_id);
  1190. pm_runtime_mark_last_busy(&swrm->pdev->dev);
  1191. pm_runtime_put_autosuspend(&swrm->pdev->dev);
  1192. return ret;
  1193. }
  1194. static int swrm_master_init(struct swr_mstr_ctrl *swrm)
  1195. {
  1196. int ret = 0;
  1197. u32 val;
  1198. u8 row_ctrl = SWR_MAX_ROW;
  1199. u8 col_ctrl = SWR_MIN_COL;
  1200. u8 ssp_period = 1;
  1201. u8 retry_cmd_num = 3;
  1202. u32 reg[SWRM_MAX_INIT_REG];
  1203. u32 value[SWRM_MAX_INIT_REG];
  1204. int len = 0;
  1205. /* Clear Rows and Cols */
  1206. val = ((row_ctrl << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
  1207. (col_ctrl << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
  1208. (ssp_period << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
  1209. reg[len] = SWRM_MCP_FRAME_CTRL_BANK_ADDR(0);
  1210. value[len++] = val;
  1211. /* Set Auto enumeration flag */
  1212. reg[len] = SWRM_ENUMERATOR_CFG_ADDR;
  1213. value[len++] = 1;
  1214. /* Mask soundwire interrupts */
  1215. reg[len] = SWRM_INTERRUPT_MASK_ADDR;
  1216. value[len++] = 0x1FFFD;
  1217. /* Configure No pings */
  1218. val = swrm->read(swrm->handle, SWRM_MCP_CFG_ADDR);
  1219. val &= ~SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK;
  1220. val |= (0x1f << SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT);
  1221. reg[len] = SWRM_MCP_CFG_ADDR;
  1222. value[len++] = val;
  1223. /* Configure number of retries of a read/write cmd */
  1224. val = (retry_cmd_num << SWRM_CMD_FIFO_CFG_NUM_OF_CMD_RETRY_SHFT);
  1225. reg[len] = SWRM_CMD_FIFO_CFG_ADDR;
  1226. value[len++] = val;
  1227. /* Set IRQ to PULSE */
  1228. reg[len] = SWRM_COMP_CFG_ADDR;
  1229. value[len++] = 0x02;
  1230. reg[len] = SWRM_COMP_CFG_ADDR;
  1231. value[len++] = 0x03;
  1232. reg[len] = SWRM_INTERRUPT_CLEAR;
  1233. value[len++] = 0x08;
  1234. swrm->bulk_write(swrm->handle, reg, value, len);
  1235. return ret;
  1236. }
  1237. static int swrm_event_notify(struct notifier_block *self,
  1238. unsigned long action, void *data)
  1239. {
  1240. struct swr_mstr_ctrl *swrm = container_of(self, struct swr_mstr_ctrl,
  1241. event_notifier);
  1242. if (!swrm || !swrm->pdev) {
  1243. pr_err("%s: swrm or pdev is NULL\n", __func__);
  1244. return -EINVAL;
  1245. }
  1246. if (action != MSM_AUD_DC_EVENT) {
  1247. dev_err(&swrm->pdev->dev, "%s: invalid event type: %lu\n", __func__, action);
  1248. return -EINVAL;
  1249. }
  1250. schedule_work(&(swrm->dc_presence_work));
  1251. return 0;
  1252. }
  1253. static void swrm_notify_work_fn(struct work_struct *work)
  1254. {
  1255. struct swr_mstr_ctrl *swrm = container_of(work, struct swr_mstr_ctrl,
  1256. dc_presence_work);
  1257. swrm_wcd_notify(swrm->pdev, SWR_DEVICE_DOWN, NULL);
  1258. }
  1259. static int swrm_probe(struct platform_device *pdev)
  1260. {
  1261. struct swr_mstr_ctrl *swrm;
  1262. struct swr_ctrl_platform_data *pdata;
  1263. int ret;
  1264. /* Allocate soundwire master driver structure */
  1265. swrm = kzalloc(sizeof(struct swr_mstr_ctrl), GFP_KERNEL);
  1266. if (!swrm) {
  1267. ret = -ENOMEM;
  1268. goto err_memory_fail;
  1269. }
  1270. swrm->dev = &pdev->dev;
  1271. swrm->pdev = pdev;
  1272. platform_set_drvdata(pdev, swrm);
  1273. swr_set_ctrl_data(&swrm->master, swrm);
  1274. pdata = dev_get_platdata(&pdev->dev);
  1275. if (!pdata) {
  1276. dev_err(&pdev->dev, "%s: pdata from parent is NULL\n",
  1277. __func__);
  1278. ret = -EINVAL;
  1279. goto err_pdata_fail;
  1280. }
  1281. swrm->handle = (void *)pdata->handle;
  1282. if (!swrm->handle) {
  1283. dev_err(&pdev->dev, "%s: swrm->handle is NULL\n",
  1284. __func__);
  1285. ret = -EINVAL;
  1286. goto err_pdata_fail;
  1287. }
  1288. swrm->read = pdata->read;
  1289. if (!swrm->read) {
  1290. dev_err(&pdev->dev, "%s: swrm->read is NULL\n",
  1291. __func__);
  1292. ret = -EINVAL;
  1293. goto err_pdata_fail;
  1294. }
  1295. swrm->write = pdata->write;
  1296. if (!swrm->write) {
  1297. dev_err(&pdev->dev, "%s: swrm->write is NULL\n",
  1298. __func__);
  1299. ret = -EINVAL;
  1300. goto err_pdata_fail;
  1301. }
  1302. swrm->bulk_write = pdata->bulk_write;
  1303. if (!swrm->bulk_write) {
  1304. dev_err(&pdev->dev, "%s: swrm->bulk_write is NULL\n",
  1305. __func__);
  1306. ret = -EINVAL;
  1307. goto err_pdata_fail;
  1308. }
  1309. swrm->clk = pdata->clk;
  1310. if (!swrm->clk) {
  1311. dev_err(&pdev->dev, "%s: swrm->clk is NULL\n",
  1312. __func__);
  1313. ret = -EINVAL;
  1314. goto err_pdata_fail;
  1315. }
  1316. swrm->reg_irq = pdata->reg_irq;
  1317. if (!swrm->reg_irq) {
  1318. dev_err(&pdev->dev, "%s: swrm->reg_irq is NULL\n",
  1319. __func__);
  1320. ret = -EINVAL;
  1321. goto err_pdata_fail;
  1322. }
  1323. swrm->master.read = swrm_read;
  1324. swrm->master.write = swrm_write;
  1325. swrm->master.bulk_write = swrm_bulk_write;
  1326. swrm->master.get_logical_dev_num = swrm_get_logical_dev_num;
  1327. swrm->master.connect_port = swrm_connect_port;
  1328. swrm->master.disconnect_port = swrm_disconnect_port;
  1329. swrm->master.slvdev_datapath_control = swrm_slvdev_datapath_control;
  1330. swrm->master.remove_from_group = swrm_remove_from_group;
  1331. swrm->master.dev.parent = &pdev->dev;
  1332. swrm->master.dev.of_node = pdev->dev.of_node;
  1333. swrm->master.num_port = 0;
  1334. swrm->num_enum_slaves = 0;
  1335. swrm->rcmd_id = 0;
  1336. swrm->wcmd_id = 0;
  1337. swrm->slave_status = 0;
  1338. swrm->num_rx_chs = 0;
  1339. swrm->clk_ref_count = 0;
  1340. swrm->state = SWR_MSTR_RESUME;
  1341. init_completion(&swrm->reset);
  1342. init_completion(&swrm->broadcast);
  1343. mutex_init(&swrm->mlock);
  1344. INIT_LIST_HEAD(&swrm->mport_list);
  1345. mutex_init(&swrm->reslock);
  1346. mutex_init(&swrm->force_down_lock);
  1347. ret = of_property_read_u32(swrm->dev->of_node, "qcom,swr-num-dev",
  1348. &swrm->num_dev);
  1349. if (ret)
  1350. dev_dbg(&pdev->dev, "%s: Looking up %s property failed\n",
  1351. __func__, "qcom,swr-num-dev");
  1352. else {
  1353. if (swrm->num_dev > SWR_MAX_SLAVE_DEVICES) {
  1354. dev_err(&pdev->dev, "%s: num_dev %d > max limit %d\n",
  1355. __func__, swrm->num_dev, SWR_MAX_SLAVE_DEVICES);
  1356. ret = -EINVAL;
  1357. goto err_pdata_fail;
  1358. }
  1359. }
  1360. ret = swrm->reg_irq(swrm->handle, swr_mstr_interrupt, swrm,
  1361. SWR_IRQ_REGISTER);
  1362. if (ret) {
  1363. dev_err(&pdev->dev, "%s: IRQ register failed ret %d\n",
  1364. __func__, ret);
  1365. goto err_irq_fail;
  1366. }
  1367. ret = swr_register_master(&swrm->master);
  1368. if (ret) {
  1369. dev_err(&pdev->dev, "%s: error adding swr master\n", __func__);
  1370. goto err_mstr_fail;
  1371. }
  1372. /* Add devices registered with board-info as the
  1373. * controller will be up now
  1374. */
  1375. swr_master_add_boarddevices(&swrm->master);
  1376. mutex_lock(&swrm->mlock);
  1377. swrm_clk_request(swrm, true);
  1378. ret = swrm_master_init(swrm);
  1379. if (ret < 0) {
  1380. dev_err(&pdev->dev,
  1381. "%s: Error in master Initializaiton, err %d\n",
  1382. __func__, ret);
  1383. mutex_unlock(&swrm->mlock);
  1384. goto err_mstr_fail;
  1385. }
  1386. swrm->version = swrm->read(swrm->handle, SWRM_COMP_HW_VERSION);
  1387. mutex_unlock(&swrm->mlock);
  1388. if (pdev->dev.of_node)
  1389. of_register_swr_devices(&swrm->master);
  1390. dbgswrm = swrm;
  1391. debugfs_swrm_dent = debugfs_create_dir(dev_name(&pdev->dev), 0);
  1392. if (!IS_ERR(debugfs_swrm_dent)) {
  1393. debugfs_peek = debugfs_create_file("swrm_peek",
  1394. S_IFREG | 0444, debugfs_swrm_dent,
  1395. (void *) "swrm_peek", &swrm_debug_ops);
  1396. debugfs_poke = debugfs_create_file("swrm_poke",
  1397. S_IFREG | 0444, debugfs_swrm_dent,
  1398. (void *) "swrm_poke", &swrm_debug_ops);
  1399. debugfs_reg_dump = debugfs_create_file("swrm_reg_dump",
  1400. S_IFREG | 0444, debugfs_swrm_dent,
  1401. (void *) "swrm_reg_dump",
  1402. &swrm_debug_ops);
  1403. }
  1404. pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer);
  1405. pm_runtime_use_autosuspend(&pdev->dev);
  1406. pm_runtime_set_active(&pdev->dev);
  1407. pm_runtime_enable(&pdev->dev);
  1408. pm_runtime_mark_last_busy(&pdev->dev);
  1409. INIT_WORK(&swrm->dc_presence_work, swrm_notify_work_fn);
  1410. swrm->event_notifier.notifier_call = swrm_event_notify;
  1411. msm_aud_evt_register_client(&swrm->event_notifier);
  1412. return 0;
  1413. err_mstr_fail:
  1414. swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
  1415. swrm, SWR_IRQ_FREE);
  1416. err_irq_fail:
  1417. mutex_destroy(&swrm->mlock);
  1418. mutex_destroy(&swrm->reslock);
  1419. mutex_destroy(&swrm->force_down_lock);
  1420. err_pdata_fail:
  1421. kfree(swrm);
  1422. err_memory_fail:
  1423. return ret;
  1424. }
  1425. static int swrm_remove(struct platform_device *pdev)
  1426. {
  1427. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  1428. if (swrm->reg_irq)
  1429. swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
  1430. swrm, SWR_IRQ_FREE);
  1431. if (swrm->mstr_port) {
  1432. kfree(swrm->mstr_port->port);
  1433. swrm->mstr_port->port = NULL;
  1434. kfree(swrm->mstr_port);
  1435. swrm->mstr_port = NULL;
  1436. }
  1437. pm_runtime_disable(&pdev->dev);
  1438. pm_runtime_set_suspended(&pdev->dev);
  1439. swr_unregister_master(&swrm->master);
  1440. msm_aud_evt_unregister_client(&swrm->event_notifier);
  1441. mutex_destroy(&swrm->mlock);
  1442. mutex_destroy(&swrm->reslock);
  1443. mutex_destroy(&swrm->force_down_lock);
  1444. kfree(swrm);
  1445. return 0;
  1446. }
  1447. static int swrm_clk_pause(struct swr_mstr_ctrl *swrm)
  1448. {
  1449. u32 val;
  1450. dev_dbg(swrm->dev, "%s: state: %d\n", __func__, swrm->state);
  1451. swrm->write(swrm->handle, SWRM_INTERRUPT_MASK_ADDR, 0x1FDFD);
  1452. val = swrm->read(swrm->handle, SWRM_MCP_CFG_ADDR);
  1453. val |= SWRM_MCP_CFG_BUS_CLK_PAUSE_BMSK;
  1454. swrm->write(swrm->handle, SWRM_MCP_CFG_ADDR, val);
  1455. swrm->state = SWR_MSTR_PAUSE;
  1456. return 0;
  1457. }
  1458. #ifdef CONFIG_PM
  1459. static int swrm_runtime_resume(struct device *dev)
  1460. {
  1461. struct platform_device *pdev = to_platform_device(dev);
  1462. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  1463. int ret = 0;
  1464. struct swr_master *mstr = &swrm->master;
  1465. struct swr_device *swr_dev;
  1466. dev_dbg(dev, "%s: pm_runtime: resume, state:%d\n",
  1467. __func__, swrm->state);
  1468. mutex_lock(&swrm->reslock);
  1469. if ((swrm->state == SWR_MSTR_PAUSE) ||
  1470. (swrm->state == SWR_MSTR_DOWN)) {
  1471. if (swrm->state == SWR_MSTR_DOWN) {
  1472. if (swrm_clk_request(swrm, true))
  1473. goto exit;
  1474. }
  1475. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  1476. ret = swr_device_up(swr_dev);
  1477. if (ret) {
  1478. dev_err(dev,
  1479. "%s: failed to wakeup swr dev %d\n",
  1480. __func__, swr_dev->dev_num);
  1481. swrm_clk_request(swrm, false);
  1482. goto exit;
  1483. }
  1484. }
  1485. swrm->write(swrm->handle, SWRM_COMP_SW_RESET, 0x01);
  1486. swrm->write(swrm->handle, SWRM_COMP_SW_RESET, 0x01);
  1487. swrm_master_init(swrm);
  1488. }
  1489. exit:
  1490. pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer);
  1491. mutex_unlock(&swrm->reslock);
  1492. return ret;
  1493. }
  1494. static int swrm_runtime_suspend(struct device *dev)
  1495. {
  1496. struct platform_device *pdev = to_platform_device(dev);
  1497. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  1498. int ret = 0;
  1499. struct swr_master *mstr = &swrm->master;
  1500. struct swr_device *swr_dev;
  1501. int current_state = 0;
  1502. dev_dbg(dev, "%s: pm_runtime: suspend state: %d\n",
  1503. __func__, swrm->state);
  1504. mutex_lock(&swrm->reslock);
  1505. mutex_lock(&swrm->force_down_lock);
  1506. current_state = swrm->state;
  1507. mutex_unlock(&swrm->force_down_lock);
  1508. if ((current_state == SWR_MSTR_RESUME) ||
  1509. (current_state == SWR_MSTR_UP) ||
  1510. (current_state == SWR_MSTR_SSR)) {
  1511. if ((current_state != SWR_MSTR_SSR) &&
  1512. swrm_is_port_en(&swrm->master)) {
  1513. dev_dbg(dev, "%s ports are enabled\n", __func__);
  1514. ret = -EBUSY;
  1515. goto exit;
  1516. }
  1517. swrm_clk_pause(swrm);
  1518. swrm->write(swrm->handle, SWRM_COMP_CFG_ADDR, 0x00);
  1519. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  1520. ret = swr_device_down(swr_dev);
  1521. if (ret) {
  1522. dev_err(dev,
  1523. "%s: failed to shutdown swr dev %d\n",
  1524. __func__, swr_dev->dev_num);
  1525. goto exit;
  1526. }
  1527. }
  1528. swrm_clk_request(swrm, false);
  1529. }
  1530. exit:
  1531. mutex_unlock(&swrm->reslock);
  1532. return ret;
  1533. }
  1534. #endif /* CONFIG_PM */
  1535. static int swrm_device_down(struct device *dev)
  1536. {
  1537. struct platform_device *pdev = to_platform_device(dev);
  1538. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  1539. int ret = 0;
  1540. dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state);
  1541. mutex_lock(&swrm->force_down_lock);
  1542. swrm->state = SWR_MSTR_SSR;
  1543. mutex_unlock(&swrm->force_down_lock);
  1544. /* Use pm runtime function to tear down */
  1545. ret = pm_runtime_put_sync_suspend(dev);
  1546. pm_runtime_get_noresume(dev);
  1547. return ret;
  1548. }
  1549. /**
  1550. * swrm_wcd_notify - parent device can notify to soundwire master through
  1551. * this function
  1552. * @pdev: pointer to platform device structure
  1553. * @id: command id from parent to the soundwire master
  1554. * @data: data from parent device to soundwire master
  1555. */
  1556. int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data)
  1557. {
  1558. struct swr_mstr_ctrl *swrm;
  1559. int ret = 0;
  1560. struct swr_master *mstr;
  1561. struct swr_device *swr_dev;
  1562. if (!pdev) {
  1563. pr_err("%s: pdev is NULL\n", __func__);
  1564. return -EINVAL;
  1565. }
  1566. swrm = platform_get_drvdata(pdev);
  1567. if (!swrm) {
  1568. dev_err(&pdev->dev, "%s: swrm is NULL\n", __func__);
  1569. return -EINVAL;
  1570. }
  1571. mstr = &swrm->master;
  1572. switch (id) {
  1573. case SWR_CH_MAP:
  1574. if (!data) {
  1575. dev_err(swrm->dev, "%s: data is NULL\n", __func__);
  1576. ret = -EINVAL;
  1577. } else {
  1578. ret = swrm_set_ch_map(swrm, data);
  1579. }
  1580. break;
  1581. case SWR_DEVICE_DOWN:
  1582. dev_dbg(swrm->dev, "%s: swr master down called\n", __func__);
  1583. mutex_lock(&swrm->mlock);
  1584. if ((swrm->state == SWR_MSTR_PAUSE) ||
  1585. (swrm->state == SWR_MSTR_DOWN))
  1586. dev_dbg(swrm->dev, "%s: SWR master is already Down: %d\n",
  1587. __func__, swrm->state);
  1588. else
  1589. swrm_device_down(&pdev->dev);
  1590. mutex_unlock(&swrm->mlock);
  1591. break;
  1592. case SWR_DEVICE_UP:
  1593. dev_dbg(swrm->dev, "%s: swr master up called\n", __func__);
  1594. mutex_lock(&swrm->mlock);
  1595. mutex_lock(&swrm->reslock);
  1596. if ((swrm->state == SWR_MSTR_RESUME) ||
  1597. (swrm->state == SWR_MSTR_UP)) {
  1598. dev_dbg(swrm->dev, "%s: SWR master is already UP: %d\n",
  1599. __func__, swrm->state);
  1600. list_for_each_entry(swr_dev, &mstr->devices, dev_list)
  1601. swr_reset_device(swr_dev);
  1602. } else {
  1603. pm_runtime_mark_last_busy(&pdev->dev);
  1604. mutex_unlock(&swrm->reslock);
  1605. pm_runtime_get_sync(&pdev->dev);
  1606. mutex_lock(&swrm->reslock);
  1607. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  1608. ret = swr_reset_device(swr_dev);
  1609. if (ret) {
  1610. dev_err(swrm->dev,
  1611. "%s: failed to reset swr device %d\n",
  1612. __func__, swr_dev->dev_num);
  1613. swrm_clk_request(swrm, false);
  1614. }
  1615. }
  1616. pm_runtime_mark_last_busy(&pdev->dev);
  1617. pm_runtime_put_autosuspend(&pdev->dev);
  1618. }
  1619. mutex_unlock(&swrm->reslock);
  1620. mutex_unlock(&swrm->mlock);
  1621. break;
  1622. case SWR_SET_NUM_RX_CH:
  1623. if (!data) {
  1624. dev_err(swrm->dev, "%s: data is NULL\n", __func__);
  1625. ret = -EINVAL;
  1626. } else {
  1627. mutex_lock(&swrm->mlock);
  1628. swrm->num_rx_chs = *(int *)data;
  1629. if ((swrm->num_rx_chs > 1) && !swrm->num_cfg_devs) {
  1630. list_for_each_entry(swr_dev, &mstr->devices,
  1631. dev_list) {
  1632. ret = swr_set_device_group(swr_dev,
  1633. SWR_BROADCAST);
  1634. if (ret)
  1635. dev_err(swrm->dev,
  1636. "%s: set num ch failed\n",
  1637. __func__);
  1638. }
  1639. } else {
  1640. list_for_each_entry(swr_dev, &mstr->devices,
  1641. dev_list) {
  1642. ret = swr_set_device_group(swr_dev,
  1643. SWR_GROUP_NONE);
  1644. if (ret)
  1645. dev_err(swrm->dev,
  1646. "%s: set num ch failed\n",
  1647. __func__);
  1648. }
  1649. }
  1650. mutex_unlock(&swrm->mlock);
  1651. }
  1652. break;
  1653. default:
  1654. dev_err(swrm->dev, "%s: swr master unknown id %d\n",
  1655. __func__, id);
  1656. break;
  1657. }
  1658. return ret;
  1659. }
  1660. EXPORT_SYMBOL(swrm_wcd_notify);
  1661. #ifdef CONFIG_PM_SLEEP
  1662. static int swrm_suspend(struct device *dev)
  1663. {
  1664. int ret = -EBUSY;
  1665. struct platform_device *pdev = to_platform_device(dev);
  1666. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  1667. dev_dbg(dev, "%s: system suspend, state: %d\n", __func__, swrm->state);
  1668. if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
  1669. ret = swrm_runtime_suspend(dev);
  1670. if (!ret) {
  1671. /*
  1672. * Synchronize runtime-pm and system-pm states:
  1673. * At this point, we are already suspended. If
  1674. * runtime-pm still thinks its active, then
  1675. * make sure its status is in sync with HW
  1676. * status. The three below calls let the
  1677. * runtime-pm know that we are suspended
  1678. * already without re-invoking the suspend
  1679. * callback
  1680. */
  1681. pm_runtime_disable(dev);
  1682. pm_runtime_set_suspended(dev);
  1683. pm_runtime_enable(dev);
  1684. }
  1685. }
  1686. if (ret == -EBUSY) {
  1687. /*
  1688. * There is a possibility that some audio stream is active
  1689. * during suspend. We dont want to return suspend failure in
  1690. * that case so that display and relevant components can still
  1691. * go to suspend.
  1692. * If there is some other error, then it should be passed-on
  1693. * to system level suspend
  1694. */
  1695. ret = 0;
  1696. }
  1697. return ret;
  1698. }
  1699. static int swrm_resume(struct device *dev)
  1700. {
  1701. int ret = 0;
  1702. struct platform_device *pdev = to_platform_device(dev);
  1703. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  1704. dev_dbg(dev, "%s: system resume, state: %d\n", __func__, swrm->state);
  1705. if (!pm_runtime_enabled(dev) || !pm_runtime_suspend(dev)) {
  1706. ret = swrm_runtime_resume(dev);
  1707. if (!ret) {
  1708. pm_runtime_mark_last_busy(dev);
  1709. pm_request_autosuspend(dev);
  1710. }
  1711. }
  1712. return ret;
  1713. }
  1714. #endif /* CONFIG_PM_SLEEP */
  1715. static const struct dev_pm_ops swrm_dev_pm_ops = {
  1716. SET_SYSTEM_SLEEP_PM_OPS(
  1717. swrm_suspend,
  1718. swrm_resume
  1719. )
  1720. SET_RUNTIME_PM_OPS(
  1721. swrm_runtime_suspend,
  1722. swrm_runtime_resume,
  1723. NULL
  1724. )
  1725. };
  1726. static const struct of_device_id swrm_dt_match[] = {
  1727. {
  1728. .compatible = "qcom,swr-wcd",
  1729. },
  1730. {}
  1731. };
  1732. static struct platform_driver swr_mstr_driver = {
  1733. .probe = swrm_probe,
  1734. .remove = swrm_remove,
  1735. .driver = {
  1736. .name = SWR_WCD_NAME,
  1737. .owner = THIS_MODULE,
  1738. .pm = &swrm_dev_pm_ops,
  1739. .of_match_table = swrm_dt_match,
  1740. .suppress_bind_attrs = true,
  1741. },
  1742. };
  1743. static int __init swrm_init(void)
  1744. {
  1745. return platform_driver_register(&swr_mstr_driver);
  1746. }
  1747. module_init(swrm_init);
  1748. static void __exit swrm_exit(void)
  1749. {
  1750. platform_driver_unregister(&swr_mstr_driver);
  1751. }
  1752. module_exit(swrm_exit);
  1753. MODULE_LICENSE("GPL v2");
  1754. MODULE_DESCRIPTION("WCD SoundWire Controller");
  1755. MODULE_ALIAS("platform:swr-wcd");