qcs405.c 278 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248624962506251625262536254625562566257625862596260626162626263626462656266626762686269627062716272627362746275627662776278627962806281628262836284628562866287628862896290629162926293629462956296629762986299630063016302630363046305630663076308630963106311631263136314631563166317631863196320632163226323632463256326632763286329633063316332633363346335633663376338633963406341634263436344634563466347634863496350635163526353635463556356635763586359636063616362636363646365636663676368636963706371637263736374637563766377637863796380638163826383638463856386638763886389639063916392639363946395639663976398639964006401640264036404640564066407640864096410641164126413641464156416641764186419642064216422642364246425642664276428642964306431643264336434643564366437643864396440644164426443644464456446644764486449645064516452645364546455645664576458645964606461646264636464646564666467646864696470647164726473647464756476647764786479648064816482648364846485648664876488648964906491649264936494649564966497649864996500650165026503650465056506650765086509651065116512651365146515651665176518651965206521652265236524652565266527652865296530653165326533653465356536653765386539654065416542654365446545654665476548654965506551655265536554655565566557655865596560656165626563656465656566656765686569657065716572657365746575657665776578657965806581658265836584658565866587658865896590659165926593659465956596659765986599660066016602660366046605660666076608660966106611661266136614661566166617661866196620662166226623662466256626662766286629663066316632663366346635663666376638663966406641664266436644664566466647664866496650665166526653665466556656665766586659666066616662666366646665666666676668666966706671667266736674667566766677667866796680668166826683668466856686668766886689669066916692669366946695669666976698669967006701670267036704670567066707670867096710671167126713671467156716671767186719672067216722672367246725672667276728672967306731673267336734673567366737673867396740674167426743674467456746674767486749675067516752675367546755675667576758675967606761676267636764676567666767676867696770677167726773677467756776677767786779678067816782678367846785678667876788678967906791679267936794679567966797679867996800680168026803680468056806680768086809681068116812681368146815681668176818681968206821682268236824682568266827682868296830683168326833683468356836683768386839684068416842684368446845684668476848684968506851685268536854685568566857685868596860686168626863686468656866686768686869687068716872687368746875687668776878687968806881688268836884688568866887688868896890689168926893689468956896689768986899690069016902690369046905690669076908690969106911691269136914691569166917691869196920692169226923692469256926692769286929693069316932693369346935693669376938693969406941694269436944694569466947694869496950695169526953695469556956695769586959696069616962696369646965696669676968696969706971697269736974697569766977697869796980698169826983698469856986698769886989699069916992699369946995699669976998699970007001700270037004700570067007700870097010701170127013701470157016701770187019702070217022702370247025702670277028702970307031703270337034703570367037703870397040704170427043704470457046704770487049705070517052705370547055705670577058705970607061706270637064706570667067706870697070707170727073707470757076707770787079708070817082708370847085708670877088708970907091709270937094709570967097709870997100710171027103710471057106710771087109711071117112711371147115711671177118711971207121712271237124712571267127712871297130713171327133713471357136713771387139714071417142714371447145714671477148714971507151715271537154715571567157715871597160716171627163716471657166716771687169717071717172717371747175717671777178717971807181718271837184718571867187718871897190719171927193719471957196719771987199720072017202720372047205720672077208720972107211721272137214721572167217721872197220722172227223722472257226722772287229723072317232723372347235723672377238723972407241724272437244724572467247724872497250725172527253725472557256725772587259726072617262726372647265726672677268726972707271727272737274727572767277727872797280728172827283728472857286728772887289729072917292729372947295729672977298729973007301730273037304730573067307730873097310731173127313731473157316731773187319732073217322732373247325732673277328732973307331733273337334733573367337733873397340734173427343734473457346734773487349735073517352735373547355735673577358735973607361736273637364736573667367736873697370737173727373737473757376737773787379738073817382738373847385738673877388738973907391739273937394739573967397739873997400740174027403740474057406740774087409741074117412741374147415741674177418741974207421742274237424742574267427742874297430743174327433743474357436743774387439744074417442744374447445744674477448744974507451745274537454745574567457745874597460746174627463746474657466746774687469747074717472747374747475747674777478747974807481748274837484748574867487748874897490749174927493749474957496749774987499750075017502750375047505750675077508750975107511751275137514751575167517751875197520752175227523752475257526752775287529753075317532753375347535753675377538753975407541754275437544754575467547754875497550755175527553755475557556755775587559756075617562756375647565756675677568756975707571757275737574757575767577757875797580758175827583758475857586758775887589759075917592759375947595759675977598759976007601760276037604760576067607760876097610761176127613761476157616761776187619762076217622762376247625762676277628762976307631763276337634763576367637763876397640764176427643764476457646764776487649765076517652765376547655765676577658765976607661766276637664766576667667766876697670767176727673767476757676767776787679768076817682768376847685768676877688768976907691769276937694769576967697769876997700770177027703770477057706770777087709771077117712771377147715771677177718771977207721772277237724772577267727772877297730773177327733773477357736773777387739774077417742774377447745774677477748774977507751775277537754775577567757775877597760776177627763776477657766776777687769777077717772777377747775777677777778777977807781778277837784778577867787778877897790779177927793779477957796779777987799780078017802780378047805780678077808780978107811781278137814781578167817781878197820782178227823782478257826782778287829783078317832783378347835783678377838783978407841784278437844784578467847784878497850785178527853785478557856785778587859786078617862786378647865786678677868786978707871787278737874787578767877787878797880788178827883788478857886788778887889789078917892789378947895789678977898789979007901790279037904790579067907790879097910791179127913791479157916791779187919792079217922792379247925792679277928792979307931793279337934793579367937793879397940794179427943794479457946794779487949795079517952795379547955795679577958795979607961796279637964796579667967796879697970797179727973797479757976797779787979798079817982798379847985798679877988798979907991799279937994799579967997799879998000800180028003800480058006800780088009801080118012801380148015801680178018801980208021802280238024802580268027802880298030803180328033803480358036803780388039804080418042804380448045804680478048804980508051805280538054805580568057805880598060806180628063806480658066806780688069807080718072807380748075807680778078807980808081808280838084808580868087808880898090809180928093809480958096809780988099810081018102810381048105810681078108810981108111811281138114811581168117811881198120812181228123812481258126812781288129813081318132813381348135813681378138813981408141814281438144814581468147814881498150815181528153815481558156815781588159816081618162816381648165816681678168816981708171817281738174817581768177817881798180818181828183818481858186818781888189819081918192819381948195819681978198819982008201820282038204820582068207820882098210821182128213821482158216821782188219822082218222822382248225822682278228822982308231823282338234823582368237823882398240824182428243824482458246824782488249825082518252825382548255825682578258825982608261826282638264826582668267826882698270827182728273827482758276827782788279828082818282828382848285828682878288828982908291829282938294829582968297829882998300830183028303830483058306830783088309831083118312831383148315831683178318831983208321832283238324832583268327832883298330833183328333833483358336833783388339834083418342834383448345834683478348834983508351835283538354835583568357835883598360836183628363836483658366836783688369837083718372837383748375837683778378837983808381838283838384838583868387838883898390839183928393839483958396839783988399840084018402840384048405840684078408840984108411841284138414841584168417841884198420842184228423842484258426842784288429843084318432843384348435843684378438843984408441844284438444844584468447844884498450845184528453845484558456845784588459846084618462846384648465846684678468846984708471847284738474847584768477847884798480848184828483848484858486848784888489849084918492849384948495849684978498849985008501850285038504850585068507850885098510851185128513851485158516851785188519852085218522852385248525852685278528852985308531853285338534853585368537853885398540854185428543854485458546854785488549855085518552855385548555855685578558855985608561856285638564856585668567856885698570857185728573857485758576857785788579858085818582858385848585858685878588858985908591859285938594859585968597859885998600860186028603860486058606860786088609861086118612861386148615861686178618861986208621862286238624862586268627862886298630863186328633863486358636863786388639864086418642864386448645864686478648864986508651865286538654865586568657865886598660866186628663866486658666866786688669867086718672867386748675867686778678867986808681868286838684868586868687868886898690869186928693869486958696869786988699870087018702870387048705870687078708870987108711871287138714871587168717871887198720872187228723872487258726872787288729873087318732873387348735873687378738873987408741874287438744874587468747874887498750875187528753875487558756875787588759876087618762876387648765876687678768876987708771877287738774877587768777877887798780878187828783878487858786878787888789879087918792879387948795879687978798879988008801880288038804880588068807880888098810881188128813881488158816881788188819882088218822882388248825882688278828882988308831883288338834883588368837883888398840884188428843884488458846884788488849885088518852885388548855885688578858885988608861886288638864886588668867886888698870887188728873887488758876887788788879888088818882888388848885888688878888888988908891889288938894889588968897889888998900890189028903890489058906890789088909891089118912891389148915891689178918891989208921892289238924892589268927892889298930893189328933893489358936893789388939894089418942894389448945894689478948894989508951895289538954895589568957895889598960896189628963896489658966896789688969897089718972897389748975897689778978897989808981898289838984898589868987898889898990899189928993899489958996899789988999900090019002900390049005900690079008900990109011901290139014901590169017901890199020902190229023902490259026902790289029903090319032903390349035903690379038903990409041904290439044904590469047904890499050905190529053905490559056905790589059906090619062906390649065906690679068906990709071907290739074907590769077907890799080908190829083908490859086908790889089909090919092909390949095909690979098909991009101910291039104910591069107910891099110911191129113911491159116911791189119912091219122912391249125912691279128912991309131913291339134913591369137913891399140914191429143914491459146914791489149915091519152915391549155915691579158915991609161916291639164916591669167916891699170917191729173917491759176917791789179918091819182918391849185918691879188918991909191919291939194919591969197919891999200920192029203920492059206920792089209921092119212921392149215921692179218921992209221922292239224922592269227922892299230923192329233923492359236923792389239924092419242924392449245924692479248924992509251925292539254925592569257925892599260926192629263926492659266926792689269927092719272927392749275927692779278927992809281928292839284928592869287928892899290929192929293929492959296929792989299930093019302930393049305930693079308930993109311931293139314931593169317931893199320932193229323932493259326932793289329933093319332933393349335933693379338933993409341934293439344934593469347934893499350935193529353935493559356935793589359936093619362936393649365936693679368936993709371937293739374937593769377937893799380938193829383938493859386938793889389939093919392939393949395939693979398939994009401940294039404940594069407940894099410941194129413941494159416941794189419942094219422942394249425942694279428942994309431943294339434943594369437943894399440944194429443944494459446944794489449945094519452945394549455945694579458945994609461946294639464946594669467946894699470947194729473947494759476947794789479948094819482948394849485948694879488948994909491949294939494949594969497949894999500950195029503950495059506950795089509951095119512951395149515951695179518951995209521952295239524952595269527952895299530953195329533953495359536953795389539954095419542954395449545954695479548954995509551955295539554955595569557955895599560956195629563956495659566956795689569957095719572957395749575957695779578957995809581958295839584958595869587958895899590959195929593959495959596959795989599960096019602960396049605960696079608960996109611961296139614961596169617961896199620962196229623962496259626962796289629963096319632963396349635963696379638963996409641964296439644964596469647964896499650965196529653965496559656965796589659966096619662966396649665966696679668966996709671967296739674967596769677967896799680968196829683968496859686968796889689969096919692969396949695969696979698969997009701970297039704970597069707970897099710971197129713971497159716971797189719972097219722972397249725972697279728972997309731973297339734973597369737973897399740974197429743974497459746974797489749975097519752975397549755975697579758975997609761976297639764976597669767976897699770977197729773977497759776977797789779978097819782978397849785978697879788978997909791979297939794979597969797979897999800980198029803980498059806980798089809981098119812981398149815981698179818981998209821982298239824982598269827982898299830983198329833983498359836983798389839984098419842984398449845984698479848984998509851985298539854985598569857985898599860986198629863986498659866986798689869987098719872987398749875987698779878987998809881988298839884988598869887988898899890989198929893989498959896989798989899990099019902990399049905990699079908990999109911991299139914991599169917991899199920992199229923992499259926992799289929993099319932993399349935993699379938993999409941994299439944994599469947994899499950995199529953995499559956995799589959996099619962996399649965996699679968996999709971997299739974997599769977997899799980998199829983998499859986998799889989999099919992999399949995999699979998999910000100011000210003100041000510006100071000810009100101001110012100131001410015100161001710018100191002010021100221002310024100251002610027100281002910030100311003210033100341003510036100371003810039100401004110042100431004410045100461004710048100491005010051100521005310054100551005610057100581005910060100611006210063100641006510066100671006810069100701007110072100731007410075100761007710078100791008010081100821008310084100851008610087100881008910090100911009210093100941009510096100971009810099101001010110102101031010410105
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
  3. */
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/gpio.h>
  7. #include <linux/of_gpio.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/slab.h>
  10. #include <linux/i2c.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <sound/core.h>
  18. #include <sound/soc.h>
  19. #include <sound/soc-dapm.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/info.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <dsp/apr_audio-v2.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include <dsp/msm_mdf.h>
  28. #include "device_event.h"
  29. #include "msm-pcm-routing-v2.h"
  30. #include <asoc/msm-cdc-pinctrl.h>
  31. #include "codecs/wcd9335.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/csra66x0/csra66x0.h"
  34. #include <dt-bindings/sound/audio-codec-port-types.h>
  35. #include "codecs/bolero/bolero-cdc.h"
  36. #include "codecs/bolero/wsa-macro.h"
  37. #define DRV_NAME "qcs405-asoc-snd"
  38. #define __CHIPSET__ "QCS405 "
  39. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  40. #define DEV_NAME_STR_LEN 32
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define SPDIF_TX_CORE_CLK_163_P84_MHZ 163840000
  55. #define TLMM_EAST_SPARE 0x07BA0000
  56. #define TLMM_SPDIF_HDMI_ARC_CTL 0x07BA2000
  57. #define WSA8810_NAME_1 "wsa881x.20170211"
  58. #define WSA8810_NAME_2 "wsa881x.20170212"
  59. #define WCN_CDC_SLIM_RX_CH_MAX 2
  60. #define WCN_CDC_SLIM_TX_CH_MAX 4
  61. #define TDM_CHANNEL_MAX 8
  62. #define BT_SLIM_TX SLIM_TX_9
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  65. enum {
  66. SLIM_RX_0 = 0,
  67. SLIM_RX_1,
  68. SLIM_RX_2,
  69. SLIM_RX_3,
  70. SLIM_RX_4,
  71. SLIM_RX_5,
  72. SLIM_RX_6,
  73. SLIM_RX_7,
  74. SLIM_RX_MAX,
  75. };
  76. enum {
  77. SLIM_TX_0 = 0,
  78. SLIM_TX_1,
  79. SLIM_TX_2,
  80. SLIM_TX_3,
  81. SLIM_TX_4,
  82. SLIM_TX_5,
  83. SLIM_TX_6,
  84. SLIM_TX_7,
  85. SLIM_TX_8,
  86. SLIM_TX_9,
  87. SLIM_TX_MAX,
  88. };
  89. enum {
  90. PRIM_MI2S = 0,
  91. SEC_MI2S,
  92. TERT_MI2S,
  93. QUAT_MI2S,
  94. QUIN_MI2S,
  95. SEN_MI2S,
  96. MI2S_MAX,
  97. };
  98. enum {
  99. PRIM_META_MI2S = 0,
  100. SEC_META_MI2S,
  101. META_MI2S_MAX,
  102. };
  103. enum {
  104. PRIM_AUX_PCM = 0,
  105. SEC_AUX_PCM,
  106. TERT_AUX_PCM,
  107. QUAT_AUX_PCM,
  108. QUIN_AUX_PCM,
  109. SEN_AUX_PCM,
  110. AUX_PCM_MAX,
  111. };
  112. enum {
  113. WSA_CDC_DMA_RX_0 = 0,
  114. WSA_CDC_DMA_RX_1,
  115. CDC_DMA_RX_MAX,
  116. };
  117. enum {
  118. WSA_CDC_DMA_TX_0 = 0,
  119. WSA_CDC_DMA_TX_1,
  120. WSA_CDC_DMA_TX_2,
  121. VA_CDC_DMA_TX_0,
  122. VA_CDC_DMA_TX_1,
  123. CDC_DMA_TX_MAX,
  124. };
  125. enum {
  126. PRIM_SPDIF_RX = 0,
  127. SEC_SPDIF_RX,
  128. SPDIF_RX_MAX,
  129. };
  130. enum {
  131. PRIM_SPDIF_TX = 0,
  132. SEC_SPDIF_TX,
  133. SPDIF_TX_MAX,
  134. };
  135. enum {
  136. HDMI_RX_IDX = 0,
  137. EXT_HDMI_RX_IDX_MAX,
  138. };
  139. struct mi2s_conf {
  140. struct mutex lock;
  141. u32 ref_cnt;
  142. u32 msm_is_mi2s_master;
  143. };
  144. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  145. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  146. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  147. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  148. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
  149. Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT,
  150. Q6AFE_LPASS_CLK_ID_SEN_MI2S_EBIT
  151. };
  152. struct meta_mi2s_conf {
  153. u32 num_member_ports;
  154. u32 member_port[MAX_NUM_I2S_META_PORT_MEMBER_PORTS];
  155. bool clk_enable[MAX_NUM_I2S_META_PORT_MEMBER_PORTS];
  156. };
  157. struct dev_config {
  158. u32 sample_rate;
  159. u32 bit_format;
  160. u32 channels;
  161. u32 data_format;
  162. };
  163. struct msm_wsa881x_dev_info {
  164. struct device_node *of_node;
  165. u32 index;
  166. };
  167. struct msm_csra66x0_dev_info {
  168. struct device_node *of_node;
  169. u32 index;
  170. };
  171. struct msm_asoc_mach_data {
  172. struct snd_info_entry *codec_root;
  173. struct device_node *dmic_01_gpio_p; /* used by pinctrl API */
  174. struct device_node *dmic_23_gpio_p; /* used by pinctrl API */
  175. struct device_node *dmic_45_gpio_p; /* used by pinctrl API */
  176. struct device_node *dmic_67_gpio_p; /* used by pinctrl API */
  177. struct device_node *lineout_booster_gpio_p; /* used by pinctrl API */
  178. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  179. int dmic_01_gpio_cnt;
  180. int dmic_23_gpio_cnt;
  181. int dmic_45_gpio_cnt;
  182. int dmic_67_gpio_cnt;
  183. struct regulator *tdm_micb_supply;
  184. u32 tdm_micb_voltage;
  185. u32 tdm_micb_current;
  186. bool codec_is_csra;
  187. void __iomem *mi2s_dsd_mode[MI2S_MAX];
  188. };
  189. struct msm_asoc_wcd93xx_codec {
  190. void* (*get_afe_config_fn)(struct snd_soc_component *component,
  191. enum afe_config_type config_type);
  192. };
  193. static const char *const pin_states[] = {"sleep", "i2s-active",
  194. "tdm-active"};
  195. enum {
  196. TDM_0 = 0,
  197. TDM_1,
  198. TDM_2,
  199. TDM_3,
  200. TDM_4,
  201. TDM_5,
  202. TDM_6,
  203. TDM_7,
  204. TDM_PORT_MAX,
  205. };
  206. enum {
  207. TDM_PRI = 0,
  208. TDM_SEC,
  209. TDM_TERT,
  210. TDM_QUAT,
  211. TDM_QUIN,
  212. TDM_INTERFACE_MAX,
  213. };
  214. struct tdm_port {
  215. u32 mode;
  216. u32 channel;
  217. };
  218. /* TDM default config */
  219. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  220. { /* PRI TDM */
  221. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  222. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  223. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  224. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  225. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  226. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  227. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  228. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  229. },
  230. { /* SEC TDM */
  231. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  232. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  233. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  234. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  235. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  236. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  237. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  238. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  239. },
  240. { /* TERT TDM */
  241. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  242. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  243. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  244. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  245. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  246. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  247. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  248. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  249. },
  250. { /* QUAT TDM */
  251. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  252. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  253. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  254. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  255. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  256. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  257. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  258. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  259. },
  260. { /* QUIN TDM */
  261. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  262. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  263. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  264. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  265. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  266. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  267. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  268. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  269. }
  270. };
  271. /* TDM default config */
  272. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  273. { /* PRI TDM */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  277. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  278. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  282. },
  283. { /* SEC TDM */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  287. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  288. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  292. },
  293. { /* TERT TDM */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  297. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  298. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  302. },
  303. { /* QUAT TDM */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  307. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  308. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  312. },
  313. { /* QUIN TDM */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  317. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  318. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  319. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  320. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  322. }
  323. };
  324. static struct dev_config ext_hdmi_rx_cfg[] = {
  325. [HDMI_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  326. };
  327. /* Default configuration of slimbus channels */
  328. static struct dev_config slim_rx_cfg[] = {
  329. [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  330. [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  331. [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  332. [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  333. [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  334. [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  335. [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  336. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  337. };
  338. static struct dev_config slim_tx_cfg[] = {
  339. [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  340. [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  341. [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  342. [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  343. [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  344. [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  345. [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  346. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  347. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  348. [SLIM_TX_9] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  349. };
  350. /* Default configuration of Codec DMA Interface Tx */
  351. static struct dev_config cdc_dma_rx_cfg[] = {
  352. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  353. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  354. };
  355. /* Default configuration of Codec DMA Interface Rx */
  356. static struct dev_config cdc_dma_tx_cfg[] = {
  357. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  358. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  359. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  360. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  361. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  362. };
  363. static struct dev_config usb_rx_cfg = {
  364. .sample_rate = SAMPLING_RATE_48KHZ,
  365. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  366. .channels = 2,
  367. };
  368. static struct dev_config usb_tx_cfg = {
  369. .sample_rate = SAMPLING_RATE_48KHZ,
  370. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  371. .channels = 1,
  372. };
  373. static struct dev_config proxy_rx_cfg = {
  374. .sample_rate = SAMPLING_RATE_48KHZ,
  375. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  376. .channels = 2,
  377. };
  378. /* Default configuration of MI2S channels */
  379. static struct dev_config mi2s_rx_cfg[] = {
  380. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  381. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  382. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  383. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  384. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  385. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  386. };
  387. static struct dev_config meta_mi2s_rx_cfg[] = {
  388. [PRIM_META_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  389. [SEC_META_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  390. };
  391. /* Default configuration of SPDIF channels */
  392. static struct dev_config spdif_rx_cfg[] = {
  393. [PRIM_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  394. [SEC_SPDIF_RX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  395. };
  396. static struct dev_config spdif_tx_cfg[] = {
  397. [PRIM_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  398. [SEC_SPDIF_TX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  399. };
  400. static struct dev_config mi2s_tx_cfg[] = {
  401. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  403. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  404. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  405. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  406. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  407. };
  408. static struct dev_config aux_pcm_rx_cfg[] = {
  409. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  410. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  411. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  412. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  413. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  414. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  415. };
  416. static struct dev_config aux_pcm_tx_cfg[] = {
  417. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  418. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  419. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  420. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  421. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  422. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  423. };
  424. static struct dev_config afe_lb_tx_cfg = {
  425. .sample_rate = SAMPLING_RATE_48KHZ,
  426. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  427. .channels = 2,
  428. };
  429. static int msm_vi_feed_tx_ch = 2;
  430. static const char *const slim_rx_ch_text[] = {"One", "Two"};
  431. static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
  432. "Five", "Six", "Seven",
  433. "Eight"};
  434. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  435. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  436. "S32_LE"};
  437. static const char *const data_format_text[] = {
  438. "LPCM",
  439. "Compr",
  440. "LPCM-60958",
  441. "Compr-60958",
  442. "NA4",
  443. "NA5",
  444. "NA6",
  445. "NA7",
  446. "NA8",
  447. "DSD_DOP_W_MARKER",
  448. "NATIVE_DSD_DATA"
  449. };
  450. static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  451. "KHZ_32", "KHZ_44P1", "KHZ_48",
  452. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  453. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  454. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  455. "KHZ_44P1", "KHZ_48",
  456. "KHZ_88P2", "KHZ_96"};
  457. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  458. "Five", "Six", "Seven",
  459. "Eight"};
  460. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  461. "Six", "Seven", "Eight"};
  462. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  463. "KHZ_16", "KHZ_22P05",
  464. "KHZ_32", "KHZ_44P1", "KHZ_48",
  465. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  466. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  467. static char const *ext_hdmi_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  468. "KHZ_192", "KHZ_32", "KHZ_44P1",
  469. "KHZ_88P2", "KHZ_176P4"};
  470. static char const *ext_hdmi_bit_format_text[] = {"S16_LE", "S24_LE",
  471. "S24_3LE"};
  472. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  473. "Five", "Six", "Seven", "Eight"};
  474. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  475. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  476. "KHZ_48", "KHZ_176P4",
  477. "KHZ_352P8"};
  478. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  479. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  480. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  481. "KHZ_48", "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  482. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  483. static const char *const mi2s_ch_text[] = {
  484. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  485. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  486. "Fourteen", "Fifteen", "Sixteen"
  487. };
  488. static const char *const meta_mi2s_ch_text[] = {
  489. "One", "Two", "Three", "Four", "Five", "Six", "Seven",
  490. "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen",
  491. "Fourteen", "Fifteen", "Sixteen", "Seventeen", "Eighteen",
  492. "Nineteen", "Twenty", "TwentyOne", "TwentyTwo", "TwentyThree",
  493. "TwentyFour", "TwentyFive", "TwentySix", "TwentySeven",
  494. "TwentyEight", "TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo"
  495. };
  496. static const char *const qos_text[] = {"Disable", "Enable"};
  497. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  498. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  499. "Five", "Six", "Seven", "Eight", "Nine", "Ten", "Eleven",
  500. "Twelve", "Thirteen", "Fourteen", "Fifteen", "Sixteen"};
  501. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  502. "KHZ_16", "KHZ_22P05",
  503. "KHZ_32", "KHZ_44P1", "KHZ_48",
  504. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  505. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  506. static const char *spdif_rate_text[] = {"KHZ_32", "KHZ_44P1", "KHZ_48",
  507. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  508. "KHZ_192"};
  509. static const char *spdif_ch_text[] = {"One", "Two"};
  510. static const char *spdif_bit_format_text[] = {"S16_LE", "S24_LE"};
  511. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(ext_hdmi_rx_chs, ch_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(ext_hdmi_rx_format, ext_hdmi_bit_format_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_sink, bt_sample_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(ext_hdmi_rx_sample_rate,
  537. ext_hdmi_sample_rate_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  568. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  569. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  570. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  571. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  572. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  573. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  574. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  575. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  576. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  577. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  578. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  579. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  580. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  581. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  582. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  583. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  584. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_data_format, data_format_text);
  585. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_data_format, data_format_text);
  586. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  587. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  588. static SOC_ENUM_SINGLE_EXT_DECL(prim_meta_mi2s_rx_sample_rate, mi2s_rate_text);
  589. static SOC_ENUM_SINGLE_EXT_DECL(sec_meta_mi2s_rx_sample_rate, mi2s_rate_text);
  590. static SOC_ENUM_SINGLE_EXT_DECL(prim_meta_mi2s_rx_chs, meta_mi2s_ch_text);
  591. static SOC_ENUM_SINGLE_EXT_DECL(sec_meta_mi2s_rx_chs, meta_mi2s_ch_text);
  592. static SOC_ENUM_SINGLE_EXT_DECL(prim_meta_mi2s_rx_format, bit_format_text);
  593. static SOC_ENUM_SINGLE_EXT_DECL(sec_meta_mi2s_rx_format, bit_format_text);
  594. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  595. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  596. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  597. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  598. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  599. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  600. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  601. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  602. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  603. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  604. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  605. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  606. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  607. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  608. cdc_dma_sample_rate_text);
  609. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  610. cdc_dma_sample_rate_text);
  611. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  612. cdc_dma_sample_rate_text);
  613. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  614. cdc_dma_sample_rate_text);
  615. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  616. cdc_dma_sample_rate_text);
  617. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  618. cdc_dma_sample_rate_text);
  619. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  620. cdc_dma_sample_rate_text);
  621. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_sample_rate, spdif_rate_text);
  622. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_sample_rate, spdif_rate_text);
  623. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_chs, spdif_ch_text);
  624. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_chs, spdif_ch_text);
  625. static SOC_ENUM_SINGLE_EXT_DECL(spdif_rx_format, spdif_bit_format_text);
  626. static SOC_ENUM_SINGLE_EXT_DECL(spdif_tx_format, spdif_bit_format_text);
  627. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_chs, cdc_dma_tx_ch_text);
  628. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_format, bit_format_text);
  629. static SOC_ENUM_SINGLE_EXT_DECL(afe_lb_tx_sample_rate,
  630. cdc_dma_sample_rate_text);
  631. static struct platform_device *spdev;
  632. static bool is_initial_boot;
  633. static bool codec_reg_done;
  634. static struct snd_soc_aux_dev *msm_aux_dev;
  635. static struct snd_soc_codec_conf *msm_codec_conf;
  636. static struct msm_asoc_wcd93xx_codec msm_codec_fn;
  637. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  638. int enable, bool dapm);
  639. static int msm_wsa881x_init(struct snd_soc_component *component);
  640. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  641. struct snd_ctl_elem_value *ucontrol);
  642. static struct snd_soc_dapm_route wcd_audio_paths[] = {
  643. {"MIC BIAS1", NULL, "MCLK TX"},
  644. {"MIC BIAS2", NULL, "MCLK TX"},
  645. {"MIC BIAS3", NULL, "MCLK TX"},
  646. {"MIC BIAS4", NULL, "MCLK TX"},
  647. };
  648. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  649. {
  650. AFE_API_VERSION_I2S_CONFIG,
  651. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  652. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  653. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  654. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  655. 0,
  656. },
  657. {
  658. AFE_API_VERSION_I2S_CONFIG,
  659. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  660. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  661. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  662. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  663. 0,
  664. },
  665. {
  666. AFE_API_VERSION_I2S_CONFIG,
  667. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  668. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  669. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  670. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  671. 0,
  672. },
  673. {
  674. AFE_API_VERSION_I2S_CONFIG,
  675. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  676. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  677. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  678. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  679. 0,
  680. },
  681. {
  682. AFE_API_VERSION_I2S_CONFIG,
  683. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  684. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  685. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  686. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  687. 0,
  688. },
  689. {
  690. AFE_API_VERSION_I2S_CONFIG,
  691. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  692. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  693. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  694. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  695. 0,
  696. }
  697. };
  698. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  699. static struct meta_mi2s_conf meta_mi2s_intf_conf[META_MI2S_MAX];
  700. static int msm_island_vad_get_portid_from_beid(int32_t be_id, int *port_id)
  701. {
  702. *port_id = 0xFFFF;
  703. switch (be_id) {
  704. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  705. *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  706. break;
  707. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  708. *port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  709. break;
  710. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  711. *port_id = AFE_PORT_ID_QUINARY_TDM_TX;
  712. break;
  713. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  714. *port_id = AFE_PORT_ID_QUINARY_PCM_TX;
  715. break;
  716. default:
  717. return -EINVAL;
  718. }
  719. return 0;
  720. }
  721. static int qcs405_send_island_vad_config(int32_t be_id)
  722. {
  723. int rc = 0;
  724. int port_id = 0xFFFF;
  725. rc = msm_island_vad_get_portid_from_beid(be_id, &port_id);
  726. if (rc) {
  727. pr_debug("%s: Invalid island interface\n", __func__);
  728. } else {
  729. /*
  730. * send island mode config
  731. * This should be the first configuration
  732. */
  733. rc = afe_send_port_island_mode(port_id);
  734. if (rc) {
  735. pr_err("%s: afe send island mode failed %d\n",
  736. __func__, rc);
  737. return rc;
  738. }
  739. rc = afe_send_port_vad_cfg_params(port_id);
  740. if (rc) {
  741. pr_err("%s: afe send vad config failed %d\n",
  742. __func__, rc);
  743. return rc;
  744. }
  745. }
  746. return 0;
  747. }
  748. static int slim_get_sample_rate_val(int sample_rate)
  749. {
  750. int sample_rate_val = 0;
  751. switch (sample_rate) {
  752. case SAMPLING_RATE_8KHZ:
  753. sample_rate_val = 0;
  754. break;
  755. case SAMPLING_RATE_16KHZ:
  756. sample_rate_val = 1;
  757. break;
  758. case SAMPLING_RATE_32KHZ:
  759. sample_rate_val = 2;
  760. break;
  761. case SAMPLING_RATE_44P1KHZ:
  762. sample_rate_val = 3;
  763. break;
  764. case SAMPLING_RATE_48KHZ:
  765. sample_rate_val = 4;
  766. break;
  767. case SAMPLING_RATE_88P2KHZ:
  768. sample_rate_val = 5;
  769. break;
  770. case SAMPLING_RATE_96KHZ:
  771. sample_rate_val = 6;
  772. break;
  773. case SAMPLING_RATE_176P4KHZ:
  774. sample_rate_val = 7;
  775. break;
  776. case SAMPLING_RATE_192KHZ:
  777. sample_rate_val = 8;
  778. break;
  779. case SAMPLING_RATE_352P8KHZ:
  780. sample_rate_val = 9;
  781. break;
  782. case SAMPLING_RATE_384KHZ:
  783. sample_rate_val = 10;
  784. break;
  785. default:
  786. sample_rate_val = 4;
  787. break;
  788. }
  789. return sample_rate_val;
  790. }
  791. static int slim_get_sample_rate(int value)
  792. {
  793. int sample_rate = 0;
  794. switch (value) {
  795. case 0:
  796. sample_rate = SAMPLING_RATE_8KHZ;
  797. break;
  798. case 1:
  799. sample_rate = SAMPLING_RATE_16KHZ;
  800. break;
  801. case 2:
  802. sample_rate = SAMPLING_RATE_32KHZ;
  803. break;
  804. case 3:
  805. sample_rate = SAMPLING_RATE_44P1KHZ;
  806. break;
  807. case 4:
  808. sample_rate = SAMPLING_RATE_48KHZ;
  809. break;
  810. case 5:
  811. sample_rate = SAMPLING_RATE_88P2KHZ;
  812. break;
  813. case 6:
  814. sample_rate = SAMPLING_RATE_96KHZ;
  815. break;
  816. case 7:
  817. sample_rate = SAMPLING_RATE_176P4KHZ;
  818. break;
  819. case 8:
  820. sample_rate = SAMPLING_RATE_192KHZ;
  821. break;
  822. case 9:
  823. sample_rate = SAMPLING_RATE_352P8KHZ;
  824. break;
  825. case 10:
  826. sample_rate = SAMPLING_RATE_384KHZ;
  827. break;
  828. default:
  829. sample_rate = SAMPLING_RATE_48KHZ;
  830. break;
  831. }
  832. return sample_rate;
  833. }
  834. static int slim_get_bit_format_val(int bit_format)
  835. {
  836. int val = 0;
  837. switch (bit_format) {
  838. case SNDRV_PCM_FORMAT_S32_LE:
  839. val = 3;
  840. break;
  841. case SNDRV_PCM_FORMAT_S24_3LE:
  842. val = 2;
  843. break;
  844. case SNDRV_PCM_FORMAT_S24_LE:
  845. val = 1;
  846. break;
  847. case SNDRV_PCM_FORMAT_S16_LE:
  848. default:
  849. val = 0;
  850. break;
  851. }
  852. return val;
  853. }
  854. static int slim_get_bit_format(int val)
  855. {
  856. int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  857. switch (val) {
  858. case 0:
  859. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  860. break;
  861. case 1:
  862. bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
  863. break;
  864. case 2:
  865. bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
  866. break;
  867. case 3:
  868. bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
  869. break;
  870. default:
  871. bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
  872. break;
  873. }
  874. return bit_fmt;
  875. }
  876. static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
  877. {
  878. int port_id = 0;
  879. if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
  880. port_id = SLIM_RX_0;
  881. } else if (strnstr(kcontrol->id.name,
  882. "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
  883. port_id = SLIM_RX_2;
  884. } else if (strnstr(kcontrol->id.name,
  885. "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
  886. port_id = SLIM_RX_5;
  887. } else if (strnstr(kcontrol->id.name,
  888. "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
  889. port_id = SLIM_RX_6;
  890. } else if (strnstr(kcontrol->id.name,
  891. "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
  892. port_id = SLIM_TX_0;
  893. } else if (strnstr(kcontrol->id.name,
  894. "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
  895. port_id = SLIM_TX_1;
  896. } else {
  897. pr_err("%s: unsupported channel: %s",
  898. __func__, kcontrol->id.name);
  899. return -EINVAL;
  900. }
  901. return port_id;
  902. }
  903. static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  904. struct snd_ctl_elem_value *ucontrol)
  905. {
  906. int ch_num = slim_get_port_idx(kcontrol);
  907. if (ch_num < 0)
  908. return ch_num;
  909. ucontrol->value.enumerated.item[0] =
  910. slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
  911. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  912. ch_num, slim_rx_cfg[ch_num].sample_rate,
  913. ucontrol->value.enumerated.item[0]);
  914. return 0;
  915. }
  916. static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  917. struct snd_ctl_elem_value *ucontrol)
  918. {
  919. int ch_num = slim_get_port_idx(kcontrol);
  920. if (ch_num < 0)
  921. return ch_num;
  922. slim_rx_cfg[ch_num].sample_rate =
  923. slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  924. pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  925. ch_num, slim_rx_cfg[ch_num].sample_rate,
  926. ucontrol->value.enumerated.item[0]);
  927. return 0;
  928. }
  929. static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  930. struct snd_ctl_elem_value *ucontrol)
  931. {
  932. int ch_num = slim_get_port_idx(kcontrol);
  933. if (ch_num < 0)
  934. return ch_num;
  935. ucontrol->value.enumerated.item[0] =
  936. slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
  937. pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  938. ch_num, slim_tx_cfg[ch_num].sample_rate,
  939. ucontrol->value.enumerated.item[0]);
  940. return 0;
  941. }
  942. static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  943. struct snd_ctl_elem_value *ucontrol)
  944. {
  945. int sample_rate = 0;
  946. int ch_num = slim_get_port_idx(kcontrol);
  947. if (ch_num < 0)
  948. return ch_num;
  949. sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
  950. if (sample_rate == SAMPLING_RATE_44P1KHZ) {
  951. pr_err("%s: Unsupported sample rate %d: for Tx path\n",
  952. __func__, sample_rate);
  953. return -EINVAL;
  954. }
  955. slim_tx_cfg[ch_num].sample_rate = sample_rate;
  956. pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
  957. ch_num, slim_tx_cfg[ch_num].sample_rate,
  958. ucontrol->value.enumerated.item[0]);
  959. return 0;
  960. }
  961. static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
  962. struct snd_ctl_elem_value *ucontrol)
  963. {
  964. int ch_num = slim_get_port_idx(kcontrol);
  965. if (ch_num < 0)
  966. return ch_num;
  967. ucontrol->value.enumerated.item[0] =
  968. slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
  969. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  970. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  971. ucontrol->value.enumerated.item[0]);
  972. return 0;
  973. }
  974. static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
  975. struct snd_ctl_elem_value *ucontrol)
  976. {
  977. int ch_num = slim_get_port_idx(kcontrol);
  978. if (ch_num < 0)
  979. return ch_num;
  980. slim_rx_cfg[ch_num].bit_format =
  981. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  982. pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
  983. __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
  984. ucontrol->value.enumerated.item[0]);
  985. return 0;
  986. }
  987. static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
  988. struct snd_ctl_elem_value *ucontrol)
  989. {
  990. int ch_num = slim_get_port_idx(kcontrol);
  991. if (ch_num < 0)
  992. return ch_num;
  993. ucontrol->value.enumerated.item[0] =
  994. slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
  995. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  996. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  997. ucontrol->value.enumerated.item[0]);
  998. return 0;
  999. }
  1000. static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
  1001. struct snd_ctl_elem_value *ucontrol)
  1002. {
  1003. int ch_num = slim_get_port_idx(kcontrol);
  1004. if (ch_num < 0)
  1005. return ch_num;
  1006. slim_tx_cfg[ch_num].bit_format =
  1007. slim_get_bit_format(ucontrol->value.enumerated.item[0]);
  1008. pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
  1009. __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
  1010. ucontrol->value.enumerated.item[0]);
  1011. return 0;
  1012. }
  1013. static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
  1014. struct snd_ctl_elem_value *ucontrol)
  1015. {
  1016. int ch_num = slim_get_port_idx(kcontrol);
  1017. if (ch_num < 0)
  1018. return ch_num;
  1019. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  1020. ch_num, slim_rx_cfg[ch_num].channels);
  1021. ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
  1022. return 0;
  1023. }
  1024. static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
  1025. struct snd_ctl_elem_value *ucontrol)
  1026. {
  1027. int ch_num = slim_get_port_idx(kcontrol);
  1028. if (ch_num < 0)
  1029. return ch_num;
  1030. slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  1031. pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
  1032. ch_num, slim_rx_cfg[ch_num].channels);
  1033. return 1;
  1034. }
  1035. static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
  1036. struct snd_ctl_elem_value *ucontrol)
  1037. {
  1038. int ch_num = slim_get_port_idx(kcontrol);
  1039. if (ch_num < 0)
  1040. return ch_num;
  1041. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  1042. ch_num, slim_tx_cfg[ch_num].channels);
  1043. ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
  1044. return 0;
  1045. }
  1046. static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
  1047. struct snd_ctl_elem_value *ucontrol)
  1048. {
  1049. int ch_num = slim_get_port_idx(kcontrol);
  1050. if (ch_num < 0)
  1051. return ch_num;
  1052. slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
  1053. pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
  1054. ch_num, slim_tx_cfg[ch_num].channels);
  1055. return 1;
  1056. }
  1057. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1058. struct snd_ctl_elem_value *ucontrol)
  1059. {
  1060. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1061. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1062. ucontrol->value.integer.value[0]);
  1063. return 0;
  1064. }
  1065. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1066. struct snd_ctl_elem_value *ucontrol)
  1067. {
  1068. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1069. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1070. return 1;
  1071. }
  1072. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  1073. struct snd_ctl_elem_value *ucontrol)
  1074. {
  1075. /*
  1076. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  1077. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  1078. * value.
  1079. */
  1080. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  1081. case SAMPLING_RATE_96KHZ:
  1082. ucontrol->value.integer.value[0] = 5;
  1083. break;
  1084. case SAMPLING_RATE_88P2KHZ:
  1085. ucontrol->value.integer.value[0] = 4;
  1086. break;
  1087. case SAMPLING_RATE_48KHZ:
  1088. ucontrol->value.integer.value[0] = 3;
  1089. break;
  1090. case SAMPLING_RATE_44P1KHZ:
  1091. ucontrol->value.integer.value[0] = 2;
  1092. break;
  1093. case SAMPLING_RATE_16KHZ:
  1094. ucontrol->value.integer.value[0] = 1;
  1095. break;
  1096. case SAMPLING_RATE_8KHZ:
  1097. default:
  1098. ucontrol->value.integer.value[0] = 0;
  1099. break;
  1100. }
  1101. pr_debug("%s: sample rate = %d", __func__,
  1102. slim_rx_cfg[SLIM_RX_7].sample_rate);
  1103. return 0;
  1104. }
  1105. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  1106. struct snd_ctl_elem_value *ucontrol)
  1107. {
  1108. switch (ucontrol->value.integer.value[0]) {
  1109. case 1:
  1110. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1111. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  1112. break;
  1113. case 2:
  1114. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1115. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  1116. break;
  1117. case 3:
  1118. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1119. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  1120. break;
  1121. case 4:
  1122. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1123. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  1124. break;
  1125. case 5:
  1126. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1127. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  1128. break;
  1129. case 0:
  1130. default:
  1131. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1132. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  1133. break;
  1134. }
  1135. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  1136. __func__,
  1137. slim_rx_cfg[SLIM_RX_7].sample_rate,
  1138. slim_tx_cfg[SLIM_TX_7].sample_rate,
  1139. ucontrol->value.enumerated.item[0]);
  1140. return 0;
  1141. }
  1142. static int msm_bt_sample_rate_sink_get(struct snd_kcontrol *kcontrol,
  1143. struct snd_ctl_elem_value *ucontrol)
  1144. {
  1145. switch (slim_tx_cfg[BT_SLIM_TX].sample_rate) {
  1146. case SAMPLING_RATE_96KHZ:
  1147. ucontrol->value.integer.value[0] = 5;
  1148. break;
  1149. case SAMPLING_RATE_88P2KHZ:
  1150. ucontrol->value.integer.value[0] = 4;
  1151. break;
  1152. case SAMPLING_RATE_48KHZ:
  1153. ucontrol->value.integer.value[0] = 3;
  1154. break;
  1155. case SAMPLING_RATE_44P1KHZ:
  1156. ucontrol->value.integer.value[0] = 2;
  1157. break;
  1158. case SAMPLING_RATE_16KHZ:
  1159. ucontrol->value.integer.value[0] = 1;
  1160. break;
  1161. case SAMPLING_RATE_8KHZ:
  1162. default:
  1163. ucontrol->value.integer.value[0] = 0;
  1164. break;
  1165. }
  1166. pr_debug("%s: sample rate = %d", __func__,
  1167. slim_tx_cfg[BT_SLIM_TX].sample_rate);
  1168. return 0;
  1169. }
  1170. static int msm_bt_sample_rate_sink_put(struct snd_kcontrol *kcontrol,
  1171. struct snd_ctl_elem_value *ucontrol)
  1172. {
  1173. switch (ucontrol->value.integer.value[0]) {
  1174. case 1:
  1175. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_16KHZ;
  1176. break;
  1177. case 2:
  1178. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_44P1KHZ;
  1179. break;
  1180. case 3:
  1181. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_48KHZ;
  1182. break;
  1183. case 4:
  1184. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_88P2KHZ;
  1185. break;
  1186. case 5:
  1187. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_96KHZ;
  1188. break;
  1189. case 0:
  1190. default:
  1191. slim_tx_cfg[BT_SLIM_TX].sample_rate = SAMPLING_RATE_8KHZ;
  1192. break;
  1193. }
  1194. pr_debug("%s: sample rate = %d, value = %d\n",
  1195. __func__,
  1196. slim_tx_cfg[BT_SLIM_TX].sample_rate,
  1197. ucontrol->value.enumerated.item[0]);
  1198. return 0;
  1199. }
  1200. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  1201. {
  1202. int idx = 0;
  1203. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  1204. sizeof("WSA_CDC_DMA_RX_0")))
  1205. idx = WSA_CDC_DMA_RX_0;
  1206. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  1207. sizeof("WSA_CDC_DMA_RX_0")))
  1208. idx = WSA_CDC_DMA_RX_1;
  1209. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  1210. sizeof("WSA_CDC_DMA_TX_0")))
  1211. idx = WSA_CDC_DMA_TX_0;
  1212. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  1213. sizeof("WSA_CDC_DMA_TX_1")))
  1214. idx = WSA_CDC_DMA_TX_1;
  1215. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  1216. sizeof("WSA_CDC_DMA_TX_2")))
  1217. idx = WSA_CDC_DMA_TX_2;
  1218. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  1219. sizeof("VA_CDC_DMA_TX_0")))
  1220. idx = VA_CDC_DMA_TX_0;
  1221. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  1222. sizeof("VA_CDC_DMA_TX_1")))
  1223. idx = VA_CDC_DMA_TX_1;
  1224. else {
  1225. pr_err("%s: unsupported port: %s\n",
  1226. __func__, kcontrol->id.name);
  1227. return -EINVAL;
  1228. }
  1229. return idx;
  1230. }
  1231. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  1232. struct snd_ctl_elem_value *ucontrol)
  1233. {
  1234. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1235. if (ch_num < 0)
  1236. return ch_num;
  1237. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1238. cdc_dma_rx_cfg[ch_num].channels - 1);
  1239. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  1240. return 0;
  1241. }
  1242. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  1243. struct snd_ctl_elem_value *ucontrol)
  1244. {
  1245. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1246. if (ch_num < 0)
  1247. return ch_num;
  1248. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1249. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  1250. cdc_dma_rx_cfg[ch_num].channels);
  1251. return 1;
  1252. }
  1253. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  1254. struct snd_ctl_elem_value *ucontrol)
  1255. {
  1256. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1257. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  1258. case SNDRV_PCM_FORMAT_S32_LE:
  1259. ucontrol->value.integer.value[0] = 3;
  1260. break;
  1261. case SNDRV_PCM_FORMAT_S24_3LE:
  1262. ucontrol->value.integer.value[0] = 2;
  1263. break;
  1264. case SNDRV_PCM_FORMAT_S24_LE:
  1265. ucontrol->value.integer.value[0] = 1;
  1266. break;
  1267. case SNDRV_PCM_FORMAT_S16_LE:
  1268. default:
  1269. ucontrol->value.integer.value[0] = 0;
  1270. break;
  1271. }
  1272. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1273. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1274. ucontrol->value.integer.value[0]);
  1275. return 0;
  1276. }
  1277. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  1278. struct snd_ctl_elem_value *ucontrol)
  1279. {
  1280. int rc = 0;
  1281. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1282. switch (ucontrol->value.integer.value[0]) {
  1283. case 3:
  1284. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1285. break;
  1286. case 2:
  1287. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1288. break;
  1289. case 1:
  1290. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1291. break;
  1292. case 0:
  1293. default:
  1294. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1295. break;
  1296. }
  1297. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  1298. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  1299. ucontrol->value.integer.value[0]);
  1300. return rc;
  1301. }
  1302. static int cdc_dma_get_sample_rate_val(int sample_rate)
  1303. {
  1304. int sample_rate_val = 0;
  1305. switch (sample_rate) {
  1306. case SAMPLING_RATE_8KHZ:
  1307. sample_rate_val = 0;
  1308. break;
  1309. case SAMPLING_RATE_11P025KHZ:
  1310. sample_rate_val = 1;
  1311. break;
  1312. case SAMPLING_RATE_16KHZ:
  1313. sample_rate_val = 2;
  1314. break;
  1315. case SAMPLING_RATE_22P05KHZ:
  1316. sample_rate_val = 3;
  1317. break;
  1318. case SAMPLING_RATE_32KHZ:
  1319. sample_rate_val = 4;
  1320. break;
  1321. case SAMPLING_RATE_44P1KHZ:
  1322. sample_rate_val = 5;
  1323. break;
  1324. case SAMPLING_RATE_48KHZ:
  1325. sample_rate_val = 6;
  1326. break;
  1327. case SAMPLING_RATE_88P2KHZ:
  1328. sample_rate_val = 7;
  1329. break;
  1330. case SAMPLING_RATE_96KHZ:
  1331. sample_rate_val = 8;
  1332. break;
  1333. case SAMPLING_RATE_176P4KHZ:
  1334. sample_rate_val = 9;
  1335. break;
  1336. case SAMPLING_RATE_192KHZ:
  1337. sample_rate_val = 10;
  1338. break;
  1339. case SAMPLING_RATE_352P8KHZ:
  1340. sample_rate_val = 11;
  1341. break;
  1342. case SAMPLING_RATE_384KHZ:
  1343. sample_rate_val = 12;
  1344. break;
  1345. default:
  1346. sample_rate_val = 6;
  1347. break;
  1348. }
  1349. return sample_rate_val;
  1350. }
  1351. static int cdc_dma_get_sample_rate(int value)
  1352. {
  1353. int sample_rate = 0;
  1354. switch (value) {
  1355. case 0:
  1356. sample_rate = SAMPLING_RATE_8KHZ;
  1357. break;
  1358. case 1:
  1359. sample_rate = SAMPLING_RATE_11P025KHZ;
  1360. break;
  1361. case 2:
  1362. sample_rate = SAMPLING_RATE_16KHZ;
  1363. break;
  1364. case 3:
  1365. sample_rate = SAMPLING_RATE_22P05KHZ;
  1366. break;
  1367. case 4:
  1368. sample_rate = SAMPLING_RATE_32KHZ;
  1369. break;
  1370. case 5:
  1371. sample_rate = SAMPLING_RATE_44P1KHZ;
  1372. break;
  1373. case 6:
  1374. sample_rate = SAMPLING_RATE_48KHZ;
  1375. break;
  1376. case 7:
  1377. sample_rate = SAMPLING_RATE_88P2KHZ;
  1378. break;
  1379. case 8:
  1380. sample_rate = SAMPLING_RATE_96KHZ;
  1381. break;
  1382. case 9:
  1383. sample_rate = SAMPLING_RATE_176P4KHZ;
  1384. break;
  1385. case 10:
  1386. sample_rate = SAMPLING_RATE_192KHZ;
  1387. break;
  1388. case 11:
  1389. sample_rate = SAMPLING_RATE_352P8KHZ;
  1390. break;
  1391. case 12:
  1392. sample_rate = SAMPLING_RATE_384KHZ;
  1393. break;
  1394. default:
  1395. sample_rate = SAMPLING_RATE_48KHZ;
  1396. break;
  1397. }
  1398. return sample_rate;
  1399. }
  1400. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1401. struct snd_ctl_elem_value *ucontrol)
  1402. {
  1403. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1404. if (ch_num < 0)
  1405. return ch_num;
  1406. ucontrol->value.enumerated.item[0] =
  1407. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  1408. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  1409. cdc_dma_rx_cfg[ch_num].sample_rate);
  1410. return 0;
  1411. }
  1412. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1413. struct snd_ctl_elem_value *ucontrol)
  1414. {
  1415. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1416. if (ch_num < 0)
  1417. return ch_num;
  1418. cdc_dma_rx_cfg[ch_num].sample_rate =
  1419. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1420. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  1421. __func__, ucontrol->value.enumerated.item[0],
  1422. cdc_dma_rx_cfg[ch_num].sample_rate);
  1423. return 0;
  1424. }
  1425. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  1426. struct snd_ctl_elem_value *ucontrol)
  1427. {
  1428. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1429. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1430. cdc_dma_tx_cfg[ch_num].channels);
  1431. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  1432. return 0;
  1433. }
  1434. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  1435. struct snd_ctl_elem_value *ucontrol)
  1436. {
  1437. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1438. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  1439. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  1440. cdc_dma_tx_cfg[ch_num].channels);
  1441. return 1;
  1442. }
  1443. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1444. struct snd_ctl_elem_value *ucontrol)
  1445. {
  1446. int sample_rate_val;
  1447. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1448. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  1449. case SAMPLING_RATE_384KHZ:
  1450. sample_rate_val = 12;
  1451. break;
  1452. case SAMPLING_RATE_352P8KHZ:
  1453. sample_rate_val = 11;
  1454. break;
  1455. case SAMPLING_RATE_192KHZ:
  1456. sample_rate_val = 10;
  1457. break;
  1458. case SAMPLING_RATE_176P4KHZ:
  1459. sample_rate_val = 9;
  1460. break;
  1461. case SAMPLING_RATE_96KHZ:
  1462. sample_rate_val = 8;
  1463. break;
  1464. case SAMPLING_RATE_88P2KHZ:
  1465. sample_rate_val = 7;
  1466. break;
  1467. case SAMPLING_RATE_48KHZ:
  1468. sample_rate_val = 6;
  1469. break;
  1470. case SAMPLING_RATE_44P1KHZ:
  1471. sample_rate_val = 5;
  1472. break;
  1473. case SAMPLING_RATE_32KHZ:
  1474. sample_rate_val = 4;
  1475. break;
  1476. case SAMPLING_RATE_22P05KHZ:
  1477. sample_rate_val = 3;
  1478. break;
  1479. case SAMPLING_RATE_16KHZ:
  1480. sample_rate_val = 2;
  1481. break;
  1482. case SAMPLING_RATE_11P025KHZ:
  1483. sample_rate_val = 1;
  1484. break;
  1485. case SAMPLING_RATE_8KHZ:
  1486. sample_rate_val = 0;
  1487. break;
  1488. default:
  1489. sample_rate_val = 6;
  1490. break;
  1491. }
  1492. ucontrol->value.integer.value[0] = sample_rate_val;
  1493. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  1494. cdc_dma_tx_cfg[ch_num].sample_rate);
  1495. return 0;
  1496. }
  1497. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1498. struct snd_ctl_elem_value *ucontrol)
  1499. {
  1500. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1501. switch (ucontrol->value.integer.value[0]) {
  1502. case 12:
  1503. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  1504. break;
  1505. case 11:
  1506. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  1507. break;
  1508. case 10:
  1509. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  1510. break;
  1511. case 9:
  1512. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  1513. break;
  1514. case 8:
  1515. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  1516. break;
  1517. case 7:
  1518. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  1519. break;
  1520. case 6:
  1521. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1522. break;
  1523. case 5:
  1524. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  1525. break;
  1526. case 4:
  1527. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  1528. break;
  1529. case 3:
  1530. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  1531. break;
  1532. case 2:
  1533. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  1534. break;
  1535. case 1:
  1536. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  1537. break;
  1538. case 0:
  1539. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  1540. break;
  1541. default:
  1542. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  1543. break;
  1544. }
  1545. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  1546. __func__, ucontrol->value.integer.value[0],
  1547. cdc_dma_tx_cfg[ch_num].sample_rate);
  1548. return 0;
  1549. }
  1550. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  1551. struct snd_ctl_elem_value *ucontrol)
  1552. {
  1553. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1554. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  1555. case SNDRV_PCM_FORMAT_S32_LE:
  1556. ucontrol->value.integer.value[0] = 3;
  1557. break;
  1558. case SNDRV_PCM_FORMAT_S24_3LE:
  1559. ucontrol->value.integer.value[0] = 2;
  1560. break;
  1561. case SNDRV_PCM_FORMAT_S24_LE:
  1562. ucontrol->value.integer.value[0] = 1;
  1563. break;
  1564. case SNDRV_PCM_FORMAT_S16_LE:
  1565. default:
  1566. ucontrol->value.integer.value[0] = 0;
  1567. break;
  1568. }
  1569. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1570. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1571. ucontrol->value.integer.value[0]);
  1572. return 0;
  1573. }
  1574. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  1575. struct snd_ctl_elem_value *ucontrol)
  1576. {
  1577. int rc = 0;
  1578. int ch_num = cdc_dma_get_port_idx(kcontrol);
  1579. switch (ucontrol->value.integer.value[0]) {
  1580. case 3:
  1581. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1582. break;
  1583. case 2:
  1584. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1585. break;
  1586. case 1:
  1587. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1588. break;
  1589. case 0:
  1590. default:
  1591. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1592. break;
  1593. }
  1594. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  1595. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  1596. ucontrol->value.integer.value[0]);
  1597. return rc;
  1598. }
  1599. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1600. struct snd_ctl_elem_value *ucontrol)
  1601. {
  1602. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1603. usb_rx_cfg.channels);
  1604. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1605. return 0;
  1606. }
  1607. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1608. struct snd_ctl_elem_value *ucontrol)
  1609. {
  1610. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1611. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1612. return 1;
  1613. }
  1614. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1615. struct snd_ctl_elem_value *ucontrol)
  1616. {
  1617. int sample_rate_val;
  1618. switch (usb_rx_cfg.sample_rate) {
  1619. case SAMPLING_RATE_384KHZ:
  1620. sample_rate_val = 12;
  1621. break;
  1622. case SAMPLING_RATE_352P8KHZ:
  1623. sample_rate_val = 11;
  1624. break;
  1625. case SAMPLING_RATE_192KHZ:
  1626. sample_rate_val = 10;
  1627. break;
  1628. case SAMPLING_RATE_176P4KHZ:
  1629. sample_rate_val = 9;
  1630. break;
  1631. case SAMPLING_RATE_96KHZ:
  1632. sample_rate_val = 8;
  1633. break;
  1634. case SAMPLING_RATE_88P2KHZ:
  1635. sample_rate_val = 7;
  1636. break;
  1637. case SAMPLING_RATE_48KHZ:
  1638. sample_rate_val = 6;
  1639. break;
  1640. case SAMPLING_RATE_44P1KHZ:
  1641. sample_rate_val = 5;
  1642. break;
  1643. case SAMPLING_RATE_32KHZ:
  1644. sample_rate_val = 4;
  1645. break;
  1646. case SAMPLING_RATE_22P05KHZ:
  1647. sample_rate_val = 3;
  1648. break;
  1649. case SAMPLING_RATE_16KHZ:
  1650. sample_rate_val = 2;
  1651. break;
  1652. case SAMPLING_RATE_11P025KHZ:
  1653. sample_rate_val = 1;
  1654. break;
  1655. case SAMPLING_RATE_8KHZ:
  1656. default:
  1657. sample_rate_val = 0;
  1658. break;
  1659. }
  1660. ucontrol->value.integer.value[0] = sample_rate_val;
  1661. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  1662. usb_rx_cfg.sample_rate);
  1663. return 0;
  1664. }
  1665. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1666. struct snd_ctl_elem_value *ucontrol)
  1667. {
  1668. switch (ucontrol->value.integer.value[0]) {
  1669. case 12:
  1670. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1671. break;
  1672. case 11:
  1673. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1674. break;
  1675. case 10:
  1676. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1677. break;
  1678. case 9:
  1679. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1680. break;
  1681. case 8:
  1682. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1683. break;
  1684. case 7:
  1685. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1686. break;
  1687. case 6:
  1688. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1689. break;
  1690. case 5:
  1691. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1692. break;
  1693. case 4:
  1694. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1695. break;
  1696. case 3:
  1697. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1698. break;
  1699. case 2:
  1700. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1701. break;
  1702. case 1:
  1703. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1704. break;
  1705. case 0:
  1706. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1707. break;
  1708. default:
  1709. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1710. break;
  1711. }
  1712. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  1713. __func__, ucontrol->value.integer.value[0],
  1714. usb_rx_cfg.sample_rate);
  1715. return 0;
  1716. }
  1717. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  1718. struct snd_ctl_elem_value *ucontrol)
  1719. {
  1720. switch (usb_rx_cfg.bit_format) {
  1721. case SNDRV_PCM_FORMAT_S32_LE:
  1722. ucontrol->value.integer.value[0] = 3;
  1723. break;
  1724. case SNDRV_PCM_FORMAT_S24_3LE:
  1725. ucontrol->value.integer.value[0] = 2;
  1726. break;
  1727. case SNDRV_PCM_FORMAT_S24_LE:
  1728. ucontrol->value.integer.value[0] = 1;
  1729. break;
  1730. case SNDRV_PCM_FORMAT_S16_LE:
  1731. default:
  1732. ucontrol->value.integer.value[0] = 0;
  1733. break;
  1734. }
  1735. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1736. __func__, usb_rx_cfg.bit_format,
  1737. ucontrol->value.integer.value[0]);
  1738. return 0;
  1739. }
  1740. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  1741. struct snd_ctl_elem_value *ucontrol)
  1742. {
  1743. int rc = 0;
  1744. switch (ucontrol->value.integer.value[0]) {
  1745. case 3:
  1746. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1747. break;
  1748. case 2:
  1749. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1750. break;
  1751. case 1:
  1752. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1753. break;
  1754. case 0:
  1755. default:
  1756. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1757. break;
  1758. }
  1759. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  1760. __func__, usb_rx_cfg.bit_format,
  1761. ucontrol->value.integer.value[0]);
  1762. return rc;
  1763. }
  1764. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1765. struct snd_ctl_elem_value *ucontrol)
  1766. {
  1767. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1768. usb_tx_cfg.channels);
  1769. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1770. return 0;
  1771. }
  1772. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1773. struct snd_ctl_elem_value *ucontrol)
  1774. {
  1775. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1776. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1777. return 1;
  1778. }
  1779. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1780. struct snd_ctl_elem_value *ucontrol)
  1781. {
  1782. int sample_rate_val;
  1783. switch (usb_tx_cfg.sample_rate) {
  1784. case SAMPLING_RATE_384KHZ:
  1785. sample_rate_val = 12;
  1786. break;
  1787. case SAMPLING_RATE_352P8KHZ:
  1788. sample_rate_val = 11;
  1789. break;
  1790. case SAMPLING_RATE_192KHZ:
  1791. sample_rate_val = 10;
  1792. break;
  1793. case SAMPLING_RATE_176P4KHZ:
  1794. sample_rate_val = 9;
  1795. break;
  1796. case SAMPLING_RATE_96KHZ:
  1797. sample_rate_val = 8;
  1798. break;
  1799. case SAMPLING_RATE_88P2KHZ:
  1800. sample_rate_val = 7;
  1801. break;
  1802. case SAMPLING_RATE_48KHZ:
  1803. sample_rate_val = 6;
  1804. break;
  1805. case SAMPLING_RATE_44P1KHZ:
  1806. sample_rate_val = 5;
  1807. break;
  1808. case SAMPLING_RATE_32KHZ:
  1809. sample_rate_val = 4;
  1810. break;
  1811. case SAMPLING_RATE_22P05KHZ:
  1812. sample_rate_val = 3;
  1813. break;
  1814. case SAMPLING_RATE_16KHZ:
  1815. sample_rate_val = 2;
  1816. break;
  1817. case SAMPLING_RATE_11P025KHZ:
  1818. sample_rate_val = 1;
  1819. break;
  1820. case SAMPLING_RATE_8KHZ:
  1821. sample_rate_val = 0;
  1822. break;
  1823. default:
  1824. sample_rate_val = 6;
  1825. break;
  1826. }
  1827. ucontrol->value.integer.value[0] = sample_rate_val;
  1828. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  1829. usb_tx_cfg.sample_rate);
  1830. return 0;
  1831. }
  1832. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1833. struct snd_ctl_elem_value *ucontrol)
  1834. {
  1835. switch (ucontrol->value.integer.value[0]) {
  1836. case 12:
  1837. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  1838. break;
  1839. case 11:
  1840. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  1841. break;
  1842. case 10:
  1843. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  1844. break;
  1845. case 9:
  1846. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  1847. break;
  1848. case 8:
  1849. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  1850. break;
  1851. case 7:
  1852. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  1853. break;
  1854. case 6:
  1855. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1856. break;
  1857. case 5:
  1858. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  1859. break;
  1860. case 4:
  1861. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  1862. break;
  1863. case 3:
  1864. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  1865. break;
  1866. case 2:
  1867. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  1868. break;
  1869. case 1:
  1870. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  1871. break;
  1872. case 0:
  1873. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  1874. break;
  1875. default:
  1876. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  1877. break;
  1878. }
  1879. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  1880. __func__, ucontrol->value.integer.value[0],
  1881. usb_tx_cfg.sample_rate);
  1882. return 0;
  1883. }
  1884. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  1885. struct snd_ctl_elem_value *ucontrol)
  1886. {
  1887. switch (usb_tx_cfg.bit_format) {
  1888. case SNDRV_PCM_FORMAT_S32_LE:
  1889. ucontrol->value.integer.value[0] = 3;
  1890. break;
  1891. case SNDRV_PCM_FORMAT_S24_3LE:
  1892. ucontrol->value.integer.value[0] = 2;
  1893. break;
  1894. case SNDRV_PCM_FORMAT_S24_LE:
  1895. ucontrol->value.integer.value[0] = 1;
  1896. break;
  1897. case SNDRV_PCM_FORMAT_S16_LE:
  1898. default:
  1899. ucontrol->value.integer.value[0] = 0;
  1900. break;
  1901. }
  1902. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1903. __func__, usb_tx_cfg.bit_format,
  1904. ucontrol->value.integer.value[0]);
  1905. return 0;
  1906. }
  1907. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  1908. struct snd_ctl_elem_value *ucontrol)
  1909. {
  1910. int rc = 0;
  1911. switch (ucontrol->value.integer.value[0]) {
  1912. case 3:
  1913. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  1914. break;
  1915. case 2:
  1916. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1917. break;
  1918. case 1:
  1919. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1920. break;
  1921. case 0:
  1922. default:
  1923. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1924. break;
  1925. }
  1926. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  1927. __func__, usb_tx_cfg.bit_format,
  1928. ucontrol->value.integer.value[0]);
  1929. return rc;
  1930. }
  1931. static int ext_hdmi_get_port_idx(struct snd_kcontrol *kcontrol)
  1932. {
  1933. int idx;
  1934. if (strnstr(kcontrol->id.name, "HDMI_RX",
  1935. sizeof("HDMI_RX"))) {
  1936. idx = HDMI_RX_IDX;
  1937. } else {
  1938. pr_err("%s: unsupported BE: %s",
  1939. __func__, kcontrol->id.name);
  1940. idx = -EINVAL;
  1941. }
  1942. return idx;
  1943. }
  1944. static int ext_hdmi_rx_format_get(struct snd_kcontrol *kcontrol,
  1945. struct snd_ctl_elem_value *ucontrol)
  1946. {
  1947. int idx = ext_hdmi_get_port_idx(kcontrol);
  1948. if (idx < 0)
  1949. return idx;
  1950. switch (ext_hdmi_rx_cfg[idx].bit_format) {
  1951. case SNDRV_PCM_FORMAT_S24_LE:
  1952. ucontrol->value.integer.value[0] = 1;
  1953. break;
  1954. case SNDRV_PCM_FORMAT_S16_LE:
  1955. default:
  1956. ucontrol->value.integer.value[0] = 0;
  1957. break;
  1958. }
  1959. pr_debug("%s: ext_hdmi_rx[%d].format = %d, ucontrol value = %ld\n",
  1960. __func__, idx, ext_hdmi_rx_cfg[idx].bit_format,
  1961. ucontrol->value.integer.value[0]);
  1962. return 0;
  1963. }
  1964. static int ext_hdmi_rx_format_put(struct snd_kcontrol *kcontrol,
  1965. struct snd_ctl_elem_value *ucontrol)
  1966. {
  1967. int idx = ext_hdmi_get_port_idx(kcontrol);
  1968. if (idx < 0)
  1969. return idx;
  1970. switch (ucontrol->value.integer.value[0]) {
  1971. case 1:
  1972. ext_hdmi_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1973. break;
  1974. case 0:
  1975. default:
  1976. ext_hdmi_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1977. break;
  1978. }
  1979. pr_debug("%s: ext_hdmi_rx[%d].format = %d, ucontrol value = %ld\n",
  1980. __func__, idx, ext_hdmi_rx_cfg[idx].bit_format,
  1981. ucontrol->value.integer.value[0]);
  1982. return 0;
  1983. }
  1984. static int ext_hdmi_rx_ch_get(struct snd_kcontrol *kcontrol,
  1985. struct snd_ctl_elem_value *ucontrol)
  1986. {
  1987. int idx = ext_hdmi_get_port_idx(kcontrol);
  1988. if (idx < 0)
  1989. return idx;
  1990. ucontrol->value.integer.value[0] =
  1991. ext_hdmi_rx_cfg[idx].channels - 2;
  1992. pr_debug("%s: ext_hdmi_rx[%d].ch = %d\n", __func__,
  1993. idx, ext_hdmi_rx_cfg[idx].channels);
  1994. return 0;
  1995. }
  1996. static int ext_hdmi_rx_ch_put(struct snd_kcontrol *kcontrol,
  1997. struct snd_ctl_elem_value *ucontrol)
  1998. {
  1999. int idx = ext_hdmi_get_port_idx(kcontrol);
  2000. if (idx < 0)
  2001. return idx;
  2002. ext_hdmi_rx_cfg[idx].channels =
  2003. ucontrol->value.integer.value[0] + 2;
  2004. pr_debug("%s: ext_hdmi_rx[%d].ch = %d\n", __func__,
  2005. idx, ext_hdmi_rx_cfg[idx].channels);
  2006. return 0;
  2007. }
  2008. static int ext_hdmi_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2009. struct snd_ctl_elem_value *ucontrol)
  2010. {
  2011. int sample_rate_val;
  2012. int idx = ext_hdmi_get_port_idx(kcontrol);
  2013. if (idx < 0)
  2014. return idx;
  2015. switch (ext_hdmi_rx_cfg[idx].sample_rate) {
  2016. case SAMPLING_RATE_176P4KHZ:
  2017. sample_rate_val = 6;
  2018. break;
  2019. case SAMPLING_RATE_88P2KHZ:
  2020. sample_rate_val = 5;
  2021. break;
  2022. case SAMPLING_RATE_44P1KHZ:
  2023. sample_rate_val = 4;
  2024. break;
  2025. case SAMPLING_RATE_32KHZ:
  2026. sample_rate_val = 3;
  2027. break;
  2028. case SAMPLING_RATE_192KHZ:
  2029. sample_rate_val = 2;
  2030. break;
  2031. case SAMPLING_RATE_96KHZ:
  2032. sample_rate_val = 1;
  2033. break;
  2034. case SAMPLING_RATE_48KHZ:
  2035. default:
  2036. sample_rate_val = 0;
  2037. break;
  2038. }
  2039. ucontrol->value.integer.value[0] = sample_rate_val;
  2040. pr_debug("%s: ext_hdmi_rx[%d].sample_rate = %d\n", __func__,
  2041. idx, ext_hdmi_rx_cfg[idx].sample_rate);
  2042. return 0;
  2043. }
  2044. static int ext_hdmi_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2045. struct snd_ctl_elem_value *ucontrol)
  2046. {
  2047. int idx = ext_hdmi_get_port_idx(kcontrol);
  2048. if (idx < 0)
  2049. return idx;
  2050. switch (ucontrol->value.integer.value[0]) {
  2051. case 6:
  2052. ext_hdmi_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  2053. break;
  2054. case 5:
  2055. ext_hdmi_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  2056. break;
  2057. case 4:
  2058. ext_hdmi_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  2059. break;
  2060. case 3:
  2061. ext_hdmi_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  2062. break;
  2063. case 2:
  2064. ext_hdmi_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  2065. break;
  2066. case 1:
  2067. ext_hdmi_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  2068. break;
  2069. case 0:
  2070. default:
  2071. ext_hdmi_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  2072. break;
  2073. }
  2074. pr_debug("%s: control value = %ld, ext_hdmi_rx[%d].sample_rate = %d\n",
  2075. __func__, ucontrol->value.integer.value[0], idx,
  2076. ext_hdmi_rx_cfg[idx].sample_rate);
  2077. return 0;
  2078. }
  2079. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  2080. struct snd_ctl_elem_value *ucontrol)
  2081. {
  2082. pr_debug("%s: proxy_rx channels = %d\n",
  2083. __func__, proxy_rx_cfg.channels);
  2084. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  2085. return 0;
  2086. }
  2087. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  2088. struct snd_ctl_elem_value *ucontrol)
  2089. {
  2090. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  2091. pr_debug("%s: proxy_rx channels = %d\n",
  2092. __func__, proxy_rx_cfg.channels);
  2093. return 1;
  2094. }
  2095. static int tdm_get_sample_rate(int value)
  2096. {
  2097. int sample_rate = 0;
  2098. switch (value) {
  2099. case 0:
  2100. sample_rate = SAMPLING_RATE_8KHZ;
  2101. break;
  2102. case 1:
  2103. sample_rate = SAMPLING_RATE_16KHZ;
  2104. break;
  2105. case 2:
  2106. sample_rate = SAMPLING_RATE_32KHZ;
  2107. break;
  2108. case 3:
  2109. sample_rate = SAMPLING_RATE_48KHZ;
  2110. break;
  2111. case 4:
  2112. sample_rate = SAMPLING_RATE_176P4KHZ;
  2113. break;
  2114. case 5:
  2115. sample_rate = SAMPLING_RATE_352P8KHZ;
  2116. break;
  2117. default:
  2118. sample_rate = SAMPLING_RATE_48KHZ;
  2119. break;
  2120. }
  2121. return sample_rate;
  2122. }
  2123. static int aux_pcm_get_sample_rate(int value)
  2124. {
  2125. int sample_rate;
  2126. switch (value) {
  2127. case 1:
  2128. sample_rate = SAMPLING_RATE_16KHZ;
  2129. break;
  2130. case 0:
  2131. default:
  2132. sample_rate = SAMPLING_RATE_8KHZ;
  2133. break;
  2134. }
  2135. return sample_rate;
  2136. }
  2137. static int tdm_get_sample_rate_val(int sample_rate)
  2138. {
  2139. int sample_rate_val = 0;
  2140. switch (sample_rate) {
  2141. case SAMPLING_RATE_8KHZ:
  2142. sample_rate_val = 0;
  2143. break;
  2144. case SAMPLING_RATE_16KHZ:
  2145. sample_rate_val = 1;
  2146. break;
  2147. case SAMPLING_RATE_32KHZ:
  2148. sample_rate_val = 2;
  2149. break;
  2150. case SAMPLING_RATE_48KHZ:
  2151. sample_rate_val = 3;
  2152. break;
  2153. case SAMPLING_RATE_176P4KHZ:
  2154. sample_rate_val = 4;
  2155. break;
  2156. case SAMPLING_RATE_352P8KHZ:
  2157. sample_rate_val = 5;
  2158. break;
  2159. default:
  2160. sample_rate_val = 3;
  2161. break;
  2162. }
  2163. return sample_rate_val;
  2164. }
  2165. static int aux_pcm_get_sample_rate_val(int sample_rate)
  2166. {
  2167. int sample_rate_val;
  2168. switch (sample_rate) {
  2169. case SAMPLING_RATE_16KHZ:
  2170. sample_rate_val = 1;
  2171. break;
  2172. case SAMPLING_RATE_8KHZ:
  2173. default:
  2174. sample_rate_val = 0;
  2175. break;
  2176. }
  2177. return sample_rate_val;
  2178. }
  2179. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  2180. struct tdm_port *port)
  2181. {
  2182. if (port) {
  2183. if (strnstr(kcontrol->id.name, "PRI",
  2184. sizeof(kcontrol->id.name))) {
  2185. port->mode = TDM_PRI;
  2186. } else if (strnstr(kcontrol->id.name, "SEC",
  2187. sizeof(kcontrol->id.name))) {
  2188. port->mode = TDM_SEC;
  2189. } else if (strnstr(kcontrol->id.name, "TERT",
  2190. sizeof(kcontrol->id.name))) {
  2191. port->mode = TDM_TERT;
  2192. } else if (strnstr(kcontrol->id.name, "QUAT",
  2193. sizeof(kcontrol->id.name))) {
  2194. port->mode = TDM_QUAT;
  2195. } else if (strnstr(kcontrol->id.name, "QUIN",
  2196. sizeof(kcontrol->id.name))) {
  2197. port->mode = TDM_QUIN;
  2198. } else {
  2199. pr_err("%s: unsupported mode in: %s",
  2200. __func__, kcontrol->id.name);
  2201. return -EINVAL;
  2202. }
  2203. if (strnstr(kcontrol->id.name, "RX_0",
  2204. sizeof(kcontrol->id.name)) ||
  2205. strnstr(kcontrol->id.name, "TX_0",
  2206. sizeof(kcontrol->id.name))) {
  2207. port->channel = TDM_0;
  2208. } else if (strnstr(kcontrol->id.name, "RX_1",
  2209. sizeof(kcontrol->id.name)) ||
  2210. strnstr(kcontrol->id.name, "TX_1",
  2211. sizeof(kcontrol->id.name))) {
  2212. port->channel = TDM_1;
  2213. } else if (strnstr(kcontrol->id.name, "RX_2",
  2214. sizeof(kcontrol->id.name)) ||
  2215. strnstr(kcontrol->id.name, "TX_2",
  2216. sizeof(kcontrol->id.name))) {
  2217. port->channel = TDM_2;
  2218. } else if (strnstr(kcontrol->id.name, "RX_3",
  2219. sizeof(kcontrol->id.name)) ||
  2220. strnstr(kcontrol->id.name, "TX_3",
  2221. sizeof(kcontrol->id.name))) {
  2222. port->channel = TDM_3;
  2223. } else if (strnstr(kcontrol->id.name, "RX_4",
  2224. sizeof(kcontrol->id.name)) ||
  2225. strnstr(kcontrol->id.name, "TX_4",
  2226. sizeof(kcontrol->id.name))) {
  2227. port->channel = TDM_4;
  2228. } else if (strnstr(kcontrol->id.name, "RX_5",
  2229. sizeof(kcontrol->id.name)) ||
  2230. strnstr(kcontrol->id.name, "TX_5",
  2231. sizeof(kcontrol->id.name))) {
  2232. port->channel = TDM_5;
  2233. } else if (strnstr(kcontrol->id.name, "RX_6",
  2234. sizeof(kcontrol->id.name)) ||
  2235. strnstr(kcontrol->id.name, "TX_6",
  2236. sizeof(kcontrol->id.name))) {
  2237. port->channel = TDM_6;
  2238. } else if (strnstr(kcontrol->id.name, "RX_7",
  2239. sizeof(kcontrol->id.name)) ||
  2240. strnstr(kcontrol->id.name, "TX_7",
  2241. sizeof(kcontrol->id.name))) {
  2242. port->channel = TDM_7;
  2243. } else {
  2244. pr_err("%s: unsupported channel in: %s",
  2245. __func__, kcontrol->id.name);
  2246. return -EINVAL;
  2247. }
  2248. } else
  2249. return -EINVAL;
  2250. return 0;
  2251. }
  2252. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2253. struct snd_ctl_elem_value *ucontrol)
  2254. {
  2255. struct tdm_port port;
  2256. int ret = tdm_get_port_idx(kcontrol, &port);
  2257. if (ret) {
  2258. pr_err("%s: unsupported control: %s",
  2259. __func__, kcontrol->id.name);
  2260. } else {
  2261. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2262. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  2263. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2264. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2265. ucontrol->value.enumerated.item[0]);
  2266. }
  2267. return ret;
  2268. }
  2269. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2270. struct snd_ctl_elem_value *ucontrol)
  2271. {
  2272. struct tdm_port port;
  2273. int ret = tdm_get_port_idx(kcontrol, &port);
  2274. if (ret) {
  2275. pr_err("%s: unsupported control: %s",
  2276. __func__, kcontrol->id.name);
  2277. } else {
  2278. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  2279. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2280. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  2281. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  2282. ucontrol->value.enumerated.item[0]);
  2283. }
  2284. return ret;
  2285. }
  2286. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2287. struct snd_ctl_elem_value *ucontrol)
  2288. {
  2289. struct tdm_port port;
  2290. int ret = tdm_get_port_idx(kcontrol, &port);
  2291. if (ret) {
  2292. pr_err("%s: unsupported control: %s",
  2293. __func__, kcontrol->id.name);
  2294. } else {
  2295. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  2296. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  2297. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2298. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2299. ucontrol->value.enumerated.item[0]);
  2300. }
  2301. return ret;
  2302. }
  2303. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2304. struct snd_ctl_elem_value *ucontrol)
  2305. {
  2306. struct tdm_port port;
  2307. int ret = tdm_get_port_idx(kcontrol, &port);
  2308. if (ret) {
  2309. pr_err("%s: unsupported control: %s",
  2310. __func__, kcontrol->id.name);
  2311. } else {
  2312. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  2313. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2314. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  2315. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  2316. ucontrol->value.enumerated.item[0]);
  2317. }
  2318. return ret;
  2319. }
  2320. static int tdm_get_format(int value)
  2321. {
  2322. int format = 0;
  2323. switch (value) {
  2324. case 0:
  2325. format = SNDRV_PCM_FORMAT_S16_LE;
  2326. break;
  2327. case 1:
  2328. format = SNDRV_PCM_FORMAT_S24_LE;
  2329. break;
  2330. case 2:
  2331. format = SNDRV_PCM_FORMAT_S32_LE;
  2332. break;
  2333. default:
  2334. format = SNDRV_PCM_FORMAT_S16_LE;
  2335. break;
  2336. }
  2337. return format;
  2338. }
  2339. static int tdm_get_format_val(int format)
  2340. {
  2341. int value = 0;
  2342. switch (format) {
  2343. case SNDRV_PCM_FORMAT_S16_LE:
  2344. value = 0;
  2345. break;
  2346. case SNDRV_PCM_FORMAT_S24_LE:
  2347. value = 1;
  2348. break;
  2349. case SNDRV_PCM_FORMAT_S32_LE:
  2350. value = 2;
  2351. break;
  2352. default:
  2353. value = 0;
  2354. break;
  2355. }
  2356. return value;
  2357. }
  2358. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  2359. struct snd_ctl_elem_value *ucontrol)
  2360. {
  2361. struct tdm_port port;
  2362. int ret = tdm_get_port_idx(kcontrol, &port);
  2363. if (ret) {
  2364. pr_err("%s: unsupported control: %s",
  2365. __func__, kcontrol->id.name);
  2366. } else {
  2367. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2368. tdm_rx_cfg[port.mode][port.channel].bit_format);
  2369. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2370. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2371. ucontrol->value.enumerated.item[0]);
  2372. }
  2373. return ret;
  2374. }
  2375. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  2376. struct snd_ctl_elem_value *ucontrol)
  2377. {
  2378. struct tdm_port port;
  2379. int ret = tdm_get_port_idx(kcontrol, &port);
  2380. if (ret) {
  2381. pr_err("%s: unsupported control: %s",
  2382. __func__, kcontrol->id.name);
  2383. } else {
  2384. tdm_rx_cfg[port.mode][port.channel].bit_format =
  2385. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2386. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  2387. tdm_rx_cfg[port.mode][port.channel].bit_format,
  2388. ucontrol->value.enumerated.item[0]);
  2389. }
  2390. return ret;
  2391. }
  2392. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  2393. struct snd_ctl_elem_value *ucontrol)
  2394. {
  2395. struct tdm_port port;
  2396. int ret = tdm_get_port_idx(kcontrol, &port);
  2397. if (ret) {
  2398. pr_err("%s: unsupported control: %s",
  2399. __func__, kcontrol->id.name);
  2400. } else {
  2401. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  2402. tdm_tx_cfg[port.mode][port.channel].bit_format);
  2403. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2404. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2405. ucontrol->value.enumerated.item[0]);
  2406. }
  2407. return ret;
  2408. }
  2409. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  2410. struct snd_ctl_elem_value *ucontrol)
  2411. {
  2412. struct tdm_port port;
  2413. int ret = tdm_get_port_idx(kcontrol, &port);
  2414. if (ret) {
  2415. pr_err("%s: unsupported control: %s",
  2416. __func__, kcontrol->id.name);
  2417. } else {
  2418. tdm_tx_cfg[port.mode][port.channel].bit_format =
  2419. tdm_get_format(ucontrol->value.enumerated.item[0]);
  2420. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  2421. tdm_tx_cfg[port.mode][port.channel].bit_format,
  2422. ucontrol->value.enumerated.item[0]);
  2423. }
  2424. return ret;
  2425. }
  2426. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  2427. struct snd_ctl_elem_value *ucontrol)
  2428. {
  2429. struct tdm_port port;
  2430. int ret = tdm_get_port_idx(kcontrol, &port);
  2431. if (ret) {
  2432. pr_err("%s: unsupported control: %s",
  2433. __func__, kcontrol->id.name);
  2434. } else {
  2435. ucontrol->value.enumerated.item[0] =
  2436. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  2437. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2438. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  2439. ucontrol->value.enumerated.item[0]);
  2440. }
  2441. return ret;
  2442. }
  2443. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  2444. struct snd_ctl_elem_value *ucontrol)
  2445. {
  2446. struct tdm_port port;
  2447. int ret = tdm_get_port_idx(kcontrol, &port);
  2448. if (ret) {
  2449. pr_err("%s: unsupported control: %s",
  2450. __func__, kcontrol->id.name);
  2451. } else {
  2452. tdm_rx_cfg[port.mode][port.channel].channels =
  2453. ucontrol->value.enumerated.item[0] + 1;
  2454. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  2455. tdm_rx_cfg[port.mode][port.channel].channels,
  2456. ucontrol->value.enumerated.item[0] + 1);
  2457. }
  2458. return ret;
  2459. }
  2460. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  2461. struct snd_ctl_elem_value *ucontrol)
  2462. {
  2463. struct tdm_port port;
  2464. int ret = tdm_get_port_idx(kcontrol, &port);
  2465. if (ret) {
  2466. pr_err("%s: unsupported control: %s",
  2467. __func__, kcontrol->id.name);
  2468. } else {
  2469. ucontrol->value.enumerated.item[0] =
  2470. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  2471. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2472. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  2473. ucontrol->value.enumerated.item[0]);
  2474. }
  2475. return ret;
  2476. }
  2477. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  2478. struct snd_ctl_elem_value *ucontrol)
  2479. {
  2480. struct tdm_port port;
  2481. int ret = tdm_get_port_idx(kcontrol, &port);
  2482. if (ret) {
  2483. pr_err("%s: unsupported control: %s",
  2484. __func__, kcontrol->id.name);
  2485. } else {
  2486. tdm_tx_cfg[port.mode][port.channel].channels =
  2487. ucontrol->value.enumerated.item[0] + 1;
  2488. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  2489. tdm_tx_cfg[port.mode][port.channel].channels,
  2490. ucontrol->value.enumerated.item[0] + 1);
  2491. }
  2492. return ret;
  2493. }
  2494. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  2495. {
  2496. int idx;
  2497. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  2498. sizeof("PRIM_AUX_PCM")))
  2499. idx = PRIM_AUX_PCM;
  2500. else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  2501. sizeof("SEC_AUX_PCM")))
  2502. idx = SEC_AUX_PCM;
  2503. else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  2504. sizeof("TERT_AUX_PCM")))
  2505. idx = TERT_AUX_PCM;
  2506. else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  2507. sizeof("QUAT_AUX_PCM")))
  2508. idx = QUAT_AUX_PCM;
  2509. else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  2510. sizeof("QUIN_AUX_PCM")))
  2511. idx = QUIN_AUX_PCM;
  2512. else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  2513. sizeof("SENN_AUX_PCM")))
  2514. idx = SEN_AUX_PCM;
  2515. else {
  2516. pr_err("%s: unsupported port: %s",
  2517. __func__, kcontrol->id.name);
  2518. idx = -EINVAL;
  2519. }
  2520. return idx;
  2521. }
  2522. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2523. struct snd_ctl_elem_value *ucontrol)
  2524. {
  2525. int idx = aux_pcm_get_port_idx(kcontrol);
  2526. if (idx < 0)
  2527. return idx;
  2528. aux_pcm_rx_cfg[idx].sample_rate =
  2529. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2530. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2531. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2532. ucontrol->value.enumerated.item[0]);
  2533. return 0;
  2534. }
  2535. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2536. struct snd_ctl_elem_value *ucontrol)
  2537. {
  2538. int idx = aux_pcm_get_port_idx(kcontrol);
  2539. if (idx < 0)
  2540. return idx;
  2541. ucontrol->value.enumerated.item[0] =
  2542. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  2543. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2544. idx, aux_pcm_rx_cfg[idx].sample_rate,
  2545. ucontrol->value.enumerated.item[0]);
  2546. return 0;
  2547. }
  2548. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2549. struct snd_ctl_elem_value *ucontrol)
  2550. {
  2551. int idx = aux_pcm_get_port_idx(kcontrol);
  2552. if (idx < 0)
  2553. return idx;
  2554. aux_pcm_tx_cfg[idx].sample_rate =
  2555. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2556. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2557. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2558. ucontrol->value.enumerated.item[0]);
  2559. return 0;
  2560. }
  2561. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2562. struct snd_ctl_elem_value *ucontrol)
  2563. {
  2564. int idx = aux_pcm_get_port_idx(kcontrol);
  2565. if (idx < 0)
  2566. return idx;
  2567. ucontrol->value.enumerated.item[0] =
  2568. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  2569. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2570. idx, aux_pcm_tx_cfg[idx].sample_rate,
  2571. ucontrol->value.enumerated.item[0]);
  2572. return 0;
  2573. }
  2574. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2575. {
  2576. int idx;
  2577. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  2578. sizeof("PRIM_MI2S_RX")))
  2579. idx = PRIM_MI2S;
  2580. else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  2581. sizeof("SEC_MI2S_RX")))
  2582. idx = SEC_MI2S;
  2583. else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  2584. sizeof("TERT_MI2S_RX")))
  2585. idx = TERT_MI2S;
  2586. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  2587. sizeof("QUAT_MI2S_RX")))
  2588. idx = QUAT_MI2S;
  2589. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  2590. sizeof("QUIN_MI2S_RX")))
  2591. idx = QUIN_MI2S;
  2592. else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  2593. sizeof("SEN_MI2S_RX")))
  2594. idx = SEN_MI2S;
  2595. else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  2596. sizeof("PRIM_MI2S_TX")))
  2597. idx = PRIM_MI2S;
  2598. else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  2599. sizeof("SEC_MI2S_TX")))
  2600. idx = SEC_MI2S;
  2601. else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  2602. sizeof("TERT_MI2S_TX")))
  2603. idx = TERT_MI2S;
  2604. else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  2605. sizeof("QUAT_MI2S_TX")))
  2606. idx = QUAT_MI2S;
  2607. else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  2608. sizeof("QUIN_MI2S_TX")))
  2609. idx = QUIN_MI2S;
  2610. else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  2611. sizeof("SEN_MI2S_TX")))
  2612. idx = SEN_MI2S;
  2613. else {
  2614. pr_err("%s: unsupported channel: %s",
  2615. __func__, kcontrol->id.name);
  2616. idx = -EINVAL;
  2617. }
  2618. return idx;
  2619. }
  2620. static int mi2s_get_sample_rate_val(int sample_rate)
  2621. {
  2622. int sample_rate_val;
  2623. switch (sample_rate) {
  2624. case SAMPLING_RATE_8KHZ:
  2625. sample_rate_val = 0;
  2626. break;
  2627. case SAMPLING_RATE_11P025KHZ:
  2628. sample_rate_val = 1;
  2629. break;
  2630. case SAMPLING_RATE_16KHZ:
  2631. sample_rate_val = 2;
  2632. break;
  2633. case SAMPLING_RATE_22P05KHZ:
  2634. sample_rate_val = 3;
  2635. break;
  2636. case SAMPLING_RATE_32KHZ:
  2637. sample_rate_val = 4;
  2638. break;
  2639. case SAMPLING_RATE_44P1KHZ:
  2640. sample_rate_val = 5;
  2641. break;
  2642. case SAMPLING_RATE_48KHZ:
  2643. sample_rate_val = 6;
  2644. break;
  2645. case SAMPLING_RATE_88P2KHZ:
  2646. sample_rate_val = 7;
  2647. break;
  2648. case SAMPLING_RATE_96KHZ:
  2649. sample_rate_val = 8;
  2650. break;
  2651. case SAMPLING_RATE_176P4KHZ:
  2652. sample_rate_val = 9;
  2653. break;
  2654. case SAMPLING_RATE_192KHZ:
  2655. sample_rate_val = 10;
  2656. break;
  2657. case SAMPLING_RATE_352P8KHZ:
  2658. sample_rate_val = 11;
  2659. break;
  2660. case SAMPLING_RATE_384KHZ:
  2661. sample_rate_val = 12;
  2662. break;
  2663. default:
  2664. sample_rate_val = 6;
  2665. break;
  2666. }
  2667. return sample_rate_val;
  2668. }
  2669. static int mi2s_get_sample_rate(int value)
  2670. {
  2671. int sample_rate;
  2672. switch (value) {
  2673. case 0:
  2674. sample_rate = SAMPLING_RATE_8KHZ;
  2675. break;
  2676. case 1:
  2677. sample_rate = SAMPLING_RATE_11P025KHZ;
  2678. break;
  2679. case 2:
  2680. sample_rate = SAMPLING_RATE_16KHZ;
  2681. break;
  2682. case 3:
  2683. sample_rate = SAMPLING_RATE_22P05KHZ;
  2684. break;
  2685. case 4:
  2686. sample_rate = SAMPLING_RATE_32KHZ;
  2687. break;
  2688. case 5:
  2689. sample_rate = SAMPLING_RATE_44P1KHZ;
  2690. break;
  2691. case 6:
  2692. sample_rate = SAMPLING_RATE_48KHZ;
  2693. break;
  2694. case 7:
  2695. sample_rate = SAMPLING_RATE_88P2KHZ;
  2696. break;
  2697. case 8:
  2698. sample_rate = SAMPLING_RATE_96KHZ;
  2699. break;
  2700. case 9:
  2701. sample_rate = SAMPLING_RATE_176P4KHZ;
  2702. break;
  2703. case 10:
  2704. sample_rate = SAMPLING_RATE_192KHZ;
  2705. break;
  2706. case 11:
  2707. sample_rate = SAMPLING_RATE_352P8KHZ;
  2708. break;
  2709. case 12:
  2710. sample_rate = SAMPLING_RATE_384KHZ;
  2711. break;
  2712. default:
  2713. sample_rate = SAMPLING_RATE_48KHZ;
  2714. break;
  2715. }
  2716. return sample_rate;
  2717. }
  2718. static int mi2s_auxpcm_get_format(int value)
  2719. {
  2720. int format;
  2721. switch (value) {
  2722. case 0:
  2723. format = SNDRV_PCM_FORMAT_S16_LE;
  2724. break;
  2725. case 1:
  2726. format = SNDRV_PCM_FORMAT_S24_LE;
  2727. break;
  2728. case 2:
  2729. format = SNDRV_PCM_FORMAT_S24_3LE;
  2730. break;
  2731. case 3:
  2732. format = SNDRV_PCM_FORMAT_S32_LE;
  2733. break;
  2734. default:
  2735. format = SNDRV_PCM_FORMAT_S16_LE;
  2736. break;
  2737. }
  2738. return format;
  2739. }
  2740. static int mi2s_auxpcm_get_format_value(int format)
  2741. {
  2742. int value;
  2743. switch (format) {
  2744. case SNDRV_PCM_FORMAT_S16_LE:
  2745. value = 0;
  2746. break;
  2747. case SNDRV_PCM_FORMAT_S24_LE:
  2748. value = 1;
  2749. break;
  2750. case SNDRV_PCM_FORMAT_S24_3LE:
  2751. value = 2;
  2752. break;
  2753. case SNDRV_PCM_FORMAT_S32_LE:
  2754. value = 3;
  2755. break;
  2756. default:
  2757. value = 0;
  2758. break;
  2759. }
  2760. return value;
  2761. }
  2762. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2763. struct snd_ctl_elem_value *ucontrol)
  2764. {
  2765. int idx = mi2s_get_port_idx(kcontrol);
  2766. if (idx < 0)
  2767. return idx;
  2768. mi2s_rx_cfg[idx].sample_rate =
  2769. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2770. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2771. idx, mi2s_rx_cfg[idx].sample_rate,
  2772. ucontrol->value.enumerated.item[0]);
  2773. return 0;
  2774. }
  2775. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2776. struct snd_ctl_elem_value *ucontrol)
  2777. {
  2778. int idx = mi2s_get_port_idx(kcontrol);
  2779. if (idx < 0)
  2780. return idx;
  2781. ucontrol->value.enumerated.item[0] =
  2782. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  2783. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2784. idx, mi2s_rx_cfg[idx].sample_rate,
  2785. ucontrol->value.enumerated.item[0]);
  2786. return 0;
  2787. }
  2788. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2789. struct snd_ctl_elem_value *ucontrol)
  2790. {
  2791. int idx = mi2s_get_port_idx(kcontrol);
  2792. if (idx < 0)
  2793. return idx;
  2794. mi2s_tx_cfg[idx].sample_rate =
  2795. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2796. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2797. idx, mi2s_tx_cfg[idx].sample_rate,
  2798. ucontrol->value.enumerated.item[0]);
  2799. return 0;
  2800. }
  2801. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2802. struct snd_ctl_elem_value *ucontrol)
  2803. {
  2804. int idx = mi2s_get_port_idx(kcontrol);
  2805. if (idx < 0)
  2806. return idx;
  2807. ucontrol->value.enumerated.item[0] =
  2808. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  2809. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  2810. idx, mi2s_tx_cfg[idx].sample_rate,
  2811. ucontrol->value.enumerated.item[0]);
  2812. return 0;
  2813. }
  2814. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2815. struct snd_ctl_elem_value *ucontrol)
  2816. {
  2817. int idx = mi2s_get_port_idx(kcontrol);
  2818. if (idx < 0)
  2819. return idx;
  2820. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2821. idx, mi2s_rx_cfg[idx].channels);
  2822. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2823. return 0;
  2824. }
  2825. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2826. struct snd_ctl_elem_value *ucontrol)
  2827. {
  2828. int idx = mi2s_get_port_idx(kcontrol);
  2829. if (idx < 0)
  2830. return idx;
  2831. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2832. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2833. idx, mi2s_rx_cfg[idx].channels);
  2834. return 1;
  2835. }
  2836. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2837. struct snd_ctl_elem_value *ucontrol)
  2838. {
  2839. int idx = mi2s_get_port_idx(kcontrol);
  2840. if (idx < 0)
  2841. return idx;
  2842. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2843. idx, mi2s_tx_cfg[idx].channels);
  2844. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2845. return 0;
  2846. }
  2847. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2848. struct snd_ctl_elem_value *ucontrol)
  2849. {
  2850. int idx = mi2s_get_port_idx(kcontrol);
  2851. if (idx < 0)
  2852. return idx;
  2853. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2854. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2855. idx, mi2s_tx_cfg[idx].channels);
  2856. return 1;
  2857. }
  2858. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  2859. struct snd_ctl_elem_value *ucontrol)
  2860. {
  2861. int idx = mi2s_get_port_idx(kcontrol);
  2862. if (idx < 0)
  2863. return idx;
  2864. ucontrol->value.enumerated.item[0] =
  2865. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  2866. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2867. idx, mi2s_rx_cfg[idx].bit_format,
  2868. ucontrol->value.enumerated.item[0]);
  2869. return 0;
  2870. }
  2871. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  2872. struct snd_ctl_elem_value *ucontrol)
  2873. {
  2874. struct msm_asoc_mach_data *pdata = NULL;
  2875. struct snd_soc_component *component = NULL;
  2876. struct snd_soc_card *card = NULL;
  2877. int idx = mi2s_get_port_idx(kcontrol);
  2878. component = snd_soc_kcontrol_component(kcontrol);
  2879. card = kcontrol->private_data;
  2880. pdata = snd_soc_card_get_drvdata(card);
  2881. if (idx < 0)
  2882. return idx;
  2883. /* check for PRIM_MI2S and CSRAx config to allow 24bit BE config only */
  2884. if ((idx == PRIM_MI2S) && (pdata->codec_is_csra == true)
  2885. && mi2s_rx_cfg[idx].data_format != AFE_DSD_DATA)
  2886. {
  2887. mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2888. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  2889. __func__, idx, mi2s_rx_cfg[idx].bit_format,
  2890. ucontrol->value.enumerated.item[0]);
  2891. } else {
  2892. mi2s_rx_cfg[idx].bit_format =
  2893. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2894. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2895. idx, mi2s_rx_cfg[idx].bit_format,
  2896. ucontrol->value.enumerated.item[0]);
  2897. }
  2898. return 0;
  2899. }
  2900. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  2901. struct snd_ctl_elem_value *ucontrol)
  2902. {
  2903. int idx = mi2s_get_port_idx(kcontrol);
  2904. if (idx < 0)
  2905. return idx;
  2906. ucontrol->value.enumerated.item[0] =
  2907. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2908. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2909. idx, mi2s_tx_cfg[idx].bit_format,
  2910. ucontrol->value.enumerated.item[0]);
  2911. return 0;
  2912. }
  2913. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2914. struct snd_ctl_elem_value *ucontrol)
  2915. {
  2916. int idx = mi2s_get_port_idx(kcontrol);
  2917. if (idx < 0)
  2918. return idx;
  2919. mi2s_tx_cfg[idx].bit_format =
  2920. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2921. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2922. idx, mi2s_tx_cfg[idx].bit_format,
  2923. ucontrol->value.enumerated.item[0]);
  2924. return 0;
  2925. }
  2926. static int msm_mi2s_tx_data_format_put(struct snd_kcontrol *kcontrol,
  2927. struct snd_ctl_elem_value *ucontrol)
  2928. {
  2929. int idx = mi2s_get_port_idx(kcontrol);
  2930. if (idx < 0)
  2931. return idx;
  2932. mi2s_tx_cfg[idx].data_format = ucontrol->value.enumerated.item[0];
  2933. pr_debug("%s: idx[%d]_data_format = %d, item = %d\n", __func__,
  2934. idx, mi2s_tx_cfg[idx].data_format,
  2935. ucontrol->value.enumerated.item[0]);
  2936. return 0;
  2937. }
  2938. static int msm_mi2s_rx_data_format_put(struct snd_kcontrol *kcontrol,
  2939. struct snd_ctl_elem_value *ucontrol)
  2940. {
  2941. int idx = mi2s_get_port_idx(kcontrol);
  2942. if (idx < 0)
  2943. return idx;
  2944. mi2s_rx_cfg[idx].data_format = ucontrol->value.enumerated.item[0];
  2945. pr_debug("%s: idx[%d]_data_format = %d, item = %d\n", __func__,
  2946. idx, mi2s_rx_cfg[idx].data_format,
  2947. ucontrol->value.enumerated.item[0]);
  2948. return 0;
  2949. }
  2950. static int msm_mi2s_tx_data_format_get(struct snd_kcontrol *kcontrol,
  2951. struct snd_ctl_elem_value *ucontrol)
  2952. {
  2953. int idx = mi2s_get_port_idx(kcontrol);
  2954. if (idx < 0)
  2955. return idx;
  2956. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].data_format;
  2957. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2958. idx, mi2s_tx_cfg[idx].data_format,
  2959. ucontrol->value.enumerated.item[0]);
  2960. return 0;
  2961. }
  2962. static int msm_mi2s_rx_data_format_get(struct snd_kcontrol *kcontrol,
  2963. struct snd_ctl_elem_value *ucontrol)
  2964. {
  2965. int idx = mi2s_get_port_idx(kcontrol);
  2966. if (idx < 0)
  2967. return idx;
  2968. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].data_format;
  2969. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  2970. idx, mi2s_rx_cfg[idx].data_format,
  2971. ucontrol->value.enumerated.item[0]);
  2972. return 0;
  2973. }
  2974. static int msm_meta_mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  2975. {
  2976. int idx = 0;
  2977. if (strnstr(kcontrol->id.name, "PRIM_META_MI2S_RX",
  2978. sizeof("PRIM_META_MI2S_RX"))) {
  2979. idx = PRIM_META_MI2S;
  2980. } else if (strnstr(kcontrol->id.name, "SEC_META_MI2S_RX",
  2981. sizeof("SEC_META_MI2S_RX"))) {
  2982. idx = SEC_META_MI2S;
  2983. } else {
  2984. pr_err("%s: unsupported port: %s",
  2985. __func__, kcontrol->id.name);
  2986. idx = -EINVAL;
  2987. }
  2988. return idx;
  2989. }
  2990. static int msm_meta_mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2991. struct snd_ctl_elem_value *ucontrol)
  2992. {
  2993. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  2994. if (idx < 0)
  2995. return idx;
  2996. ucontrol->value.enumerated.item[0] =
  2997. mi2s_get_sample_rate_val(meta_mi2s_rx_cfg[idx].sample_rate);
  2998. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  2999. idx, meta_mi2s_rx_cfg[idx].sample_rate,
  3000. ucontrol->value.enumerated.item[0]);
  3001. return 0;
  3002. }
  3003. static int msm_meta_mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  3004. struct snd_ctl_elem_value *ucontrol)
  3005. {
  3006. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  3007. if (idx < 0)
  3008. return idx;
  3009. meta_mi2s_rx_cfg[idx].sample_rate =
  3010. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  3011. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  3012. idx, meta_mi2s_rx_cfg[idx].sample_rate,
  3013. ucontrol->value.enumerated.item[0]);
  3014. return 0;
  3015. }
  3016. static int msm_meta_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  3017. struct snd_ctl_elem_value *ucontrol)
  3018. {
  3019. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  3020. if (idx < 0)
  3021. return idx;
  3022. ucontrol->value.enumerated.item[0] = meta_mi2s_rx_cfg[idx].channels - 1;
  3023. pr_debug("%s: meta_mi2s_[%d]_rx_ch = %d\n", __func__,
  3024. idx, meta_mi2s_rx_cfg[idx].channels);
  3025. return 0;
  3026. }
  3027. static int msm_meta_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  3028. struct snd_ctl_elem_value *ucontrol)
  3029. {
  3030. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  3031. if (idx < 0)
  3032. return idx;
  3033. meta_mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  3034. pr_debug("%s: meta_mi2s_[%d]_rx_ch = %d\n", __func__,
  3035. idx, meta_mi2s_rx_cfg[idx].channels);
  3036. return 1;
  3037. }
  3038. static int msm_meta_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  3039. struct snd_ctl_elem_value *ucontrol)
  3040. {
  3041. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  3042. if (idx < 0)
  3043. return idx;
  3044. ucontrol->value.enumerated.item[0] =
  3045. mi2s_auxpcm_get_format_value(meta_mi2s_rx_cfg[idx].bit_format);
  3046. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  3047. idx, meta_mi2s_rx_cfg[idx].bit_format,
  3048. ucontrol->value.enumerated.item[0]);
  3049. return 0;
  3050. }
  3051. static int msm_meta_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  3052. struct snd_ctl_elem_value *ucontrol)
  3053. {
  3054. struct msm_asoc_mach_data *pdata = NULL;
  3055. struct snd_soc_card *card = NULL;
  3056. int idx = msm_meta_mi2s_get_port_idx(kcontrol);
  3057. card = kcontrol->private_data;
  3058. pdata = snd_soc_card_get_drvdata(card);
  3059. if (idx < 0)
  3060. return idx;
  3061. /* check for PRIM_META_MI2S and CSRAx to allow 24bit BE config only */
  3062. if ((idx == PRIM_META_MI2S) && pdata->codec_is_csra) {
  3063. meta_mi2s_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  3064. pr_debug("%s: Keeping default format idx[%d]_rx_format = %d, item = %d\n",
  3065. __func__, idx, meta_mi2s_rx_cfg[idx].bit_format,
  3066. ucontrol->value.enumerated.item[0]);
  3067. } else {
  3068. meta_mi2s_rx_cfg[idx].bit_format =
  3069. mi2s_auxpcm_get_format(
  3070. ucontrol->value.enumerated.item[0]);
  3071. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  3072. idx, meta_mi2s_rx_cfg[idx].bit_format,
  3073. ucontrol->value.enumerated.item[0]);
  3074. }
  3075. return 0;
  3076. }
  3077. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  3078. struct snd_ctl_elem_value *ucontrol)
  3079. {
  3080. int idx = aux_pcm_get_port_idx(kcontrol);
  3081. if (idx < 0)
  3082. return idx;
  3083. ucontrol->value.enumerated.item[0] =
  3084. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  3085. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  3086. idx, aux_pcm_rx_cfg[idx].bit_format,
  3087. ucontrol->value.enumerated.item[0]);
  3088. return 0;
  3089. }
  3090. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  3091. struct snd_ctl_elem_value *ucontrol)
  3092. {
  3093. int idx = aux_pcm_get_port_idx(kcontrol);
  3094. if (idx < 0)
  3095. return idx;
  3096. aux_pcm_rx_cfg[idx].bit_format =
  3097. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  3098. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  3099. idx, aux_pcm_rx_cfg[idx].bit_format,
  3100. ucontrol->value.enumerated.item[0]);
  3101. return 0;
  3102. }
  3103. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  3104. struct snd_ctl_elem_value *ucontrol)
  3105. {
  3106. int idx = aux_pcm_get_port_idx(kcontrol);
  3107. if (idx < 0)
  3108. return idx;
  3109. ucontrol->value.enumerated.item[0] =
  3110. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  3111. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  3112. idx, aux_pcm_tx_cfg[idx].bit_format,
  3113. ucontrol->value.enumerated.item[0]);
  3114. return 0;
  3115. }
  3116. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  3117. struct snd_ctl_elem_value *ucontrol)
  3118. {
  3119. int idx = aux_pcm_get_port_idx(kcontrol);
  3120. if (idx < 0)
  3121. return idx;
  3122. aux_pcm_tx_cfg[idx].bit_format =
  3123. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  3124. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  3125. idx, aux_pcm_tx_cfg[idx].bit_format,
  3126. ucontrol->value.enumerated.item[0]);
  3127. return 0;
  3128. }
  3129. static int spdif_get_port_idx(struct snd_kcontrol *kcontrol)
  3130. {
  3131. int idx;
  3132. if (strnstr(kcontrol->id.name, "PRIM_SPDIF_RX",
  3133. sizeof("PRIM_SPDIF_RX")))
  3134. idx = PRIM_SPDIF_RX;
  3135. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_RX",
  3136. sizeof("SEC_SPDIF_RX")))
  3137. idx = SEC_SPDIF_RX;
  3138. else if (strnstr(kcontrol->id.name, "PRIM_SPDIF_TX",
  3139. sizeof("PRIM_SPDIF_TX")))
  3140. idx = PRIM_SPDIF_TX;
  3141. else if (strnstr(kcontrol->id.name, "SEC_SPDIF_TX",
  3142. sizeof("SEC_SPDIF_TX")))
  3143. idx = SEC_SPDIF_TX;
  3144. else {
  3145. pr_err("%s: unsupported channel: %s",
  3146. __func__, kcontrol->id.name);
  3147. idx = -EINVAL;
  3148. }
  3149. return idx;
  3150. }
  3151. static int spdif_get_sample_rate_val(int sample_rate)
  3152. {
  3153. int sample_rate_val;
  3154. switch (sample_rate) {
  3155. case SAMPLING_RATE_32KHZ:
  3156. sample_rate_val = 0;
  3157. break;
  3158. case SAMPLING_RATE_44P1KHZ:
  3159. sample_rate_val = 1;
  3160. break;
  3161. case SAMPLING_RATE_48KHZ:
  3162. sample_rate_val = 2;
  3163. break;
  3164. case SAMPLING_RATE_88P2KHZ:
  3165. sample_rate_val = 3;
  3166. break;
  3167. case SAMPLING_RATE_96KHZ:
  3168. sample_rate_val = 4;
  3169. break;
  3170. case SAMPLING_RATE_176P4KHZ:
  3171. sample_rate_val = 5;
  3172. break;
  3173. case SAMPLING_RATE_192KHZ:
  3174. sample_rate_val = 6;
  3175. break;
  3176. default:
  3177. sample_rate_val = 2;
  3178. break;
  3179. }
  3180. return sample_rate_val;
  3181. }
  3182. static int spdif_get_sample_rate(int value)
  3183. {
  3184. int sample_rate;
  3185. switch (value) {
  3186. case 0:
  3187. sample_rate = SAMPLING_RATE_32KHZ;
  3188. break;
  3189. case 1:
  3190. sample_rate = SAMPLING_RATE_44P1KHZ;
  3191. break;
  3192. case 2:
  3193. sample_rate = SAMPLING_RATE_48KHZ;
  3194. break;
  3195. case 3:
  3196. sample_rate = SAMPLING_RATE_88P2KHZ;
  3197. break;
  3198. case 4:
  3199. sample_rate = SAMPLING_RATE_96KHZ;
  3200. break;
  3201. case 5:
  3202. sample_rate = SAMPLING_RATE_176P4KHZ;
  3203. break;
  3204. case 6:
  3205. sample_rate = SAMPLING_RATE_192KHZ;
  3206. break;
  3207. default:
  3208. sample_rate = SAMPLING_RATE_48KHZ;
  3209. break;
  3210. }
  3211. return sample_rate;
  3212. }
  3213. static int spdif_get_format(int value)
  3214. {
  3215. int format;
  3216. switch (value) {
  3217. case 0:
  3218. format = SNDRV_PCM_FORMAT_S16_LE;
  3219. break;
  3220. case 1:
  3221. format = SNDRV_PCM_FORMAT_S24_LE;
  3222. break;
  3223. default:
  3224. format = SNDRV_PCM_FORMAT_S16_LE;
  3225. break;
  3226. }
  3227. return format;
  3228. }
  3229. static int spdif_get_format_value(int format)
  3230. {
  3231. int value;
  3232. switch (format) {
  3233. case SNDRV_PCM_FORMAT_S16_LE:
  3234. value = 0;
  3235. break;
  3236. case SNDRV_PCM_FORMAT_S24_LE:
  3237. value = 1;
  3238. break;
  3239. default:
  3240. value = 0;
  3241. break;
  3242. }
  3243. return value;
  3244. }
  3245. static int msm_spdif_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  3246. struct snd_ctl_elem_value *ucontrol)
  3247. {
  3248. int idx = spdif_get_port_idx(kcontrol);
  3249. if (idx < 0)
  3250. return idx;
  3251. spdif_rx_cfg[idx].sample_rate =
  3252. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  3253. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  3254. idx, spdif_rx_cfg[idx].sample_rate,
  3255. ucontrol->value.enumerated.item[0]);
  3256. return 0;
  3257. }
  3258. static int msm_spdif_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  3259. struct snd_ctl_elem_value *ucontrol)
  3260. {
  3261. int idx = spdif_get_port_idx(kcontrol);
  3262. if (idx < 0)
  3263. return idx;
  3264. ucontrol->value.enumerated.item[0] =
  3265. spdif_get_sample_rate_val(spdif_rx_cfg[idx].sample_rate);
  3266. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  3267. idx, spdif_rx_cfg[idx].sample_rate,
  3268. ucontrol->value.enumerated.item[0]);
  3269. return 0;
  3270. }
  3271. static int msm_spdif_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  3272. struct snd_ctl_elem_value *ucontrol)
  3273. {
  3274. int idx = spdif_get_port_idx(kcontrol);
  3275. if (idx < 0)
  3276. return idx;
  3277. spdif_tx_cfg[idx].sample_rate =
  3278. spdif_get_sample_rate(ucontrol->value.enumerated.item[0]);
  3279. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  3280. idx, spdif_tx_cfg[idx].sample_rate,
  3281. ucontrol->value.enumerated.item[0]);
  3282. return 0;
  3283. }
  3284. static int msm_spdif_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  3285. struct snd_ctl_elem_value *ucontrol)
  3286. {
  3287. int idx = spdif_get_port_idx(kcontrol);
  3288. if (idx < 0)
  3289. return idx;
  3290. ucontrol->value.enumerated.item[0] =
  3291. spdif_get_sample_rate_val(spdif_tx_cfg[idx].sample_rate);
  3292. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  3293. idx, spdif_tx_cfg[idx].sample_rate,
  3294. ucontrol->value.enumerated.item[0]);
  3295. return 0;
  3296. }
  3297. static int msm_spdif_rx_ch_get(struct snd_kcontrol *kcontrol,
  3298. struct snd_ctl_elem_value *ucontrol)
  3299. {
  3300. int idx = spdif_get_port_idx(kcontrol);
  3301. if (idx < 0)
  3302. return idx;
  3303. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  3304. idx, spdif_rx_cfg[idx].channels);
  3305. ucontrol->value.enumerated.item[0] = spdif_rx_cfg[idx].channels - 1;
  3306. return 0;
  3307. }
  3308. static int msm_spdif_rx_ch_put(struct snd_kcontrol *kcontrol,
  3309. struct snd_ctl_elem_value *ucontrol)
  3310. {
  3311. int idx = spdif_get_port_idx(kcontrol);
  3312. if (idx < 0)
  3313. return idx;
  3314. spdif_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  3315. pr_debug("%s: msm_spdif_[%d]_rx_ch = %d\n", __func__,
  3316. idx, spdif_rx_cfg[idx].channels);
  3317. return 1;
  3318. }
  3319. static int msm_spdif_tx_ch_get(struct snd_kcontrol *kcontrol,
  3320. struct snd_ctl_elem_value *ucontrol)
  3321. {
  3322. int idx = spdif_get_port_idx(kcontrol);
  3323. if (idx < 0)
  3324. return idx;
  3325. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  3326. idx, spdif_tx_cfg[idx].channels);
  3327. ucontrol->value.enumerated.item[0] = spdif_tx_cfg[idx].channels - 1;
  3328. return 0;
  3329. }
  3330. static int msm_spdif_tx_ch_put(struct snd_kcontrol *kcontrol,
  3331. struct snd_ctl_elem_value *ucontrol)
  3332. {
  3333. int idx = spdif_get_port_idx(kcontrol);
  3334. if (idx < 0)
  3335. return idx;
  3336. spdif_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  3337. pr_debug("%s: msm_spdif_[%d]_tx_ch = %d\n", __func__,
  3338. idx, spdif_tx_cfg[idx].channels);
  3339. return 1;
  3340. }
  3341. static int msm_spdif_rx_format_get(struct snd_kcontrol *kcontrol,
  3342. struct snd_ctl_elem_value *ucontrol)
  3343. {
  3344. int idx = spdif_get_port_idx(kcontrol);
  3345. if (idx < 0)
  3346. return idx;
  3347. ucontrol->value.enumerated.item[0] =
  3348. spdif_get_format_value(spdif_rx_cfg[idx].bit_format);
  3349. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  3350. idx, spdif_rx_cfg[idx].bit_format,
  3351. ucontrol->value.enumerated.item[0]);
  3352. return 0;
  3353. }
  3354. static int msm_spdif_rx_format_put(struct snd_kcontrol *kcontrol,
  3355. struct snd_ctl_elem_value *ucontrol)
  3356. {
  3357. int idx = spdif_get_port_idx(kcontrol);
  3358. if (idx < 0)
  3359. return idx;
  3360. spdif_rx_cfg[idx].bit_format =
  3361. spdif_get_format(ucontrol->value.enumerated.item[0]);
  3362. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  3363. idx, spdif_rx_cfg[idx].bit_format,
  3364. ucontrol->value.enumerated.item[0]);
  3365. return 0;
  3366. }
  3367. static int msm_spdif_tx_format_get(struct snd_kcontrol *kcontrol,
  3368. struct snd_ctl_elem_value *ucontrol)
  3369. {
  3370. int idx = spdif_get_port_idx(kcontrol);
  3371. if (idx < 0)
  3372. return idx;
  3373. ucontrol->value.enumerated.item[0] =
  3374. spdif_get_format_value(spdif_tx_cfg[idx].bit_format);
  3375. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  3376. idx, spdif_tx_cfg[idx].bit_format,
  3377. ucontrol->value.enumerated.item[0]);
  3378. return 0;
  3379. }
  3380. static int msm_spdif_tx_format_put(struct snd_kcontrol *kcontrol,
  3381. struct snd_ctl_elem_value *ucontrol)
  3382. {
  3383. int idx = spdif_get_port_idx(kcontrol);
  3384. if (idx < 0)
  3385. return idx;
  3386. spdif_tx_cfg[idx].bit_format =
  3387. spdif_get_format(ucontrol->value.enumerated.item[0]);
  3388. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  3389. idx, spdif_tx_cfg[idx].bit_format,
  3390. ucontrol->value.enumerated.item[0]);
  3391. return 0;
  3392. }
  3393. static int afe_lb_tx_ch_get(struct snd_kcontrol *kcontrol,
  3394. struct snd_ctl_elem_value *ucontrol)
  3395. {
  3396. pr_debug("%s: afe_lb_tx_ch = %d\n", __func__,
  3397. afe_lb_tx_cfg.channels);
  3398. ucontrol->value.integer.value[0] = afe_lb_tx_cfg.channels - 1;
  3399. return 0;
  3400. }
  3401. static int afe_lb_tx_ch_put(struct snd_kcontrol *kcontrol,
  3402. struct snd_ctl_elem_value *ucontrol)
  3403. {
  3404. afe_lb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  3405. pr_debug("%s: afe_lb_tx_ch = %d\n", __func__, afe_lb_tx_cfg.channels);
  3406. return 0;
  3407. }
  3408. static int afe_lb_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  3409. struct snd_ctl_elem_value *ucontrol)
  3410. {
  3411. int sample_rate_val;
  3412. switch (afe_lb_tx_cfg.sample_rate) {
  3413. case SAMPLING_RATE_384KHZ:
  3414. sample_rate_val = 12;
  3415. break;
  3416. case SAMPLING_RATE_352P8KHZ:
  3417. sample_rate_val = 11;
  3418. break;
  3419. case SAMPLING_RATE_192KHZ:
  3420. sample_rate_val = 10;
  3421. break;
  3422. case SAMPLING_RATE_176P4KHZ:
  3423. sample_rate_val = 9;
  3424. break;
  3425. case SAMPLING_RATE_96KHZ:
  3426. sample_rate_val = 8;
  3427. break;
  3428. case SAMPLING_RATE_88P2KHZ:
  3429. sample_rate_val = 7;
  3430. break;
  3431. case SAMPLING_RATE_48KHZ:
  3432. sample_rate_val = 6;
  3433. break;
  3434. case SAMPLING_RATE_44P1KHZ:
  3435. sample_rate_val = 5;
  3436. break;
  3437. case SAMPLING_RATE_32KHZ:
  3438. sample_rate_val = 4;
  3439. break;
  3440. case SAMPLING_RATE_22P05KHZ:
  3441. sample_rate_val = 3;
  3442. break;
  3443. case SAMPLING_RATE_16KHZ:
  3444. sample_rate_val = 2;
  3445. break;
  3446. case SAMPLING_RATE_11P025KHZ:
  3447. sample_rate_val = 1;
  3448. break;
  3449. case SAMPLING_RATE_8KHZ:
  3450. sample_rate_val = 0;
  3451. break;
  3452. default:
  3453. sample_rate_val = 6;
  3454. break;
  3455. }
  3456. ucontrol->value.integer.value[0] = sample_rate_val;
  3457. pr_debug("%s: afe_lb_tx_sample_rate = %d\n", __func__,
  3458. afe_lb_tx_cfg.sample_rate);
  3459. return 0;
  3460. }
  3461. static int afe_lb_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  3462. struct snd_ctl_elem_value *ucontrol)
  3463. {
  3464. switch (ucontrol->value.integer.value[0]) {
  3465. case 12:
  3466. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  3467. break;
  3468. case 11:
  3469. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  3470. break;
  3471. case 10:
  3472. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  3473. break;
  3474. case 9:
  3475. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  3476. break;
  3477. case 8:
  3478. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  3479. break;
  3480. case 7:
  3481. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  3482. break;
  3483. case 6:
  3484. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  3485. break;
  3486. case 5:
  3487. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  3488. break;
  3489. case 4:
  3490. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  3491. break;
  3492. case 3:
  3493. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  3494. break;
  3495. case 2:
  3496. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  3497. break;
  3498. case 1:
  3499. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  3500. break;
  3501. case 0:
  3502. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  3503. break;
  3504. default:
  3505. afe_lb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  3506. break;
  3507. }
  3508. pr_debug("%s: control value = %ld, afe_lb_tx_sample_rate = %d\n",
  3509. __func__, ucontrol->value.integer.value[0],
  3510. afe_lb_tx_cfg.sample_rate);
  3511. return 0;
  3512. }
  3513. static int afe_lb_tx_format_get(struct snd_kcontrol *kcontrol,
  3514. struct snd_ctl_elem_value *ucontrol)
  3515. {
  3516. switch (afe_lb_tx_cfg.bit_format) {
  3517. case SNDRV_PCM_FORMAT_S32_LE:
  3518. ucontrol->value.integer.value[0] = 3;
  3519. break;
  3520. case SNDRV_PCM_FORMAT_S24_3LE:
  3521. ucontrol->value.integer.value[0] = 2;
  3522. break;
  3523. case SNDRV_PCM_FORMAT_S24_LE:
  3524. ucontrol->value.integer.value[0] = 1;
  3525. break;
  3526. case SNDRV_PCM_FORMAT_S16_LE:
  3527. default:
  3528. ucontrol->value.integer.value[0] = 0;
  3529. break;
  3530. }
  3531. pr_debug("%s: afe_lb_tx_format = %d, ucontrol value = %ld\n",
  3532. __func__, afe_lb_tx_cfg.bit_format,
  3533. ucontrol->value.integer.value[0]);
  3534. return 0;
  3535. }
  3536. static int afe_lb_tx_format_put(struct snd_kcontrol *kcontrol,
  3537. struct snd_ctl_elem_value *ucontrol)
  3538. {
  3539. switch (ucontrol->value.integer.value[0]) {
  3540. case 3:
  3541. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  3542. break;
  3543. case 2:
  3544. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  3545. break;
  3546. case 1:
  3547. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  3548. break;
  3549. case 0:
  3550. default:
  3551. afe_lb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  3552. break;
  3553. }
  3554. pr_debug("%s: afe_lb_tx_format = %d, ucontrol value = %ld\n",
  3555. __func__, afe_lb_tx_cfg.bit_format,
  3556. ucontrol->value.integer.value[0]);
  3557. return 0;
  3558. }
  3559. static const struct snd_kcontrol_new msm_snd_sb_controls[] = {
  3560. SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
  3561. slim_rx_ch_get, slim_rx_ch_put),
  3562. SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
  3563. slim_rx_ch_get, slim_rx_ch_put),
  3564. SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
  3565. slim_tx_ch_get, slim_tx_ch_put),
  3566. SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
  3567. slim_tx_ch_get, slim_tx_ch_put),
  3568. SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
  3569. slim_rx_ch_get, slim_rx_ch_put),
  3570. SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
  3571. slim_rx_ch_get, slim_rx_ch_put),
  3572. SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
  3573. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3574. SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
  3575. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3576. SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
  3577. slim_rx_bit_format_get, slim_rx_bit_format_put),
  3578. SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
  3579. slim_tx_bit_format_get, slim_tx_bit_format_put),
  3580. SOC_ENUM_EXT("HDMI_RX Bit Format", ext_hdmi_rx_format,
  3581. ext_hdmi_rx_format_get, ext_hdmi_rx_format_put),
  3582. SOC_ENUM_EXT("HDMI_RX SampleRate", ext_hdmi_rx_sample_rate,
  3583. ext_hdmi_rx_sample_rate_get,
  3584. ext_hdmi_rx_sample_rate_put),
  3585. SOC_ENUM_EXT("HDMI_RX Channels", ext_hdmi_rx_chs,
  3586. ext_hdmi_rx_ch_get,
  3587. ext_hdmi_rx_ch_put),
  3588. SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
  3589. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3590. SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
  3591. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3592. SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
  3593. slim_tx_sample_rate_get, slim_tx_sample_rate_put),
  3594. SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
  3595. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3596. SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
  3597. slim_rx_sample_rate_get, slim_rx_sample_rate_put),
  3598. };
  3599. static const struct snd_kcontrol_new msm_snd_va_controls[] = {
  3600. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  3601. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3602. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  3603. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3604. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  3605. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3606. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  3607. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3608. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3609. va_cdc_dma_tx_0_sample_rate,
  3610. cdc_dma_tx_sample_rate_get,
  3611. cdc_dma_tx_sample_rate_put),
  3612. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3613. va_cdc_dma_tx_1_sample_rate,
  3614. cdc_dma_tx_sample_rate_get,
  3615. cdc_dma_tx_sample_rate_put),
  3616. };
  3617. static const struct snd_kcontrol_new msm_snd_wsa_controls[] = {
  3618. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3619. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3620. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  3621. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3622. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  3623. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  3624. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  3625. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3626. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  3627. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3628. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  3629. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  3630. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  3631. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3632. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  3633. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  3634. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  3635. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3636. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  3637. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  3638. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  3639. wsa_cdc_dma_rx_0_sample_rate,
  3640. cdc_dma_rx_sample_rate_get,
  3641. cdc_dma_rx_sample_rate_put),
  3642. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  3643. wsa_cdc_dma_rx_1_sample_rate,
  3644. cdc_dma_rx_sample_rate_get,
  3645. cdc_dma_rx_sample_rate_put),
  3646. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  3647. wsa_cdc_dma_tx_0_sample_rate,
  3648. cdc_dma_tx_sample_rate_get,
  3649. cdc_dma_tx_sample_rate_put),
  3650. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  3651. wsa_cdc_dma_tx_1_sample_rate,
  3652. cdc_dma_tx_sample_rate_get,
  3653. cdc_dma_tx_sample_rate_put),
  3654. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  3655. wsa_cdc_dma_tx_2_sample_rate,
  3656. cdc_dma_tx_sample_rate_get,
  3657. cdc_dma_tx_sample_rate_put),
  3658. };
  3659. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3660. SOC_ENUM_EXT("BT_TX SampleRate", bt_sample_rate_sink,
  3661. msm_bt_sample_rate_sink_get,
  3662. msm_bt_sample_rate_sink_put),
  3663. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3664. msm_bt_sample_rate_get,
  3665. msm_bt_sample_rate_put),
  3666. SOC_ENUM_EXT("BT_RX SampleRate", bt_sample_rate,
  3667. msm_bt_sample_rate_get,
  3668. msm_bt_sample_rate_put),
  3669. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3670. proxy_rx_ch_get, proxy_rx_ch_put),
  3671. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3672. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3673. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3674. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3675. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3676. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3677. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3678. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3679. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3680. usb_audio_rx_sample_rate_get,
  3681. usb_audio_rx_sample_rate_put),
  3682. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3683. usb_audio_tx_sample_rate_get,
  3684. usb_audio_tx_sample_rate_put),
  3685. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3686. tdm_rx_sample_rate_get,
  3687. tdm_rx_sample_rate_put),
  3688. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3689. tdm_tx_sample_rate_get,
  3690. tdm_tx_sample_rate_put),
  3691. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3692. tdm_rx_format_get,
  3693. tdm_rx_format_put),
  3694. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3695. tdm_tx_format_get,
  3696. tdm_tx_format_put),
  3697. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3698. tdm_rx_ch_get,
  3699. tdm_rx_ch_put),
  3700. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3701. tdm_tx_ch_get,
  3702. tdm_tx_ch_put),
  3703. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3704. tdm_rx_sample_rate_get,
  3705. tdm_rx_sample_rate_put),
  3706. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3707. tdm_tx_sample_rate_get,
  3708. tdm_tx_sample_rate_put),
  3709. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3710. tdm_rx_format_get,
  3711. tdm_rx_format_put),
  3712. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3713. tdm_tx_format_get,
  3714. tdm_tx_format_put),
  3715. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3716. tdm_rx_ch_get,
  3717. tdm_rx_ch_put),
  3718. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3719. tdm_tx_ch_get,
  3720. tdm_tx_ch_put),
  3721. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3722. tdm_rx_sample_rate_get,
  3723. tdm_rx_sample_rate_put),
  3724. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3725. tdm_tx_sample_rate_get,
  3726. tdm_tx_sample_rate_put),
  3727. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3728. tdm_rx_format_get,
  3729. tdm_rx_format_put),
  3730. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3731. tdm_tx_format_get,
  3732. tdm_tx_format_put),
  3733. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3734. tdm_rx_ch_get,
  3735. tdm_rx_ch_put),
  3736. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3737. tdm_tx_ch_get,
  3738. tdm_tx_ch_put),
  3739. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3740. tdm_rx_sample_rate_get,
  3741. tdm_rx_sample_rate_put),
  3742. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3743. tdm_tx_sample_rate_get,
  3744. tdm_tx_sample_rate_put),
  3745. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3746. tdm_rx_format_get,
  3747. tdm_rx_format_put),
  3748. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3749. tdm_tx_format_get,
  3750. tdm_tx_format_put),
  3751. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3752. tdm_rx_ch_get,
  3753. tdm_rx_ch_put),
  3754. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3755. tdm_tx_ch_get,
  3756. tdm_tx_ch_put),
  3757. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3758. tdm_rx_sample_rate_get,
  3759. tdm_rx_sample_rate_put),
  3760. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3761. tdm_tx_sample_rate_get,
  3762. tdm_tx_sample_rate_put),
  3763. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3764. tdm_rx_format_get,
  3765. tdm_rx_format_put),
  3766. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3767. tdm_tx_format_get,
  3768. tdm_tx_format_put),
  3769. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3770. tdm_rx_ch_get,
  3771. tdm_rx_ch_put),
  3772. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3773. tdm_tx_ch_get,
  3774. tdm_tx_ch_put),
  3775. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3776. aux_pcm_rx_sample_rate_get,
  3777. aux_pcm_rx_sample_rate_put),
  3778. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3779. aux_pcm_rx_sample_rate_get,
  3780. aux_pcm_rx_sample_rate_put),
  3781. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3782. aux_pcm_rx_sample_rate_get,
  3783. aux_pcm_rx_sample_rate_put),
  3784. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3785. aux_pcm_rx_sample_rate_get,
  3786. aux_pcm_rx_sample_rate_put),
  3787. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3788. aux_pcm_rx_sample_rate_get,
  3789. aux_pcm_rx_sample_rate_put),
  3790. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3791. aux_pcm_tx_sample_rate_get,
  3792. aux_pcm_tx_sample_rate_put),
  3793. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3794. aux_pcm_tx_sample_rate_get,
  3795. aux_pcm_tx_sample_rate_put),
  3796. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3797. aux_pcm_tx_sample_rate_get,
  3798. aux_pcm_tx_sample_rate_put),
  3799. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3800. aux_pcm_tx_sample_rate_get,
  3801. aux_pcm_tx_sample_rate_put),
  3802. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3803. aux_pcm_tx_sample_rate_get,
  3804. aux_pcm_tx_sample_rate_put),
  3805. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3806. aux_pcm_tx_sample_rate_get,
  3807. aux_pcm_tx_sample_rate_put),
  3808. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3809. mi2s_rx_sample_rate_get,
  3810. mi2s_rx_sample_rate_put),
  3811. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3812. mi2s_rx_sample_rate_get,
  3813. mi2s_rx_sample_rate_put),
  3814. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3815. mi2s_rx_sample_rate_get,
  3816. mi2s_rx_sample_rate_put),
  3817. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3818. mi2s_rx_sample_rate_get,
  3819. mi2s_rx_sample_rate_put),
  3820. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3821. mi2s_rx_sample_rate_get,
  3822. mi2s_rx_sample_rate_put),
  3823. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3824. mi2s_rx_sample_rate_get,
  3825. mi2s_rx_sample_rate_put),
  3826. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3827. mi2s_tx_sample_rate_get,
  3828. mi2s_tx_sample_rate_put),
  3829. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3830. mi2s_tx_sample_rate_get,
  3831. mi2s_tx_sample_rate_put),
  3832. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3833. mi2s_tx_sample_rate_get,
  3834. mi2s_tx_sample_rate_put),
  3835. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3836. mi2s_tx_sample_rate_get,
  3837. mi2s_tx_sample_rate_put),
  3838. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3839. mi2s_tx_sample_rate_get,
  3840. mi2s_tx_sample_rate_put),
  3841. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3842. mi2s_tx_sample_rate_get,
  3843. mi2s_tx_sample_rate_put),
  3844. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3845. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3846. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3847. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3848. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3849. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3850. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3851. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3852. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3853. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3854. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3855. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3856. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3857. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3858. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3859. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3860. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3861. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3862. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3863. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3864. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3865. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3866. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3867. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3868. SOC_ENUM_EXT("PRIM_MI2S_TX DataFormat", mi2s_tx_data_format,
  3869. msm_mi2s_tx_data_format_get,
  3870. msm_mi2s_tx_data_format_put),
  3871. SOC_ENUM_EXT("QUAT_MI2S_TX DataFormat", mi2s_tx_data_format,
  3872. msm_mi2s_tx_data_format_get,
  3873. msm_mi2s_tx_data_format_put),
  3874. SOC_ENUM_EXT("PRIM_MI2S_RX DataFormat", mi2s_rx_data_format,
  3875. msm_mi2s_rx_data_format_get,
  3876. msm_mi2s_rx_data_format_put),
  3877. SOC_ENUM_EXT("QUAT_MI2S_RX DataFormat", mi2s_rx_data_format,
  3878. msm_mi2s_rx_data_format_get,
  3879. msm_mi2s_rx_data_format_put),
  3880. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3881. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3882. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3883. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3884. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3885. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3886. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3887. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3888. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3889. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3890. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3891. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3892. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3893. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3894. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3895. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3896. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3897. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3898. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3899. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3900. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3901. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3902. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3903. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3904. SOC_ENUM_EXT("PRIM_META_MI2S_RX SampleRate",
  3905. prim_meta_mi2s_rx_sample_rate,
  3906. msm_meta_mi2s_rx_sample_rate_get,
  3907. msm_meta_mi2s_rx_sample_rate_put),
  3908. SOC_ENUM_EXT("SEC_META_MI2S_RX SampleRate",
  3909. sec_meta_mi2s_rx_sample_rate,
  3910. msm_meta_mi2s_rx_sample_rate_get,
  3911. msm_meta_mi2s_rx_sample_rate_put),
  3912. SOC_ENUM_EXT("PRIM_META_MI2S_RX Channels", prim_meta_mi2s_rx_chs,
  3913. msm_meta_mi2s_rx_ch_get,
  3914. msm_meta_mi2s_rx_ch_put),
  3915. SOC_ENUM_EXT("SEC_META_MI2S_RX Channels", sec_meta_mi2s_rx_chs,
  3916. msm_meta_mi2s_rx_ch_get,
  3917. msm_meta_mi2s_rx_ch_put),
  3918. SOC_ENUM_EXT("PRIM_META_MI2S_RX Format", mi2s_rx_format,
  3919. msm_meta_mi2s_rx_format_get,
  3920. msm_meta_mi2s_rx_format_put),
  3921. SOC_ENUM_EXT("SEC_META_MI2S_RX Format", mi2s_rx_format,
  3922. msm_meta_mi2s_rx_format_get,
  3923. msm_meta_mi2s_rx_format_put),
  3924. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3925. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3926. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3927. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3928. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3929. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3930. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3931. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3932. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3933. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3934. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3935. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3936. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3937. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3938. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3939. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3940. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3941. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3942. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3943. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3944. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3945. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3946. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3947. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3948. SOC_SINGLE_MULTI_EXT("VAD CFG", SND_SOC_NOPM, 0, 1000, 0, 3, NULL,
  3949. msm_snd_vad_cfg_put),
  3950. SOC_ENUM_EXT("PRIM_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3951. msm_spdif_rx_sample_rate_get,
  3952. msm_spdif_rx_sample_rate_put),
  3953. SOC_ENUM_EXT("PRIM_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3954. msm_spdif_tx_sample_rate_get,
  3955. msm_spdif_tx_sample_rate_put),
  3956. SOC_ENUM_EXT("SEC_SPDIF_RX SampleRate", spdif_rx_sample_rate,
  3957. msm_spdif_rx_sample_rate_get,
  3958. msm_spdif_rx_sample_rate_put),
  3959. SOC_ENUM_EXT("SEC_SPDIF_TX SampleRate", spdif_tx_sample_rate,
  3960. msm_spdif_tx_sample_rate_get,
  3961. msm_spdif_tx_sample_rate_put),
  3962. SOC_ENUM_EXT("PRIM_SPDIF_RX Channels", spdif_rx_chs,
  3963. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3964. SOC_ENUM_EXT("PRIM_SPDIF_TX Channels", spdif_tx_chs,
  3965. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3966. SOC_ENUM_EXT("SEC_SPDIF_RX Channels", spdif_rx_chs,
  3967. msm_spdif_rx_ch_get, msm_spdif_rx_ch_put),
  3968. SOC_ENUM_EXT("SEC_SPDIF_TX Channels", spdif_tx_chs,
  3969. msm_spdif_tx_ch_get, msm_spdif_tx_ch_put),
  3970. SOC_ENUM_EXT("PRIM_SPDIF_RX Format", spdif_rx_format,
  3971. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3972. SOC_ENUM_EXT("PRIM_SPDIF_TX Format", spdif_tx_format,
  3973. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3974. SOC_ENUM_EXT("SEC_SPDIF_RX Format", spdif_rx_format,
  3975. msm_spdif_rx_format_get, msm_spdif_rx_format_put),
  3976. SOC_ENUM_EXT("SEC_SPDIF_TX Format", spdif_tx_format,
  3977. msm_spdif_tx_format_get, msm_spdif_tx_format_put),
  3978. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_lb_tx_chs,
  3979. afe_lb_tx_ch_get, afe_lb_tx_ch_put),
  3980. SOC_ENUM_EXT("AFE_LOOPBACK_TX Format", afe_lb_tx_format,
  3981. afe_lb_tx_format_get, afe_lb_tx_format_put),
  3982. SOC_ENUM_EXT("AFE_LOOPBACK_TX SampleRate", afe_lb_tx_sample_rate,
  3983. afe_lb_tx_sample_rate_get,
  3984. afe_lb_tx_sample_rate_put),
  3985. };
  3986. static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
  3987. int enable, bool dapm)
  3988. {
  3989. int ret = 0;
  3990. if (!strcmp(component.name, "tasha_codec")) {
  3991. ret = tasha_cdc_mclk_enable(component, enable, dapm);
  3992. } else {
  3993. dev_err(component->dev, "%s: unknown codec to enable ext clk\n",
  3994. __func__);
  3995. ret = -EINVAL;
  3996. }
  3997. return ret;
  3998. }
  3999. static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_component *component,
  4000. int enable, bool dapm)
  4001. {
  4002. int ret = 0;
  4003. if (!strcmp(component.name, "tasha_codec")) {
  4004. ret = tasha_cdc_mclk_tx_enable(component, enable, dapm);
  4005. } else {
  4006. dev_err(component->dev, "%s: unknown codec to enable TX ext clk\n",
  4007. __func__);
  4008. ret = -EINVAL;
  4009. }
  4010. return ret;
  4011. }
  4012. static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
  4013. struct snd_kcontrol *kcontrol, int event)
  4014. {
  4015. struct snd_soc_component *component =
  4016. snd_soc_dapm_to_component(w->dapm);
  4017. pr_debug("%s: event = %d\n", __func__, event);
  4018. switch (event) {
  4019. case SND_SOC_DAPM_PRE_PMU:
  4020. return msm_snd_enable_codec_ext_tx_clk(component, 1, true);
  4021. case SND_SOC_DAPM_POST_PMD:
  4022. return msm_snd_enable_codec_ext_tx_clk(component, 0, true);
  4023. }
  4024. return 0;
  4025. }
  4026. static int msm_mclk_event(struct snd_soc_dapm_widget *w,
  4027. struct snd_kcontrol *kcontrol, int event)
  4028. {
  4029. struct snd_soc_component *component =
  4030. snd_soc_dapm_to_component(w->dapm);
  4031. pr_debug("%s: event = %d\n", __func__, event);
  4032. switch (event) {
  4033. case SND_SOC_DAPM_PRE_PMU:
  4034. return msm_snd_enable_codec_ext_clk(component, 1, true);
  4035. case SND_SOC_DAPM_POST_PMD:
  4036. return msm_snd_enable_codec_ext_clk(component, 0, true);
  4037. }
  4038. return 0;
  4039. }
  4040. static int msm_lineout_booster_ctrl_event(struct snd_soc_dapm_widget *w,
  4041. struct snd_kcontrol *k, int event)
  4042. {
  4043. struct snd_soc_component *component =
  4044. snd_soc_dapm_to_component(w->dapm);
  4045. struct snd_soc_card *card = component->card;
  4046. struct msm_asoc_mach_data *pdata =
  4047. snd_soc_card_get_drvdata(card);
  4048. pr_debug("%s: event = %d\n", __func__, event);
  4049. switch (event) {
  4050. case SND_SOC_DAPM_POST_PMU:
  4051. msm_cdc_pinctrl_select_active_state(
  4052. pdata->lineout_booster_gpio_p);
  4053. break;
  4054. case SND_SOC_DAPM_PRE_PMD:
  4055. msm_cdc_pinctrl_select_sleep_state(
  4056. pdata->lineout_booster_gpio_p);
  4057. break;
  4058. }
  4059. return 0;
  4060. }
  4061. static const struct snd_soc_dapm_widget msm_dapm_widgets[] = {
  4062. SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
  4063. msm_mclk_event,
  4064. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4065. SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
  4066. msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  4067. SND_SOC_DAPM_SPK("lineout booster", msm_lineout_booster_ctrl_event),
  4068. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4069. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4070. };
  4071. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4072. struct snd_kcontrol *kcontrol, int event)
  4073. {
  4074. struct msm_asoc_mach_data *pdata = NULL;
  4075. struct snd_soc_component *component =
  4076. snd_soc_dapm_to_component(w->dapm);
  4077. int ret = 0;
  4078. uint32_t dmic_idx;
  4079. int *dmic_gpio_cnt;
  4080. struct device_node *dmic_gpio;
  4081. char *wname;
  4082. wname = strpbrk(w->name, "01234567");
  4083. if (!wname) {
  4084. dev_err(component->dev, "%s: widget not found\n", __func__);
  4085. return -EINVAL;
  4086. }
  4087. ret = kstrtouint(wname, 10, &dmic_idx);
  4088. if (ret < 0) {
  4089. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4090. __func__);
  4091. return -EINVAL;
  4092. }
  4093. pdata = snd_soc_card_get_drvdata(component->card);
  4094. switch (dmic_idx) {
  4095. case 0:
  4096. case 1:
  4097. dmic_gpio_cnt = &pdata->dmic_01_gpio_cnt;
  4098. dmic_gpio = pdata->dmic_01_gpio_p;
  4099. break;
  4100. case 2:
  4101. case 3:
  4102. dmic_gpio_cnt = &pdata->dmic_23_gpio_cnt;
  4103. dmic_gpio = pdata->dmic_23_gpio_p;
  4104. break;
  4105. case 4:
  4106. case 5:
  4107. dmic_gpio_cnt = &pdata->dmic_45_gpio_cnt;
  4108. dmic_gpio = pdata->dmic_45_gpio_p;
  4109. break;
  4110. case 6:
  4111. case 7:
  4112. dmic_gpio_cnt = &pdata->dmic_67_gpio_cnt;
  4113. dmic_gpio = pdata->dmic_67_gpio_p;
  4114. break;
  4115. default:
  4116. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4117. __func__);
  4118. return -EINVAL;
  4119. }
  4120. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4121. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4122. switch (event) {
  4123. case SND_SOC_DAPM_PRE_PMU:
  4124. (*dmic_gpio_cnt)++;
  4125. if (*dmic_gpio_cnt == 1) {
  4126. ret = msm_cdc_pinctrl_select_active_state(
  4127. dmic_gpio);
  4128. if (ret < 0) {
  4129. dev_err(component->dev, "%s: gpio set cannot be activated %sd\n",
  4130. __func__, "dmic_gpio");
  4131. return ret;
  4132. }
  4133. }
  4134. break;
  4135. case SND_SOC_DAPM_POST_PMD:
  4136. (*dmic_gpio_cnt)--;
  4137. if (*dmic_gpio_cnt == 0) {
  4138. ret = msm_cdc_pinctrl_select_sleep_state(
  4139. dmic_gpio);
  4140. if (ret < 0) {
  4141. dev_err(component->dev, "%s: gpio set cannot be de-activated %sd\n",
  4142. __func__, "dmic_gpio");
  4143. return ret;
  4144. }
  4145. }
  4146. break;
  4147. default:
  4148. dev_err(component->dev, "%s: invalid DAPM event %d\n",
  4149. __func__, event);
  4150. return -EINVAL;
  4151. }
  4152. return 0;
  4153. }
  4154. static const struct snd_soc_dapm_widget msm_va_dapm_widgets[] = {
  4155. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4156. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4157. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4158. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4159. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4160. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4161. SND_SOC_DAPM_MIC("Digital Mic6", msm_dmic_event),
  4162. SND_SOC_DAPM_MIC("Digital Mic7", msm_dmic_event),
  4163. };
  4164. static const struct snd_soc_dapm_widget msm_wsa_dapm_widgets[] = {
  4165. };
  4166. static inline int param_is_mask(int p)
  4167. {
  4168. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  4169. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  4170. }
  4171. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  4172. int n)
  4173. {
  4174. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  4175. }
  4176. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  4177. unsigned int bit)
  4178. {
  4179. if (bit >= SNDRV_MASK_MAX)
  4180. return;
  4181. if (param_is_mask(n)) {
  4182. struct snd_mask *m = param_to_mask(p, n);
  4183. m->bits[0] = 0;
  4184. m->bits[1] = 0;
  4185. m->bits[bit >> 5] |= (1 << (bit & 31));
  4186. }
  4187. }
  4188. static int msm_slim_get_ch_from_beid(int32_t be_id)
  4189. {
  4190. int ch_id = 0;
  4191. switch (be_id) {
  4192. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  4193. ch_id = SLIM_RX_0;
  4194. break;
  4195. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  4196. ch_id = SLIM_RX_1;
  4197. break;
  4198. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  4199. ch_id = SLIM_RX_2;
  4200. break;
  4201. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  4202. ch_id = SLIM_RX_3;
  4203. break;
  4204. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  4205. ch_id = SLIM_RX_4;
  4206. break;
  4207. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  4208. ch_id = SLIM_RX_6;
  4209. break;
  4210. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  4211. ch_id = SLIM_TX_0;
  4212. break;
  4213. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  4214. ch_id = SLIM_TX_3;
  4215. break;
  4216. default:
  4217. ch_id = SLIM_RX_0;
  4218. break;
  4219. }
  4220. return ch_id;
  4221. }
  4222. static int msm_ext_hdmi_get_idx_from_beid(int32_t be_id)
  4223. {
  4224. int idx;
  4225. switch (be_id) {
  4226. case MSM_BACKEND_DAI_HDMI_RX_MS:
  4227. idx = HDMI_RX_IDX;
  4228. break;
  4229. default:
  4230. pr_err("%s: Incorrect ext_hdmi BE id %d\n", __func__, be_id);
  4231. idx = -EINVAL;
  4232. break;
  4233. }
  4234. return idx;
  4235. }
  4236. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  4237. {
  4238. int idx = 0;
  4239. switch (be_id) {
  4240. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4241. idx = WSA_CDC_DMA_RX_0;
  4242. break;
  4243. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4244. idx = WSA_CDC_DMA_TX_0;
  4245. break;
  4246. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4247. idx = WSA_CDC_DMA_RX_1;
  4248. break;
  4249. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4250. idx = WSA_CDC_DMA_TX_1;
  4251. break;
  4252. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4253. idx = WSA_CDC_DMA_TX_2;
  4254. break;
  4255. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4256. idx = VA_CDC_DMA_TX_0;
  4257. break;
  4258. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4259. idx = VA_CDC_DMA_TX_1;
  4260. break;
  4261. default:
  4262. idx = VA_CDC_DMA_TX_0;
  4263. break;
  4264. }
  4265. return idx;
  4266. }
  4267. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  4268. struct snd_pcm_hw_params *params)
  4269. {
  4270. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4271. struct snd_interval *rate = hw_param_interval(params,
  4272. SNDRV_PCM_HW_PARAM_RATE);
  4273. struct snd_interval *channels = hw_param_interval(params,
  4274. SNDRV_PCM_HW_PARAM_CHANNELS);
  4275. int rc = 0;
  4276. int idx;
  4277. void *config = NULL;
  4278. struct snd_soc_component *component = NULL;
  4279. pr_debug("%s: format = %d, rate = %d\n",
  4280. __func__, params_format(params), params_rate(params));
  4281. switch (dai_link->id) {
  4282. case MSM_BACKEND_DAI_SLIMBUS_0_RX:
  4283. case MSM_BACKEND_DAI_SLIMBUS_1_RX:
  4284. case MSM_BACKEND_DAI_SLIMBUS_2_RX:
  4285. case MSM_BACKEND_DAI_SLIMBUS_3_RX:
  4286. case MSM_BACKEND_DAI_SLIMBUS_4_RX:
  4287. case MSM_BACKEND_DAI_SLIMBUS_6_RX:
  4288. idx = msm_slim_get_ch_from_beid(dai_link->id);
  4289. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4290. slim_rx_cfg[idx].bit_format);
  4291. rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
  4292. channels->min = channels->max = slim_rx_cfg[idx].channels;
  4293. break;
  4294. case MSM_BACKEND_DAI_SLIMBUS_0_TX:
  4295. case MSM_BACKEND_DAI_SLIMBUS_3_TX:
  4296. idx = msm_slim_get_ch_from_beid(dai_link->id);
  4297. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4298. slim_tx_cfg[idx].bit_format);
  4299. rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
  4300. channels->min = channels->max = slim_tx_cfg[idx].channels;
  4301. break;
  4302. case MSM_BACKEND_DAI_SLIMBUS_1_TX:
  4303. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4304. slim_tx_cfg[1].bit_format);
  4305. rate->min = rate->max = slim_tx_cfg[1].sample_rate;
  4306. channels->min = channels->max = slim_tx_cfg[1].channels;
  4307. break;
  4308. case MSM_BACKEND_DAI_SLIMBUS_4_TX:
  4309. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4310. SNDRV_PCM_FORMAT_S32_LE);
  4311. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  4312. channels->min = channels->max = msm_vi_feed_tx_ch;
  4313. break;
  4314. case MSM_BACKEND_DAI_SLIMBUS_5_RX:
  4315. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4316. slim_rx_cfg[5].bit_format);
  4317. rate->min = rate->max = slim_rx_cfg[5].sample_rate;
  4318. channels->min = channels->max = slim_rx_cfg[5].channels;
  4319. break;
  4320. case MSM_BACKEND_DAI_SLIMBUS_5_TX:
  4321. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4322. if (!component) {
  4323. pr_err("%s: component is NULL\n", __func__);
  4324. return -EINVAL;
  4325. }
  4326. rate->min = rate->max = SAMPLING_RATE_16KHZ;
  4327. channels->min = channels->max = 1;
  4328. config = msm_codec_fn.get_afe_config_fn(component,
  4329. AFE_SLIMBUS_SLAVE_PORT_CONFIG);
  4330. if (config) {
  4331. rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
  4332. config, SLIMBUS_5_TX);
  4333. if (rc)
  4334. pr_err("%s: Failed to set slimbus slave port config %d\n",
  4335. __func__, rc);
  4336. }
  4337. break;
  4338. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  4339. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4340. slim_rx_cfg[SLIM_RX_7].bit_format);
  4341. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  4342. channels->min = channels->max =
  4343. slim_rx_cfg[SLIM_RX_7].channels;
  4344. break;
  4345. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  4346. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  4347. channels->min = channels->max =
  4348. slim_tx_cfg[SLIM_TX_7].channels;
  4349. break;
  4350. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  4351. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  4352. channels->min = channels->max =
  4353. slim_tx_cfg[SLIM_TX_8].channels;
  4354. break;
  4355. case MSM_BACKEND_DAI_SLIMBUS_9_TX:
  4356. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4357. slim_tx_cfg[SLIM_TX_9].bit_format);
  4358. rate->min = rate->max = slim_tx_cfg[SLIM_TX_9].sample_rate;
  4359. channels->min = channels->max =
  4360. slim_tx_cfg[SLIM_TX_9].channels;
  4361. break;
  4362. case MSM_BACKEND_DAI_USB_RX:
  4363. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4364. usb_rx_cfg.bit_format);
  4365. rate->min = rate->max = usb_rx_cfg.sample_rate;
  4366. channels->min = channels->max = usb_rx_cfg.channels;
  4367. break;
  4368. case MSM_BACKEND_DAI_USB_TX:
  4369. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4370. usb_tx_cfg.bit_format);
  4371. rate->min = rate->max = usb_tx_cfg.sample_rate;
  4372. channels->min = channels->max = usb_tx_cfg.channels;
  4373. break;
  4374. case MSM_BACKEND_DAI_AFE_PCM_RX:
  4375. channels->min = channels->max = proxy_rx_cfg.channels;
  4376. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4377. break;
  4378. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  4379. channels->min = channels->max =
  4380. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  4381. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4382. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  4383. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  4384. break;
  4385. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  4386. channels->min = channels->max =
  4387. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  4388. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4389. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  4390. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  4391. break;
  4392. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  4393. channels->min = channels->max =
  4394. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  4395. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4396. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  4397. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  4398. break;
  4399. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  4400. channels->min = channels->max =
  4401. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  4402. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4403. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  4404. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  4405. break;
  4406. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  4407. channels->min = channels->max =
  4408. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  4409. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4410. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  4411. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  4412. break;
  4413. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  4414. channels->min = channels->max =
  4415. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  4416. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4417. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  4418. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  4419. break;
  4420. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  4421. channels->min = channels->max =
  4422. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  4423. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4424. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  4425. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4426. break;
  4427. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  4428. channels->min = channels->max =
  4429. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  4430. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4431. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  4432. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  4433. break;
  4434. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  4435. channels->min = channels->max =
  4436. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  4437. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4438. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  4439. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4440. break;
  4441. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  4442. channels->min = channels->max =
  4443. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  4444. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4445. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  4446. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  4447. break;
  4448. case MSM_BACKEND_DAI_AUXPCM_RX:
  4449. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4450. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  4451. rate->min = rate->max =
  4452. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  4453. channels->min = channels->max =
  4454. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  4455. break;
  4456. case MSM_BACKEND_DAI_AUXPCM_TX:
  4457. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4458. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  4459. rate->min = rate->max =
  4460. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  4461. channels->min = channels->max =
  4462. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  4463. break;
  4464. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  4465. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4466. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  4467. rate->min = rate->max =
  4468. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  4469. channels->min = channels->max =
  4470. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  4471. break;
  4472. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  4473. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4474. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  4475. rate->min = rate->max =
  4476. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  4477. channels->min = channels->max =
  4478. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  4479. break;
  4480. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  4481. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4482. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  4483. rate->min = rate->max =
  4484. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  4485. channels->min = channels->max =
  4486. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  4487. break;
  4488. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  4489. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4490. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  4491. rate->min = rate->max =
  4492. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  4493. channels->min = channels->max =
  4494. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  4495. break;
  4496. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  4497. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4498. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  4499. rate->min = rate->max =
  4500. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  4501. channels->min = channels->max =
  4502. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  4503. break;
  4504. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  4505. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4506. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  4507. rate->min = rate->max =
  4508. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  4509. channels->min = channels->max =
  4510. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  4511. break;
  4512. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  4513. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4514. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  4515. rate->min = rate->max =
  4516. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  4517. channels->min = channels->max =
  4518. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  4519. break;
  4520. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  4521. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4522. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  4523. rate->min = rate->max =
  4524. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  4525. channels->min = channels->max =
  4526. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  4527. break;
  4528. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  4529. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4530. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  4531. rate->min = rate->max =
  4532. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  4533. channels->min = channels->max =
  4534. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  4535. break;
  4536. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  4537. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4538. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  4539. rate->min = rate->max =
  4540. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  4541. channels->min = channels->max =
  4542. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  4543. break;
  4544. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  4545. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4546. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  4547. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  4548. channels->min = channels->max =
  4549. mi2s_rx_cfg[PRIM_MI2S].channels;
  4550. break;
  4551. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  4552. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4553. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  4554. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  4555. channels->min = channels->max =
  4556. mi2s_tx_cfg[PRIM_MI2S].channels;
  4557. break;
  4558. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  4559. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4560. mi2s_rx_cfg[SEC_MI2S].bit_format);
  4561. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  4562. channels->min = channels->max =
  4563. mi2s_rx_cfg[SEC_MI2S].channels;
  4564. break;
  4565. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  4566. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4567. mi2s_tx_cfg[SEC_MI2S].bit_format);
  4568. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  4569. channels->min = channels->max =
  4570. mi2s_tx_cfg[SEC_MI2S].channels;
  4571. break;
  4572. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  4573. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4574. mi2s_rx_cfg[TERT_MI2S].bit_format);
  4575. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  4576. channels->min = channels->max =
  4577. mi2s_rx_cfg[TERT_MI2S].channels;
  4578. break;
  4579. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  4580. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4581. mi2s_tx_cfg[TERT_MI2S].bit_format);
  4582. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  4583. channels->min = channels->max =
  4584. mi2s_tx_cfg[TERT_MI2S].channels;
  4585. break;
  4586. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  4587. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4588. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  4589. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  4590. channels->min = channels->max =
  4591. mi2s_rx_cfg[QUAT_MI2S].channels;
  4592. break;
  4593. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  4594. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4595. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  4596. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  4597. channels->min = channels->max =
  4598. mi2s_tx_cfg[QUAT_MI2S].channels;
  4599. break;
  4600. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  4601. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4602. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  4603. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  4604. channels->min = channels->max =
  4605. mi2s_rx_cfg[QUIN_MI2S].channels;
  4606. break;
  4607. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  4608. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4609. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  4610. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  4611. channels->min = channels->max =
  4612. mi2s_tx_cfg[QUIN_MI2S].channels;
  4613. break;
  4614. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  4615. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4616. mi2s_rx_cfg[SEN_MI2S].bit_format);
  4617. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  4618. channels->min = channels->max =
  4619. mi2s_rx_cfg[SEN_MI2S].channels;
  4620. break;
  4621. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  4622. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4623. mi2s_tx_cfg[SEN_MI2S].bit_format);
  4624. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  4625. channels->min = channels->max =
  4626. mi2s_tx_cfg[SEN_MI2S].channels;
  4627. break;
  4628. case MSM_BACKEND_DAI_PRI_META_MI2S_RX:
  4629. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4630. meta_mi2s_rx_cfg[PRIM_META_MI2S].bit_format);
  4631. rate->min = rate->max =
  4632. meta_mi2s_rx_cfg[PRIM_META_MI2S].sample_rate;
  4633. channels->min = channels->max =
  4634. meta_mi2s_rx_cfg[PRIM_META_MI2S].channels;
  4635. break;
  4636. case MSM_BACKEND_DAI_SEC_META_MI2S_RX:
  4637. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4638. meta_mi2s_rx_cfg[SEC_META_MI2S].bit_format);
  4639. rate->min = rate->max =
  4640. meta_mi2s_rx_cfg[SEC_META_MI2S].sample_rate;
  4641. channels->min = channels->max =
  4642. meta_mi2s_rx_cfg[SEC_META_MI2S].channels;
  4643. break;
  4644. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4645. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4646. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4647. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4648. cdc_dma_rx_cfg[idx].bit_format);
  4649. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  4650. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  4651. break;
  4652. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4653. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4654. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4655. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4656. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4657. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4658. cdc_dma_tx_cfg[idx].bit_format);
  4659. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  4660. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  4661. break;
  4662. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4663. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4664. SNDRV_PCM_FORMAT_S32_LE);
  4665. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  4666. channels->min = channels->max = msm_vi_feed_tx_ch;
  4667. break;
  4668. case MSM_BACKEND_DAI_PRI_SPDIF_RX:
  4669. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4670. spdif_rx_cfg[PRIM_SPDIF_RX].bit_format);
  4671. rate->min = rate->max =
  4672. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate;
  4673. channels->min = channels->max =
  4674. spdif_rx_cfg[PRIM_SPDIF_RX].channels;
  4675. break;
  4676. case MSM_BACKEND_DAI_PRI_SPDIF_TX:
  4677. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4678. spdif_tx_cfg[PRIM_SPDIF_TX].bit_format);
  4679. rate->min = rate->max =
  4680. spdif_tx_cfg[PRIM_SPDIF_TX].sample_rate;
  4681. channels->min = channels->max =
  4682. spdif_tx_cfg[PRIM_SPDIF_TX].channels;
  4683. break;
  4684. case MSM_BACKEND_DAI_SEC_SPDIF_RX:
  4685. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4686. spdif_rx_cfg[SEC_SPDIF_RX].bit_format);
  4687. rate->min = rate->max =
  4688. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate;
  4689. channels->min = channels->max =
  4690. spdif_rx_cfg[SEC_SPDIF_RX].channels;
  4691. break;
  4692. case MSM_BACKEND_DAI_SEC_SPDIF_TX:
  4693. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4694. spdif_tx_cfg[SEC_SPDIF_TX].bit_format);
  4695. rate->min = rate->max =
  4696. spdif_tx_cfg[SEC_SPDIF_TX].sample_rate;
  4697. channels->min = channels->max =
  4698. spdif_tx_cfg[SEC_SPDIF_TX].channels;
  4699. break;
  4700. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  4701. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4702. afe_lb_tx_cfg.bit_format);
  4703. rate->min = rate->max = afe_lb_tx_cfg.sample_rate;
  4704. channels->min = channels->max = afe_lb_tx_cfg.channels;
  4705. break;
  4706. case MSM_BACKEND_DAI_HDMI_RX_MS:
  4707. idx = msm_ext_hdmi_get_idx_from_beid(dai_link->id);
  4708. if (idx < 0) {
  4709. pr_err("%s: Incorrect ext hdmi idx %d\n",
  4710. __func__, idx);
  4711. rc = idx;
  4712. goto done;
  4713. }
  4714. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  4715. ext_hdmi_rx_cfg[idx].bit_format);
  4716. rate->min = rate->max = ext_hdmi_rx_cfg[idx].sample_rate;
  4717. channels->min = channels->max = ext_hdmi_rx_cfg[idx].channels;
  4718. break;
  4719. default:
  4720. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  4721. break;
  4722. }
  4723. done:
  4724. return rc;
  4725. }
  4726. static int msm_afe_set_config(struct snd_soc_component *component)
  4727. {
  4728. int ret = 0;
  4729. void *config_data = NULL;
  4730. if (!msm_codec_fn.get_afe_config_fn) {
  4731. dev_err(component->dev, "%s: codec get afe config not init'ed\n",
  4732. __func__);
  4733. return -EINVAL;
  4734. }
  4735. config_data = msm_codec_fn.get_afe_config_fn(component,
  4736. AFE_CDC_REGISTERS_CONFIG);
  4737. if (config_data) {
  4738. ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
  4739. if (ret) {
  4740. dev_err(component->dev,
  4741. "%s: Failed to set codec registers config %d\n",
  4742. __func__, ret);
  4743. return ret;
  4744. }
  4745. }
  4746. config_data = msm_codec_fn.get_afe_config_fn(component,
  4747. AFE_CDC_REGISTER_PAGE_CONFIG);
  4748. if (config_data) {
  4749. ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
  4750. 0);
  4751. if (ret)
  4752. dev_err(component->dev,
  4753. "%s: Failed to set cdc register page config\n",
  4754. __func__);
  4755. }
  4756. config_data = msm_codec_fn.get_afe_config_fn(component,
  4757. AFE_SLIMBUS_SLAVE_CONFIG);
  4758. if (config_data) {
  4759. ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
  4760. if (ret) {
  4761. dev_err(component->dev,
  4762. "%s: Failed to set slimbus slave config %d\n",
  4763. __func__, ret);
  4764. return ret;
  4765. }
  4766. }
  4767. return 0;
  4768. }
  4769. static void msm_afe_clear_config(void)
  4770. {
  4771. afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
  4772. afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
  4773. }
  4774. static int msm_adsp_power_up_config(struct snd_soc_component *component,
  4775. struct snd_card *card)
  4776. {
  4777. int ret = 0;
  4778. unsigned long timeout;
  4779. int adsp_ready = 0;
  4780. bool snd_card_online = 0;
  4781. timeout = jiffies +
  4782. msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS);
  4783. do {
  4784. if (!snd_card_online) {
  4785. snd_card_online = snd_card_is_online_state(card);
  4786. pr_debug("%s: Sound card is %s\n", __func__,
  4787. snd_card_online ? "Online" : "Offline");
  4788. }
  4789. if (!adsp_ready) {
  4790. adsp_ready = q6core_is_adsp_ready();
  4791. pr_debug("%s: ADSP Audio is %s\n", __func__,
  4792. adsp_ready ? "ready" : "not ready");
  4793. }
  4794. if (snd_card_online && adsp_ready)
  4795. break;
  4796. /*
  4797. * Sound card/ADSP will be coming up after subsystem restart and
  4798. * it might not be fully up when the control reaches
  4799. * here. So, wait for 50msec before checking ADSP state
  4800. */
  4801. msleep(50);
  4802. } while (time_after(timeout, jiffies));
  4803. if (!snd_card_online || !adsp_ready) {
  4804. pr_err("%s: Timeout. Sound card is %s, ADSP Audio is %s\n",
  4805. __func__,
  4806. snd_card_online ? "Online" : "Offline",
  4807. adsp_ready ? "ready" : "not ready");
  4808. ret = -ETIMEDOUT;
  4809. goto err;
  4810. }
  4811. ret = msm_afe_set_config(component);
  4812. if (ret)
  4813. pr_err("%s: Failed to set AFE config. err %d\n",
  4814. __func__, ret);
  4815. return 0;
  4816. err:
  4817. return ret;
  4818. }
  4819. static int qcs405_notifier_service_cb(struct notifier_block *this,
  4820. unsigned long opcode, void *ptr)
  4821. {
  4822. int ret;
  4823. struct snd_soc_card *card = NULL;
  4824. const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
  4825. struct snd_soc_pcm_runtime *rtd;
  4826. struct snd_soc_dai *codec_dai;
  4827. struct snd_soc_component *component;
  4828. pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
  4829. switch (opcode) {
  4830. case AUDIO_NOTIFIER_SERVICE_DOWN:
  4831. /*
  4832. * Use flag to ignore initial boot notifications
  4833. * On initial boot msm_adsp_power_up_config is
  4834. * called on init. There is no need to clear
  4835. * and set the config again on initial boot.
  4836. */
  4837. if (is_initial_boot)
  4838. break;
  4839. msm_afe_clear_config();
  4840. break;
  4841. case AUDIO_NOTIFIER_SERVICE_UP:
  4842. if (is_initial_boot) {
  4843. is_initial_boot = false;
  4844. break;
  4845. }
  4846. if (!spdev)
  4847. return -EINVAL;
  4848. card = platform_get_drvdata(spdev);
  4849. rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
  4850. if (!rtd) {
  4851. dev_err(card->dev,
  4852. "%s: snd_soc_get_pcm_runtime for %s failed!\n",
  4853. __func__, be_dl_name);
  4854. ret = -EINVAL;
  4855. goto err;
  4856. }
  4857. codec_dai = rtd->codec_dai;
  4858. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec"))
  4859. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4860. ret = msm_adsp_power_up_config(component, card->snd_card);
  4861. if (ret < 0) {
  4862. dev_err(card->dev,
  4863. "%s: msm_adsp_power_up_config failed ret = %d!\n",
  4864. __func__, ret);
  4865. goto err;
  4866. }
  4867. break;
  4868. default:
  4869. break;
  4870. }
  4871. err:
  4872. return NOTIFY_OK;
  4873. }
  4874. static struct notifier_block service_nb = {
  4875. .notifier_call = qcs405_notifier_service_cb,
  4876. .priority = -INT_MAX,
  4877. };
  4878. static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4879. {
  4880. int ret = 0;
  4881. void *config_data;
  4882. struct snd_soc_component *component;
  4883. struct snd_soc_dapm_context *dapm;
  4884. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4885. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4886. struct snd_card *card;
  4887. struct msm_asoc_mach_data *pdata =
  4888. snd_soc_card_get_drvdata(rtd->card);
  4889. /*
  4890. * Codec SLIMBUS configuration
  4891. * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
  4892. * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
  4893. * TX14, TX15, TX16
  4894. */
  4895. unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150,
  4896. 151, 152, 153, 154, 155, 156};
  4897. unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133,
  4898. 134, 135, 136, 137, 138, 139,
  4899. 140, 141, 142, 143};
  4900. pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
  4901. rtd->pmdown_time = 0;
  4902. if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) {
  4903. component = snd_soc_rtdcom_lookup(rtd, "tasha_codec");
  4904. dapm = snd_soc_component_get_dapm(component);
  4905. }
  4906. ret = snd_soc_add_component_controls(component, msm_snd_sb_controls,
  4907. ARRAY_SIZE(msm_snd_sb_controls));
  4908. if (ret < 0) {
  4909. pr_err("%s: add_codec_controls failed, err %d\n",
  4910. __func__, ret);
  4911. return ret;
  4912. }
  4913. snd_soc_dapm_new_controls(dapm, msm_dapm_widgets,
  4914. ARRAY_SIZE(msm_dapm_widgets));
  4915. snd_soc_dapm_add_routes(dapm, wcd_audio_paths,
  4916. ARRAY_SIZE(wcd_audio_paths));
  4917. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
  4918. snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
  4919. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4920. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4921. snd_soc_dapm_ignore_suspend(dapm, "lineout booster");
  4922. snd_soc_dapm_sync(dapm);
  4923. snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4924. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4925. msm_codec_fn.get_afe_config_fn = tasha_get_afe_config;
  4926. ret = msm_adsp_power_up_config(component, rtd->card->snd_card);
  4927. if (ret) {
  4928. dev_err(component->dev, "%s: Failed to set AFE config %d\n",
  4929. __func__, ret);
  4930. goto err;
  4931. }
  4932. config_data = msm_codec_fn.get_afe_config_fn(component,
  4933. AFE_AANC_VERSION);
  4934. if (config_data) {
  4935. ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
  4936. if (ret) {
  4937. dev_err(component->dev, "%s: Failed to set aanc version %d\n",
  4938. __func__, ret);
  4939. goto err;
  4940. }
  4941. }
  4942. card = rtd->card->snd_card;
  4943. if (!pdata->codec_root)
  4944. pdata->codec_root = snd_info_create_subdir(card->module,
  4945. "codecs", card->proc_root);
  4946. if (!pdata->codec_root) {
  4947. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4948. __func__);
  4949. ret = 0;
  4950. goto err;
  4951. }
  4952. tasha_codec_info_create_codec_entry(pdata->codec_root, component);
  4953. codec_reg_done = true;
  4954. return 0;
  4955. err:
  4956. return ret;
  4957. }
  4958. static int msm_va_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  4959. {
  4960. int ret = 0;
  4961. struct snd_soc_component *component;
  4962. struct snd_soc_dapm_context *dapm;
  4963. struct snd_card *card;
  4964. struct msm_asoc_mach_data *pdata =
  4965. snd_soc_card_get_drvdata(rtd->card);
  4966. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4967. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4968. if (!component) {
  4969. pr_err("%s: component is NULL\n", __func__);
  4970. return -EINVAL;
  4971. }
  4972. dapm = snd_soc_component_get_dapm(component);
  4973. ret = snd_soc_add_component_controls(component, msm_snd_va_controls,
  4974. ARRAY_SIZE(msm_snd_va_controls));
  4975. if (ret < 0) {
  4976. dev_err(component->dev, "%s: add_component_controls for va failed, err %d\n",
  4977. __func__, ret);
  4978. return ret;
  4979. }
  4980. snd_soc_dapm_new_controls(dapm, msm_va_dapm_widgets,
  4981. ARRAY_SIZE(msm_va_dapm_widgets));
  4982. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4983. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4984. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4985. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4986. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4987. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4988. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6");
  4989. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic7");
  4990. snd_soc_dapm_sync(dapm);
  4991. card = rtd->card->snd_card;
  4992. if (!pdata->codec_root)
  4993. pdata->codec_root = snd_info_create_subdir(card->module,
  4994. "codecs", card->proc_root);
  4995. if (!pdata->codec_root) {
  4996. dev_dbg(codec->dev, "%s: Cannot create codecs module entry\n",
  4997. __func__);
  4998. ret = 0;
  4999. goto done;
  5000. }
  5001. bolero_info_create_codec_entry(pdata->codec_root, component);
  5002. done:
  5003. return ret;
  5004. }
  5005. static int msm_wsa_cdc_dma_init(struct snd_soc_pcm_runtime *rtd)
  5006. {
  5007. int ret = 0;
  5008. struct snd_soc_component *component = NULL;
  5009. struct snd_soc_dapm_context *dapm = NULL;
  5010. struct snd_soc_component *aux_comp = NULL;
  5011. struct snd_card *card = NULL;
  5012. struct msm_asoc_mach_data *pdata =
  5013. snd_soc_card_get_drvdata(rtd->card);
  5014. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  5015. if (!component) {
  5016. pr_err("%s: component is NULL\n", __func__);
  5017. return -EINVAL;
  5018. }
  5019. dapm = snd_soc_component_get_dapm(component);
  5020. ret = snd_soc_add_component_controls(component, msm_snd_wsa_controls,
  5021. ARRAY_SIZE(msm_snd_wsa_controls));
  5022. if (ret < 0) {
  5023. dev_err(component->dev, "%s: add_codec_controls for wsa failed, err %d\n",
  5024. __func__, ret);
  5025. return ret;
  5026. }
  5027. snd_soc_dapm_new_controls(dapm, msm_wsa_dapm_widgets,
  5028. ARRAY_SIZE(msm_wsa_dapm_widgets));
  5029. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  5030. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  5031. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  5032. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  5033. snd_soc_dapm_sync(dapm);
  5034. /*
  5035. * Send speaker configuration only for WSA8810.
  5036. * Default configuration is for WSA8815.
  5037. */
  5038. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  5039. __func__, rtd->card->num_aux_devs);
  5040. if (rtd->card->num_aux_devs &&
  5041. !list_empty(&rtd->card->component_dev_list)) {
  5042. aux_comp = list_first_entry(
  5043. &rtd->card->component_dev_list,
  5044. struct snd_soc_component,
  5045. card_aux_list);
  5046. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  5047. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  5048. wsa_macro_set_spkr_mode(component,
  5049. WSA_MACRO_SPKR_MODE_1);
  5050. wsa_macro_set_spkr_gain_offset(component,
  5051. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  5052. }
  5053. }
  5054. card = rtd->card->snd_card;
  5055. if (!pdata->codec_root)
  5056. pdata->codec_root = snd_info_create_subdir(card->module,
  5057. "codecs", card->proc_root);
  5058. if (!pdata->codec_root) {
  5059. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  5060. __func__);
  5061. ret = 0;
  5062. goto done;
  5063. }
  5064. bolero_info_create_codec_entry(pdata->codec_root, component);
  5065. done:
  5066. return ret;
  5067. }
  5068. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  5069. {
  5070. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  5071. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161, 162};
  5072. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  5073. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  5074. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  5075. }
  5076. static int msm_snd_hw_params(struct snd_pcm_substream *substream,
  5077. struct snd_pcm_hw_params *params)
  5078. {
  5079. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5080. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  5081. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5082. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5083. int ret = 0;
  5084. u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
  5085. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  5086. u32 user_set_tx_ch = 0;
  5087. u32 rx_ch_count;
  5088. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  5089. ret = snd_soc_dai_get_channel_map(codec_dai,
  5090. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  5091. if (ret < 0) {
  5092. pr_err("%s: failed to get codec chan map, err:%d\n",
  5093. __func__, ret);
  5094. goto err;
  5095. }
  5096. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
  5097. pr_debug("%s: rx_5_ch=%d\n", __func__,
  5098. slim_rx_cfg[5].channels);
  5099. rx_ch_count = slim_rx_cfg[5].channels;
  5100. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
  5101. pr_debug("%s: rx_2_ch=%d\n", __func__,
  5102. slim_rx_cfg[2].channels);
  5103. rx_ch_count = slim_rx_cfg[2].channels;
  5104. } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
  5105. pr_debug("%s: rx_6_ch=%d\n", __func__,
  5106. slim_rx_cfg[6].channels);
  5107. rx_ch_count = slim_rx_cfg[6].channels;
  5108. } else {
  5109. pr_debug("%s: rx_0_ch=%d\n", __func__,
  5110. slim_rx_cfg[0].channels);
  5111. rx_ch_count = slim_rx_cfg[0].channels;
  5112. }
  5113. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  5114. rx_ch_count, rx_ch);
  5115. if (ret < 0) {
  5116. pr_err("%s: failed to set cpu chan map, err:%d\n",
  5117. __func__, ret);
  5118. goto err;
  5119. }
  5120. } else {
  5121. pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
  5122. codec_dai->name, codec_dai->id, user_set_tx_ch);
  5123. ret = snd_soc_dai_get_channel_map(codec_dai,
  5124. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  5125. if (ret < 0) {
  5126. pr_err("%s: failed to get tx codec chan map, err:%d\n",
  5127. __func__, ret);
  5128. goto err;
  5129. }
  5130. /* For <codec>_tx1 case */
  5131. if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
  5132. user_set_tx_ch = slim_tx_cfg[0].channels;
  5133. /* For <codec>_tx3 case */
  5134. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
  5135. user_set_tx_ch = slim_tx_cfg[1].channels;
  5136. else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
  5137. user_set_tx_ch = msm_vi_feed_tx_ch;
  5138. else
  5139. user_set_tx_ch = tx_ch_cnt;
  5140. pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
  5141. __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
  5142. tx_ch_cnt, dai_link->id);
  5143. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5144. user_set_tx_ch, tx_ch, 0, 0);
  5145. if (ret < 0)
  5146. pr_err("%s: failed to set tx cpu chan map, err:%d\n",
  5147. __func__, ret);
  5148. }
  5149. err:
  5150. return ret;
  5151. }
  5152. static int msm_snd_auxpcm_startup(struct snd_pcm_substream *substream)
  5153. {
  5154. int ret = 0;
  5155. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5156. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5157. ret = qcs405_send_island_vad_config(dai_link->id);
  5158. if (ret) {
  5159. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5160. __func__, ret);
  5161. }
  5162. return ret;
  5163. }
  5164. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  5165. {
  5166. int ret = 0;
  5167. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5168. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5169. ret = qcs405_send_island_vad_config(dai_link->id);
  5170. if (ret) {
  5171. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5172. __func__, ret);
  5173. }
  5174. return ret;
  5175. }
  5176. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  5177. struct snd_pcm_hw_params *params)
  5178. {
  5179. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5180. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  5181. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5182. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5183. int ret = 0;
  5184. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  5185. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  5186. u32 user_set_tx_ch = 0;
  5187. u32 user_set_rx_ch = 0;
  5188. u32 ch_id;
  5189. ret = snd_soc_dai_get_channel_map(codec_dai,
  5190. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  5191. &rx_ch_cdc_dma);
  5192. if (ret < 0) {
  5193. pr_err("%s: failed to get codec chan map, err:%d\n",
  5194. __func__, ret);
  5195. goto err;
  5196. }
  5197. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  5198. switch (dai_link->id) {
  5199. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  5200. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  5201. {
  5202. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  5203. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  5204. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  5205. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  5206. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  5207. user_set_rx_ch, &rx_ch_cdc_dma);
  5208. if (ret < 0) {
  5209. pr_err("%s: failed to set cpu chan map, err:%d\n",
  5210. __func__, ret);
  5211. goto err;
  5212. }
  5213. }
  5214. break;
  5215. }
  5216. } else {
  5217. switch (dai_link->id) {
  5218. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  5219. {
  5220. user_set_tx_ch = msm_vi_feed_tx_ch;
  5221. }
  5222. break;
  5223. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  5224. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  5225. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  5226. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  5227. {
  5228. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  5229. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  5230. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  5231. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  5232. }
  5233. break;
  5234. }
  5235. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  5236. &tx_ch_cdc_dma, 0, 0);
  5237. if (ret < 0) {
  5238. pr_err("%s: failed to set cpu chan map, err:%d\n",
  5239. __func__, ret);
  5240. goto err;
  5241. }
  5242. }
  5243. err:
  5244. return ret;
  5245. }
  5246. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  5247. struct snd_pcm_hw_params *params)
  5248. {
  5249. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5250. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  5251. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5252. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5253. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  5254. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  5255. int ret;
  5256. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  5257. codec_dai->name, codec_dai->id);
  5258. ret = snd_soc_dai_get_channel_map(codec_dai,
  5259. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  5260. if (ret) {
  5261. dev_err(rtd->dev,
  5262. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  5263. __func__, ret);
  5264. goto err;
  5265. }
  5266. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  5267. __func__, tx_ch_cnt, dai_link->id);
  5268. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5269. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  5270. if (ret)
  5271. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  5272. __func__, ret);
  5273. err:
  5274. return ret;
  5275. }
  5276. static int msm_get_port_id(int be_id)
  5277. {
  5278. int afe_port_id;
  5279. switch (be_id) {
  5280. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  5281. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  5282. break;
  5283. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  5284. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  5285. break;
  5286. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  5287. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  5288. break;
  5289. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  5290. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  5291. break;
  5292. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  5293. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  5294. break;
  5295. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  5296. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  5297. break;
  5298. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  5299. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  5300. break;
  5301. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  5302. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  5303. break;
  5304. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  5305. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  5306. break;
  5307. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  5308. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  5309. break;
  5310. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  5311. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  5312. break;
  5313. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  5314. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  5315. break;
  5316. default:
  5317. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  5318. afe_port_id = -EINVAL;
  5319. }
  5320. return afe_port_id;
  5321. }
  5322. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  5323. {
  5324. u32 bit_per_sample;
  5325. switch (bit_format) {
  5326. case SNDRV_PCM_FORMAT_S32_LE:
  5327. case SNDRV_PCM_FORMAT_S24_3LE:
  5328. case SNDRV_PCM_FORMAT_S24_LE:
  5329. bit_per_sample = 32;
  5330. break;
  5331. case SNDRV_PCM_FORMAT_S16_LE:
  5332. default:
  5333. bit_per_sample = 16;
  5334. break;
  5335. }
  5336. return bit_per_sample;
  5337. }
  5338. static void update_mi2s_clk_val(int dai_id, int stream)
  5339. {
  5340. u32 bit_per_sample;
  5341. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  5342. bit_per_sample =
  5343. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  5344. mi2s_clk[dai_id].clk_freq_in_hz =
  5345. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  5346. } else {
  5347. bit_per_sample =
  5348. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  5349. mi2s_clk[dai_id].clk_freq_in_hz =
  5350. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  5351. }
  5352. }
  5353. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  5354. {
  5355. int ret = 0;
  5356. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5357. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5358. int port_id = 0;
  5359. int index = cpu_dai->id;
  5360. port_id = msm_get_port_id(rtd->dai_link->id);
  5361. if (port_id < 0) {
  5362. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  5363. ret = port_id;
  5364. goto err;
  5365. }
  5366. if (enable) {
  5367. update_mi2s_clk_val(index, substream->stream);
  5368. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5369. mi2s_clk[index].clk_freq_in_hz);
  5370. }
  5371. mi2s_clk[index].enable = enable;
  5372. ret = afe_set_lpass_clock_v2(port_id,
  5373. &mi2s_clk[index]);
  5374. if (ret < 0) {
  5375. dev_err(rtd->card->dev,
  5376. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5377. __func__, port_id, ret);
  5378. goto err;
  5379. }
  5380. err:
  5381. return ret;
  5382. }
  5383. static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  5384. struct snd_pcm_hw_params *params)
  5385. {
  5386. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5387. struct snd_interval *rate = hw_param_interval(params,
  5388. SNDRV_PCM_HW_PARAM_RATE);
  5389. struct snd_interval *channels = hw_param_interval(params,
  5390. SNDRV_PCM_HW_PARAM_CHANNELS);
  5391. if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
  5392. channels->min = channels->max =
  5393. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  5394. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  5395. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  5396. rate->min = rate->max =
  5397. tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  5398. } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
  5399. channels->min = channels->max =
  5400. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  5401. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  5402. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  5403. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  5404. } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
  5405. channels->min = channels->max =
  5406. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  5407. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  5408. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  5409. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  5410. } else {
  5411. pr_err("%s: dai id 0x%x not supported\n",
  5412. __func__, cpu_dai->id);
  5413. return -EINVAL;
  5414. }
  5415. pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
  5416. __func__, cpu_dai->id, channels->max, rate->max,
  5417. params_format(params));
  5418. return 0;
  5419. }
  5420. static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  5421. struct snd_pcm_hw_params *params)
  5422. {
  5423. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5424. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5425. int ret = 0;
  5426. int slot_width = 32;
  5427. int channels, slots = 8;
  5428. unsigned int slot_mask, rate, clk_freq;
  5429. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  5430. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  5431. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  5432. switch (cpu_dai->id) {
  5433. case AFE_PORT_ID_PRIMARY_TDM_RX:
  5434. channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  5435. break;
  5436. case AFE_PORT_ID_SECONDARY_TDM_RX:
  5437. channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  5438. break;
  5439. case AFE_PORT_ID_TERTIARY_TDM_RX:
  5440. channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  5441. break;
  5442. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  5443. channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  5444. break;
  5445. case AFE_PORT_ID_QUINARY_TDM_RX:
  5446. channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  5447. break;
  5448. case AFE_PORT_ID_PRIMARY_TDM_TX:
  5449. channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  5450. break;
  5451. case AFE_PORT_ID_SECONDARY_TDM_TX:
  5452. channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  5453. break;
  5454. case AFE_PORT_ID_TERTIARY_TDM_TX:
  5455. channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  5456. break;
  5457. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  5458. channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  5459. break;
  5460. case AFE_PORT_ID_QUINARY_TDM_TX:
  5461. channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  5462. break;
  5463. default:
  5464. pr_err("%s: dai id 0x%x not supported\n",
  5465. __func__, cpu_dai->id);
  5466. return -EINVAL;
  5467. }
  5468. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  5469. /*2 slot config - bits 0 and 1 set for the first two slots */
  5470. slot_mask = 0x0000FFFF >> (16-channels);
  5471. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  5472. __func__, slot_width, slots);
  5473. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  5474. slots, slot_width);
  5475. if (ret < 0) {
  5476. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  5477. __func__, ret);
  5478. goto end;
  5479. }
  5480. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5481. 0, NULL, channels, slot_offset);
  5482. if (ret < 0) {
  5483. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  5484. __func__, ret);
  5485. goto end;
  5486. }
  5487. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  5488. /*2 slot config - bits 0 and 1 set for the first two slots */
  5489. slot_mask = 0x0000FFFF >> (16-channels);
  5490. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  5491. __func__, slot_width, slots);
  5492. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  5493. slots, slot_width);
  5494. if (ret < 0) {
  5495. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  5496. __func__, ret);
  5497. goto end;
  5498. }
  5499. ret = snd_soc_dai_set_channel_map(cpu_dai,
  5500. channels, slot_offset, 0, NULL);
  5501. if (ret < 0) {
  5502. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  5503. __func__, ret);
  5504. goto end;
  5505. }
  5506. } else {
  5507. ret = -EINVAL;
  5508. pr_err("%s: invalid use case, err:%d\n",
  5509. __func__, ret);
  5510. goto end;
  5511. }
  5512. rate = params_rate(params);
  5513. clk_freq = rate * slot_width * slots;
  5514. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  5515. if (ret < 0)
  5516. pr_err("%s: failed to set tdm clk, err:%d\n",
  5517. __func__, ret);
  5518. end:
  5519. return ret;
  5520. }
  5521. static int msm_get_tdm_mode(u32 port_id)
  5522. {
  5523. u32 tdm_mode;
  5524. switch (port_id) {
  5525. case AFE_PORT_ID_PRIMARY_TDM_RX:
  5526. case AFE_PORT_ID_PRIMARY_TDM_TX:
  5527. tdm_mode = TDM_PRI;
  5528. break;
  5529. case AFE_PORT_ID_SECONDARY_TDM_RX:
  5530. case AFE_PORT_ID_SECONDARY_TDM_TX:
  5531. tdm_mode = TDM_SEC;
  5532. break;
  5533. case AFE_PORT_ID_TERTIARY_TDM_RX:
  5534. case AFE_PORT_ID_TERTIARY_TDM_TX:
  5535. tdm_mode = TDM_TERT;
  5536. break;
  5537. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  5538. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  5539. tdm_mode = TDM_QUAT;
  5540. break;
  5541. case AFE_PORT_ID_QUINARY_TDM_RX:
  5542. case AFE_PORT_ID_QUINARY_TDM_TX:
  5543. tdm_mode = TDM_QUIN;
  5544. break;
  5545. default:
  5546. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  5547. tdm_mode = -EINVAL;
  5548. }
  5549. return tdm_mode;
  5550. }
  5551. static int qcs405_tdm_snd_startup(struct snd_pcm_substream *substream)
  5552. {
  5553. int ret = 0;
  5554. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5555. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5556. struct snd_soc_card *card = rtd->card;
  5557. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5558. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5559. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  5560. if (tdm_mode >= TDM_INTERFACE_MAX) {
  5561. ret = -EINVAL;
  5562. pr_err("%s: Invalid TDM interface %d\n",
  5563. __func__, ret);
  5564. return ret;
  5565. }
  5566. if (pdata->mi2s_gpio_p[tdm_mode]) {
  5567. ret = msm_cdc_pinctrl_select_active_state(
  5568. pdata->mi2s_gpio_p[tdm_mode]);
  5569. if (ret)
  5570. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  5571. __func__, ret);
  5572. }
  5573. /* Enable Mic bias for TDM Mics */
  5574. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  5575. if (pdata->tdm_micb_supply) {
  5576. ret = regulator_set_voltage(pdata->tdm_micb_supply,
  5577. pdata->tdm_micb_voltage,
  5578. pdata->tdm_micb_voltage);
  5579. if (ret) {
  5580. pr_err("%s: Setting voltage failed, err = %d\n",
  5581. __func__, ret);
  5582. return ret;
  5583. }
  5584. ret = regulator_set_load(pdata->tdm_micb_supply,
  5585. pdata->tdm_micb_current);
  5586. if (ret) {
  5587. pr_err("%s: Setting current failed, err = %d\n",
  5588. __func__, ret);
  5589. return ret;
  5590. }
  5591. ret = regulator_enable(pdata->tdm_micb_supply);
  5592. if (ret) {
  5593. pr_err("%s: regulator enable failed, err = %d\n",
  5594. __func__, ret);
  5595. return ret;
  5596. }
  5597. }
  5598. }
  5599. ret = qcs405_send_island_vad_config(dai_link->id);
  5600. if (ret) {
  5601. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5602. __func__, ret);
  5603. return ret;
  5604. }
  5605. return ret;
  5606. }
  5607. static void qcs405_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  5608. {
  5609. int ret = 0;
  5610. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5611. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5612. struct snd_soc_card *card = rtd->card;
  5613. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5614. u32 tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  5615. if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_TX) {
  5616. if (pdata->tdm_micb_supply) {
  5617. ret = regulator_disable(pdata->tdm_micb_supply);
  5618. if (ret)
  5619. pr_err("%s: regulator disable failed, err = %d\n",
  5620. __func__, ret);
  5621. regulator_set_voltage(pdata->tdm_micb_supply, 0,
  5622. pdata->tdm_micb_voltage);
  5623. regulator_set_load(pdata->tdm_micb_supply, 0);
  5624. }
  5625. }
  5626. if (pdata->mi2s_gpio_p[tdm_mode]) {
  5627. ret = msm_cdc_pinctrl_select_sleep_state(
  5628. pdata->mi2s_gpio_p[tdm_mode]);
  5629. if (ret)
  5630. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  5631. __func__, ret);
  5632. }
  5633. }
  5634. static struct snd_soc_ops qcs405_tdm_be_ops = {
  5635. .hw_params = qcs405_tdm_snd_hw_params,
  5636. .startup = qcs405_tdm_snd_startup,
  5637. .shutdown = qcs405_tdm_snd_shutdown
  5638. };
  5639. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  5640. {
  5641. cpumask_t mask;
  5642. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  5643. pm_qos_remove_request(&substream->latency_pm_qos_req);
  5644. cpumask_clear(&mask);
  5645. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  5646. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  5647. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  5648. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  5649. pm_qos_add_request(&substream->latency_pm_qos_req,
  5650. PM_QOS_CPU_DMA_LATENCY,
  5651. MSM_LL_QOS_VALUE);
  5652. return 0;
  5653. }
  5654. static struct snd_soc_ops msm_fe_qos_ops = {
  5655. .prepare = msm_fe_qos_prepare,
  5656. };
  5657. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  5658. {
  5659. int ret = 0, val = 0;
  5660. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5661. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5662. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  5663. int index = cpu_dai->id;
  5664. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  5665. struct snd_soc_card *card = rtd->card;
  5666. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5667. int data_format;
  5668. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  5669. data_format = mi2s_rx_cfg[index].data_format;
  5670. else
  5671. data_format = mi2s_tx_cfg[index].data_format;
  5672. dev_dbg(rtd->card->dev,
  5673. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5674. __func__, substream->name, substream->stream,
  5675. cpu_dai->name, cpu_dai->id);
  5676. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5677. ret = -EINVAL;
  5678. dev_err(rtd->card->dev,
  5679. "%s: CPU DAI id (%d) out of range\n",
  5680. __func__, cpu_dai->id);
  5681. goto err;
  5682. }
  5683. /*
  5684. * Mutex protection in case the same MI2S
  5685. * interface using for both TX and RX so
  5686. * that the same clock won't be enable twice.
  5687. */
  5688. mutex_lock(&mi2s_intf_conf[index].lock);
  5689. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  5690. /* Check if msm needs to provide the clock to the interface */
  5691. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  5692. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  5693. fmt = SND_SOC_DAIFMT_CBM_CFM;
  5694. }
  5695. if (data_format == AFE_DSD_DATA)
  5696. fmt = SND_SOC_DAIFMT_CBM_CFS;
  5697. ret = msm_mi2s_set_sclk(substream, true);
  5698. if (ret < 0) {
  5699. dev_err(rtd->card->dev,
  5700. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  5701. __func__, ret);
  5702. goto clean_up;
  5703. }
  5704. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  5705. if (ret < 0) {
  5706. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  5707. __func__, index, ret);
  5708. goto clk_off;
  5709. }
  5710. if (pdata->mi2s_gpio_p[index]) {
  5711. if ((data_format == AFE_DSD_DATA) &&
  5712. ((index == QUAT_MI2S) ||
  5713. (index == PRIM_MI2S))) {
  5714. msm_cdc_pinctrl_select_alt_active_state(
  5715. pdata->mi2s_gpio_p[index]);
  5716. } else {
  5717. msm_cdc_pinctrl_select_active_state(
  5718. pdata->mi2s_gpio_p[index]);
  5719. }
  5720. }
  5721. if (index == QUAT_MI2S || index == PRIM_MI2S) {
  5722. switch (data_format) {
  5723. case AFE_DSD_DATA:
  5724. if (pdata->mi2s_dsd_mode[index]) {
  5725. val = ioread32(
  5726. pdata->mi2s_dsd_mode[index]);
  5727. val = val | 0x1;
  5728. iowrite32(val,
  5729. pdata->mi2s_dsd_mode[index]);
  5730. }
  5731. break;
  5732. default:
  5733. break;
  5734. }
  5735. }
  5736. }
  5737. ret = qcs405_send_island_vad_config(dai_link->id);
  5738. if (ret) {
  5739. pr_err("%s: send island/vad cfg failed, err = %d\n",
  5740. __func__, ret);
  5741. return ret;
  5742. }
  5743. clk_off:
  5744. if (ret < 0)
  5745. msm_mi2s_set_sclk(substream, false);
  5746. clean_up:
  5747. if (ret < 0)
  5748. mi2s_intf_conf[index].ref_cnt--;
  5749. mutex_unlock(&mi2s_intf_conf[index].lock);
  5750. err:
  5751. return ret;
  5752. }
  5753. static int msm_mi2s_snd_hw_free(struct snd_pcm_substream *substream)
  5754. {
  5755. int i, data_format = 0;
  5756. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5757. int index = rtd->cpu_dai->id;
  5758. struct snd_soc_card *card = rtd->card;
  5759. struct snd_soc_component *component;
  5760. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  5761. data_format = mi2s_rx_cfg[index].data_format;
  5762. else
  5763. data_format = mi2s_tx_cfg[index].data_format;
  5764. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5765. substream->name, substream->stream);
  5766. /* Call csra mute function if data format is DSD, else return */
  5767. if (data_format != AFE_DSD_DATA)
  5768. return 0;
  5769. for (i = 0; i < card->num_aux_devs; i++) {
  5770. component =
  5771. soc_find_component(card->aux_dev[i].codec_of_node,
  5772. NULL);
  5773. csra66x0_hw_free_mute(component);
  5774. }
  5775. return 0;
  5776. }
  5777. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  5778. {
  5779. int ret;
  5780. int val;
  5781. int data_format;
  5782. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5783. int index = rtd->cpu_dai->id;
  5784. struct snd_soc_card *card = rtd->card;
  5785. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5786. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  5787. data_format = mi2s_rx_cfg[index].data_format;
  5788. else
  5789. data_format = mi2s_tx_cfg[index].data_format;
  5790. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5791. substream->name, substream->stream);
  5792. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5793. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  5794. return;
  5795. }
  5796. mutex_lock(&mi2s_intf_conf[index].lock);
  5797. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  5798. if (pdata->mi2s_gpio_p[index])
  5799. msm_cdc_pinctrl_select_sleep_state(
  5800. pdata->mi2s_gpio_p[index]);
  5801. if (index == QUAT_MI2S || index == PRIM_MI2S) {
  5802. switch (data_format) {
  5803. case AFE_DSD_DATA:
  5804. if (pdata->mi2s_dsd_mode[index]) {
  5805. val = ioread32(
  5806. pdata->mi2s_dsd_mode[index]);
  5807. val = val & ~1;
  5808. iowrite32(val,
  5809. pdata->mi2s_dsd_mode[index]);
  5810. }
  5811. break;
  5812. default:
  5813. break;
  5814. }
  5815. }
  5816. ret = msm_mi2s_set_sclk(substream, false);
  5817. if (ret < 0)
  5818. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  5819. __func__, index, ret);
  5820. }
  5821. mutex_unlock(&mi2s_intf_conf[index].lock);
  5822. }
  5823. static int msm_meta_mi2s_set_sclk(struct snd_pcm_substream *substream,
  5824. int member_id, bool enable)
  5825. {
  5826. int ret = 0;
  5827. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5828. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5829. int be_id = 0;
  5830. int port_id = 0;
  5831. int index = cpu_dai->id;
  5832. u32 bit_per_sample = 0;
  5833. switch (member_id) {
  5834. case PRIM_MI2S:
  5835. be_id = MSM_BACKEND_DAI_PRI_MI2S_RX;
  5836. break;
  5837. case SEC_MI2S:
  5838. be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX;
  5839. break;
  5840. case TERT_MI2S:
  5841. be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX;
  5842. break;
  5843. case QUAT_MI2S:
  5844. be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX;
  5845. break;
  5846. default:
  5847. dev_err(rtd->card->dev, "%s: Invalid member_id\n", __func__);
  5848. ret = -EINVAL;
  5849. goto err;
  5850. }
  5851. port_id = msm_get_port_id(be_id);
  5852. if (port_id < 0) {
  5853. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  5854. ret = port_id;
  5855. goto err;
  5856. }
  5857. if (enable) {
  5858. bit_per_sample =
  5859. get_mi2s_bits_per_sample(
  5860. meta_mi2s_rx_cfg[index].bit_format);
  5861. mi2s_clk[member_id].clk_freq_in_hz =
  5862. meta_mi2s_rx_cfg[index].sample_rate * 2 *
  5863. bit_per_sample;
  5864. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  5865. mi2s_clk[member_id].clk_freq_in_hz);
  5866. }
  5867. mi2s_clk[member_id].enable = enable;
  5868. ret = afe_set_lpass_clock_v2(port_id, &mi2s_clk[member_id]);
  5869. if (ret < 0) {
  5870. dev_err(rtd->card->dev,
  5871. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  5872. __func__, port_id, ret);
  5873. goto err;
  5874. }
  5875. err:
  5876. return ret;
  5877. }
  5878. static int msm_meta_mi2s_snd_startup(struct snd_pcm_substream *substream)
  5879. {
  5880. int ret = 0;
  5881. int i = 0;
  5882. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5883. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5884. int index = cpu_dai->id;
  5885. int member_port = 0;
  5886. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  5887. struct snd_soc_card *card = rtd->card;
  5888. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5889. u16 port_id = 0;
  5890. dev_dbg(rtd->card->dev,
  5891. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  5892. __func__, substream->name, substream->stream,
  5893. cpu_dai->name, cpu_dai->id);
  5894. if (index < PRIM_META_MI2S || index >= META_MI2S_MAX) {
  5895. ret = -EINVAL;
  5896. dev_err(rtd->card->dev,
  5897. "%s: CPU DAI id (%d) out of range\n",
  5898. __func__, cpu_dai->id);
  5899. goto err;
  5900. }
  5901. for (i = 0; i < meta_mi2s_intf_conf[index].num_member_ports; i++) {
  5902. member_port = meta_mi2s_intf_conf[index].member_port[i];
  5903. if (!mi2s_intf_conf[member_port].msm_is_mi2s_master) {
  5904. mi2s_clk[member_port].clk_id =
  5905. mi2s_ebit_clk[member_port];
  5906. fmt = SND_SOC_DAIFMT_CBM_CFM;
  5907. }
  5908. ret = msm_meta_mi2s_set_sclk(substream, member_port, true);
  5909. if (ret < 0) {
  5910. dev_err(rtd->card->dev,
  5911. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  5912. __func__, ret);
  5913. goto clk_off;
  5914. }
  5915. meta_mi2s_intf_conf[index].clk_enable[i] = true;
  5916. if (i == 0) {
  5917. port_id = msm_get_port_id(rtd->dai_link->id);
  5918. ret = afe_set_clk_id(port_id,
  5919. mi2s_clk[member_port].clk_id);
  5920. if (ret < 0)
  5921. pr_err("%s: afe_set_clk_id fail %d\n",
  5922. __func__, ret);
  5923. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  5924. if (ret < 0) {
  5925. pr_err("%s: set fmt cpu dai failed for META_MI2S (%d), err:%d\n",
  5926. __func__, index, ret);
  5927. goto clk_off;
  5928. }
  5929. }
  5930. if (pdata->mi2s_gpio_p[member_port])
  5931. msm_cdc_pinctrl_select_active_state(
  5932. pdata->mi2s_gpio_p[member_port]);
  5933. }
  5934. return 0;
  5935. clk_off:
  5936. for (i = 0; i < meta_mi2s_intf_conf[index].num_member_ports; i++) {
  5937. member_port = meta_mi2s_intf_conf[index].member_port[i];
  5938. if (pdata->mi2s_gpio_p[member_port])
  5939. msm_cdc_pinctrl_select_sleep_state(
  5940. pdata->mi2s_gpio_p[member_port]);
  5941. if (meta_mi2s_intf_conf[index].clk_enable[i]) {
  5942. msm_meta_mi2s_set_sclk(substream, member_port, false);
  5943. meta_mi2s_intf_conf[index].clk_enable[i] = false;
  5944. }
  5945. }
  5946. err:
  5947. return ret;
  5948. }
  5949. static void msm_meta_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  5950. {
  5951. int ret = 0;
  5952. int i = 0;
  5953. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5954. int index = rtd->cpu_dai->id;
  5955. int member_port = 0;
  5956. struct snd_soc_card *card = rtd->card;
  5957. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  5958. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  5959. substream->name, substream->stream);
  5960. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  5961. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  5962. return;
  5963. }
  5964. for (i = 0; i < meta_mi2s_intf_conf[index].num_member_ports; i++) {
  5965. member_port = meta_mi2s_intf_conf[index].member_port[i];
  5966. if (pdata->mi2s_gpio_p[member_port])
  5967. msm_cdc_pinctrl_select_sleep_state(
  5968. pdata->mi2s_gpio_p[member_port]);
  5969. ret = msm_meta_mi2s_set_sclk(substream, member_port, false);
  5970. if (ret < 0)
  5971. pr_err("%s:clock disable failed for META MI2S (%d); ret=%d\n",
  5972. __func__, index, ret);
  5973. }
  5974. }
  5975. static int msm_spdif_set_clk(struct snd_pcm_substream *substream, bool enable)
  5976. {
  5977. int ret = 0;
  5978. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  5979. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  5980. int port_id = cpu_dai->id;
  5981. struct afe_clk_set clk_cfg;
  5982. clk_cfg.clk_set_minor_version = Q6AFE_LPASS_CLK_CONFIG_API_VERSION;
  5983. clk_cfg.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO;
  5984. clk_cfg.clk_root = Q6AFE_LPASS_CLK_ROOT_DEFAULT;
  5985. clk_cfg.enable = enable;
  5986. /* Set core clock (based on sample rate for RX, fixed for TX) */
  5987. switch (port_id) {
  5988. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  5989. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE;
  5990. /* rate x 2ch x 2_for_biphase_coding x 32_bits_per_sample */
  5991. clk_cfg.clk_freq_in_hz =
  5992. spdif_rx_cfg[PRIM_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5993. break;
  5994. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  5995. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE;
  5996. clk_cfg.clk_freq_in_hz =
  5997. spdif_rx_cfg[SEC_SPDIF_RX].sample_rate * 2 * 2 * 32;
  5998. break;
  5999. case AFE_PORT_ID_PRIMARY_SPDIF_TX:
  6000. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE;
  6001. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  6002. break;
  6003. case AFE_PORT_ID_SECONDARY_SPDIF_TX:
  6004. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE;
  6005. clk_cfg.clk_freq_in_hz = SPDIF_TX_CORE_CLK_163_P84_MHZ;
  6006. break;
  6007. }
  6008. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  6009. if (ret < 0) {
  6010. dev_err(rtd->card->dev,
  6011. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  6012. __func__, port_id, ret);
  6013. goto err;
  6014. }
  6015. /* Set NPL clock for RX in addition */
  6016. switch (port_id) {
  6017. case AFE_PORT_ID_PRIMARY_SPDIF_RX:
  6018. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_NPL;
  6019. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  6020. if (ret < 0) {
  6021. dev_err(rtd->card->dev,
  6022. "%s: afe NPL failed port 0x%x, err:%d\n",
  6023. __func__, port_id, ret);
  6024. goto err;
  6025. }
  6026. break;
  6027. case AFE_PORT_ID_SECONDARY_SPDIF_RX:
  6028. clk_cfg.clk_id = AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_NPL;
  6029. ret = afe_set_lpass_clock_v2(port_id, &clk_cfg);
  6030. if (ret < 0) {
  6031. dev_err(rtd->card->dev,
  6032. "%s: afe NPL failed for port 0x%x, err:%d\n",
  6033. __func__, port_id, ret);
  6034. goto err;
  6035. }
  6036. break;
  6037. }
  6038. if (enable) {
  6039. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  6040. clk_cfg.clk_freq_in_hz);
  6041. }
  6042. err:
  6043. return ret;
  6044. }
  6045. static int msm_spdif_snd_startup(struct snd_pcm_substream *substream)
  6046. {
  6047. int ret = 0;
  6048. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  6049. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  6050. int port_id = cpu_dai->id;
  6051. dev_dbg(rtd->card->dev,
  6052. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  6053. __func__, substream->name, substream->stream,
  6054. cpu_dai->name, cpu_dai->id);
  6055. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  6056. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  6057. ret = -EINVAL;
  6058. dev_err(rtd->card->dev,
  6059. "%s: CPU DAI id (%d) out of range\n",
  6060. __func__, cpu_dai->id);
  6061. goto err;
  6062. }
  6063. ret = msm_spdif_set_clk(substream, true);
  6064. if (ret < 0) {
  6065. dev_err(rtd->card->dev,
  6066. "%s: afe lpass clock failed to enable (%d), err:%d\n",
  6067. __func__, port_id, ret);
  6068. }
  6069. err:
  6070. return ret;
  6071. }
  6072. static void msm_spdif_snd_shutdown(struct snd_pcm_substream *substream)
  6073. {
  6074. int ret;
  6075. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  6076. int port_id = rtd->cpu_dai->id;
  6077. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  6078. substream->name, substream->stream);
  6079. if (port_id < AFE_PORT_ID_PRIMARY_SPDIF_RX ||
  6080. port_id > AFE_PORT_ID_SECONDARY_SPDIF_TX) {
  6081. pr_err("%s:invalid SPDIF DAI(%d)\n", __func__, port_id);
  6082. return;
  6083. }
  6084. ret = msm_spdif_set_clk(substream, false);
  6085. if (ret < 0)
  6086. pr_err("%s:clock disable failed for SPDIF (%d); ret=%d\n",
  6087. __func__, port_id, ret);
  6088. }
  6089. static struct snd_soc_ops msm_mi2s_be_ops = {
  6090. .startup = msm_mi2s_snd_startup,
  6091. .hw_free = msm_mi2s_snd_hw_free,
  6092. .shutdown = msm_mi2s_snd_shutdown,
  6093. };
  6094. static struct snd_soc_ops msm_meta_mi2s_be_ops = {
  6095. .startup = msm_meta_mi2s_snd_startup,
  6096. .shutdown = msm_meta_mi2s_snd_shutdown,
  6097. };
  6098. static struct snd_soc_ops msm_auxpcm_be_ops = {
  6099. .startup = msm_snd_auxpcm_startup,
  6100. };
  6101. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  6102. .startup = msm_snd_cdc_dma_startup,
  6103. .hw_params = msm_snd_cdc_dma_hw_params,
  6104. };
  6105. static struct snd_soc_ops msm_be_ops = {
  6106. .hw_params = msm_snd_hw_params,
  6107. };
  6108. static struct snd_soc_ops msm_wcn_ops = {
  6109. .hw_params = msm_wcn_hw_params,
  6110. };
  6111. static struct snd_soc_ops msm_spdif_be_ops = {
  6112. .startup = msm_spdif_snd_startup,
  6113. .shutdown = msm_spdif_snd_shutdown,
  6114. };
  6115. /* Digital audio interface glue - connects codec <---> CPU */
  6116. static struct snd_soc_dai_link msm_common_dai_links[] = {
  6117. /* FrontEnd DAI Links */
  6118. {
  6119. .name = MSM_DAILINK_NAME(Media1),
  6120. .stream_name = "MultiMedia1",
  6121. .cpu_dai_name = "MultiMedia1",
  6122. .platform_name = "msm-pcm-dsp.0",
  6123. .dynamic = 1,
  6124. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6125. .dpcm_playback = 1,
  6126. .dpcm_capture = 1,
  6127. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6128. SND_SOC_DPCM_TRIGGER_POST},
  6129. .codec_dai_name = "snd-soc-dummy-dai",
  6130. .codec_name = "snd-soc-dummy",
  6131. .ignore_suspend = 1,
  6132. /* this dainlink has playback support */
  6133. .ignore_pmdown_time = 1,
  6134. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6135. },
  6136. {
  6137. .name = MSM_DAILINK_NAME(Media2),
  6138. .stream_name = "MultiMedia2",
  6139. .cpu_dai_name = "MultiMedia2",
  6140. .platform_name = "msm-pcm-dsp.0",
  6141. .dynamic = 1,
  6142. .dpcm_playback = 1,
  6143. .dpcm_capture = 1,
  6144. .codec_dai_name = "snd-soc-dummy-dai",
  6145. .codec_name = "snd-soc-dummy",
  6146. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6147. SND_SOC_DPCM_TRIGGER_POST},
  6148. .ignore_suspend = 1,
  6149. /* this dainlink has playback support */
  6150. .ignore_pmdown_time = 1,
  6151. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  6152. },
  6153. {
  6154. .name = "VoiceMMode1",
  6155. .stream_name = "VoiceMMode1",
  6156. .cpu_dai_name = "VoiceMMode1",
  6157. .platform_name = "msm-pcm-voice",
  6158. .dynamic = 1,
  6159. .dpcm_playback = 1,
  6160. .dpcm_capture = 1,
  6161. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6162. SND_SOC_DPCM_TRIGGER_POST},
  6163. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6164. .ignore_suspend = 1,
  6165. .ignore_pmdown_time = 1,
  6166. .codec_dai_name = "snd-soc-dummy-dai",
  6167. .codec_name = "snd-soc-dummy",
  6168. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  6169. },
  6170. {
  6171. .name = "MSM VoIP",
  6172. .stream_name = "VoIP",
  6173. .cpu_dai_name = "VoIP",
  6174. .platform_name = "msm-voip-dsp",
  6175. .dynamic = 1,
  6176. .dpcm_playback = 1,
  6177. .dpcm_capture = 1,
  6178. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6179. SND_SOC_DPCM_TRIGGER_POST},
  6180. .codec_dai_name = "snd-soc-dummy-dai",
  6181. .codec_name = "snd-soc-dummy",
  6182. .ignore_suspend = 1,
  6183. /* this dainlink has playback support */
  6184. .ignore_pmdown_time = 1,
  6185. .id = MSM_FRONTEND_DAI_VOIP,
  6186. },
  6187. {
  6188. .name = MSM_DAILINK_NAME(ULL),
  6189. .stream_name = "MultiMedia3",
  6190. .cpu_dai_name = "MultiMedia3",
  6191. .platform_name = "msm-pcm-dsp.2",
  6192. .dynamic = 1,
  6193. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6194. .dpcm_playback = 1,
  6195. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6196. SND_SOC_DPCM_TRIGGER_POST},
  6197. .codec_dai_name = "snd-soc-dummy-dai",
  6198. .codec_name = "snd-soc-dummy",
  6199. .ignore_suspend = 1,
  6200. /* this dainlink has playback support */
  6201. .ignore_pmdown_time = 1,
  6202. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  6203. },
  6204. /* Hostless PCM purpose */
  6205. {
  6206. .name = "SLIMBUS_0 Hostless",
  6207. .stream_name = "SLIMBUS_0 Hostless",
  6208. .cpu_dai_name = "SLIMBUS0_HOSTLESS",
  6209. .platform_name = "msm-pcm-hostless",
  6210. .dynamic = 1,
  6211. .dpcm_playback = 1,
  6212. .dpcm_capture = 1,
  6213. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6214. SND_SOC_DPCM_TRIGGER_POST},
  6215. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6216. .ignore_suspend = 1,
  6217. /* this dailink has playback support */
  6218. .ignore_pmdown_time = 1,
  6219. .codec_dai_name = "snd-soc-dummy-dai",
  6220. .codec_name = "snd-soc-dummy",
  6221. },
  6222. {
  6223. .name = "MSM AFE-PCM RX",
  6224. .stream_name = "AFE-PROXY RX",
  6225. .cpu_dai_name = "msm-dai-q6-dev.241",
  6226. .codec_name = "msm-stub-codec.1",
  6227. .codec_dai_name = "msm-stub-rx",
  6228. .platform_name = "msm-pcm-afe",
  6229. .dpcm_playback = 1,
  6230. .ignore_suspend = 1,
  6231. /* this dainlink has playback support */
  6232. .ignore_pmdown_time = 1,
  6233. },
  6234. {
  6235. .name = "MSM AFE-PCM TX",
  6236. .stream_name = "AFE-PROXY TX",
  6237. .cpu_dai_name = "msm-dai-q6-dev.240",
  6238. .codec_name = "msm-stub-codec.1",
  6239. .codec_dai_name = "msm-stub-tx",
  6240. .platform_name = "msm-pcm-afe",
  6241. .dpcm_capture = 1,
  6242. .ignore_suspend = 1,
  6243. },
  6244. {
  6245. .name = MSM_DAILINK_NAME(Compress1),
  6246. .stream_name = "Compress1",
  6247. .cpu_dai_name = "MultiMedia4",
  6248. .platform_name = "msm-compress-dsp",
  6249. .dynamic = 1,
  6250. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6251. .dpcm_playback = 1,
  6252. .dpcm_capture = 1,
  6253. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6254. SND_SOC_DPCM_TRIGGER_POST},
  6255. .codec_dai_name = "snd-soc-dummy-dai",
  6256. .codec_name = "snd-soc-dummy",
  6257. .ignore_suspend = 1,
  6258. .ignore_pmdown_time = 1,
  6259. /* this dainlink has playback support */
  6260. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  6261. },
  6262. {
  6263. .name = "AUXPCM Hostless",
  6264. .stream_name = "AUXPCM Hostless",
  6265. .cpu_dai_name = "AUXPCM_HOSTLESS",
  6266. .platform_name = "msm-pcm-hostless",
  6267. .dynamic = 1,
  6268. .dpcm_playback = 1,
  6269. .dpcm_capture = 1,
  6270. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6271. SND_SOC_DPCM_TRIGGER_POST},
  6272. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6273. .ignore_suspend = 1,
  6274. /* this dainlink has playback support */
  6275. .ignore_pmdown_time = 1,
  6276. .codec_dai_name = "snd-soc-dummy-dai",
  6277. .codec_name = "snd-soc-dummy",
  6278. },
  6279. {
  6280. .name = "SLIMBUS_1 Hostless",
  6281. .stream_name = "SLIMBUS_1 Hostless",
  6282. .cpu_dai_name = "SLIMBUS1_HOSTLESS",
  6283. .platform_name = "msm-pcm-hostless",
  6284. .dynamic = 1,
  6285. .dpcm_playback = 1,
  6286. .dpcm_capture = 1,
  6287. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6288. SND_SOC_DPCM_TRIGGER_POST},
  6289. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6290. .ignore_suspend = 1,
  6291. /* this dailink has playback support */
  6292. .ignore_pmdown_time = 1,
  6293. .codec_dai_name = "snd-soc-dummy-dai",
  6294. .codec_name = "snd-soc-dummy",
  6295. },
  6296. {
  6297. .name = "SLIMBUS_3 Hostless",
  6298. .stream_name = "SLIMBUS_3 Hostless",
  6299. .cpu_dai_name = "SLIMBUS3_HOSTLESS",
  6300. .platform_name = "msm-pcm-hostless",
  6301. .dynamic = 1,
  6302. .dpcm_playback = 1,
  6303. .dpcm_capture = 1,
  6304. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6305. SND_SOC_DPCM_TRIGGER_POST},
  6306. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6307. .ignore_suspend = 1,
  6308. /* this dailink has playback support */
  6309. .ignore_pmdown_time = 1,
  6310. .codec_dai_name = "snd-soc-dummy-dai",
  6311. .codec_name = "snd-soc-dummy",
  6312. },
  6313. {
  6314. .name = "SLIMBUS_4 Hostless",
  6315. .stream_name = "SLIMBUS_4 Hostless",
  6316. .cpu_dai_name = "SLIMBUS4_HOSTLESS",
  6317. .platform_name = "msm-pcm-hostless",
  6318. .dynamic = 1,
  6319. .dpcm_playback = 1,
  6320. .dpcm_capture = 1,
  6321. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6322. SND_SOC_DPCM_TRIGGER_POST},
  6323. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6324. .ignore_suspend = 1,
  6325. /* this dailink has playback support */
  6326. .ignore_pmdown_time = 1,
  6327. .codec_dai_name = "snd-soc-dummy-dai",
  6328. .codec_name = "snd-soc-dummy",
  6329. },
  6330. {
  6331. .name = MSM_DAILINK_NAME(LowLatency),
  6332. .stream_name = "MultiMedia5",
  6333. .cpu_dai_name = "MultiMedia5",
  6334. .platform_name = "msm-pcm-dsp.1",
  6335. .dynamic = 1,
  6336. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6337. .dpcm_playback = 1,
  6338. .dpcm_capture = 1,
  6339. .codec_dai_name = "snd-soc-dummy-dai",
  6340. .codec_name = "snd-soc-dummy",
  6341. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6342. SND_SOC_DPCM_TRIGGER_POST},
  6343. .ignore_suspend = 1,
  6344. /* this dainlink has playback support */
  6345. .ignore_pmdown_time = 1,
  6346. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  6347. .ops = &msm_fe_qos_ops,
  6348. },
  6349. {
  6350. .name = "Listen 1 Audio Service",
  6351. .stream_name = "Listen 1 Audio Service",
  6352. .cpu_dai_name = "LSM1",
  6353. .platform_name = "msm-lsm-client",
  6354. .dynamic = 1,
  6355. .dpcm_capture = 1,
  6356. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6357. SND_SOC_DPCM_TRIGGER_POST },
  6358. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6359. .ignore_suspend = 1,
  6360. .codec_dai_name = "snd-soc-dummy-dai",
  6361. .codec_name = "snd-soc-dummy",
  6362. .id = MSM_FRONTEND_DAI_LSM1,
  6363. },
  6364. /* Multiple Tunnel instances */
  6365. {
  6366. .name = MSM_DAILINK_NAME(Compress2),
  6367. .stream_name = "Compress2",
  6368. .cpu_dai_name = "MultiMedia7",
  6369. .platform_name = "msm-compress-dsp",
  6370. .dynamic = 1,
  6371. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6372. .dpcm_playback = 1,
  6373. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6374. SND_SOC_DPCM_TRIGGER_POST},
  6375. .codec_dai_name = "snd-soc-dummy-dai",
  6376. .codec_name = "snd-soc-dummy",
  6377. .ignore_suspend = 1,
  6378. .ignore_pmdown_time = 1,
  6379. /* this dainlink has playback support */
  6380. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  6381. },
  6382. {
  6383. .name = MSM_DAILINK_NAME(MultiMedia10),
  6384. .stream_name = "MultiMedia10",
  6385. .cpu_dai_name = "MultiMedia10",
  6386. .platform_name = "msm-pcm-dsp.1",
  6387. .dynamic = 1,
  6388. .dpcm_playback = 1,
  6389. .dpcm_capture = 1,
  6390. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6391. SND_SOC_DPCM_TRIGGER_POST},
  6392. .codec_dai_name = "snd-soc-dummy-dai",
  6393. .codec_name = "snd-soc-dummy",
  6394. .ignore_suspend = 1,
  6395. .ignore_pmdown_time = 1,
  6396. /* this dainlink has playback support */
  6397. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  6398. },
  6399. {
  6400. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  6401. .stream_name = "MM_NOIRQ",
  6402. .cpu_dai_name = "MultiMedia8",
  6403. .platform_name = "msm-pcm-dsp-noirq",
  6404. .dynamic = 1,
  6405. .dpcm_playback = 1,
  6406. .dpcm_capture = 1,
  6407. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6408. SND_SOC_DPCM_TRIGGER_POST},
  6409. .codec_dai_name = "snd-soc-dummy-dai",
  6410. .codec_name = "snd-soc-dummy",
  6411. .ignore_suspend = 1,
  6412. .ignore_pmdown_time = 1,
  6413. /* this dainlink has playback support */
  6414. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  6415. .ops = &msm_fe_qos_ops,
  6416. },
  6417. /* HDMI Hostless */
  6418. {
  6419. .name = "HDMI_RX_HOSTLESS",
  6420. .stream_name = "HDMI_RX_HOSTLESS",
  6421. .cpu_dai_name = "HDMI_HOSTLESS",
  6422. .platform_name = "msm-pcm-hostless",
  6423. .dynamic = 1,
  6424. .dpcm_playback = 1,
  6425. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6426. SND_SOC_DPCM_TRIGGER_POST},
  6427. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6428. .ignore_suspend = 1,
  6429. .ignore_pmdown_time = 1,
  6430. .codec_dai_name = "snd-soc-dummy-dai",
  6431. .codec_name = "snd-soc-dummy",
  6432. },
  6433. {
  6434. .name = "VoiceMMode2",
  6435. .stream_name = "VoiceMMode2",
  6436. .cpu_dai_name = "VoiceMMode2",
  6437. .platform_name = "msm-pcm-voice",
  6438. .dynamic = 1,
  6439. .dpcm_playback = 1,
  6440. .dpcm_capture = 1,
  6441. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6442. SND_SOC_DPCM_TRIGGER_POST},
  6443. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6444. .ignore_suspend = 1,
  6445. .ignore_pmdown_time = 1,
  6446. .codec_dai_name = "snd-soc-dummy-dai",
  6447. .codec_name = "snd-soc-dummy",
  6448. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  6449. },
  6450. /* LSM FE */
  6451. {
  6452. .name = "Listen 2 Audio Service",
  6453. .stream_name = "Listen 2 Audio Service",
  6454. .cpu_dai_name = "LSM2",
  6455. .platform_name = "msm-lsm-client",
  6456. .dynamic = 1,
  6457. .dpcm_capture = 1,
  6458. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6459. SND_SOC_DPCM_TRIGGER_POST },
  6460. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6461. .ignore_suspend = 1,
  6462. .codec_dai_name = "snd-soc-dummy-dai",
  6463. .codec_name = "snd-soc-dummy",
  6464. .id = MSM_FRONTEND_DAI_LSM2,
  6465. },
  6466. {
  6467. .name = "Listen 3 Audio Service",
  6468. .stream_name = "Listen 3 Audio Service",
  6469. .cpu_dai_name = "LSM3",
  6470. .platform_name = "msm-lsm-client",
  6471. .dynamic = 1,
  6472. .dpcm_capture = 1,
  6473. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6474. SND_SOC_DPCM_TRIGGER_POST },
  6475. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6476. .ignore_suspend = 1,
  6477. .codec_dai_name = "snd-soc-dummy-dai",
  6478. .codec_name = "snd-soc-dummy",
  6479. .id = MSM_FRONTEND_DAI_LSM3,
  6480. },
  6481. {
  6482. .name = "Listen 4 Audio Service",
  6483. .stream_name = "Listen 4 Audio Service",
  6484. .cpu_dai_name = "LSM4",
  6485. .platform_name = "msm-lsm-client",
  6486. .dynamic = 1,
  6487. .dpcm_capture = 1,
  6488. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6489. SND_SOC_DPCM_TRIGGER_POST },
  6490. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6491. .ignore_suspend = 1,
  6492. .codec_dai_name = "snd-soc-dummy-dai",
  6493. .codec_name = "snd-soc-dummy",
  6494. .id = MSM_FRONTEND_DAI_LSM4,
  6495. },
  6496. {
  6497. .name = "Listen 5 Audio Service",
  6498. .stream_name = "Listen 5 Audio Service",
  6499. .cpu_dai_name = "LSM5",
  6500. .platform_name = "msm-lsm-client",
  6501. .dynamic = 1,
  6502. .dpcm_capture = 1,
  6503. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6504. SND_SOC_DPCM_TRIGGER_POST },
  6505. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6506. .ignore_suspend = 1,
  6507. .codec_dai_name = "snd-soc-dummy-dai",
  6508. .codec_name = "snd-soc-dummy",
  6509. .id = MSM_FRONTEND_DAI_LSM5,
  6510. },
  6511. {
  6512. .name = "Listen 6 Audio Service",
  6513. .stream_name = "Listen 6 Audio Service",
  6514. .cpu_dai_name = "LSM6",
  6515. .platform_name = "msm-lsm-client",
  6516. .dynamic = 1,
  6517. .dpcm_capture = 1,
  6518. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6519. SND_SOC_DPCM_TRIGGER_POST },
  6520. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6521. .ignore_suspend = 1,
  6522. .codec_dai_name = "snd-soc-dummy-dai",
  6523. .codec_name = "snd-soc-dummy",
  6524. .id = MSM_FRONTEND_DAI_LSM6,
  6525. },
  6526. {
  6527. .name = "Listen 7 Audio Service",
  6528. .stream_name = "Listen 7 Audio Service",
  6529. .cpu_dai_name = "LSM7",
  6530. .platform_name = "msm-lsm-client",
  6531. .dynamic = 1,
  6532. .dpcm_capture = 1,
  6533. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6534. SND_SOC_DPCM_TRIGGER_POST },
  6535. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6536. .ignore_suspend = 1,
  6537. .codec_dai_name = "snd-soc-dummy-dai",
  6538. .codec_name = "snd-soc-dummy",
  6539. .id = MSM_FRONTEND_DAI_LSM7,
  6540. },
  6541. {
  6542. .name = "Listen 8 Audio Service",
  6543. .stream_name = "Listen 8 Audio Service",
  6544. .cpu_dai_name = "LSM8",
  6545. .platform_name = "msm-lsm-client",
  6546. .dynamic = 1,
  6547. .dpcm_capture = 1,
  6548. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  6549. SND_SOC_DPCM_TRIGGER_POST },
  6550. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6551. .ignore_suspend = 1,
  6552. .codec_dai_name = "snd-soc-dummy-dai",
  6553. .codec_name = "snd-soc-dummy",
  6554. .id = MSM_FRONTEND_DAI_LSM8,
  6555. },
  6556. {
  6557. .name = MSM_DAILINK_NAME(Media9),
  6558. .stream_name = "MultiMedia9",
  6559. .cpu_dai_name = "MultiMedia9",
  6560. .platform_name = "msm-pcm-dsp.0",
  6561. .dynamic = 1,
  6562. .dpcm_playback = 1,
  6563. .dpcm_capture = 1,
  6564. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6565. SND_SOC_DPCM_TRIGGER_POST},
  6566. .codec_dai_name = "snd-soc-dummy-dai",
  6567. .codec_name = "snd-soc-dummy",
  6568. .ignore_suspend = 1,
  6569. /* this dainlink has playback support */
  6570. .ignore_pmdown_time = 1,
  6571. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  6572. },
  6573. {
  6574. .name = MSM_DAILINK_NAME(Compress4),
  6575. .stream_name = "Compress4",
  6576. .cpu_dai_name = "MultiMedia11",
  6577. .platform_name = "msm-compress-dsp",
  6578. .dynamic = 1,
  6579. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6580. .dpcm_playback = 1,
  6581. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6582. SND_SOC_DPCM_TRIGGER_POST},
  6583. .codec_dai_name = "snd-soc-dummy-dai",
  6584. .codec_name = "snd-soc-dummy",
  6585. .ignore_suspend = 1,
  6586. .ignore_pmdown_time = 1,
  6587. /* this dainlink has playback support */
  6588. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  6589. },
  6590. {
  6591. .name = MSM_DAILINK_NAME(Compress5),
  6592. .stream_name = "Compress5",
  6593. .cpu_dai_name = "MultiMedia12",
  6594. .platform_name = "msm-compress-dsp",
  6595. .dynamic = 1,
  6596. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6597. .dpcm_playback = 1,
  6598. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6599. SND_SOC_DPCM_TRIGGER_POST},
  6600. .codec_dai_name = "snd-soc-dummy-dai",
  6601. .codec_name = "snd-soc-dummy",
  6602. .ignore_suspend = 1,
  6603. .ignore_pmdown_time = 1,
  6604. /* this dainlink has playback support */
  6605. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  6606. },
  6607. {
  6608. .name = MSM_DAILINK_NAME(Compress6),
  6609. .stream_name = "Compress6",
  6610. .cpu_dai_name = "MultiMedia13",
  6611. .platform_name = "msm-compress-dsp",
  6612. .dynamic = 1,
  6613. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6614. .dpcm_playback = 1,
  6615. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6616. SND_SOC_DPCM_TRIGGER_POST},
  6617. .codec_dai_name = "snd-soc-dummy-dai",
  6618. .codec_name = "snd-soc-dummy",
  6619. .ignore_suspend = 1,
  6620. .ignore_pmdown_time = 1,
  6621. /* this dainlink has playback support */
  6622. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  6623. },
  6624. {
  6625. .name = MSM_DAILINK_NAME(Compress7),
  6626. .stream_name = "Compress7",
  6627. .cpu_dai_name = "MultiMedia14",
  6628. .platform_name = "msm-compress-dsp",
  6629. .dynamic = 1,
  6630. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6631. .dpcm_playback = 1,
  6632. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6633. SND_SOC_DPCM_TRIGGER_POST},
  6634. .codec_dai_name = "snd-soc-dummy-dai",
  6635. .codec_name = "snd-soc-dummy",
  6636. .ignore_suspend = 1,
  6637. .ignore_pmdown_time = 1,
  6638. /* this dainlink has playback support */
  6639. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  6640. },
  6641. {
  6642. .name = MSM_DAILINK_NAME(Compress8),
  6643. .stream_name = "Compress8",
  6644. .cpu_dai_name = "MultiMedia15",
  6645. .platform_name = "msm-compress-dsp",
  6646. .dynamic = 1,
  6647. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6648. .dpcm_playback = 1,
  6649. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6650. SND_SOC_DPCM_TRIGGER_POST},
  6651. .codec_dai_name = "snd-soc-dummy-dai",
  6652. .codec_name = "snd-soc-dummy",
  6653. .ignore_suspend = 1,
  6654. .ignore_pmdown_time = 1,
  6655. /* this dainlink has playback support */
  6656. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  6657. },
  6658. {
  6659. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  6660. .stream_name = "MM_NOIRQ_2",
  6661. .cpu_dai_name = "MultiMedia16",
  6662. .platform_name = "msm-pcm-dsp-noirq",
  6663. .dynamic = 1,
  6664. .dpcm_playback = 1,
  6665. .dpcm_capture = 1,
  6666. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6667. SND_SOC_DPCM_TRIGGER_POST},
  6668. .codec_dai_name = "snd-soc-dummy-dai",
  6669. .codec_name = "snd-soc-dummy",
  6670. .ignore_suspend = 1,
  6671. .ignore_pmdown_time = 1,
  6672. /* this dainlink has playback support */
  6673. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  6674. },
  6675. {
  6676. .name = "SLIMBUS_8 Hostless",
  6677. .stream_name = "SLIMBUS8_HOSTLESS Capture",
  6678. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  6679. .platform_name = "msm-pcm-hostless",
  6680. .dynamic = 1,
  6681. .dpcm_capture = 1,
  6682. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6683. SND_SOC_DPCM_TRIGGER_POST},
  6684. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6685. .ignore_suspend = 1,
  6686. .codec_dai_name = "snd-soc-dummy-dai",
  6687. .codec_name = "snd-soc-dummy",
  6688. },
  6689. /* Hostless PCM purpose */
  6690. {
  6691. .name = "CDC_DMA Hostless",
  6692. .stream_name = "CDC_DMA Hostless",
  6693. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  6694. .platform_name = "msm-pcm-hostless",
  6695. .dynamic = 1,
  6696. .dpcm_playback = 1,
  6697. .dpcm_capture = 1,
  6698. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6699. SND_SOC_DPCM_TRIGGER_POST},
  6700. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6701. .ignore_suspend = 1,
  6702. /* this dailink has playback support */
  6703. .ignore_pmdown_time = 1,
  6704. .codec_dai_name = "snd-soc-dummy-dai",
  6705. .codec_name = "snd-soc-dummy",
  6706. },
  6707. };
  6708. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  6709. {
  6710. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  6711. .stream_name = "WSA CDC DMA0 Capture",
  6712. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  6713. .platform_name = "msm-pcm-hostless",
  6714. .codec_name = "bolero_codec",
  6715. .codec_dai_name = "wsa_macro_vifeedback",
  6716. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  6717. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6718. .ignore_suspend = 1,
  6719. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6720. .ops = &msm_cdc_dma_be_ops,
  6721. },
  6722. };
  6723. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  6724. {
  6725. .name = MSM_DAILINK_NAME(ASM Loopback),
  6726. .stream_name = "MultiMedia6",
  6727. .cpu_dai_name = "MultiMedia6",
  6728. .platform_name = "msm-pcm-loopback",
  6729. .dynamic = 1,
  6730. .dpcm_playback = 1,
  6731. .dpcm_capture = 1,
  6732. .codec_dai_name = "snd-soc-dummy-dai",
  6733. .codec_name = "snd-soc-dummy",
  6734. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6735. SND_SOC_DPCM_TRIGGER_POST},
  6736. .ignore_suspend = 1,
  6737. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6738. .ignore_pmdown_time = 1,
  6739. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  6740. },
  6741. {
  6742. .name = "USB Audio Hostless",
  6743. .stream_name = "USB Audio Hostless",
  6744. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  6745. .platform_name = "msm-pcm-hostless",
  6746. .dynamic = 1,
  6747. .dpcm_playback = 1,
  6748. .dpcm_capture = 1,
  6749. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6750. SND_SOC_DPCM_TRIGGER_POST},
  6751. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6752. .ignore_suspend = 1,
  6753. .ignore_pmdown_time = 1,
  6754. .codec_dai_name = "snd-soc-dummy-dai",
  6755. .codec_name = "snd-soc-dummy",
  6756. },
  6757. {
  6758. .name = "SLIMBUS_7 Hostless",
  6759. .stream_name = "SLIMBUS_7 Hostless",
  6760. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  6761. .platform_name = "msm-pcm-hostless",
  6762. .dynamic = 1,
  6763. .dpcm_capture = 1,
  6764. .dpcm_playback = 1,
  6765. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6766. SND_SOC_DPCM_TRIGGER_POST},
  6767. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  6768. .ignore_suspend = 1,
  6769. .ignore_pmdown_time = 1,
  6770. .codec_dai_name = "snd-soc-dummy-dai",
  6771. .codec_name = "snd-soc-dummy",
  6772. },
  6773. {
  6774. .name = MSM_DAILINK_NAME(Compr Capture2),
  6775. .stream_name = "Compr Capture2",
  6776. .cpu_dai_name = "MultiMedia18",
  6777. .platform_name = "msm-compress-dsp",
  6778. .dynamic = 1,
  6779. .dpcm_capture = 1,
  6780. .codec_dai_name = "snd-soc-dummy-dai",
  6781. .codec_name = "snd-soc-dummy",
  6782. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6783. SND_SOC_DPCM_TRIGGER_POST},
  6784. .ignore_pmdown_time = 1,
  6785. .id = MSM_FRONTEND_DAI_MULTIMEDIA18,
  6786. },
  6787. {
  6788. .name = MSM_DAILINK_NAME(Transcode Loopback Playback),
  6789. .stream_name = "Transcode Loopback Playback",
  6790. .cpu_dai_name = "MultiMedia26",
  6791. .platform_name = "msm-transcode-loopback",
  6792. .dynamic = 1,
  6793. .dpcm_playback = 1,
  6794. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6795. SND_SOC_DPCM_TRIGGER_POST},
  6796. .codec_dai_name = "snd-soc-dummy-dai",
  6797. .codec_name = "snd-soc-dummy",
  6798. .ignore_suspend = 1,
  6799. .ignore_pmdown_time = 1,
  6800. /* this dailink has playback support */
  6801. .id = MSM_FRONTEND_DAI_MULTIMEDIA26,
  6802. },
  6803. {
  6804. .name = MSM_DAILINK_NAME(Transcode Loopback Capture),
  6805. .stream_name = "Transcode Loopback Capture",
  6806. .cpu_dai_name = "MultiMedia27",
  6807. .platform_name = "msm-transcode-loopback",
  6808. .dynamic = 1,
  6809. .dpcm_capture = 1,
  6810. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6811. SND_SOC_DPCM_TRIGGER_POST},
  6812. .codec_dai_name = "snd-soc-dummy-dai",
  6813. .codec_name = "snd-soc-dummy",
  6814. .ignore_suspend = 1,
  6815. .ignore_pmdown_time = 1,
  6816. .id = MSM_FRONTEND_DAI_MULTIMEDIA27,
  6817. },
  6818. {
  6819. .name = MSM_DAILINK_NAME(Compr Capture3),
  6820. .stream_name = "Compr Capture3",
  6821. .cpu_dai_name = "MultiMedia19",
  6822. .platform_name = "msm-compress-dsp",
  6823. .dynamic = 1,
  6824. .dpcm_capture = 1,
  6825. .codec_dai_name = "snd-soc-dummy-dai",
  6826. .codec_name = "snd-soc-dummy",
  6827. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6828. SND_SOC_DPCM_TRIGGER_POST},
  6829. .ignore_pmdown_time = 1,
  6830. .id = MSM_FRONTEND_DAI_MULTIMEDIA19,
  6831. },
  6832. {
  6833. .name = MSM_DAILINK_NAME(Compr Capture4),
  6834. .stream_name = "Compr Capture4",
  6835. .cpu_dai_name = "MultiMedia28",
  6836. .platform_name = "msm-compress-dsp",
  6837. .dynamic = 1,
  6838. .dpcm_capture = 1,
  6839. .codec_dai_name = "snd-soc-dummy-dai",
  6840. .codec_name = "snd-soc-dummy",
  6841. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6842. SND_SOC_DPCM_TRIGGER_POST},
  6843. .ignore_pmdown_time = 1,
  6844. .id = MSM_FRONTEND_DAI_MULTIMEDIA28,
  6845. },
  6846. {
  6847. .name = MSM_DAILINK_NAME(Compr Capture5),
  6848. .stream_name = "Compr Capture5",
  6849. .cpu_dai_name = "MultiMedia29",
  6850. .platform_name = "msm-compress-dsp",
  6851. .dynamic = 1,
  6852. .dpcm_capture = 1,
  6853. .codec_dai_name = "snd-soc-dummy-dai",
  6854. .codec_name = "snd-soc-dummy",
  6855. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6856. SND_SOC_DPCM_TRIGGER_POST},
  6857. .ignore_pmdown_time = 1,
  6858. .id = MSM_FRONTEND_DAI_MULTIMEDIA29,
  6859. },
  6860. {
  6861. .name = MSM_DAILINK_NAME(Compr Capture6),
  6862. .stream_name = "Compr Capture6",
  6863. .cpu_dai_name = "MultiMedia30",
  6864. .platform_name = "msm-compress-dsp",
  6865. .dynamic = 1,
  6866. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  6867. .dpcm_capture = 1,
  6868. .codec_dai_name = "snd-soc-dummy-dai",
  6869. .codec_name = "snd-soc-dummy",
  6870. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6871. SND_SOC_DPCM_TRIGGER_POST},
  6872. .ignore_pmdown_time = 1,
  6873. .id = MSM_FRONTEND_DAI_MULTIMEDIA30,
  6874. },
  6875. };
  6876. static struct snd_soc_dai_link ext_hdmi_be_dai_link[] = {
  6877. /* HDMI RX BACK END DAI Link */
  6878. {
  6879. .name = LPASS_BE_HDMI_MS,
  6880. .stream_name = "HDMI MS Playback",
  6881. .cpu_dai_name = "msm-dai-q6-hdmi.24578",
  6882. .platform_name = "msm-pcm-routing",
  6883. .codec_name = "msm-ext-disp-audio-codec-rx",
  6884. .codec_dai_name = "msm_hdmi_ms_audio_codec_rx_dai",
  6885. .no_pcm = 1,
  6886. .dpcm_playback = 1,
  6887. .id = MSM_BACKEND_DAI_HDMI_RX_MS,
  6888. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6889. .ignore_pmdown_time = 1,
  6890. .ignore_suspend = 1,
  6891. },
  6892. };
  6893. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  6894. /* Backend AFE DAI Links */
  6895. {
  6896. .name = LPASS_BE_AFE_PCM_RX,
  6897. .stream_name = "AFE Playback",
  6898. .cpu_dai_name = "msm-dai-q6-dev.224",
  6899. .platform_name = "msm-pcm-routing",
  6900. .codec_name = "msm-stub-codec.1",
  6901. .codec_dai_name = "msm-stub-rx",
  6902. .no_pcm = 1,
  6903. .dpcm_playback = 1,
  6904. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  6905. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6906. /* this dainlink has playback support */
  6907. .ignore_pmdown_time = 1,
  6908. .ignore_suspend = 1,
  6909. },
  6910. {
  6911. .name = LPASS_BE_AFE_PCM_TX,
  6912. .stream_name = "AFE Capture",
  6913. .cpu_dai_name = "msm-dai-q6-dev.225",
  6914. .platform_name = "msm-pcm-routing",
  6915. .codec_name = "msm-stub-codec.1",
  6916. .codec_dai_name = "msm-stub-tx",
  6917. .no_pcm = 1,
  6918. .dpcm_capture = 1,
  6919. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  6920. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6921. .ignore_suspend = 1,
  6922. },
  6923. /* Incall Record Uplink BACK END DAI Link */
  6924. {
  6925. .name = LPASS_BE_INCALL_RECORD_TX,
  6926. .stream_name = "Voice Uplink Capture",
  6927. .cpu_dai_name = "msm-dai-q6-dev.32772",
  6928. .platform_name = "msm-pcm-routing",
  6929. .codec_name = "msm-stub-codec.1",
  6930. .codec_dai_name = "msm-stub-tx",
  6931. .no_pcm = 1,
  6932. .dpcm_capture = 1,
  6933. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  6934. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6935. .ignore_suspend = 1,
  6936. },
  6937. /* Incall Record Downlink BACK END DAI Link */
  6938. {
  6939. .name = LPASS_BE_INCALL_RECORD_RX,
  6940. .stream_name = "Voice Downlink Capture",
  6941. .cpu_dai_name = "msm-dai-q6-dev.32771",
  6942. .platform_name = "msm-pcm-routing",
  6943. .codec_name = "msm-stub-codec.1",
  6944. .codec_dai_name = "msm-stub-tx",
  6945. .no_pcm = 1,
  6946. .dpcm_capture = 1,
  6947. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  6948. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6949. .ignore_suspend = 1,
  6950. },
  6951. /* Incall Music BACK END DAI Link */
  6952. {
  6953. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  6954. .stream_name = "Voice Farend Playback",
  6955. .cpu_dai_name = "msm-dai-q6-dev.32773",
  6956. .platform_name = "msm-pcm-routing",
  6957. .codec_name = "msm-stub-codec.1",
  6958. .codec_dai_name = "msm-stub-rx",
  6959. .no_pcm = 1,
  6960. .dpcm_playback = 1,
  6961. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  6962. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6963. .ignore_suspend = 1,
  6964. .ignore_pmdown_time = 1,
  6965. },
  6966. /* Incall Music 2 BACK END DAI Link */
  6967. {
  6968. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  6969. .stream_name = "Voice2 Farend Playback",
  6970. .cpu_dai_name = "msm-dai-q6-dev.32770",
  6971. .platform_name = "msm-pcm-routing",
  6972. .codec_name = "msm-stub-codec.1",
  6973. .codec_dai_name = "msm-stub-rx",
  6974. .no_pcm = 1,
  6975. .dpcm_playback = 1,
  6976. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  6977. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6978. .ignore_suspend = 1,
  6979. .ignore_pmdown_time = 1,
  6980. },
  6981. {
  6982. .name = LPASS_BE_USB_AUDIO_RX,
  6983. .stream_name = "USB Audio Playback",
  6984. .cpu_dai_name = "msm-dai-q6-dev.28672",
  6985. .platform_name = "msm-pcm-routing",
  6986. .codec_name = "msm-stub-codec.1",
  6987. .codec_dai_name = "msm-stub-rx",
  6988. .no_pcm = 1,
  6989. .dpcm_playback = 1,
  6990. .id = MSM_BACKEND_DAI_USB_RX,
  6991. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6992. .ignore_pmdown_time = 1,
  6993. .ignore_suspend = 1,
  6994. },
  6995. {
  6996. .name = LPASS_BE_USB_AUDIO_TX,
  6997. .stream_name = "USB Audio Capture",
  6998. .cpu_dai_name = "msm-dai-q6-dev.28673",
  6999. .platform_name = "msm-pcm-routing",
  7000. .codec_name = "msm-stub-codec.1",
  7001. .codec_dai_name = "msm-stub-tx",
  7002. .no_pcm = 1,
  7003. .dpcm_capture = 1,
  7004. .id = MSM_BACKEND_DAI_USB_TX,
  7005. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7006. .ignore_suspend = 1,
  7007. },
  7008. {
  7009. .name = LPASS_BE_PRI_TDM_RX_0,
  7010. .stream_name = "Primary TDM0 Playback",
  7011. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  7012. .platform_name = "msm-pcm-routing",
  7013. .codec_name = "msm-stub-codec.1",
  7014. .codec_dai_name = "msm-stub-rx",
  7015. .no_pcm = 1,
  7016. .dpcm_playback = 1,
  7017. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  7018. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7019. .ops = &qcs405_tdm_be_ops,
  7020. .ignore_suspend = 1,
  7021. .ignore_pmdown_time = 1,
  7022. },
  7023. {
  7024. .name = LPASS_BE_PRI_TDM_TX_0,
  7025. .stream_name = "Primary TDM0 Capture",
  7026. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  7027. .platform_name = "msm-pcm-routing",
  7028. .codec_name = "msm-stub-codec.1",
  7029. .codec_dai_name = "msm-stub-tx",
  7030. .no_pcm = 1,
  7031. .dpcm_capture = 1,
  7032. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  7033. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7034. .ops = &qcs405_tdm_be_ops,
  7035. .ignore_suspend = 1,
  7036. },
  7037. {
  7038. .name = LPASS_BE_SEC_TDM_RX_0,
  7039. .stream_name = "Secondary TDM0 Playback",
  7040. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  7041. .platform_name = "msm-pcm-routing",
  7042. .codec_name = "msm-stub-codec.1",
  7043. .codec_dai_name = "msm-stub-rx",
  7044. .no_pcm = 1,
  7045. .dpcm_playback = 1,
  7046. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  7047. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7048. .ops = &qcs405_tdm_be_ops,
  7049. .ignore_suspend = 1,
  7050. .ignore_pmdown_time = 1,
  7051. },
  7052. {
  7053. .name = LPASS_BE_SEC_TDM_TX_0,
  7054. .stream_name = "Secondary TDM0 Capture",
  7055. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  7056. .platform_name = "msm-pcm-routing",
  7057. .codec_name = "msm-stub-codec.1",
  7058. .codec_dai_name = "msm-stub-tx",
  7059. .no_pcm = 1,
  7060. .dpcm_capture = 1,
  7061. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  7062. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7063. .ops = &qcs405_tdm_be_ops,
  7064. .ignore_suspend = 1,
  7065. },
  7066. {
  7067. .name = LPASS_BE_TERT_TDM_RX_0,
  7068. .stream_name = "Tertiary TDM0 Playback",
  7069. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  7070. .platform_name = "msm-pcm-routing",
  7071. .codec_name = "msm-stub-codec.1",
  7072. .codec_dai_name = "msm-stub-rx",
  7073. .no_pcm = 1,
  7074. .dpcm_playback = 1,
  7075. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  7076. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7077. .ops = &qcs405_tdm_be_ops,
  7078. .ignore_suspend = 1,
  7079. .ignore_pmdown_time = 1,
  7080. },
  7081. {
  7082. .name = LPASS_BE_TERT_TDM_TX_0,
  7083. .stream_name = "Tertiary TDM0 Capture",
  7084. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  7085. .platform_name = "msm-pcm-routing",
  7086. .codec_name = "msm-stub-codec.1",
  7087. .codec_dai_name = "msm-stub-tx",
  7088. .no_pcm = 1,
  7089. .dpcm_capture = 1,
  7090. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  7091. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7092. .ops = &qcs405_tdm_be_ops,
  7093. .ignore_suspend = 1,
  7094. },
  7095. {
  7096. .name = LPASS_BE_QUAT_TDM_RX_0,
  7097. .stream_name = "Quaternary TDM0 Playback",
  7098. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  7099. .platform_name = "msm-pcm-routing",
  7100. .codec_name = "msm-stub-codec.1",
  7101. .codec_dai_name = "msm-stub-rx",
  7102. .no_pcm = 1,
  7103. .dpcm_playback = 1,
  7104. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  7105. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  7106. .ops = &qcs405_tdm_be_ops,
  7107. .ignore_suspend = 1,
  7108. .ignore_pmdown_time = 1,
  7109. },
  7110. {
  7111. .name = LPASS_BE_QUAT_TDM_TX_0,
  7112. .stream_name = "Quaternary TDM0 Capture",
  7113. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  7114. .platform_name = "msm-pcm-routing",
  7115. .codec_name = "msm-stub-codec.1",
  7116. .codec_dai_name = "msm-stub-tx",
  7117. .no_pcm = 1,
  7118. .dpcm_capture = 1,
  7119. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  7120. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7121. .ops = &qcs405_tdm_be_ops,
  7122. .ignore_suspend = 1,
  7123. },
  7124. {
  7125. .name = LPASS_BE_QUIN_TDM_RX_0,
  7126. .stream_name = "Quinary TDM0 Playback",
  7127. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  7128. .platform_name = "msm-pcm-routing",
  7129. .codec_name = "msm-stub-codec.1",
  7130. .codec_dai_name = "msm-stub-rx",
  7131. .no_pcm = 1,
  7132. .dpcm_playback = 1,
  7133. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  7134. .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
  7135. .ops = &qcs405_tdm_be_ops,
  7136. .ignore_suspend = 1,
  7137. .ignore_pmdown_time = 1,
  7138. },
  7139. {
  7140. .name = LPASS_BE_QUIN_TDM_TX_0,
  7141. .stream_name = "Quinary TDM0 Capture",
  7142. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  7143. .platform_name = "msm-pcm-routing",
  7144. .codec_name = "msm-stub-codec.1",
  7145. .codec_dai_name = "msm-stub-tx",
  7146. .no_pcm = 1,
  7147. .dpcm_capture = 1,
  7148. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  7149. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7150. .ops = &qcs405_tdm_be_ops,
  7151. .ignore_suspend = 1,
  7152. },
  7153. };
  7154. static struct snd_soc_dai_link msm_tasha_be_dai_links[] = {
  7155. {
  7156. .name = LPASS_BE_SLIMBUS_0_RX,
  7157. .stream_name = "Slimbus Playback",
  7158. .cpu_dai_name = "msm-dai-q6-dev.16384",
  7159. .platform_name = "msm-pcm-routing",
  7160. .codec_name = "tasha_codec",
  7161. .codec_dai_name = "tasha_mix_rx1",
  7162. .no_pcm = 1,
  7163. .dpcm_playback = 1,
  7164. .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
  7165. .init = &msm_audrx_init,
  7166. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7167. /* this dainlink has playback support */
  7168. .ignore_pmdown_time = 1,
  7169. .ignore_suspend = 1,
  7170. .ops = &msm_be_ops,
  7171. },
  7172. {
  7173. .name = LPASS_BE_SLIMBUS_0_TX,
  7174. .stream_name = "Slimbus Capture",
  7175. .cpu_dai_name = "msm-dai-q6-dev.16385",
  7176. .platform_name = "msm-pcm-routing",
  7177. .codec_name = "tasha_codec",
  7178. .codec_dai_name = "tasha_tx1",
  7179. .no_pcm = 1,
  7180. .dpcm_capture = 1,
  7181. .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
  7182. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7183. .ignore_suspend = 1,
  7184. .ops = &msm_be_ops,
  7185. },
  7186. {
  7187. .name = LPASS_BE_SLIMBUS_1_RX,
  7188. .stream_name = "Slimbus1 Playback",
  7189. .cpu_dai_name = "msm-dai-q6-dev.16386",
  7190. .platform_name = "msm-pcm-routing",
  7191. .codec_name = "tasha_codec",
  7192. .codec_dai_name = "tasha_mix_rx1",
  7193. .no_pcm = 1,
  7194. .dpcm_playback = 1,
  7195. .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
  7196. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7197. .ops = &msm_be_ops,
  7198. /* dai link has playback support */
  7199. .ignore_pmdown_time = 1,
  7200. .ignore_suspend = 1,
  7201. },
  7202. {
  7203. .name = LPASS_BE_SLIMBUS_1_TX,
  7204. .stream_name = "Slimbus1 Capture",
  7205. .cpu_dai_name = "msm-dai-q6-dev.16387",
  7206. .platform_name = "msm-pcm-routing",
  7207. .codec_name = "tasha_codec",
  7208. .codec_dai_name = "tasha_tx3",
  7209. .no_pcm = 1,
  7210. .dpcm_capture = 1,
  7211. .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
  7212. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7213. .ops = &msm_be_ops,
  7214. .ignore_suspend = 1,
  7215. },
  7216. {
  7217. .name = LPASS_BE_SLIMBUS_2_RX,
  7218. .stream_name = "Slimbus2 Playback",
  7219. .cpu_dai_name = "msm-dai-q6-dev.16388",
  7220. .platform_name = "msm-pcm-routing",
  7221. .codec_name = "tasha_codec",
  7222. .codec_dai_name = "tasha_rx2",
  7223. .no_pcm = 1,
  7224. .dpcm_playback = 1,
  7225. .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
  7226. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7227. .ops = &msm_be_ops,
  7228. .ignore_pmdown_time = 1,
  7229. .ignore_suspend = 1,
  7230. },
  7231. {
  7232. .name = LPASS_BE_SLIMBUS_3_RX,
  7233. .stream_name = "Slimbus3 Playback",
  7234. .cpu_dai_name = "msm-dai-q6-dev.16390",
  7235. .platform_name = "msm-pcm-routing",
  7236. .codec_name = "tasha_codec",
  7237. .codec_dai_name = "tasha_mix_rx1",
  7238. .no_pcm = 1,
  7239. .dpcm_playback = 1,
  7240. .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
  7241. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7242. .ops = &msm_be_ops,
  7243. /* dai link has playback support */
  7244. .ignore_pmdown_time = 1,
  7245. .ignore_suspend = 1,
  7246. },
  7247. {
  7248. .name = LPASS_BE_SLIMBUS_3_TX,
  7249. .stream_name = "Slimbus3 Capture",
  7250. .cpu_dai_name = "msm-dai-q6-dev.16391",
  7251. .platform_name = "msm-pcm-routing",
  7252. .codec_name = "tasha_codec",
  7253. .codec_dai_name = "tasha_tx1",
  7254. .no_pcm = 1,
  7255. .dpcm_capture = 1,
  7256. .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
  7257. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7258. .ops = &msm_be_ops,
  7259. .ignore_suspend = 1,
  7260. },
  7261. {
  7262. .name = LPASS_BE_SLIMBUS_4_RX,
  7263. .stream_name = "Slimbus4 Playback",
  7264. .cpu_dai_name = "msm-dai-q6-dev.16392",
  7265. .platform_name = "msm-pcm-routing",
  7266. .codec_name = "tasha_codec",
  7267. .codec_dai_name = "tasha_mix_rx1",
  7268. .no_pcm = 1,
  7269. .dpcm_playback = 1,
  7270. .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
  7271. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7272. .ops = &msm_be_ops,
  7273. /* dai link has playback support */
  7274. .ignore_pmdown_time = 1,
  7275. .ignore_suspend = 1,
  7276. },
  7277. {
  7278. .name = LPASS_BE_SLIMBUS_5_RX,
  7279. .stream_name = "Slimbus5 Playback",
  7280. .cpu_dai_name = "msm-dai-q6-dev.16394",
  7281. .platform_name = "msm-pcm-routing",
  7282. .codec_name = "tasha_codec",
  7283. .codec_dai_name = "tasha_rx3",
  7284. .no_pcm = 1,
  7285. .dpcm_playback = 1,
  7286. .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
  7287. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7288. .ops = &msm_be_ops,
  7289. /* dai link has playback support */
  7290. .ignore_pmdown_time = 1,
  7291. .ignore_suspend = 1,
  7292. },
  7293. {
  7294. .name = LPASS_BE_SLIMBUS_6_RX,
  7295. .stream_name = "Slimbus6 Playback",
  7296. .cpu_dai_name = "msm-dai-q6-dev.16396",
  7297. .platform_name = "msm-pcm-routing",
  7298. .codec_name = "tasha_codec",
  7299. .codec_dai_name = "tasha_rx4",
  7300. .no_pcm = 1,
  7301. .dpcm_playback = 1,
  7302. .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
  7303. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7304. .ops = &msm_be_ops,
  7305. /* dai link has playback support */
  7306. .ignore_pmdown_time = 1,
  7307. .ignore_suspend = 1,
  7308. },
  7309. /* Slimbus VI Recording */
  7310. {
  7311. .name = LPASS_BE_SLIMBUS_TX_VI,
  7312. .stream_name = "Slimbus4 Capture",
  7313. .cpu_dai_name = "msm-dai-q6-dev.16393",
  7314. .platform_name = "msm-pcm-routing",
  7315. .codec_name = "tasha_codec",
  7316. .codec_dai_name = "tasha_vifeedback",
  7317. .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
  7318. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7319. .ops = &msm_be_ops,
  7320. .ignore_suspend = 1,
  7321. .no_pcm = 1,
  7322. .dpcm_capture = 1,
  7323. .ignore_pmdown_time = 1,
  7324. },
  7325. };
  7326. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  7327. {
  7328. .name = LPASS_BE_SLIMBUS_7_RX,
  7329. .stream_name = "Slimbus7 Playback",
  7330. .cpu_dai_name = "msm-dai-q6-dev.16398",
  7331. .platform_name = "msm-pcm-routing",
  7332. .codec_name = "btfmslim_slave",
  7333. /* BT codec driver determines capabilities based on
  7334. * dai name, bt codecdai name should always contains
  7335. * supported usecase information
  7336. */
  7337. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  7338. .no_pcm = 1,
  7339. .dpcm_playback = 1,
  7340. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  7341. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7342. .ops = &msm_wcn_ops,
  7343. /* dai link has playback support */
  7344. .ignore_pmdown_time = 1,
  7345. .ignore_suspend = 1,
  7346. },
  7347. {
  7348. .name = LPASS_BE_SLIMBUS_7_TX,
  7349. .stream_name = "Slimbus7 Capture",
  7350. .cpu_dai_name = "msm-dai-q6-dev.16399",
  7351. .platform_name = "msm-pcm-routing",
  7352. .codec_name = "btfmslim_slave",
  7353. .codec_dai_name = "btfm_bt_sco_slim_tx",
  7354. .no_pcm = 1,
  7355. .dpcm_capture = 1,
  7356. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  7357. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7358. .ops = &msm_wcn_ops,
  7359. .ignore_suspend = 1,
  7360. },
  7361. {
  7362. .name = LPASS_BE_SLIMBUS_8_TX,
  7363. .stream_name = "Slimbus8 Capture",
  7364. .cpu_dai_name = "msm-dai-q6-dev.16401",
  7365. .platform_name = "msm-pcm-routing",
  7366. .codec_name = "btfmslim_slave",
  7367. .codec_dai_name = "btfm_fm_slim_tx",
  7368. .no_pcm = 1,
  7369. .dpcm_capture = 1,
  7370. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  7371. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7372. .init = &msm_wcn_init,
  7373. .ops = &msm_wcn_ops,
  7374. .ignore_suspend = 1,
  7375. },
  7376. {
  7377. .name = LPASS_BE_SLIMBUS_9_TX,
  7378. .stream_name = "Slimbus9 Capture",
  7379. .cpu_dai_name = "msm-dai-q6-dev.16403",
  7380. .platform_name = "msm-pcm-routing",
  7381. .codec_name = "btfmslim_slave",
  7382. .codec_dai_name = "btfm_bt_split_a2dp_slim_tx",
  7383. .no_pcm = 1,
  7384. .dpcm_capture = 1,
  7385. .id = MSM_BACKEND_DAI_SLIMBUS_9_TX,
  7386. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7387. .ops = &msm_wcn_ops,
  7388. .ignore_suspend = 1,
  7389. },
  7390. };
  7391. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  7392. {
  7393. .name = LPASS_BE_PRI_MI2S_RX,
  7394. .stream_name = "Primary MI2S Playback",
  7395. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  7396. .platform_name = "msm-pcm-routing",
  7397. .codec_name = "msm-stub-codec.1",
  7398. .codec_dai_name = "msm-stub-rx",
  7399. .no_pcm = 1,
  7400. .dpcm_playback = 1,
  7401. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  7402. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7403. .ops = &msm_mi2s_be_ops,
  7404. .ignore_suspend = 1,
  7405. .ignore_pmdown_time = 1,
  7406. },
  7407. {
  7408. .name = LPASS_BE_PRI_MI2S_TX,
  7409. .stream_name = "Primary MI2S Capture",
  7410. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  7411. .platform_name = "msm-pcm-routing",
  7412. .codec_name = "msm-stub-codec.1",
  7413. .codec_dai_name = "msm-stub-tx",
  7414. .no_pcm = 1,
  7415. .dpcm_capture = 1,
  7416. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  7417. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7418. .ops = &msm_mi2s_be_ops,
  7419. .ignore_suspend = 1,
  7420. },
  7421. {
  7422. .name = LPASS_BE_SEC_MI2S_RX,
  7423. .stream_name = "Secondary MI2S Playback",
  7424. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  7425. .platform_name = "msm-pcm-routing",
  7426. .codec_name = "msm-stub-codec.1",
  7427. .codec_dai_name = "msm-stub-rx",
  7428. .no_pcm = 1,
  7429. .dpcm_playback = 1,
  7430. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  7431. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7432. .ops = &msm_mi2s_be_ops,
  7433. .ignore_suspend = 1,
  7434. .ignore_pmdown_time = 1,
  7435. },
  7436. {
  7437. .name = LPASS_BE_SEC_MI2S_TX,
  7438. .stream_name = "Secondary MI2S Capture",
  7439. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  7440. .platform_name = "msm-pcm-routing",
  7441. .codec_name = "msm-stub-codec.1",
  7442. .codec_dai_name = "msm-stub-tx",
  7443. .no_pcm = 1,
  7444. .dpcm_capture = 1,
  7445. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  7446. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7447. .ops = &msm_mi2s_be_ops,
  7448. .ignore_suspend = 1,
  7449. },
  7450. {
  7451. .name = LPASS_BE_TERT_MI2S_RX,
  7452. .stream_name = "Tertiary MI2S Playback",
  7453. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  7454. .platform_name = "msm-pcm-routing",
  7455. .codec_name = "msm-stub-codec.1",
  7456. .codec_dai_name = "msm-stub-rx",
  7457. .no_pcm = 1,
  7458. .dpcm_playback = 1,
  7459. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  7460. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7461. .ops = &msm_mi2s_be_ops,
  7462. .ignore_suspend = 1,
  7463. .ignore_pmdown_time = 1,
  7464. },
  7465. {
  7466. .name = LPASS_BE_TERT_MI2S_TX,
  7467. .stream_name = "Tertiary MI2S Capture",
  7468. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  7469. .platform_name = "msm-pcm-routing",
  7470. .codec_name = "msm-stub-codec.1",
  7471. .codec_dai_name = "msm-stub-tx",
  7472. .no_pcm = 1,
  7473. .dpcm_capture = 1,
  7474. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  7475. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7476. .ops = &msm_mi2s_be_ops,
  7477. .ignore_suspend = 1,
  7478. },
  7479. {
  7480. .name = LPASS_BE_QUAT_MI2S_RX,
  7481. .stream_name = "Quaternary MI2S Playback",
  7482. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  7483. .platform_name = "msm-pcm-routing",
  7484. .codec_name = "msm-stub-codec.1",
  7485. .codec_dai_name = "msm-stub-rx",
  7486. .no_pcm = 1,
  7487. .dpcm_playback = 1,
  7488. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  7489. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7490. .ops = &msm_mi2s_be_ops,
  7491. .ignore_suspend = 1,
  7492. .ignore_pmdown_time = 1,
  7493. },
  7494. {
  7495. .name = LPASS_BE_QUAT_MI2S_TX,
  7496. .stream_name = "Quaternary MI2S Capture",
  7497. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  7498. .platform_name = "msm-pcm-routing",
  7499. .codec_name = "msm-stub-codec.1",
  7500. .codec_dai_name = "msm-stub-tx",
  7501. .no_pcm = 1,
  7502. .dpcm_capture = 1,
  7503. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  7504. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7505. .ops = &msm_mi2s_be_ops,
  7506. .ignore_suspend = 1,
  7507. },
  7508. {
  7509. .name = LPASS_BE_QUIN_MI2S_RX,
  7510. .stream_name = "Quinary MI2S Playback",
  7511. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  7512. .platform_name = "msm-pcm-routing",
  7513. .codec_name = "msm-stub-codec.1",
  7514. .codec_dai_name = "msm-stub-rx",
  7515. .no_pcm = 1,
  7516. .dpcm_playback = 1,
  7517. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  7518. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7519. .ops = &msm_mi2s_be_ops,
  7520. .ignore_suspend = 1,
  7521. .ignore_pmdown_time = 1,
  7522. },
  7523. {
  7524. .name = LPASS_BE_QUIN_MI2S_TX,
  7525. .stream_name = "Quinary MI2S Capture",
  7526. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  7527. .platform_name = "msm-pcm-routing",
  7528. .codec_name = "msm-stub-codec.1",
  7529. .codec_dai_name = "msm-stub-tx",
  7530. .no_pcm = 1,
  7531. .dpcm_capture = 1,
  7532. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  7533. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7534. .ops = &msm_mi2s_be_ops,
  7535. .ignore_suspend = 1,
  7536. },
  7537. };
  7538. static struct snd_soc_dai_link msm_meta_mi2s_be_dai_links[] = {
  7539. {
  7540. .name = LPASS_BE_PRI_META_MI2S_RX,
  7541. .stream_name = "Primary META MI2S Playback",
  7542. .cpu_dai_name = "msm-dai-q6-meta-mi2s.4864",
  7543. .platform_name = "msm-pcm-routing",
  7544. .codec_name = "msm-stub-codec.1",
  7545. .codec_dai_name = "msm-stub-rx",
  7546. .no_pcm = 1,
  7547. .dpcm_playback = 1,
  7548. .id = MSM_BACKEND_DAI_PRI_META_MI2S_RX,
  7549. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7550. .ops = &msm_meta_mi2s_be_ops,
  7551. .ignore_suspend = 1,
  7552. .ignore_pmdown_time = 1,
  7553. },
  7554. {
  7555. .name = LPASS_BE_SEC_META_MI2S_RX,
  7556. .stream_name = "Secondary META MI2S Playback",
  7557. .cpu_dai_name = "msm-dai-q6-meta-mi2s.4866",
  7558. .platform_name = "msm-pcm-routing",
  7559. .codec_name = "msm-stub-codec.1",
  7560. .codec_dai_name = "msm-stub-rx",
  7561. .no_pcm = 1,
  7562. .dpcm_playback = 1,
  7563. .id = MSM_BACKEND_DAI_SEC_META_MI2S_RX,
  7564. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7565. .ops = &msm_meta_mi2s_be_ops,
  7566. .ignore_suspend = 1,
  7567. .ignore_pmdown_time = 1,
  7568. },
  7569. };
  7570. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  7571. /* Primary AUX PCM Backend DAI Links */
  7572. {
  7573. .name = LPASS_BE_AUXPCM_RX,
  7574. .stream_name = "AUX PCM Playback",
  7575. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  7576. .platform_name = "msm-pcm-routing",
  7577. .codec_name = "msm-stub-codec.1",
  7578. .codec_dai_name = "msm-stub-rx",
  7579. .no_pcm = 1,
  7580. .dpcm_playback = 1,
  7581. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  7582. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7583. .ops = &msm_auxpcm_be_ops,
  7584. .ignore_pmdown_time = 1,
  7585. .ignore_suspend = 1,
  7586. },
  7587. {
  7588. .name = LPASS_BE_AUXPCM_TX,
  7589. .stream_name = "AUX PCM Capture",
  7590. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  7591. .platform_name = "msm-pcm-routing",
  7592. .codec_name = "msm-stub-codec.1",
  7593. .codec_dai_name = "msm-stub-tx",
  7594. .no_pcm = 1,
  7595. .dpcm_capture = 1,
  7596. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  7597. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7598. .ops = &msm_auxpcm_be_ops,
  7599. .ignore_suspend = 1,
  7600. },
  7601. /* Secondary AUX PCM Backend DAI Links */
  7602. {
  7603. .name = LPASS_BE_SEC_AUXPCM_RX,
  7604. .stream_name = "Sec AUX PCM Playback",
  7605. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  7606. .platform_name = "msm-pcm-routing",
  7607. .codec_name = "msm-stub-codec.1",
  7608. .codec_dai_name = "msm-stub-rx",
  7609. .no_pcm = 1,
  7610. .dpcm_playback = 1,
  7611. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  7612. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7613. .ops = &msm_auxpcm_be_ops,
  7614. .ignore_pmdown_time = 1,
  7615. .ignore_suspend = 1,
  7616. },
  7617. {
  7618. .name = LPASS_BE_SEC_AUXPCM_TX,
  7619. .stream_name = "Sec AUX PCM Capture",
  7620. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  7621. .platform_name = "msm-pcm-routing",
  7622. .codec_name = "msm-stub-codec.1",
  7623. .codec_dai_name = "msm-stub-tx",
  7624. .no_pcm = 1,
  7625. .dpcm_capture = 1,
  7626. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  7627. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7628. .ops = &msm_auxpcm_be_ops,
  7629. .ignore_suspend = 1,
  7630. },
  7631. /* Tertiary AUX PCM Backend DAI Links */
  7632. {
  7633. .name = LPASS_BE_TERT_AUXPCM_RX,
  7634. .stream_name = "Tert AUX PCM Playback",
  7635. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  7636. .platform_name = "msm-pcm-routing",
  7637. .codec_name = "msm-stub-codec.1",
  7638. .codec_dai_name = "msm-stub-rx",
  7639. .no_pcm = 1,
  7640. .dpcm_playback = 1,
  7641. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  7642. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7643. .ops = &msm_auxpcm_be_ops,
  7644. .ignore_suspend = 1,
  7645. },
  7646. {
  7647. .name = LPASS_BE_TERT_AUXPCM_TX,
  7648. .stream_name = "Tert AUX PCM Capture",
  7649. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  7650. .platform_name = "msm-pcm-routing",
  7651. .codec_name = "msm-stub-codec.1",
  7652. .codec_dai_name = "msm-stub-tx",
  7653. .no_pcm = 1,
  7654. .dpcm_capture = 1,
  7655. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  7656. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7657. .ops = &msm_auxpcm_be_ops,
  7658. .ignore_suspend = 1,
  7659. },
  7660. /* Quaternary AUX PCM Backend DAI Links */
  7661. {
  7662. .name = LPASS_BE_QUAT_AUXPCM_RX,
  7663. .stream_name = "Quat AUX PCM Playback",
  7664. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  7665. .platform_name = "msm-pcm-routing",
  7666. .codec_name = "msm-stub-codec.1",
  7667. .codec_dai_name = "msm-stub-rx",
  7668. .no_pcm = 1,
  7669. .dpcm_playback = 1,
  7670. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  7671. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7672. .ops = &msm_auxpcm_be_ops,
  7673. .ignore_pmdown_time = 1,
  7674. .ignore_suspend = 1,
  7675. },
  7676. {
  7677. .name = LPASS_BE_QUAT_AUXPCM_TX,
  7678. .stream_name = "Quat AUX PCM Capture",
  7679. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  7680. .platform_name = "msm-pcm-routing",
  7681. .codec_name = "msm-stub-codec.1",
  7682. .codec_dai_name = "msm-stub-tx",
  7683. .no_pcm = 1,
  7684. .dpcm_capture = 1,
  7685. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  7686. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7687. .ops = &msm_auxpcm_be_ops,
  7688. .ignore_suspend = 1,
  7689. },
  7690. /* Quinary AUX PCM Backend DAI Links */
  7691. {
  7692. .name = LPASS_BE_QUIN_AUXPCM_RX,
  7693. .stream_name = "Quin AUX PCM Playback",
  7694. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  7695. .platform_name = "msm-pcm-routing",
  7696. .codec_name = "msm-stub-codec.1",
  7697. .codec_dai_name = "msm-stub-rx",
  7698. .no_pcm = 1,
  7699. .dpcm_playback = 1,
  7700. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  7701. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7702. .ops = &msm_auxpcm_be_ops,
  7703. .ignore_pmdown_time = 1,
  7704. .ignore_suspend = 1,
  7705. },
  7706. {
  7707. .name = LPASS_BE_QUIN_AUXPCM_TX,
  7708. .stream_name = "Quin AUX PCM Capture",
  7709. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  7710. .platform_name = "msm-pcm-routing",
  7711. .codec_name = "msm-stub-codec.1",
  7712. .codec_dai_name = "msm-stub-tx",
  7713. .no_pcm = 1,
  7714. .dpcm_capture = 1,
  7715. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  7716. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7717. .ops = &msm_auxpcm_be_ops,
  7718. .ignore_suspend = 1,
  7719. },
  7720. };
  7721. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  7722. /* WSA CDC DMA Backend DAI Links */
  7723. {
  7724. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  7725. .stream_name = "WSA CDC DMA0 Playback",
  7726. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  7727. .platform_name = "msm-pcm-routing",
  7728. .codec_name = "bolero_codec",
  7729. .codec_dai_name = "wsa_macro_rx1",
  7730. .no_pcm = 1,
  7731. .dpcm_playback = 1,
  7732. .init = &msm_wsa_cdc_dma_init,
  7733. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  7734. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7735. .ignore_pmdown_time = 1,
  7736. .ignore_suspend = 1,
  7737. .ops = &msm_cdc_dma_be_ops,
  7738. },
  7739. {
  7740. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  7741. .stream_name = "WSA CDC DMA1 Playback",
  7742. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  7743. .platform_name = "msm-pcm-routing",
  7744. .codec_name = "bolero_codec",
  7745. .codec_dai_name = "wsa_macro_rx_mix",
  7746. .no_pcm = 1,
  7747. .dpcm_playback = 1,
  7748. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  7749. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7750. .ignore_pmdown_time = 1,
  7751. .ignore_suspend = 1,
  7752. .ops = &msm_cdc_dma_be_ops,
  7753. },
  7754. {
  7755. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  7756. .stream_name = "WSA CDC DMA1 Capture",
  7757. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  7758. .platform_name = "msm-pcm-routing",
  7759. .codec_name = "bolero_codec",
  7760. .codec_dai_name = "wsa_macro_echo",
  7761. .no_pcm = 1,
  7762. .dpcm_capture = 1,
  7763. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  7764. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7765. .ignore_suspend = 1,
  7766. .ops = &msm_cdc_dma_be_ops,
  7767. },
  7768. };
  7769. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  7770. {
  7771. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  7772. .stream_name = "VA CDC DMA0 Capture",
  7773. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  7774. .platform_name = "msm-pcm-routing",
  7775. .codec_name = "bolero_codec",
  7776. .codec_dai_name = "va_macro_tx1",
  7777. .no_pcm = 1,
  7778. .dpcm_capture = 1,
  7779. .init = &msm_va_cdc_dma_init,
  7780. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  7781. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7782. .ignore_suspend = 1,
  7783. .ops = &msm_cdc_dma_be_ops,
  7784. },
  7785. {
  7786. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  7787. .stream_name = "VA CDC DMA1 Capture",
  7788. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  7789. .platform_name = "msm-pcm-routing",
  7790. .codec_name = "bolero_codec",
  7791. .codec_dai_name = "va_macro_tx2",
  7792. .no_pcm = 1,
  7793. .dpcm_capture = 1,
  7794. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  7795. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7796. .ignore_suspend = 1,
  7797. .ops = &msm_cdc_dma_be_ops,
  7798. },
  7799. };
  7800. static struct snd_soc_dai_link msm_spdif_be_dai_links[] = {
  7801. {
  7802. .name = LPASS_BE_PRI_SPDIF_RX,
  7803. .stream_name = "Primary SPDIF Playback",
  7804. .cpu_dai_name = "msm-dai-q6-spdif.20480",
  7805. .platform_name = "msm-pcm-routing",
  7806. .codec_name = "msm-stub-codec.1",
  7807. .codec_dai_name = "msm-stub-rx",
  7808. .no_pcm = 1,
  7809. .dpcm_playback = 1,
  7810. .id = MSM_BACKEND_DAI_PRI_SPDIF_RX,
  7811. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7812. .ops = &msm_spdif_be_ops,
  7813. .ignore_suspend = 1,
  7814. .ignore_pmdown_time = 1,
  7815. },
  7816. {
  7817. .name = LPASS_BE_PRI_SPDIF_TX,
  7818. .stream_name = "Primary SPDIF Capture",
  7819. .cpu_dai_name = "msm-dai-q6-spdif.20481",
  7820. .platform_name = "msm-pcm-routing",
  7821. .codec_name = "msm-stub-codec.1",
  7822. .codec_dai_name = "msm-stub-tx",
  7823. .no_pcm = 1,
  7824. .dpcm_capture = 1,
  7825. .id = MSM_BACKEND_DAI_PRI_SPDIF_TX,
  7826. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7827. .ops = &msm_spdif_be_ops,
  7828. .ignore_suspend = 1,
  7829. },
  7830. {
  7831. .name = LPASS_BE_SEC_SPDIF_RX,
  7832. .stream_name = "Secondary SPDIF Playback",
  7833. .cpu_dai_name = "msm-dai-q6-spdif.20482",
  7834. .platform_name = "msm-pcm-routing",
  7835. .codec_name = "msm-stub-codec.1",
  7836. .codec_dai_name = "msm-stub-rx",
  7837. .no_pcm = 1,
  7838. .dpcm_playback = 1,
  7839. .id = MSM_BACKEND_DAI_SEC_SPDIF_RX,
  7840. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7841. .ops = &msm_spdif_be_ops,
  7842. .ignore_suspend = 1,
  7843. .ignore_pmdown_time = 1,
  7844. },
  7845. {
  7846. .name = LPASS_BE_SEC_SPDIF_TX,
  7847. .stream_name = "Secondary SPDIF Capture",
  7848. .cpu_dai_name = "msm-dai-q6-spdif.20483",
  7849. .platform_name = "msm-pcm-routing",
  7850. .codec_name = "msm-stub-codec.1",
  7851. .codec_dai_name = "msm-stub-tx",
  7852. .no_pcm = 1,
  7853. .dpcm_capture = 1,
  7854. .id = MSM_BACKEND_DAI_SEC_SPDIF_TX,
  7855. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7856. .ops = &msm_spdif_be_ops,
  7857. .ignore_suspend = 1,
  7858. },
  7859. };
  7860. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  7861. {
  7862. .name = LPASS_BE_AFE_LOOPBACK_TX,
  7863. .stream_name = "AFE Loopback Capture",
  7864. .cpu_dai_name = "msm-dai-q6-dev.24577",
  7865. .platform_name = "msm-pcm-routing",
  7866. .codec_name = "msm-stub-codec.1",
  7867. .codec_dai_name = "msm-stub-tx",
  7868. .no_pcm = 1,
  7869. .dpcm_capture = 1,
  7870. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  7871. .be_hw_params_fixup = msm_be_hw_params_fixup,
  7872. .ignore_pmdown_time = 1,
  7873. .ignore_suspend = 1,
  7874. },
  7875. };
  7876. static struct snd_soc_dai_link msm_qcs405_dai_links[
  7877. ARRAY_SIZE(msm_common_dai_links) +
  7878. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  7879. ARRAY_SIZE(msm_common_be_dai_links) +
  7880. ARRAY_SIZE(msm_tasha_be_dai_links) +
  7881. ARRAY_SIZE(msm_wcn_be_dai_links) +
  7882. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  7883. ARRAY_SIZE(msm_meta_mi2s_be_dai_links) +
  7884. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  7885. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  7886. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  7887. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  7888. ARRAY_SIZE(msm_spdif_be_dai_links) +
  7889. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  7890. ARRAY_SIZE(ext_hdmi_be_dai_link)];
  7891. static int msm_snd_card_tasha_late_probe(struct snd_soc_card *card)
  7892. {
  7893. int ret = 0;
  7894. ret = audio_notifier_register("qcs405", AUDIO_NOTIFIER_ADSP_DOMAIN,
  7895. &service_nb);
  7896. if (ret < 0)
  7897. pr_err("%s: Audio notifier register failed ret = %d\n",
  7898. __func__, ret);
  7899. return ret;
  7900. }
  7901. static int msm_snd_vad_cfg_put(struct snd_kcontrol *kcontrol,
  7902. struct snd_ctl_elem_value *ucontrol)
  7903. {
  7904. int ret = 0;
  7905. int port_id;
  7906. uint32_t vad_enable = ucontrol->value.integer.value[0];
  7907. uint32_t preroll_config = ucontrol->value.integer.value[1];
  7908. uint32_t vad_intf = ucontrol->value.integer.value[2];
  7909. if ((preroll_config < 0) || (preroll_config > 1000) ||
  7910. (vad_enable < 0) || (vad_enable > 1) ||
  7911. (vad_intf > MSM_BACKEND_DAI_MAX)) {
  7912. pr_err("%s: Invalid arguments\n", __func__);
  7913. ret = -EINVAL;
  7914. goto done;
  7915. }
  7916. pr_debug("%s: vad_enable=%d preroll_config=%d vad_intf=%d\n", __func__,
  7917. vad_enable, preroll_config, vad_intf);
  7918. ret = msm_island_vad_get_portid_from_beid(vad_intf, &port_id);
  7919. if (ret) {
  7920. pr_err("%s: Invalid vad interface\n", __func__);
  7921. goto done;
  7922. }
  7923. afe_set_vad_cfg(vad_enable, preroll_config, port_id);
  7924. done:
  7925. return ret;
  7926. }
  7927. static int msm_snd_card_codec_late_probe(struct snd_soc_card *card)
  7928. {
  7929. int ret = 0;
  7930. uint32_t tasha_codec = 0;
  7931. ret = afe_cal_init_hwdep(card);
  7932. if (ret) {
  7933. dev_err(card->dev, "afe cal hwdep init failed (%d)\n", ret);
  7934. ret = 0;
  7935. }
  7936. /* tasha late probe when it is present */
  7937. ret = of_property_read_u32(card->dev->of_node, "qcom,tasha-codec",
  7938. &tasha_codec);
  7939. if (ret) {
  7940. dev_err(card->dev, "%s: No DT match tasha codec\n", __func__);
  7941. ret = 0;
  7942. } else {
  7943. if (tasha_codec) {
  7944. ret = msm_snd_card_tasha_late_probe(card);
  7945. if (ret)
  7946. dev_err(card->dev, "%s: tasha late probe err\n",
  7947. __func__);
  7948. }
  7949. }
  7950. return ret;
  7951. }
  7952. struct snd_soc_card snd_soc_card_qcs405_msm = {
  7953. .name = "qcs405-snd-card",
  7954. .controls = msm_snd_controls,
  7955. .num_controls = ARRAY_SIZE(msm_snd_controls),
  7956. .late_probe = msm_snd_card_codec_late_probe,
  7957. };
  7958. static int msm_populate_dai_link_component_of_node(
  7959. struct snd_soc_card *card)
  7960. {
  7961. int i, index, ret = 0;
  7962. struct device *cdev = card->dev;
  7963. struct snd_soc_dai_link *dai_link = card->dai_link;
  7964. struct device_node *np;
  7965. if (!cdev) {
  7966. pr_err("%s: Sound card device memory NULL\n", __func__);
  7967. return -ENODEV;
  7968. }
  7969. for (i = 0; i < card->num_links; i++) {
  7970. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  7971. continue;
  7972. /* populate platform_of_node for snd card dai links */
  7973. if (dai_link[i].platform_name &&
  7974. !dai_link[i].platform_of_node) {
  7975. index = of_property_match_string(cdev->of_node,
  7976. "asoc-platform-names",
  7977. dai_link[i].platform_name);
  7978. if (index < 0) {
  7979. pr_err("%s: No match found for platform name: %s\n",
  7980. __func__, dai_link[i].platform_name);
  7981. ret = index;
  7982. goto err;
  7983. }
  7984. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  7985. index);
  7986. if (!np) {
  7987. pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
  7988. __func__, dai_link[i].platform_name,
  7989. index);
  7990. ret = -ENODEV;
  7991. goto err;
  7992. }
  7993. dai_link[i].platform_of_node = np;
  7994. dai_link[i].platform_name = NULL;
  7995. }
  7996. /* populate cpu_of_node for snd card dai links */
  7997. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  7998. index = of_property_match_string(cdev->of_node,
  7999. "asoc-cpu-names",
  8000. dai_link[i].cpu_dai_name);
  8001. if (index >= 0) {
  8002. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  8003. index);
  8004. if (!np) {
  8005. pr_err("%s: retrieving phandle for cpu dai %s failed\n",
  8006. __func__,
  8007. dai_link[i].cpu_dai_name);
  8008. ret = -ENODEV;
  8009. goto err;
  8010. }
  8011. dai_link[i].cpu_of_node = np;
  8012. dai_link[i].cpu_dai_name = NULL;
  8013. }
  8014. }
  8015. /* populate codec_of_node for snd card dai links */
  8016. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  8017. index = of_property_match_string(cdev->of_node,
  8018. "asoc-codec-names",
  8019. dai_link[i].codec_name);
  8020. if (index < 0)
  8021. continue;
  8022. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  8023. index);
  8024. if (!np) {
  8025. pr_err("%s: retrieving phandle for codec %s failed\n",
  8026. __func__, dai_link[i].codec_name);
  8027. ret = -ENODEV;
  8028. goto err;
  8029. }
  8030. dai_link[i].codec_of_node = np;
  8031. dai_link[i].codec_name = NULL;
  8032. }
  8033. }
  8034. err:
  8035. return ret;
  8036. }
  8037. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  8038. /* FrontEnd DAI Links */
  8039. {
  8040. .name = "MSMSTUB Media1",
  8041. .stream_name = "MultiMedia1",
  8042. .cpu_dai_name = "MultiMedia1",
  8043. .platform_name = "msm-pcm-dsp.0",
  8044. .dynamic = 1,
  8045. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  8046. .dpcm_playback = 1,
  8047. .dpcm_capture = 1,
  8048. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  8049. SND_SOC_DPCM_TRIGGER_POST},
  8050. .codec_dai_name = "snd-soc-dummy-dai",
  8051. .codec_name = "snd-soc-dummy",
  8052. .ignore_suspend = 1,
  8053. /* this dainlink has playback support */
  8054. .ignore_pmdown_time = 1,
  8055. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  8056. },
  8057. };
  8058. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  8059. /* Backend DAI Links */
  8060. {
  8061. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  8062. .stream_name = "VA CDC DMA0 Capture",
  8063. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  8064. .platform_name = "msm-pcm-routing",
  8065. .codec_name = "bolero_codec",
  8066. .codec_dai_name = "va_macro_tx1",
  8067. .no_pcm = 1,
  8068. .dpcm_capture = 1,
  8069. .init = &msm_va_cdc_dma_init,
  8070. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  8071. .be_hw_params_fixup = msm_be_hw_params_fixup,
  8072. .ignore_suspend = 1,
  8073. .ops = &msm_cdc_dma_be_ops,
  8074. },
  8075. {
  8076. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  8077. .stream_name = "VA CDC DMA1 Capture",
  8078. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  8079. .platform_name = "msm-pcm-routing",
  8080. .codec_name = "bolero_codec",
  8081. .codec_dai_name = "va_macro_tx2",
  8082. .no_pcm = 1,
  8083. .dpcm_capture = 1,
  8084. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  8085. .be_hw_params_fixup = msm_be_hw_params_fixup,
  8086. .ignore_suspend = 1,
  8087. .ops = &msm_cdc_dma_be_ops,
  8088. },
  8089. };
  8090. static struct snd_soc_dai_link msm_stub_dai_links[
  8091. ARRAY_SIZE(msm_stub_fe_dai_links) +
  8092. ARRAY_SIZE(msm_stub_be_dai_links)];
  8093. struct snd_soc_card snd_soc_card_stub_msm = {
  8094. .name = "qcs405-stub-snd-card",
  8095. };
  8096. static const struct of_device_id qcs405_asoc_machine_of_match[] = {
  8097. { .compatible = "qcom,qcs405-asoc-snd",
  8098. .data = "codec"},
  8099. { .compatible = "qcom,qcs405-asoc-snd-stub",
  8100. .data = "stub_codec"},
  8101. {},
  8102. };
  8103. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  8104. {
  8105. struct snd_soc_card *card = NULL;
  8106. struct snd_soc_dai_link *dailink;
  8107. int total_links = 0;
  8108. uint32_t tasha_codec = 0, auxpcm_audio_intf = 0;
  8109. uint32_t va_bolero_codec = 0, wsa_bolero_codec = 0, mi2s_audio_intf = 0;
  8110. uint32_t spdif_audio_intf = 0, wcn_audio_intf = 0;
  8111. uint32_t afe_loopback_intf = 0, meta_mi2s_intf = 0;
  8112. uint32_t ext_disp_hdmi_rx = 0;
  8113. const struct of_device_id *match;
  8114. char __iomem *spdif_cfg, *spdif_pin_ctl;
  8115. int rc = 0;
  8116. match = of_match_node(qcs405_asoc_machine_of_match, dev->of_node);
  8117. if (!match) {
  8118. dev_err(dev, "%s: No DT match found for sound card\n",
  8119. __func__);
  8120. return NULL;
  8121. }
  8122. if (!strcmp(match->data, "codec")) {
  8123. card = &snd_soc_card_qcs405_msm;
  8124. memcpy(msm_qcs405_dai_links + total_links,
  8125. msm_common_dai_links,
  8126. sizeof(msm_common_dai_links));
  8127. total_links += ARRAY_SIZE(msm_common_dai_links);
  8128. rc = of_property_read_u32(dev->of_node, "qcom,wsa-bolero-codec",
  8129. &wsa_bolero_codec);
  8130. if (rc) {
  8131. dev_dbg(dev, "%s: No DT match WSA Macro codec\n",
  8132. __func__);
  8133. } else {
  8134. if (wsa_bolero_codec) {
  8135. dev_dbg(dev, "%s(): WSA macro in bolero codec present\n",
  8136. __func__);
  8137. memcpy(msm_qcs405_dai_links + total_links,
  8138. msm_bolero_fe_dai_links,
  8139. sizeof(msm_bolero_fe_dai_links));
  8140. total_links +=
  8141. ARRAY_SIZE(msm_bolero_fe_dai_links);
  8142. }
  8143. }
  8144. memcpy(msm_qcs405_dai_links + total_links,
  8145. msm_common_misc_fe_dai_links,
  8146. sizeof(msm_common_misc_fe_dai_links));
  8147. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  8148. memcpy(msm_qcs405_dai_links + total_links,
  8149. msm_common_be_dai_links,
  8150. sizeof(msm_common_be_dai_links));
  8151. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  8152. rc = of_property_read_u32(dev->of_node, "qcom,tasha-codec",
  8153. &tasha_codec);
  8154. if (rc) {
  8155. dev_dbg(dev, "%s: No DT match tasha codec\n",
  8156. __func__);
  8157. } else {
  8158. if (tasha_codec) {
  8159. memcpy(msm_qcs405_dai_links + total_links,
  8160. msm_tasha_be_dai_links,
  8161. sizeof(msm_tasha_be_dai_links));
  8162. total_links +=
  8163. ARRAY_SIZE(msm_tasha_be_dai_links);
  8164. }
  8165. }
  8166. rc = of_property_read_u32(dev->of_node, "qcom,va-bolero-codec",
  8167. &va_bolero_codec);
  8168. if (rc) {
  8169. dev_dbg(dev, "%s: No DT match VA Macro codec\n",
  8170. __func__);
  8171. } else {
  8172. if (va_bolero_codec) {
  8173. dev_dbg(dev, "%s(): VA macro in bolero codec present\n",
  8174. __func__);
  8175. memcpy(msm_qcs405_dai_links + total_links,
  8176. msm_va_cdc_dma_be_dai_links,
  8177. sizeof(msm_va_cdc_dma_be_dai_links));
  8178. total_links +=
  8179. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  8180. }
  8181. }
  8182. if (wsa_bolero_codec) {
  8183. dev_dbg(dev, "%s(): WSAmacro in bolero codec present\n",
  8184. __func__);
  8185. memcpy(msm_qcs405_dai_links + total_links,
  8186. msm_wsa_cdc_dma_be_dai_links,
  8187. sizeof(msm_wsa_cdc_dma_be_dai_links));
  8188. total_links +=
  8189. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  8190. }
  8191. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  8192. &mi2s_audio_intf);
  8193. if (rc) {
  8194. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  8195. __func__);
  8196. } else {
  8197. if (mi2s_audio_intf) {
  8198. memcpy(msm_qcs405_dai_links + total_links,
  8199. msm_mi2s_be_dai_links,
  8200. sizeof(msm_mi2s_be_dai_links));
  8201. total_links +=
  8202. ARRAY_SIZE(msm_mi2s_be_dai_links);
  8203. }
  8204. }
  8205. rc = of_property_read_u32(dev->of_node, "qcom,meta-mi2s-intf",
  8206. &meta_mi2s_intf);
  8207. if (rc) {
  8208. dev_dbg(dev, "%s: No DT match META-MI2S interface\n",
  8209. __func__);
  8210. } else {
  8211. if (meta_mi2s_intf) {
  8212. memcpy(msm_qcs405_dai_links + total_links,
  8213. msm_meta_mi2s_be_dai_links,
  8214. sizeof(msm_meta_mi2s_be_dai_links));
  8215. total_links +=
  8216. ARRAY_SIZE(msm_meta_mi2s_be_dai_links);
  8217. }
  8218. }
  8219. rc = of_property_read_u32(dev->of_node,
  8220. "qcom,auxpcm-audio-intf",
  8221. &auxpcm_audio_intf);
  8222. if (rc) {
  8223. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  8224. __func__);
  8225. } else {
  8226. if (auxpcm_audio_intf) {
  8227. memcpy(msm_qcs405_dai_links + total_links,
  8228. msm_auxpcm_be_dai_links,
  8229. sizeof(msm_auxpcm_be_dai_links));
  8230. total_links +=
  8231. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  8232. }
  8233. }
  8234. rc = of_property_read_u32(dev->of_node, "qcom,spdif-audio-intf",
  8235. &spdif_audio_intf);
  8236. if (rc) {
  8237. dev_dbg(dev, "%s: No DT match SPDIF audio interface\n",
  8238. __func__);
  8239. } else {
  8240. if (spdif_audio_intf) {
  8241. memcpy(msm_qcs405_dai_links + total_links,
  8242. msm_spdif_be_dai_links,
  8243. sizeof(msm_spdif_be_dai_links));
  8244. total_links +=
  8245. ARRAY_SIZE(msm_spdif_be_dai_links);
  8246. /* enable spdif coax pins */
  8247. spdif_cfg = ioremap(TLMM_EAST_SPARE, 0x4);
  8248. spdif_pin_ctl =
  8249. ioremap(TLMM_SPDIF_HDMI_ARC_CTL, 0x4);
  8250. iowrite32(0xc0, spdif_cfg);
  8251. iowrite32(0x2220, spdif_pin_ctl);
  8252. }
  8253. }
  8254. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  8255. &wcn_audio_intf);
  8256. if (rc) {
  8257. dev_dbg(dev, "%s: No DT match WCN audio interface\n",
  8258. __func__);
  8259. } else {
  8260. if (wcn_audio_intf) {
  8261. memcpy(msm_qcs405_dai_links + total_links,
  8262. msm_wcn_be_dai_links,
  8263. sizeof(msm_wcn_be_dai_links));
  8264. total_links +=
  8265. ARRAY_SIZE(msm_wcn_be_dai_links);
  8266. }
  8267. }
  8268. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  8269. &afe_loopback_intf);
  8270. if (rc) {
  8271. dev_dbg(dev, "%s: No DT match AFE loopback audio interface\n",
  8272. __func__);
  8273. } else {
  8274. if (afe_loopback_intf) {
  8275. memcpy(msm_qcs405_dai_links + total_links,
  8276. msm_afe_rxtx_lb_be_dai_link,
  8277. sizeof(msm_afe_rxtx_lb_be_dai_link));
  8278. total_links +=
  8279. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  8280. }
  8281. }
  8282. rc = of_property_read_u32(dev->of_node,
  8283. "qcom,ext-disp-audio-rx", &ext_disp_hdmi_rx);
  8284. if (rc) {
  8285. dev_dbg(dev, "%s: No DT match ext disp hdmi rx\n",
  8286. __func__);
  8287. } else {
  8288. if (ext_disp_hdmi_rx) {
  8289. memcpy(msm_qcs405_dai_links + total_links,
  8290. ext_hdmi_be_dai_link,
  8291. sizeof(ext_hdmi_be_dai_link));
  8292. total_links += ARRAY_SIZE(ext_hdmi_be_dai_link);
  8293. }
  8294. }
  8295. dailink = msm_qcs405_dai_links;
  8296. } else if (!strcmp(match->data, "stub_codec")) {
  8297. card = &snd_soc_card_stub_msm;
  8298. memcpy(msm_stub_dai_links + total_links,
  8299. msm_stub_fe_dai_links,
  8300. sizeof(msm_stub_fe_dai_links));
  8301. total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
  8302. memcpy(msm_stub_dai_links + total_links,
  8303. msm_stub_be_dai_links,
  8304. sizeof(msm_stub_be_dai_links));
  8305. total_links += ARRAY_SIZE(msm_stub_be_dai_links);
  8306. dailink = msm_stub_dai_links;
  8307. }
  8308. if (card) {
  8309. card->dai_link = dailink;
  8310. card->num_links = total_links;
  8311. }
  8312. return card;
  8313. }
  8314. static int msm_wsa881x_init(struct snd_soc_component *component)
  8315. {
  8316. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  8317. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  8318. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  8319. SPKR_L_BOOST, SPKR_L_VI};
  8320. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  8321. SPKR_R_BOOST, SPKR_R_VI};
  8322. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  8323. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  8324. struct msm_asoc_mach_data *pdata;
  8325. struct snd_soc_dapm_context *dapm;
  8326. int ret = 0;
  8327. if (!component) {
  8328. pr_err("%s component is NULL\n", __func__);
  8329. return -EINVAL;
  8330. }
  8331. dapm = snd_soc_component_get_dapm(component);
  8332. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  8333. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  8334. __func__, component->name);
  8335. wsa881x_set_channel_map(component, &spkleft_ports[0],
  8336. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  8337. &ch_rate[0], &spkleft_port_types[0]);
  8338. if (dapm->component) {
  8339. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  8340. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  8341. }
  8342. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  8343. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  8344. __func__, component->name);
  8345. wsa881x_set_channel_map(component, &spkright_ports[0],
  8346. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  8347. &ch_rate[0], &spkright_port_types[0]);
  8348. if (dapm->component) {
  8349. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  8350. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  8351. }
  8352. } else {
  8353. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  8354. component->name);
  8355. ret = -EINVAL;
  8356. goto err;
  8357. }
  8358. pdata = snd_soc_card_get_drvdata(component->card);
  8359. if (pdata && pdata->codec_root)
  8360. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  8361. component);
  8362. err:
  8363. return ret;
  8364. }
  8365. static int msm_init_wsa_dev(struct platform_device *pdev,
  8366. struct snd_soc_card *card)
  8367. {
  8368. struct device_node *wsa_of_node;
  8369. u32 wsa_max_devs;
  8370. u32 wsa_dev_cnt;
  8371. int i;
  8372. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  8373. const char *wsa_auxdev_name_prefix[1];
  8374. char *dev_name_str = NULL;
  8375. int found = 0;
  8376. int ret = 0;
  8377. /* Get maximum WSA device count for this platform */
  8378. ret = of_property_read_u32(pdev->dev.of_node,
  8379. "qcom,wsa-max-devs", &wsa_max_devs);
  8380. if (ret) {
  8381. dev_info(&pdev->dev,
  8382. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  8383. __func__, pdev->dev.of_node->full_name, ret);
  8384. card->num_aux_devs = 0;
  8385. return 0;
  8386. }
  8387. if (wsa_max_devs == 0) {
  8388. dev_warn(&pdev->dev,
  8389. "%s: Max WSA devices is 0 for this target?\n",
  8390. __func__);
  8391. card->num_aux_devs = 0;
  8392. return 0;
  8393. }
  8394. /* Get count of WSA device phandles for this platform */
  8395. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  8396. "qcom,wsa-devs", NULL);
  8397. if (wsa_dev_cnt == -ENOENT) {
  8398. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  8399. __func__);
  8400. goto err;
  8401. } else if (wsa_dev_cnt <= 0) {
  8402. dev_err(&pdev->dev,
  8403. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  8404. __func__, wsa_dev_cnt);
  8405. ret = -EINVAL;
  8406. goto err;
  8407. }
  8408. /*
  8409. * Expect total phandles count to be NOT less than maximum possible
  8410. * WSA count. However, if it is less, then assign same value to
  8411. * max count as well.
  8412. */
  8413. if (wsa_dev_cnt < wsa_max_devs) {
  8414. dev_dbg(&pdev->dev,
  8415. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  8416. __func__, wsa_max_devs, wsa_dev_cnt);
  8417. wsa_max_devs = wsa_dev_cnt;
  8418. }
  8419. /* Make sure prefix string passed for each WSA device */
  8420. ret = of_property_count_strings(pdev->dev.of_node,
  8421. "qcom,wsa-aux-dev-prefix");
  8422. if (ret != wsa_dev_cnt) {
  8423. dev_err(&pdev->dev,
  8424. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  8425. __func__, wsa_dev_cnt, ret);
  8426. ret = -EINVAL;
  8427. goto err;
  8428. }
  8429. /*
  8430. * Alloc mem to store phandle and index info of WSA device, if already
  8431. * registered with ALSA core
  8432. */
  8433. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  8434. sizeof(struct msm_wsa881x_dev_info),
  8435. GFP_KERNEL);
  8436. if (!wsa881x_dev_info) {
  8437. ret = -ENOMEM;
  8438. goto err;
  8439. }
  8440. /*
  8441. * search and check whether all WSA devices are already
  8442. * registered with ALSA core or not. If found a node, store
  8443. * the node and the index in a local array of struct for later
  8444. * use.
  8445. */
  8446. for (i = 0; i < wsa_dev_cnt; i++) {
  8447. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  8448. "qcom,wsa-devs", i);
  8449. if (unlikely(!wsa_of_node)) {
  8450. /* we should not be here */
  8451. dev_err(&pdev->dev,
  8452. "%s: wsa dev node is not present\n",
  8453. __func__);
  8454. ret = -EINVAL;
  8455. goto err_free_dev_info;
  8456. }
  8457. if (soc_find_component(wsa_of_node, NULL)) {
  8458. /* WSA device registered with ALSA core */
  8459. wsa881x_dev_info[found].of_node = wsa_of_node;
  8460. wsa881x_dev_info[found].index = i;
  8461. found++;
  8462. if (found == wsa_max_devs)
  8463. break;
  8464. }
  8465. }
  8466. if (found < wsa_max_devs) {
  8467. dev_err(&pdev->dev,
  8468. "%s: failed to find %d components. Found only %d\n",
  8469. __func__, wsa_max_devs, found);
  8470. return -EPROBE_DEFER;
  8471. }
  8472. dev_info(&pdev->dev,
  8473. "%s: found %d wsa881x devices registered with ALSA core\n",
  8474. __func__, found);
  8475. card->num_aux_devs = wsa_max_devs;
  8476. card->num_configs = wsa_max_devs;
  8477. /* Alloc array of AUX devs struct */
  8478. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  8479. sizeof(struct snd_soc_aux_dev),
  8480. GFP_KERNEL);
  8481. if (!msm_aux_dev) {
  8482. ret = -ENOMEM;
  8483. goto err_free_dev_info;
  8484. }
  8485. /* Alloc array of codec conf struct */
  8486. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  8487. sizeof(struct snd_soc_codec_conf),
  8488. GFP_KERNEL);
  8489. if (!msm_codec_conf) {
  8490. ret = -ENOMEM;
  8491. goto err_free_aux_dev;
  8492. }
  8493. for (i = 0; i < card->num_aux_devs; i++) {
  8494. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  8495. GFP_KERNEL);
  8496. if (!dev_name_str) {
  8497. ret = -ENOMEM;
  8498. goto err_free_cdc_conf;
  8499. }
  8500. ret = of_property_read_string_index(pdev->dev.of_node,
  8501. "qcom,wsa-aux-dev-prefix",
  8502. wsa881x_dev_info[i].index,
  8503. wsa_auxdev_name_prefix);
  8504. if (ret) {
  8505. dev_err(&pdev->dev,
  8506. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  8507. __func__, ret);
  8508. ret = -EINVAL;
  8509. goto err_free_dev_name_str;
  8510. }
  8511. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  8512. msm_aux_dev[i].name = dev_name_str;
  8513. msm_aux_dev[i].codec_name = NULL;
  8514. msm_aux_dev[i].codec_of_node =
  8515. wsa881x_dev_info[i].of_node;
  8516. msm_aux_dev[i].init = msm_wsa881x_init;
  8517. msm_codec_conf[i].dev_name = NULL;
  8518. msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0];
  8519. msm_codec_conf[i].of_node =
  8520. wsa881x_dev_info[i].of_node;
  8521. }
  8522. card->codec_conf = msm_codec_conf;
  8523. card->aux_dev = msm_aux_dev;
  8524. return 0;
  8525. err_free_dev_name_str:
  8526. devm_kfree(&pdev->dev, dev_name_str);
  8527. err_free_cdc_conf:
  8528. devm_kfree(&pdev->dev, msm_codec_conf);
  8529. err_free_aux_dev:
  8530. devm_kfree(&pdev->dev, msm_aux_dev);
  8531. err_free_dev_info:
  8532. devm_kfree(&pdev->dev, wsa881x_dev_info);
  8533. err:
  8534. return ret;
  8535. }
  8536. static int msm_csra66x0_init(struct snd_soc_component *component)
  8537. {
  8538. if (!component) {
  8539. pr_err("%s component is NULL\n", __func__);
  8540. return -EINVAL;
  8541. }
  8542. return 0;
  8543. }
  8544. static int msm_init_csra_dev(struct platform_device *pdev,
  8545. struct snd_soc_card *card)
  8546. {
  8547. struct device_node *csra_of_node;
  8548. u32 csra_max_devs;
  8549. u32 csra_dev_cnt;
  8550. char *dev_name_str = NULL;
  8551. struct msm_csra66x0_dev_info *csra66x0_dev_info;
  8552. const char *csra_auxdev_name_prefix[1];
  8553. int i;
  8554. int found = 0;
  8555. int ret = 0;
  8556. /* Get maximum CSRA device count for this platform */
  8557. ret = of_property_read_u32(pdev->dev.of_node,
  8558. "qcom,csra-max-devs", &csra_max_devs);
  8559. if (ret) {
  8560. dev_info(&pdev->dev,
  8561. "%s: csra-max-devs property missing in DT %s, ret = %d\n",
  8562. __func__, pdev->dev.of_node->full_name, ret);
  8563. card->num_aux_devs = 0;
  8564. return 0;
  8565. }
  8566. if (csra_max_devs == 0) {
  8567. dev_warn(&pdev->dev,
  8568. "%s: Max CSRA devices is 0 for this target?\n",
  8569. __func__);
  8570. return 0;
  8571. }
  8572. /* Get count of CSRA device phandles for this platform */
  8573. csra_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  8574. "qcom,csra-devs", NULL);
  8575. if (csra_dev_cnt == -ENOENT) {
  8576. dev_warn(&pdev->dev, "%s: No csra device defined in DT.\n",
  8577. __func__);
  8578. goto err;
  8579. } else if (csra_dev_cnt <= 0) {
  8580. dev_err(&pdev->dev,
  8581. "%s: Error reading csra device from DT. csra_dev_cnt = %d\n",
  8582. __func__, csra_dev_cnt);
  8583. ret = -EINVAL;
  8584. goto err;
  8585. }
  8586. /*
  8587. * Expect total phandles count to be NOT less than maximum possible
  8588. * CSRA count. However, if it is less, then assign same value to
  8589. * max count as well.
  8590. */
  8591. if (csra_dev_cnt < csra_max_devs) {
  8592. dev_dbg(&pdev->dev,
  8593. "%s: csra_max_devs = %d cannot exceed csra_dev_cnt = %d\n",
  8594. __func__, csra_max_devs, csra_dev_cnt);
  8595. csra_max_devs = csra_dev_cnt;
  8596. }
  8597. /* Make sure prefix string passed for each CSRA device */
  8598. ret = of_property_count_strings(pdev->dev.of_node,
  8599. "qcom,csra-aux-dev-prefix");
  8600. if (ret != csra_dev_cnt) {
  8601. dev_err(&pdev->dev,
  8602. "%s: expecting %d csra prefix. Defined only %d in DT\n",
  8603. __func__, csra_dev_cnt, ret);
  8604. ret = -EINVAL;
  8605. goto err;
  8606. }
  8607. /*
  8608. * Alloc mem to store phandle and index info of CSRA device, if already
  8609. * registered with ALSA core
  8610. */
  8611. csra66x0_dev_info = devm_kcalloc(&pdev->dev, csra_max_devs,
  8612. sizeof(struct msm_csra66x0_dev_info),
  8613. GFP_KERNEL);
  8614. if (!csra66x0_dev_info) {
  8615. ret = -ENOMEM;
  8616. goto err;
  8617. }
  8618. /*
  8619. * search and check whether all CSRA devices are already
  8620. * registered with ALSA core or not. If found a node, store
  8621. * the node and the index in a local array of struct for later
  8622. * use.
  8623. */
  8624. for (i = 0; i < csra_dev_cnt; i++) {
  8625. csra_of_node = of_parse_phandle(pdev->dev.of_node,
  8626. "qcom,csra-devs", i);
  8627. if (unlikely(!csra_of_node)) {
  8628. /* we should not be here */
  8629. dev_err(&pdev->dev,
  8630. "%s: csra dev node is not present\n",
  8631. __func__);
  8632. ret = -EINVAL;
  8633. goto err_free_dev_info;
  8634. }
  8635. if (soc_find_component(csra_of_node, NULL)) {
  8636. /* CSRA device registered with ALSA core */
  8637. csra66x0_dev_info[found].of_node = csra_of_node;
  8638. csra66x0_dev_info[found].index = i;
  8639. found++;
  8640. if (found == csra_max_devs)
  8641. break;
  8642. }
  8643. }
  8644. if (found < csra_max_devs) {
  8645. dev_dbg(&pdev->dev,
  8646. "%s: failed to find %d components. Found only %d\n",
  8647. __func__, csra_max_devs, found);
  8648. return -EPROBE_DEFER;
  8649. }
  8650. dev_info(&pdev->dev,
  8651. "%s: found %d csra66x0 devices registered with ALSA core\n",
  8652. __func__, found);
  8653. card->num_aux_devs = csra_max_devs;
  8654. card->num_configs = csra_max_devs;
  8655. /* Alloc array of AUX devs struct */
  8656. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  8657. sizeof(struct snd_soc_aux_dev), GFP_KERNEL);
  8658. if (!msm_aux_dev) {
  8659. ret = -ENOMEM;
  8660. goto err_free_dev_info;
  8661. }
  8662. /* Alloc array of codec conf struct */
  8663. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  8664. sizeof(struct snd_soc_codec_conf), GFP_KERNEL);
  8665. if (!msm_codec_conf) {
  8666. ret = -ENOMEM;
  8667. goto err_free_aux_dev;
  8668. }
  8669. for (i = 0; i < card->num_aux_devs; i++) {
  8670. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  8671. GFP_KERNEL);
  8672. if (!dev_name_str) {
  8673. ret = -ENOMEM;
  8674. goto err_free_cdc_conf;
  8675. }
  8676. ret = of_property_read_string_index(pdev->dev.of_node,
  8677. "qcom,csra-aux-dev-prefix",
  8678. csra66x0_dev_info[i].index,
  8679. csra_auxdev_name_prefix);
  8680. if (ret) {
  8681. dev_err(&pdev->dev,
  8682. "%s: failed to read csra aux dev prefix, ret = %d\n",
  8683. __func__, ret);
  8684. ret = -EINVAL;
  8685. goto err_free_dev_name_str;
  8686. }
  8687. snprintf(dev_name_str, strlen("csra66x0.%d"), "csra66x0.%d", i);
  8688. msm_aux_dev[i].name = dev_name_str;
  8689. msm_aux_dev[i].codec_name = NULL;
  8690. msm_aux_dev[i].codec_of_node =
  8691. csra66x0_dev_info[i].of_node;
  8692. msm_aux_dev[i].init = msm_csra66x0_init; /* codec specific init */
  8693. msm_codec_conf[i].dev_name = NULL;
  8694. msm_codec_conf[i].name_prefix = csra_auxdev_name_prefix[0];
  8695. msm_codec_conf[i].of_node = csra66x0_dev_info[i].of_node;
  8696. }
  8697. card->codec_conf = msm_codec_conf;
  8698. card->aux_dev = msm_aux_dev;
  8699. return 0;
  8700. err_free_dev_name_str:
  8701. devm_kfree(&pdev->dev, dev_name_str);
  8702. err_free_cdc_conf:
  8703. devm_kfree(&pdev->dev, msm_codec_conf);
  8704. err_free_aux_dev:
  8705. devm_kfree(&pdev->dev, msm_aux_dev);
  8706. err_free_dev_info:
  8707. devm_kfree(&pdev->dev, csra66x0_dev_info);
  8708. err:
  8709. return ret;
  8710. }
  8711. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  8712. {
  8713. int count;
  8714. u32 mi2s_master_slave[MI2S_MAX];
  8715. int ret;
  8716. for (count = 0; count < MI2S_MAX; count++) {
  8717. mutex_init(&mi2s_intf_conf[count].lock);
  8718. mi2s_intf_conf[count].ref_cnt = 0;
  8719. }
  8720. ret = of_property_read_u32_array(pdev->dev.of_node,
  8721. "qcom,msm-mi2s-master",
  8722. mi2s_master_slave, MI2S_MAX);
  8723. if (ret) {
  8724. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  8725. __func__);
  8726. } else {
  8727. for (count = 0; count < MI2S_MAX; count++) {
  8728. mi2s_intf_conf[count].msm_is_mi2s_master =
  8729. mi2s_master_slave[count];
  8730. }
  8731. }
  8732. }
  8733. static void msm_i2s_auxpcm_deinit(void)
  8734. {
  8735. int count;
  8736. for (count = 0; count < MI2S_MAX; count++) {
  8737. mutex_destroy(&mi2s_intf_conf[count].lock);
  8738. mi2s_intf_conf[count].ref_cnt = 0;
  8739. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  8740. }
  8741. }
  8742. static void msm_meta_mi2s_init(struct platform_device *pdev)
  8743. {
  8744. int rc = 0;
  8745. int i = 0;
  8746. int index = 0;
  8747. bool parse_of = false;
  8748. struct snd_soc_card *card = platform_get_drvdata(pdev);
  8749. struct snd_soc_dai_link *dai_link = card->dai_link;
  8750. dev_dbg(&pdev->dev, "%s: read from DT\n", __func__);
  8751. for (index = 0; index < META_MI2S_MAX; index++) {
  8752. meta_mi2s_intf_conf[index].num_member_ports = 0;
  8753. meta_mi2s_intf_conf[index].member_port[0] = 0;
  8754. meta_mi2s_intf_conf[index].member_port[1] = 0;
  8755. meta_mi2s_intf_conf[index].member_port[2] = 0;
  8756. meta_mi2s_intf_conf[index].member_port[3] = 0;
  8757. meta_mi2s_intf_conf[index].clk_enable[0] = false;
  8758. meta_mi2s_intf_conf[index].clk_enable[1] = false;
  8759. meta_mi2s_intf_conf[index].clk_enable[2] = false;
  8760. meta_mi2s_intf_conf[index].clk_enable[3] = false;
  8761. }
  8762. /* get member port info to set matching clocks for involved ports */
  8763. for (i = 0; i < card->num_links; i++) {
  8764. if (dai_link[i].id == MSM_BACKEND_DAI_PRI_META_MI2S_RX) {
  8765. parse_of = true;
  8766. index = PRIM_META_MI2S;
  8767. } else if (dai_link[i].id == MSM_BACKEND_DAI_SEC_META_MI2S_RX) {
  8768. parse_of = true;
  8769. index = SEC_META_MI2S;
  8770. } else {
  8771. parse_of = false;
  8772. }
  8773. if (parse_of && dai_link[i].cpu_of_node) {
  8774. rc = of_property_read_u32(dai_link[i].cpu_of_node,
  8775. "qcom,msm-mi2s-num-members",
  8776. &meta_mi2s_intf_conf[index].num_member_ports);
  8777. if (rc) {
  8778. dev_err(&pdev->dev, "%s: invalid num from DT file %s\n",
  8779. __func__, "qcom,msm-mi2s-num-members");
  8780. }
  8781. if (meta_mi2s_intf_conf[index].num_member_ports >
  8782. MAX_NUM_I2S_META_PORT_MEMBER_PORTS) {
  8783. dev_err(&pdev->dev, "%s: num-members %d too large from DT file\n",
  8784. __func__,
  8785. meta_mi2s_intf_conf[index].num_member_ports);
  8786. }
  8787. if (meta_mi2s_intf_conf[index].num_member_ports > 0) {
  8788. rc = of_property_read_u32_array(
  8789. dai_link[i].cpu_of_node,
  8790. "qcom,msm-mi2s-member-id",
  8791. meta_mi2s_intf_conf[index].member_port,
  8792. meta_mi2s_intf_conf[index].num_member_ports);
  8793. if (rc) {
  8794. dev_err(&pdev->dev, "%s: member-id from DT file %s\n",
  8795. __func__,
  8796. "qcom,msm-mi2s-member-id");
  8797. }
  8798. }
  8799. dev_dbg(&pdev->dev, "dev name %s num-members=%d\n",
  8800. dev_name(&pdev->dev),
  8801. meta_mi2s_intf_conf[index].num_member_ports);
  8802. dev_dbg(&pdev->dev, "member array (%d, %d, %d, %d)\n",
  8803. meta_mi2s_intf_conf[index].member_port[0],
  8804. meta_mi2s_intf_conf[index].member_port[1],
  8805. meta_mi2s_intf_conf[index].member_port[2],
  8806. meta_mi2s_intf_conf[index].member_port[3]);
  8807. }
  8808. }
  8809. }
  8810. static int msm_scan_i2c_addr(struct platform_device *pdev,
  8811. uint32_t busnum, uint32_t addr)
  8812. {
  8813. struct i2c_adapter *adap;
  8814. u8 rbuf;
  8815. struct i2c_msg msg;
  8816. int status = 0;
  8817. adap = i2c_get_adapter(busnum);
  8818. if (!adap) {
  8819. dev_err(&pdev->dev, "%s: Cannot get I2C adapter %d\n",
  8820. __func__, busnum);
  8821. return -EBUSY;
  8822. }
  8823. /* to test presence, read one byte from device */
  8824. msg.addr = addr;
  8825. msg.flags = I2C_M_RD;
  8826. msg.len = 1;
  8827. msg.buf = &rbuf;
  8828. status = i2c_transfer(adap, &msg, 1);
  8829. i2c_put_adapter(adap);
  8830. if (status != 1) {
  8831. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x failed\n",
  8832. __func__, addr);
  8833. return -ENODEV;
  8834. }
  8835. dev_dbg(&pdev->dev, "%s: I2C read from addr 0x%02x successful\n",
  8836. __func__, addr);
  8837. return 0;
  8838. }
  8839. static int msm_detect_ep92_dev(struct platform_device *pdev,
  8840. struct snd_soc_card *card)
  8841. {
  8842. int i;
  8843. uint32_t ep92_busnum = 0;
  8844. uint32_t ep92_reg = 0;
  8845. const char *ep92_name = NULL;
  8846. struct snd_soc_dai_link *dai;
  8847. int rc = 0;
  8848. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-busnum",
  8849. &ep92_busnum);
  8850. if (rc) {
  8851. dev_info(&pdev->dev, "%s: No DT match ep92-reg\n", __func__);
  8852. return 0;
  8853. }
  8854. rc = of_property_read_u32(pdev->dev.of_node, "qcom,ep92-reg",
  8855. &ep92_reg);
  8856. if (rc) {
  8857. dev_info(&pdev->dev, "%s: No DT match ep92-busnum\n", __func__);
  8858. return 0;
  8859. }
  8860. rc = of_property_read_string(pdev->dev.of_node, "qcom,ep92-name",
  8861. &ep92_name);
  8862. if (rc) {
  8863. dev_info(&pdev->dev, "%s: No DT match ep92-name\n", __func__);
  8864. return 0;
  8865. }
  8866. /* check I2C bus for connected ep92 chip */
  8867. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  8868. /* check a second time after a short delay */
  8869. msleep(20);
  8870. if (msm_scan_i2c_addr(pdev, ep92_busnum, ep92_reg) < 0) {
  8871. dev_info(&pdev->dev, "%s: No ep92 device found\n",
  8872. __func__);
  8873. /* continue with snd_card registration without ep92 */
  8874. return 0;
  8875. }
  8876. }
  8877. dev_info(&pdev->dev, "%s: ep92 device found\n", __func__);
  8878. /* update codec info in MI2S dai link */
  8879. dai = &msm_mi2s_be_dai_links[0];
  8880. for (i=0; i<ARRAY_SIZE(msm_mi2s_be_dai_links); i++) {
  8881. if (strcmp(dai->name, LPASS_BE_SEC_MI2S_TX) == 0) {
  8882. dev_dbg(&pdev->dev,
  8883. "%s: Set Sec MI2S dai to ep92 codec\n",
  8884. __func__);
  8885. dai->codec_name = ep92_name;
  8886. dai->codec_dai_name = "ep92-hdmi";
  8887. break;
  8888. }
  8889. dai++;
  8890. }
  8891. /* update codec info in SPDIF dai link */
  8892. dai = &msm_spdif_be_dai_links[0];
  8893. for (i=0; i<ARRAY_SIZE(msm_spdif_be_dai_links); i++) {
  8894. if (strcmp(dai->name, LPASS_BE_SEC_SPDIF_TX) == 0) {
  8895. dev_dbg(&pdev->dev,
  8896. "%s: Set Sec SPDIF dai to ep92 codec\n",
  8897. __func__);
  8898. dai->codec_name = ep92_name;
  8899. dai->codec_dai_name = "ep92-arc";
  8900. break;
  8901. }
  8902. dai++;
  8903. }
  8904. return 0;
  8905. }
  8906. static int msm_asoc_machine_probe(struct platform_device *pdev)
  8907. {
  8908. struct snd_soc_card *card;
  8909. struct msm_asoc_mach_data *pdata;
  8910. int ret;
  8911. u32 val;
  8912. const char *micb_supply_str = "tdm-vdd-micb-supply";
  8913. const char *micb_supply_str1 = "tdm-vdd-micb";
  8914. const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage";
  8915. const char *micb_current_str = "qcom,tdm-vdd-micb-current";
  8916. u32 v_base_addr;
  8917. if (!pdev->dev.of_node) {
  8918. dev_err(&pdev->dev, "No platform supplied from device tree\n");
  8919. return -EINVAL;
  8920. }
  8921. pdata = devm_kzalloc(&pdev->dev,
  8922. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  8923. if (!pdata)
  8924. return -ENOMEM;
  8925. ret = of_property_read_u32(
  8926. pdev->dev.of_node, "tcsr_i2s_dsd_prim", &v_base_addr);
  8927. if (ret) {
  8928. dev_err(&pdev->dev, "MUX addr invalid for MI2S dsd prim\n");
  8929. } else {
  8930. pdata->mi2s_dsd_mode[PRIM_MI2S] =
  8931. devm_ioremap(&pdev->dev, v_base_addr, 4);
  8932. if (pdata->mi2s_dsd_mode[PRIM_MI2S] == NULL) {
  8933. pr_err("%s ioremap failure for muxsel virt addr dsd prim\n",
  8934. __func__);
  8935. }
  8936. }
  8937. ret = of_property_read_u32(
  8938. pdev->dev.of_node, "tcsr_i2s_dsd_quat", &v_base_addr);
  8939. if (ret) {
  8940. dev_err(&pdev->dev, "MUX addr invalid for MI2S dsd quat\n");
  8941. } else {
  8942. pdata->mi2s_dsd_mode[QUAT_MI2S] =
  8943. devm_ioremap(&pdev->dev, v_base_addr, 4);
  8944. if (pdata->mi2s_dsd_mode[QUAT_MI2S] == NULL) {
  8945. pr_err("%s ioremap failure for muxsel virt addr dsd quat\n",
  8946. __func__);
  8947. }
  8948. }
  8949. /* test for ep92 HDMI bridge and update dai links accordingly */
  8950. ret = msm_detect_ep92_dev(pdev, card);
  8951. if (ret)
  8952. goto err;
  8953. card = populate_snd_card_dailinks(&pdev->dev);
  8954. if (!card) {
  8955. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  8956. ret = -EINVAL;
  8957. goto err;
  8958. }
  8959. card->dev = &pdev->dev;
  8960. platform_set_drvdata(pdev, card);
  8961. snd_soc_card_set_drvdata(card, pdata);
  8962. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  8963. if (ret) {
  8964. dev_err(&pdev->dev, "parse card name failed, err:%d\n",
  8965. ret);
  8966. goto err;
  8967. }
  8968. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  8969. if (ret) {
  8970. dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
  8971. ret);
  8972. goto err;
  8973. }
  8974. ret = msm_populate_dai_link_component_of_node(card);
  8975. if (ret) {
  8976. ret = -EPROBE_DEFER;
  8977. goto err;
  8978. }
  8979. ret = of_property_read_u32(pdev->dev.of_node, "qcom,csra-codec", &val);
  8980. if (ret) {
  8981. dev_info(&pdev->dev, "no 'qcom,csra-codec' in DT\n");
  8982. val = 0;
  8983. }
  8984. if (val) {
  8985. pdata->codec_is_csra = true;
  8986. mi2s_rx_cfg[PRIM_MI2S].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  8987. meta_mi2s_rx_cfg[PRIM_META_MI2S].bit_format =
  8988. SNDRV_PCM_FORMAT_S24_LE;
  8989. ret = msm_init_csra_dev(pdev, card);
  8990. if (ret)
  8991. goto err;
  8992. } else {
  8993. pdata->codec_is_csra = false;
  8994. ret = msm_init_wsa_dev(pdev, card);
  8995. if (ret)
  8996. goto err;
  8997. }
  8998. pdata->dmic_01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  8999. "qcom,cdc-dmic01-gpios", 0);
  9000. pdata->dmic_23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  9001. "qcom,cdc-dmic23-gpios", 0);
  9002. pdata->dmic_45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  9003. "qcom,cdc-dmic45-gpios", 0);
  9004. pdata->dmic_67_gpio_p = of_parse_phandle(pdev->dev.of_node,
  9005. "qcom,cdc-dmic67-gpios", 0);
  9006. pdata->lineout_booster_gpio_p = of_parse_phandle(pdev->dev.of_node,
  9007. "qcom,lineout-booster-gpio", 0);
  9008. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  9009. "qcom,pri-mi2s-gpios", 0);
  9010. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  9011. "qcom,sec-mi2s-gpios", 0);
  9012. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  9013. "qcom,tert-mi2s-gpios", 0);
  9014. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  9015. "qcom,quat-mi2s-gpios", 0);
  9016. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  9017. "qcom,quin-mi2s-gpios", 0);
  9018. if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) {
  9019. pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev,
  9020. micb_supply_str1);
  9021. if (IS_ERR(pdata->tdm_micb_supply)) {
  9022. ret = PTR_ERR(pdata->tdm_micb_supply);
  9023. dev_err(&pdev->dev,
  9024. "%s:Failed to get micbias supply for TDM Mic %d\n",
  9025. __func__, ret);
  9026. }
  9027. ret = of_property_read_u32(pdev->dev.of_node,
  9028. micb_voltage_str,
  9029. &pdata->tdm_micb_voltage);
  9030. if (ret) {
  9031. dev_err(&pdev->dev,
  9032. "%s:Looking up %s property in node %s failed\n",
  9033. __func__, micb_voltage_str,
  9034. pdev->dev.of_node->full_name);
  9035. }
  9036. ret = of_property_read_u32(pdev->dev.of_node,
  9037. micb_current_str,
  9038. &pdata->tdm_micb_current);
  9039. if (ret) {
  9040. dev_err(&pdev->dev,
  9041. "%s:Looking up %s property in node %s failed\n",
  9042. __func__, micb_current_str,
  9043. pdev->dev.of_node->full_name);
  9044. }
  9045. }
  9046. ret = devm_snd_soc_register_card(&pdev->dev, card);
  9047. if (ret == -EPROBE_DEFER) {
  9048. if (codec_reg_done)
  9049. ret = -EINVAL;
  9050. goto err;
  9051. } else if (ret) {
  9052. dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
  9053. ret);
  9054. goto err;
  9055. }
  9056. dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
  9057. spdev = pdev;
  9058. ret = msm_mdf_mem_init();
  9059. if (ret)
  9060. dev_err(&pdev->dev, "msm_mdf_mem_init failed (%d)\n",
  9061. ret);
  9062. msm_i2s_auxpcm_init(pdev);
  9063. msm_meta_mi2s_init(pdev);
  9064. is_initial_boot = true;
  9065. return 0;
  9066. err:
  9067. return ret;
  9068. }
  9069. static int msm_asoc_machine_remove(struct platform_device *pdev)
  9070. {
  9071. audio_notifier_deregister("qcs405");
  9072. msm_i2s_auxpcm_deinit();
  9073. msm_mdf_mem_deinit();
  9074. return 0;
  9075. }
  9076. static struct platform_driver qcs405_asoc_machine_driver = {
  9077. .driver = {
  9078. .name = DRV_NAME,
  9079. .owner = THIS_MODULE,
  9080. .pm = &snd_soc_pm_ops,
  9081. .of_match_table = qcs405_asoc_machine_of_match,
  9082. .suppress_bind_attrs = true,
  9083. },
  9084. .probe = msm_asoc_machine_probe,
  9085. .remove = msm_asoc_machine_remove,
  9086. };
  9087. module_platform_driver(qcs405_asoc_machine_driver);
  9088. MODULE_DESCRIPTION("ALSA SoC QCS405 Machine driver");
  9089. MODULE_LICENSE("GPL v2");
  9090. MODULE_ALIAS("platform:" DRV_NAME);
  9091. MODULE_DEVICE_TABLE(of, qcs405_asoc_machine_of_match);