cvp_hfi.c 150 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <asm/memory.h>
  7. #include <linux/coresight-stm.h>
  8. #include <linux/delay.h>
  9. #include <linux/devfreq.h>
  10. #include <linux/hash.h>
  11. #include <linux/io.h>
  12. #include <linux/iommu.h>
  13. #include <linux/iopoll.h>
  14. #include <linux/of.h>
  15. #include <linux/pm_qos.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/slab.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/soc/qcom/llcc-qcom.h>
  21. #include <linux/qcom_scm.h>
  22. #include <linux/soc/qcom/smem.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/reset.h>
  25. #include <linux/pm_wakeup.h>
  26. #include "hfi_packetization.h"
  27. #include "msm_cvp_debug.h"
  28. #include "cvp_core_hfi.h"
  29. #include "cvp_hfi_helper.h"
  30. #include "cvp_hfi_io.h"
  31. #include "msm_cvp_dsp.h"
  32. #include "msm_cvp_clocks.h"
  33. #include "vm/cvp_vm.h"
  34. #include "cvp_dump.h"
  35. // ysi - added for debug
  36. #include <linux/clk/qcom.h>
  37. #include "msm_cvp_common.h"
  38. #define REG_ADDR_OFFSET_BITMASK 0x000FFFFF
  39. #define QDSS_IOVA_START 0x80001000
  40. #define MIN_PAYLOAD_SIZE 3
  41. struct cvp_tzbsp_memprot {
  42. u32 cp_start;
  43. u32 cp_size;
  44. u32 cp_nonpixel_start;
  45. u32 cp_nonpixel_size;
  46. };
  47. #define TZBSP_CVP_PAS_ID 26
  48. /* Poll interval in uS */
  49. #define POLL_INTERVAL_US 50
  50. enum tzbsp_subsys_state {
  51. TZ_SUBSYS_STATE_SUSPEND = 0,
  52. TZ_SUBSYS_STATE_RESUME = 1,
  53. TZ_SUBSYS_STATE_RESTORE_THRESHOLD = 2,
  54. };
  55. const struct msm_cvp_gov_data CVP_DEFAULT_BUS_VOTE = {
  56. .data = NULL,
  57. .data_count = 0,
  58. };
  59. const int cvp_max_packets = 32;
  60. static void iris_hfi_pm_handler(struct work_struct *work);
  61. static DECLARE_DELAYED_WORK(iris_hfi_pm_work, iris_hfi_pm_handler);
  62. static inline int __resume(struct iris_hfi_device *device);
  63. static inline int __suspend(struct iris_hfi_device *device);
  64. static int __disable_regulator(struct iris_hfi_device *device,
  65. const char *name);
  66. static int __enable_regulator(struct iris_hfi_device *device,
  67. const char *name);
  68. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet);
  69. static int __initialize_packetization(struct iris_hfi_device *device);
  70. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  71. u32 session_id);
  72. static bool __is_session_valid(struct iris_hfi_device *device,
  73. struct cvp_hal_session *session, const char *func);
  74. static int __iface_cmdq_write(struct iris_hfi_device *device,
  75. void *pkt);
  76. static int __load_fw(struct iris_hfi_device *device);
  77. static int __power_on_init(struct iris_hfi_device *device);
  78. static void __unload_fw(struct iris_hfi_device *device);
  79. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state);
  80. static int __enable_subcaches(struct iris_hfi_device *device);
  81. static int __set_subcaches(struct iris_hfi_device *device);
  82. static int __release_subcaches(struct iris_hfi_device *device);
  83. static int __disable_subcaches(struct iris_hfi_device *device);
  84. static int __power_collapse(struct iris_hfi_device *device, bool force);
  85. static int iris_hfi_noc_error_info(void *dev);
  86. static void interrupt_init_iris2(struct iris_hfi_device *device);
  87. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device);
  88. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device);
  89. static void power_off_iris2(struct iris_hfi_device *device);
  90. static int __set_ubwc_config(struct iris_hfi_device *device);
  91. static void __noc_error_info_iris2(struct iris_hfi_device *device);
  92. static int __enable_hw_power_collapse(struct iris_hfi_device *device);
  93. static int __disable_hw_power_collapse(struct iris_hfi_device *device);
  94. static int __power_off_controller(struct iris_hfi_device *device);
  95. static int __hwfence_regs_map(struct iris_hfi_device *device);
  96. static int __hwfence_regs_unmap(struct iris_hfi_device *device);
  97. static int __reset_control_assert_name(struct iris_hfi_device *device, const char *name);
  98. static int __reset_control_deassert_name(struct iris_hfi_device *device, const char *name);
  99. static int __reset_control_acquire(struct iris_hfi_device *device, const char *name);
  100. static int __reset_control_release(struct iris_hfi_device *device, const char *name);
  101. static bool __is_ctl_power_on(struct iris_hfi_device *device);
  102. static void __print_sidebandmanager_regs(struct iris_hfi_device *device);
  103. static void dump_noc_reg(struct iris_hfi_device *device);
  104. static struct cvp_hal_ops hal_ops = {
  105. .interrupt_init = interrupt_init_iris2,
  106. .setup_dsp_uc_memmap = setup_dsp_uc_memmap_vpu5,
  107. .clock_config_on_enable = clock_config_on_enable_vpu5,
  108. .power_off = power_off_iris2,
  109. .noc_error_info = __noc_error_info_iris2,
  110. .reset_control_assert_name = __reset_control_assert_name,
  111. .reset_control_deassert_name = __reset_control_deassert_name,
  112. .reset_control_acquire_name = __reset_control_acquire,
  113. .reset_control_release_name = __reset_control_release,
  114. };
  115. /**
  116. * Utility function to enforce some of our assumptions. Spam calls to this
  117. * in hotspots in code to double check some of the assumptions that we hold.
  118. */
  119. static inline void __strict_check(struct iris_hfi_device *device)
  120. {
  121. msm_cvp_res_handle_fatal_hw_error(device->res,
  122. !mutex_is_locked(&device->lock));
  123. }
  124. static inline void __set_state(struct iris_hfi_device *device,
  125. enum iris_hfi_state state)
  126. {
  127. device->state = state;
  128. }
  129. static inline bool __core_in_valid_state(struct iris_hfi_device *device)
  130. {
  131. return device->state != IRIS_STATE_DEINIT;
  132. }
  133. static inline bool is_sys_cache_present(struct iris_hfi_device *device)
  134. {
  135. return device->res->sys_cache_present;
  136. }
  137. static int cvp_synx_recover(void)
  138. {
  139. #ifdef CVP_SYNX_ENABLED
  140. return synx_recover(SYNX_CLIENT_EVA_CTX0);
  141. #else
  142. return 0;
  143. #endif /* End of CVP_SYNX_ENABLED */
  144. }
  145. #define ROW_SIZE 32
  146. unsigned long long get_aon_time(void)
  147. {
  148. unsigned long long val;
  149. asm volatile("mrs %0, cntvct_el0" : "=r" (val));
  150. return val;
  151. }
  152. int get_hfi_version(void)
  153. {
  154. struct msm_cvp_core *core;
  155. struct iris_hfi_device *hfi;
  156. core = cvp_driver->cvp_core;
  157. hfi = (struct iris_hfi_device *)core->dev_ops->hfi_device_data;
  158. return hfi->version;
  159. }
  160. unsigned int get_msg_size(struct cvp_hfi_msg_session_hdr *hdr)
  161. {
  162. struct msm_cvp_core *core;
  163. struct iris_hfi_device *device;
  164. u32 minor_ver;
  165. core = cvp_driver->cvp_core;
  166. if (core)
  167. device = core->dev_ops->hfi_device_data;
  168. else
  169. return 0;
  170. if (!device) {
  171. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  172. return 0;
  173. }
  174. minor_ver = (device->version & HFI_VERSION_MINOR_MASK) >>
  175. HFI_VERSION_MINOR_SHIFT;
  176. if (minor_ver < 2)
  177. return sizeof(struct cvp_hfi_msg_session_hdr);
  178. if (hdr->packet_type == HFI_MSG_SESSION_CVP_FD)
  179. return sizeof(struct cvp_hfi_msg_session_hdr_ext);
  180. else
  181. return sizeof(struct cvp_hfi_msg_session_hdr);
  182. }
  183. unsigned int get_msg_session_id(void *msg)
  184. {
  185. struct cvp_hfi_msg_session_hdr *hdr =
  186. (struct cvp_hfi_msg_session_hdr *)msg;
  187. return hdr->session_id;
  188. }
  189. unsigned int get_msg_errorcode(void *msg)
  190. {
  191. struct cvp_hfi_msg_session_hdr *hdr =
  192. (struct cvp_hfi_msg_session_hdr *)msg;
  193. return hdr->error_type;
  194. }
  195. int get_msg_opconfigs(void *msg, unsigned int *session_id,
  196. unsigned int *error_type, unsigned int *config_id)
  197. {
  198. struct cvp_hfi_msg_session_op_cfg_packet *cfg =
  199. (struct cvp_hfi_msg_session_op_cfg_packet *)msg;
  200. *session_id = cfg->session_id;
  201. *error_type = cfg->error_type;
  202. *config_id = cfg->op_conf_id;
  203. return 0;
  204. }
  205. static void __dump_packet(u8 *packet, enum cvp_msg_prio log_level)
  206. {
  207. u32 c = 0, packet_size = *(u32 *)packet;
  208. /*
  209. * row must contain enough for 0xdeadbaad * 8 to be converted into
  210. * "de ad ba ab " * 8 + '\0'
  211. */
  212. char row[3 * ROW_SIZE];
  213. for (c = 0; c * ROW_SIZE < packet_size; ++c) {
  214. int bytes_to_read = ((c + 1) * ROW_SIZE > packet_size) ?
  215. packet_size % ROW_SIZE : ROW_SIZE;
  216. hex_dump_to_buffer(packet + c * ROW_SIZE, bytes_to_read,
  217. ROW_SIZE, 4, row, sizeof(row), false);
  218. dprintk(log_level, "%s\n", row);
  219. }
  220. }
  221. static int __dsp_suspend(struct iris_hfi_device *device, bool force)
  222. {
  223. int rc;
  224. if (msm_cvp_dsp_disable)
  225. return 0;
  226. dprintk(CVP_DSP, "%s: suspend dsp\n", __func__);
  227. rc = cvp_dsp_suspend(force);
  228. if (rc) {
  229. if (rc != -EBUSY)
  230. dprintk(CVP_ERR,
  231. "%s: dsp suspend failed with error %d\n",
  232. __func__, rc);
  233. return rc;
  234. }
  235. dprintk(CVP_DSP, "%s: dsp suspended\n", __func__);
  236. return 0;
  237. }
  238. static int __dsp_resume(struct iris_hfi_device *device)
  239. {
  240. int rc;
  241. if (msm_cvp_dsp_disable)
  242. return 0;
  243. dprintk(CVP_DSP, "%s: resume dsp\n", __func__);
  244. rc = cvp_dsp_resume();
  245. if (rc) {
  246. dprintk(CVP_ERR,
  247. "%s: dsp resume failed with error %d\n",
  248. __func__, rc);
  249. return rc;
  250. }
  251. dprintk(CVP_DSP, "%s: dsp resumed\n", __func__);
  252. return rc;
  253. }
  254. static int __dsp_shutdown(struct iris_hfi_device *device)
  255. {
  256. int rc;
  257. if (msm_cvp_dsp_disable)
  258. return 0;
  259. dprintk(CVP_DSP, "%s: shutdown dsp\n", __func__);
  260. rc = cvp_dsp_shutdown();
  261. if (rc) {
  262. dprintk(CVP_ERR,
  263. "%s: dsp shutdown failed with error %d\n",
  264. __func__, rc);
  265. WARN_ON(1);
  266. }
  267. dprintk(CVP_DSP, "%s: dsp shutdown successful\n", __func__);
  268. return rc;
  269. }
  270. static int __acquire_regulator(struct regulator_info *rinfo,
  271. struct iris_hfi_device *device)
  272. {
  273. int rc = 0;
  274. if (rinfo->has_hw_power_collapse) {
  275. /*Acquire XO_RESET to avoid race condition with video*/
  276. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  277. if (rc) {
  278. dprintk(CVP_ERR,
  279. "XO_RESET could not be acquired: skip acquiring the regulator %s from FW\n",
  280. rinfo->name);
  281. return -EINVAL;
  282. }
  283. rc = regulator_set_mode(rinfo->regulator,
  284. REGULATOR_MODE_NORMAL);
  285. if (rc) {
  286. /*
  287. * This is somewhat fatal, but nothing we can do
  288. * about it. We can't disable the regulator w/o
  289. * getting it back under s/w control
  290. */
  291. dprintk(CVP_WARN,
  292. "Failed to acquire regulator control: %s\n",
  293. rinfo->name);
  294. } else {
  295. dprintk(CVP_PWR,
  296. "Acquire regulator control from HW: %s\n",
  297. rinfo->name);
  298. }
  299. /*Release XO_RESET after regulator is enabled.*/
  300. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  301. }
  302. if (!regulator_is_enabled(rinfo->regulator)) {
  303. dprintk(CVP_WARN, "Regulator is not enabled %s\n",
  304. rinfo->name);
  305. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  306. }
  307. return rc;
  308. }
  309. static int __hand_off_regulator(struct iris_hfi_device *device, struct regulator_info *rinfo)
  310. {
  311. int rc = 0;
  312. if (rinfo->has_hw_power_collapse) {
  313. /*Acquire XO_RESET to avoid race condition with video*/
  314. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  315. if (rc) {
  316. dprintk(CVP_ERR,
  317. "XO_RESET could not be acquired: skip hand off the regulator %s to FW\n",
  318. rinfo->name);
  319. return -EINVAL;
  320. }
  321. rc = regulator_set_mode(rinfo->regulator,
  322. REGULATOR_MODE_FAST);
  323. /*Release XO_RESET after regulator is enabled.*/
  324. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  325. if (rc) {
  326. dprintk(CVP_WARN,
  327. "Failed to hand off regulator control: %s\n",
  328. rinfo->name);
  329. } else {
  330. dprintk(CVP_PWR,
  331. "Hand off regulator control to HW: %s\n",
  332. rinfo->name);
  333. }
  334. }
  335. return rc;
  336. }
  337. static int __hand_off_regulators(struct iris_hfi_device *device)
  338. {
  339. struct regulator_info *rinfo;
  340. int rc = 0, c = 0;
  341. iris_hfi_for_each_regulator(device, rinfo) {
  342. rc = __hand_off_regulator(device, rinfo);
  343. /*
  344. * If one regulator hand off failed, driver should take
  345. * the control for other regulators back.
  346. */
  347. if (rc)
  348. goto err_reg_handoff_failed;
  349. c++;
  350. }
  351. return rc;
  352. err_reg_handoff_failed:
  353. iris_hfi_for_each_regulator_reverse_continue(device, rinfo, c)
  354. __acquire_regulator(rinfo, device);
  355. return rc;
  356. }
  357. static int __take_back_regulators(struct iris_hfi_device *device)
  358. {
  359. struct regulator_info *rinfo;
  360. int rc = 0;
  361. iris_hfi_for_each_regulator(device, rinfo) {
  362. rc = __acquire_regulator(rinfo, device);
  363. /*
  364. * if one regulator hand off failed, driver should take
  365. * the control for other regulators back.
  366. */
  367. if (rc)
  368. return rc;
  369. }
  370. return rc;
  371. }
  372. static int __write_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  373. bool *rx_req_is_set)
  374. {
  375. struct cvp_hfi_queue_header *queue;
  376. struct cvp_hfi_cmd_session_hdr *cmd_pkt;
  377. u32 packet_size_in_words, new_write_idx;
  378. u32 empty_space, read_idx, write_idx;
  379. u32 *write_ptr;
  380. if (!qinfo || !packet) {
  381. dprintk(CVP_ERR, "Invalid Params\n");
  382. return -EINVAL;
  383. } else if (!qinfo->q_array.align_virtual_addr) {
  384. dprintk(CVP_WARN, "Queues have already been freed\n");
  385. return -EINVAL;
  386. }
  387. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  388. if (!queue) {
  389. dprintk(CVP_ERR, "queue not present\n");
  390. return -ENOENT;
  391. }
  392. cmd_pkt = (struct cvp_hfi_cmd_session_hdr *)packet;
  393. if (cmd_pkt->size >= sizeof(struct cvp_hfi_cmd_session_hdr))
  394. dprintk(CVP_CMD, "%s: pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  395. __func__, cmd_pkt->packet_type,
  396. cmd_pkt->session_id,
  397. cmd_pkt->client_data.transaction_id,
  398. cmd_pkt->client_data.kdata & (FENCE_BIT - 1));
  399. else if (cmd_pkt->size >= 12)
  400. dprintk(CVP_CMD, "%s: pkt_type %08x sess_id %08x\n", __func__,
  401. cmd_pkt->packet_type, cmd_pkt->session_id);
  402. if (msm_cvp_debug & CVP_PKT) {
  403. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  404. __dump_packet(packet, CVP_PKT);
  405. }
  406. packet_size_in_words = (*(u32 *)packet) >> 2;
  407. if (!packet_size_in_words || packet_size_in_words >
  408. qinfo->q_array.mem_size>>2) {
  409. dprintk(CVP_ERR, "Invalid packet size\n");
  410. return -ENODATA;
  411. }
  412. spin_lock(&qinfo->hfi_lock);
  413. read_idx = queue->qhdr_read_idx;
  414. write_idx = queue->qhdr_write_idx;
  415. empty_space = (write_idx >= read_idx) ?
  416. ((qinfo->q_array.mem_size>>2) - (write_idx - read_idx)) :
  417. (read_idx - write_idx);
  418. if (empty_space <= packet_size_in_words) {
  419. queue->qhdr_tx_req = 1;
  420. spin_unlock(&qinfo->hfi_lock);
  421. dprintk(CVP_ERR, "Insufficient size (%d) to write (%d)\n",
  422. empty_space, packet_size_in_words);
  423. return -ENOTEMPTY;
  424. }
  425. queue->qhdr_tx_req = 0;
  426. new_write_idx = write_idx + packet_size_in_words;
  427. write_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  428. (write_idx << 2));
  429. if (write_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  430. write_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  431. qinfo->q_array.mem_size)) {
  432. spin_unlock(&qinfo->hfi_lock);
  433. dprintk(CVP_ERR, "Invalid write index\n");
  434. return -ENODATA;
  435. }
  436. if (new_write_idx < (qinfo->q_array.mem_size >> 2)) {
  437. memcpy(write_ptr, packet, packet_size_in_words << 2);
  438. } else {
  439. new_write_idx -= qinfo->q_array.mem_size >> 2;
  440. memcpy(write_ptr, packet, (packet_size_in_words -
  441. new_write_idx) << 2);
  442. memcpy((void *)qinfo->q_array.align_virtual_addr,
  443. packet + ((packet_size_in_words - new_write_idx) << 2),
  444. new_write_idx << 2);
  445. }
  446. /*
  447. * Memory barrier to make sure packet is written before updating the
  448. * write index
  449. */
  450. mb();
  451. queue->qhdr_write_idx = new_write_idx;
  452. if (rx_req_is_set)
  453. *rx_req_is_set = queue->qhdr_rx_req == 1;
  454. /*
  455. * Memory barrier to make sure write index is updated before an
  456. * interrupt is raised.
  457. */
  458. mb();
  459. spin_unlock(&qinfo->hfi_lock);
  460. return 0;
  461. }
  462. static int __read_queue(struct cvp_iface_q_info *qinfo, u8 *packet,
  463. u32 *pb_tx_req_is_set)
  464. {
  465. struct cvp_hfi_queue_header *queue;
  466. struct cvp_hfi_msg_session_hdr *msg_pkt;
  467. u32 packet_size_in_words, new_read_idx;
  468. u32 *read_ptr;
  469. u32 receive_request = 0;
  470. u32 read_idx, write_idx;
  471. int rc = 0;
  472. if (!qinfo || !packet || !pb_tx_req_is_set) {
  473. dprintk(CVP_ERR, "Invalid Params\n");
  474. return -EINVAL;
  475. } else if (!qinfo->q_array.align_virtual_addr) {
  476. dprintk(CVP_WARN, "Queues have already been freed\n");
  477. return -EINVAL;
  478. }
  479. /*
  480. * Memory barrier to make sure data is valid before
  481. *reading it
  482. */
  483. mb();
  484. queue = (struct cvp_hfi_queue_header *) qinfo->q_hdr;
  485. if (!queue) {
  486. dprintk(CVP_ERR, "Queue memory is not allocated\n");
  487. return -ENOMEM;
  488. }
  489. /*
  490. * Do not set receive request for debug queue, if set,
  491. * Iris generates interrupt for debug messages even
  492. * when there is no response message available.
  493. * In general debug queue will not become full as it
  494. * is being emptied out for every interrupt from Iris.
  495. * Iris will anyway generates interrupt if it is full.
  496. */
  497. spin_lock(&qinfo->hfi_lock);
  498. if (queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_MSG_Q)
  499. receive_request = 1;
  500. read_idx = queue->qhdr_read_idx;
  501. write_idx = queue->qhdr_write_idx;
  502. if (read_idx == write_idx) {
  503. queue->qhdr_rx_req = receive_request;
  504. /*
  505. * mb() to ensure qhdr is updated in main memory
  506. * so that iris reads the updated header values
  507. */
  508. mb();
  509. *pb_tx_req_is_set = 0;
  510. if (write_idx != queue->qhdr_write_idx) {
  511. queue->qhdr_rx_req = 0;
  512. } else {
  513. spin_unlock(&qinfo->hfi_lock);
  514. dprintk(CVP_HFI,
  515. "%s queue is empty, rx_req = %u, tx_req = %u, read_idx = %u\n",
  516. receive_request ? "message" : "debug",
  517. queue->qhdr_rx_req, queue->qhdr_tx_req,
  518. queue->qhdr_read_idx);
  519. return -ENODATA;
  520. }
  521. }
  522. read_ptr = (u32 *)((qinfo->q_array.align_virtual_addr) +
  523. (read_idx << 2));
  524. if (read_ptr < (u32 *)qinfo->q_array.align_virtual_addr ||
  525. read_ptr > (u32 *)(qinfo->q_array.align_virtual_addr +
  526. qinfo->q_array.mem_size - sizeof(*read_ptr))) {
  527. spin_unlock(&qinfo->hfi_lock);
  528. dprintk(CVP_ERR, "Invalid read index\n");
  529. return -ENODATA;
  530. }
  531. packet_size_in_words = (*read_ptr) >> 2;
  532. if (!packet_size_in_words) {
  533. spin_unlock(&qinfo->hfi_lock);
  534. dprintk(CVP_ERR, "Zero packet size\n");
  535. return -ENODATA;
  536. }
  537. new_read_idx = read_idx + packet_size_in_words;
  538. if (((packet_size_in_words << 2) <= CVP_IFACEQ_VAR_HUGE_PKT_SIZE)
  539. && read_idx <= (qinfo->q_array.mem_size >> 2)) {
  540. if (new_read_idx < (qinfo->q_array.mem_size >> 2)) {
  541. memcpy(packet, read_ptr,
  542. packet_size_in_words << 2);
  543. } else {
  544. new_read_idx -= (qinfo->q_array.mem_size >> 2);
  545. memcpy(packet, read_ptr,
  546. (packet_size_in_words - new_read_idx) << 2);
  547. memcpy(packet + ((packet_size_in_words -
  548. new_read_idx) << 2),
  549. (u8 *)qinfo->q_array.align_virtual_addr,
  550. new_read_idx << 2);
  551. }
  552. } else {
  553. dprintk(CVP_WARN,
  554. "BAD packet received, read_idx: %#x, pkt_size: %d\n",
  555. read_idx, packet_size_in_words << 2);
  556. dprintk(CVP_WARN, "Dropping this packet\n");
  557. new_read_idx = write_idx;
  558. rc = -ENODATA;
  559. }
  560. if (new_read_idx != queue->qhdr_write_idx)
  561. queue->qhdr_rx_req = 0;
  562. else
  563. queue->qhdr_rx_req = receive_request;
  564. queue->qhdr_read_idx = new_read_idx;
  565. /*
  566. * mb() to ensure qhdr is updated in main memory
  567. * so that iris reads the updated header values
  568. */
  569. mb();
  570. *pb_tx_req_is_set = (queue->qhdr_tx_req == 1) ? 1 : 0;
  571. spin_unlock(&qinfo->hfi_lock);
  572. if (!(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  573. msg_pkt = (struct cvp_hfi_msg_session_hdr *)packet;
  574. dprintk(CVP_CMD, "%s: "
  575. "pkt_type %08x sess_id %08x trans_id %u ktid %llu\n",
  576. __func__, msg_pkt->packet_type,
  577. msg_pkt->session_id,
  578. msg_pkt->client_data.transaction_id,
  579. msg_pkt->client_data.kdata & (FENCE_BIT - 1));
  580. }
  581. if ((msm_cvp_debug & CVP_PKT) &&
  582. !(queue->qhdr_type & HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q)) {
  583. dprintk(CVP_PKT, "%s: %pK\n", __func__, qinfo);
  584. __dump_packet(packet, CVP_PKT);
  585. }
  586. return rc;
  587. }
  588. static int __smem_alloc(struct iris_hfi_device *dev, struct cvp_mem_addr *mem,
  589. u32 size, u32 align, u32 flags)
  590. {
  591. struct msm_cvp_smem *alloc = &mem->mem_data;
  592. int rc = 0;
  593. if (!dev || !mem || !size) {
  594. dprintk(CVP_ERR, "Invalid Params\n");
  595. return -EINVAL;
  596. }
  597. dprintk(CVP_INFO, "start to alloc size: %d, flags: %d\n", size, flags);
  598. alloc->flags = flags;
  599. rc = msm_cvp_smem_alloc(size, align, 1, (void *)dev->res, alloc);
  600. if (rc) {
  601. dprintk(CVP_ERR, "Alloc failed\n");
  602. rc = -ENOMEM;
  603. goto fail_smem_alloc;
  604. }
  605. dprintk(CVP_MEM, "%s: ptr = %pK, size = %d\n", __func__,
  606. alloc->kvaddr, size);
  607. mem->mem_size = alloc->size;
  608. mem->align_virtual_addr = alloc->kvaddr;
  609. mem->align_device_addr = alloc->device_addr;
  610. alloc->pkt_type = 0;
  611. alloc->buf_idx = 0;
  612. return rc;
  613. fail_smem_alloc:
  614. return rc;
  615. }
  616. static void __smem_free(struct iris_hfi_device *dev, struct msm_cvp_smem *mem)
  617. {
  618. if (!dev || !mem) {
  619. dprintk(CVP_ERR, "invalid param %pK %pK\n", dev, mem);
  620. return;
  621. }
  622. msm_cvp_smem_free(mem);
  623. }
  624. static void __write_register(struct iris_hfi_device *device,
  625. u32 reg, u32 value)
  626. {
  627. u32 hwiosymaddr = reg;
  628. u8 *base_addr;
  629. if (!device) {
  630. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  631. return;
  632. }
  633. __strict_check(device);
  634. if (!device->power_enabled) {
  635. dprintk(CVP_WARN,
  636. "HFI Write register failed : Power is OFF\n");
  637. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  638. return;
  639. }
  640. base_addr = device->cvp_hal_data->register_base;
  641. dprintk(CVP_REG, "Base addr: %pK, written to: %#x, Value: %#x...\n",
  642. base_addr, hwiosymaddr, value);
  643. base_addr += hwiosymaddr;
  644. writel_relaxed(value, base_addr);
  645. /*
  646. * Memory barrier to make sure value is written into the register.
  647. */
  648. wmb();
  649. }
  650. static int __read_gcc_register(struct iris_hfi_device *device, u32 reg)
  651. {
  652. int rc = 0;
  653. u8 *base_addr;
  654. if (!device) {
  655. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  656. return -EINVAL;
  657. }
  658. __strict_check(device);
  659. if (!device->power_enabled) {
  660. dprintk(CVP_WARN,
  661. "%s HFI Read register failed : Power is OFF\n",
  662. __func__);
  663. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  664. return -EINVAL;
  665. }
  666. base_addr = device->cvp_hal_data->gcc_reg_base;
  667. rc = readl_relaxed(base_addr + reg);
  668. /*
  669. * Memory barrier to make sure value is read correctly from the
  670. * register.
  671. */
  672. rmb();
  673. dprintk(CVP_REG,
  674. "GCC Base addr: %pK, read from: %#x, value: %#x...\n",
  675. base_addr, reg, rc);
  676. return rc;
  677. }
  678. static int __read_register(struct iris_hfi_device *device, u32 reg)
  679. {
  680. int rc = 0;
  681. u8 *base_addr;
  682. if (!device) {
  683. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  684. return -EINVAL;
  685. }
  686. __strict_check(device);
  687. if (!device->power_enabled) {
  688. dprintk(CVP_WARN,
  689. "HFI Read register failed : Power is OFF\n");
  690. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  691. return -EINVAL;
  692. }
  693. base_addr = device->cvp_hal_data->register_base;
  694. rc = readl_relaxed(base_addr + reg);
  695. /*
  696. * Memory barrier to make sure value is read correctly from the
  697. * register.
  698. */
  699. rmb();
  700. dprintk(CVP_REG, "Base addr: %pK, read from: %#x, value: %#x...\n",
  701. base_addr, reg, rc);
  702. return rc;
  703. }
  704. static bool __is_ctl_power_on(struct iris_hfi_device *device)
  705. {
  706. u32 reg;
  707. reg = __read_register(device, CVP_CC_MVS1C_GDSCR);
  708. if (!(reg & 0x80000000))
  709. return false;
  710. reg = __read_register(device, CVP_CC_MVS1C_CBCR);
  711. if (reg & 0x80000000)
  712. return false;
  713. return true;
  714. }
  715. static int __set_registers(struct iris_hfi_device *device)
  716. {
  717. struct msm_cvp_core *core;
  718. struct msm_cvp_platform_data *pdata;
  719. struct reg_set *reg_set;
  720. int i;
  721. if (!device->res) {
  722. dprintk(CVP_ERR,
  723. "device resources null, cannot set registers\n");
  724. return -EINVAL ;
  725. }
  726. core = cvp_driver->cvp_core;
  727. pdata = core->platform_data;
  728. reg_set = &device->res->reg_set;
  729. for (i = 0; i < reg_set->count; i++) {
  730. __write_register(device, reg_set->reg_tbl[i].reg,
  731. reg_set->reg_tbl[i].value);
  732. dprintk(CVP_REG, "write_reg offset=%x, val=%x\n",
  733. reg_set->reg_tbl[i].reg,
  734. reg_set->reg_tbl[i].value);
  735. }
  736. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  737. if (i) {
  738. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  739. return -EINVAL;
  740. }
  741. __write_register(device, CVP_CPU_CS_AXI4_QOS,
  742. pdata->noc_qos->axi_qos);
  743. __write_register(device,
  744. CVP_NOC_RGE_PRIORITYLUT_LOW +
  745. device->res->qos_noc_rge_niu_offset,
  746. pdata->noc_qos->prioritylut_low);
  747. __write_register(device,
  748. CVP_NOC_RGE_PRIORITYLUT_HIGH +
  749. device->res->qos_noc_rge_niu_offset,
  750. pdata->noc_qos->prioritylut_high);
  751. __write_register(device,
  752. CVP_NOC_RGE_URGENCY_LOW +
  753. device->res->qos_noc_rge_niu_offset,
  754. pdata->noc_qos->urgency_low);
  755. __write_register(device,
  756. CVP_NOC_RGE_DANGERLUT_LOW +
  757. device->res->qos_noc_rge_niu_offset,
  758. pdata->noc_qos->dangerlut_low);
  759. __write_register(device,
  760. CVP_NOC_RGE_SAFELUT_LOW +
  761. device->res->qos_noc_rge_niu_offset,
  762. pdata->noc_qos->safelut_low);
  763. __write_register(device,
  764. CVP_NOC_GCE_PRIORITYLUT_LOW +
  765. device->res->qos_noc_gce_vadl_tof_niu_offset,
  766. pdata->noc_qos->prioritylut_low);
  767. __write_register(device,
  768. CVP_NOC_GCE_PRIORITYLUT_HIGH +
  769. device->res->qos_noc_gce_vadl_tof_niu_offset,
  770. pdata->noc_qos->prioritylut_high);
  771. __write_register(device,
  772. CVP_NOC_GCE_URGENCY_LOW +
  773. device->res->qos_noc_gce_vadl_tof_niu_offset,
  774. pdata->noc_qos->urgency_low);
  775. __write_register(device,
  776. CVP_NOC_GCE_DANGERLUT_LOW +
  777. device->res->qos_noc_gce_vadl_tof_niu_offset,
  778. pdata->noc_qos->dangerlut_low);
  779. __write_register(device,
  780. CVP_NOC_GCE_SAFELUT_LOW +
  781. device->res->qos_noc_gce_vadl_tof_niu_offset,
  782. pdata->noc_qos->safelut_low);
  783. __write_register(device,
  784. CVP_NOC_CDM_PRIORITYLUT_LOW +
  785. device->res->qos_noc_cdm_niu_offset,
  786. pdata->noc_qos->prioritylut_low);
  787. __write_register(device,
  788. CVP_NOC_CDM_PRIORITYLUT_HIGH +
  789. device->res->qos_noc_cdm_niu_offset,
  790. pdata->noc_qos->prioritylut_high);
  791. __write_register(device,
  792. CVP_NOC_CDM_URGENCY_LOW +
  793. device->res->qos_noc_cdm_niu_offset,
  794. pdata->noc_qos->urgency_low_ro);
  795. __write_register(device,
  796. CVP_NOC_CDM_DANGERLUT_LOW +
  797. device->res->qos_noc_cdm_niu_offset,
  798. pdata->noc_qos->dangerlut_low);
  799. __write_register(device,
  800. CVP_NOC_CDM_SAFELUT_LOW +
  801. device->res->qos_noc_cdm_niu_offset,
  802. pdata->noc_qos->safelut_low);
  803. /* Below registers write moved from FW to SW to enable UBWC */
  804. __write_register(device,
  805. CVP_NOC_RGE_NIU_DECCTL_LOW +
  806. device->res->qos_noc_rge_niu_offset,
  807. 0x1);
  808. __write_register(device,
  809. CVP_NOC_RGE_NIU_ENCCTL_LOW +
  810. device->res->qos_noc_rge_niu_offset,
  811. 0x1);
  812. __write_register(device,
  813. CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW +
  814. device->res->qos_noc_gce_vadl_tof_niu_offset,
  815. 0x1);
  816. __write_register(device,
  817. CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW +
  818. device->res->qos_noc_gce_vadl_tof_niu_offset,
  819. 0x1);
  820. __write_register(device,
  821. CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS +
  822. device->res->noc_core_err_offset,
  823. 0x3);
  824. __write_register(device,
  825. CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW +
  826. device->res->noc_main_sidebandmanager_offset,
  827. 0x1);
  828. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  829. return 0;
  830. }
  831. /*
  832. * The existence of this function is a hack for 8996 (or certain Iris versions)
  833. * to overcome a hardware bug. Whenever the GDSCs momentarily power collapse
  834. * (after calling __hand_off_regulators()), the values of the threshold
  835. * registers (typically programmed by TZ) are incorrectly reset. As a result
  836. * reprogram these registers at certain agreed upon points.
  837. */
  838. static void __set_threshold_registers(struct iris_hfi_device *device)
  839. {
  840. u32 version = __read_register(device, CVP_WRAPPER_HW_VERSION);
  841. version &= ~GENMASK(15, 0);
  842. if (version != (0x3 << 28 | 0x43 << 16))
  843. return;
  844. if (__tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESTORE_THRESHOLD))
  845. dprintk(CVP_ERR, "Failed to restore threshold values\n");
  846. }
  847. static int __unvote_buses(struct iris_hfi_device *device)
  848. {
  849. int rc = 0;
  850. struct bus_info *bus = NULL;
  851. kfree(device->bus_vote.data);
  852. device->bus_vote.data = NULL;
  853. device->bus_vote.data_count = 0;
  854. iris_hfi_for_each_bus(device, bus) {
  855. rc = cvp_set_bw(bus, 0);
  856. if (rc) {
  857. dprintk(CVP_ERR,
  858. "%s: Failed unvoting bus\n", __func__);
  859. goto err_unknown_device;
  860. }
  861. }
  862. err_unknown_device:
  863. return rc;
  864. }
  865. static int __vote_buses(struct iris_hfi_device *device,
  866. struct cvp_bus_vote_data *data, int num_data)
  867. {
  868. int rc = 0;
  869. struct bus_info *bus = NULL;
  870. struct cvp_bus_vote_data *new_data = NULL;
  871. if (!num_data) {
  872. dprintk(CVP_PWR, "No vote data available\n");
  873. goto no_data_count;
  874. } else if (!data) {
  875. dprintk(CVP_ERR, "Invalid voting data\n");
  876. return -EINVAL;
  877. }
  878. new_data = kmemdup(data, num_data * sizeof(*new_data), GFP_KERNEL);
  879. if (!new_data) {
  880. dprintk(CVP_ERR, "Can't alloc memory to cache bus votes\n");
  881. rc = -ENOMEM;
  882. goto err_no_mem;
  883. }
  884. no_data_count:
  885. kfree(device->bus_vote.data);
  886. device->bus_vote.data = new_data;
  887. device->bus_vote.data_count = num_data;
  888. iris_hfi_for_each_bus(device, bus) {
  889. if (bus) {
  890. rc = cvp_set_bw(bus, bus->range[1]);
  891. if (rc)
  892. dprintk(CVP_ERR,
  893. "Failed voting bus %s to ab %u\n",
  894. bus->name, bus->range[1]*1000);
  895. }
  896. }
  897. err_no_mem:
  898. return rc;
  899. }
  900. static int iris_hfi_vote_buses(void *dev, struct bus_info *bus, unsigned long bw)
  901. {
  902. int rc = 0;
  903. struct iris_hfi_device *device = dev;
  904. if (!device)
  905. return -EINVAL;
  906. mutex_lock(&device->lock);
  907. rc = cvp_set_bw(bus, bw);
  908. mutex_unlock(&device->lock);
  909. return rc;
  910. }
  911. static int __core_set_resource(struct iris_hfi_device *device,
  912. struct cvp_resource_hdr *resource_hdr, void *resource_value)
  913. {
  914. struct cvp_hfi_cmd_sys_set_resource_packet *pkt;
  915. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  916. int rc = 0;
  917. if (!device || !resource_hdr || !resource_value) {
  918. dprintk(CVP_ERR, "set_res: Invalid Params\n");
  919. return -EINVAL;
  920. }
  921. pkt = (struct cvp_hfi_cmd_sys_set_resource_packet *) packet;
  922. rc = call_hfi_pkt_op(device, sys_set_resource,
  923. pkt, resource_hdr, resource_value);
  924. if (rc) {
  925. dprintk(CVP_ERR, "set_res: failed to create packet\n");
  926. goto err_create_pkt;
  927. }
  928. rc = __iface_cmdq_write(device, pkt);
  929. if (rc)
  930. rc = -ENOTEMPTY;
  931. err_create_pkt:
  932. return rc;
  933. }
  934. static int __core_release_resource(struct iris_hfi_device *device,
  935. struct cvp_resource_hdr *resource_hdr)
  936. {
  937. struct cvp_hfi_cmd_sys_release_resource_packet *pkt;
  938. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  939. int rc = 0;
  940. if (!device || !resource_hdr) {
  941. dprintk(CVP_ERR, "release_res: Invalid Params\n");
  942. return -EINVAL;
  943. }
  944. pkt = (struct cvp_hfi_cmd_sys_release_resource_packet *) packet;
  945. rc = call_hfi_pkt_op(device, sys_release_resource,
  946. pkt, resource_hdr);
  947. if (rc) {
  948. dprintk(CVP_ERR, "release_res: failed to create packet\n");
  949. goto err_create_pkt;
  950. }
  951. rc = __iface_cmdq_write(device, pkt);
  952. if (rc)
  953. rc = -ENOTEMPTY;
  954. err_create_pkt:
  955. return rc;
  956. }
  957. static int __tzbsp_set_cvp_state(enum tzbsp_subsys_state state)
  958. {
  959. int rc = 0;
  960. rc = qcom_scm_set_remote_state(state, TZBSP_CVP_PAS_ID);
  961. dprintk(CVP_CORE, "Set state %d, resp %d\n", state, rc);
  962. if (rc) {
  963. dprintk(CVP_ERR, "Failed qcom_scm_set_remote_state %d\n", rc);
  964. return rc;
  965. }
  966. return 0;
  967. }
  968. /*
  969. * Based on fal10_veto, X2RPMh, core_pwr_on and PWAitMode value, infer
  970. * value of xtss_sw_reset. xtss_sw_reset is a TZ register bit. Driver
  971. * cannot access it directly.
  972. *
  973. * In __boot_firmware() function, the caller of this function. It checks
  974. * "core_pwr_on" == false, basically core powered off. So this function
  975. * doesn't check core_pwr_on. Assume core_pwr_on = false.
  976. *
  977. * fal10_veto = VPU_CPU_CS_X2RPMh[2] |
  978. * ( ~VPU_CPU_CS_X2RPMh[1] & core_pwr_on ) |
  979. * ( ~VPU_CPU_CS_X2RPMh[0] & ~( xtss_sw_reset | PWaitMode ) ) ;
  980. */
  981. static inline void check_tensilica_in_reset(struct iris_hfi_device *device)
  982. {
  983. u32 X2RPMh, fal10_veto, wait_mode;
  984. X2RPMh = __read_register(device, CVP_CPU_CS_X2RPMh);
  985. X2RPMh = X2RPMh & 0x7;
  986. /* wait_mode = 1: Tensilica is in WFI mode (PWaitMode = true) */
  987. wait_mode = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  988. wait_mode = wait_mode & 0x1;
  989. fal10_veto = __read_register(device, CVP_CPU_CS_X2RPMh_STATUS);
  990. fal10_veto = fal10_veto & 0x1;
  991. dprintk(CVP_WARN, "tensilica reset check %#x %#x %#x\n",
  992. X2RPMh, wait_mode, fal10_veto);
  993. }
  994. static const char boot_states[0x40][32] = {
  995. "NOT INIT",
  996. "RST_START",
  997. "INIT_MEMCTL",
  998. "INTENABLE_RST",
  999. "LITBASE_RST",
  1000. "PREFETCH_EN",
  1001. "MPU_INIT",
  1002. "CTRL_INIT_READ",
  1003. "MEMCTL_L1_FIX",
  1004. "RESTORE_EXTRA_NW",
  1005. "CORE_RESTORE",
  1006. "COLD_BOOT",
  1007. "DISABLE_CACHE",
  1008. "BEFORE_MPU_C",
  1009. "RET_MPU_C",
  1010. "IN_MPU_C",
  1011. "IN_MPU_DEFAULT",
  1012. "IN_MPU_SYNX",
  1013. "UCR_SIZE_FAIL",
  1014. "UCR_ADDR_FAIL",
  1015. "UCR1_SIZE_FAIL",
  1016. "UCR1_ADDR_FAIL",
  1017. "UCR_OVERLAPPED_UCR1",
  1018. "UCR1_OVERLAPPED_UCR",
  1019. "UCR_EQ_UCR1",
  1020. "MPU_CHECK_DONE",
  1021. "BEFORE_INT_LOCK",
  1022. "AFTER_INT_LOCK",
  1023. "BEFORE_INT_UNLOCK",
  1024. "AFTER_INT_UNLOCK",
  1025. "CALL_START",
  1026. "MAIN_ENTRY",
  1027. "VENUS_INIT_ENTRY",
  1028. "VSYS_INIT_ENTRY",
  1029. "BEFORE_XOS_CLK",
  1030. "AFTER_XOS_CLK",
  1031. "LOG_MUTEX_INIT",
  1032. "CREATE_FRAMEWORK_ENTRY",
  1033. "DTG_INIT",
  1034. "IDLE_TASK_INIT",
  1035. "VENUS_CORE_INIT",
  1036. "HW_CORES_INIT",
  1037. "RST_THREAD_INIT",
  1038. "HOST_THREAD_INIT",
  1039. "ALL_THREADS_INIT",
  1040. "TASK_MEMPOOL",
  1041. "SESSION_MUTEX",
  1042. "SIGNALS_INIT",
  1043. "RST_SIGNAL_INIT",
  1044. "INTR_EN_HOST",
  1045. "INTR_REG_HOST",
  1046. "INTR_EN_DSP",
  1047. "INTR_REG_DSP",
  1048. "X2HSOFTINTEN",
  1049. "H2XSOFTINTEN",
  1050. "CPU2DSPINTEN",
  1051. "DSP2CPUINT_SWRESET",
  1052. "THREADS_START",
  1053. "RST_THREAD_START",
  1054. "HST_THREAD_START",
  1055. "HST_THREAD_ENTRY"
  1056. };
  1057. static inline int __boot_firmware(struct iris_hfi_device *device)
  1058. {
  1059. int rc = 0, loop = 10;
  1060. u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 5000;
  1061. u32 reg_gdsc;
  1062. /*
  1063. * Hand off control of regulators to h/w _after_ enabling clocks.
  1064. * Note that the GDSC will turn off when switching from normal
  1065. * (s/w triggered) to fast (HW triggered) unless the h/w vote is
  1066. * present. Since Iris isn't up yet, the GDSC will be off briefly.
  1067. */
  1068. if (__enable_hw_power_collapse(device))
  1069. dprintk(CVP_ERR, "Failed to enabled inter-frame PC\n");
  1070. if (!msm_cvp_fw_low_power_mode)
  1071. goto skip_core_power_check;
  1072. while (loop) {
  1073. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  1074. if (reg_gdsc & 0x80000000) {
  1075. usleep_range(100, 200);
  1076. loop--;
  1077. } else {
  1078. break;
  1079. }
  1080. }
  1081. if (!loop)
  1082. dprintk(CVP_ERR, "fail to power off CORE during resume\n");
  1083. skip_core_power_check:
  1084. ctrl_init_val = BIT(0);
  1085. /* RUMI: CVP_CTRL_INIT in MPTest has bit 0 and 3 set */
  1086. __write_register(device, CVP_CTRL_INIT, ctrl_init_val);
  1087. while (!(ctrl_status & CVP_CTRL_INIT_STATUS__M) && count < max_tries) {
  1088. ctrl_status = __read_register(device, CVP_CTRL_STATUS);
  1089. if ((ctrl_status & CVP_CTRL_ERROR_STATUS__M) == 0x4) {
  1090. dprintk(CVP_ERR, "invalid setting for UC_REGION\n");
  1091. rc = -ENODATA;
  1092. break;
  1093. }
  1094. /* Reduce to 50, 100 on silicon */
  1095. usleep_range(50, 100);
  1096. count++;
  1097. }
  1098. if (!(ctrl_status & CVP_CTRL_INIT_STATUS__M)) {
  1099. ctrl_init_val = __read_register(device, CVP_CTRL_INIT);
  1100. dprintk(CVP_ERR,
  1101. "Failed to boot FW status: %x %x %s\n",
  1102. ctrl_status, ctrl_init_val,
  1103. boot_states[(ctrl_status >> 9) & 0x3f]);
  1104. check_tensilica_in_reset(device);
  1105. rc = -ENODEV;
  1106. }
  1107. /* Enable interrupt before sending commands to tensilica */
  1108. __write_register(device, CVP_CPU_CS_H2XSOFTINTEN, 0x1);
  1109. __write_register(device, CVP_CPU_CS_X2RPMh, 0x0);
  1110. return rc;
  1111. }
  1112. static int iris_hfi_resume(void *dev)
  1113. {
  1114. int rc = 0;
  1115. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1116. if (!device) {
  1117. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1118. return -EINVAL;
  1119. }
  1120. dprintk(CVP_CORE, "Resuming Iris\n");
  1121. mutex_lock(&device->lock);
  1122. rc = __resume(device);
  1123. mutex_unlock(&device->lock);
  1124. return rc;
  1125. }
  1126. static int iris_hfi_suspend(void *dev)
  1127. {
  1128. int rc = 0;
  1129. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1130. if (!device) {
  1131. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1132. return -EINVAL;
  1133. } else if (!device->res->sw_power_collapsible) {
  1134. return -ENOTSUPP;
  1135. }
  1136. dprintk(CVP_CORE, "Suspending Iris\n");
  1137. mutex_lock(&device->lock);
  1138. rc = __power_collapse(device, true);
  1139. if (rc) {
  1140. dprintk(CVP_WARN, "%s: Iris is busy\n", __func__);
  1141. rc = -EBUSY;
  1142. }
  1143. mutex_unlock(&device->lock);
  1144. /* Cancel pending delayed works if any */
  1145. if (!rc)
  1146. cancel_delayed_work(&iris_hfi_pm_work);
  1147. return rc;
  1148. }
  1149. void cvp_dump_csr(struct iris_hfi_device *dev)
  1150. {
  1151. u32 reg;
  1152. if (!dev)
  1153. return;
  1154. if (!dev->power_enabled || dev->reg_dumped)
  1155. return;
  1156. reg = __read_register(dev, CVP_WRAPPER_CPU_STATUS);
  1157. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_STATUS: %x\n", reg);
  1158. reg = __read_register(dev, CVP_CPU_CS_SCIACMDARG0);
  1159. dprintk(CVP_ERR, "CVP_CPU_CS_SCIACMDARG0: %x\n", reg);
  1160. reg = __read_register(dev, CVP_WRAPPER_INTR_STATUS);
  1161. dprintk(CVP_ERR, "CVP_WRAPPER_INTR_STATUS: %x\n", reg);
  1162. reg = __read_register(dev, CVP_CPU_CS_H2ASOFTINT);
  1163. dprintk(CVP_ERR, "CVP_CPU_CS_H2ASOFTINT: %x\n", reg);
  1164. reg = __read_register(dev, CVP_CPU_CS_A2HSOFTINT);
  1165. dprintk(CVP_ERR, "CVP_CPU_CS_A2HSOFTINT: %x\n", reg);
  1166. reg = __read_register(dev, CVP_CC_MVS1C_GDSCR);
  1167. dprintk(CVP_ERR, "CVP_CC_MVS1C_GDSCR: %x\n", reg);
  1168. reg = __read_register(dev, CVP_CC_MVS1C_CBCR);
  1169. dprintk(CVP_ERR, "CVP_CC_MVS1C_CBCR: %x\n", reg);
  1170. reg = __read_register(dev, CVP_WRAPPER_CPU_CLOCK_CONFIG);
  1171. dprintk(CVP_ERR, "CVP_WRAPPER_CPU_CLOCK_CONFIG: %x\n", reg);
  1172. reg = __read_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  1173. dprintk(CVP_ERR, "CVP_WRAPPER_CORE_CLOCK_CONFIG: %x\n", reg);
  1174. dump_noc_reg(dev);
  1175. dev->reg_dumped = true;
  1176. }
  1177. static int iris_hfi_flush_debug_queue(void *dev)
  1178. {
  1179. int rc = 0;
  1180. struct iris_hfi_device *device = (struct iris_hfi_device *) dev;
  1181. if (!device) {
  1182. dprintk(CVP_ERR, "%s invalid device\n", __func__);
  1183. return -EINVAL;
  1184. }
  1185. mutex_lock(&device->lock);
  1186. if (!device->power_enabled) {
  1187. dprintk(CVP_WARN, "%s: iris power off\n", __func__);
  1188. rc = -EINVAL;
  1189. goto exit;
  1190. }
  1191. cvp_dump_csr(device);
  1192. __flush_debug_queue(device, NULL);
  1193. exit:
  1194. mutex_unlock(&device->lock);
  1195. return rc;
  1196. }
  1197. static int iris_hfi_scale_clocks(void *dev, u32 freq)
  1198. {
  1199. int rc = 0;
  1200. struct iris_hfi_device *device = dev;
  1201. if (!device) {
  1202. dprintk(CVP_ERR, "Invalid args: %pK\n", device);
  1203. return -EINVAL;
  1204. }
  1205. mutex_lock(&device->lock);
  1206. if (__resume(device)) {
  1207. dprintk(CVP_ERR, "Resume from power collapse failed\n");
  1208. rc = -ENODEV;
  1209. goto exit;
  1210. }
  1211. rc = msm_cvp_set_clocks_impl(device, freq);
  1212. exit:
  1213. mutex_unlock(&device->lock);
  1214. return rc;
  1215. }
  1216. /* Writes into cmdq without raising an interrupt */
  1217. static int __iface_cmdq_write_relaxed(struct iris_hfi_device *device,
  1218. void *pkt, bool *requires_interrupt)
  1219. {
  1220. struct cvp_iface_q_info *q_info;
  1221. struct cvp_hal_cmd_pkt_hdr *cmd_packet;
  1222. int result = -E2BIG;
  1223. if (!device || !pkt) {
  1224. dprintk(CVP_ERR, "Invalid Params\n");
  1225. return -EINVAL;
  1226. }
  1227. __strict_check(device);
  1228. if (!__core_in_valid_state(device)) {
  1229. dprintk(CVP_ERR, "%s - fw not in init state\n", __func__);
  1230. result = -EINVAL;
  1231. goto err_q_null;
  1232. }
  1233. cmd_packet = (struct cvp_hal_cmd_pkt_hdr *)pkt;
  1234. device->last_packet_type = cmd_packet->packet_type;
  1235. q_info = &device->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1236. if (!q_info) {
  1237. dprintk(CVP_ERR, "cannot write to shared Q's\n");
  1238. goto err_q_null;
  1239. }
  1240. if (!q_info->q_array.align_virtual_addr) {
  1241. dprintk(CVP_ERR, "cannot write to shared CMD Q's\n");
  1242. result = -ENODATA;
  1243. goto err_q_null;
  1244. }
  1245. if (__resume(device)) {
  1246. dprintk(CVP_ERR, "%s: Power on failed\n", __func__);
  1247. goto err_q_write;
  1248. }
  1249. if (!__write_queue(q_info, (u8 *)pkt, requires_interrupt)) {
  1250. if (device->res->sw_power_collapsible) {
  1251. cancel_delayed_work(&iris_hfi_pm_work);
  1252. if (!queue_delayed_work(device->iris_pm_workq,
  1253. &iris_hfi_pm_work,
  1254. msecs_to_jiffies(
  1255. device->res->msm_cvp_pwr_collapse_delay))) {
  1256. dprintk(CVP_PWR,
  1257. "PM work already scheduled\n");
  1258. }
  1259. }
  1260. result = 0;
  1261. } else {
  1262. dprintk(CVP_ERR, "__iface_cmdq_write: queue full\n");
  1263. }
  1264. err_q_write:
  1265. err_q_null:
  1266. return result;
  1267. }
  1268. static int __iface_cmdq_write(struct iris_hfi_device *device, void *pkt)
  1269. {
  1270. bool needs_interrupt = false;
  1271. int rc = __iface_cmdq_write_relaxed(device, pkt, &needs_interrupt);
  1272. if (!rc && needs_interrupt) {
  1273. /* Consumer of cmdq prefers that we raise an interrupt */
  1274. rc = 0;
  1275. if (!__is_ctl_power_on(device))
  1276. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1277. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1278. }
  1279. return rc;
  1280. }
  1281. static int __iface_msgq_read(struct iris_hfi_device *device, void *pkt)
  1282. {
  1283. u32 tx_req_is_set = 0;
  1284. int rc = 0;
  1285. struct cvp_iface_q_info *q_info;
  1286. if (!pkt) {
  1287. dprintk(CVP_ERR, "Invalid Params\n");
  1288. return -EINVAL;
  1289. }
  1290. __strict_check(device);
  1291. if (!__core_in_valid_state(device)) {
  1292. dprintk(CVP_WARN, "%s - fw not in init state\n", __func__);
  1293. rc = -EINVAL;
  1294. goto read_error_null;
  1295. }
  1296. q_info = &device->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1297. if (q_info->q_array.align_virtual_addr == NULL) {
  1298. dprintk(CVP_ERR, "cannot read from shared MSG Q's\n");
  1299. rc = -ENODATA;
  1300. goto read_error_null;
  1301. }
  1302. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1303. if (tx_req_is_set) {
  1304. if (!__is_ctl_power_on(device))
  1305. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1306. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1307. }
  1308. rc = 0;
  1309. } else
  1310. rc = -ENODATA;
  1311. read_error_null:
  1312. return rc;
  1313. }
  1314. static int __iface_dbgq_read(struct iris_hfi_device *device, void *pkt)
  1315. {
  1316. u32 tx_req_is_set = 0;
  1317. int rc = 0;
  1318. struct cvp_iface_q_info *q_info;
  1319. if (!pkt) {
  1320. dprintk(CVP_ERR, "Invalid Params\n");
  1321. return -EINVAL;
  1322. }
  1323. __strict_check(device);
  1324. q_info = &device->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1325. if (q_info->q_array.align_virtual_addr == NULL) {
  1326. dprintk(CVP_ERR, "cannot read from shared DBG Q's\n");
  1327. rc = -ENODATA;
  1328. goto dbg_error_null;
  1329. }
  1330. if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {
  1331. if (tx_req_is_set) {
  1332. if (!__is_ctl_power_on(device))
  1333. dprintk(CVP_ERR, "%s power off, don't access reg\n", __func__);
  1334. __write_register(device, CVP_CPU_CS_H2ASOFTINT, 1);
  1335. }
  1336. rc = 0;
  1337. } else
  1338. rc = -ENODATA;
  1339. dbg_error_null:
  1340. return rc;
  1341. }
  1342. static void __set_queue_hdr_defaults(struct cvp_hfi_queue_header *q_hdr)
  1343. {
  1344. q_hdr->qhdr_status = 0x1;
  1345. q_hdr->qhdr_type = CVP_IFACEQ_DFLT_QHDR;
  1346. q_hdr->qhdr_q_size = CVP_IFACEQ_QUEUE_SIZE / 4;
  1347. q_hdr->qhdr_pkt_size = 0;
  1348. q_hdr->qhdr_rx_wm = 0x1;
  1349. q_hdr->qhdr_tx_wm = 0x1;
  1350. q_hdr->qhdr_rx_req = 0x1;
  1351. q_hdr->qhdr_tx_req = 0x0;
  1352. q_hdr->qhdr_rx_irq_status = 0x0;
  1353. q_hdr->qhdr_tx_irq_status = 0x0;
  1354. q_hdr->qhdr_read_idx = 0x0;
  1355. q_hdr->qhdr_write_idx = 0x0;
  1356. }
  1357. /*
  1358. *Unused, keep for reference
  1359. */
  1360. /*
  1361. static void __interface_dsp_queues_release(struct iris_hfi_device *device)
  1362. {
  1363. int i;
  1364. struct msm_cvp_smem *mem_data = &device->dsp_iface_q_table.mem_data;
  1365. struct context_bank_info *cb = mem_data->mapping_info.cb_info;
  1366. if (!device->dsp_iface_q_table.align_virtual_addr) {
  1367. dprintk(CVP_ERR, "%s: already released\n", __func__);
  1368. return;
  1369. }
  1370. dma_unmap_single_attrs(cb->dev, mem_data->device_addr,
  1371. mem_data->size, DMA_BIDIRECTIONAL, 0);
  1372. dma_free_coherent(device->res->mem_cdsp.dev, mem_data->size,
  1373. mem_data->kvaddr, mem_data->dma_handle);
  1374. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1375. device->dsp_iface_queues[i].q_hdr = NULL;
  1376. device->dsp_iface_queues[i].q_array.align_virtual_addr = NULL;
  1377. device->dsp_iface_queues[i].q_array.align_device_addr = 0;
  1378. }
  1379. device->dsp_iface_q_table.align_virtual_addr = NULL;
  1380. device->dsp_iface_q_table.align_device_addr = 0;
  1381. }
  1382. */
  1383. static int __interface_dsp_queues_init(struct iris_hfi_device *dev)
  1384. {
  1385. int rc = 0;
  1386. u32 i;
  1387. struct cvp_iface_q_info *iface_q;
  1388. int offset = 0;
  1389. phys_addr_t fw_bias = 0;
  1390. size_t q_size;
  1391. struct msm_cvp_smem *mem_data;
  1392. void *kvaddr;
  1393. dma_addr_t dma_handle;
  1394. dma_addr_t iova;
  1395. struct context_bank_info *cb;
  1396. q_size = ALIGN(QUEUE_SIZE, SZ_1M);
  1397. mem_data = &dev->dsp_iface_q_table.mem_data;
  1398. if (mem_data->kvaddr) {
  1399. memset((void *)mem_data->kvaddr, 0, q_size);
  1400. cvp_dsp_init_hfi_queue_hdr(dev);
  1401. return 0;
  1402. }
  1403. /* Allocate dsp queues from CDSP device memory */
  1404. kvaddr = dma_alloc_coherent(dev->res->mem_cdsp.dev, q_size,
  1405. &dma_handle, GFP_KERNEL);
  1406. if (IS_ERR_OR_NULL(kvaddr)) {
  1407. dprintk(CVP_ERR, "%s: failed dma allocation\n", __func__);
  1408. goto fail_dma_alloc;
  1409. }
  1410. cb = msm_cvp_smem_get_context_bank(dev->res, SMEM_CDSP);
  1411. if (!cb) {
  1412. dprintk(CVP_ERR,
  1413. "%s: failed to get DSP context bank\n", __func__);
  1414. goto fail_dma_map;
  1415. }
  1416. iova = dma_map_single_attrs(cb->dev, phys_to_virt(dma_handle),
  1417. q_size, DMA_BIDIRECTIONAL, 0);
  1418. if (dma_mapping_error(cb->dev, iova)) {
  1419. dprintk(CVP_ERR, "%s: failed dma mapping\n", __func__);
  1420. goto fail_dma_map;
  1421. }
  1422. dprintk(CVP_DSP,
  1423. "%s: kvaddr %pK dma_handle %#llx iova %#llx size %zd\n",
  1424. __func__, kvaddr, dma_handle, iova, q_size);
  1425. memset(mem_data, 0, sizeof(struct msm_cvp_smem));
  1426. mem_data->kvaddr = kvaddr;
  1427. mem_data->device_addr = iova;
  1428. mem_data->dma_handle = dma_handle;
  1429. mem_data->size = q_size;
  1430. mem_data->mapping_info.cb_info = cb;
  1431. if (!is_iommu_present(dev->res))
  1432. fw_bias = dev->cvp_hal_data->firmware_base;
  1433. dev->dsp_iface_q_table.align_virtual_addr = kvaddr;
  1434. dev->dsp_iface_q_table.align_device_addr = iova - fw_bias;
  1435. dev->dsp_iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1436. offset = dev->dsp_iface_q_table.mem_size;
  1437. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1438. iface_q = &dev->dsp_iface_queues[i];
  1439. iface_q->q_array.align_device_addr = iova + offset - fw_bias;
  1440. iface_q->q_array.align_virtual_addr = kvaddr + offset;
  1441. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1442. offset += iface_q->q_array.mem_size;
  1443. spin_lock_init(&iface_q->hfi_lock);
  1444. }
  1445. cvp_dsp_init_hfi_queue_hdr(dev);
  1446. return rc;
  1447. fail_dma_map:
  1448. dma_free_coherent(dev->res->mem_cdsp.dev, q_size, kvaddr, dma_handle);
  1449. fail_dma_alloc:
  1450. return -ENOMEM;
  1451. }
  1452. static void __interface_queues_release(struct iris_hfi_device *device)
  1453. {
  1454. #ifdef CONFIG_EVA_TVM
  1455. int i;
  1456. struct cvp_hfi_mem_map_table *qdss;
  1457. struct cvp_hfi_mem_map *mem_map;
  1458. int num_entries = device->res->qdss_addr_set.count;
  1459. unsigned long mem_map_table_base_addr;
  1460. struct context_bank_info *cb;
  1461. if (device->qdss.align_virtual_addr) {
  1462. qdss = (struct cvp_hfi_mem_map_table *)
  1463. device->qdss.align_virtual_addr;
  1464. qdss->mem_map_num_entries = num_entries;
  1465. mem_map_table_base_addr =
  1466. device->qdss.align_device_addr +
  1467. sizeof(struct cvp_hfi_mem_map_table);
  1468. qdss->mem_map_table_base_addr =
  1469. (u32)mem_map_table_base_addr;
  1470. if ((unsigned long)qdss->mem_map_table_base_addr !=
  1471. mem_map_table_base_addr) {
  1472. dprintk(CVP_ERR,
  1473. "Invalid mem_map_table_base_addr %#lx",
  1474. mem_map_table_base_addr);
  1475. }
  1476. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1477. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1478. for (i = 0; cb && i < num_entries; i++) {
  1479. iommu_unmap(cb->domain,
  1480. mem_map[i].virtual_addr,
  1481. mem_map[i].size);
  1482. }
  1483. __smem_free(device, &device->qdss.mem_data);
  1484. }
  1485. __smem_free(device, &device->iface_q_table.mem_data);
  1486. __smem_free(device, &device->sfr.mem_data);
  1487. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1488. device->iface_queues[i].q_hdr = NULL;
  1489. device->iface_queues[i].q_array.align_virtual_addr = NULL;
  1490. device->iface_queues[i].q_array.align_device_addr = 0;
  1491. }
  1492. device->iface_q_table.align_virtual_addr = NULL;
  1493. device->iface_q_table.align_device_addr = 0;
  1494. device->qdss.align_virtual_addr = NULL;
  1495. device->qdss.align_device_addr = 0;
  1496. device->sfr.align_virtual_addr = NULL;
  1497. device->sfr.align_device_addr = 0;
  1498. device->mem_addr.align_virtual_addr = NULL;
  1499. device->mem_addr.align_device_addr = 0;
  1500. #endif
  1501. }
  1502. static int __get_qdss_iommu_virtual_addr(struct iris_hfi_device *dev,
  1503. struct cvp_hfi_mem_map *mem_map,
  1504. struct iommu_domain *domain)
  1505. {
  1506. int i;
  1507. int rc = 0;
  1508. dma_addr_t iova = QDSS_IOVA_START;
  1509. int num_entries = dev->res->qdss_addr_set.count;
  1510. struct addr_range *qdss_addr_tbl = dev->res->qdss_addr_set.addr_tbl;
  1511. if (!num_entries)
  1512. return -ENODATA;
  1513. for (i = 0; i < num_entries; i++) {
  1514. if (domain) {
  1515. rc = iommu_map(domain, iova,
  1516. qdss_addr_tbl[i].start,
  1517. qdss_addr_tbl[i].size,
  1518. IOMMU_READ | IOMMU_WRITE);
  1519. if (rc) {
  1520. dprintk(CVP_ERR,
  1521. "IOMMU QDSS mapping failed for addr %#x\n",
  1522. qdss_addr_tbl[i].start);
  1523. rc = -ENOMEM;
  1524. break;
  1525. }
  1526. } else {
  1527. iova = qdss_addr_tbl[i].start;
  1528. }
  1529. mem_map[i].virtual_addr = (u32)iova;
  1530. mem_map[i].physical_addr = qdss_addr_tbl[i].start;
  1531. mem_map[i].size = qdss_addr_tbl[i].size;
  1532. mem_map[i].attr = 0x0;
  1533. iova += mem_map[i].size;
  1534. }
  1535. if (i < num_entries) {
  1536. dprintk(CVP_ERR,
  1537. "QDSS mapping failed, Freeing other entries %d\n", i);
  1538. for (--i; domain && i >= 0; i--) {
  1539. iommu_unmap(domain,
  1540. mem_map[i].virtual_addr,
  1541. mem_map[i].size);
  1542. }
  1543. }
  1544. return rc;
  1545. }
  1546. static void __setup_ucregion_memory_map(struct iris_hfi_device *device)
  1547. {
  1548. __write_register(device, CVP_UC_REGION_ADDR,
  1549. (u32)device->iface_q_table.align_device_addr);
  1550. __write_register(device, CVP_UC_REGION_SIZE, SHARED_QSIZE);
  1551. __write_register(device, CVP_QTBL_ADDR,
  1552. (u32)device->iface_q_table.align_device_addr);
  1553. __write_register(device, CVP_QTBL_INFO, 0x01);
  1554. if (device->sfr.align_device_addr)
  1555. __write_register(device, CVP_SFR_ADDR,
  1556. (u32)device->sfr.align_device_addr);
  1557. if (device->qdss.align_device_addr)
  1558. __write_register(device, CVP_MMAP_ADDR,
  1559. (u32)device->qdss.align_device_addr);
  1560. call_iris_op(device, setup_dsp_uc_memmap, device);
  1561. }
  1562. static void __hfi_queue_init(struct iris_hfi_device *dev)
  1563. {
  1564. int i, offset = 0;
  1565. struct cvp_hfi_queue_table_header *q_tbl_hdr;
  1566. struct cvp_iface_q_info *iface_q;
  1567. struct cvp_hfi_queue_header *q_hdr;
  1568. if (!dev)
  1569. return;
  1570. offset += dev->iface_q_table.mem_size;
  1571. for (i = 0; i < CVP_IFACEQ_NUMQ; i++) {
  1572. iface_q = &dev->iface_queues[i];
  1573. iface_q->q_array.align_device_addr =
  1574. dev->iface_q_table.align_device_addr + offset;
  1575. iface_q->q_array.align_virtual_addr =
  1576. dev->iface_q_table.align_virtual_addr + offset;
  1577. iface_q->q_array.mem_size = CVP_IFACEQ_QUEUE_SIZE;
  1578. offset += iface_q->q_array.mem_size;
  1579. iface_q->q_hdr = CVP_IFACEQ_GET_QHDR_START_ADDR(
  1580. dev->iface_q_table.align_virtual_addr, i);
  1581. __set_queue_hdr_defaults(iface_q->q_hdr);
  1582. spin_lock_init(&iface_q->hfi_lock);
  1583. }
  1584. q_tbl_hdr = (struct cvp_hfi_queue_table_header *)
  1585. dev->iface_q_table.align_virtual_addr;
  1586. q_tbl_hdr->qtbl_version = 0;
  1587. q_tbl_hdr->device_addr = (void *)dev;
  1588. strlcpy(q_tbl_hdr->name, "msm_cvp", sizeof(q_tbl_hdr->name));
  1589. q_tbl_hdr->qtbl_size = CVP_IFACEQ_TABLE_SIZE;
  1590. q_tbl_hdr->qtbl_qhdr0_offset =
  1591. sizeof(struct cvp_hfi_queue_table_header);
  1592. q_tbl_hdr->qtbl_qhdr_size = sizeof(struct cvp_hfi_queue_header);
  1593. q_tbl_hdr->qtbl_num_q = CVP_IFACEQ_NUMQ;
  1594. q_tbl_hdr->qtbl_num_active_q = CVP_IFACEQ_NUMQ;
  1595. iface_q = &dev->iface_queues[CVP_IFACEQ_CMDQ_IDX];
  1596. q_hdr = iface_q->q_hdr;
  1597. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1598. q_hdr->qhdr_type |= HFI_Q_ID_HOST_TO_CTRL_CMD_Q;
  1599. iface_q = &dev->iface_queues[CVP_IFACEQ_MSGQ_IDX];
  1600. q_hdr = iface_q->q_hdr;
  1601. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1602. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_MSG_Q;
  1603. iface_q = &dev->iface_queues[CVP_IFACEQ_DBGQ_IDX];
  1604. q_hdr = iface_q->q_hdr;
  1605. q_hdr->qhdr_start_addr = iface_q->q_array.align_device_addr;
  1606. q_hdr->qhdr_type |= HFI_Q_ID_CTRL_TO_HOST_DEBUG_Q;
  1607. /*
  1608. * Set receive request to zero on debug queue as there is no
  1609. * need of interrupt from cvp hardware for debug messages
  1610. */
  1611. q_hdr->qhdr_rx_req = 0;
  1612. }
  1613. static void __sfr_init(struct iris_hfi_device *dev)
  1614. {
  1615. struct cvp_hfi_sfr_struct *vsfr;
  1616. if (!dev)
  1617. return;
  1618. vsfr = (struct cvp_hfi_sfr_struct *) dev->sfr.align_virtual_addr;
  1619. if (vsfr)
  1620. vsfr->bufSize = ALIGNED_SFR_SIZE;
  1621. }
  1622. static int __interface_queues_init(struct iris_hfi_device *dev)
  1623. {
  1624. int rc = 0;
  1625. struct cvp_hfi_mem_map_table *qdss;
  1626. struct cvp_hfi_mem_map *mem_map;
  1627. struct cvp_mem_addr *mem_addr;
  1628. int num_entries = dev->res->qdss_addr_set.count;
  1629. phys_addr_t fw_bias = 0;
  1630. size_t q_size;
  1631. unsigned long mem_map_table_base_addr;
  1632. struct context_bank_info *cb;
  1633. q_size = SHARED_QSIZE - ALIGNED_SFR_SIZE - ALIGNED_QDSS_SIZE;
  1634. mem_addr = &dev->mem_addr;
  1635. if (!is_iommu_present(dev->res))
  1636. fw_bias = dev->cvp_hal_data->firmware_base;
  1637. if (dev->iface_q_table.align_virtual_addr) {
  1638. memset((void *)dev->iface_q_table.align_virtual_addr,
  1639. 0, q_size);
  1640. goto hfi_queue_init;
  1641. }
  1642. rc = __smem_alloc(dev, mem_addr, q_size, 1, SMEM_UNCACHED);
  1643. if (rc) {
  1644. dprintk(CVP_ERR, "iface_q_table_alloc_fail\n");
  1645. goto fail_alloc_queue;
  1646. }
  1647. dev->iface_q_table.align_virtual_addr = mem_addr->align_virtual_addr;
  1648. dev->iface_q_table.align_device_addr = mem_addr->align_device_addr -
  1649. fw_bias;
  1650. dev->iface_q_table.mem_size = CVP_IFACEQ_TABLE_SIZE;
  1651. dev->iface_q_table.mem_data = mem_addr->mem_data;
  1652. hfi_queue_init:
  1653. __hfi_queue_init(dev);
  1654. if (dev->sfr.align_virtual_addr) {
  1655. memset((void *)dev->sfr.align_virtual_addr,
  1656. 0, ALIGNED_SFR_SIZE);
  1657. goto sfr_init;
  1658. }
  1659. rc = __smem_alloc(dev, mem_addr, ALIGNED_SFR_SIZE, 1, SMEM_UNCACHED);
  1660. if (rc) {
  1661. dprintk(CVP_WARN, "sfr_alloc_fail: SFR not will work\n");
  1662. dev->sfr.align_device_addr = 0;
  1663. } else {
  1664. dev->sfr.align_device_addr = mem_addr->align_device_addr -
  1665. fw_bias;
  1666. dev->sfr.align_virtual_addr = mem_addr->align_virtual_addr;
  1667. dev->sfr.mem_size = ALIGNED_SFR_SIZE;
  1668. dev->sfr.mem_data = mem_addr->mem_data;
  1669. }
  1670. sfr_init:
  1671. __sfr_init(dev);
  1672. if (dev->qdss.align_virtual_addr)
  1673. goto dsp_hfi_queue_init;
  1674. if ((msm_cvp_fw_debug_mode & HFI_DEBUG_MODE_QDSS) && num_entries) {
  1675. rc = __smem_alloc(dev, mem_addr, ALIGNED_QDSS_SIZE, 1,
  1676. SMEM_UNCACHED);
  1677. if (rc) {
  1678. dprintk(CVP_WARN,
  1679. "qdss_alloc_fail: QDSS messages logging will not work\n");
  1680. dev->qdss.align_device_addr = 0;
  1681. } else {
  1682. dev->qdss.align_device_addr =
  1683. mem_addr->align_device_addr - fw_bias;
  1684. dev->qdss.align_virtual_addr =
  1685. mem_addr->align_virtual_addr;
  1686. dev->qdss.mem_size = ALIGNED_QDSS_SIZE;
  1687. dev->qdss.mem_data = mem_addr->mem_data;
  1688. }
  1689. }
  1690. if (dev->qdss.align_virtual_addr) {
  1691. qdss =
  1692. (struct cvp_hfi_mem_map_table *)dev->qdss.align_virtual_addr;
  1693. qdss->mem_map_num_entries = num_entries;
  1694. mem_map_table_base_addr = dev->qdss.align_device_addr +
  1695. sizeof(struct cvp_hfi_mem_map_table);
  1696. qdss->mem_map_table_base_addr = mem_map_table_base_addr;
  1697. mem_map = (struct cvp_hfi_mem_map *)(qdss + 1);
  1698. cb = msm_cvp_smem_get_context_bank(dev->res, 0);
  1699. if (!cb) {
  1700. dprintk(CVP_ERR,
  1701. "%s: failed to get context bank\n", __func__);
  1702. return -EINVAL;
  1703. }
  1704. rc = __get_qdss_iommu_virtual_addr(dev, mem_map, cb->domain);
  1705. if (rc) {
  1706. dprintk(CVP_ERR,
  1707. "IOMMU mapping failed, Freeing qdss memdata\n");
  1708. __smem_free(dev, &dev->qdss.mem_data);
  1709. dev->qdss.align_virtual_addr = NULL;
  1710. dev->qdss.align_device_addr = 0;
  1711. }
  1712. }
  1713. dsp_hfi_queue_init:
  1714. rc = __interface_dsp_queues_init(dev);
  1715. if (rc) {
  1716. dprintk(CVP_ERR, "dsp_queues_init failed\n");
  1717. goto fail_alloc_queue;
  1718. }
  1719. __setup_ucregion_memory_map(dev);
  1720. return 0;
  1721. fail_alloc_queue:
  1722. return -ENOMEM;
  1723. }
  1724. static int __sys_set_debug(struct iris_hfi_device *device, u32 debug)
  1725. {
  1726. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1727. int rc = 0;
  1728. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1729. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1730. rc = call_hfi_pkt_op(device, sys_debug_config, pkt, debug);
  1731. if (rc) {
  1732. dprintk(CVP_WARN,
  1733. "Debug mode setting to FW failed\n");
  1734. return -ENOTEMPTY;
  1735. }
  1736. if (__iface_cmdq_write(device, pkt))
  1737. return -ENOTEMPTY;
  1738. return 0;
  1739. }
  1740. static int __sys_set_idle_indicator(struct iris_hfi_device *device,
  1741. bool enable)
  1742. {
  1743. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1744. int rc = 0;
  1745. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1746. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1747. rc = call_hfi_pkt_op(device, sys_set_idle_indicator, pkt, enable);
  1748. if (__iface_cmdq_write(device, pkt))
  1749. return -ENOTEMPTY;
  1750. return 0;
  1751. }
  1752. static int __sys_set_coverage(struct iris_hfi_device *device, u32 mode)
  1753. {
  1754. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1755. int rc = 0;
  1756. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1757. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1758. rc = call_hfi_pkt_op(device, sys_coverage_config,
  1759. pkt, mode);
  1760. if (rc) {
  1761. dprintk(CVP_WARN,
  1762. "Coverage mode setting to FW failed\n");
  1763. return -ENOTEMPTY;
  1764. }
  1765. if (__iface_cmdq_write(device, pkt)) {
  1766. dprintk(CVP_WARN, "Failed to send coverage pkt to f/w\n");
  1767. return -ENOTEMPTY;
  1768. }
  1769. return 0;
  1770. }
  1771. static int __sys_set_power_control(struct iris_hfi_device *device,
  1772. bool enable)
  1773. {
  1774. struct regulator_info *rinfo;
  1775. bool supported = false;
  1776. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  1777. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  1778. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  1779. iris_hfi_for_each_regulator(device, rinfo) {
  1780. if (rinfo->has_hw_power_collapse) {
  1781. supported = true;
  1782. break;
  1783. }
  1784. }
  1785. if (!supported)
  1786. return 0;
  1787. call_hfi_pkt_op(device, sys_power_control, pkt, enable);
  1788. if (__iface_cmdq_write(device, pkt))
  1789. return -ENOTEMPTY;
  1790. return 0;
  1791. }
  1792. static void cvp_pm_qos_update(struct iris_hfi_device *device, bool vote_on)
  1793. {
  1794. u32 latency, off_vote_cnt;
  1795. int i, err = 0;
  1796. spin_lock(&device->res->pm_qos.lock);
  1797. off_vote_cnt = device->res->pm_qos.off_vote_cnt;
  1798. spin_unlock(&device->res->pm_qos.lock);
  1799. if (vote_on && off_vote_cnt)
  1800. return;
  1801. latency = vote_on ? device->res->pm_qos.latency_us :
  1802. PM_QOS_RESUME_LATENCY_DEFAULT_VALUE;
  1803. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  1804. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  1805. if (!cpu_possible(device->res->pm_qos.silver_cores[i]))
  1806. continue;
  1807. err = dev_pm_qos_update_request(
  1808. &device->res->pm_qos.pm_qos_hdls[i],
  1809. latency);
  1810. if (err < 0) {
  1811. if (vote_on) {
  1812. dprintk(CVP_WARN,
  1813. "pm qos on failed %d\n", err);
  1814. } else {
  1815. dprintk(CVP_WARN,
  1816. "pm qos off failed %d\n", err);
  1817. }
  1818. }
  1819. }
  1820. }
  1821. static int iris_pm_qos_update(void *device)
  1822. {
  1823. struct iris_hfi_device *dev;
  1824. if (!device) {
  1825. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  1826. return -ENODEV;
  1827. }
  1828. dev = device;
  1829. mutex_lock(&dev->lock);
  1830. cvp_pm_qos_update(dev, true);
  1831. mutex_unlock(&dev->lock);
  1832. return 0;
  1833. }
  1834. static int __hwfence_regs_map(struct iris_hfi_device *device)
  1835. {
  1836. int rc = 0;
  1837. struct context_bank_info *cb;
  1838. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1839. if (!cb) {
  1840. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1841. return -EINVAL;
  1842. }
  1843. if (device->res->reg_mappings.ipclite_phyaddr != 0) {
  1844. rc = iommu_map(cb->domain,
  1845. device->res->reg_mappings.ipclite_iova,
  1846. device->res->reg_mappings.ipclite_phyaddr,
  1847. device->res->reg_mappings.ipclite_size,
  1848. IOMMU_READ | IOMMU_WRITE);
  1849. if (rc) {
  1850. dprintk(CVP_ERR, "map ipclite fail %d %#x %#x %#x\n",
  1851. rc, device->res->reg_mappings.ipclite_iova,
  1852. device->res->reg_mappings.ipclite_phyaddr,
  1853. device->res->reg_mappings.ipclite_size);
  1854. return rc;
  1855. }
  1856. }
  1857. if (device->res->reg_mappings.hwmutex_phyaddr != 0) {
  1858. rc = iommu_map(cb->domain,
  1859. device->res->reg_mappings.hwmutex_iova,
  1860. device->res->reg_mappings.hwmutex_phyaddr,
  1861. device->res->reg_mappings.hwmutex_size,
  1862. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1863. if (rc) {
  1864. dprintk(CVP_ERR, "map hwmutex fail %d %#x %#x %#x\n",
  1865. rc, device->res->reg_mappings.hwmutex_iova,
  1866. device->res->reg_mappings.hwmutex_phyaddr,
  1867. device->res->reg_mappings.hwmutex_size);
  1868. return rc;
  1869. }
  1870. }
  1871. if (device->res->reg_mappings.aon_phyaddr != 0) {
  1872. rc = iommu_map(cb->domain,
  1873. device->res->reg_mappings.aon_iova,
  1874. device->res->reg_mappings.aon_phyaddr,
  1875. device->res->reg_mappings.aon_size,
  1876. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1877. if (rc) {
  1878. dprintk(CVP_ERR, "map aon fail %d %#x %#x %#x\n",
  1879. rc, device->res->reg_mappings.aon_iova,
  1880. device->res->reg_mappings.aon_phyaddr,
  1881. device->res->reg_mappings.aon_size);
  1882. return rc;
  1883. }
  1884. }
  1885. if (device->res->reg_mappings.timer_phyaddr != 0) {
  1886. rc = iommu_map(cb->domain,
  1887. device->res->reg_mappings.timer_iova,
  1888. device->res->reg_mappings.timer_phyaddr,
  1889. device->res->reg_mappings.timer_size,
  1890. IOMMU_MMIO | IOMMU_READ | IOMMU_WRITE);
  1891. if (rc) {
  1892. dprintk(CVP_ERR, "map timer fail %d %#x %#x %#x\n",
  1893. rc, device->res->reg_mappings.timer_iova,
  1894. device->res->reg_mappings.timer_phyaddr,
  1895. device->res->reg_mappings.timer_size);
  1896. return rc;
  1897. }
  1898. }
  1899. return rc;
  1900. }
  1901. static int __hwfence_regs_unmap(struct iris_hfi_device *device)
  1902. {
  1903. int rc = 0;
  1904. struct context_bank_info *cb;
  1905. cb = msm_cvp_smem_get_context_bank(device->res, 0);
  1906. if (!cb) {
  1907. dprintk(CVP_ERR, "%s: fail to get cb\n", __func__);
  1908. return -EINVAL;
  1909. }
  1910. if (device->res->reg_mappings.ipclite_iova != 0) {
  1911. iommu_unmap(cb->domain,
  1912. device->res->reg_mappings.ipclite_iova,
  1913. device->res->reg_mappings.ipclite_size);
  1914. }
  1915. if (device->res->reg_mappings.hwmutex_iova != 0) {
  1916. iommu_unmap(cb->domain,
  1917. device->res->reg_mappings.hwmutex_iova,
  1918. device->res->reg_mappings.hwmutex_size);
  1919. }
  1920. if (device->res->reg_mappings.aon_iova != 0) {
  1921. iommu_unmap(cb->domain,
  1922. device->res->reg_mappings.aon_iova,
  1923. device->res->reg_mappings.aon_size);
  1924. }
  1925. if (device->res->reg_mappings.timer_iova != 0) {
  1926. iommu_unmap(cb->domain,
  1927. device->res->reg_mappings.timer_iova,
  1928. device->res->reg_mappings.timer_size);
  1929. }
  1930. return rc;
  1931. }
  1932. static int iris_hfi_core_init(void *device)
  1933. {
  1934. int rc = 0;
  1935. u32 ipcc_iova;
  1936. struct cvp_hfi_cmd_sys_init_packet pkt;
  1937. struct cvp_hfi_cmd_sys_get_property_packet version_pkt;
  1938. struct iris_hfi_device *dev;
  1939. if (!device) {
  1940. dprintk(CVP_ERR, "Invalid device\n");
  1941. return -ENODEV;
  1942. }
  1943. dev = device;
  1944. dprintk(CVP_CORE, "Core initializing\n");
  1945. pm_stay_awake(dev->res->pdev->dev.parent);
  1946. mutex_lock(&dev->lock);
  1947. dev->bus_vote.data =
  1948. kzalloc(sizeof(struct cvp_bus_vote_data), GFP_KERNEL);
  1949. if (!dev->bus_vote.data) {
  1950. dprintk(CVP_ERR, "Bus vote data memory is not allocated\n");
  1951. rc = -ENOMEM;
  1952. goto err_no_mem;
  1953. }
  1954. dev->bus_vote.data_count = 1;
  1955. dev->bus_vote.data->power_mode = CVP_POWER_TURBO;
  1956. __hwfence_regs_map(dev);
  1957. rc = __power_on_init(dev);
  1958. if (rc) {
  1959. dprintk(CVP_ERR, "Failed to power on init EVA\n");
  1960. goto err_load_fw;
  1961. }
  1962. rc = cvp_synx_recover();
  1963. if (rc) {
  1964. dprintk(CVP_ERR, "Failed to recover synx\n");
  1965. goto err_core_init;
  1966. }
  1967. /* mmrm registration */
  1968. if (msm_cvp_mmrm_enabled) {
  1969. rc = msm_cvp_mmrm_register(device);
  1970. if (rc) {
  1971. dprintk(CVP_ERR, "Failed to register mmrm client\n");
  1972. goto err_core_init;
  1973. }
  1974. }
  1975. __set_state(dev, IRIS_STATE_INIT);
  1976. dev->reg_dumped = false;
  1977. dprintk(CVP_CORE, "Dev_Virt: %pa, Reg_Virt: %pK\n",
  1978. &dev->cvp_hal_data->firmware_base,
  1979. dev->cvp_hal_data->register_base);
  1980. rc = __interface_queues_init(dev);
  1981. if (rc) {
  1982. dprintk(CVP_ERR, "failed to init queues\n");
  1983. rc = -ENOMEM;
  1984. goto err_core_init;
  1985. }
  1986. cvp_register_va_md_region();
  1987. // Add node for dev struct
  1988. add_va_node_to_list(CVP_QUEUE_DUMP, dev,
  1989. sizeof(struct iris_hfi_device),
  1990. "iris_hfi_device-dev", false);
  1991. add_queue_header_to_va_md_list((void*)dev);
  1992. add_hfi_queue_to_va_md_list((void*)dev);
  1993. rc = msm_cvp_map_ipcc_regs(&ipcc_iova);
  1994. if (!rc) {
  1995. dprintk(CVP_CORE, "IPCC iova 0x%x\n", ipcc_iova);
  1996. __write_register(dev, CVP_MMAP_ADDR, ipcc_iova);
  1997. }
  1998. rc = __load_fw(dev);
  1999. if (rc) {
  2000. dprintk(CVP_ERR, "Failed to load Iris FW\n");
  2001. goto err_core_init;
  2002. }
  2003. rc = __boot_firmware(dev);
  2004. if (rc) {
  2005. dprintk(CVP_ERR, "Failed to start core\n");
  2006. rc = -ENODEV;
  2007. goto err_core_init;
  2008. }
  2009. dev->version = __read_register(dev, CVP_VERSION_INFO);
  2010. rc = call_hfi_pkt_op(dev, sys_init, &pkt, 0);
  2011. if (rc) {
  2012. dprintk(CVP_ERR, "Failed to create sys init pkt\n");
  2013. goto err_core_init;
  2014. }
  2015. if (__iface_cmdq_write(dev, &pkt)) {
  2016. rc = -ENOTEMPTY;
  2017. goto err_core_init;
  2018. }
  2019. rc = call_hfi_pkt_op(dev, sys_image_version, &version_pkt);
  2020. if (rc || __iface_cmdq_write(dev, &version_pkt))
  2021. dprintk(CVP_WARN, "Failed to send image version pkt to f/w\n");
  2022. __sys_set_debug(device, msm_cvp_fw_debug);
  2023. __enable_subcaches(device);
  2024. __set_subcaches(device);
  2025. __set_ubwc_config(device);
  2026. __sys_set_idle_indicator(device, true);
  2027. if (dev->res->pm_qos.latency_us) {
  2028. int err = 0;
  2029. u32 i, cpu;
  2030. dev->res->pm_qos.pm_qos_hdls = kcalloc(
  2031. dev->res->pm_qos.silver_count,
  2032. sizeof(struct dev_pm_qos_request),
  2033. GFP_KERNEL);
  2034. if (!dev->res->pm_qos.pm_qos_hdls) {
  2035. dprintk(CVP_WARN, "Failed allocate pm_qos_hdls\n");
  2036. goto pm_qos_bail;
  2037. }
  2038. for (i = 0; i < dev->res->pm_qos.silver_count; i++) {
  2039. cpu = dev->res->pm_qos.silver_cores[i];
  2040. if (!cpu_possible(cpu))
  2041. continue;
  2042. err = dev_pm_qos_add_request(
  2043. get_cpu_device(cpu),
  2044. &dev->res->pm_qos.pm_qos_hdls[i],
  2045. DEV_PM_QOS_RESUME_LATENCY,
  2046. dev->res->pm_qos.latency_us);
  2047. if (err < 0)
  2048. dprintk(CVP_WARN,
  2049. "%s pm_qos_add_req %d failed\n",
  2050. __func__, i);
  2051. }
  2052. }
  2053. pm_qos_bail:
  2054. mutex_unlock(&dev->lock);
  2055. cvp_dsp_send_hfi_queue();
  2056. pm_relax(dev->res->pdev->dev.parent);
  2057. dprintk(CVP_CORE, "Core inited successfully\n");
  2058. return 0;
  2059. err_core_init:
  2060. __set_state(dev, IRIS_STATE_DEINIT);
  2061. __unload_fw(dev);
  2062. if (dev->mmrm_cvp)
  2063. {
  2064. msm_cvp_mmrm_deregister(dev);
  2065. }
  2066. err_load_fw:
  2067. __hwfence_regs_unmap(dev);
  2068. err_no_mem:
  2069. dprintk(CVP_ERR, "Core init failed\n");
  2070. mutex_unlock(&dev->lock);
  2071. pm_relax(dev->res->pdev->dev.parent);
  2072. return rc;
  2073. }
  2074. static int iris_hfi_core_release(void *dev)
  2075. {
  2076. int rc = 0, i;
  2077. struct iris_hfi_device *device = dev;
  2078. struct cvp_hal_session *session, *next;
  2079. struct dev_pm_qos_request *qos_hdl;
  2080. u32 ipcc_iova;
  2081. if (!device) {
  2082. dprintk(CVP_ERR, "invalid device\n");
  2083. return -ENODEV;
  2084. }
  2085. mutex_lock(&device->lock);
  2086. dprintk(CVP_WARN, "Core releasing\n");
  2087. if (device->res->pm_qos.latency_us &&
  2088. device->res->pm_qos.pm_qos_hdls) {
  2089. for (i = 0; i < device->res->pm_qos.silver_count; i++) {
  2090. if (!cpu_possible(device->res->pm_qos.silver_cores[i]))
  2091. continue;
  2092. qos_hdl = &device->res->pm_qos.pm_qos_hdls[i];
  2093. if ((qos_hdl != NULL) && dev_pm_qos_request_active(qos_hdl))
  2094. dev_pm_qos_remove_request(qos_hdl);
  2095. }
  2096. kfree(device->res->pm_qos.pm_qos_hdls);
  2097. device->res->pm_qos.pm_qos_hdls = NULL;
  2098. }
  2099. __resume(device);
  2100. __set_state(device, IRIS_STATE_DEINIT);
  2101. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  2102. if (rc)
  2103. dprintk(CVP_WARN, "Failed to suspend cvp FW%d\n", rc);
  2104. __dsp_shutdown(device);
  2105. __disable_subcaches(device);
  2106. ipcc_iova = __read_register(device, CVP_MMAP_ADDR);
  2107. msm_cvp_unmap_ipcc_regs(ipcc_iova);
  2108. __unload_fw(device);
  2109. __hwfence_regs_unmap(device);
  2110. if (msm_cvp_mmrm_enabled) {
  2111. rc = msm_cvp_mmrm_deregister(device);
  2112. if (rc) {
  2113. dprintk(CVP_ERR,
  2114. "%s: Failed msm_cvp_mmrm_deregister:%d\n",
  2115. __func__, rc);
  2116. }
  2117. }
  2118. /* unlink all sessions from device */
  2119. list_for_each_entry_safe(session, next, &device->sess_head, list) {
  2120. list_del(&session->list);
  2121. session->device = NULL;
  2122. }
  2123. dprintk(CVP_CORE, "Core released successfully\n");
  2124. mutex_unlock(&device->lock);
  2125. return rc;
  2126. }
  2127. static void __core_clear_interrupt(struct iris_hfi_device *device)
  2128. {
  2129. u32 intr_status = 0, mask = 0;
  2130. if (!device) {
  2131. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2132. return;
  2133. }
  2134. intr_status = __read_register(device, CVP_WRAPPER_INTR_STATUS);
  2135. mask = (CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK | CVP_FATAL_INTR_BMSK);
  2136. if (intr_status & mask) {
  2137. device->intr_status |= intr_status;
  2138. device->reg_count++;
  2139. dprintk(CVP_CORE,
  2140. "INTERRUPT for device: %pK: times: %d status: %d\n",
  2141. device, device->reg_count, intr_status);
  2142. } else {
  2143. device->spur_count++;
  2144. }
  2145. __write_register(device, CVP_CPU_CS_A2HSOFTINTCLR, 1);
  2146. }
  2147. static int iris_hfi_core_trigger_ssr(void *device,
  2148. enum hal_ssr_trigger_type type)
  2149. {
  2150. struct cvp_hfi_cmd_sys_test_ssr_packet pkt;
  2151. int rc = 0;
  2152. struct iris_hfi_device *dev;
  2153. cvp_free_va_md_list();
  2154. if (!device) {
  2155. dprintk(CVP_ERR, "invalid device\n");
  2156. return -ENODEV;
  2157. }
  2158. dev = device;
  2159. if (mutex_trylock(&dev->lock)) {
  2160. rc = call_hfi_pkt_op(dev, ssr_cmd, type, &pkt);
  2161. if (rc) {
  2162. dprintk(CVP_ERR, "%s: failed to create packet\n",
  2163. __func__);
  2164. goto err_create_pkt;
  2165. }
  2166. if (__iface_cmdq_write(dev, &pkt))
  2167. rc = -ENOTEMPTY;
  2168. } else {
  2169. return -EAGAIN;
  2170. }
  2171. err_create_pkt:
  2172. mutex_unlock(&dev->lock);
  2173. return rc;
  2174. }
  2175. static void __set_default_sys_properties(struct iris_hfi_device *device)
  2176. {
  2177. if (__sys_set_debug(device, msm_cvp_fw_debug))
  2178. dprintk(CVP_WARN, "Setting fw_debug msg ON failed\n");
  2179. if (__sys_set_power_control(device, msm_cvp_fw_low_power_mode))
  2180. dprintk(CVP_WARN, "Setting h/w power collapse ON failed\n");
  2181. }
  2182. static void __session_clean(struct cvp_hal_session *session)
  2183. {
  2184. struct cvp_hal_session *temp, *next;
  2185. struct iris_hfi_device *device;
  2186. if (!session || !session->device) {
  2187. dprintk(CVP_WARN, "%s: invalid params\n", __func__);
  2188. return;
  2189. }
  2190. device = session->device;
  2191. dprintk(CVP_SESS, "deleted the session: %pK\n", session);
  2192. /*
  2193. * session might have been removed from the device list in
  2194. * core_release, so check and remove if it is in the list
  2195. */
  2196. list_for_each_entry_safe(temp, next, &device->sess_head, list) {
  2197. if (session == temp) {
  2198. list_del(&session->list);
  2199. break;
  2200. }
  2201. }
  2202. /* Poison the session handle with zeros */
  2203. *session = (struct cvp_hal_session){ {0} };
  2204. kfree(session);
  2205. }
  2206. static int iris_hfi_session_clean(void *session)
  2207. {
  2208. struct cvp_hal_session *sess_close;
  2209. struct iris_hfi_device *device;
  2210. if (!session) {
  2211. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2212. return -EINVAL;
  2213. }
  2214. sess_close = session;
  2215. device = sess_close->device;
  2216. if (!device) {
  2217. dprintk(CVP_ERR, "Invalid device handle %s\n", __func__);
  2218. return -EINVAL;
  2219. }
  2220. mutex_lock(&device->lock);
  2221. __session_clean(sess_close);
  2222. mutex_unlock(&device->lock);
  2223. return 0;
  2224. }
  2225. static int iris_debug_hook(void *device)
  2226. {
  2227. struct iris_hfi_device *dev = device;
  2228. u32 val;
  2229. if (!device) {
  2230. dprintk(CVP_ERR, "%s Invalid device\n", __func__);
  2231. return -ENODEV;
  2232. }
  2233. //__write_register(dev, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0x11);
  2234. //__write_register(dev, CVP_WRAPPER_TZ_CPU_CLOCK_CONFIG, 0x1);
  2235. dprintk(CVP_ERR, "Halt Tensilica and core and axi\n");
  2236. return 0;
  2237. /******* FDU & MPU *****/
  2238. #define CVP0_CVP_SS_FDU_SECURE_ENABLE 0x90
  2239. #define CVP0_CVP_SS_MPU_SECURE_ENABLE 0x94
  2240. #define CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE 0xA0
  2241. #define CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE 0xA4
  2242. #define CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE 0xA8
  2243. #define CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE 0xAC
  2244. val = __read_register(dev, CVP0_CVP_SS_FDU_SECURE_ENABLE);
  2245. dprintk(CVP_ERR, "FDU_SECURE_ENABLE %#x\n", val);
  2246. val = __read_register(dev, CVP0_CVP_SS_MPU_SECURE_ENABLE);
  2247. dprintk(CVP_ERR, "MPU_SECURE_ENABLE %#x\n", val);
  2248. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_0_SECURE_ENABLE);
  2249. dprintk(CVP_ERR, "ARP_THREAD_0_SECURE_ENABLE %#x\n", val);
  2250. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_1_SECURE_ENABLE);
  2251. dprintk(CVP_ERR, "ARP_THREAD_1_SECURE_ENABLE %#x\n", val);
  2252. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_2_SECURE_ENABLE);
  2253. dprintk(CVP_ERR, "ARP_THREAD_2_SECURE_ENABLE %#x\n", val);
  2254. val = __read_register(dev, CVP0_CVP_SS_ARP_THREAD_3_SECURE_ENABLE);
  2255. dprintk(CVP_ERR, "ARP_THREAD_3_SECURE_ENABLE %#x\n", val);
  2256. if (true)
  2257. return 0;
  2258. /***** GCE *******
  2259. * Bit 0 of below register is CDM secure enable for GCE
  2260. * CDM buffer will be in CB4 if set
  2261. */
  2262. #define CVP_GCE_GCE_SS_CP_CTL 0x51100
  2263. /* STATUS bit0 && CFG bit 4 of below register set,
  2264. * expect pixel buffers in CB3,
  2265. * otherwise in CB0
  2266. * CFG bit 9:8 b01 -> LMC input in CB3
  2267. * CFG bit 9:8 b10 -> LMC input in CB4
  2268. */
  2269. #define CVP_GCE0_CP_STATUS 0x51080
  2270. #define CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG 0x52020
  2271. val = __read_register(dev, CVP_GCE_GCE_SS_CP_CTL);
  2272. dprintk(CVP_ERR, "CVP_GCE_GCE_SS_CP_CTL %#x\n", val);
  2273. val = __read_register(dev, CVP_GCE0_CP_STATUS);
  2274. dprintk(CVP_ERR, "CVP_GCE0_CP_STATUS %#x\n", val);
  2275. val = __read_register(dev, CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG);
  2276. dprintk(CVP_ERR, "CVP_GCE0_BIU_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2277. /***** RGE *****
  2278. * Bit 0 of below regiser is CDM secure enable for RGE
  2279. * CDM buffer to be in CB4 i fset
  2280. */
  2281. #define CVP_RGE0_TOPRGE_CP_CTL 0x31010
  2282. /* CFG bit 4 && IN bit 0:
  2283. * if both are set, expect CB3 or CB4 depending on IN 6:4 field
  2284. * either is clear, expect CB0
  2285. */
  2286. #define CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG 0x32020
  2287. #define CVP_RGE0_TOPSPARE_IN 0x311F4
  2288. val = __read_register(dev, CVP_RGE0_TOPRGE_CP_CTL);
  2289. dprintk(CVP_ERR, "CVP_RGE0_TOPRGE_CP_CTL %#x\n", val);
  2290. val = __read_register(dev, CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2291. dprintk(CVP_ERR, "CVP_RGE0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2292. val = __read_register(dev, CVP_RGE0_TOPSPARE_IN);
  2293. dprintk(CVP_ERR, "CVP_RGE0_TOPSPARE_IN %#x\n", val);
  2294. /****** VADL ******
  2295. * Bit 0 of below register is CDM secure enable for VADL
  2296. * CDM buffer will bei in CB4 if set
  2297. */
  2298. #define CVP_VADL0_VADL_SS_CP_CTL 0x21010
  2299. /* Below registers are used the same way as RGE */
  2300. #define CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG 0x22020
  2301. #define CVP_VADL0_SPARE_IN 0x211F4
  2302. val = __read_register(dev, CVP_VADL0_VADL_SS_CP_CTL);
  2303. dprintk(CVP_ERR, "CVP_VADL0_VADL_SS_CP_CTL %#x\n", val);
  2304. val = __read_register(dev, CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2305. dprintk(CVP_ERR, "CVP_VADL0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2306. val = __read_register(dev, CVP_VADL0_SPARE_IN);
  2307. dprintk(CVP_ERR, "CVP_VADL0_SPARE_IN %#x\n", val);
  2308. /****** ITOF *****
  2309. * Below registers are used the same way as RGE
  2310. */
  2311. #define CVP_ITOF0_TOF_SS_CP_CTL 0x41010
  2312. #define CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG 0x42020
  2313. #define CVP_ITOF0_TOF_SS_SPARE_IN 0x411F4
  2314. val = __read_register(dev, CVP_ITOF0_TOF_SS_CP_CTL);
  2315. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_CP_CTL %#x\n", val);
  2316. val = __read_register(dev, CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG);
  2317. dprintk(CVP_ERR, "CVP_ITOF0_BUS_RD_INPUT_IF_SECURITY_CFG %#x\n", val);
  2318. val = __read_register(dev, CVP_ITOF0_TOF_SS_SPARE_IN);
  2319. dprintk(CVP_ERR, "CVP_ITOF0_TOF_SS_SPARE_IN %#x\n", val);
  2320. return 0;
  2321. }
  2322. static int iris_hfi_session_init(void *device, void *session_id,
  2323. void **new_session)
  2324. {
  2325. struct cvp_hfi_cmd_sys_session_init_packet pkt;
  2326. struct iris_hfi_device *dev;
  2327. struct cvp_hal_session *s;
  2328. if (!device || !new_session) {
  2329. dprintk(CVP_ERR, "%s - invalid input\n", __func__);
  2330. return -EINVAL;
  2331. }
  2332. dev = device;
  2333. mutex_lock(&dev->lock);
  2334. s = kzalloc(sizeof(*s), GFP_KERNEL);
  2335. if (!s) {
  2336. dprintk(CVP_ERR, "new session fail: Out of memory\n");
  2337. goto err_session_init_fail;
  2338. }
  2339. s->session_id = session_id;
  2340. s->device = dev;
  2341. dprintk(CVP_SESS,
  2342. "%s: inst %pK, session %pK\n", __func__, session_id, s);
  2343. list_add_tail(&s->list, &dev->sess_head);
  2344. __set_default_sys_properties(device);
  2345. if (call_hfi_pkt_op(dev, session_init, &pkt, s)) {
  2346. dprintk(CVP_ERR, "session_init: failed to create packet\n");
  2347. goto err_session_init_fail;
  2348. }
  2349. *new_session = s;
  2350. if (__iface_cmdq_write(dev, &pkt))
  2351. goto err_session_init_fail;
  2352. mutex_unlock(&dev->lock);
  2353. return 0;
  2354. err_session_init_fail:
  2355. if (s)
  2356. __session_clean(s);
  2357. *new_session = NULL;
  2358. mutex_unlock(&dev->lock);
  2359. return -EINVAL;
  2360. }
  2361. static int __send_session_cmd(struct cvp_hal_session *session, int pkt_type)
  2362. {
  2363. struct cvp_hal_session_cmd_pkt pkt;
  2364. int rc = 0;
  2365. struct iris_hfi_device *device = session->device;
  2366. if (!__is_session_valid(device, session, __func__))
  2367. return -ECONNRESET;
  2368. rc = call_hfi_pkt_op(device, session_cmd,
  2369. &pkt, pkt_type, session);
  2370. if (rc == -EPERM)
  2371. return 0;
  2372. if (rc) {
  2373. dprintk(CVP_ERR, "send session cmd: create pkt failed\n");
  2374. goto err_create_pkt;
  2375. }
  2376. if (__iface_cmdq_write(session->device, &pkt))
  2377. rc = -ENOTEMPTY;
  2378. err_create_pkt:
  2379. return rc;
  2380. }
  2381. static int iris_hfi_session_end(void *session)
  2382. {
  2383. struct cvp_hal_session *sess;
  2384. struct iris_hfi_device *device;
  2385. int rc = 0;
  2386. if (!session) {
  2387. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2388. return -EINVAL;
  2389. }
  2390. sess = session;
  2391. device = sess->device;
  2392. if (!device) {
  2393. dprintk(CVP_ERR, "Invalid session %s\n", __func__);
  2394. return -EINVAL;
  2395. }
  2396. mutex_lock(&device->lock);
  2397. if (msm_cvp_fw_coverage) {
  2398. if (__sys_set_coverage(sess->device, msm_cvp_fw_coverage))
  2399. dprintk(CVP_WARN, "Fw_coverage msg ON failed\n");
  2400. }
  2401. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_END);
  2402. mutex_unlock(&device->lock);
  2403. return rc;
  2404. }
  2405. static int iris_hfi_session_abort(void *sess)
  2406. {
  2407. struct cvp_hal_session *session = sess;
  2408. struct iris_hfi_device *device;
  2409. int rc = 0;
  2410. if (!session || !session->device) {
  2411. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2412. return -EINVAL;
  2413. }
  2414. device = session->device;
  2415. mutex_lock(&device->lock);
  2416. rc = __send_session_cmd(session, HFI_CMD_SYS_SESSION_ABORT);
  2417. mutex_unlock(&device->lock);
  2418. return rc;
  2419. }
  2420. static int iris_hfi_session_set_buffers(void *sess, u32 iova, u32 size)
  2421. {
  2422. struct cvp_hfi_cmd_session_set_buffers_packet pkt;
  2423. int rc = 0;
  2424. struct cvp_hal_session *session = sess;
  2425. struct iris_hfi_device *device;
  2426. if (!session || !session->device || !iova || !size) {
  2427. dprintk(CVP_ERR, "Invalid Params\n");
  2428. return -EINVAL;
  2429. }
  2430. device = session->device;
  2431. mutex_lock(&device->lock);
  2432. if (!__is_session_valid(device, session, __func__)) {
  2433. rc = -ECONNRESET;
  2434. goto err_create_pkt;
  2435. }
  2436. rc = call_hfi_pkt_op(device, session_set_buffers,
  2437. &pkt, session, iova, size);
  2438. if (rc) {
  2439. dprintk(CVP_ERR, "set buffers: failed to create packet\n");
  2440. goto err_create_pkt;
  2441. }
  2442. if (__iface_cmdq_write(session->device, &pkt))
  2443. rc = -ENOTEMPTY;
  2444. err_create_pkt:
  2445. mutex_unlock(&device->lock);
  2446. return rc;
  2447. }
  2448. static int iris_hfi_session_release_buffers(void *sess)
  2449. {
  2450. struct cvp_session_release_buffers_packet pkt;
  2451. int rc = 0;
  2452. struct cvp_hal_session *session = sess;
  2453. struct iris_hfi_device *device;
  2454. if (!session || !session->device) {
  2455. dprintk(CVP_ERR, "Invalid Params\n");
  2456. return -EINVAL;
  2457. }
  2458. device = session->device;
  2459. mutex_lock(&device->lock);
  2460. if (!__is_session_valid(device, session, __func__)) {
  2461. rc = -ECONNRESET;
  2462. goto err_create_pkt;
  2463. }
  2464. rc = call_hfi_pkt_op(device, session_release_buffers, &pkt, session);
  2465. if (rc) {
  2466. dprintk(CVP_ERR, "release buffers: failed to create packet\n");
  2467. goto err_create_pkt;
  2468. }
  2469. if (__iface_cmdq_write(session->device, &pkt))
  2470. rc = -ENOTEMPTY;
  2471. err_create_pkt:
  2472. mutex_unlock(&device->lock);
  2473. return rc;
  2474. }
  2475. static int iris_hfi_session_send(void *sess,
  2476. struct eva_kmd_hfi_packet *in_pkt)
  2477. {
  2478. int rc = 0;
  2479. struct eva_kmd_hfi_packet pkt;
  2480. struct cvp_hal_session *session = sess;
  2481. struct iris_hfi_device *device;
  2482. if (!session || !session->device) {
  2483. dprintk(CVP_ERR, "invalid session");
  2484. return -ENODEV;
  2485. }
  2486. device = session->device;
  2487. mutex_lock(&device->lock);
  2488. if (!__is_session_valid(device, session, __func__)) {
  2489. rc = -ECONNRESET;
  2490. goto err_send_pkt;
  2491. }
  2492. rc = call_hfi_pkt_op(device, session_send,
  2493. &pkt, session, in_pkt);
  2494. if (rc) {
  2495. dprintk(CVP_ERR,
  2496. "failed to create pkt\n");
  2497. goto err_send_pkt;
  2498. }
  2499. if (__iface_cmdq_write(session->device, &pkt))
  2500. rc = -ENOTEMPTY;
  2501. err_send_pkt:
  2502. mutex_unlock(&device->lock);
  2503. return rc;
  2504. return rc;
  2505. }
  2506. static int iris_hfi_session_flush(void *sess)
  2507. {
  2508. struct cvp_hal_session *session = sess;
  2509. struct iris_hfi_device *device;
  2510. int rc = 0;
  2511. if (!session || !session->device) {
  2512. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2513. return -EINVAL;
  2514. }
  2515. device = session->device;
  2516. mutex_lock(&device->lock);
  2517. rc = __send_session_cmd(session, HFI_CMD_SESSION_CVP_FLUSH);
  2518. mutex_unlock(&device->lock);
  2519. return rc;
  2520. }
  2521. static int iris_hfi_session_start(void *sess)
  2522. {
  2523. struct cvp_hal_session *session = sess;
  2524. struct iris_hfi_device *device;
  2525. int rc = 0;
  2526. if (!session || !session->device) {
  2527. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2528. return -EINVAL;
  2529. }
  2530. device = session->device;
  2531. mutex_lock(&device->lock);
  2532. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_START);
  2533. mutex_unlock(&device->lock);
  2534. return rc;
  2535. }
  2536. static int iris_hfi_session_stop(void *sess)
  2537. {
  2538. struct cvp_hal_session *session = sess;
  2539. struct iris_hfi_device *device;
  2540. int rc = 0;
  2541. if (!session || !session->device) {
  2542. dprintk(CVP_ERR, "Invalid Params %s\n", __func__);
  2543. return -EINVAL;
  2544. }
  2545. device = session->device;
  2546. mutex_lock(&device->lock);
  2547. rc = __send_session_cmd(session, HFI_CMD_SESSION_EVA_STOP);
  2548. mutex_unlock(&device->lock);
  2549. return rc;
  2550. }
  2551. static void __process_fatal_error(
  2552. struct iris_hfi_device *device)
  2553. {
  2554. struct msm_cvp_cb_cmd_done cmd_done = {0};
  2555. device->callback(HAL_SYS_ERROR, &cmd_done);
  2556. }
  2557. static int __prepare_pc(struct iris_hfi_device *device)
  2558. {
  2559. int rc = 0;
  2560. struct cvp_hfi_cmd_sys_pc_prep_packet pkt;
  2561. rc = call_hfi_pkt_op(device, sys_pc_prep, &pkt);
  2562. if (rc) {
  2563. dprintk(CVP_ERR, "Failed to create sys pc prep pkt\n");
  2564. goto err_pc_prep;
  2565. }
  2566. if (__iface_cmdq_write(device, &pkt))
  2567. rc = -ENOTEMPTY;
  2568. if (rc)
  2569. dprintk(CVP_ERR, "Failed to prepare iris for power off");
  2570. err_pc_prep:
  2571. return rc;
  2572. }
  2573. static void iris_hfi_pm_handler(struct work_struct *work)
  2574. {
  2575. int rc = 0;
  2576. struct msm_cvp_core *core;
  2577. struct iris_hfi_device *device;
  2578. core = cvp_driver->cvp_core;
  2579. if (core)
  2580. device = core->dev_ops->hfi_device_data;
  2581. else
  2582. return;
  2583. if (!device) {
  2584. dprintk(CVP_ERR, "%s: NULL device\n", __func__);
  2585. return;
  2586. }
  2587. dprintk(CVP_PWR,
  2588. "Entering %s\n", __func__);
  2589. /*
  2590. * It is ok to check this variable outside the lock since
  2591. * it is being updated in this context only
  2592. */
  2593. if (device->skip_pc_count >= CVP_MAX_PC_SKIP_COUNT) {
  2594. dprintk(CVP_WARN, "Failed to PC for %d times\n",
  2595. device->skip_pc_count);
  2596. device->skip_pc_count = 0;
  2597. __process_fatal_error(device);
  2598. return;
  2599. }
  2600. mutex_lock(&device->lock);
  2601. if (gfa_cv.state == DSP_SUSPEND)
  2602. rc = __power_collapse(device, true);
  2603. else
  2604. rc = __power_collapse(device, false);
  2605. mutex_unlock(&device->lock);
  2606. switch (rc) {
  2607. case 0:
  2608. device->skip_pc_count = 0;
  2609. /* Cancel pending delayed works if any */
  2610. cancel_delayed_work(&iris_hfi_pm_work);
  2611. dprintk(CVP_PWR, "%s: power collapse successful!\n",
  2612. __func__);
  2613. break;
  2614. case -EBUSY:
  2615. device->skip_pc_count = 0;
  2616. dprintk(CVP_PWR, "%s: retry PC as cvp is busy\n", __func__);
  2617. queue_delayed_work(device->iris_pm_workq,
  2618. &iris_hfi_pm_work, msecs_to_jiffies(
  2619. device->res->msm_cvp_pwr_collapse_delay));
  2620. break;
  2621. case -EAGAIN:
  2622. device->skip_pc_count++;
  2623. dprintk(CVP_WARN, "%s: retry power collapse (count %d)\n",
  2624. __func__, device->skip_pc_count);
  2625. queue_delayed_work(device->iris_pm_workq,
  2626. &iris_hfi_pm_work, msecs_to_jiffies(
  2627. device->res->msm_cvp_pwr_collapse_delay));
  2628. break;
  2629. default:
  2630. dprintk(CVP_ERR, "%s: power collapse failed\n", __func__);
  2631. break;
  2632. }
  2633. }
  2634. static int __power_collapse(struct iris_hfi_device *device, bool force)
  2635. {
  2636. int rc = 0;
  2637. u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
  2638. int count = 0;
  2639. const int max_tries = 150;
  2640. if (!device) {
  2641. dprintk(CVP_ERR, "%s: invalid params\n", __func__);
  2642. return -EINVAL;
  2643. }
  2644. if (!device->power_enabled) {
  2645. dprintk(CVP_PWR, "%s: Power already disabled\n",
  2646. __func__);
  2647. goto exit;
  2648. }
  2649. rc = __core_in_valid_state(device);
  2650. if (!rc) {
  2651. dprintk(CVP_WARN,
  2652. "Core is in bad state, Skipping power collapse\n");
  2653. return -EINVAL;
  2654. }
  2655. rc = __dsp_suspend(device, force);
  2656. if (rc == -EBUSY)
  2657. goto exit;
  2658. else if (rc)
  2659. goto skip_power_off;
  2660. __flush_debug_queue(device, device->raw_packet);
  2661. pc_ready = __read_register(device, CVP_CTRL_STATUS) &
  2662. CVP_CTRL_STATUS_PC_READY;
  2663. if (!pc_ready) {
  2664. wfi_status = __read_register(device,
  2665. CVP_WRAPPER_CPU_STATUS);
  2666. idle_status = __read_register(device,
  2667. CVP_CTRL_STATUS);
  2668. if (!(wfi_status & BIT(0))) {
  2669. dprintk(CVP_WARN,
  2670. "Skipping PC as wfi_status (%#x) bit not set\n",
  2671. wfi_status);
  2672. goto skip_power_off;
  2673. }
  2674. if (!(idle_status & BIT(30))) {
  2675. dprintk(CVP_WARN,
  2676. "Skipping PC as idle_status (%#x) bit not set\n",
  2677. idle_status);
  2678. goto skip_power_off;
  2679. }
  2680. rc = __prepare_pc(device);
  2681. if (rc) {
  2682. dprintk(CVP_WARN, "Failed PC %d\n", rc);
  2683. goto skip_power_off;
  2684. }
  2685. while (count < max_tries) {
  2686. wfi_status = __read_register(device,
  2687. CVP_WRAPPER_CPU_STATUS);
  2688. pc_ready = __read_register(device,
  2689. CVP_CTRL_STATUS);
  2690. if ((wfi_status & BIT(0)) && (pc_ready &
  2691. CVP_CTRL_STATUS_PC_READY))
  2692. break;
  2693. usleep_range(150, 250);
  2694. count++;
  2695. }
  2696. if (count == max_tries) {
  2697. dprintk(CVP_ERR,
  2698. "Skip PC. Core is not ready (%#x, %#x)\n",
  2699. wfi_status, pc_ready);
  2700. goto skip_power_off;
  2701. }
  2702. } else {
  2703. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  2704. if (!(wfi_status & BIT(0))) {
  2705. dprintk(CVP_WARN,
  2706. "Skip PC as wfi_status (%#x) bit not set\n",
  2707. wfi_status);
  2708. goto skip_power_off;
  2709. }
  2710. }
  2711. rc = __suspend(device);
  2712. if (rc)
  2713. dprintk(CVP_ERR, "Failed __suspend\n");
  2714. exit:
  2715. return rc;
  2716. skip_power_off:
  2717. dprintk(CVP_PWR, "Skip PC(%#x, %#x, %#x)\n",
  2718. wfi_status, idle_status, pc_ready);
  2719. __flush_debug_queue(device, device->raw_packet);
  2720. return -EAGAIN;
  2721. }
  2722. static void __process_sys_error(struct iris_hfi_device *device)
  2723. {
  2724. struct cvp_hfi_sfr_struct *vsfr = NULL;
  2725. vsfr = (struct cvp_hfi_sfr_struct *)device->sfr.align_virtual_addr;
  2726. if (vsfr) {
  2727. void *p = memchr(vsfr->rg_data, '\0', vsfr->bufSize);
  2728. /*
  2729. * SFR isn't guaranteed to be NULL terminated
  2730. * since SYS_ERROR indicates that Iris is in the
  2731. * process of crashing.
  2732. */
  2733. if (p == NULL)
  2734. vsfr->rg_data[vsfr->bufSize - 1] = '\0';
  2735. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2736. vsfr->rg_data);
  2737. }
  2738. }
  2739. static void __flush_debug_queue(struct iris_hfi_device *device, u8 *packet)
  2740. {
  2741. bool local_packet = false;
  2742. enum cvp_msg_prio log_level = CVP_FW;
  2743. if (!device) {
  2744. dprintk(CVP_ERR, "%s: Invalid params\n", __func__);
  2745. return;
  2746. }
  2747. if (!packet) {
  2748. packet = kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  2749. if (!packet) {
  2750. dprintk(CVP_ERR, "In %s() Fail to allocate mem\n",
  2751. __func__);
  2752. return;
  2753. }
  2754. local_packet = true;
  2755. /*
  2756. * Local packek is used when something FATAL occurred.
  2757. * It is good to print these logs by default.
  2758. */
  2759. log_level = CVP_ERR;
  2760. }
  2761. #define SKIP_INVALID_PKT(pkt_size, payload_size, pkt_hdr_size) ({ \
  2762. if (pkt_size < pkt_hdr_size || \
  2763. payload_size < MIN_PAYLOAD_SIZE || \
  2764. payload_size > \
  2765. (pkt_size - pkt_hdr_size + sizeof(u8))) { \
  2766. dprintk(CVP_ERR, \
  2767. "%s: invalid msg size - %d\n", \
  2768. __func__, pkt->msg_size); \
  2769. continue; \
  2770. } \
  2771. })
  2772. while (!__iface_dbgq_read(device, packet)) {
  2773. struct cvp_hfi_packet_header *pkt =
  2774. (struct cvp_hfi_packet_header *) packet;
  2775. if (pkt->size < sizeof(struct cvp_hfi_packet_header)) {
  2776. dprintk(CVP_ERR, "Invalid pkt size - %s\n",
  2777. __func__);
  2778. continue;
  2779. }
  2780. if (pkt->packet_type == HFI_MSG_SYS_DEBUG) {
  2781. struct cvp_hfi_msg_sys_debug_packet *pkt =
  2782. (struct cvp_hfi_msg_sys_debug_packet *) packet;
  2783. SKIP_INVALID_PKT(pkt->size,
  2784. pkt->msg_size, sizeof(*pkt));
  2785. /*
  2786. * All fw messages starts with new line character. This
  2787. * causes dprintk to print this message in two lines
  2788. * in the kernel log. Ignoring the first character
  2789. * from the message fixes this to print it in a single
  2790. * line.
  2791. */
  2792. pkt->rg_msg_data[pkt->msg_size-1] = '\0';
  2793. dprintk(log_level, "%s", &pkt->rg_msg_data[1]);
  2794. }
  2795. }
  2796. #undef SKIP_INVALID_PKT
  2797. if (local_packet)
  2798. kfree(packet);
  2799. }
  2800. static bool __is_session_valid(struct iris_hfi_device *device,
  2801. struct cvp_hal_session *session, const char *func)
  2802. {
  2803. struct cvp_hal_session *temp = NULL;
  2804. if (!device || !session)
  2805. goto invalid;
  2806. list_for_each_entry(temp, &device->sess_head, list)
  2807. if (session == temp)
  2808. return true;
  2809. invalid:
  2810. dprintk(CVP_WARN, "%s: device %pK, invalid session %pK\n",
  2811. func, device, session);
  2812. return false;
  2813. }
  2814. static struct cvp_hal_session *__get_session(struct iris_hfi_device *device,
  2815. u32 session_id)
  2816. {
  2817. struct cvp_hal_session *temp = NULL;
  2818. list_for_each_entry(temp, &device->sess_head, list) {
  2819. if (session_id == hash32_ptr(temp))
  2820. return temp;
  2821. }
  2822. return NULL;
  2823. }
  2824. #define _INVALID_MSG_ "Unrecognized MSG (%#x) session (%pK), discarding\n"
  2825. #define _INVALID_STATE_ "Ignore responses from %d to %d invalid state\n"
  2826. #define _DEVFREQ_FAIL_ "Failed to add devfreq device bus %s governor %s: %d\n"
  2827. static void process_system_msg(struct msm_cvp_cb_info *info,
  2828. struct iris_hfi_device *device,
  2829. void *raw_packet)
  2830. {
  2831. struct cvp_hal_sys_init_done sys_init_done = {0};
  2832. switch (info->response_type) {
  2833. case HAL_SYS_ERROR:
  2834. __process_sys_error(device);
  2835. break;
  2836. case HAL_SYS_RELEASE_RESOURCE_DONE:
  2837. dprintk(CVP_CORE, "Received SYS_RELEASE_RESOURCE\n");
  2838. break;
  2839. case HAL_SYS_INIT_DONE:
  2840. dprintk(CVP_CORE, "Received SYS_INIT_DONE\n");
  2841. sys_init_done.capabilities =
  2842. device->sys_init_capabilities;
  2843. cvp_hfi_process_sys_init_done_prop_read(
  2844. (struct cvp_hfi_msg_sys_init_done_packet *)
  2845. raw_packet, &sys_init_done);
  2846. info->response.cmd.data.sys_init_done = sys_init_done;
  2847. break;
  2848. default:
  2849. break;
  2850. }
  2851. }
  2852. static void **get_session_id(struct msm_cvp_cb_info *info)
  2853. {
  2854. void **session_id = NULL;
  2855. /* For session-related packets, validate session */
  2856. switch (info->response_type) {
  2857. case HAL_SESSION_INIT_DONE:
  2858. case HAL_SESSION_END_DONE:
  2859. case HAL_SESSION_ABORT_DONE:
  2860. case HAL_SESSION_START_DONE:
  2861. case HAL_SESSION_STOP_DONE:
  2862. case HAL_SESSION_FLUSH_DONE:
  2863. case HAL_SESSION_SET_BUFFER_DONE:
  2864. case HAL_SESSION_SUSPEND_DONE:
  2865. case HAL_SESSION_RESUME_DONE:
  2866. case HAL_SESSION_SET_PROP_DONE:
  2867. case HAL_SESSION_GET_PROP_DONE:
  2868. case HAL_SESSION_RELEASE_BUFFER_DONE:
  2869. case HAL_SESSION_REGISTER_BUFFER_DONE:
  2870. case HAL_SESSION_UNREGISTER_BUFFER_DONE:
  2871. case HAL_SESSION_PROPERTY_INFO:
  2872. case HAL_SESSION_EVENT_CHANGE:
  2873. case HAL_SESSION_DUMP_NOTIFY:
  2874. case HAL_SESSION_ERROR:
  2875. session_id = &info->response.cmd.session_id;
  2876. break;
  2877. case HAL_RESPONSE_UNUSED:
  2878. default:
  2879. session_id = NULL;
  2880. break;
  2881. }
  2882. return session_id;
  2883. }
  2884. static void print_msg_hdr(void *hdr)
  2885. {
  2886. struct cvp_hfi_msg_session_hdr *new_hdr =
  2887. (struct cvp_hfi_msg_session_hdr *)hdr;
  2888. dprintk(CVP_HFI, "HFI MSG received: %x %x %x %x %x %x %x %#llx\n",
  2889. new_hdr->size, new_hdr->packet_type,
  2890. new_hdr->session_id,
  2891. new_hdr->client_data.transaction_id,
  2892. new_hdr->client_data.data1,
  2893. new_hdr->client_data.data2,
  2894. new_hdr->error_type,
  2895. new_hdr->client_data.kdata);
  2896. }
  2897. static int __response_handler(struct iris_hfi_device *device)
  2898. {
  2899. struct msm_cvp_cb_info *packets;
  2900. int packet_count = 0;
  2901. u8 *raw_packet = NULL;
  2902. bool requeue_pm_work = true;
  2903. if (!device || device->state != IRIS_STATE_INIT)
  2904. return 0;
  2905. packets = device->response_pkt;
  2906. raw_packet = device->raw_packet;
  2907. if (!raw_packet || !packets) {
  2908. dprintk(CVP_ERR,
  2909. "%s: Invalid args : Res pkt = %pK, Raw pkt = %pK\n",
  2910. __func__, packets, raw_packet);
  2911. return 0;
  2912. }
  2913. if (device->intr_status & CVP_FATAL_INTR_BMSK) {
  2914. struct cvp_hfi_sfr_struct *vsfr = (struct cvp_hfi_sfr_struct *)
  2915. device->sfr.align_virtual_addr;
  2916. struct msm_cvp_cb_info info = {
  2917. .response_type = HAL_SYS_WATCHDOG_TIMEOUT,
  2918. .response.cmd = {
  2919. .device_id = 0,
  2920. }
  2921. };
  2922. if (vsfr)
  2923. dprintk(CVP_ERR, "SFR Message from FW: %s\n",
  2924. vsfr->rg_data);
  2925. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CPU_NOC_BMSK)
  2926. dprintk(CVP_ERR, "Received Xtensa NOC error\n");
  2927. if (device->intr_status & CVP_WRAPPER_INTR_MASK_CORE_NOC_BMSK)
  2928. dprintk(CVP_ERR, "Received CVP core NOC error\n");
  2929. if (device->intr_status & CVP_WRAPPER_INTR_MASK_A2HWD_BMSK)
  2930. dprintk(CVP_ERR, "Received CVP watchdog timeout\n");
  2931. packets[packet_count++] = info;
  2932. goto exit;
  2933. }
  2934. /* Bleed the msg queue dry of packets */
  2935. while (!__iface_msgq_read(device, raw_packet)) {
  2936. void **session_id = NULL;
  2937. struct msm_cvp_cb_info *info = &packets[packet_count++];
  2938. struct cvp_hfi_msg_session_hdr *hdr =
  2939. (struct cvp_hfi_msg_session_hdr *)raw_packet;
  2940. int rc = 0;
  2941. print_msg_hdr(hdr);
  2942. rc = cvp_hfi_process_msg_packet(0, raw_packet, info);
  2943. if (rc) {
  2944. dprintk(CVP_WARN,
  2945. "Corrupt/unknown packet found, discarding\n");
  2946. --packet_count;
  2947. continue;
  2948. } else if (info->response_type == HAL_NO_RESP) {
  2949. --packet_count;
  2950. continue;
  2951. }
  2952. /* Process the packet types that we're interested in */
  2953. process_system_msg(info, device, raw_packet);
  2954. session_id = get_session_id(info);
  2955. /*
  2956. * hfi_process_msg_packet provides a session_id that's a hashed
  2957. * value of struct cvp_hal_session, we need to coerce the hashed
  2958. * value back to pointer that we can use. Ideally, hfi_process\
  2959. * _msg_packet should take care of this, but it doesn't have
  2960. * required information for it
  2961. */
  2962. if (session_id) {
  2963. struct cvp_hal_session *session = NULL;
  2964. if (upper_32_bits((uintptr_t)*session_id) != 0) {
  2965. dprintk(CVP_ERR,
  2966. "Upper 32-bits != 0 for sess_id=%pK\n",
  2967. *session_id);
  2968. }
  2969. session = __get_session(device,
  2970. (u32)(uintptr_t)*session_id);
  2971. if (!session) {
  2972. dprintk(CVP_ERR, _INVALID_MSG_,
  2973. info->response_type,
  2974. *session_id);
  2975. --packet_count;
  2976. continue;
  2977. }
  2978. *session_id = session->session_id;
  2979. }
  2980. if (packet_count >= cvp_max_packets) {
  2981. dprintk(CVP_WARN,
  2982. "Too many packets in message queue!\n");
  2983. break;
  2984. }
  2985. /* do not read packets after sys error packet */
  2986. if (info->response_type == HAL_SYS_ERROR)
  2987. break;
  2988. }
  2989. if (requeue_pm_work && device->res->sw_power_collapsible) {
  2990. cancel_delayed_work(&iris_hfi_pm_work);
  2991. if (!queue_delayed_work(device->iris_pm_workq,
  2992. &iris_hfi_pm_work,
  2993. msecs_to_jiffies(
  2994. device->res->msm_cvp_pwr_collapse_delay))) {
  2995. dprintk(CVP_ERR, "PM work already scheduled\n");
  2996. }
  2997. }
  2998. exit:
  2999. __flush_debug_queue(device, raw_packet);
  3000. return packet_count;
  3001. }
  3002. irqreturn_t iris_hfi_core_work_handler(int irq, void *data)
  3003. {
  3004. struct msm_cvp_core *core;
  3005. struct iris_hfi_device *device;
  3006. int num_responses = 0, i = 0;
  3007. u32 intr_status;
  3008. static bool warning_on = true;
  3009. core = cvp_driver->cvp_core;
  3010. if (core)
  3011. device = core->dev_ops->hfi_device_data;
  3012. else
  3013. return IRQ_HANDLED;
  3014. mutex_lock(&device->lock);
  3015. if (!__core_in_valid_state(device)) {
  3016. if (warning_on) {
  3017. dprintk(CVP_WARN, "%s Core not in init state\n",
  3018. __func__);
  3019. warning_on = false;
  3020. }
  3021. goto err_no_work;
  3022. }
  3023. warning_on = true;
  3024. if (!device->callback) {
  3025. dprintk(CVP_ERR, "No interrupt callback function: %pK\n",
  3026. device);
  3027. goto err_no_work;
  3028. }
  3029. if (__resume(device)) {
  3030. dprintk(CVP_ERR, "%s: Power enable failed\n", __func__);
  3031. goto err_no_work;
  3032. }
  3033. __core_clear_interrupt(device);
  3034. num_responses = __response_handler(device);
  3035. dprintk(CVP_HFI, "%s:: cvp_driver_debug num_responses = %d ",
  3036. __func__, num_responses);
  3037. err_no_work:
  3038. /* Keep the interrupt status before releasing device lock */
  3039. intr_status = device->intr_status;
  3040. mutex_unlock(&device->lock);
  3041. /*
  3042. * Issue the callbacks outside of the locked contex to preserve
  3043. * re-entrancy.
  3044. */
  3045. for (i = 0; !IS_ERR_OR_NULL(device->response_pkt) &&
  3046. i < num_responses; ++i) {
  3047. struct msm_cvp_cb_info *r = &device->response_pkt[i];
  3048. void *rsp = (void *)&r->response;
  3049. if (!__core_in_valid_state(device)) {
  3050. dprintk(CVP_ERR,
  3051. _INVALID_STATE_, (i + 1), num_responses);
  3052. break;
  3053. }
  3054. dprintk(CVP_HFI, "Processing response %d of %d, type %d\n",
  3055. (i + 1), num_responses, r->response_type);
  3056. /* callback = void cvp_handle_cmd_response() */
  3057. device->callback(r->response_type, rsp);
  3058. }
  3059. /* We need re-enable the irq which was disabled in ISR handler */
  3060. if (!(intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  3061. enable_irq(device->cvp_hal_data->irq);
  3062. return IRQ_HANDLED;
  3063. }
  3064. irqreturn_t cvp_hfi_isr(int irq, void *dev)
  3065. {
  3066. disable_irq_nosync(irq);
  3067. return IRQ_WAKE_THREAD;
  3068. }
  3069. static void iris_hfi_wd_work_handler(struct work_struct *work)
  3070. {
  3071. struct msm_cvp_core *core;
  3072. struct iris_hfi_device *device;
  3073. struct msm_cvp_cb_cmd_done response = {0};
  3074. enum hal_command_response cmd = HAL_SYS_WATCHDOG_TIMEOUT;
  3075. core = cvp_driver->cvp_core;
  3076. if (core)
  3077. device = core->dev_ops->hfi_device_data;
  3078. else
  3079. return;
  3080. if (msm_cvp_hw_wd_recovery) {
  3081. dprintk(CVP_ERR, "Cleaning up as HW WD recovery is enable %d\n",
  3082. msm_cvp_hw_wd_recovery);
  3083. __print_sidebandmanager_regs(device);
  3084. response.device_id = 0;
  3085. handle_sys_error(cmd, (void *) &response);
  3086. enable_irq(device->cvp_hal_data->irq_wd);
  3087. }
  3088. else {
  3089. dprintk(CVP_ERR, "Crashing the device as HW WD recovery is disable %d\n",
  3090. msm_cvp_hw_wd_recovery);
  3091. BUG_ON(1);
  3092. }
  3093. }
  3094. static DECLARE_WORK(iris_hfi_wd_work, iris_hfi_wd_work_handler);
  3095. irqreturn_t iris_hfi_isr_wd(int irq, void *dev)
  3096. {
  3097. struct iris_hfi_device *device = dev;
  3098. dprintk(CVP_ERR, "Got HW WDOG IRQ at %llu! \n", get_aon_time());
  3099. disable_irq_nosync(irq);
  3100. queue_work(device->cvp_workq, &iris_hfi_wd_work);
  3101. return IRQ_HANDLED;
  3102. }
  3103. static int __init_reset_clk(struct msm_cvp_platform_resources *res,
  3104. int reset_index)
  3105. {
  3106. int rc = 0;
  3107. struct reset_control *rst;
  3108. struct reset_info *rst_info;
  3109. struct reset_set *rst_set = &res->reset_set;
  3110. if (!rst_set->reset_tbl)
  3111. return 0;
  3112. rst_info = &rst_set->reset_tbl[reset_index];
  3113. rst = rst_info->rst;
  3114. dprintk(CVP_PWR, "reset_clk: name %s rst %pK required_stage=%d\n",
  3115. rst_set->reset_tbl[reset_index].name, rst, rst_info->required_stage);
  3116. if (rst)
  3117. goto skip_reset_init;
  3118. if (rst_info->required_stage == CVP_ON_USE) {
  3119. rst = reset_control_get_exclusive_released(&res->pdev->dev,
  3120. rst_set->reset_tbl[reset_index].name);
  3121. if (IS_ERR(rst)) {
  3122. rc = PTR_ERR(rst);
  3123. dprintk(CVP_ERR, "reset get exclusive fail %d\n", rc);
  3124. return rc;
  3125. }
  3126. dprintk(CVP_PWR, "reset_clk: name %s get exclusive rst %llx\n",
  3127. rst_set->reset_tbl[reset_index].name, rst);
  3128. } else if (rst_info->required_stage == CVP_ON_INIT) {
  3129. rst = devm_reset_control_get(&res->pdev->dev,
  3130. rst_set->reset_tbl[reset_index].name);
  3131. if (IS_ERR(rst)) {
  3132. rc = PTR_ERR(rst);
  3133. dprintk(CVP_ERR, "reset get fail %d\n", rc);
  3134. return rc;
  3135. }
  3136. dprintk(CVP_PWR, "reset_clk: name %s get rst %llx\n",
  3137. rst_set->reset_tbl[reset_index].name, rst);
  3138. } else {
  3139. dprintk(CVP_ERR, "Invalid reset stage\n");
  3140. return -EINVAL;
  3141. }
  3142. rst_set->reset_tbl[reset_index].rst = rst;
  3143. rst_info->state = RESET_INIT;
  3144. return 0;
  3145. skip_reset_init:
  3146. return rc;
  3147. }
  3148. static int __reset_control_assert_name(struct iris_hfi_device *device,
  3149. const char *name)
  3150. {
  3151. struct reset_info *rcinfo = NULL;
  3152. int rc = 0;
  3153. bool found = false;
  3154. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3155. if (strcmp(rcinfo->name, name))
  3156. continue;
  3157. found = true;
  3158. rc = reset_control_assert(rcinfo->rst);
  3159. if (rc)
  3160. dprintk(CVP_ERR,
  3161. "%s: failed to assert reset control (%s), rc = %d\n",
  3162. __func__, rcinfo->name, rc);
  3163. else
  3164. dprintk(CVP_PWR, "%s: assert reset control (%s)\n",
  3165. __func__, rcinfo->name);
  3166. break;
  3167. }
  3168. if (!found) {
  3169. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3170. __func__, name);
  3171. rc = -EINVAL;
  3172. }
  3173. return rc;
  3174. }
  3175. static int __reset_control_deassert_name(struct iris_hfi_device *device,
  3176. const char *name)
  3177. {
  3178. struct reset_info *rcinfo = NULL;
  3179. int rc = 0;
  3180. bool found = false;
  3181. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3182. if (strcmp(rcinfo->name, name))
  3183. continue;
  3184. found = true;
  3185. rc = reset_control_deassert(rcinfo->rst);
  3186. if (rc)
  3187. dprintk(CVP_ERR,
  3188. "%s: deassert reset control for (%s) failed, rc %d\n",
  3189. __func__, rcinfo->name, rc);
  3190. else
  3191. dprintk(CVP_PWR, "%s: deassert reset control (%s)\n",
  3192. __func__, rcinfo->name);
  3193. break;
  3194. }
  3195. if (!found) {
  3196. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3197. __func__, name);
  3198. rc = -EINVAL;
  3199. }
  3200. return rc;
  3201. }
  3202. static int __reset_control_acquire(struct iris_hfi_device *device,
  3203. const char *name)
  3204. {
  3205. struct reset_info *rcinfo = NULL;
  3206. int rc = 0;
  3207. bool found = false;
  3208. int max_retries = 1000;
  3209. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3210. if (strcmp(rcinfo->name, name))
  3211. continue;
  3212. found = true;
  3213. if (rcinfo->state == RESET_ACQUIRED)
  3214. return rc;
  3215. acquire_again:
  3216. rc = reset_control_acquire(rcinfo->rst);
  3217. if (rc) {
  3218. if (rc == -EBUSY) {
  3219. usleep_range(1000, 1500);
  3220. max_retries--;
  3221. if (max_retries) {
  3222. goto acquire_again;
  3223. } else {
  3224. dprintk(CVP_ERR,
  3225. "%s acquire %s -EBUSY\n",
  3226. __func__, rcinfo->name);
  3227. BUG_ON(1);
  3228. }
  3229. } else {
  3230. dprintk(CVP_ERR,
  3231. "%s: acquire failed (%s) rc %d\n",
  3232. __func__, rcinfo->name, rc);
  3233. rc = -EINVAL;
  3234. }
  3235. } else {
  3236. dprintk(CVP_PWR, "%s: reset acquire succeed (%s)\n",
  3237. __func__, rcinfo->name);
  3238. rcinfo->state = RESET_ACQUIRED;
  3239. }
  3240. break;
  3241. }
  3242. if (!found) {
  3243. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3244. __func__, name);
  3245. rc = -EINVAL;
  3246. }
  3247. return rc;
  3248. }
  3249. static int __reset_control_release(struct iris_hfi_device *device,
  3250. const char *name)
  3251. {
  3252. struct reset_info *rcinfo = NULL;
  3253. int rc = 0;
  3254. bool found = false;
  3255. iris_hfi_for_each_reset_clock(device, rcinfo) {
  3256. if (strcmp(rcinfo->name, name))
  3257. continue;
  3258. found = true;
  3259. if (rcinfo->state != RESET_ACQUIRED) {
  3260. dprintk(CVP_WARN, "Double releasing reset clk?\n");
  3261. return -EINVAL;
  3262. }
  3263. reset_control_release(rcinfo->rst);
  3264. dprintk(CVP_PWR, "%s: reset release succeed (%s)\n",
  3265. __func__, rcinfo->name);
  3266. rcinfo->state = RESET_RELEASED;
  3267. break;
  3268. }
  3269. if (!found) {
  3270. dprintk(CVP_PWR, "%s: reset control (%s) not found\n",
  3271. __func__, name);
  3272. rc = -EINVAL;
  3273. }
  3274. return rc;
  3275. }
  3276. static void __deinit_bus(struct iris_hfi_device *device)
  3277. {
  3278. struct bus_info *bus = NULL;
  3279. if (!device)
  3280. return;
  3281. kfree(device->bus_vote.data);
  3282. device->bus_vote = CVP_DEFAULT_BUS_VOTE;
  3283. iris_hfi_for_each_bus_reverse(device, bus) {
  3284. dev_set_drvdata(bus->dev, NULL);
  3285. icc_put(bus->client);
  3286. bus->client = NULL;
  3287. }
  3288. }
  3289. static int __init_bus(struct iris_hfi_device *device)
  3290. {
  3291. struct bus_info *bus = NULL;
  3292. int rc = 0;
  3293. if (!device)
  3294. return -EINVAL;
  3295. iris_hfi_for_each_bus(device, bus) {
  3296. /*
  3297. * This is stupid, but there's no other easy way to ahold
  3298. * of struct bus_info in iris_hfi_devfreq_*()
  3299. */
  3300. WARN(dev_get_drvdata(bus->dev), "%s's drvdata already set\n",
  3301. dev_name(bus->dev));
  3302. dev_set_drvdata(bus->dev, device);
  3303. bus->client = icc_get(&device->res->pdev->dev,
  3304. bus->master, bus->slave);
  3305. if (IS_ERR_OR_NULL(bus->client)) {
  3306. rc = PTR_ERR(bus->client) ?: -EBADHANDLE;
  3307. dprintk(CVP_ERR, "Failed to register bus %s: %d\n",
  3308. bus->name, rc);
  3309. bus->client = NULL;
  3310. goto err_add_dev;
  3311. }
  3312. }
  3313. return 0;
  3314. err_add_dev:
  3315. __deinit_bus(device);
  3316. return rc;
  3317. }
  3318. static void __deinit_regulators(struct iris_hfi_device *device)
  3319. {
  3320. struct regulator_info *rinfo = NULL;
  3321. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3322. if (rinfo->regulator) {
  3323. regulator_put(rinfo->regulator);
  3324. rinfo->regulator = NULL;
  3325. }
  3326. }
  3327. }
  3328. static int __init_regulators(struct iris_hfi_device *device)
  3329. {
  3330. int rc = 0;
  3331. struct regulator_info *rinfo = NULL;
  3332. iris_hfi_for_each_regulator(device, rinfo) {
  3333. rinfo->regulator = regulator_get(&device->res->pdev->dev,
  3334. rinfo->name);
  3335. if (IS_ERR_OR_NULL(rinfo->regulator)) {
  3336. rc = PTR_ERR(rinfo->regulator) ?: -EBADHANDLE;
  3337. dprintk(CVP_ERR, "Failed to get regulator: %s\n",
  3338. rinfo->name);
  3339. rinfo->regulator = NULL;
  3340. goto err_reg_get;
  3341. }
  3342. }
  3343. return 0;
  3344. err_reg_get:
  3345. __deinit_regulators(device);
  3346. return rc;
  3347. }
  3348. static void __deinit_subcaches(struct iris_hfi_device *device)
  3349. {
  3350. struct subcache_info *sinfo = NULL;
  3351. if (!device) {
  3352. dprintk(CVP_ERR, "deinit_subcaches: invalid device %pK\n",
  3353. device);
  3354. goto exit;
  3355. }
  3356. if (!is_sys_cache_present(device))
  3357. goto exit;
  3358. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3359. if (sinfo->subcache) {
  3360. dprintk(CVP_CORE, "deinit_subcaches: %s\n",
  3361. sinfo->name);
  3362. llcc_slice_putd(sinfo->subcache);
  3363. sinfo->subcache = NULL;
  3364. }
  3365. }
  3366. exit:
  3367. return;
  3368. }
  3369. static int __init_subcaches(struct iris_hfi_device *device)
  3370. {
  3371. int rc = 0;
  3372. struct subcache_info *sinfo = NULL;
  3373. if (!device) {
  3374. dprintk(CVP_ERR, "init_subcaches: invalid device %pK\n",
  3375. device);
  3376. return -EINVAL;
  3377. }
  3378. if (!is_sys_cache_present(device))
  3379. return 0;
  3380. iris_hfi_for_each_subcache(device, sinfo) {
  3381. if (!strcmp("cvp", sinfo->name)) {
  3382. sinfo->subcache = llcc_slice_getd(LLCC_CVP);
  3383. } else if (!strcmp("cvpfw", sinfo->name)) {
  3384. sinfo->subcache = llcc_slice_getd(LLCC_CVPFW);
  3385. } else {
  3386. dprintk(CVP_ERR, "Invalid subcache name %s\n",
  3387. sinfo->name);
  3388. }
  3389. if (IS_ERR_OR_NULL(sinfo->subcache)) {
  3390. rc = PTR_ERR(sinfo->subcache) ?
  3391. PTR_ERR(sinfo->subcache) : -EBADHANDLE;
  3392. dprintk(CVP_ERR,
  3393. "init_subcaches: invalid subcache: %s rc %d\n",
  3394. sinfo->name, rc);
  3395. sinfo->subcache = NULL;
  3396. goto err_subcache_get;
  3397. }
  3398. dprintk(CVP_CORE, "init_subcaches: %s\n",
  3399. sinfo->name);
  3400. }
  3401. return 0;
  3402. err_subcache_get:
  3403. __deinit_subcaches(device);
  3404. return rc;
  3405. }
  3406. static int __init_resources(struct iris_hfi_device *device,
  3407. struct msm_cvp_platform_resources *res)
  3408. {
  3409. int i, rc = 0;
  3410. rc = __init_regulators(device);
  3411. if (rc) {
  3412. dprintk(CVP_ERR, "Failed to get all regulators\n");
  3413. return -ENODEV;
  3414. }
  3415. rc = msm_cvp_init_clocks(device);
  3416. if (rc) {
  3417. dprintk(CVP_ERR, "Failed to init clocks\n");
  3418. rc = -ENODEV;
  3419. goto err_init_clocks;
  3420. }
  3421. for (i = 0; i < device->res->reset_set.count; i++) {
  3422. rc = __init_reset_clk(res, i);
  3423. if (rc) {
  3424. dprintk(CVP_ERR, "Failed to init reset clocks\n");
  3425. rc = -ENODEV;
  3426. goto err_init_reset_clk;
  3427. }
  3428. }
  3429. rc = __init_bus(device);
  3430. if (rc) {
  3431. dprintk(CVP_ERR, "Failed to init bus: %d\n", rc);
  3432. goto err_init_bus;
  3433. }
  3434. rc = __init_subcaches(device);
  3435. if (rc)
  3436. dprintk(CVP_WARN, "Failed to init subcaches: %d\n", rc);
  3437. device->sys_init_capabilities =
  3438. kzalloc(sizeof(struct msm_cvp_capability)
  3439. * CVP_MAX_SESSIONS, GFP_KERNEL);
  3440. return rc;
  3441. err_init_reset_clk:
  3442. err_init_bus:
  3443. msm_cvp_deinit_clocks(device);
  3444. err_init_clocks:
  3445. __deinit_regulators(device);
  3446. return rc;
  3447. }
  3448. static void __deinit_resources(struct iris_hfi_device *device)
  3449. {
  3450. __deinit_subcaches(device);
  3451. __deinit_bus(device);
  3452. msm_cvp_deinit_clocks(device);
  3453. __deinit_regulators(device);
  3454. kfree(device->sys_init_capabilities);
  3455. device->sys_init_capabilities = NULL;
  3456. }
  3457. static int __disable_regulator_impl(struct regulator_info *rinfo,
  3458. struct iris_hfi_device *device)
  3459. {
  3460. int rc = 0;
  3461. dprintk(CVP_PWR, "Disabling regulator %s\n", rinfo->name);
  3462. /*
  3463. * This call is needed. Driver needs to acquire the control back
  3464. * from HW in order to disable the regualtor. Else the behavior
  3465. * is unknown.
  3466. */
  3467. rc = __acquire_regulator(rinfo, device);
  3468. if (rc) {
  3469. /*
  3470. * This is somewhat fatal, but nothing we can do
  3471. * about it. We can't disable the regulator w/o
  3472. * getting it back under s/w control
  3473. */
  3474. dprintk(CVP_WARN,
  3475. "Failed to acquire control on %s\n",
  3476. rinfo->name);
  3477. goto disable_regulator_failed;
  3478. }
  3479. /*Acquire XO_RESET to avoid race condition with video*/
  3480. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3481. if (rc) {
  3482. dprintk(CVP_ERR,
  3483. "XO_RESET could not be acquired: skip disabling the regulator %s\n",
  3484. rinfo->name);
  3485. return -EINVAL;
  3486. }
  3487. rc = regulator_disable(rinfo->regulator);
  3488. /*Release XO_RESET after regulator is enabled.*/
  3489. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  3490. if (rc) {
  3491. dprintk(CVP_WARN,
  3492. "Failed to disable %s: %d\n",
  3493. rinfo->name, rc);
  3494. goto disable_regulator_failed;
  3495. }
  3496. return 0;
  3497. disable_regulator_failed:
  3498. /* Bring attention to this issue */
  3499. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3500. return rc;
  3501. }
  3502. static int __disable_hw_power_collapse(struct iris_hfi_device *device)
  3503. {
  3504. int rc = 0;
  3505. if (!msm_cvp_fw_low_power_mode) {
  3506. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3507. return 0;
  3508. }
  3509. rc = __take_back_regulators(device);
  3510. if (rc)
  3511. dprintk(CVP_WARN,
  3512. "%s : Failed to disable HW power collapse %d\n",
  3513. __func__, rc);
  3514. return rc;
  3515. }
  3516. static int __enable_hw_power_collapse(struct iris_hfi_device *device)
  3517. {
  3518. int rc = 0;
  3519. if (!msm_cvp_fw_low_power_mode) {
  3520. dprintk(CVP_PWR, "Not enabling hardware power collapse\n");
  3521. return 0;
  3522. }
  3523. rc = __hand_off_regulators(device);
  3524. if (rc)
  3525. dprintk(CVP_WARN,
  3526. "%s : Failed to enable HW power collapse %d\n",
  3527. __func__, rc);
  3528. return rc;
  3529. }
  3530. static int __enable_regulator(struct iris_hfi_device *device,
  3531. const char *name)
  3532. {
  3533. int rc = 0;
  3534. struct regulator_info *rinfo;
  3535. iris_hfi_for_each_regulator(device, rinfo) {
  3536. if (strcmp(rinfo->name, name))
  3537. continue;
  3538. /*Acquire XO_RESET to avoid race condition with video*/
  3539. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3540. if (rc) {
  3541. dprintk(CVP_ERR,
  3542. "XO_RESET could not be acquired: skip enabling the regulator %s\n",
  3543. rinfo->name);
  3544. return -EINVAL;
  3545. }
  3546. rc = regulator_enable(rinfo->regulator);
  3547. /*Release XO_RESET after regulator is enabled.*/
  3548. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  3549. if (rc) {
  3550. dprintk(CVP_ERR, "Failed to enable %s: %d\n",
  3551. rinfo->name, rc);
  3552. return rc;
  3553. }
  3554. if (!regulator_is_enabled(rinfo->regulator)) {
  3555. dprintk(CVP_ERR,"%s: regulator %s not enabled\n",
  3556. __func__, rinfo->name);
  3557. regulator_disable(rinfo->regulator);
  3558. return -EINVAL;
  3559. }
  3560. dprintk(CVP_PWR, "Enabled regulator %s\n", rinfo->name);
  3561. return 0;
  3562. }
  3563. dprintk(CVP_ERR, "regulator %s not found\n", name);
  3564. return -EINVAL;
  3565. }
  3566. static int __disable_regulator(struct iris_hfi_device *device,
  3567. const char *name)
  3568. {
  3569. struct regulator_info *rinfo;
  3570. iris_hfi_for_each_regulator_reverse(device, rinfo) {
  3571. if (strcmp(rinfo->name, name))
  3572. continue;
  3573. __disable_regulator_impl(rinfo, device);
  3574. dprintk(CVP_PWR, "%s Disabled regulator %s\n", __func__, name);
  3575. return 0;
  3576. }
  3577. dprintk(CVP_ERR, "%s regulator %s not found\n", __func__, name);
  3578. return -EINVAL;
  3579. }
  3580. static int __enable_subcaches(struct iris_hfi_device *device)
  3581. {
  3582. int rc = 0;
  3583. u32 c = 0;
  3584. struct subcache_info *sinfo;
  3585. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3586. return 0;
  3587. /* Activate subcaches */
  3588. iris_hfi_for_each_subcache(device, sinfo) {
  3589. rc = llcc_slice_activate(sinfo->subcache);
  3590. if (rc) {
  3591. dprintk(CVP_WARN, "Failed to activate %s: %d\n",
  3592. sinfo->name, rc);
  3593. msm_cvp_res_handle_fatal_hw_error(device->res, true);
  3594. goto err_activate_fail;
  3595. }
  3596. sinfo->isactive = true;
  3597. dprintk(CVP_CORE, "Activated subcache %s\n", sinfo->name);
  3598. c++;
  3599. }
  3600. dprintk(CVP_CORE, "Activated %d Subcaches to CVP\n", c);
  3601. return 0;
  3602. err_activate_fail:
  3603. __release_subcaches(device);
  3604. __disable_subcaches(device);
  3605. return 0;
  3606. }
  3607. static int __set_subcaches(struct iris_hfi_device *device)
  3608. {
  3609. int rc = 0;
  3610. u32 c = 0;
  3611. struct subcache_info *sinfo;
  3612. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3613. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3614. struct cvp_hfi_resource_subcache_type *sc_res;
  3615. struct cvp_resource_hdr rhdr;
  3616. if (device->res->sys_cache_res_set || msm_cvp_syscache_disable) {
  3617. dprintk(CVP_CORE, "Subcaches already set or disabled\n");
  3618. return 0;
  3619. }
  3620. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3621. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3622. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3623. iris_hfi_for_each_subcache(device, sinfo) {
  3624. if (sinfo->isactive) {
  3625. sc_res[c].size = sinfo->subcache->slice_size;
  3626. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3627. c++;
  3628. }
  3629. }
  3630. /* Set resource to CVP for activated subcaches */
  3631. if (c) {
  3632. dprintk(CVP_CORE, "Setting %d Subcaches\n", c);
  3633. rhdr.resource_handle = sc_res_info; /* cookie */
  3634. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3635. sc_res_info->num_entries = c;
  3636. rc = __core_set_resource(device, &rhdr, (void *)sc_res_info);
  3637. if (rc) {
  3638. dprintk(CVP_WARN, "Failed to set subcaches %d\n", rc);
  3639. goto err_fail_set_subacaches;
  3640. }
  3641. iris_hfi_for_each_subcache(device, sinfo) {
  3642. if (sinfo->isactive)
  3643. sinfo->isset = true;
  3644. }
  3645. dprintk(CVP_CORE, "Set Subcaches done to CVP\n");
  3646. device->res->sys_cache_res_set = true;
  3647. }
  3648. return 0;
  3649. err_fail_set_subacaches:
  3650. __disable_subcaches(device);
  3651. return 0;
  3652. }
  3653. static int __release_subcaches(struct iris_hfi_device *device)
  3654. {
  3655. struct subcache_info *sinfo;
  3656. int rc = 0;
  3657. u32 c = 0;
  3658. u32 resource[CVP_MAX_SUBCACHE_SIZE];
  3659. struct cvp_hfi_resource_syscache_info_type *sc_res_info;
  3660. struct cvp_hfi_resource_subcache_type *sc_res;
  3661. struct cvp_resource_hdr rhdr;
  3662. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3663. return 0;
  3664. memset((void *)resource, 0x0, (sizeof(u32) * CVP_MAX_SUBCACHE_SIZE));
  3665. sc_res_info = (struct cvp_hfi_resource_syscache_info_type *)resource;
  3666. sc_res = &(sc_res_info->rg_subcache_entries[0]);
  3667. /* Release resource command to Iris */
  3668. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3669. if (sinfo->isset) {
  3670. /* Update the entry */
  3671. sc_res[c].size = sinfo->subcache->slice_size;
  3672. sc_res[c].sc_id = sinfo->subcache->slice_id;
  3673. c++;
  3674. sinfo->isset = false;
  3675. }
  3676. }
  3677. if (c > 0) {
  3678. dprintk(CVP_CORE, "Releasing %d subcaches\n", c);
  3679. rhdr.resource_handle = sc_res_info; /* cookie */
  3680. rhdr.resource_id = CVP_RESOURCE_SYSCACHE;
  3681. rc = __core_release_resource(device, &rhdr);
  3682. if (rc)
  3683. dprintk(CVP_WARN,
  3684. "Failed to release %d subcaches\n", c);
  3685. }
  3686. device->res->sys_cache_res_set = false;
  3687. return 0;
  3688. }
  3689. static int __disable_subcaches(struct iris_hfi_device *device)
  3690. {
  3691. struct subcache_info *sinfo;
  3692. int rc = 0;
  3693. if (msm_cvp_syscache_disable || !is_sys_cache_present(device))
  3694. return 0;
  3695. /* De-activate subcaches */
  3696. iris_hfi_for_each_subcache_reverse(device, sinfo) {
  3697. if (sinfo->isactive) {
  3698. dprintk(CVP_CORE, "De-activate subcache %s\n",
  3699. sinfo->name);
  3700. rc = llcc_slice_deactivate(sinfo->subcache);
  3701. if (rc) {
  3702. dprintk(CVP_WARN,
  3703. "Failed to de-activate %s: %d\n",
  3704. sinfo->name, rc);
  3705. }
  3706. sinfo->isactive = false;
  3707. }
  3708. }
  3709. return 0;
  3710. }
  3711. static void interrupt_init_iris2(struct iris_hfi_device *device)
  3712. {
  3713. u32 mask_val = 0;
  3714. /* All interrupts should be disabled initially 0x1F6 : Reset value */
  3715. mask_val = __read_register(device, CVP_WRAPPER_INTR_MASK);
  3716. /* Write 0 to unmask CPU and WD interrupts */
  3717. mask_val &= ~(CVP_FATAL_INTR_BMSK | CVP_WRAPPER_INTR_MASK_A2HCPU_BMSK);
  3718. __write_register(device, CVP_WRAPPER_INTR_MASK, mask_val);
  3719. dprintk(CVP_REG, "Init irq: reg: %x, mask value %x\n",
  3720. CVP_WRAPPER_INTR_MASK, mask_val);
  3721. mask_val = 0;
  3722. mask_val = __read_register(device, CVP_SS_IRQ_MASK);
  3723. mask_val &= ~(CVP_SS_INTR_BMASK);
  3724. __write_register(device, CVP_SS_IRQ_MASK, mask_val);
  3725. dprintk(CVP_REG, "Init irq_wd: reg: %x, mask value %x\n",
  3726. CVP_SS_IRQ_MASK, mask_val);
  3727. }
  3728. static void setup_dsp_uc_memmap_vpu5(struct iris_hfi_device *device)
  3729. {
  3730. /* initialize DSP QTBL & UCREGION with CPU queues */
  3731. __write_register(device, HFI_DSP_QTBL_ADDR,
  3732. (u32)device->dsp_iface_q_table.align_device_addr);
  3733. __write_register(device, HFI_DSP_UC_REGION_ADDR,
  3734. (u32)device->dsp_iface_q_table.align_device_addr);
  3735. __write_register(device, HFI_DSP_UC_REGION_SIZE,
  3736. device->dsp_iface_q_table.mem_data.size);
  3737. }
  3738. static void clock_config_on_enable_vpu5(struct iris_hfi_device *device)
  3739. {
  3740. __write_register(device, CVP_WRAPPER_CPU_CLOCK_CONFIG, 0);
  3741. }
  3742. static int __set_ubwc_config(struct iris_hfi_device *device)
  3743. {
  3744. u8 packet[CVP_IFACEQ_VAR_SMALL_PKT_SIZE];
  3745. int rc = 0;
  3746. struct cvp_hfi_cmd_sys_set_property_packet *pkt =
  3747. (struct cvp_hfi_cmd_sys_set_property_packet *) &packet;
  3748. if (!device->res->ubwc_config)
  3749. return 0;
  3750. rc = call_hfi_pkt_op(device, sys_ubwc_config, pkt,
  3751. device->res->ubwc_config);
  3752. if (rc) {
  3753. dprintk(CVP_WARN,
  3754. "ubwc config setting to FW failed\n");
  3755. rc = -ENOTEMPTY;
  3756. goto fail_to_set_ubwc_config;
  3757. }
  3758. if (__iface_cmdq_write(device, pkt)) {
  3759. rc = -ENOTEMPTY;
  3760. goto fail_to_set_ubwc_config;
  3761. }
  3762. fail_to_set_ubwc_config:
  3763. return rc;
  3764. }
  3765. static int __power_on_controller(struct iris_hfi_device *device)
  3766. {
  3767. int rc = 0;
  3768. rc = __enable_regulator(device, "cvp");
  3769. if (rc) {
  3770. dprintk(CVP_ERR, "Failed to enable ctrler: %d\n", rc);
  3771. return rc;
  3772. }
  3773. rc = msm_cvp_prepare_enable_clk(device, "sleep_clk");
  3774. if (rc) {
  3775. dprintk(CVP_ERR, "Failed to enable sleep clk: %d\n", rc);
  3776. goto fail_reset_clks;
  3777. }
  3778. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  3779. if (rc)
  3780. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  3781. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  3782. if (rc)
  3783. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  3784. /* wait for deassert */
  3785. usleep_range(300, 400);
  3786. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  3787. if (rc)
  3788. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  3789. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  3790. if (rc)
  3791. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  3792. rc = msm_cvp_prepare_enable_clk(device, "gcc_video_axi1");
  3793. if (rc) {
  3794. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  3795. goto fail_reset_clks;
  3796. }
  3797. rc = msm_cvp_prepare_enable_clk(device, "cvp_clk");
  3798. if (rc) {
  3799. dprintk(CVP_ERR, "Failed to enable cvp_clk: %d\n", rc);
  3800. goto fail_enable_clk;
  3801. }
  3802. dprintk(CVP_PWR, "EVA controller powered on\n");
  3803. return 0;
  3804. fail_enable_clk:
  3805. msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  3806. fail_reset_clks:
  3807. __disable_regulator(device, "cvp");
  3808. return rc;
  3809. }
  3810. static int __power_on_core(struct iris_hfi_device *device)
  3811. {
  3812. int rc = 0;
  3813. rc = __enable_regulator(device, "cvp-core");
  3814. if (rc) {
  3815. dprintk(CVP_ERR, "Failed to enable core: %d\n", rc);
  3816. return rc;
  3817. }
  3818. rc = msm_cvp_prepare_enable_clk(device, "video_cc_mvs1_clk_src");
  3819. if (rc) {
  3820. dprintk(CVP_ERR, "Failed to enable video_cc_mvs1_clk_src:%d\n",
  3821. rc);
  3822. __disable_regulator(device, "cvp-core");
  3823. return rc;
  3824. }
  3825. rc = msm_cvp_prepare_enable_clk(device, "core_clk");
  3826. if (rc) {
  3827. dprintk(CVP_ERR, "Failed to enable core_clk: %d\n", rc);
  3828. __disable_regulator(device, "cvp-core");
  3829. return rc;
  3830. }
  3831. /*#ifdef CONFIG_EVA_PINEAPPLE
  3832. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_ARCG_CONTROL, 0);
  3833. __write_register(device, CVP_NOC_RCGCONTROLLER_HYSTERESIS_LOW, 0x2f);
  3834. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 1);
  3835. __write_register(device, CVP_NOC_RCGCONTROLLER_MAINCTL_LOW, 1);
  3836. usleep_range(50, 100);
  3837. __write_register(device, CVP_NOC_RCG_VNOC_NOC_CLK_FORCECLOCKON_LOW, 0);
  3838. #endif*/
  3839. dprintk(CVP_PWR, "EVA core powered on\n");
  3840. return 0;
  3841. }
  3842. static int __iris_power_on(struct iris_hfi_device *device)
  3843. {
  3844. int rc = 0;
  3845. u32 reg_gdsc, reg_cbcr, spare_val;
  3846. if (device->power_enabled)
  3847. return 0;
  3848. /* Vote for all hardware resources */
  3849. rc = __vote_buses(device, device->bus_vote.data,
  3850. device->bus_vote.data_count);
  3851. if (rc) {
  3852. dprintk(CVP_ERR, "Failed to vote buses, err: %d\n", rc);
  3853. goto fail_vote_buses;
  3854. }
  3855. rc = __power_on_controller(device);
  3856. if (rc)
  3857. goto fail_enable_controller;
  3858. rc = __power_on_core(device);
  3859. if (rc)
  3860. goto fail_enable_core;
  3861. rc = msm_cvp_scale_clocks(device);
  3862. if (rc) {
  3863. dprintk(CVP_WARN,
  3864. "Failed to scale clocks, perf may regress\n");
  3865. rc = 0;
  3866. } else {
  3867. dprintk(CVP_PWR, "Done with scaling\n");
  3868. }
  3869. /*Do not access registers before this point!*/
  3870. device->power_enabled = true;
  3871. /* Thomas input to debug CPU NoC hang */
  3872. __write_register(device, CVP_NOC_SBM_FAULTINEN0_LOW, 0x1);
  3873. __write_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS, 0x3);
  3874. /*
  3875. * Re-program all of the registers that get reset as a result of
  3876. * regulator_disable() and _enable()
  3877. * calling below function requires CORE powered on
  3878. */
  3879. rc = __set_registers(device);
  3880. if (rc)
  3881. goto fail_enable_core;
  3882. dprintk(CVP_CORE, "Done with register set\n");
  3883. reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
  3884. reg_cbcr = __read_register(device, CVP_CC_MVS1_CBCR);
  3885. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000)) {
  3886. rc = -EINVAL;
  3887. dprintk(CVP_ERR, "CORE power on failed gdsc %x cbcr %x\n",
  3888. reg_gdsc, reg_cbcr);
  3889. goto fail_enable_core;
  3890. }
  3891. reg_gdsc = __read_register(device, CVP_CC_MVS1C_GDSCR);
  3892. reg_cbcr = __read_register(device, CVP_CC_MVS1C_CBCR);
  3893. if (!(reg_gdsc & 0x80000000) || (reg_cbcr & 0x80000000)) {
  3894. rc = -EINVAL;
  3895. dprintk(CVP_ERR, "CTRL power on failed gdsc %x cbcr %x\n",
  3896. reg_gdsc, reg_cbcr);
  3897. goto fail_enable_core;
  3898. }
  3899. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3900. if ((spare_val & 0x2) != 0) {
  3901. usleep_range(2000, 3000);
  3902. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  3903. if ((spare_val & 0x2) != 0) {
  3904. dprintk(CVP_ERR, "WRAPPER_SPARE non-zero %#x\n", spare_val);
  3905. rc = -EINVAL;
  3906. goto fail_enable_core;
  3907. }
  3908. }
  3909. call_iris_op(device, interrupt_init, device);
  3910. dprintk(CVP_CORE, "Done with interrupt enabling\n");
  3911. device->intr_status = 0;
  3912. enable_irq(device->cvp_hal_data->irq);
  3913. __write_register(device,
  3914. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x7);
  3915. pr_info_ratelimited(CVP_DBG_TAG "cvp (eva) powered on\n", "pwr");
  3916. return 0;
  3917. fail_enable_core:
  3918. __power_off_controller(device);
  3919. fail_enable_controller:
  3920. __unvote_buses(device);
  3921. fail_vote_buses:
  3922. device->power_enabled = false;
  3923. return rc;
  3924. }
  3925. static inline int __suspend(struct iris_hfi_device *device)
  3926. {
  3927. int rc = 0;
  3928. if (!device) {
  3929. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  3930. return -EINVAL;
  3931. } else if (!device->power_enabled) {
  3932. dprintk(CVP_PWR, "Power already disabled\n");
  3933. return 0;
  3934. }
  3935. dprintk(CVP_PWR, "Entering suspend\n");
  3936. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  3937. if (rc) {
  3938. dprintk(CVP_WARN, "Failed to suspend cvp core %d\n", rc);
  3939. goto err_tzbsp_suspend;
  3940. }
  3941. __disable_subcaches(device);
  3942. call_iris_op(device, power_off, device);
  3943. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  3944. cvp_pm_qos_update(device, false);
  3945. return rc;
  3946. err_tzbsp_suspend:
  3947. return rc;
  3948. }
  3949. static void __print_sidebandmanager_regs(struct iris_hfi_device *device)
  3950. {
  3951. u32 sbm_ln0_low, axi_cbcr, val;
  3952. u32 main_sbm_ln0_low = 0xdeadbeef, main_sbm_ln0_high = 0xdeadbeef;
  3953. u32 main_sbm_ln1_high = 0xdeadbeef, cpu_cs_x2rpmh;
  3954. int rc;
  3955. sbm_ln0_low =
  3956. __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
  3957. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3958. __write_register(device, CVP_CPU_CS_X2RPMh,
  3959. (cpu_cs_x2rpmh | CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK));
  3960. usleep_range(500, 1000);
  3961. cpu_cs_x2rpmh = __read_register(device, CVP_CPU_CS_X2RPMh);
  3962. if (!(cpu_cs_x2rpmh & CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK)) {
  3963. dprintk(CVP_WARN,
  3964. "failed set CVP_CPU_CS_X2RPMH mask %x\n",
  3965. cpu_cs_x2rpmh);
  3966. goto exit;
  3967. }
  3968. axi_cbcr = __read_gcc_register(device, CVP_GCC_VIDEO_AXI1_CBCR);
  3969. if (axi_cbcr & 0x80000000) {
  3970. dprintk(CVP_WARN, "failed to turn on AXI clock %x\n",
  3971. axi_cbcr);
  3972. goto exit;
  3973. }
  3974. /* Added by Thomas to debug CPU NoC hang */
  3975. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  3976. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRVLD_LOW %#x\n", val);
  3977. val = __read_register(device, CVP_NOC_SBM_FAULTINSTATUS0_LOW);
  3978. dprintk(CVP_ERR, "CVP_NOC_SBM_FAULTINSTATUS0_LOW %#x\n", val);
  3979. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  3980. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_LOW %#x\n", val);
  3981. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  3982. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH %#x\n", val);
  3983. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  3984. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_LOW %#x\n", val);
  3985. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  3986. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH %#x\n", val);
  3987. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  3988. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_LOW %#x\n", val);
  3989. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  3990. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH %#x\n", val);
  3991. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  3992. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_LOW %#x\n", val);
  3993. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  3994. dprintk(CVP_ERR, "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH %#x\n", val);
  3995. /* end of addition */
  3996. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  3997. if (rc) {
  3998. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  3999. goto exit;
  4000. }
  4001. main_sbm_ln0_low = __read_register(device,
  4002. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW +
  4003. device->res->noc_main_sidebandmanager_offset);
  4004. main_sbm_ln0_high = __read_register(device,
  4005. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_HIGH +
  4006. device->res->noc_main_sidebandmanager_offset);
  4007. main_sbm_ln1_high = __read_register(device,
  4008. CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN1_HIGH +
  4009. device->res->noc_main_sidebandmanager_offset);
  4010. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4011. exit:
  4012. cpu_cs_x2rpmh = cpu_cs_x2rpmh & (~CVP_CPU_CS_X2RPMh_SWOVERRIDE_BMSK);
  4013. __write_register(device, CVP_CPU_CS_X2RPMh, cpu_cs_x2rpmh);
  4014. dprintk(CVP_WARN, "Sidebandmanager regs %x %x %x %x %x\n",
  4015. sbm_ln0_low, main_sbm_ln0_low,
  4016. main_sbm_ln0_high, main_sbm_ln1_high,
  4017. cpu_cs_x2rpmh);
  4018. }
  4019. static void __enter_cpu_noc_lpi(struct iris_hfi_device *device)
  4020. {
  4021. u32 lpi_status, count = 0, max_count = 2000;
  4022. /* New addition to put CPU/Tensilica to low power */
  4023. count = 0;
  4024. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x1);
  4025. while (count < max_count) {
  4026. lpi_status = __read_register(device, CVP_WRAPPER_CPU_NOC_LPI_STATUS);
  4027. if ((lpi_status & BIT(1)) || ((lpi_status & BIT(2)) && (!(lpi_status & BIT(0))))) {
  4028. /*
  4029. * If QDENY == true, or
  4030. * If QACTIVE == true && QACCEPT == false
  4031. * Try again
  4032. */
  4033. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x0);
  4034. usleep_range(10, 20);
  4035. __write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x1);
  4036. usleep_range(1000, 1200);
  4037. count++;
  4038. } else {
  4039. break;
  4040. }
  4041. }
  4042. dprintk(CVP_PWR,
  4043. "%s, CPU Noc: lpi_status %x (count %d)\n", __func__, lpi_status, count);
  4044. if (count == max_count) {
  4045. u32 pc_ready, wfi_status;
  4046. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  4047. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  4048. dprintk(CVP_WARN,
  4049. "%s, CPU NOC not in qaccept status %x %x %x\n",
  4050. __func__, lpi_status, wfi_status, pc_ready);
  4051. __print_sidebandmanager_regs(device);
  4052. }
  4053. }
  4054. static int __power_off_controller(struct iris_hfi_device *device)
  4055. {
  4056. u32 lpi_status, count = 0, max_count = 1000;
  4057. int rc;
  4058. u32 spare_val, spare_status;
  4059. /* HPG 6.2.2 Step 1 */
  4060. __write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
  4061. /* HPG 6.2.2 Step 2, noc to low power */
  4062. __enter_cpu_noc_lpi(device);
  4063. /* HPG 6.2.2 Step 3, debug bridge to low power BYPASSED */
  4064. /* HPG 6.2.2 Step 4, debug bridge to lpi release */
  4065. __write_register(device,
  4066. CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL, 0x0);
  4067. lpi_status = 0x1;
  4068. count = 0;
  4069. while (lpi_status && count < max_count) {
  4070. lpi_status = __read_register(device,
  4071. CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS);
  4072. usleep_range(50, 100);
  4073. count++;
  4074. }
  4075. dprintk(CVP_PWR,
  4076. "DBLP Release: lpi_status %d(count %d)\n",
  4077. lpi_status, count);
  4078. if (count == max_count) {
  4079. dprintk(CVP_WARN,
  4080. "DBLP Release: lpi_status %x\n", lpi_status);
  4081. }
  4082. /* PDXFIFO reset: addition for Kailua / Lanai */
  4083. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x3);
  4084. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x1);
  4085. __write_register(device, CVP_WRAPPER_QNS4PDXFIFO_RESET, 0x0);
  4086. __write_register(device, CVP_WRAPPER_AXI_CLOCK_CONFIG, 0x0);
  4087. /* HPG 6.2.2 Step 5 */
  4088. msm_cvp_disable_unprepare_clk(device, "cvp_clk");
  4089. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_axi_reset");
  4090. if (rc)
  4091. dprintk(CVP_ERR, "%s: assert cvp_axi_reset failed\n", __func__);
  4092. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_core_reset");
  4093. if (rc)
  4094. dprintk(CVP_ERR, "%s: assert cvp_core_reset failed\n", __func__);
  4095. /* wait for deassert */
  4096. usleep_range(1000, 1050);
  4097. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_axi_reset");
  4098. if (rc)
  4099. dprintk(CVP_ERR, "%s: de-assert cvp_axi_reset failed\n", __func__);
  4100. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_core_reset");
  4101. if (rc)
  4102. dprintk(CVP_ERR, "%s: de-assert cvp_core_reset failed\n", __func__);
  4103. /* disable EVA NoC clock */
  4104. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x1);
  4105. /* enable EVA NoC reset */
  4106. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x1);
  4107. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4108. if (rc) {
  4109. dprintk(CVP_ERR, "FATAL ERROR, HPG step 17 to 20 will be bypassed\n");
  4110. goto skip_xo_reset;
  4111. }
  4112. spare_status = 0x1;
  4113. while (spare_status != 0x0) {
  4114. spare_val = __read_register(device, CVP_AON_WRAPPER_SPARE);
  4115. spare_status = spare_val & 0x2;
  4116. usleep_range(50, 100);
  4117. }
  4118. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x1);
  4119. rc = call_iris_op(device, reset_control_assert_name, device, "cvp_xo_reset");
  4120. if (rc)
  4121. dprintk(CVP_ERR, "%s: assert cvp_xo_reset failed\n", __func__);
  4122. /* de-assert EVA_NoC reset */
  4123. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_SW_RESET, 0x0);
  4124. /* de-assert EVA video_cc XO reset and enable video_cc XO clock after 80us */
  4125. usleep_range(80, 100);
  4126. rc = call_iris_op(device, reset_control_deassert_name, device, "cvp_xo_reset");
  4127. if (rc)
  4128. dprintk(CVP_ERR, "%s: de-assert cvp_xo_reset failed\n", __func__);
  4129. /* clear XO mask bit - this step was missing in previous sequence */
  4130. __write_register(device, CVP_AON_WRAPPER_SPARE, 0x0);
  4131. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4132. skip_xo_reset:
  4133. /* enable EVA NoC clock */
  4134. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL, 0x0);
  4135. /* De-assert EVA_CTL Force Sleep Retention */
  4136. usleep_range(400, 500);
  4137. /* HPG 6.2.2 Step 6 */
  4138. __disable_regulator(device, "cvp");
  4139. /* HPG 6.2.2 Step 7 */
  4140. rc = msm_cvp_disable_unprepare_clk(device, "gcc_video_axi1");
  4141. if (rc) {
  4142. dprintk(CVP_ERR, "Failed to enable axi1 clk: %d\n", rc);
  4143. }
  4144. rc = msm_cvp_disable_unprepare_clk(device, "sleep_clk");
  4145. if (rc) {
  4146. dprintk(CVP_ERR, "Failed to disable sleep clk: %d\n", rc);
  4147. }
  4148. return 0;
  4149. }
  4150. static int __power_off_core(struct iris_hfi_device *device)
  4151. {
  4152. u32 reg_status = 0, lpi_status, config, value = 0, count = 0;
  4153. u32 warn_flag = 0, max_count = 10;
  4154. value = __read_register(device, CVP_CC_MVS1_GDSCR);
  4155. if (!(value & 0x80000000)) {
  4156. /*
  4157. * Core has been powered off by f/w.
  4158. * Check NOC reset registers to ensure
  4159. * NO outstanding NoC transactions
  4160. */
  4161. value = __read_register(device, CVP_NOC_RESET_ACK);
  4162. if (value) {
  4163. dprintk(CVP_WARN,
  4164. "Core off with NOC RESET ACK non-zero %x\n",
  4165. value);
  4166. __print_sidebandmanager_regs(device);
  4167. }
  4168. __disable_regulator(device, "cvp-core");
  4169. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4170. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4171. return 0;
  4172. } else if (!(value & 0x2)) {
  4173. /*
  4174. * HW_CONTROL PC disabled, then core is powered on for
  4175. * CVP NoC access
  4176. */
  4177. __disable_regulator(device, "cvp-core");
  4178. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4179. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4180. return 0;
  4181. }
  4182. dprintk(CVP_PWR, "Driver controls Core power off now\n");
  4183. /*
  4184. * check to make sure core clock branch enabled else
  4185. * we cannot read core idle register
  4186. */
  4187. config = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4188. if (config) {
  4189. dprintk(CVP_PWR,
  4190. "core clock config not enabled, enable it to access core\n");
  4191. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0);
  4192. }
  4193. /*
  4194. * add MNoC idle check before collapsing MVS1 per HPG update
  4195. * poll for NoC DMA idle -> HPG 6.2.1
  4196. *
  4197. */
  4198. do {
  4199. value = __read_register(device, CVP_SS_IDLE_STATUS);
  4200. if (value & 0x400000)
  4201. break;
  4202. else
  4203. usleep_range(1000, 2000);
  4204. count++;
  4205. } while (count < max_count);
  4206. if (count == max_count) {
  4207. dprintk(CVP_WARN, "Core fail to go idle %x\n", value);
  4208. warn_flag = 1;
  4209. }
  4210. count = 0;
  4211. max_count = 1000;
  4212. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x1);
  4213. while (!reg_status && count < max_count) {
  4214. lpi_status =
  4215. __read_register(device,
  4216. CVP_AON_WRAPPER_CVP_NOC_LPI_STATUS);
  4217. reg_status = lpi_status & BIT(0);
  4218. /* Wait for Core noc lpi status to be set */
  4219. usleep_range(50, 100);
  4220. count++;
  4221. }
  4222. dprintk(CVP_PWR,
  4223. "Core Noc: lpi_status %x noc_status %x (count %d)\n",
  4224. lpi_status, reg_status, count);
  4225. if (count == max_count) {
  4226. u32 pc_ready, wfi_status;
  4227. wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
  4228. pc_ready = __read_register(device, CVP_CTRL_STATUS);
  4229. dprintk(CVP_WARN,
  4230. "Core NOC not in qaccept status %x %x %x %x\n",
  4231. reg_status, lpi_status, wfi_status, pc_ready);
  4232. __print_sidebandmanager_regs(device);
  4233. }
  4234. __write_register(device, CVP_AON_WRAPPER_CVP_NOC_LPI_CONTROL, 0x0);
  4235. if (warn_flag)
  4236. __print_sidebandmanager_regs(device);
  4237. /* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ) */
  4238. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x3);
  4239. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x2);
  4240. __write_register(device, CVP_AHB_BRIDGE_SYNC_RESET, 0x0);
  4241. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, config);
  4242. __disable_hw_power_collapse(device);
  4243. usleep_range(100, 200);
  4244. __disable_regulator(device, "cvp-core");
  4245. msm_cvp_disable_unprepare_clk(device, "core_clk");
  4246. msm_cvp_disable_unprepare_clk(device, "video_cc_mvs1_clk_src");
  4247. return 0;
  4248. }
  4249. static void power_off_iris2(struct iris_hfi_device *device)
  4250. {
  4251. if (!device->power_enabled || !device->res->sw_power_collapsible)
  4252. return;
  4253. if (!(device->intr_status & CVP_WRAPPER_INTR_STATUS_A2HWD_BMSK))
  4254. disable_irq_nosync(device->cvp_hal_data->irq);
  4255. device->intr_status = 0;
  4256. __power_off_core(device);
  4257. __power_off_controller(device);
  4258. if (__unvote_buses(device))
  4259. dprintk(CVP_WARN, "Failed to unvote for buses\n");
  4260. /*Do not access registers after this point!*/
  4261. device->power_enabled = false;
  4262. pr_info(CVP_DBG_TAG "cvp (eva) power collapsed\n", "pwr");
  4263. }
  4264. static inline int __resume(struct iris_hfi_device *device)
  4265. {
  4266. int rc = 0;
  4267. struct msm_cvp_core *core;
  4268. if (!device) {
  4269. dprintk(CVP_ERR, "Invalid params: %pK\n", device);
  4270. return -EINVAL;
  4271. } else if (device->power_enabled) {
  4272. goto exit;
  4273. } else if (!__core_in_valid_state(device)) {
  4274. dprintk(CVP_PWR, "iris_hfi_device in deinit state.");
  4275. return -EINVAL;
  4276. }
  4277. core = cvp_driver->cvp_core;
  4278. dprintk(CVP_PWR, "Resuming from power collapse\n");
  4279. rc = __iris_power_on(device);
  4280. if (rc) {
  4281. dprintk(CVP_ERR, "Failed to power on cvp\n");
  4282. goto err_iris_power_on;
  4283. }
  4284. __setup_ucregion_memory_map(device);
  4285. /* RUMI: set CVP_CTRL_INIT register to disable synx in FW */
  4286. /* Reboot the firmware */
  4287. rc = __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_RESUME);
  4288. if (rc) {
  4289. dprintk(CVP_ERR, "Failed to resume cvp core %d\n", rc);
  4290. goto err_set_cvp_state;
  4291. }
  4292. /* Wait for boot completion */
  4293. rc = __boot_firmware(device);
  4294. if (rc) {
  4295. dprintk(CVP_ERR, "Failed to reset cvp core\n");
  4296. goto err_reset_core;
  4297. }
  4298. /*
  4299. * Work around for H/W bug, need to reprogram these registers once
  4300. * firmware is out reset
  4301. */
  4302. __set_threshold_registers(device);
  4303. if (device->res->pm_qos.latency_us && device->res->pm_qos.pm_qos_hdls)
  4304. cvp_pm_qos_update(device, true);
  4305. __sys_set_debug(device, msm_cvp_fw_debug);
  4306. __enable_subcaches(device);
  4307. __set_subcaches(device);
  4308. __dsp_resume(device);
  4309. dprintk(CVP_PWR, "Resumed from power collapse\n");
  4310. exit:
  4311. /* Don't reset skip_pc_count for SYS_PC_PREP cmd */
  4312. if (device->last_packet_type != HFI_CMD_SYS_PC_PREP)
  4313. device->skip_pc_count = 0;
  4314. return rc;
  4315. err_reset_core:
  4316. __tzbsp_set_cvp_state(TZ_SUBSYS_STATE_SUSPEND);
  4317. err_set_cvp_state:
  4318. call_iris_op(device, power_off, device);
  4319. err_iris_power_on:
  4320. dprintk(CVP_ERR, "Failed to resume from power collapse\n");
  4321. return rc;
  4322. }
  4323. static int __power_on_init(struct iris_hfi_device *device)
  4324. {
  4325. int rc = 0;
  4326. /* Initialize resources */
  4327. rc = __init_resources(device, device->res);
  4328. if (rc) {
  4329. dprintk(CVP_ERR, "Failed to init resources: %d\n", rc);
  4330. return rc;
  4331. }
  4332. rc = __initialize_packetization(device);
  4333. if (rc) {
  4334. dprintk(CVP_ERR, "Failed to initialize packetization\n");
  4335. goto fail_iris_init;
  4336. }
  4337. rc = __iris_power_on(device);
  4338. if (rc) {
  4339. dprintk(CVP_ERR, "Failed to power on iris in in load_fw\n");
  4340. goto fail_iris_init;
  4341. }
  4342. return rc;
  4343. fail_iris_init:
  4344. __deinit_resources(device);
  4345. return rc;
  4346. }
  4347. static int __load_fw(struct iris_hfi_device *device)
  4348. {
  4349. int rc = 0;
  4350. if ((!device->res->use_non_secure_pil && !device->res->firmware_base)
  4351. || device->res->use_non_secure_pil) {
  4352. rc = load_cvp_fw_impl(device);
  4353. if (rc)
  4354. goto fail_load_fw;
  4355. }
  4356. return rc;
  4357. fail_load_fw:
  4358. call_iris_op(device, power_off, device);
  4359. return rc;
  4360. }
  4361. static void __unload_fw(struct iris_hfi_device *device)
  4362. {
  4363. if (!device->resources.fw.cookie)
  4364. return;
  4365. cancel_delayed_work(&iris_hfi_pm_work);
  4366. if (device->state != IRIS_STATE_DEINIT)
  4367. flush_workqueue(device->iris_pm_workq);
  4368. /* New addition to put CPU/Tensilica to low power */
  4369. __enter_cpu_noc_lpi(device);
  4370. unload_cvp_fw_impl(device);
  4371. __interface_queues_release(device);
  4372. call_iris_op(device, power_off, device);
  4373. __deinit_resources(device);
  4374. dprintk(CVP_WARN, "Firmware unloaded\n");
  4375. }
  4376. static int iris_hfi_get_fw_info(void *dev, struct cvp_hal_fw_info *fw_info)
  4377. {
  4378. int i = 0;
  4379. struct iris_hfi_device *device = dev;
  4380. if (!device || !fw_info) {
  4381. dprintk(CVP_ERR,
  4382. "%s Invalid parameter: device = %pK fw_info = %pK\n",
  4383. __func__, device, fw_info);
  4384. return -EINVAL;
  4385. }
  4386. mutex_lock(&device->lock);
  4387. while (cvp_driver->fw_version[i++] != 'V' && i < CVP_VERSION_LENGTH)
  4388. ;
  4389. if (i == CVP_VERSION_LENGTH - 1) {
  4390. dprintk(CVP_WARN, "Iris version string is not proper\n");
  4391. fw_info->version[0] = '\0';
  4392. goto fail_version_string;
  4393. }
  4394. memcpy(&fw_info->version[0], &cvp_driver->fw_version[0],
  4395. CVP_VERSION_LENGTH);
  4396. fw_info->version[CVP_VERSION_LENGTH - 1] = '\0';
  4397. fail_version_string:
  4398. dprintk(CVP_CORE, "F/W version retrieved : %s\n", fw_info->version);
  4399. fw_info->base_addr = device->cvp_hal_data->firmware_base;
  4400. fw_info->register_base = device->res->register_base;
  4401. fw_info->register_size = device->cvp_hal_data->register_size;
  4402. fw_info->irq = device->cvp_hal_data->irq;
  4403. mutex_unlock(&device->lock);
  4404. return 0;
  4405. }
  4406. static int iris_hfi_get_core_capabilities(void *dev)
  4407. {
  4408. dprintk(CVP_CORE, "%s not supported yet!\n", __func__);
  4409. return 0;
  4410. }
  4411. static const char * const mid_names[16] = {
  4412. "CVP_FW",
  4413. "ARP_DATA",
  4414. "CVP_MPU_PIXEL",
  4415. "CVP_MPU_NON_PIXEL",
  4416. "CVP_FDU_PIXEL",
  4417. "CVP_FDU_NON_PIXEL",
  4418. "CVP_GCE_PIXEL",
  4419. "CVP_GCE_NON_PIXEL",
  4420. "CVP_TOF_PIXEL",
  4421. "CVP_TOF_NON_PIXEL",
  4422. "CVP_VADL_PIXEL",
  4423. "CVP_VADL_NON_PIXEL",
  4424. "CVP_RGE_NON_PIXEL",
  4425. "CVP_CDM",
  4426. "Invalid",
  4427. "Invalid"
  4428. };
  4429. static void __print_reg_details(u32 val)
  4430. {
  4431. u32 mid, sid;
  4432. mid = (val >> 5) & 0xF;
  4433. sid = (val >> 2) & 0x7;
  4434. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  4435. dprintk(CVP_ERR, "Sub-client:%s, SID: %d\n", mid_names[mid], sid);
  4436. }
  4437. static void __err_log(bool logging, u32 *data, const char *name, u32 val)
  4438. {
  4439. if (logging)
  4440. *data = val;
  4441. dprintk(CVP_ERR, "%s: %#x\n", name, val);
  4442. }
  4443. static void __noc_error_info_iris2(struct iris_hfi_device *device)
  4444. {
  4445. struct msm_cvp_core *core;
  4446. struct cvp_noc_log *noc_log;
  4447. u32 val = 0, regi, regii, regiii;
  4448. bool log_required = false;
  4449. int rc;
  4450. core = cvp_driver->cvp_core;
  4451. if (!core->ssr_count && core->resources.max_ssr_allowed > 1)
  4452. log_required = true;
  4453. noc_log = &core->log.noc_log;
  4454. if (noc_log->used) {
  4455. dprintk(CVP_WARN, "Data already in NoC log, skip logging\n");
  4456. return;
  4457. }
  4458. noc_log->used = 1;
  4459. __disable_hw_power_collapse(device);
  4460. val = __read_register(device, CVP_CC_MVS1_GDSCR);
  4461. regi = __read_register(device, CVP_AON_WRAPPER_CVP_NOC_CORE_CLK_CONTROL);
  4462. regii = __read_register(device, CVP_CC_MVS1_CBCR);
  4463. regiii = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4464. dprintk(CVP_ERR, "noc reg check: %#x %#x %#x %#x\n",
  4465. val, regi, regii, regiii);
  4466. val = __read_register(device, CVP_NOC_ERR_SWID_LOW_OFFS);
  4467. __err_log(log_required, &noc_log->err_ctrl_swid_low,
  4468. "CVP_NOC_ERL_MAIN_SWID_LOW", val);
  4469. val = __read_register(device, CVP_NOC_ERR_SWID_HIGH_OFFS);
  4470. __err_log(log_required, &noc_log->err_ctrl_swid_high,
  4471. "CVP_NOC_ERL_MAIN_SWID_HIGH", val);
  4472. val = __read_register(device, CVP_NOC_ERR_MAINCTL_LOW_OFFS);
  4473. __err_log(log_required, &noc_log->err_ctrl_mainctl_low,
  4474. "CVP_NOC_ERL_MAIN_MAINCTL_LOW", val);
  4475. val = __read_register(device, CVP_NOC_ERR_ERRVLD_LOW_OFFS);
  4476. __err_log(log_required, &noc_log->err_ctrl_errvld_low,
  4477. "CVP_NOC_ERL_MAIN_ERRVLD_LOW", val);
  4478. val = __read_register(device, CVP_NOC_ERR_ERRCLR_LOW_OFFS);
  4479. __err_log(log_required, &noc_log->err_ctrl_errclr_low,
  4480. "CVP_NOC_ERL_MAIN_ERRCLR_LOW", val);
  4481. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_LOW_OFFS);
  4482. __err_log(log_required, &noc_log->err_ctrl_errlog0_low,
  4483. "CVP_NOC_ERL_MAIN_ERRLOG0_LOW", val);
  4484. val = __read_register(device, CVP_NOC_ERR_ERRLOG0_HIGH_OFFS);
  4485. __err_log(log_required, &noc_log->err_ctrl_errlog0_high,
  4486. "CVP_NOC_ERL_MAIN_ERRLOG0_HIGH", val);
  4487. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_LOW_OFFS);
  4488. __err_log(log_required, &noc_log->err_ctrl_errlog1_low,
  4489. "CVP_NOC_ERL_MAIN_ERRLOG1_LOW", val);
  4490. val = __read_register(device, CVP_NOC_ERR_ERRLOG1_HIGH_OFFS);
  4491. __err_log(log_required, &noc_log->err_ctrl_errlog1_high,
  4492. "CVP_NOC_ERL_MAIN_ERRLOG1_HIGH", val);
  4493. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_LOW_OFFS);
  4494. __err_log(log_required, &noc_log->err_ctrl_errlog2_low,
  4495. "CVP_NOC_ERL_MAIN_ERRLOG2_LOW", val);
  4496. val = __read_register(device, CVP_NOC_ERR_ERRLOG2_HIGH_OFFS);
  4497. __err_log(log_required, &noc_log->err_ctrl_errlog2_high,
  4498. "CVP_NOC_ERL_MAIN_ERRLOG2_HIGH", val);
  4499. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_LOW_OFFS);
  4500. __err_log(log_required, &noc_log->err_ctrl_errlog3_low,
  4501. "CVP_NOC_ERL_MAIN_ERRLOG3_LOW", val);
  4502. val = __read_register(device, CVP_NOC_ERR_ERRLOG3_HIGH_OFFS);
  4503. __err_log(log_required, &noc_log->err_ctrl_errlog3_high,
  4504. "CVP_NOC_ERL_MAIN_ERRLOG3_HIGH", val);
  4505. rc = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4506. if (rc) {
  4507. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  4508. return;
  4509. }
  4510. val = __read_register(device,
  4511. CVP_NOC_CORE_ERR_SWID_LOW_OFFS + device->res->noc_core_err_offset);
  4512. __err_log(log_required, &noc_log->err_core_swid_low,
  4513. "CVP_NOC__CORE_ERL_MAIN_SWID_LOW", val);
  4514. val = __read_register(device,
  4515. CVP_NOC_CORE_ERR_SWID_HIGH_OFFS + device->res->noc_core_err_offset);
  4516. __err_log(log_required, &noc_log->err_core_swid_high,
  4517. "CVP_NOC_CORE_ERL_MAIN_SWID_HIGH", val);
  4518. val = __read_register(device,
  4519. CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS + device->res->noc_core_err_offset);
  4520. __err_log(log_required, &noc_log->err_core_mainctl_low,
  4521. "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW", val);
  4522. val = __read_register(device,
  4523. CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS + device->res->noc_core_err_offset);
  4524. __err_log(log_required, &noc_log->err_core_errvld_low,
  4525. "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW", val);
  4526. val = __read_register(device,
  4527. CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS + device->res->noc_core_err_offset);
  4528. __err_log(log_required, &noc_log->err_core_errclr_low,
  4529. "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW", val);
  4530. val = __read_register(device,
  4531. CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS + device->res->noc_core_err_offset);
  4532. __err_log(log_required, &noc_log->err_core_errlog0_low,
  4533. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW", val);
  4534. val = __read_register(device,
  4535. CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS + device->res->noc_core_err_offset);
  4536. __err_log(log_required, &noc_log->err_core_errlog0_high,
  4537. "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH", val);
  4538. val = __read_register(device,
  4539. CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS + device->res->noc_core_err_offset);
  4540. __err_log(log_required, &noc_log->err_core_errlog1_low,
  4541. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW", val);
  4542. val = __read_register(device,
  4543. CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS + device->res->noc_core_err_offset);
  4544. __err_log(log_required, &noc_log->err_core_errlog1_high,
  4545. "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH", val);
  4546. val = __read_register(device,
  4547. CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS + device->res->noc_core_err_offset);
  4548. __err_log(log_required, &noc_log->err_core_errlog2_low,
  4549. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW", val);
  4550. val = __read_register(device,
  4551. CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS + device->res->noc_core_err_offset);
  4552. __err_log(log_required, &noc_log->err_core_errlog2_high,
  4553. "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH", val);
  4554. val = __read_register(device,
  4555. CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS + device->res->noc_core_err_offset);
  4556. __err_log(log_required, &noc_log->err_core_errlog3_low,
  4557. "CORE ERRLOG3_LOW, below details", val);
  4558. __print_reg_details(val);
  4559. val = __read_register(device,
  4560. CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS + device->res->noc_core_err_offset);
  4561. __err_log(log_required, &noc_log->err_core_errlog3_high,
  4562. "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH", val);
  4563. __write_register(device,
  4564. CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS + device->res->noc_core_err_offset, 0x1);
  4565. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4566. #define CVP_SS_CLK_HALT 0x8
  4567. #define CVP_SS_CLK_EN 0xC
  4568. #define CVP_SS_ARP_TEST_BUS_CONTROL 0x700
  4569. #define CVP_SS_ARP_TEST_BUS_REGISTER 0x704
  4570. #define CVP_DMA_TEST_BUS_CONTROL 0x66A0
  4571. #define CVP_DMA_TEST_BUS_REGISTER 0x66A4
  4572. #define CVP_VPU_WRAPPER_CORE_CONFIG 0xB0088
  4573. __write_register(device, CVP_SS_CLK_HALT, 0);
  4574. __write_register(device, CVP_SS_CLK_EN, 0x3f);
  4575. __write_register(device, CVP_VPU_WRAPPER_CORE_CONFIG, 0);
  4576. }
  4577. static int iris_hfi_noc_error_info(void *dev)
  4578. {
  4579. struct iris_hfi_device *device;
  4580. if (!dev) {
  4581. dprintk(CVP_ERR, "%s: null device\n", __func__);
  4582. return -EINVAL;
  4583. }
  4584. device = dev;
  4585. mutex_lock(&device->lock);
  4586. dprintk(CVP_ERR, "%s: non error information\n", __func__);
  4587. call_iris_op(device, noc_error_info, device);
  4588. mutex_unlock(&device->lock);
  4589. return 0;
  4590. }
  4591. static int __initialize_packetization(struct iris_hfi_device *device)
  4592. {
  4593. int rc = 0;
  4594. if (!device || !device->res) {
  4595. dprintk(CVP_ERR, "%s - invalid param\n", __func__);
  4596. return -EINVAL;
  4597. }
  4598. device->packetization_type = HFI_PACKETIZATION_4XX;
  4599. device->pkt_ops = cvp_hfi_get_pkt_ops_handle(
  4600. device->packetization_type);
  4601. if (!device->pkt_ops) {
  4602. rc = -EINVAL;
  4603. dprintk(CVP_ERR, "Failed to get pkt_ops handle\n");
  4604. }
  4605. return rc;
  4606. }
  4607. void __init_cvp_ops(struct iris_hfi_device *device)
  4608. {
  4609. device->hal_ops = &hal_ops;
  4610. }
  4611. static struct iris_hfi_device *__add_device(struct msm_cvp_platform_resources *res,
  4612. hfi_cmd_response_callback callback)
  4613. {
  4614. struct iris_hfi_device *hdevice = NULL;
  4615. int rc = 0;
  4616. if (!res || !callback) {
  4617. dprintk(CVP_ERR, "Invalid Parameters\n");
  4618. return NULL;
  4619. }
  4620. hdevice = kzalloc(sizeof(*hdevice), GFP_KERNEL);
  4621. if (!hdevice) {
  4622. dprintk(CVP_ERR, "failed to allocate new device\n");
  4623. goto exit;
  4624. }
  4625. hdevice->response_pkt = kmalloc_array(cvp_max_packets,
  4626. sizeof(*hdevice->response_pkt), GFP_KERNEL);
  4627. if (!hdevice->response_pkt) {
  4628. dprintk(CVP_ERR, "failed to allocate response_pkt\n");
  4629. goto err_cleanup;
  4630. }
  4631. hdevice->raw_packet =
  4632. kzalloc(CVP_IFACEQ_VAR_HUGE_PKT_SIZE, GFP_KERNEL);
  4633. if (!hdevice->raw_packet) {
  4634. dprintk(CVP_ERR, "failed to allocate raw packet\n");
  4635. goto err_cleanup;
  4636. }
  4637. rc = vm_manager.vm_ops->vm_init_reg_and_irq(hdevice, res);
  4638. if (rc)
  4639. goto err_cleanup;
  4640. hdevice->res = res;
  4641. hdevice->callback = callback;
  4642. __init_cvp_ops(hdevice);
  4643. hdevice->cvp_workq = create_singlethread_workqueue(
  4644. "msm_cvp_workerq_iris");
  4645. if (!hdevice->cvp_workq) {
  4646. dprintk(CVP_ERR, ": create cvp workq failed\n");
  4647. goto err_cleanup;
  4648. }
  4649. hdevice->iris_pm_workq = create_singlethread_workqueue(
  4650. "pm_workerq_iris");
  4651. if (!hdevice->iris_pm_workq) {
  4652. dprintk(CVP_ERR, ": create pm workq failed\n");
  4653. goto err_cleanup;
  4654. }
  4655. mutex_init(&hdevice->lock);
  4656. INIT_LIST_HEAD(&hdevice->sess_head);
  4657. return hdevice;
  4658. err_cleanup:
  4659. if (hdevice->iris_pm_workq)
  4660. destroy_workqueue(hdevice->iris_pm_workq);
  4661. if (hdevice->cvp_workq)
  4662. destroy_workqueue(hdevice->cvp_workq);
  4663. kfree(hdevice->response_pkt);
  4664. kfree(hdevice->raw_packet);
  4665. kfree(hdevice);
  4666. exit:
  4667. return NULL;
  4668. }
  4669. static struct iris_hfi_device *__get_device(struct msm_cvp_platform_resources *res,
  4670. hfi_cmd_response_callback callback)
  4671. {
  4672. if (!res || !callback) {
  4673. dprintk(CVP_ERR, "Invalid params: %pK %pK\n", res, callback);
  4674. return NULL;
  4675. }
  4676. return __add_device(res, callback);
  4677. }
  4678. void cvp_iris_hfi_delete_device(void *device)
  4679. {
  4680. struct msm_cvp_core *core;
  4681. struct iris_hfi_device *dev = NULL;
  4682. if (!device)
  4683. return;
  4684. core = cvp_driver->cvp_core;
  4685. if (core)
  4686. dev = core->dev_ops->hfi_device_data;
  4687. if (!dev)
  4688. return;
  4689. mutex_destroy(&dev->lock);
  4690. destroy_workqueue(dev->cvp_workq);
  4691. destroy_workqueue(dev->iris_pm_workq);
  4692. free_irq(dev->cvp_hal_data->irq, dev);
  4693. iounmap(dev->cvp_hal_data->register_base);
  4694. iounmap(dev->cvp_hal_data->gcc_reg_base);
  4695. kfree(dev->cvp_hal_data);
  4696. kfree(dev->response_pkt);
  4697. kfree(dev->raw_packet);
  4698. kfree(dev);
  4699. }
  4700. static int iris_hfi_validate_session(void *sess, const char *func)
  4701. {
  4702. struct cvp_hal_session *session = sess;
  4703. int rc = 0;
  4704. struct iris_hfi_device *device;
  4705. if (!session || !session->device) {
  4706. dprintk(CVP_ERR, " %s Invalid Params %pK\n", __func__, session);
  4707. return -EINVAL;
  4708. }
  4709. device = session->device;
  4710. mutex_lock(&device->lock);
  4711. if (!__is_session_valid(device, session, func))
  4712. rc = -ECONNRESET;
  4713. mutex_unlock(&device->lock);
  4714. return rc;
  4715. }
  4716. static void iris_init_hfi_callbacks(struct cvp_hfi_ops *ops_tbl)
  4717. {
  4718. ops_tbl->core_init = iris_hfi_core_init;
  4719. ops_tbl->core_release = iris_hfi_core_release;
  4720. ops_tbl->core_trigger_ssr = iris_hfi_core_trigger_ssr;
  4721. ops_tbl->session_init = iris_hfi_session_init;
  4722. ops_tbl->session_end = iris_hfi_session_end;
  4723. ops_tbl->session_start = iris_hfi_session_start;
  4724. ops_tbl->session_stop = iris_hfi_session_stop;
  4725. ops_tbl->session_abort = iris_hfi_session_abort;
  4726. ops_tbl->session_clean = iris_hfi_session_clean;
  4727. ops_tbl->session_set_buffers = iris_hfi_session_set_buffers;
  4728. ops_tbl->session_release_buffers = iris_hfi_session_release_buffers;
  4729. ops_tbl->session_send = iris_hfi_session_send;
  4730. ops_tbl->session_flush = iris_hfi_session_flush;
  4731. ops_tbl->scale_clocks = iris_hfi_scale_clocks;
  4732. ops_tbl->vote_bus = iris_hfi_vote_buses;
  4733. ops_tbl->get_fw_info = iris_hfi_get_fw_info;
  4734. ops_tbl->get_core_capabilities = iris_hfi_get_core_capabilities;
  4735. ops_tbl->suspend = iris_hfi_suspend;
  4736. ops_tbl->resume = iris_hfi_resume;
  4737. ops_tbl->flush_debug_queue = iris_hfi_flush_debug_queue;
  4738. ops_tbl->noc_error_info = iris_hfi_noc_error_info;
  4739. ops_tbl->validate_session = iris_hfi_validate_session;
  4740. ops_tbl->pm_qos_update = iris_pm_qos_update;
  4741. ops_tbl->debug_hook = iris_debug_hook;
  4742. }
  4743. int cvp_iris_hfi_initialize(struct cvp_hfi_ops *ops_tbl,
  4744. struct msm_cvp_platform_resources *res,
  4745. hfi_cmd_response_callback callback)
  4746. {
  4747. int rc = 0;
  4748. if (!ops_tbl || !res || !callback) {
  4749. dprintk(CVP_ERR, "Invalid params: %pK %pK %pK\n",
  4750. ops_tbl, res, callback);
  4751. rc = -EINVAL;
  4752. goto err_iris_hfi_init;
  4753. }
  4754. ops_tbl->hfi_device_data = __get_device(res, callback);
  4755. if (IS_ERR_OR_NULL(ops_tbl->hfi_device_data)) {
  4756. rc = PTR_ERR(ops_tbl->hfi_device_data) ?: -EINVAL;
  4757. goto err_iris_hfi_init;
  4758. }
  4759. iris_init_hfi_callbacks(ops_tbl);
  4760. err_iris_hfi_init:
  4761. return rc;
  4762. }
  4763. static void dump_noc_reg(struct iris_hfi_device *device)
  4764. {
  4765. u32 val = 0, config;
  4766. int i;
  4767. struct regulator_info *rinfo;
  4768. int rc = 0;
  4769. if (msm_cvp_fw_low_power_mode) {
  4770. iris_hfi_for_each_regulator(device, rinfo) {
  4771. if (strcmp(rinfo->name, "cvp-core"))
  4772. continue;
  4773. rc = __acquire_regulator(rinfo, device);
  4774. if (rc)
  4775. dprintk(CVP_WARN,
  4776. "%s, Failed to acquire regulator control: %s\n",
  4777. __func__, rinfo->name);
  4778. }
  4779. }
  4780. val = __read_register(device, CVP_CC_MVS1_GDSCR);
  4781. dprintk(CVP_ERR, "%s, CVP_CC_MVS1_GDSCR: 0x%x", __func__, val);
  4782. config = __read_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG);
  4783. dprintk(CVP_ERR, "%s, CVP_WRAPPER_CORE_CLOCK_CONFIG: 0x%x", __func__, config);
  4784. if (config) {
  4785. dprintk(CVP_PWR,
  4786. "core clock config not enabled, enable it to access core\n");
  4787. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, 0);
  4788. }
  4789. i = call_iris_op(device, reset_control_acquire_name, device, "cvp_xo_reset");
  4790. if (i) {
  4791. dprintk(CVP_WARN, "%s Fail acquire xo_reset\n", __func__);
  4792. return;
  4793. }
  4794. val = __read_register(device, CVP_NOC_RGE_NIU_DECCTL_LOW
  4795. + device->res->qos_noc_rge_niu_offset);
  4796. dprintk(CVP_ERR, "CVP_NOC_RGE_NIU_DECCTL_LOW: 0x%x", val);
  4797. val = __read_register(device, CVP_NOC_RGE_NIU_ENCCTL_LOW
  4798. + device->res->qos_noc_rge_niu_offset);
  4799. dprintk(CVP_ERR, "CVP_NOC_RGE_NIU_ENCCTL_LOW: 0x%x", val);
  4800. val = __read_register(device, CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW
  4801. + device->res->qos_noc_gce_vadl_tof_niu_offset);
  4802. dprintk(CVP_ERR, "CVP_NOC_GCE_VADL_TOF_NIU_DECCTL_LOW: 0x%x", val);
  4803. val = __read_register(device, CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW
  4804. + device->res->qos_noc_gce_vadl_tof_niu_offset);
  4805. dprintk(CVP_ERR, "CVP_NOC_GCE_VADL_TOF_NIU_ENCCTL_LOW: 0x%x", val);
  4806. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS
  4807. + device->res->noc_core_err_offset);
  4808. dprintk(CVP_ERR, "CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS: 0x%x", val);
  4809. val = __read_register(device, CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW
  4810. + device->res->noc_main_sidebandmanager_offset);
  4811. dprintk(CVP_ERR, "CVP_NOC_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW: 0x%x", val);
  4812. dprintk(CVP_ERR, "Dumping Core NoC registers\n");
  4813. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_LOW_OFFS
  4814. + device->res->noc_core_err_offset);
  4815. dprintk(CVP_ERR, "CVP_NOC__CORE_ERL_MAIN_SWID_LOW: 0x%x", val);
  4816. val = __read_register(device, CVP_NOC_CORE_ERR_SWID_HIGH_OFFS
  4817. + device->res->noc_core_err_offset);
  4818. dprintk(CVP_ERR, "CVVP_NOC_CORE_ERL_MAIN_SWID_HIGH 0x%x", val);
  4819. val = __read_register(device, CVP_NOC_CORE_ERR_MAINCTL_LOW_OFFS
  4820. + device->res->noc_core_err_offset);
  4821. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_MAINCTL_LOW 0x%x", val);
  4822. val = __read_register(device, CVP_NOC_CORE_ERR_ERRVLD_LOW_OFFS
  4823. + device->res->noc_core_err_offset);
  4824. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRVLD_LOW 0x%x", val);
  4825. val = __read_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS
  4826. + device->res->noc_core_err_offset);
  4827. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRCLR_LOW 0x%x", val);
  4828. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_LOW_OFFS
  4829. + device->res->noc_core_err_offset);
  4830. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_LOW 0x%x", val);
  4831. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG0_HIGH_OFFS
  4832. + device->res->noc_core_err_offset);
  4833. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG0_HIGH 0x%x", val);
  4834. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_LOW_OFFS
  4835. + device->res->noc_core_err_offset);
  4836. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_LOW 0x%x", val);
  4837. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG1_HIGH_OFFS
  4838. + device->res->noc_core_err_offset);
  4839. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG1_HIGH 0x%x", val);
  4840. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_LOW_OFFS
  4841. + device->res->noc_core_err_offset);
  4842. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_LOW 0x%x", val);
  4843. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG2_HIGH_OFFS
  4844. + device->res->noc_core_err_offset);
  4845. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG2_HIGH 0x%x", val);
  4846. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_LOW_OFFS
  4847. + device->res->noc_core_err_offset);
  4848. dprintk(CVP_ERR, "CORE ERRLOG3_LOW 0x%x, below details", val);
  4849. __print_reg_details(val);
  4850. val = __read_register(device, CVP_NOC_CORE_ERR_ERRLOG3_HIGH_OFFS
  4851. + device->res->noc_core_err_offset);
  4852. dprintk(CVP_ERR, "CVP_NOC_CORE_ERL_MAIN_ERRLOG3_HIGH 0x%x", val);
  4853. __write_register(device, CVP_NOC_CORE_ERR_ERRCLR_LOW_OFFS
  4854. + device->res->noc_core_err_offset, 0x1);
  4855. call_iris_op(device, reset_control_release_name, device, "cvp_xo_reset");
  4856. if (msm_cvp_fw_low_power_mode) {
  4857. iris_hfi_for_each_regulator(device, rinfo) {
  4858. if (strcmp(rinfo->name, "cvp-core"))
  4859. continue;
  4860. rc = __hand_off_regulator(device, rinfo);
  4861. }
  4862. }
  4863. __write_register(device, CVP_WRAPPER_CORE_CLOCK_CONFIG, config);
  4864. }