dp_main.c 156 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <qdf_module.h>
  23. #include <hal_api.h>
  24. #include <hif.h>
  25. #include <htt.h>
  26. #include <wdi_event.h>
  27. #include <queue.h>
  28. #include "dp_htt.h"
  29. #include "dp_types.h"
  30. #include "dp_internal.h"
  31. #include "dp_tx.h"
  32. #include "dp_tx_desc.h"
  33. #include "dp_rx.h"
  34. #include <cdp_txrx_handle.h>
  35. #include <wlan_cfg.h>
  36. #include "cdp_txrx_cmn_struct.h"
  37. #include <qdf_util.h>
  38. #include "dp_peer.h"
  39. #include "dp_rx_mon.h"
  40. #include "htt_stats.h"
  41. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  42. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  43. #include "cdp_txrx_flow_ctrl_v2.h"
  44. #else
  45. static inline void
  46. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  47. {
  48. return;
  49. }
  50. #endif
  51. #include <ol_cfg.h>
  52. #include "dp_ipa.h"
  53. #define DP_INTR_POLL_TIMER_MS 10
  54. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  55. #define DP_MCS_LENGTH (6*MAX_MCS)
  56. #define DP_NSS_LENGTH (6*SS_COUNT)
  57. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  58. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  59. #define DP_MAX_MCS_STRING_LEN 30
  60. #define DP_CURR_FW_STATS_AVAIL 19
  61. #define DP_HTT_DBG_EXT_STATS_MAX 256
  62. #ifdef IPA_OFFLOAD
  63. /* Exclude IPA rings from the interrupt context */
  64. #define TX_RING_MASK_VAL 0x7
  65. #define RX_RING_MASK_VAL 0x7
  66. #else
  67. #define TX_RING_MASK_VAL 0xF
  68. #define RX_RING_MASK_VAL 0xF
  69. #endif
  70. bool rx_hash = 1;
  71. qdf_declare_param(rx_hash, bool);
  72. #define STR_MAXLEN 64
  73. /**
  74. * default_dscp_tid_map - Default DSCP-TID mapping
  75. *
  76. * DSCP TID AC
  77. * 000000 0 WME_AC_BE
  78. * 001000 1 WME_AC_BK
  79. * 010000 1 WME_AC_BK
  80. * 011000 0 WME_AC_BE
  81. * 100000 5 WME_AC_VI
  82. * 101000 5 WME_AC_VI
  83. * 110000 6 WME_AC_VO
  84. * 111000 6 WME_AC_VO
  85. */
  86. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  87. 0, 0, 0, 0, 0, 0, 0, 0,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 1, 1, 1, 1, 1, 1, 1, 1,
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 5, 5, 5, 5, 5, 5, 5, 5,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. 6, 6, 6, 6, 6, 6, 6, 6,
  95. };
  96. /*
  97. * struct dp_rate_debug
  98. *
  99. * @mcs_type: print string for a given mcs
  100. * @valid: valid mcs rate?
  101. */
  102. struct dp_rate_debug {
  103. char mcs_type[DP_MAX_MCS_STRING_LEN];
  104. uint8_t valid;
  105. };
  106. #define MCS_VALID 1
  107. #define MCS_INVALID 0
  108. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  109. {
  110. {"CCK 11 Mbps Long ", MCS_VALID},
  111. {"CCK 5.5 Mbps Long ", MCS_VALID},
  112. {"CCK 2 Mbps Long ", MCS_VALID},
  113. {"CCK 1 Mbps Long ", MCS_VALID},
  114. {"CCK 11 Mbps Short ", MCS_VALID},
  115. {"CCK 5.5 Mbps Short", MCS_VALID},
  116. {"CCK 2 Mbps Short ", MCS_VALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_INVALID},
  122. {"INVALID ", MCS_VALID},
  123. },
  124. {
  125. {"OFDM 48 Mbps", MCS_VALID},
  126. {"OFDM 24 Mbps", MCS_VALID},
  127. {"OFDM 12 Mbps", MCS_VALID},
  128. {"OFDM 6 Mbps ", MCS_VALID},
  129. {"OFDM 54 Mbps", MCS_VALID},
  130. {"OFDM 36 Mbps", MCS_VALID},
  131. {"OFDM 18 Mbps", MCS_VALID},
  132. {"OFDM 9 Mbps ", MCS_VALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_VALID},
  138. },
  139. {
  140. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  142. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  143. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  144. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  145. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  146. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  147. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_VALID},
  153. },
  154. {
  155. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  157. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  158. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  159. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  161. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  162. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  163. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  164. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  166. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  167. {"INVALID ", MCS_VALID},
  168. },
  169. {
  170. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  172. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  173. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  174. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  176. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  177. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  178. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  179. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  181. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  182. {"INVALID ", MCS_VALID},
  183. }
  184. };
  185. /**
  186. * @brief Cpu ring map types
  187. */
  188. enum dp_cpu_ring_map_types {
  189. DP_DEFAULT_MAP,
  190. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  191. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  192. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  193. DP_CPU_RING_MAP_MAX
  194. };
  195. /**
  196. * @brief Cpu to tx ring map
  197. */
  198. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  199. {0x0, 0x1, 0x2, 0x0},
  200. {0x1, 0x2, 0x1, 0x2},
  201. {0x0, 0x2, 0x0, 0x2},
  202. {0x2, 0x2, 0x2, 0x2}
  203. };
  204. /**
  205. * @brief Select the type of statistics
  206. */
  207. enum dp_stats_type {
  208. STATS_FW = 0,
  209. STATS_HOST = 1,
  210. STATS_TYPE_MAX = 2,
  211. };
  212. /**
  213. * @brief General Firmware statistics options
  214. *
  215. */
  216. enum dp_fw_stats {
  217. TXRX_FW_STATS_INVALID = -1,
  218. };
  219. /**
  220. * dp_stats_mapping_table - Firmware and Host statistics
  221. * currently supported
  222. */
  223. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  224. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  235. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  243. /* Last ENUM for HTT FW STATS */
  244. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  245. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  251. {TXRX_FW_STATS_INVALID, TXRX_SRNG_PTR_STATS},
  252. };
  253. /**
  254. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  255. * @ring_num: ring num of the ring being queried
  256. * @grp_mask: the grp_mask array for the ring type in question.
  257. *
  258. * The grp_mask array is indexed by group number and the bit fields correspond
  259. * to ring numbers. We are finding which interrupt group a ring belongs to.
  260. *
  261. * Return: the index in the grp_mask array with the ring number.
  262. * -QDF_STATUS_E_NOENT if no entry is found
  263. */
  264. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  265. {
  266. int ext_group_num;
  267. int mask = 1 << ring_num;
  268. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  269. ext_group_num++) {
  270. if (mask & grp_mask[ext_group_num])
  271. return ext_group_num;
  272. }
  273. return -QDF_STATUS_E_NOENT;
  274. }
  275. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  276. enum hal_ring_type ring_type,
  277. int ring_num)
  278. {
  279. int *grp_mask;
  280. switch (ring_type) {
  281. case WBM2SW_RELEASE:
  282. /* dp_tx_comp_handler - soc->tx_comp_ring */
  283. if (ring_num < 3)
  284. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  285. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  286. else if (ring_num == 3) {
  287. /* sw treats this as a separate ring type */
  288. grp_mask = &soc->wlan_cfg_ctx->
  289. int_rx_wbm_rel_ring_mask[0];
  290. ring_num = 0;
  291. } else {
  292. qdf_assert(0);
  293. return -QDF_STATUS_E_NOENT;
  294. }
  295. break;
  296. case REO_EXCEPTION:
  297. /* dp_rx_err_process - &soc->reo_exception_ring */
  298. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  299. break;
  300. case REO_DST:
  301. /* dp_rx_process - soc->reo_dest_ring */
  302. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  303. break;
  304. case REO_STATUS:
  305. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  306. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  307. break;
  308. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  309. case RXDMA_MONITOR_STATUS:
  310. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  311. case RXDMA_MONITOR_DST:
  312. /* dp_mon_process */
  313. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  314. break;
  315. case RXDMA_DST:
  316. /* dp_rxdma_err_process */
  317. grp_mask = &soc->wlan_cfg_ctx->int_rxdma2host_ring_mask[0];
  318. break;
  319. case RXDMA_MONITOR_BUF:
  320. case RXDMA_BUF:
  321. /* TODO: support low_thresh interrupt */
  322. return -QDF_STATUS_E_NOENT;
  323. break;
  324. case TCL_DATA:
  325. case TCL_CMD:
  326. case REO_CMD:
  327. case SW2WBM_RELEASE:
  328. case WBM_IDLE_LINK:
  329. /* normally empty SW_TO_HW rings */
  330. return -QDF_STATUS_E_NOENT;
  331. break;
  332. case TCL_STATUS:
  333. case REO_REINJECT:
  334. /* misc unused rings */
  335. return -QDF_STATUS_E_NOENT;
  336. break;
  337. case CE_SRC:
  338. case CE_DST:
  339. case CE_DST_STATUS:
  340. /* CE_rings - currently handled by hif */
  341. default:
  342. return -QDF_STATUS_E_NOENT;
  343. break;
  344. }
  345. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  346. }
  347. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  348. *ring_params, int ring_type, int ring_num)
  349. {
  350. int msi_group_number;
  351. int msi_data_count;
  352. int ret;
  353. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  354. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  355. &msi_data_count, &msi_data_start,
  356. &msi_irq_start);
  357. if (ret)
  358. return;
  359. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  360. ring_num);
  361. if (msi_group_number < 0) {
  362. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  363. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  364. ring_type, ring_num);
  365. ring_params->msi_addr = 0;
  366. ring_params->msi_data = 0;
  367. return;
  368. }
  369. if (msi_group_number > msi_data_count) {
  370. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  371. FL("2 msi_groups will share an msi; msi_group_num %d"),
  372. msi_group_number);
  373. QDF_ASSERT(0);
  374. }
  375. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  376. ring_params->msi_addr = addr_low;
  377. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  378. ring_params->msi_data = (msi_group_number % msi_data_count)
  379. + msi_data_start;
  380. ring_params->flags |= HAL_SRNG_MSI_INTR;
  381. }
  382. /**
  383. * dp_print_ast_stats() - Dump AST table contents
  384. * @soc: Datapath soc handle
  385. *
  386. * return void
  387. */
  388. #ifdef FEATURE_WDS
  389. static void dp_print_ast_stats(struct dp_soc *soc)
  390. {
  391. uint8_t i;
  392. uint8_t num_entries = 0;
  393. struct dp_vdev *vdev;
  394. struct dp_pdev *pdev;
  395. struct dp_peer *peer;
  396. struct dp_ast_entry *ase, *tmp_ase;
  397. DP_PRINT_STATS("AST Stats:");
  398. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  399. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  400. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  401. DP_PRINT_STATS("AST Table:");
  402. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  403. pdev = soc->pdev_list[i];
  404. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  405. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  406. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  407. DP_PRINT_STATS("%6d mac_addr = %pM"
  408. " peer_mac_addr = %pM"
  409. " type = %d"
  410. " next_hop = %d"
  411. " is_active = %d"
  412. " is_bss = %d",
  413. ++num_entries,
  414. ase->mac_addr.raw,
  415. ase->peer->mac_addr.raw,
  416. ase->type,
  417. ase->next_hop,
  418. ase->is_active,
  419. ase->is_bss);
  420. }
  421. }
  422. }
  423. }
  424. }
  425. #else
  426. static void dp_print_ast_stats(struct dp_soc *soc)
  427. {
  428. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  429. return;
  430. }
  431. #endif
  432. /*
  433. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  434. */
  435. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  436. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  437. {
  438. void *hal_soc = soc->hal_soc;
  439. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  440. /* TODO: See if we should get align size from hal */
  441. uint32_t ring_base_align = 8;
  442. struct hal_srng_params ring_params;
  443. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  444. /* TODO: Currently hal layer takes care of endianness related settings.
  445. * See if these settings need to passed from DP layer
  446. */
  447. ring_params.flags = 0;
  448. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  449. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  450. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  451. srng->hal_srng = NULL;
  452. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  453. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  454. soc->osdev, soc->osdev->dev, srng->alloc_size,
  455. &(srng->base_paddr_unaligned));
  456. if (!srng->base_vaddr_unaligned) {
  457. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  458. FL("alloc failed - ring_type: %d, ring_num %d"),
  459. ring_type, ring_num);
  460. return QDF_STATUS_E_NOMEM;
  461. }
  462. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  463. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  464. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  465. ((unsigned long)(ring_params.ring_base_vaddr) -
  466. (unsigned long)srng->base_vaddr_unaligned);
  467. ring_params.num_entries = num_entries;
  468. if (soc->intr_mode == DP_INTR_MSI) {
  469. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  470. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  471. FL("Using MSI for ring_type: %d, ring_num %d"),
  472. ring_type, ring_num);
  473. } else {
  474. ring_params.msi_data = 0;
  475. ring_params.msi_addr = 0;
  476. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  477. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  478. ring_type, ring_num);
  479. }
  480. /*
  481. * Setup interrupt timer and batch counter thresholds for
  482. * interrupt mitigation based on ring type
  483. */
  484. if (ring_type == REO_DST) {
  485. ring_params.intr_timer_thres_us =
  486. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  487. ring_params.intr_batch_cntr_thres_entries =
  488. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  489. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  490. ring_params.intr_timer_thres_us =
  491. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  492. ring_params.intr_batch_cntr_thres_entries =
  493. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  494. } else {
  495. ring_params.intr_timer_thres_us =
  496. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  497. ring_params.intr_batch_cntr_thres_entries =
  498. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  499. }
  500. /* Enable low threshold interrupts for rx buffer rings (regular and
  501. * monitor buffer rings.
  502. * TODO: See if this is required for any other ring
  503. */
  504. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  505. /* TODO: Setting low threshold to 1/8th of ring size
  506. * see if this needs to be configurable
  507. */
  508. ring_params.low_threshold = num_entries >> 3;
  509. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  510. ring_params.intr_timer_thres_us = 0x1000;
  511. }
  512. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  513. mac_id, &ring_params);
  514. return 0;
  515. }
  516. /**
  517. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  518. * Any buffers allocated and attached to ring entries are expected to be freed
  519. * before calling this function.
  520. */
  521. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  522. int ring_type, int ring_num)
  523. {
  524. if (!srng->hal_srng) {
  525. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  526. FL("Ring type: %d, num:%d not setup"),
  527. ring_type, ring_num);
  528. return;
  529. }
  530. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  531. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  532. srng->alloc_size,
  533. srng->base_vaddr_unaligned,
  534. srng->base_paddr_unaligned, 0);
  535. srng->hal_srng = NULL;
  536. }
  537. #ifdef IPA_OFFLOAD
  538. /**
  539. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  540. * @soc: data path instance
  541. * @pdev: core txrx pdev context
  542. *
  543. * Free allocated TX buffers with WBM SRNG
  544. *
  545. * Return: none
  546. */
  547. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  548. {
  549. int idx;
  550. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  551. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  552. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  553. }
  554. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  555. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  556. }
  557. /**
  558. * dp_rx_ipa_uc_detach - free autonomy RX resources
  559. * @soc: data path instance
  560. * @pdev: core txrx pdev context
  561. *
  562. * This function will detach DP RX into main device context
  563. * will free DP Rx resources.
  564. *
  565. * Return: none
  566. */
  567. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  568. {
  569. }
  570. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  571. {
  572. /* TX resource detach */
  573. dp_tx_ipa_uc_detach(soc, pdev);
  574. /* RX resource detach */
  575. dp_rx_ipa_uc_detach(soc, pdev);
  576. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  577. return QDF_STATUS_SUCCESS; /* success */
  578. }
  579. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  580. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  581. /**
  582. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  583. * @soc: data path instance
  584. * @pdev: Physical device handle
  585. *
  586. * Allocate TX buffer from non-cacheable memory
  587. * Attache allocated TX buffers with WBM SRNG
  588. *
  589. * Return: int
  590. */
  591. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  592. {
  593. uint32_t tx_buffer_count;
  594. uint32_t ring_base_align = 8;
  595. void *buffer_vaddr_unaligned;
  596. void *buffer_vaddr;
  597. qdf_dma_addr_t buffer_paddr_unaligned;
  598. qdf_dma_addr_t buffer_paddr;
  599. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  600. uint32_t paddr_lo;
  601. uint32_t paddr_hi;
  602. void *ring_entry;
  603. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  604. int retval = QDF_STATUS_SUCCESS;
  605. /*
  606. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  607. * unsigned int uc_tx_buf_sz =
  608. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  609. */
  610. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  611. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  612. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  613. "requested %d buffers to be posted to wbm ring",
  614. ring_size);
  615. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  616. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  617. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  618. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  619. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  620. return -ENOMEM;
  621. }
  622. hal_srng_access_start(soc->hal_soc, wbm_srng);
  623. /* Allocate TX buffers as many as possible */
  624. for (tx_buffer_count = 0;
  625. tx_buffer_count < ring_size; tx_buffer_count++) {
  626. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  627. if (!ring_entry) {
  628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  629. "Failed to get WBM ring entry\n");
  630. goto fail;
  631. }
  632. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  633. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  634. if (!buffer_vaddr_unaligned) {
  635. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  636. "IPA WDI TX buffer alloc fail %d allocated\n",
  637. tx_buffer_count);
  638. break;
  639. }
  640. buffer_vaddr = buffer_vaddr_unaligned +
  641. ((unsigned long)buffer_vaddr_unaligned %
  642. ring_base_align);
  643. buffer_paddr = buffer_paddr_unaligned +
  644. ((unsigned long)(buffer_vaddr) -
  645. (unsigned long)buffer_vaddr_unaligned);
  646. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  647. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  648. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  649. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  650. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  651. buffer_vaddr;
  652. }
  653. hal_srng_access_end(soc->hal_soc, wbm_srng);
  654. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  655. return retval;
  656. fail:
  657. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  658. return retval;
  659. }
  660. /**
  661. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  662. * @soc: data path instance
  663. * @pdev: core txrx pdev context
  664. *
  665. * This function will attach a DP RX instance into the main
  666. * device (SOC) context.
  667. *
  668. * Return: QDF_STATUS_SUCCESS: success
  669. * QDF_STATUS_E_RESOURCES: Error return
  670. */
  671. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  672. {
  673. return QDF_STATUS_SUCCESS;
  674. }
  675. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  676. {
  677. int error;
  678. /* TX resource attach */
  679. error = dp_tx_ipa_uc_attach(soc, pdev);
  680. if (error) {
  681. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  682. "DP IPA UC TX attach fail code %d\n", error);
  683. return error;
  684. }
  685. /* RX resource attach */
  686. error = dp_rx_ipa_uc_attach(soc, pdev);
  687. if (error) {
  688. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  689. "DP IPA UC RX attach fail code %d\n", error);
  690. dp_tx_ipa_uc_detach(soc, pdev);
  691. return error;
  692. }
  693. return QDF_STATUS_SUCCESS; /* success */
  694. }
  695. #else
  696. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  697. {
  698. return QDF_STATUS_SUCCESS;
  699. }
  700. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  701. {
  702. return QDF_STATUS_SUCCESS;
  703. }
  704. #endif
  705. /* TODO: Need this interface from HIF */
  706. void *hif_get_hal_handle(void *hif_handle);
  707. /*
  708. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  709. * @dp_ctx: DP SOC handle
  710. * @budget: Number of frames/descriptors that can be processed in one shot
  711. *
  712. * Return: remaining budget/quota for the soc device
  713. */
  714. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  715. {
  716. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  717. struct dp_soc *soc = int_ctx->soc;
  718. int ring = 0;
  719. uint32_t work_done = 0;
  720. int budget = dp_budget;
  721. uint8_t tx_mask = int_ctx->tx_ring_mask;
  722. uint8_t rx_mask = int_ctx->rx_ring_mask;
  723. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  724. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  725. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  726. uint32_t remaining_quota = dp_budget;
  727. /* Process Tx completion interrupts first to return back buffers */
  728. while (tx_mask) {
  729. if (tx_mask & 0x1) {
  730. work_done = dp_tx_comp_handler(soc,
  731. soc->tx_comp_ring[ring].hal_srng,
  732. remaining_quota);
  733. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  734. "tx mask 0x%x ring %d, budget %d, work_done %d",
  735. tx_mask, ring, budget, work_done);
  736. budget -= work_done;
  737. if (budget <= 0)
  738. goto budget_done;
  739. remaining_quota = budget;
  740. }
  741. tx_mask = tx_mask >> 1;
  742. ring++;
  743. }
  744. /* Process REO Exception ring interrupt */
  745. if (rx_err_mask) {
  746. work_done = dp_rx_err_process(soc,
  747. soc->reo_exception_ring.hal_srng,
  748. remaining_quota);
  749. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  750. "REO Exception Ring: work_done %d budget %d",
  751. work_done, budget);
  752. budget -= work_done;
  753. if (budget <= 0) {
  754. goto budget_done;
  755. }
  756. remaining_quota = budget;
  757. }
  758. /* Process Rx WBM release ring interrupt */
  759. if (rx_wbm_rel_mask) {
  760. work_done = dp_rx_wbm_err_process(soc,
  761. soc->rx_rel_ring.hal_srng, remaining_quota);
  762. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  763. "WBM Release Ring: work_done %d budget %d",
  764. work_done, budget);
  765. budget -= work_done;
  766. if (budget <= 0) {
  767. goto budget_done;
  768. }
  769. remaining_quota = budget;
  770. }
  771. /* Process Rx interrupts */
  772. if (rx_mask) {
  773. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  774. if (rx_mask & (1 << ring)) {
  775. work_done = dp_rx_process(int_ctx,
  776. soc->reo_dest_ring[ring].hal_srng,
  777. remaining_quota);
  778. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  779. "rx mask 0x%x ring %d, work_done %d budget %d",
  780. rx_mask, ring, work_done, budget);
  781. budget -= work_done;
  782. if (budget <= 0)
  783. goto budget_done;
  784. remaining_quota = budget;
  785. }
  786. }
  787. }
  788. if (reo_status_mask)
  789. dp_reo_status_ring_handler(soc);
  790. /* Process LMAC interrupts */
  791. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  792. if (soc->pdev_list[ring] == NULL)
  793. continue;
  794. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  795. work_done = dp_mon_process(soc, ring, remaining_quota);
  796. budget -= work_done;
  797. remaining_quota = budget;
  798. }
  799. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  800. work_done = dp_rxdma_err_process(soc, ring,
  801. remaining_quota);
  802. budget -= work_done;
  803. }
  804. }
  805. qdf_lro_flush(int_ctx->lro_ctx);
  806. budget_done:
  807. return dp_budget - budget;
  808. }
  809. #ifdef DP_INTR_POLL_BASED
  810. /* dp_interrupt_timer()- timer poll for interrupts
  811. *
  812. * @arg: SoC Handle
  813. *
  814. * Return:
  815. *
  816. */
  817. static void dp_interrupt_timer(void *arg)
  818. {
  819. struct dp_soc *soc = (struct dp_soc *) arg;
  820. int i;
  821. if (qdf_atomic_read(&soc->cmn_init_done)) {
  822. for (i = 0;
  823. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  824. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  825. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  826. }
  827. }
  828. /*
  829. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  830. * @txrx_soc: DP SOC handle
  831. *
  832. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  833. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  834. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  835. *
  836. * Return: 0 for success. nonzero for failure.
  837. */
  838. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  839. {
  840. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  841. int i;
  842. soc->intr_mode = DP_INTR_POLL;
  843. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  844. soc->intr_ctx[i].dp_intr_id = i;
  845. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  846. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  847. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  848. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  849. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  850. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  851. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  852. soc->intr_ctx[i].soc = soc;
  853. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  854. }
  855. qdf_timer_init(soc->osdev, &soc->int_timer,
  856. dp_interrupt_timer, (void *)soc,
  857. QDF_TIMER_TYPE_WAKE_APPS);
  858. return QDF_STATUS_SUCCESS;
  859. }
  860. #ifdef CONFIG_MCL
  861. extern int con_mode_monitor;
  862. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  863. /*
  864. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  865. * @txrx_soc: DP SOC handle
  866. *
  867. * Call the appropriate attach function based on the mode of operation.
  868. * This is a WAR for enabling monitor mode.
  869. *
  870. * Return: 0 for success. nonzero for failure.
  871. */
  872. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  873. {
  874. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  875. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  876. FL("Attach interrupts in Poll mode"));
  877. return dp_soc_interrupt_attach_poll(txrx_soc);
  878. } else {
  879. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  880. FL("Attach interrupts in MSI mode"));
  881. return dp_soc_interrupt_attach(txrx_soc);
  882. }
  883. }
  884. #else
  885. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  886. {
  887. return dp_soc_interrupt_attach_poll(txrx_soc);
  888. }
  889. #endif
  890. #endif
  891. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  892. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  893. {
  894. int j;
  895. int num_irq = 0;
  896. int tx_mask =
  897. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  898. int rx_mask =
  899. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  900. int rx_mon_mask =
  901. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  902. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  903. soc->wlan_cfg_ctx, intr_ctx_num);
  904. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  905. soc->wlan_cfg_ctx, intr_ctx_num);
  906. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  907. soc->wlan_cfg_ctx, intr_ctx_num);
  908. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  909. soc->wlan_cfg_ctx, intr_ctx_num);
  910. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  911. if (tx_mask & (1 << j)) {
  912. irq_id_map[num_irq++] =
  913. (wbm2host_tx_completions_ring1 - j);
  914. }
  915. if (rx_mask & (1 << j)) {
  916. irq_id_map[num_irq++] =
  917. (reo2host_destination_ring1 - j);
  918. }
  919. if (rxdma2host_ring_mask & (1 << j)) {
  920. irq_id_map[num_irq++] =
  921. rxdma2host_destination_ring_mac1 -
  922. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  923. }
  924. if (rx_mon_mask & (1 << j)) {
  925. irq_id_map[num_irq++] =
  926. ppdu_end_interrupts_mac1 -
  927. wlan_cfg_get_hw_mac_idx(soc->wlan_cfg_ctx, j);
  928. }
  929. if (rx_wbm_rel_ring_mask & (1 << j))
  930. irq_id_map[num_irq++] = wbm2host_rx_release;
  931. if (rx_err_ring_mask & (1 << j))
  932. irq_id_map[num_irq++] = reo2host_exception;
  933. if (reo_status_ring_mask & (1 << j))
  934. irq_id_map[num_irq++] = reo2host_status;
  935. }
  936. *num_irq_r = num_irq;
  937. }
  938. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  939. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  940. int msi_vector_count, int msi_vector_start)
  941. {
  942. int tx_mask = wlan_cfg_get_tx_ring_mask(
  943. soc->wlan_cfg_ctx, intr_ctx_num);
  944. int rx_mask = wlan_cfg_get_rx_ring_mask(
  945. soc->wlan_cfg_ctx, intr_ctx_num);
  946. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  947. soc->wlan_cfg_ctx, intr_ctx_num);
  948. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  949. soc->wlan_cfg_ctx, intr_ctx_num);
  950. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  951. soc->wlan_cfg_ctx, intr_ctx_num);
  952. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  953. soc->wlan_cfg_ctx, intr_ctx_num);
  954. int rxdma2host_ring_mask = wlan_cfg_get_rxdma2host_ring_mask(
  955. soc->wlan_cfg_ctx, intr_ctx_num);
  956. unsigned int vector =
  957. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  958. int num_irq = 0;
  959. soc->intr_mode = DP_INTR_MSI;
  960. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  961. rx_wbm_rel_ring_mask | reo_status_ring_mask | rxdma2host_ring_mask)
  962. irq_id_map[num_irq++] =
  963. pld_get_msi_irq(soc->osdev->dev, vector);
  964. *num_irq_r = num_irq;
  965. }
  966. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  967. int *irq_id_map, int *num_irq)
  968. {
  969. int msi_vector_count, ret;
  970. uint32_t msi_base_data, msi_vector_start;
  971. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  972. &msi_vector_count,
  973. &msi_base_data,
  974. &msi_vector_start);
  975. if (ret)
  976. return dp_soc_interrupt_map_calculate_integrated(soc,
  977. intr_ctx_num, irq_id_map, num_irq);
  978. else
  979. dp_soc_interrupt_map_calculate_msi(soc,
  980. intr_ctx_num, irq_id_map, num_irq,
  981. msi_vector_count, msi_vector_start);
  982. }
  983. /*
  984. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  985. * @txrx_soc: DP SOC handle
  986. *
  987. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  988. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  989. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  990. *
  991. * Return: 0 for success. nonzero for failure.
  992. */
  993. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  994. {
  995. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  996. int i = 0;
  997. int num_irq = 0;
  998. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  999. int ret = 0;
  1000. /* Map of IRQ ids registered with one interrupt context */
  1001. int irq_id_map[HIF_MAX_GRP_IRQ];
  1002. int tx_mask =
  1003. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  1004. int rx_mask =
  1005. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1006. int rx_mon_mask =
  1007. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1008. int rx_err_ring_mask =
  1009. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1010. int rx_wbm_rel_ring_mask =
  1011. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1012. int reo_status_ring_mask =
  1013. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1014. int rxdma2host_ring_mask =
  1015. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1016. soc->intr_ctx[i].dp_intr_id = i;
  1017. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1018. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1019. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1020. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1021. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1022. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1023. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1024. soc->intr_ctx[i].soc = soc;
  1025. num_irq = 0;
  1026. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1027. &num_irq);
  1028. ret = hif_register_ext_group(soc->hif_handle,
  1029. num_irq, irq_id_map, dp_service_srngs,
  1030. &soc->intr_ctx[i], "dp_intr",
  1031. HIF_EXEC_NAPI_TYPE, 2);
  1032. if (ret) {
  1033. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1034. FL("failed, ret = %d"), ret);
  1035. return QDF_STATUS_E_FAILURE;
  1036. }
  1037. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1038. }
  1039. hif_configure_ext_group_interrupts(soc->hif_handle);
  1040. return QDF_STATUS_SUCCESS;
  1041. }
  1042. /*
  1043. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1044. * @txrx_soc: DP SOC handle
  1045. *
  1046. * Return: void
  1047. */
  1048. static void dp_soc_interrupt_detach(void *txrx_soc)
  1049. {
  1050. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1051. int i;
  1052. if (soc->intr_mode == DP_INTR_POLL) {
  1053. qdf_timer_stop(&soc->int_timer);
  1054. qdf_timer_free(&soc->int_timer);
  1055. } else {
  1056. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1057. }
  1058. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1059. soc->intr_ctx[i].tx_ring_mask = 0;
  1060. soc->intr_ctx[i].rx_ring_mask = 0;
  1061. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1062. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1063. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1064. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1065. soc->intr_ctx[i].rxdma2host_ring_mask = 0;
  1066. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1067. }
  1068. }
  1069. #define AVG_MAX_MPDUS_PER_TID 128
  1070. #define AVG_TIDS_PER_CLIENT 2
  1071. #define AVG_FLOWS_PER_TID 2
  1072. #define AVG_MSDUS_PER_FLOW 128
  1073. #define AVG_MSDUS_PER_MPDU 4
  1074. /*
  1075. * Allocate and setup link descriptor pool that will be used by HW for
  1076. * various link and queue descriptors and managed by WBM
  1077. */
  1078. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1079. {
  1080. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1081. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1082. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1083. uint32_t num_mpdus_per_link_desc =
  1084. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1085. uint32_t num_msdus_per_link_desc =
  1086. hal_num_msdus_per_link_desc(soc->hal_soc);
  1087. uint32_t num_mpdu_links_per_queue_desc =
  1088. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1089. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1090. uint32_t total_link_descs, total_mem_size;
  1091. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1092. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1093. uint32_t num_link_desc_banks;
  1094. uint32_t last_bank_size = 0;
  1095. uint32_t entry_size, num_entries;
  1096. int i;
  1097. uint32_t desc_id = 0;
  1098. /* Only Tx queue descriptors are allocated from common link descriptor
  1099. * pool Rx queue descriptors are not included in this because (REO queue
  1100. * extension descriptors) they are expected to be allocated contiguously
  1101. * with REO queue descriptors
  1102. */
  1103. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1104. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1105. num_mpdu_queue_descs = num_mpdu_link_descs /
  1106. num_mpdu_links_per_queue_desc;
  1107. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1108. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1109. num_msdus_per_link_desc;
  1110. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1111. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1112. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1113. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1114. /* Round up to power of 2 */
  1115. total_link_descs = 1;
  1116. while (total_link_descs < num_entries)
  1117. total_link_descs <<= 1;
  1118. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1119. FL("total_link_descs: %u, link_desc_size: %d"),
  1120. total_link_descs, link_desc_size);
  1121. total_mem_size = total_link_descs * link_desc_size;
  1122. total_mem_size += link_desc_align;
  1123. if (total_mem_size <= max_alloc_size) {
  1124. num_link_desc_banks = 0;
  1125. last_bank_size = total_mem_size;
  1126. } else {
  1127. num_link_desc_banks = (total_mem_size) /
  1128. (max_alloc_size - link_desc_align);
  1129. last_bank_size = total_mem_size %
  1130. (max_alloc_size - link_desc_align);
  1131. }
  1132. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1133. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1134. total_mem_size, num_link_desc_banks);
  1135. for (i = 0; i < num_link_desc_banks; i++) {
  1136. soc->link_desc_banks[i].base_vaddr_unaligned =
  1137. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1138. max_alloc_size,
  1139. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1140. soc->link_desc_banks[i].size = max_alloc_size;
  1141. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1142. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1143. ((unsigned long)(
  1144. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1145. link_desc_align));
  1146. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1147. soc->link_desc_banks[i].base_paddr_unaligned) +
  1148. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1149. (unsigned long)(
  1150. soc->link_desc_banks[i].base_vaddr_unaligned));
  1151. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1152. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1153. FL("Link descriptor memory alloc failed"));
  1154. goto fail;
  1155. }
  1156. }
  1157. if (last_bank_size) {
  1158. /* Allocate last bank in case total memory required is not exact
  1159. * multiple of max_alloc_size
  1160. */
  1161. soc->link_desc_banks[i].base_vaddr_unaligned =
  1162. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1163. last_bank_size,
  1164. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1165. soc->link_desc_banks[i].size = last_bank_size;
  1166. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1167. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1168. ((unsigned long)(
  1169. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1170. link_desc_align));
  1171. soc->link_desc_banks[i].base_paddr =
  1172. (unsigned long)(
  1173. soc->link_desc_banks[i].base_paddr_unaligned) +
  1174. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1175. (unsigned long)(
  1176. soc->link_desc_banks[i].base_vaddr_unaligned));
  1177. }
  1178. /* Allocate and setup link descriptor idle list for HW internal use */
  1179. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1180. total_mem_size = entry_size * total_link_descs;
  1181. if (total_mem_size <= max_alloc_size) {
  1182. void *desc;
  1183. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1184. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1185. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1186. FL("Link desc idle ring setup failed"));
  1187. goto fail;
  1188. }
  1189. hal_srng_access_start_unlocked(soc->hal_soc,
  1190. soc->wbm_idle_link_ring.hal_srng);
  1191. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1192. soc->link_desc_banks[i].base_paddr; i++) {
  1193. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1194. ((unsigned long)(
  1195. soc->link_desc_banks[i].base_vaddr) -
  1196. (unsigned long)(
  1197. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1198. / link_desc_size;
  1199. unsigned long paddr = (unsigned long)(
  1200. soc->link_desc_banks[i].base_paddr);
  1201. while (num_entries && (desc = hal_srng_src_get_next(
  1202. soc->hal_soc,
  1203. soc->wbm_idle_link_ring.hal_srng))) {
  1204. hal_set_link_desc_addr(desc,
  1205. LINK_DESC_COOKIE(desc_id, i), paddr);
  1206. num_entries--;
  1207. desc_id++;
  1208. paddr += link_desc_size;
  1209. }
  1210. }
  1211. hal_srng_access_end_unlocked(soc->hal_soc,
  1212. soc->wbm_idle_link_ring.hal_srng);
  1213. } else {
  1214. uint32_t num_scatter_bufs;
  1215. uint32_t num_entries_per_buf;
  1216. uint32_t rem_entries;
  1217. uint8_t *scatter_buf_ptr;
  1218. uint16_t scatter_buf_num;
  1219. soc->wbm_idle_scatter_buf_size =
  1220. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1221. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1222. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1223. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1224. soc->hal_soc, total_mem_size,
  1225. soc->wbm_idle_scatter_buf_size);
  1226. for (i = 0; i < num_scatter_bufs; i++) {
  1227. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1228. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1229. soc->wbm_idle_scatter_buf_size,
  1230. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1231. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1232. QDF_TRACE(QDF_MODULE_ID_DP,
  1233. QDF_TRACE_LEVEL_ERROR,
  1234. FL("Scatter list memory alloc failed"));
  1235. goto fail;
  1236. }
  1237. }
  1238. /* Populate idle list scatter buffers with link descriptor
  1239. * pointers
  1240. */
  1241. scatter_buf_num = 0;
  1242. scatter_buf_ptr = (uint8_t *)(
  1243. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1244. rem_entries = num_entries_per_buf;
  1245. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1246. soc->link_desc_banks[i].base_paddr; i++) {
  1247. uint32_t num_link_descs =
  1248. (soc->link_desc_banks[i].size -
  1249. ((unsigned long)(
  1250. soc->link_desc_banks[i].base_vaddr) -
  1251. (unsigned long)(
  1252. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1253. / link_desc_size;
  1254. unsigned long paddr = (unsigned long)(
  1255. soc->link_desc_banks[i].base_paddr);
  1256. while (num_link_descs) {
  1257. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1258. LINK_DESC_COOKIE(desc_id, i), paddr);
  1259. num_link_descs--;
  1260. desc_id++;
  1261. paddr += link_desc_size;
  1262. rem_entries--;
  1263. if (rem_entries) {
  1264. scatter_buf_ptr += entry_size;
  1265. } else {
  1266. rem_entries = num_entries_per_buf;
  1267. scatter_buf_num++;
  1268. if (scatter_buf_num >= num_scatter_bufs)
  1269. break;
  1270. scatter_buf_ptr = (uint8_t *)(
  1271. soc->wbm_idle_scatter_buf_base_vaddr[
  1272. scatter_buf_num]);
  1273. }
  1274. }
  1275. }
  1276. /* Setup link descriptor idle list in HW */
  1277. hal_setup_link_idle_list(soc->hal_soc,
  1278. soc->wbm_idle_scatter_buf_base_paddr,
  1279. soc->wbm_idle_scatter_buf_base_vaddr,
  1280. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1281. (uint32_t)(scatter_buf_ptr -
  1282. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1283. scatter_buf_num-1])), total_link_descs);
  1284. }
  1285. return 0;
  1286. fail:
  1287. if (soc->wbm_idle_link_ring.hal_srng) {
  1288. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1289. WBM_IDLE_LINK, 0);
  1290. }
  1291. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1292. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1293. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1294. soc->wbm_idle_scatter_buf_size,
  1295. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1296. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1297. }
  1298. }
  1299. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1300. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1301. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1302. soc->link_desc_banks[i].size,
  1303. soc->link_desc_banks[i].base_vaddr_unaligned,
  1304. soc->link_desc_banks[i].base_paddr_unaligned,
  1305. 0);
  1306. }
  1307. }
  1308. return QDF_STATUS_E_FAILURE;
  1309. }
  1310. /*
  1311. * Free link descriptor pool that was setup HW
  1312. */
  1313. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1314. {
  1315. int i;
  1316. if (soc->wbm_idle_link_ring.hal_srng) {
  1317. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1318. WBM_IDLE_LINK, 0);
  1319. }
  1320. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1321. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1322. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1323. soc->wbm_idle_scatter_buf_size,
  1324. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1325. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1326. }
  1327. }
  1328. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1329. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1330. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1331. soc->link_desc_banks[i].size,
  1332. soc->link_desc_banks[i].base_vaddr_unaligned,
  1333. soc->link_desc_banks[i].base_paddr_unaligned,
  1334. 0);
  1335. }
  1336. }
  1337. }
  1338. /* TODO: Following should be configurable */
  1339. #define WBM_RELEASE_RING_SIZE 64
  1340. #define TCL_CMD_RING_SIZE 32
  1341. #define TCL_STATUS_RING_SIZE 32
  1342. #if defined(QCA_WIFI_QCA6290)
  1343. #define REO_DST_RING_SIZE 1024
  1344. #else
  1345. #define REO_DST_RING_SIZE 2048
  1346. #endif
  1347. #define REO_REINJECT_RING_SIZE 32
  1348. #define RX_RELEASE_RING_SIZE 1024
  1349. #define REO_EXCEPTION_RING_SIZE 128
  1350. #define REO_CMD_RING_SIZE 32
  1351. #define REO_STATUS_RING_SIZE 32
  1352. #define RXDMA_BUF_RING_SIZE 1024
  1353. #define RXDMA_REFILL_RING_SIZE 2048
  1354. #define RXDMA_MONITOR_BUF_RING_SIZE 4096
  1355. #define RXDMA_MONITOR_DST_RING_SIZE 2048
  1356. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1357. #define RXDMA_MONITOR_DESC_RING_SIZE 2048
  1358. #define RXDMA_ERR_DST_RING_SIZE 1024
  1359. /*
  1360. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1361. * @soc: Datapath SOC handle
  1362. *
  1363. * This is a timer function used to age out stale WDS nodes from
  1364. * AST table
  1365. */
  1366. #ifdef FEATURE_WDS
  1367. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1368. {
  1369. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1370. struct dp_pdev *pdev;
  1371. struct dp_vdev *vdev;
  1372. struct dp_peer *peer;
  1373. struct dp_ast_entry *ase, *temp_ase;
  1374. int i;
  1375. qdf_spin_lock_bh(&soc->ast_lock);
  1376. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1377. pdev = soc->pdev_list[i];
  1378. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1379. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1380. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1381. /*
  1382. * Do not expire static ast entries
  1383. */
  1384. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1385. continue;
  1386. if (ase->is_active) {
  1387. ase->is_active = FALSE;
  1388. continue;
  1389. }
  1390. DP_STATS_INC(soc, ast.aged_out, 1);
  1391. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1392. pdev->osif_pdev,
  1393. ase->mac_addr.raw);
  1394. dp_peer_del_ast(soc, ase);
  1395. }
  1396. }
  1397. }
  1398. }
  1399. qdf_spin_unlock_bh(&soc->ast_lock);
  1400. if (qdf_atomic_read(&soc->cmn_init_done))
  1401. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1402. }
  1403. /*
  1404. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1405. * @soc: Datapath SOC handle
  1406. *
  1407. * Return: None
  1408. */
  1409. static void dp_soc_wds_attach(struct dp_soc *soc)
  1410. {
  1411. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1412. dp_wds_aging_timer_fn, (void *)soc,
  1413. QDF_TIMER_TYPE_WAKE_APPS);
  1414. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1415. }
  1416. /*
  1417. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1418. * @txrx_soc: DP SOC handle
  1419. *
  1420. * Return: None
  1421. */
  1422. static void dp_soc_wds_detach(struct dp_soc *soc)
  1423. {
  1424. qdf_timer_stop(&soc->wds_aging_timer);
  1425. qdf_timer_free(&soc->wds_aging_timer);
  1426. }
  1427. #else
  1428. static void dp_soc_wds_attach(struct dp_soc *soc)
  1429. {
  1430. }
  1431. static void dp_soc_wds_detach(struct dp_soc *soc)
  1432. {
  1433. }
  1434. #endif
  1435. /*
  1436. * dp_soc_reset_ring_map() - Reset cpu ring map
  1437. * @soc: Datapath soc handler
  1438. *
  1439. * This api resets the default cpu ring map
  1440. */
  1441. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1442. {
  1443. uint8_t i;
  1444. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1445. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1446. if (nss_config == 1) {
  1447. /*
  1448. * Setting Tx ring map for one nss offloaded radio
  1449. */
  1450. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1451. } else if (nss_config == 2) {
  1452. /*
  1453. * Setting Tx ring for two nss offloaded radios
  1454. */
  1455. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1456. } else {
  1457. /*
  1458. * Setting Tx ring map for all nss offloaded radios
  1459. */
  1460. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1461. }
  1462. }
  1463. }
  1464. #ifdef IPA_OFFLOAD
  1465. /**
  1466. * dp_reo_remap_config() - configure reo remap register value based
  1467. * nss configuration.
  1468. * based on offload_radio value below remap configuration
  1469. * get applied.
  1470. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1471. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1472. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1473. * 3 - both Radios handled by NSS (remap not required)
  1474. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1475. *
  1476. * @remap1: output parameter indicates reo remap 1 register value
  1477. * @remap2: output parameter indicates reo remap 2 register value
  1478. * Return: bool type, true if remap is configured else false.
  1479. */
  1480. static bool dp_reo_remap_config(struct dp_soc *soc,
  1481. uint32_t *remap1,
  1482. uint32_t *remap2)
  1483. {
  1484. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1485. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1486. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1487. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1488. return true;
  1489. }
  1490. #else
  1491. static bool dp_reo_remap_config(struct dp_soc *soc,
  1492. uint32_t *remap1,
  1493. uint32_t *remap2)
  1494. {
  1495. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1496. switch (offload_radio) {
  1497. case 0:
  1498. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1499. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1500. (0x3 << 18) | (0x4 << 21)) << 8;
  1501. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1502. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1503. (0x3 << 18) | (0x4 << 21)) << 8;
  1504. break;
  1505. case 1:
  1506. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1507. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1508. (0x2 << 18) | (0x3 << 21)) << 8;
  1509. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1510. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1511. (0x4 << 18) | (0x2 << 21)) << 8;
  1512. break;
  1513. case 2:
  1514. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1515. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1516. (0x1 << 18) | (0x3 << 21)) << 8;
  1517. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1518. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1519. (0x4 << 18) | (0x1 << 21)) << 8;
  1520. break;
  1521. case 3:
  1522. /* return false if both radios are offloaded to NSS */
  1523. return false;
  1524. }
  1525. return true;
  1526. }
  1527. #endif
  1528. /*
  1529. * dp_soc_cmn_setup() - Common SoC level initializion
  1530. * @soc: Datapath SOC handle
  1531. *
  1532. * This is an internal function used to setup common SOC data structures,
  1533. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1534. */
  1535. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1536. {
  1537. int i;
  1538. struct hal_reo_params reo_params;
  1539. int tx_ring_size;
  1540. int tx_comp_ring_size;
  1541. if (qdf_atomic_read(&soc->cmn_init_done))
  1542. return 0;
  1543. if (dp_peer_find_attach(soc))
  1544. goto fail0;
  1545. if (dp_hw_link_desc_pool_setup(soc))
  1546. goto fail1;
  1547. /* Setup SRNG rings */
  1548. /* Common rings */
  1549. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1550. WBM_RELEASE_RING_SIZE)) {
  1551. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1552. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1553. goto fail1;
  1554. }
  1555. soc->num_tcl_data_rings = 0;
  1556. /* Tx data rings */
  1557. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1558. soc->num_tcl_data_rings =
  1559. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1560. tx_comp_ring_size =
  1561. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1562. tx_ring_size =
  1563. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1564. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1565. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1566. TCL_DATA, i, 0, tx_ring_size)) {
  1567. QDF_TRACE(QDF_MODULE_ID_DP,
  1568. QDF_TRACE_LEVEL_ERROR,
  1569. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1570. goto fail1;
  1571. }
  1572. /*
  1573. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1574. * count
  1575. */
  1576. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1577. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1578. QDF_TRACE(QDF_MODULE_ID_DP,
  1579. QDF_TRACE_LEVEL_ERROR,
  1580. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1581. goto fail1;
  1582. }
  1583. }
  1584. } else {
  1585. /* This will be incremented during per pdev ring setup */
  1586. soc->num_tcl_data_rings = 0;
  1587. }
  1588. if (dp_tx_soc_attach(soc)) {
  1589. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1590. FL("dp_tx_soc_attach failed"));
  1591. goto fail1;
  1592. }
  1593. /* TCL command and status rings */
  1594. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1595. TCL_CMD_RING_SIZE)) {
  1596. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1597. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1598. goto fail1;
  1599. }
  1600. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1601. TCL_STATUS_RING_SIZE)) {
  1602. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1603. FL("dp_srng_setup failed for tcl_status_ring"));
  1604. goto fail1;
  1605. }
  1606. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1607. * descriptors
  1608. */
  1609. /* Rx data rings */
  1610. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1611. soc->num_reo_dest_rings =
  1612. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1613. QDF_TRACE(QDF_MODULE_ID_DP,
  1614. QDF_TRACE_LEVEL_ERROR,
  1615. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1616. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1617. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1618. i, 0, REO_DST_RING_SIZE)) {
  1619. QDF_TRACE(QDF_MODULE_ID_DP,
  1620. QDF_TRACE_LEVEL_ERROR,
  1621. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1622. goto fail1;
  1623. }
  1624. }
  1625. } else {
  1626. /* This will be incremented during per pdev ring setup */
  1627. soc->num_reo_dest_rings = 0;
  1628. }
  1629. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1630. /* REO reinjection ring */
  1631. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1632. REO_REINJECT_RING_SIZE)) {
  1633. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1634. FL("dp_srng_setup failed for reo_reinject_ring"));
  1635. goto fail1;
  1636. }
  1637. /* Rx release ring */
  1638. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1639. RX_RELEASE_RING_SIZE)) {
  1640. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1641. FL("dp_srng_setup failed for rx_rel_ring"));
  1642. goto fail1;
  1643. }
  1644. /* Rx exception ring */
  1645. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1646. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1647. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1648. FL("dp_srng_setup failed for reo_exception_ring"));
  1649. goto fail1;
  1650. }
  1651. /* REO command and status rings */
  1652. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1653. REO_CMD_RING_SIZE)) {
  1654. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1655. FL("dp_srng_setup failed for reo_cmd_ring"));
  1656. goto fail1;
  1657. }
  1658. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1659. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1660. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1661. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1662. REO_STATUS_RING_SIZE)) {
  1663. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1664. FL("dp_srng_setup failed for reo_status_ring"));
  1665. goto fail1;
  1666. }
  1667. qdf_spinlock_create(&soc->ast_lock);
  1668. dp_soc_wds_attach(soc);
  1669. /* Reset the cpu ring map if radio is NSS offloaded */
  1670. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1671. dp_soc_reset_cpu_ring_map(soc);
  1672. }
  1673. /* Setup HW REO */
  1674. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1675. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1676. /*
  1677. * Reo ring remap is not required if both radios
  1678. * are offloaded to NSS
  1679. */
  1680. if (!dp_reo_remap_config(soc,
  1681. &reo_params.remap1,
  1682. &reo_params.remap2))
  1683. goto out;
  1684. reo_params.rx_hash_enabled = true;
  1685. }
  1686. out:
  1687. hal_reo_setup(soc->hal_soc, &reo_params);
  1688. qdf_atomic_set(&soc->cmn_init_done, 1);
  1689. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1690. return 0;
  1691. fail1:
  1692. /*
  1693. * Cleanup will be done as part of soc_detach, which will
  1694. * be called on pdev attach failure
  1695. */
  1696. fail0:
  1697. return QDF_STATUS_E_FAILURE;
  1698. }
  1699. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1700. static void dp_lro_hash_setup(struct dp_soc *soc)
  1701. {
  1702. struct cdp_lro_hash_config lro_hash;
  1703. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1704. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1705. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1706. FL("LRO disabled RX hash disabled"));
  1707. return;
  1708. }
  1709. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1710. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1711. lro_hash.lro_enable = 1;
  1712. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1713. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1714. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1715. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1716. }
  1717. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1718. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1719. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1720. LRO_IPV4_SEED_ARR_SZ));
  1721. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1722. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1723. LRO_IPV6_SEED_ARR_SZ));
  1724. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1725. "lro_hash: lro_enable: 0x%x"
  1726. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1727. lro_hash.lro_enable, lro_hash.tcp_flag,
  1728. lro_hash.tcp_flag_mask);
  1729. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1730. FL("lro_hash: toeplitz_hash_ipv4:"));
  1731. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1732. QDF_TRACE_LEVEL_ERROR,
  1733. (void *)lro_hash.toeplitz_hash_ipv4,
  1734. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1735. LRO_IPV4_SEED_ARR_SZ));
  1736. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1737. FL("lro_hash: toeplitz_hash_ipv6:"));
  1738. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1739. QDF_TRACE_LEVEL_ERROR,
  1740. (void *)lro_hash.toeplitz_hash_ipv6,
  1741. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1742. LRO_IPV6_SEED_ARR_SZ));
  1743. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1744. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1745. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1746. (soc->osif_soc, &lro_hash);
  1747. }
  1748. /*
  1749. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1750. * @soc: data path SoC handle
  1751. * @pdev: Physical device handle
  1752. *
  1753. * Return: 0 - success, > 0 - failure
  1754. */
  1755. #ifdef QCA_HOST2FW_RXBUF_RING
  1756. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1757. struct dp_pdev *pdev)
  1758. {
  1759. int max_mac_rings =
  1760. wlan_cfg_get_num_mac_rings
  1761. (pdev->wlan_cfg_ctx);
  1762. int i;
  1763. for (i = 0; i < max_mac_rings; i++) {
  1764. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1765. "%s: pdev_id %d mac_id %d\n",
  1766. __func__, pdev->pdev_id, i);
  1767. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1768. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1769. QDF_TRACE(QDF_MODULE_ID_DP,
  1770. QDF_TRACE_LEVEL_ERROR,
  1771. FL("failed rx mac ring setup"));
  1772. return QDF_STATUS_E_FAILURE;
  1773. }
  1774. }
  1775. return QDF_STATUS_SUCCESS;
  1776. }
  1777. #else
  1778. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1779. struct dp_pdev *pdev)
  1780. {
  1781. return QDF_STATUS_SUCCESS;
  1782. }
  1783. #endif
  1784. /**
  1785. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1786. * @pdev - DP_PDEV handle
  1787. *
  1788. * Return: void
  1789. */
  1790. static inline void
  1791. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1792. {
  1793. uint8_t map_id;
  1794. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1795. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1796. sizeof(default_dscp_tid_map));
  1797. }
  1798. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1799. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1800. pdev->dscp_tid_map[map_id],
  1801. map_id);
  1802. }
  1803. }
  1804. /*
  1805. * dp_reset_intr_mask() - reset interrupt mask
  1806. * @dp_soc - DP Soc handle
  1807. * @dp_pdev - DP pdev handle
  1808. *
  1809. * Return: Return void
  1810. */
  1811. static inline
  1812. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1813. {
  1814. /*
  1815. * We will set the interrupt mask to zero for NSS offloaded radio
  1816. */
  1817. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1818. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1819. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1820. }
  1821. /*
  1822. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1823. * @soc: data path SoC handle
  1824. *
  1825. * Return: none
  1826. */
  1827. #ifdef IPA_OFFLOAD
  1828. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1829. struct dp_pdev *pdev)
  1830. {
  1831. void *hal_srng;
  1832. struct hal_srng_params srng_params;
  1833. qdf_dma_addr_t hp_addr, tp_addr;
  1834. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1835. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1836. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1837. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1838. srng_params.ring_base_paddr;
  1839. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1840. srng_params.ring_base_vaddr;
  1841. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1842. srng_params.num_entries * srng_params.entry_size;
  1843. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1844. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1845. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1846. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1847. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1848. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1849. srng_params.ring_base_paddr;
  1850. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1851. srng_params.ring_base_vaddr;
  1852. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1853. srng_params.num_entries * srng_params.entry_size;
  1854. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1855. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1856. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1857. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1858. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1859. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1860. srng_params.ring_base_paddr;
  1861. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1862. srng_params.ring_base_vaddr;
  1863. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1864. srng_params.num_entries * srng_params.entry_size;
  1865. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1866. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1867. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1868. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1869. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1870. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1871. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1872. __func__);
  1873. return -EFAULT;
  1874. }
  1875. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1876. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1877. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1878. srng_params.ring_base_paddr;
  1879. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1880. srng_params.ring_base_vaddr;
  1881. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1882. srng_params.num_entries * srng_params.entry_size;
  1883. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1884. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1885. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1886. "%s: ring_base_paddr:%pK, ring_base_vaddr:%pK"
  1887. "_entries:%d, hp_addr:%pK\n",
  1888. __func__,
  1889. (void *)srng_params.ring_base_paddr,
  1890. (void *)srng_params.ring_base_vaddr,
  1891. srng_params.num_entries,
  1892. (void *)hp_addr);
  1893. return 0;
  1894. }
  1895. #else
  1896. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1897. struct dp_pdev *pdev)
  1898. {
  1899. return 0;
  1900. }
  1901. #endif
  1902. /*
  1903. * dp_pdev_attach_wifi3() - attach txrx pdev
  1904. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1905. * @txrx_soc: Datapath SOC handle
  1906. * @htc_handle: HTC handle for host-target interface
  1907. * @qdf_osdev: QDF OS device
  1908. * @pdev_id: PDEV ID
  1909. *
  1910. * Return: DP PDEV handle on success, NULL on failure
  1911. */
  1912. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1913. struct cdp_cfg *ctrl_pdev,
  1914. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1915. {
  1916. int tx_ring_size;
  1917. int tx_comp_ring_size;
  1918. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1919. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1920. if (!pdev) {
  1921. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1922. FL("DP PDEV memory allocation failed"));
  1923. goto fail0;
  1924. }
  1925. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1926. if (!pdev->wlan_cfg_ctx) {
  1927. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1928. FL("pdev cfg_attach failed"));
  1929. qdf_mem_free(pdev);
  1930. goto fail0;
  1931. }
  1932. /*
  1933. * set nss pdev config based on soc config
  1934. */
  1935. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1936. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1937. pdev->soc = soc;
  1938. pdev->osif_pdev = ctrl_pdev;
  1939. pdev->pdev_id = pdev_id;
  1940. soc->pdev_list[pdev_id] = pdev;
  1941. soc->pdev_count++;
  1942. TAILQ_INIT(&pdev->vdev_list);
  1943. pdev->vdev_count = 0;
  1944. qdf_spinlock_create(&pdev->tx_mutex);
  1945. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1946. TAILQ_INIT(&pdev->neighbour_peers_list);
  1947. if (dp_soc_cmn_setup(soc)) {
  1948. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1949. FL("dp_soc_cmn_setup failed"));
  1950. goto fail1;
  1951. }
  1952. /* Setup per PDEV TCL rings if configured */
  1953. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1954. tx_ring_size =
  1955. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1956. tx_comp_ring_size =
  1957. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1958. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1959. pdev_id, pdev_id, tx_ring_size)) {
  1960. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1961. FL("dp_srng_setup failed for tcl_data_ring"));
  1962. goto fail1;
  1963. }
  1964. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1965. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1966. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1967. FL("dp_srng_setup failed for tx_comp_ring"));
  1968. goto fail1;
  1969. }
  1970. soc->num_tcl_data_rings++;
  1971. }
  1972. /* Tx specific init */
  1973. if (dp_tx_pdev_attach(pdev)) {
  1974. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1975. FL("dp_tx_pdev_attach failed"));
  1976. goto fail1;
  1977. }
  1978. /* Setup per PDEV REO rings if configured */
  1979. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1980. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1981. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1982. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1983. FL("dp_srng_setup failed for reo_dest_ringn"));
  1984. goto fail1;
  1985. }
  1986. soc->num_reo_dest_rings++;
  1987. }
  1988. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1989. RXDMA_REFILL_RING_SIZE)) {
  1990. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1991. FL("dp_srng_setup failed rx refill ring"));
  1992. goto fail1;
  1993. }
  1994. if (dp_rxdma_ring_setup(soc, pdev)) {
  1995. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1996. FL("RXDMA ring config failed"));
  1997. goto fail1;
  1998. }
  1999. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  2000. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  2001. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2002. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  2003. goto fail1;
  2004. }
  2005. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  2006. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  2007. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2008. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2009. goto fail1;
  2010. }
  2011. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  2012. RXDMA_MONITOR_STATUS, 0, pdev_id,
  2013. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2014. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2015. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2016. goto fail1;
  2017. }
  2018. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2019. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2020. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2021. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2022. goto fail1;
  2023. }
  2024. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2025. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2026. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2027. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2028. goto fail1;
  2029. }
  2030. if (dp_ipa_ring_resource_setup(soc, pdev))
  2031. goto fail1;
  2032. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2033. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2034. "%s: dp_ipa_uc_attach failed\n", __func__);
  2035. goto fail1;
  2036. }
  2037. /* Rx specific init */
  2038. if (dp_rx_pdev_attach(pdev)) {
  2039. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2040. FL("dp_rx_pdev_attach failed "));
  2041. goto fail0;
  2042. }
  2043. DP_STATS_INIT(pdev);
  2044. #ifndef CONFIG_WIN
  2045. /* MCL */
  2046. dp_local_peer_id_pool_init(pdev);
  2047. #endif
  2048. dp_dscp_tid_map_setup(pdev);
  2049. /* Rx monitor mode specific init */
  2050. if (dp_rx_pdev_mon_attach(pdev)) {
  2051. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2052. "dp_rx_pdev_attach failed\n");
  2053. goto fail1;
  2054. }
  2055. if (dp_wdi_event_attach(pdev)) {
  2056. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2057. "dp_wdi_evet_attach failed\n");
  2058. goto fail1;
  2059. }
  2060. /* set the reo destination during initialization */
  2061. pdev->reo_dest = pdev->pdev_id + 1;
  2062. /*
  2063. * reset the interrupt mask for offloaded radio
  2064. */
  2065. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  2066. dp_soc_reset_intr_mask(soc, pdev);
  2067. }
  2068. return (struct cdp_pdev *)pdev;
  2069. fail1:
  2070. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2071. fail0:
  2072. return NULL;
  2073. }
  2074. /*
  2075. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2076. * @soc: data path SoC handle
  2077. * @pdev: Physical device handle
  2078. *
  2079. * Return: void
  2080. */
  2081. #ifdef QCA_HOST2FW_RXBUF_RING
  2082. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2083. struct dp_pdev *pdev)
  2084. {
  2085. int max_mac_rings =
  2086. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2087. int i;
  2088. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2089. max_mac_rings : MAX_RX_MAC_RINGS;
  2090. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2091. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2092. RXDMA_BUF, 1);
  2093. }
  2094. #else
  2095. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2096. struct dp_pdev *pdev)
  2097. {
  2098. }
  2099. #endif
  2100. /*
  2101. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2102. * @pdev: device object
  2103. *
  2104. * Return: void
  2105. */
  2106. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2107. {
  2108. struct dp_neighbour_peer *peer = NULL;
  2109. struct dp_neighbour_peer *temp_peer = NULL;
  2110. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2111. neighbour_peer_list_elem, temp_peer) {
  2112. /* delete this peer from the list */
  2113. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2114. peer, neighbour_peer_list_elem);
  2115. qdf_mem_free(peer);
  2116. }
  2117. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2118. }
  2119. /*
  2120. * dp_pdev_detach_wifi3() - detach txrx pdev
  2121. * @txrx_pdev: Datapath PDEV handle
  2122. * @force: Force detach
  2123. *
  2124. */
  2125. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2126. {
  2127. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2128. struct dp_soc *soc = pdev->soc;
  2129. dp_wdi_event_detach(pdev);
  2130. dp_tx_pdev_detach(pdev);
  2131. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2132. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2133. TCL_DATA, pdev->pdev_id);
  2134. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2135. WBM2SW_RELEASE, pdev->pdev_id);
  2136. }
  2137. dp_rx_pdev_detach(pdev);
  2138. dp_rx_pdev_mon_detach(pdev);
  2139. dp_neighbour_peers_detach(pdev);
  2140. qdf_spinlock_destroy(&pdev->tx_mutex);
  2141. dp_ipa_uc_detach(soc, pdev);
  2142. /* Cleanup per PDEV REO rings if configured */
  2143. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2144. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2145. REO_DST, pdev->pdev_id);
  2146. }
  2147. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2148. dp_rxdma_ring_cleanup(soc, pdev);
  2149. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2150. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2151. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2152. RXDMA_MONITOR_STATUS, 0);
  2153. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2154. RXDMA_MONITOR_DESC, 0);
  2155. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2156. soc->pdev_list[pdev->pdev_id] = NULL;
  2157. soc->pdev_count--;
  2158. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2159. qdf_mem_free(pdev);
  2160. }
  2161. /*
  2162. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2163. * @soc: DP SOC handle
  2164. */
  2165. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2166. {
  2167. struct reo_desc_list_node *desc;
  2168. struct dp_rx_tid *rx_tid;
  2169. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2170. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2171. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2172. rx_tid = &desc->rx_tid;
  2173. qdf_mem_unmap_nbytes_single(soc->osdev,
  2174. rx_tid->hw_qdesc_paddr,
  2175. QDF_DMA_BIDIRECTIONAL,
  2176. rx_tid->hw_qdesc_alloc_size);
  2177. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2178. qdf_mem_free(desc);
  2179. }
  2180. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2181. qdf_list_destroy(&soc->reo_desc_freelist);
  2182. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2183. }
  2184. /*
  2185. * dp_soc_detach_wifi3() - Detach txrx SOC
  2186. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2187. */
  2188. static void dp_soc_detach_wifi3(void *txrx_soc)
  2189. {
  2190. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2191. int i;
  2192. qdf_atomic_set(&soc->cmn_init_done, 0);
  2193. qdf_flush_work(&soc->htt_stats.work);
  2194. qdf_disable_work(&soc->htt_stats.work);
  2195. /* Free pending htt stats messages */
  2196. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2197. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2198. if (soc->pdev_list[i])
  2199. dp_pdev_detach_wifi3(
  2200. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2201. }
  2202. dp_peer_find_detach(soc);
  2203. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2204. * SW descriptors
  2205. */
  2206. /* Free the ring memories */
  2207. /* Common rings */
  2208. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2209. dp_tx_soc_detach(soc);
  2210. /* Tx data rings */
  2211. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2212. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2213. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2214. TCL_DATA, i);
  2215. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2216. WBM2SW_RELEASE, i);
  2217. }
  2218. }
  2219. /* TCL command and status rings */
  2220. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2221. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2222. /* Rx data rings */
  2223. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2224. soc->num_reo_dest_rings =
  2225. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2226. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2227. /* TODO: Get number of rings and ring sizes
  2228. * from wlan_cfg
  2229. */
  2230. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2231. REO_DST, i);
  2232. }
  2233. }
  2234. /* REO reinjection ring */
  2235. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2236. /* Rx release ring */
  2237. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2238. /* Rx exception ring */
  2239. /* TODO: Better to store ring_type and ring_num in
  2240. * dp_srng during setup
  2241. */
  2242. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2243. /* REO command and status rings */
  2244. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2245. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2246. dp_hw_link_desc_pool_cleanup(soc);
  2247. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2248. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2249. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2250. htt_soc_detach(soc->htt_handle);
  2251. dp_reo_cmdlist_destroy(soc);
  2252. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2253. dp_reo_desc_freelist_destroy(soc);
  2254. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2255. dp_soc_wds_detach(soc);
  2256. qdf_spinlock_destroy(&soc->ast_lock);
  2257. qdf_mem_free(soc);
  2258. }
  2259. /*
  2260. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2261. * @soc: data path SoC handle
  2262. * @pdev: physical device handle
  2263. *
  2264. * Return: void
  2265. */
  2266. #ifdef IPA_OFFLOAD
  2267. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2268. struct dp_pdev *pdev)
  2269. {
  2270. htt_srng_setup(soc->htt_handle, 0,
  2271. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2272. }
  2273. #else
  2274. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2275. struct dp_pdev *pdev)
  2276. {
  2277. }
  2278. #endif
  2279. /*
  2280. * dp_rxdma_ring_config() - configure the RX DMA rings
  2281. *
  2282. * This function is used to configure the MAC rings.
  2283. * On MCL host provides buffers in Host2FW ring
  2284. * FW refills (copies) buffers to the ring and updates
  2285. * ring_idx in register
  2286. *
  2287. * @soc: data path SoC handle
  2288. *
  2289. * Return: void
  2290. */
  2291. #ifdef QCA_HOST2FW_RXBUF_RING
  2292. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2293. {
  2294. int i;
  2295. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2296. struct dp_pdev *pdev = soc->pdev_list[i];
  2297. if (pdev) {
  2298. int mac_id = 0;
  2299. int j;
  2300. bool dbs_enable = 0;
  2301. int max_mac_rings =
  2302. wlan_cfg_get_num_mac_rings
  2303. (pdev->wlan_cfg_ctx);
  2304. htt_srng_setup(soc->htt_handle, 0,
  2305. pdev->rx_refill_buf_ring.hal_srng,
  2306. RXDMA_BUF);
  2307. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2308. if (soc->cdp_soc.ol_ops->
  2309. is_hw_dbs_2x2_capable) {
  2310. dbs_enable = soc->cdp_soc.ol_ops->
  2311. is_hw_dbs_2x2_capable(soc->psoc);
  2312. }
  2313. if (dbs_enable) {
  2314. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2315. QDF_TRACE_LEVEL_ERROR,
  2316. FL("DBS enabled max_mac_rings %d\n"),
  2317. max_mac_rings);
  2318. } else {
  2319. max_mac_rings = 1;
  2320. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2321. QDF_TRACE_LEVEL_ERROR,
  2322. FL("DBS disabled, max_mac_rings %d\n"),
  2323. max_mac_rings);
  2324. }
  2325. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2326. FL("pdev_id %d max_mac_rings %d\n"),
  2327. pdev->pdev_id, max_mac_rings);
  2328. for (j = 0; j < max_mac_rings; j++) {
  2329. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2330. QDF_TRACE_LEVEL_ERROR,
  2331. FL("mac_id %d\n"), mac_id);
  2332. htt_srng_setup(soc->htt_handle, mac_id,
  2333. pdev->rx_mac_buf_ring[j]
  2334. .hal_srng,
  2335. RXDMA_BUF);
  2336. mac_id++;
  2337. }
  2338. /* Configure monitor mode rings */
  2339. htt_srng_setup(soc->htt_handle, i,
  2340. pdev->rxdma_mon_buf_ring.hal_srng,
  2341. RXDMA_MONITOR_BUF);
  2342. htt_srng_setup(soc->htt_handle, i,
  2343. pdev->rxdma_mon_dst_ring.hal_srng,
  2344. RXDMA_MONITOR_DST);
  2345. htt_srng_setup(soc->htt_handle, i,
  2346. pdev->rxdma_mon_status_ring.hal_srng,
  2347. RXDMA_MONITOR_STATUS);
  2348. htt_srng_setup(soc->htt_handle, i,
  2349. pdev->rxdma_mon_desc_ring.hal_srng,
  2350. RXDMA_MONITOR_DESC);
  2351. htt_srng_setup(soc->htt_handle, i,
  2352. pdev->rxdma_err_dst_ring.hal_srng,
  2353. RXDMA_DST);
  2354. }
  2355. }
  2356. }
  2357. #else
  2358. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2359. {
  2360. int i;
  2361. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2362. struct dp_pdev *pdev = soc->pdev_list[i];
  2363. if (pdev) {
  2364. htt_srng_setup(soc->htt_handle, i,
  2365. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2366. htt_srng_setup(soc->htt_handle, i,
  2367. pdev->rxdma_mon_buf_ring.hal_srng,
  2368. RXDMA_MONITOR_BUF);
  2369. htt_srng_setup(soc->htt_handle, i,
  2370. pdev->rxdma_mon_dst_ring.hal_srng,
  2371. RXDMA_MONITOR_DST);
  2372. htt_srng_setup(soc->htt_handle, i,
  2373. pdev->rxdma_mon_status_ring.hal_srng,
  2374. RXDMA_MONITOR_STATUS);
  2375. htt_srng_setup(soc->htt_handle, i,
  2376. pdev->rxdma_mon_desc_ring.hal_srng,
  2377. RXDMA_MONITOR_DESC);
  2378. htt_srng_setup(soc->htt_handle, i,
  2379. pdev->rxdma_err_dst_ring.hal_srng,
  2380. RXDMA_DST);
  2381. }
  2382. }
  2383. }
  2384. #endif
  2385. /*
  2386. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2387. * @txrx_soc: Datapath SOC handle
  2388. */
  2389. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2390. {
  2391. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2392. htt_soc_attach_target(soc->htt_handle);
  2393. dp_rxdma_ring_config(soc);
  2394. DP_STATS_INIT(soc);
  2395. /* initialize work queue for stats processing */
  2396. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2397. return 0;
  2398. }
  2399. /*
  2400. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2401. * @txrx_soc: Datapath SOC handle
  2402. */
  2403. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2404. {
  2405. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2406. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2407. }
  2408. /*
  2409. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2410. * @txrx_soc: Datapath SOC handle
  2411. * @nss_cfg: nss config
  2412. */
  2413. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2414. {
  2415. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2416. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2417. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2418. FL("nss-wifi<0> nss config is enabled"));
  2419. }
  2420. /*
  2421. * dp_vdev_attach_wifi3() - attach txrx vdev
  2422. * @txrx_pdev: Datapath PDEV handle
  2423. * @vdev_mac_addr: MAC address of the virtual interface
  2424. * @vdev_id: VDEV Id
  2425. * @wlan_op_mode: VDEV operating mode
  2426. *
  2427. * Return: DP VDEV handle on success, NULL on failure
  2428. */
  2429. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2430. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2431. {
  2432. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2433. struct dp_soc *soc = pdev->soc;
  2434. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2435. int tx_ring_size;
  2436. if (!vdev) {
  2437. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2438. FL("DP VDEV memory allocation failed"));
  2439. goto fail0;
  2440. }
  2441. vdev->pdev = pdev;
  2442. vdev->vdev_id = vdev_id;
  2443. vdev->opmode = op_mode;
  2444. vdev->osdev = soc->osdev;
  2445. vdev->osif_rx = NULL;
  2446. vdev->osif_rsim_rx_decap = NULL;
  2447. vdev->osif_get_key = NULL;
  2448. vdev->osif_rx_mon = NULL;
  2449. vdev->osif_tx_free_ext = NULL;
  2450. vdev->osif_vdev = NULL;
  2451. vdev->delete.pending = 0;
  2452. vdev->safemode = 0;
  2453. vdev->drop_unenc = 1;
  2454. #ifdef notyet
  2455. vdev->filters_num = 0;
  2456. #endif
  2457. qdf_mem_copy(
  2458. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2459. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2460. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2461. vdev->dscp_tid_map_id = 0;
  2462. vdev->mcast_enhancement_en = 0;
  2463. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2464. /* TODO: Initialize default HTT meta data that will be used in
  2465. * TCL descriptors for packets transmitted from this VDEV
  2466. */
  2467. TAILQ_INIT(&vdev->peer_list);
  2468. /* add this vdev into the pdev's list */
  2469. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2470. pdev->vdev_count++;
  2471. dp_tx_vdev_attach(vdev);
  2472. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2473. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2474. goto fail1;
  2475. if ((soc->intr_mode == DP_INTR_POLL) &&
  2476. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2477. if (pdev->vdev_count == 1)
  2478. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2479. }
  2480. dp_lro_hash_setup(soc);
  2481. /* LRO */
  2482. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2483. wlan_op_mode_sta == vdev->opmode)
  2484. vdev->lro_enable = true;
  2485. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2486. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2487. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2488. "Created vdev %pK (%pM)", vdev, vdev->mac_addr.raw);
  2489. DP_STATS_INIT(vdev);
  2490. return (struct cdp_vdev *)vdev;
  2491. fail1:
  2492. dp_tx_vdev_detach(vdev);
  2493. qdf_mem_free(vdev);
  2494. fail0:
  2495. return NULL;
  2496. }
  2497. /**
  2498. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2499. * @vdev: Datapath VDEV handle
  2500. * @osif_vdev: OSIF vdev handle
  2501. * @txrx_ops: Tx and Rx operations
  2502. *
  2503. * Return: DP VDEV handle on success, NULL on failure
  2504. */
  2505. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2506. void *osif_vdev,
  2507. struct ol_txrx_ops *txrx_ops)
  2508. {
  2509. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2510. vdev->osif_vdev = osif_vdev;
  2511. vdev->osif_rx = txrx_ops->rx.rx;
  2512. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2513. vdev->osif_get_key = txrx_ops->get_key;
  2514. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2515. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2516. #ifdef notyet
  2517. #if ATH_SUPPORT_WAPI
  2518. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2519. #endif
  2520. #endif
  2521. #ifdef UMAC_SUPPORT_PROXY_ARP
  2522. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2523. #endif
  2524. vdev->me_convert = txrx_ops->me_convert;
  2525. /* TODO: Enable the following once Tx code is integrated */
  2526. txrx_ops->tx.tx = dp_tx_send;
  2527. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2528. "DP Vdev Register success");
  2529. }
  2530. /*
  2531. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2532. * @txrx_vdev: Datapath VDEV handle
  2533. * @callback: Callback OL_IF on completion of detach
  2534. * @cb_context: Callback context
  2535. *
  2536. */
  2537. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2538. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2539. {
  2540. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2541. struct dp_pdev *pdev = vdev->pdev;
  2542. struct dp_soc *soc = pdev->soc;
  2543. /* preconditions */
  2544. qdf_assert(vdev);
  2545. /* remove the vdev from its parent pdev's list */
  2546. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2547. /*
  2548. * Use peer_ref_mutex while accessing peer_list, in case
  2549. * a peer is in the process of being removed from the list.
  2550. */
  2551. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2552. /* check that the vdev has no peers allocated */
  2553. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2554. /* debug print - will be removed later */
  2555. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2556. FL("not deleting vdev object %pK (%pM)"
  2557. "until deletion finishes for all its peers"),
  2558. vdev, vdev->mac_addr.raw);
  2559. /* indicate that the vdev needs to be deleted */
  2560. vdev->delete.pending = 1;
  2561. vdev->delete.callback = callback;
  2562. vdev->delete.context = cb_context;
  2563. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2564. return;
  2565. }
  2566. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2567. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2568. vdev->vdev_id);
  2569. dp_tx_vdev_detach(vdev);
  2570. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2571. FL("deleting vdev object %pK (%pM)"), vdev, vdev->mac_addr.raw);
  2572. qdf_mem_free(vdev);
  2573. if (callback)
  2574. callback(cb_context);
  2575. }
  2576. /*
  2577. * dp_peer_create_wifi3() - attach txrx peer
  2578. * @txrx_vdev: Datapath VDEV handle
  2579. * @peer_mac_addr: Peer MAC address
  2580. *
  2581. * Return: DP peeer handle on success, NULL on failure
  2582. */
  2583. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2584. uint8_t *peer_mac_addr)
  2585. {
  2586. struct dp_peer *peer;
  2587. int i;
  2588. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2589. struct dp_pdev *pdev;
  2590. struct dp_soc *soc;
  2591. /* preconditions */
  2592. qdf_assert(vdev);
  2593. qdf_assert(peer_mac_addr);
  2594. pdev = vdev->pdev;
  2595. soc = pdev->soc;
  2596. #ifdef notyet
  2597. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2598. soc->mempool_ol_ath_peer);
  2599. #else
  2600. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2601. #endif
  2602. if (!peer)
  2603. return NULL; /* failure */
  2604. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2605. TAILQ_INIT(&peer->ast_entry_list);
  2606. /* store provided params */
  2607. peer->vdev = vdev;
  2608. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2609. qdf_spinlock_create(&peer->peer_info_lock);
  2610. qdf_mem_copy(
  2611. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2612. /* TODO: See of rx_opt_proc is really required */
  2613. peer->rx_opt_proc = soc->rx_opt_proc;
  2614. /* initialize the peer_id */
  2615. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2616. peer->peer_ids[i] = HTT_INVALID_PEER;
  2617. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2618. qdf_atomic_init(&peer->ref_cnt);
  2619. /* keep one reference for attach */
  2620. qdf_atomic_inc(&peer->ref_cnt);
  2621. /* add this peer into the vdev's list */
  2622. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2623. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2624. /* TODO: See if hash based search is required */
  2625. dp_peer_find_hash_add(soc, peer);
  2626. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2627. "vdev %pK created peer %pK (%pM) ref_cnt: %d",
  2628. vdev, peer, peer->mac_addr.raw,
  2629. qdf_atomic_read(&peer->ref_cnt));
  2630. /*
  2631. * For every peer MAp message search and set if bss_peer
  2632. */
  2633. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2634. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2635. "vdev bss_peer!!!!");
  2636. peer->bss_peer = 1;
  2637. vdev->vap_bss_peer = peer;
  2638. }
  2639. #ifndef CONFIG_WIN
  2640. dp_local_peer_id_alloc(pdev, peer);
  2641. #endif
  2642. DP_STATS_INIT(peer);
  2643. return (void *)peer;
  2644. }
  2645. /*
  2646. * dp_peer_setup_wifi3() - initialize the peer
  2647. * @vdev_hdl: virtual device object
  2648. * @peer: Peer object
  2649. *
  2650. * Return: void
  2651. */
  2652. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2653. {
  2654. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2655. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2656. struct dp_pdev *pdev;
  2657. struct dp_soc *soc;
  2658. bool hash_based = 0;
  2659. enum cdp_host_reo_dest_ring reo_dest;
  2660. /* preconditions */
  2661. qdf_assert(vdev);
  2662. qdf_assert(peer);
  2663. pdev = vdev->pdev;
  2664. soc = pdev->soc;
  2665. dp_peer_rx_init(pdev, peer);
  2666. peer->last_assoc_rcvd = 0;
  2667. peer->last_disassoc_rcvd = 0;
  2668. peer->last_deauth_rcvd = 0;
  2669. /*
  2670. * hash based steering is disabled for Radios which are offloaded
  2671. * to NSS
  2672. */
  2673. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2674. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2675. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2676. FL("hash based steering for pdev: %d is %d\n"),
  2677. pdev->pdev_id, hash_based);
  2678. if (!hash_based)
  2679. reo_dest = pdev->reo_dest;
  2680. else
  2681. reo_dest = 1;
  2682. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2683. /* TODO: Check the destination ring number to be passed to FW */
  2684. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2685. pdev->osif_pdev, peer->mac_addr.raw,
  2686. peer->vdev->vdev_id, hash_based, reo_dest);
  2687. }
  2688. return;
  2689. }
  2690. /*
  2691. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2692. * @vdev_handle: virtual device object
  2693. * @htt_pkt_type: type of pkt
  2694. *
  2695. * Return: void
  2696. */
  2697. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2698. enum htt_cmn_pkt_type val)
  2699. {
  2700. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2701. vdev->tx_encap_type = val;
  2702. }
  2703. /*
  2704. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2705. * @vdev_handle: virtual device object
  2706. * @htt_pkt_type: type of pkt
  2707. *
  2708. * Return: void
  2709. */
  2710. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2711. enum htt_cmn_pkt_type val)
  2712. {
  2713. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2714. vdev->rx_decap_type = val;
  2715. }
  2716. /*
  2717. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2718. * @pdev_handle: physical device object
  2719. * @val: reo destination ring index (1 - 4)
  2720. *
  2721. * Return: void
  2722. */
  2723. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2724. enum cdp_host_reo_dest_ring val)
  2725. {
  2726. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2727. if (pdev)
  2728. pdev->reo_dest = val;
  2729. }
  2730. /*
  2731. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2732. * @pdev_handle: physical device object
  2733. *
  2734. * Return: reo destination ring index
  2735. */
  2736. static enum cdp_host_reo_dest_ring
  2737. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2738. {
  2739. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2740. if (pdev)
  2741. return pdev->reo_dest;
  2742. else
  2743. return cdp_host_reo_dest_ring_unknown;
  2744. }
  2745. #ifdef QCA_SUPPORT_SON
  2746. static void dp_son_peer_authorize(struct dp_peer *peer)
  2747. {
  2748. struct dp_soc *soc;
  2749. soc = peer->vdev->pdev->soc;
  2750. peer->peer_bs_inact_flag = 0;
  2751. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2752. return;
  2753. }
  2754. #else
  2755. static void dp_son_peer_authorize(struct dp_peer *peer)
  2756. {
  2757. return;
  2758. }
  2759. #endif
  2760. /*
  2761. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2762. * @pdev_handle: device object
  2763. * @val: value to be set
  2764. *
  2765. * Return: void
  2766. */
  2767. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2768. uint32_t val)
  2769. {
  2770. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2771. /* Enable/Disable smart mesh filtering. This flag will be checked
  2772. * during rx processing to check if packets are from NAC clients.
  2773. */
  2774. pdev->filter_neighbour_peers = val;
  2775. return 0;
  2776. }
  2777. /*
  2778. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2779. * address for smart mesh filtering
  2780. * @pdev_handle: device object
  2781. * @cmd: Add/Del command
  2782. * @macaddr: nac client mac address
  2783. *
  2784. * Return: void
  2785. */
  2786. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2787. uint32_t cmd, uint8_t *macaddr)
  2788. {
  2789. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2790. struct dp_neighbour_peer *peer = NULL;
  2791. if (!macaddr)
  2792. goto fail0;
  2793. /* Store address of NAC (neighbour peer) which will be checked
  2794. * against TA of received packets.
  2795. */
  2796. if (cmd == DP_NAC_PARAM_ADD) {
  2797. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2798. sizeof(*peer));
  2799. if (!peer) {
  2800. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2801. FL("DP neighbour peer node memory allocation failed"));
  2802. goto fail0;
  2803. }
  2804. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2805. macaddr, DP_MAC_ADDR_LEN);
  2806. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2807. /* add this neighbour peer into the list */
  2808. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2809. neighbour_peer_list_elem);
  2810. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2811. return 1;
  2812. } else if (cmd == DP_NAC_PARAM_DEL) {
  2813. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2814. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2815. neighbour_peer_list_elem) {
  2816. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2817. macaddr, DP_MAC_ADDR_LEN)) {
  2818. /* delete this peer from the list */
  2819. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2820. peer, neighbour_peer_list_elem);
  2821. qdf_mem_free(peer);
  2822. break;
  2823. }
  2824. }
  2825. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2826. return 1;
  2827. }
  2828. fail0:
  2829. return 0;
  2830. }
  2831. /*
  2832. * dp_get_sec_type() - Get the security type
  2833. * @peer: Datapath peer handle
  2834. * @sec_idx: Security id (mcast, ucast)
  2835. *
  2836. * return sec_type: Security type
  2837. */
  2838. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2839. {
  2840. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2841. return dpeer->security[sec_idx].sec_type;
  2842. }
  2843. /*
  2844. * dp_peer_authorize() - authorize txrx peer
  2845. * @peer_handle: Datapath peer handle
  2846. * @authorize
  2847. *
  2848. */
  2849. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2850. {
  2851. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2852. struct dp_soc *soc;
  2853. if (peer != NULL) {
  2854. soc = peer->vdev->pdev->soc;
  2855. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2856. dp_son_peer_authorize(peer);
  2857. peer->authorize = authorize ? 1 : 0;
  2858. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2859. }
  2860. }
  2861. /*
  2862. * dp_peer_unref_delete() - unref and delete peer
  2863. * @peer_handle: Datapath peer handle
  2864. *
  2865. */
  2866. void dp_peer_unref_delete(void *peer_handle)
  2867. {
  2868. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2869. struct dp_vdev *vdev = peer->vdev;
  2870. struct dp_pdev *pdev = vdev->pdev;
  2871. struct dp_soc *soc = pdev->soc;
  2872. struct dp_peer *tmppeer;
  2873. int found = 0;
  2874. uint16_t peer_id;
  2875. /*
  2876. * Hold the lock all the way from checking if the peer ref count
  2877. * is zero until the peer references are removed from the hash
  2878. * table and vdev list (if the peer ref count is zero).
  2879. * This protects against a new HL tx operation starting to use the
  2880. * peer object just after this function concludes it's done being used.
  2881. * Furthermore, the lock needs to be held while checking whether the
  2882. * vdev's list of peers is empty, to make sure that list is not modified
  2883. * concurrently with the empty check.
  2884. */
  2885. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2886. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2887. "%s: peer %pK ref_cnt(before decrement): %d\n", __func__,
  2888. peer, qdf_atomic_read(&peer->ref_cnt));
  2889. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2890. peer_id = peer->peer_ids[0];
  2891. /*
  2892. * Make sure that the reference to the peer in
  2893. * peer object map is removed
  2894. */
  2895. if (peer_id != HTT_INVALID_PEER)
  2896. soc->peer_id_to_obj_map[peer_id] = NULL;
  2897. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2898. "Deleting peer %pK (%pM)", peer, peer->mac_addr.raw);
  2899. /* remove the reference to the peer from the hash table */
  2900. dp_peer_find_hash_remove(soc, peer);
  2901. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2902. if (tmppeer == peer) {
  2903. found = 1;
  2904. break;
  2905. }
  2906. }
  2907. if (found) {
  2908. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2909. peer_list_elem);
  2910. } else {
  2911. /*Ignoring the remove operation as peer not found*/
  2912. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2913. "peer %pK not found in vdev (%pK)->peer_list:%pK",
  2914. peer, vdev, &peer->vdev->peer_list);
  2915. }
  2916. /* cleanup the peer data */
  2917. dp_peer_cleanup(vdev, peer);
  2918. /* check whether the parent vdev has no peers left */
  2919. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2920. /*
  2921. * Now that there are no references to the peer, we can
  2922. * release the peer reference lock.
  2923. */
  2924. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2925. /*
  2926. * Check if the parent vdev was waiting for its peers
  2927. * to be deleted, in order for it to be deleted too.
  2928. */
  2929. if (vdev->delete.pending) {
  2930. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2931. vdev->delete.callback;
  2932. void *vdev_delete_context =
  2933. vdev->delete.context;
  2934. QDF_TRACE(QDF_MODULE_ID_DP,
  2935. QDF_TRACE_LEVEL_INFO_HIGH,
  2936. FL("deleting vdev object %pK (%pM)"
  2937. " - its last peer is done"),
  2938. vdev, vdev->mac_addr.raw);
  2939. /* all peers are gone, go ahead and delete it */
  2940. qdf_mem_free(vdev);
  2941. if (vdev_delete_cb)
  2942. vdev_delete_cb(vdev_delete_context);
  2943. }
  2944. } else {
  2945. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2946. }
  2947. #ifdef notyet
  2948. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2949. #else
  2950. qdf_mem_free(peer);
  2951. #endif
  2952. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2953. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2954. vdev->vdev_id, peer->mac_addr.raw);
  2955. }
  2956. } else {
  2957. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2958. }
  2959. }
  2960. /*
  2961. * dp_peer_detach_wifi3() – Detach txrx peer
  2962. * @peer_handle: Datapath peer handle
  2963. *
  2964. */
  2965. static void dp_peer_delete_wifi3(void *peer_handle)
  2966. {
  2967. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2968. /* redirect the peer's rx delivery function to point to a
  2969. * discard func
  2970. */
  2971. peer->rx_opt_proc = dp_rx_discard;
  2972. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2973. FL("peer %pK (%pM)"), peer, peer->mac_addr.raw);
  2974. #ifndef CONFIG_WIN
  2975. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2976. #endif
  2977. qdf_spinlock_destroy(&peer->peer_info_lock);
  2978. /*
  2979. * Remove the reference added during peer_attach.
  2980. * The peer will still be left allocated until the
  2981. * PEER_UNMAP message arrives to remove the other
  2982. * reference, added by the PEER_MAP message.
  2983. */
  2984. dp_peer_unref_delete(peer_handle);
  2985. }
  2986. /*
  2987. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2988. * @peer_handle: Datapath peer handle
  2989. *
  2990. */
  2991. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2992. {
  2993. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2994. return vdev->mac_addr.raw;
  2995. }
  2996. /*
  2997. * dp_vdev_set_wds() - Enable per packet stats
  2998. * @vdev_handle: DP VDEV handle
  2999. * @val: value
  3000. *
  3001. * Return: none
  3002. */
  3003. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  3004. {
  3005. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3006. vdev->wds_enabled = val;
  3007. return 0;
  3008. }
  3009. /*
  3010. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  3011. * @peer_handle: Datapath peer handle
  3012. *
  3013. */
  3014. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3015. uint8_t vdev_id)
  3016. {
  3017. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3018. struct dp_vdev *vdev = NULL;
  3019. if (qdf_unlikely(!pdev))
  3020. return NULL;
  3021. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3022. if (vdev->vdev_id == vdev_id)
  3023. break;
  3024. }
  3025. return (struct cdp_vdev *)vdev;
  3026. }
  3027. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3028. {
  3029. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3030. return vdev->opmode;
  3031. }
  3032. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3033. {
  3034. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3035. struct dp_pdev *pdev = vdev->pdev;
  3036. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3037. }
  3038. /**
  3039. * dp_reset_monitor_mode() - Disable monitor mode
  3040. * @pdev_handle: Datapath PDEV handle
  3041. *
  3042. * Return: 0 on success, not 0 on failure
  3043. */
  3044. static int dp_reset_monitor_mode(struct cdp_pdev *pdev_handle)
  3045. {
  3046. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3047. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3048. struct dp_soc *soc;
  3049. uint8_t pdev_id;
  3050. pdev_id = pdev->pdev_id;
  3051. soc = pdev->soc;
  3052. pdev->monitor_vdev = NULL;
  3053. qdf_mem_set(&(htt_tlv_filter), sizeof(htt_tlv_filter), 0x0);
  3054. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3055. pdev->rxdma_mon_buf_ring.hal_srng,
  3056. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3057. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3058. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3059. RX_BUFFER_SIZE, &htt_tlv_filter);
  3060. return 0;
  3061. }
  3062. /**
  3063. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3064. * @vdev_handle: Datapath VDEV handle
  3065. * @smart_monitor: Flag to denote if its smart monitor mode
  3066. *
  3067. * Return: 0 on success, not 0 on failure
  3068. */
  3069. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3070. uint8_t smart_monitor)
  3071. {
  3072. /* Many monitor VAPs can exists in a system but only one can be up at
  3073. * anytime
  3074. */
  3075. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3076. struct dp_pdev *pdev;
  3077. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3078. struct dp_soc *soc;
  3079. uint8_t pdev_id;
  3080. qdf_assert(vdev);
  3081. pdev = vdev->pdev;
  3082. pdev_id = pdev->pdev_id;
  3083. soc = pdev->soc;
  3084. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3085. "pdev=%pK, pdev_id=%d, soc=%pK vdev=%pK\n",
  3086. pdev, pdev_id, soc, vdev);
  3087. /*Check if current pdev's monitor_vdev exists */
  3088. if (pdev->monitor_vdev) {
  3089. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3090. "vdev=%pK\n", vdev);
  3091. qdf_assert(vdev);
  3092. }
  3093. pdev->monitor_vdev = vdev;
  3094. /* If smart monitor mode, do not configure monitor ring */
  3095. if (smart_monitor)
  3096. return QDF_STATUS_SUCCESS;
  3097. htt_tlv_filter.mpdu_start = 1;
  3098. htt_tlv_filter.msdu_start = 1;
  3099. htt_tlv_filter.packet = 1;
  3100. htt_tlv_filter.msdu_end = 1;
  3101. htt_tlv_filter.mpdu_end = 1;
  3102. htt_tlv_filter.packet_header = 1;
  3103. htt_tlv_filter.attention = 1;
  3104. htt_tlv_filter.ppdu_start = 0;
  3105. htt_tlv_filter.ppdu_end = 0;
  3106. htt_tlv_filter.ppdu_end_user_stats = 0;
  3107. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3108. htt_tlv_filter.ppdu_end_status_done = 0;
  3109. htt_tlv_filter.header_per_msdu = 1;
  3110. htt_tlv_filter.enable_fp = 1;
  3111. htt_tlv_filter.enable_md = 0;
  3112. htt_tlv_filter.enable_mo = 1;
  3113. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3114. pdev->rxdma_mon_buf_ring.hal_srng,
  3115. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3116. htt_tlv_filter.mpdu_start = 1;
  3117. htt_tlv_filter.msdu_start = 1;
  3118. htt_tlv_filter.packet = 0;
  3119. htt_tlv_filter.msdu_end = 1;
  3120. htt_tlv_filter.mpdu_end = 1;
  3121. htt_tlv_filter.packet_header = 1;
  3122. htt_tlv_filter.attention = 1;
  3123. htt_tlv_filter.ppdu_start = 1;
  3124. htt_tlv_filter.ppdu_end = 1;
  3125. htt_tlv_filter.ppdu_end_user_stats = 1;
  3126. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3127. htt_tlv_filter.ppdu_end_status_done = 1;
  3128. htt_tlv_filter.header_per_msdu = 0;
  3129. htt_tlv_filter.enable_fp = 1;
  3130. htt_tlv_filter.enable_md = 0;
  3131. htt_tlv_filter.enable_mo = 1;
  3132. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3133. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3134. RX_BUFFER_SIZE, &htt_tlv_filter);
  3135. return QDF_STATUS_SUCCESS;
  3136. }
  3137. #ifdef MESH_MODE_SUPPORT
  3138. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3139. {
  3140. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3141. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3142. FL("val %d"), val);
  3143. vdev->mesh_vdev = val;
  3144. }
  3145. /*
  3146. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3147. * @vdev_hdl: virtual device object
  3148. * @val: value to be set
  3149. *
  3150. * Return: void
  3151. */
  3152. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3153. {
  3154. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3155. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3156. FL("val %d"), val);
  3157. vdev->mesh_rx_filter = val;
  3158. }
  3159. #endif
  3160. /**
  3161. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3162. * @vdev: DP VDEV handle
  3163. *
  3164. * return: void
  3165. */
  3166. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3167. {
  3168. struct dp_peer *peer = NULL;
  3169. struct dp_soc *soc = vdev->pdev->soc;
  3170. int i;
  3171. uint8_t pream_type;
  3172. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3173. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3174. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3175. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3176. for (i = 0; i < MAX_MCS; i++) {
  3177. DP_STATS_AGGR(vdev, peer,
  3178. tx.pkt_type[pream_type].mcs_count[i]);
  3179. DP_STATS_AGGR(vdev, peer,
  3180. rx.pkt_type[pream_type].mcs_count[i]);
  3181. }
  3182. }
  3183. for (i = 0; i < MAX_BW; i++) {
  3184. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3185. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3186. }
  3187. for (i = 0; i < SS_COUNT; i++)
  3188. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3189. for (i = 0; i < WME_AC_MAX; i++) {
  3190. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3191. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3192. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3193. }
  3194. for (i = 0; i < MAX_GI; i++) {
  3195. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3196. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3197. }
  3198. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3199. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3200. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3201. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3202. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3203. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3204. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3205. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3206. DP_STATS_AGGR(vdev, peer, tx.retries);
  3207. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3208. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3209. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3210. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3211. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3212. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3213. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3214. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3215. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3216. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3217. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3218. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3219. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3220. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3221. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3222. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3223. peer->stats.rx.multicast.num;
  3224. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3225. peer->stats.rx.multicast.bytes;
  3226. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3227. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3228. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3229. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3230. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3231. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3232. vdev->stats.tx.last_ack_rssi =
  3233. peer->stats.tx.last_ack_rssi;
  3234. }
  3235. if (soc->cdp_soc.ol_ops->update_dp_stats)
  3236. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3237. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3238. }
  3239. /**
  3240. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3241. * @pdev: DP PDEV handle
  3242. *
  3243. * return: void
  3244. */
  3245. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3246. {
  3247. struct dp_vdev *vdev = NULL;
  3248. uint8_t i;
  3249. uint8_t pream_type;
  3250. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3251. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3252. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3253. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3254. dp_aggregate_vdev_stats(vdev);
  3255. for (pream_type = 0; pream_type < DOT11_MAX; pream_type++) {
  3256. for (i = 0; i < MAX_MCS; i++) {
  3257. DP_STATS_AGGR(pdev, vdev,
  3258. tx.pkt_type[pream_type].mcs_count[i]);
  3259. DP_STATS_AGGR(pdev, vdev,
  3260. rx.pkt_type[pream_type].mcs_count[i]);
  3261. }
  3262. }
  3263. for (i = 0; i < MAX_BW; i++) {
  3264. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3265. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3266. }
  3267. for (i = 0; i < SS_COUNT; i++)
  3268. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3269. for (i = 0; i < WME_AC_MAX; i++) {
  3270. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3271. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3272. DP_STATS_AGGR(pdev, vdev,
  3273. tx.excess_retries_ac[i]);
  3274. }
  3275. for (i = 0; i < MAX_GI; i++) {
  3276. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3277. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3278. }
  3279. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3280. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3281. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3282. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3283. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3284. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3285. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3286. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3287. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3288. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3289. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3290. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3291. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3292. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3293. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3294. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3295. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3296. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3297. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3298. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3299. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3300. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3301. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3302. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3303. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3304. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3305. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3306. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3307. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3308. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3309. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3310. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3311. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3312. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3313. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3314. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3315. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3316. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3317. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3318. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3319. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3320. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3321. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3322. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3323. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3324. DP_STATS_AGGR(pdev, vdev,
  3325. tx_i.mcast_en.dropped_map_error);
  3326. DP_STATS_AGGR(pdev, vdev,
  3327. tx_i.mcast_en.dropped_self_mac);
  3328. DP_STATS_AGGR(pdev, vdev,
  3329. tx_i.mcast_en.dropped_send_fail);
  3330. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3331. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3332. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3333. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3334. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3335. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3336. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3337. pdev->stats.tx_i.dropped.dma_error +
  3338. pdev->stats.tx_i.dropped.ring_full +
  3339. pdev->stats.tx_i.dropped.enqueue_fail +
  3340. pdev->stats.tx_i.dropped.desc_na +
  3341. pdev->stats.tx_i.dropped.res_full;
  3342. pdev->stats.tx.last_ack_rssi =
  3343. vdev->stats.tx.last_ack_rssi;
  3344. pdev->stats.tx_i.tso.num_seg =
  3345. vdev->stats.tx_i.tso.num_seg;
  3346. }
  3347. }
  3348. /**
  3349. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3350. * @pdev: DP_PDEV Handle
  3351. *
  3352. * Return:void
  3353. */
  3354. static inline void
  3355. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3356. {
  3357. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3358. DP_PRINT_STATS("Received From Stack:");
  3359. DP_PRINT_STATS(" Packets = %d",
  3360. pdev->stats.tx_i.rcvd.num);
  3361. DP_PRINT_STATS(" Bytes = %d",
  3362. pdev->stats.tx_i.rcvd.bytes);
  3363. DP_PRINT_STATS("Processed:");
  3364. DP_PRINT_STATS(" Packets = %d",
  3365. pdev->stats.tx_i.processed.num);
  3366. DP_PRINT_STATS(" Bytes = %d",
  3367. pdev->stats.tx_i.processed.bytes);
  3368. DP_PRINT_STATS("Completions:");
  3369. DP_PRINT_STATS(" Packets = %d",
  3370. pdev->stats.tx.comp_pkt.num);
  3371. DP_PRINT_STATS(" Bytes = %d",
  3372. pdev->stats.tx.comp_pkt.bytes);
  3373. DP_PRINT_STATS("Dropped:");
  3374. DP_PRINT_STATS(" Total = %d",
  3375. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3376. DP_PRINT_STATS(" Dma_map_error = %d",
  3377. pdev->stats.tx_i.dropped.dma_error);
  3378. DP_PRINT_STATS(" Ring Full = %d",
  3379. pdev->stats.tx_i.dropped.ring_full);
  3380. DP_PRINT_STATS(" Descriptor Not available = %d",
  3381. pdev->stats.tx_i.dropped.desc_na);
  3382. DP_PRINT_STATS(" HW enqueue failed= %d",
  3383. pdev->stats.tx_i.dropped.enqueue_fail);
  3384. DP_PRINT_STATS(" Resources Full = %d",
  3385. pdev->stats.tx_i.dropped.res_full);
  3386. DP_PRINT_STATS(" FW removed = %d",
  3387. pdev->stats.tx.dropped.fw_rem);
  3388. DP_PRINT_STATS(" FW removed transmitted = %d",
  3389. pdev->stats.tx.dropped.fw_rem_tx);
  3390. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3391. pdev->stats.tx.dropped.fw_rem_notx);
  3392. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3393. pdev->stats.tx.dropped.age_out);
  3394. DP_PRINT_STATS("Scatter Gather:");
  3395. DP_PRINT_STATS(" Packets = %d",
  3396. pdev->stats.tx_i.sg.sg_pkt.num);
  3397. DP_PRINT_STATS(" Bytes = %d",
  3398. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3399. DP_PRINT_STATS(" Dropped By Host = %d",
  3400. pdev->stats.tx_i.sg.dropped_host);
  3401. DP_PRINT_STATS(" Dropped By Target = %d",
  3402. pdev->stats.tx_i.sg.dropped_target);
  3403. DP_PRINT_STATS("TSO:");
  3404. DP_PRINT_STATS(" Number of Segments = %d",
  3405. pdev->stats.tx_i.tso.num_seg);
  3406. DP_PRINT_STATS(" Packets = %d",
  3407. pdev->stats.tx_i.tso.tso_pkt.num);
  3408. DP_PRINT_STATS(" Bytes = %d",
  3409. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3410. DP_PRINT_STATS(" Dropped By Host = %d",
  3411. pdev->stats.tx_i.tso.dropped_host);
  3412. DP_PRINT_STATS("Mcast Enhancement:");
  3413. DP_PRINT_STATS(" Packets = %d",
  3414. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3415. DP_PRINT_STATS(" Bytes = %d",
  3416. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3417. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3418. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3419. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3420. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3421. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3422. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3423. DP_PRINT_STATS(" Unicast sent = %d",
  3424. pdev->stats.tx_i.mcast_en.ucast);
  3425. DP_PRINT_STATS("Raw:");
  3426. DP_PRINT_STATS(" Packets = %d",
  3427. pdev->stats.tx_i.raw.raw_pkt.num);
  3428. DP_PRINT_STATS(" Bytes = %d",
  3429. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3430. DP_PRINT_STATS(" DMA map error = %d",
  3431. pdev->stats.tx_i.raw.dma_map_error);
  3432. DP_PRINT_STATS("Reinjected:");
  3433. DP_PRINT_STATS(" Packets = %d",
  3434. pdev->stats.tx_i.reinject_pkts.num);
  3435. DP_PRINT_STATS("Bytes = %d\n",
  3436. pdev->stats.tx_i.reinject_pkts.bytes);
  3437. DP_PRINT_STATS("Inspected:");
  3438. DP_PRINT_STATS(" Packets = %d",
  3439. pdev->stats.tx_i.inspect_pkts.num);
  3440. DP_PRINT_STATS(" Bytes = %d",
  3441. pdev->stats.tx_i.inspect_pkts.bytes);
  3442. }
  3443. /**
  3444. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3445. * @pdev: DP_PDEV Handle
  3446. *
  3447. * Return: void
  3448. */
  3449. static inline void
  3450. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3451. {
  3452. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3453. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3454. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3455. pdev->stats.rx.rcvd_reo[0].num,
  3456. pdev->stats.rx.rcvd_reo[1].num,
  3457. pdev->stats.rx.rcvd_reo[2].num,
  3458. pdev->stats.rx.rcvd_reo[3].num);
  3459. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3460. pdev->stats.rx.rcvd_reo[0].bytes,
  3461. pdev->stats.rx.rcvd_reo[1].bytes,
  3462. pdev->stats.rx.rcvd_reo[2].bytes,
  3463. pdev->stats.rx.rcvd_reo[3].bytes);
  3464. DP_PRINT_STATS("Replenished:");
  3465. DP_PRINT_STATS(" Packets = %d",
  3466. pdev->stats.replenish.pkts.num);
  3467. DP_PRINT_STATS(" Bytes = %d",
  3468. pdev->stats.replenish.pkts.bytes);
  3469. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3470. pdev->stats.buf_freelist);
  3471. DP_PRINT_STATS("Dropped:");
  3472. DP_PRINT_STATS(" msdu_not_done = %d",
  3473. pdev->stats.dropped.msdu_not_done);
  3474. DP_PRINT_STATS("Sent To Stack:");
  3475. DP_PRINT_STATS(" Packets = %d",
  3476. pdev->stats.rx.to_stack.num);
  3477. DP_PRINT_STATS(" Bytes = %d",
  3478. pdev->stats.rx.to_stack.bytes);
  3479. DP_PRINT_STATS("Multicast/Broadcast:");
  3480. DP_PRINT_STATS(" Packets = %d",
  3481. pdev->stats.rx.multicast.num);
  3482. DP_PRINT_STATS(" Bytes = %d",
  3483. pdev->stats.rx.multicast.bytes);
  3484. DP_PRINT_STATS("Errors:");
  3485. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3486. pdev->stats.replenish.rxdma_err);
  3487. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3488. pdev->stats.err.desc_alloc_fail);
  3489. }
  3490. /**
  3491. * dp_print_soc_tx_stats(): Print SOC level stats
  3492. * @soc DP_SOC Handle
  3493. *
  3494. * Return: void
  3495. */
  3496. static inline void
  3497. dp_print_soc_tx_stats(struct dp_soc *soc)
  3498. {
  3499. DP_PRINT_STATS("SOC Tx Stats:\n");
  3500. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3501. soc->stats.tx.desc_in_use);
  3502. DP_PRINT_STATS("Invalid peer:");
  3503. DP_PRINT_STATS(" Packets = %d",
  3504. soc->stats.tx.tx_invalid_peer.num);
  3505. DP_PRINT_STATS(" Bytes = %d",
  3506. soc->stats.tx.tx_invalid_peer.bytes);
  3507. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3508. soc->stats.tx.tcl_ring_full[0],
  3509. soc->stats.tx.tcl_ring_full[1],
  3510. soc->stats.tx.tcl_ring_full[2]);
  3511. }
  3512. /**
  3513. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3514. * @soc: DP_SOC Handle
  3515. *
  3516. * Return:void
  3517. */
  3518. static inline void
  3519. dp_print_soc_rx_stats(struct dp_soc *soc)
  3520. {
  3521. uint32_t i;
  3522. char reo_error[DP_REO_ERR_LENGTH];
  3523. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3524. uint8_t index = 0;
  3525. DP_PRINT_STATS("SOC Rx Stats:\n");
  3526. DP_PRINT_STATS("Errors:\n");
  3527. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3528. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3529. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3530. DP_PRINT_STATS("Invalid RBM = %d",
  3531. soc->stats.rx.err.invalid_rbm);
  3532. DP_PRINT_STATS("Invalid Vdev = %d",
  3533. soc->stats.rx.err.invalid_vdev);
  3534. DP_PRINT_STATS("Invalid Pdev = %d",
  3535. soc->stats.rx.err.invalid_pdev);
  3536. DP_PRINT_STATS("Invalid Peer = %d",
  3537. soc->stats.rx.err.rx_invalid_peer.num);
  3538. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3539. soc->stats.rx.err.hal_ring_access_fail);
  3540. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3541. index += qdf_snprint(&rxdma_error[index],
  3542. DP_RXDMA_ERR_LENGTH - index,
  3543. " %d", soc->stats.rx.err.rxdma_error[i]);
  3544. }
  3545. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3546. rxdma_error);
  3547. index = 0;
  3548. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3549. index += qdf_snprint(&reo_error[index],
  3550. DP_REO_ERR_LENGTH - index,
  3551. " %d", soc->stats.rx.err.reo_error[i]);
  3552. }
  3553. DP_PRINT_STATS("REO Error(0-14):%s",
  3554. reo_error);
  3555. }
  3556. /**
  3557. * dp_print_ring_stat_from_hal(): Print hal level ring stats
  3558. * @soc: DP_SOC handle
  3559. * @srng: DP_SRNG handle
  3560. * @ring_name: SRNG name
  3561. *
  3562. * Return: void
  3563. */
  3564. static inline void
  3565. dp_print_ring_stat_from_hal(struct dp_soc *soc, struct dp_srng *srng,
  3566. char *ring_name)
  3567. {
  3568. uint32_t tailp;
  3569. uint32_t headp;
  3570. if (srng->hal_srng != NULL) {
  3571. hal_api_get_tphp(soc->hal_soc, srng->hal_srng, &tailp, &headp);
  3572. DP_PRINT_STATS("%s : Head pointer = %d Tail Pointer = %d\n",
  3573. ring_name, headp, tailp);
  3574. }
  3575. }
  3576. /**
  3577. * dp_print_ring_stats(): Print tail and head pointer
  3578. * @pdev: DP_PDEV handle
  3579. *
  3580. * Return:void
  3581. */
  3582. static inline void
  3583. dp_print_ring_stats(struct dp_pdev *pdev)
  3584. {
  3585. uint32_t i;
  3586. char ring_name[STR_MAXLEN + 1];
  3587. dp_print_ring_stat_from_hal(pdev->soc,
  3588. &pdev->soc->reo_exception_ring,
  3589. "Reo Exception Ring");
  3590. dp_print_ring_stat_from_hal(pdev->soc,
  3591. &pdev->soc->reo_reinject_ring,
  3592. "Reo Inject Ring");
  3593. dp_print_ring_stat_from_hal(pdev->soc,
  3594. &pdev->soc->reo_cmd_ring,
  3595. "Reo Command Ring");
  3596. dp_print_ring_stat_from_hal(pdev->soc,
  3597. &pdev->soc->reo_status_ring,
  3598. "Reo Status Ring");
  3599. dp_print_ring_stat_from_hal(pdev->soc,
  3600. &pdev->soc->rx_rel_ring,
  3601. "Rx Release ring");
  3602. dp_print_ring_stat_from_hal(pdev->soc,
  3603. &pdev->soc->tcl_cmd_ring,
  3604. "Tcl command Ring");
  3605. dp_print_ring_stat_from_hal(pdev->soc,
  3606. &pdev->soc->tcl_status_ring,
  3607. "Tcl Status Ring");
  3608. dp_print_ring_stat_from_hal(pdev->soc,
  3609. &pdev->soc->wbm_desc_rel_ring,
  3610. "Wbm Desc Rel Ring");
  3611. for (i = 0; i < MAX_REO_DEST_RINGS; i++) {
  3612. snprintf(ring_name, STR_MAXLEN, "Reo Dest Ring %d", i);
  3613. dp_print_ring_stat_from_hal(pdev->soc,
  3614. &pdev->soc->reo_dest_ring[i],
  3615. ring_name);
  3616. }
  3617. for (i = 0; i < pdev->soc->num_tcl_data_rings; i++) {
  3618. snprintf(ring_name, STR_MAXLEN, "Tcl Data Ring %d", i);
  3619. dp_print_ring_stat_from_hal(pdev->soc,
  3620. &pdev->soc->tcl_data_ring[i],
  3621. ring_name);
  3622. }
  3623. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  3624. snprintf(ring_name, STR_MAXLEN, "Tx Comp Ring %d", i);
  3625. dp_print_ring_stat_from_hal(pdev->soc,
  3626. &pdev->soc->tx_comp_ring[i],
  3627. ring_name);
  3628. }
  3629. dp_print_ring_stat_from_hal(pdev->soc,
  3630. &pdev->rx_refill_buf_ring,
  3631. "Rx Refill Buf Ring");
  3632. #ifdef IPA_OFFLOAD
  3633. dp_print_ring_stat_from_hal(pdev->soc,
  3634. &pdev->ipa_rx_refill_buf_ring,
  3635. "IPA Rx Refill Buf Ring");
  3636. #endif
  3637. dp_print_ring_stat_from_hal(pdev->soc,
  3638. &pdev->rxdma_mon_buf_ring,
  3639. "Rxdma Mon Buf Ring");
  3640. dp_print_ring_stat_from_hal(pdev->soc,
  3641. &pdev->rxdma_mon_dst_ring,
  3642. "Rxdma Mon Dst Ring");
  3643. dp_print_ring_stat_from_hal(pdev->soc,
  3644. &pdev->rxdma_mon_status_ring,
  3645. "Rxdma Mon Status Ring");
  3646. dp_print_ring_stat_from_hal(pdev->soc,
  3647. &pdev->rxdma_mon_desc_ring,
  3648. "Rxdma mon desc Ring");
  3649. dp_print_ring_stat_from_hal(pdev->soc,
  3650. &pdev->rxdma_err_dst_ring,
  3651. "Rxdma err dst ring");
  3652. for (i = 0; i < MAX_RX_MAC_RINGS; i++) {
  3653. snprintf(ring_name, STR_MAXLEN, "Rx mac buf ring %d", i);
  3654. dp_print_ring_stat_from_hal(pdev->soc,
  3655. &pdev->rx_mac_buf_ring[i],
  3656. ring_name);
  3657. }
  3658. }
  3659. /**
  3660. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3661. * @vdev: DP_VDEV handle
  3662. *
  3663. * Return:void
  3664. */
  3665. static inline void
  3666. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3667. {
  3668. struct dp_peer *peer = NULL;
  3669. DP_STATS_CLR(vdev->pdev);
  3670. DP_STATS_CLR(vdev->pdev->soc);
  3671. DP_STATS_CLR(vdev);
  3672. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3673. if (!peer)
  3674. return;
  3675. DP_STATS_CLR(peer);
  3676. }
  3677. }
  3678. /**
  3679. * dp_print_rx_rates(): Print Rx rate stats
  3680. * @vdev: DP_VDEV handle
  3681. *
  3682. * Return:void
  3683. */
  3684. static inline void
  3685. dp_print_rx_rates(struct dp_vdev *vdev)
  3686. {
  3687. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3688. uint8_t i, mcs, pkt_type;
  3689. uint8_t index = 0;
  3690. char nss[DP_NSS_LENGTH];
  3691. DP_PRINT_STATS("Rx Rate Info:\n");
  3692. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3693. index = 0;
  3694. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3695. if (!dp_rate_string[pkt_type][mcs].valid)
  3696. continue;
  3697. DP_PRINT_STATS(" %s = %d",
  3698. dp_rate_string[pkt_type][mcs].mcs_type,
  3699. pdev->stats.rx.pkt_type[pkt_type].
  3700. mcs_count[mcs]);
  3701. }
  3702. DP_PRINT_STATS("\n");
  3703. }
  3704. index = 0;
  3705. for (i = 0; i < SS_COUNT; i++) {
  3706. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3707. " %d", pdev->stats.rx.nss[i]);
  3708. }
  3709. DP_PRINT_STATS("NSS(0-7) = %s",
  3710. nss);
  3711. DP_PRINT_STATS("SGI ="
  3712. " 0.8us %d,"
  3713. " 0.4us %d,"
  3714. " 1.6us %d,"
  3715. " 3.2us %d,",
  3716. pdev->stats.rx.sgi_count[0],
  3717. pdev->stats.rx.sgi_count[1],
  3718. pdev->stats.rx.sgi_count[2],
  3719. pdev->stats.rx.sgi_count[3]);
  3720. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3721. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3722. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3723. DP_PRINT_STATS("Reception Type ="
  3724. " SU: %d,"
  3725. " MU_MIMO:%d,"
  3726. " MU_OFDMA:%d,"
  3727. " MU_OFDMA_MIMO:%d\n",
  3728. pdev->stats.rx.reception_type[0],
  3729. pdev->stats.rx.reception_type[1],
  3730. pdev->stats.rx.reception_type[2],
  3731. pdev->stats.rx.reception_type[3]);
  3732. DP_PRINT_STATS("Aggregation:\n");
  3733. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3734. pdev->stats.rx.ampdu_cnt);
  3735. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3736. pdev->stats.rx.non_ampdu_cnt);
  3737. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3738. pdev->stats.rx.amsdu_cnt);
  3739. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3740. pdev->stats.rx.non_amsdu_cnt);
  3741. }
  3742. /**
  3743. * dp_print_tx_rates(): Print tx rates
  3744. * @vdev: DP_VDEV handle
  3745. *
  3746. * Return:void
  3747. */
  3748. static inline void
  3749. dp_print_tx_rates(struct dp_vdev *vdev)
  3750. {
  3751. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3752. uint8_t mcs, pkt_type;
  3753. uint32_t index;
  3754. DP_PRINT_STATS("Tx Rate Info:\n");
  3755. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3756. index = 0;
  3757. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3758. if (!dp_rate_string[pkt_type][mcs].valid)
  3759. continue;
  3760. DP_PRINT_STATS(" %s = %d",
  3761. dp_rate_string[pkt_type][mcs].mcs_type,
  3762. pdev->stats.tx.pkt_type[pkt_type].
  3763. mcs_count[mcs]);
  3764. }
  3765. DP_PRINT_STATS("\n");
  3766. }
  3767. DP_PRINT_STATS("SGI ="
  3768. " 0.8us %d"
  3769. " 0.4us %d"
  3770. " 1.6us %d"
  3771. " 3.2us %d",
  3772. pdev->stats.tx.sgi_count[0],
  3773. pdev->stats.tx.sgi_count[1],
  3774. pdev->stats.tx.sgi_count[2],
  3775. pdev->stats.tx.sgi_count[3]);
  3776. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3777. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3778. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3779. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3780. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3781. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3782. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3783. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3784. DP_PRINT_STATS("Aggregation:\n");
  3785. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3786. pdev->stats.tx.amsdu_cnt);
  3787. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3788. pdev->stats.tx.non_amsdu_cnt);
  3789. }
  3790. /**
  3791. * dp_print_peer_stats():print peer stats
  3792. * @peer: DP_PEER handle
  3793. *
  3794. * return void
  3795. */
  3796. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3797. {
  3798. uint8_t i, mcs, pkt_type;
  3799. uint32_t index;
  3800. char nss[DP_NSS_LENGTH];
  3801. DP_PRINT_STATS("Node Tx Stats:\n");
  3802. DP_PRINT_STATS("Total Packet Completions = %d",
  3803. peer->stats.tx.comp_pkt.num);
  3804. DP_PRINT_STATS("Total Bytes Completions = %d",
  3805. peer->stats.tx.comp_pkt.bytes);
  3806. DP_PRINT_STATS("Success Packets = %d",
  3807. peer->stats.tx.tx_success.num);
  3808. DP_PRINT_STATS("Success Bytes = %d",
  3809. peer->stats.tx.tx_success.bytes);
  3810. DP_PRINT_STATS("Packets Failed = %d",
  3811. peer->stats.tx.tx_failed);
  3812. DP_PRINT_STATS("Packets In OFDMA = %d",
  3813. peer->stats.tx.ofdma);
  3814. DP_PRINT_STATS("Packets In STBC = %d",
  3815. peer->stats.tx.stbc);
  3816. DP_PRINT_STATS("Packets In LDPC = %d",
  3817. peer->stats.tx.ldpc);
  3818. DP_PRINT_STATS("Packet Retries = %d",
  3819. peer->stats.tx.retries);
  3820. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3821. peer->stats.tx.amsdu_cnt);
  3822. DP_PRINT_STATS("Last Packet RSSI = %d",
  3823. peer->stats.tx.last_ack_rssi);
  3824. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3825. peer->stats.tx.dropped.fw_rem);
  3826. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3827. peer->stats.tx.dropped.fw_rem_tx);
  3828. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3829. peer->stats.tx.dropped.fw_rem_notx);
  3830. DP_PRINT_STATS("Dropped : Age Out = %d",
  3831. peer->stats.tx.dropped.age_out);
  3832. DP_PRINT_STATS("Rate Info:");
  3833. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3834. index = 0;
  3835. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3836. if (!dp_rate_string[pkt_type][mcs].valid)
  3837. continue;
  3838. DP_PRINT_STATS(" %s = %d",
  3839. dp_rate_string[pkt_type][mcs].mcs_type,
  3840. peer->stats.tx.pkt_type[pkt_type].
  3841. mcs_count[mcs]);
  3842. }
  3843. DP_PRINT_STATS("\n");
  3844. }
  3845. DP_PRINT_STATS("SGI = "
  3846. " 0.8us %d"
  3847. " 0.4us %d"
  3848. " 1.6us %d"
  3849. " 3.2us %d",
  3850. peer->stats.tx.sgi_count[0],
  3851. peer->stats.tx.sgi_count[1],
  3852. peer->stats.tx.sgi_count[2],
  3853. peer->stats.tx.sgi_count[3]);
  3854. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3855. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3856. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3857. DP_PRINT_STATS("Aggregation:");
  3858. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3859. peer->stats.tx.amsdu_cnt);
  3860. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3861. peer->stats.tx.non_amsdu_cnt);
  3862. DP_PRINT_STATS("Node Rx Stats:");
  3863. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3864. peer->stats.rx.to_stack.num);
  3865. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3866. peer->stats.rx.to_stack.bytes);
  3867. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3868. DP_PRINT_STATS("Packets Received = %d",
  3869. peer->stats.rx.rcvd_reo[i].num);
  3870. DP_PRINT_STATS("Bytes Received = %d",
  3871. peer->stats.rx.rcvd_reo[i].bytes);
  3872. }
  3873. DP_PRINT_STATS("Multicast Packets Received = %d",
  3874. peer->stats.rx.multicast.num);
  3875. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3876. peer->stats.rx.multicast.bytes);
  3877. DP_PRINT_STATS("WDS Packets Received = %d",
  3878. peer->stats.rx.wds.num);
  3879. DP_PRINT_STATS("WDS Bytes Received = %d",
  3880. peer->stats.rx.wds.bytes);
  3881. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3882. peer->stats.rx.intra_bss.pkts.num);
  3883. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3884. peer->stats.rx.intra_bss.pkts.bytes);
  3885. DP_PRINT_STATS("Raw Packets Received = %d",
  3886. peer->stats.rx.raw.num);
  3887. DP_PRINT_STATS("Raw Bytes Received = %d",
  3888. peer->stats.rx.raw.bytes);
  3889. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3890. peer->stats.rx.err.mic_err);
  3891. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3892. peer->stats.rx.err.decrypt_err);
  3893. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3894. peer->stats.rx.non_ampdu_cnt);
  3895. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3896. peer->stats.rx.ampdu_cnt);
  3897. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3898. peer->stats.rx.non_amsdu_cnt);
  3899. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3900. peer->stats.rx.amsdu_cnt);
  3901. DP_PRINT_STATS("SGI ="
  3902. " 0.8us %d"
  3903. " 0.4us %d"
  3904. " 1.6us %d"
  3905. " 3.2us %d",
  3906. peer->stats.rx.sgi_count[0],
  3907. peer->stats.rx.sgi_count[1],
  3908. peer->stats.rx.sgi_count[2],
  3909. peer->stats.rx.sgi_count[3]);
  3910. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3911. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3912. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3913. DP_PRINT_STATS("Reception Type ="
  3914. " SU %d,"
  3915. " MU_MIMO %d,"
  3916. " MU_OFDMA %d,"
  3917. " MU_OFDMA_MIMO %d",
  3918. peer->stats.rx.reception_type[0],
  3919. peer->stats.rx.reception_type[1],
  3920. peer->stats.rx.reception_type[2],
  3921. peer->stats.rx.reception_type[3]);
  3922. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3923. index = 0;
  3924. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3925. if (!dp_rate_string[pkt_type][mcs].valid)
  3926. continue;
  3927. DP_PRINT_STATS(" %s = %d",
  3928. dp_rate_string[pkt_type][mcs].mcs_type,
  3929. peer->stats.rx.pkt_type[pkt_type].
  3930. mcs_count[mcs]);
  3931. }
  3932. DP_PRINT_STATS("\n");
  3933. }
  3934. index = 0;
  3935. for (i = 0; i < SS_COUNT; i++) {
  3936. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3937. " %d", peer->stats.rx.nss[i]);
  3938. }
  3939. DP_PRINT_STATS("NSS(0-7) = %s",
  3940. nss);
  3941. DP_PRINT_STATS("Aggregation:");
  3942. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3943. peer->stats.rx.ampdu_cnt);
  3944. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3945. peer->stats.rx.non_ampdu_cnt);
  3946. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3947. peer->stats.rx.amsdu_cnt);
  3948. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3949. peer->stats.rx.non_amsdu_cnt);
  3950. }
  3951. /**
  3952. * dp_print_host_stats()- Function to print the stats aggregated at host
  3953. * @vdev_handle: DP_VDEV handle
  3954. * @type: host stats type
  3955. *
  3956. * Available Stat types
  3957. * TXRX_CLEAR_STATS : Clear the stats
  3958. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3959. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3960. * TXRX_TX_HOST_STATS: Print Tx Stats
  3961. * TXRX_RX_HOST_STATS: Print Rx Stats
  3962. * TXRX_AST_STATS: Print AST Stats
  3963. * TXRX_SRNG_PTR_STATS: Print SRNG ring pointer stats
  3964. *
  3965. * Return: 0 on success, print error message in case of failure
  3966. */
  3967. static int
  3968. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3969. {
  3970. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3971. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3972. dp_aggregate_pdev_stats(pdev);
  3973. switch (type) {
  3974. case TXRX_CLEAR_STATS:
  3975. dp_txrx_host_stats_clr(vdev);
  3976. break;
  3977. case TXRX_RX_RATE_STATS:
  3978. dp_print_rx_rates(vdev);
  3979. break;
  3980. case TXRX_TX_RATE_STATS:
  3981. dp_print_tx_rates(vdev);
  3982. break;
  3983. case TXRX_TX_HOST_STATS:
  3984. dp_print_pdev_tx_stats(pdev);
  3985. dp_print_soc_tx_stats(pdev->soc);
  3986. break;
  3987. case TXRX_RX_HOST_STATS:
  3988. dp_print_pdev_rx_stats(pdev);
  3989. dp_print_soc_rx_stats(pdev->soc);
  3990. break;
  3991. case TXRX_AST_STATS:
  3992. dp_print_ast_stats(pdev->soc);
  3993. break;
  3994. case TXRX_SRNG_PTR_STATS:
  3995. dp_print_ring_stats(pdev);
  3996. break;
  3997. default:
  3998. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3999. break;
  4000. }
  4001. return 0;
  4002. }
  4003. /*
  4004. * dp_get_host_peer_stats()- function to print peer stats
  4005. * @pdev_handle: DP_PDEV handle
  4006. * @mac_addr: mac address of the peer
  4007. *
  4008. * Return: void
  4009. */
  4010. static void
  4011. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  4012. {
  4013. struct dp_peer *peer;
  4014. uint8_t local_id;
  4015. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  4016. &local_id);
  4017. if (!peer) {
  4018. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  4019. "%s: Invalid peer\n", __func__);
  4020. return;
  4021. }
  4022. dp_print_peer_stats(peer);
  4023. dp_peer_rxtid_stats(peer);
  4024. return;
  4025. }
  4026. /*
  4027. * dp_ppdu_ring_cfg()- Configure PPDU Stats ring
  4028. * @pdev: DP_PDEV handle
  4029. *
  4030. * Return: void
  4031. */
  4032. static void
  4033. dp_ppdu_ring_cfg(struct dp_pdev *pdev)
  4034. {
  4035. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4036. htt_tlv_filter.mpdu_start = 0;
  4037. htt_tlv_filter.msdu_start = 0;
  4038. htt_tlv_filter.packet = 0;
  4039. htt_tlv_filter.msdu_end = 0;
  4040. htt_tlv_filter.mpdu_end = 0;
  4041. htt_tlv_filter.packet_header = 1;
  4042. htt_tlv_filter.attention = 1;
  4043. htt_tlv_filter.ppdu_start = 1;
  4044. htt_tlv_filter.ppdu_end = 1;
  4045. htt_tlv_filter.ppdu_end_user_stats = 1;
  4046. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4047. htt_tlv_filter.ppdu_end_status_done = 1;
  4048. htt_tlv_filter.enable_fp = 1;
  4049. htt_tlv_filter.enable_md = 0;
  4050. htt_tlv_filter.enable_mo = 0;
  4051. htt_h2t_rx_ring_cfg(pdev->soc->htt_handle, pdev->pdev_id,
  4052. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  4053. RX_BUFFER_SIZE, &htt_tlv_filter);
  4054. }
  4055. /*
  4056. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  4057. * @pdev_handle: DP_PDEV handle
  4058. *
  4059. * Return: void
  4060. */
  4061. static void
  4062. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4063. {
  4064. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4065. pdev->enhanced_stats_en = 1;
  4066. dp_ppdu_ring_cfg(pdev);
  4067. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4068. }
  4069. /*
  4070. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  4071. * @pdev_handle: DP_PDEV handle
  4072. *
  4073. * Return: void
  4074. */
  4075. static void
  4076. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  4077. {
  4078. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4079. pdev->enhanced_stats_en = 0;
  4080. }
  4081. /*
  4082. * dp_get_fw_peer_stats()- function to print peer stats
  4083. * @pdev_handle: DP_PDEV handle
  4084. * @mac_addr: mac address of the peer
  4085. * @cap: Type of htt stats requested
  4086. *
  4087. * Currently Supporting only MAC ID based requests Only
  4088. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  4089. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  4090. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  4091. *
  4092. * Return: void
  4093. */
  4094. static void
  4095. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  4096. uint32_t cap)
  4097. {
  4098. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  4099. uint32_t config_param0 = 0;
  4100. uint32_t config_param1 = 0;
  4101. uint32_t config_param2 = 0;
  4102. uint32_t config_param3 = 0;
  4103. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  4104. config_param0 |= (1 << (cap + 1));
  4105. config_param1 = 0x8f;
  4106. config_param2 |= (mac_addr[0] & 0x000000ff);
  4107. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  4108. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  4109. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  4110. config_param3 |= (mac_addr[4] & 0x000000ff);
  4111. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  4112. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  4113. config_param0, config_param1, config_param2,
  4114. config_param3);
  4115. }
  4116. /*
  4117. * dp_set_vdev_param: function to set parameters in vdev
  4118. * @param: parameter type to be set
  4119. * @val: value of parameter to be set
  4120. *
  4121. * return: void
  4122. */
  4123. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  4124. enum cdp_vdev_param_type param, uint32_t val)
  4125. {
  4126. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4127. switch (param) {
  4128. case CDP_ENABLE_WDS:
  4129. vdev->wds_enabled = val;
  4130. break;
  4131. case CDP_ENABLE_NAWDS:
  4132. vdev->nawds_enabled = val;
  4133. break;
  4134. case CDP_ENABLE_MCAST_EN:
  4135. vdev->mcast_enhancement_en = val;
  4136. break;
  4137. case CDP_ENABLE_PROXYSTA:
  4138. vdev->proxysta_vdev = val;
  4139. break;
  4140. case CDP_UPDATE_TDLS_FLAGS:
  4141. vdev->tdls_link_connected = val;
  4142. break;
  4143. case CDP_CFG_WDS_AGING_TIMER:
  4144. if (val == 0)
  4145. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  4146. else if (val != vdev->wds_aging_timer_val)
  4147. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  4148. vdev->wds_aging_timer_val = val;
  4149. break;
  4150. case CDP_ENABLE_AP_BRIDGE:
  4151. if (wlan_op_mode_sta != vdev->opmode)
  4152. vdev->ap_bridge_enabled = val;
  4153. else
  4154. vdev->ap_bridge_enabled = false;
  4155. break;
  4156. default:
  4157. break;
  4158. }
  4159. dp_tx_vdev_update_search_flags(vdev);
  4160. }
  4161. /**
  4162. * dp_peer_set_nawds: set nawds bit in peer
  4163. * @peer_handle: pointer to peer
  4164. * @value: enable/disable nawds
  4165. *
  4166. * return: void
  4167. */
  4168. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4169. {
  4170. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4171. peer->nawds_enabled = value;
  4172. }
  4173. /*
  4174. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4175. * @vdev_handle: DP_VDEV handle
  4176. * @map_id:ID of map that needs to be updated
  4177. *
  4178. * Return: void
  4179. */
  4180. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4181. uint8_t map_id)
  4182. {
  4183. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4184. vdev->dscp_tid_map_id = map_id;
  4185. return;
  4186. }
  4187. /**
  4188. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4189. * @pdev: DP_PDEV handle
  4190. * @map_id: ID of map that needs to be updated
  4191. * @tos: index value in map
  4192. * @tid: tid value passed by the user
  4193. *
  4194. * Return: void
  4195. */
  4196. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4197. uint8_t map_id, uint8_t tos, uint8_t tid)
  4198. {
  4199. uint8_t dscp;
  4200. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4201. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4202. pdev->dscp_tid_map[map_id][dscp] = tid;
  4203. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4204. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4205. map_id, dscp);
  4206. return;
  4207. }
  4208. /**
  4209. * dp_fw_stats_process(): Process TxRX FW stats request
  4210. * @vdev_handle: DP VDEV handle
  4211. * @val: value passed by user
  4212. *
  4213. * return: int
  4214. */
  4215. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4216. {
  4217. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4218. struct dp_pdev *pdev = NULL;
  4219. if (!vdev) {
  4220. DP_TRACE(NONE, "VDEV not found");
  4221. return 1;
  4222. }
  4223. pdev = vdev->pdev;
  4224. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4225. }
  4226. /*
  4227. * dp_txrx_stats() - function to map to firmware and host stats
  4228. * @vdev: virtual handle
  4229. * @stats: type of statistics requested
  4230. *
  4231. * Return: integer
  4232. */
  4233. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4234. {
  4235. int host_stats;
  4236. int fw_stats;
  4237. if (stats >= CDP_TXRX_MAX_STATS)
  4238. return 0;
  4239. /*
  4240. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4241. * has to be updated if new FW HTT stats added
  4242. */
  4243. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4244. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4245. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4246. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4247. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4248. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4249. stats, fw_stats, host_stats);
  4250. if (fw_stats != TXRX_FW_STATS_INVALID)
  4251. return dp_fw_stats_process(vdev, fw_stats);
  4252. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4253. (host_stats <= TXRX_HOST_STATS_MAX))
  4254. return dp_print_host_stats(vdev, host_stats);
  4255. else
  4256. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4257. "Wrong Input for TxRx Stats");
  4258. return 0;
  4259. }
  4260. /*
  4261. * dp_print_napi_stats(): NAPI stats
  4262. * @soc - soc handle
  4263. */
  4264. static void dp_print_napi_stats(struct dp_soc *soc)
  4265. {
  4266. hif_print_napi_stats(soc->hif_handle);
  4267. }
  4268. /*
  4269. * dp_print_per_ring_stats(): Packet count per ring
  4270. * @soc - soc handle
  4271. */
  4272. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4273. {
  4274. uint8_t core, ring;
  4275. uint64_t total_packets;
  4276. DP_TRACE(FATAL, "Reo packets per ring:");
  4277. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4278. total_packets = 0;
  4279. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4280. for (core = 0; core < NR_CPUS; core++) {
  4281. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4282. core, soc->stats.rx.ring_packets[core][ring]);
  4283. total_packets += soc->stats.rx.ring_packets[core][ring];
  4284. }
  4285. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4286. ring, total_packets);
  4287. }
  4288. }
  4289. /*
  4290. * dp_txrx_path_stats() - Function to display dump stats
  4291. * @soc - soc handle
  4292. *
  4293. * return: none
  4294. */
  4295. static void dp_txrx_path_stats(struct dp_soc *soc)
  4296. {
  4297. uint8_t error_code;
  4298. uint8_t loop_pdev;
  4299. struct dp_pdev *pdev;
  4300. uint8_t i;
  4301. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4302. pdev = soc->pdev_list[loop_pdev];
  4303. dp_aggregate_pdev_stats(pdev);
  4304. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4305. "Tx path Statistics:");
  4306. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4307. pdev->stats.tx_i.rcvd.num,
  4308. pdev->stats.tx_i.rcvd.bytes);
  4309. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4310. pdev->stats.tx_i.processed.num,
  4311. pdev->stats.tx_i.processed.bytes);
  4312. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4313. pdev->stats.tx.tx_success.num,
  4314. pdev->stats.tx.tx_success.bytes);
  4315. DP_TRACE(FATAL, "Dropped in host:");
  4316. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4317. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4318. DP_TRACE(FATAL, "Descriptor not available: %u",
  4319. pdev->stats.tx_i.dropped.desc_na);
  4320. DP_TRACE(FATAL, "Ring full: %u",
  4321. pdev->stats.tx_i.dropped.ring_full);
  4322. DP_TRACE(FATAL, "Enqueue fail: %u",
  4323. pdev->stats.tx_i.dropped.enqueue_fail);
  4324. DP_TRACE(FATAL, "DMA Error: %u",
  4325. pdev->stats.tx_i.dropped.dma_error);
  4326. DP_TRACE(FATAL, "Dropped in hardware:");
  4327. DP_TRACE(FATAL, "total packets dropped: %u",
  4328. pdev->stats.tx.tx_failed);
  4329. DP_TRACE(FATAL, "mpdu age out: %u",
  4330. pdev->stats.tx.dropped.age_out);
  4331. DP_TRACE(FATAL, "firmware removed: %u",
  4332. pdev->stats.tx.dropped.fw_rem);
  4333. DP_TRACE(FATAL, "firmware removed tx: %u",
  4334. pdev->stats.tx.dropped.fw_rem_tx);
  4335. DP_TRACE(FATAL, "firmware removed notx %u",
  4336. pdev->stats.tx.dropped.fw_rem_notx);
  4337. DP_TRACE(FATAL, "peer_invalid: %u",
  4338. pdev->soc->stats.tx.tx_invalid_peer.num);
  4339. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4340. DP_TRACE(FATAL, "Single Packet: %u",
  4341. pdev->stats.tx_comp_histogram.pkts_1);
  4342. DP_TRACE(FATAL, "2-20 Packets: %u",
  4343. pdev->stats.tx_comp_histogram.pkts_2_20);
  4344. DP_TRACE(FATAL, "21-40 Packets: %u",
  4345. pdev->stats.tx_comp_histogram.pkts_21_40);
  4346. DP_TRACE(FATAL, "41-60 Packets: %u",
  4347. pdev->stats.tx_comp_histogram.pkts_41_60);
  4348. DP_TRACE(FATAL, "61-80 Packets: %u",
  4349. pdev->stats.tx_comp_histogram.pkts_61_80);
  4350. DP_TRACE(FATAL, "81-100 Packets: %u",
  4351. pdev->stats.tx_comp_histogram.pkts_81_100);
  4352. DP_TRACE(FATAL, "101-200 Packets: %u",
  4353. pdev->stats.tx_comp_histogram.pkts_101_200);
  4354. DP_TRACE(FATAL, " 201+ Packets: %u",
  4355. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4356. DP_TRACE(FATAL, "Rx path statistics");
  4357. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4358. pdev->stats.rx.to_stack.num,
  4359. pdev->stats.rx.to_stack.bytes);
  4360. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4361. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4362. i, pdev->stats.rx.rcvd_reo[i].num,
  4363. pdev->stats.rx.rcvd_reo[i].bytes);
  4364. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4365. pdev->stats.rx.intra_bss.pkts.num,
  4366. pdev->stats.rx.intra_bss.pkts.bytes);
  4367. DP_TRACE(FATAL, "intra-bss fails %u msdus ( %u bytes),",
  4368. pdev->stats.rx.intra_bss.fail.num,
  4369. pdev->stats.rx.intra_bss.fail.bytes);
  4370. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4371. pdev->stats.rx.raw.num,
  4372. pdev->stats.rx.raw.bytes);
  4373. DP_TRACE(FATAL, "dropped: error %u msdus",
  4374. pdev->stats.rx.err.mic_err);
  4375. DP_TRACE(FATAL, "peer invalid %u",
  4376. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4377. DP_TRACE(FATAL, "Reo Statistics");
  4378. DP_TRACE(FATAL, "rbm error: %u msdus",
  4379. pdev->soc->stats.rx.err.invalid_rbm);
  4380. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4381. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4382. DP_TRACE(FATAL, "Reo errors");
  4383. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4384. error_code++) {
  4385. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4386. error_code,
  4387. pdev->soc->stats.rx.err.reo_error[error_code]);
  4388. }
  4389. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4390. error_code++) {
  4391. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4392. error_code,
  4393. pdev->soc->stats.rx.err
  4394. .rxdma_error[error_code]);
  4395. }
  4396. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4397. DP_TRACE(FATAL, "Single Packet: %u",
  4398. pdev->stats.rx_ind_histogram.pkts_1);
  4399. DP_TRACE(FATAL, "2-20 Packets: %u",
  4400. pdev->stats.rx_ind_histogram.pkts_2_20);
  4401. DP_TRACE(FATAL, "21-40 Packets: %u",
  4402. pdev->stats.rx_ind_histogram.pkts_21_40);
  4403. DP_TRACE(FATAL, "41-60 Packets: %u",
  4404. pdev->stats.rx_ind_histogram.pkts_41_60);
  4405. DP_TRACE(FATAL, "61-80 Packets: %u",
  4406. pdev->stats.rx_ind_histogram.pkts_61_80);
  4407. DP_TRACE(FATAL, "81-100 Packets: %u",
  4408. pdev->stats.rx_ind_histogram.pkts_81_100);
  4409. DP_TRACE(FATAL, "101-200 Packets: %u",
  4410. pdev->stats.rx_ind_histogram.pkts_101_200);
  4411. DP_TRACE(FATAL, " 201+ Packets: %u",
  4412. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4413. }
  4414. }
  4415. /*
  4416. * dp_txrx_dump_stats() - Dump statistics
  4417. * @value - Statistics option
  4418. */
  4419. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4420. {
  4421. struct dp_soc *soc =
  4422. (struct dp_soc *)psoc;
  4423. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4424. if (!soc) {
  4425. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4426. "%s: soc is NULL", __func__);
  4427. return QDF_STATUS_E_INVAL;
  4428. }
  4429. switch (value) {
  4430. case CDP_TXRX_PATH_STATS:
  4431. dp_txrx_path_stats(soc);
  4432. break;
  4433. case CDP_RX_RING_STATS:
  4434. dp_print_per_ring_stats(soc);
  4435. break;
  4436. case CDP_TXRX_TSO_STATS:
  4437. /* TODO: NOT IMPLEMENTED */
  4438. break;
  4439. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4440. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4441. break;
  4442. case CDP_DP_NAPI_STATS:
  4443. dp_print_napi_stats(soc);
  4444. break;
  4445. case CDP_TXRX_DESC_STATS:
  4446. /* TODO: NOT IMPLEMENTED */
  4447. break;
  4448. default:
  4449. status = QDF_STATUS_E_INVAL;
  4450. break;
  4451. }
  4452. return status;
  4453. }
  4454. static struct cdp_wds_ops dp_ops_wds = {
  4455. .vdev_set_wds = dp_vdev_set_wds,
  4456. };
  4457. /*
  4458. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4459. * @soc - datapath soc handle
  4460. * @peer - datapath peer handle
  4461. *
  4462. * Delete the AST entries belonging to a peer
  4463. */
  4464. #ifdef FEATURE_WDS
  4465. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4466. struct dp_peer *peer)
  4467. {
  4468. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4469. qdf_spin_lock_bh(&soc->ast_lock);
  4470. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4471. if (ast_entry->next_hop) {
  4472. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4473. peer->vdev->pdev->osif_pdev,
  4474. ast_entry->mac_addr.raw);
  4475. }
  4476. dp_peer_del_ast(soc, ast_entry);
  4477. }
  4478. qdf_spin_unlock_bh(&soc->ast_lock);
  4479. }
  4480. #else
  4481. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4482. struct dp_peer *peer)
  4483. {
  4484. }
  4485. #endif
  4486. /*
  4487. * dp_txrx_data_tx_cb_set(): set the callback for non standard tx
  4488. * @vdev_handle - datapath vdev handle
  4489. * @callback - callback function
  4490. * @ctxt: callback context
  4491. *
  4492. */
  4493. static void
  4494. dp_txrx_data_tx_cb_set(struct cdp_vdev *vdev_handle,
  4495. ol_txrx_data_tx_cb callback, void *ctxt)
  4496. {
  4497. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4498. vdev->tx_non_std_data_callback.func = callback;
  4499. vdev->tx_non_std_data_callback.ctxt = ctxt;
  4500. }
  4501. #ifdef CONFIG_WIN
  4502. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4503. {
  4504. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4505. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4506. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4507. dp_peer_delete_ast_entries(soc, peer);
  4508. }
  4509. #endif
  4510. static struct cdp_cmn_ops dp_ops_cmn = {
  4511. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4512. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4513. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4514. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4515. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4516. .txrx_peer_create = dp_peer_create_wifi3,
  4517. .txrx_peer_setup = dp_peer_setup_wifi3,
  4518. #ifdef CONFIG_WIN
  4519. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4520. #else
  4521. .txrx_peer_teardown = NULL,
  4522. #endif
  4523. .txrx_peer_delete = dp_peer_delete_wifi3,
  4524. .txrx_vdev_register = dp_vdev_register_wifi3,
  4525. .txrx_soc_detach = dp_soc_detach_wifi3,
  4526. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4527. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4528. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4529. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4530. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4531. .delba_process = dp_delba_process_wifi3,
  4532. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4533. .flush_cache_rx_queue = NULL,
  4534. /* TODO: get API's for dscp-tid need to be added*/
  4535. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4536. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4537. .txrx_stats = dp_txrx_stats,
  4538. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4539. .display_stats = dp_txrx_dump_stats,
  4540. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4541. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4542. #ifdef DP_INTR_POLL_BASED
  4543. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4544. #else
  4545. .txrx_intr_attach = dp_soc_interrupt_attach,
  4546. #endif
  4547. .txrx_intr_detach = dp_soc_interrupt_detach,
  4548. .set_pn_check = dp_set_pn_check_wifi3,
  4549. /* TODO: Add other functions */
  4550. .txrx_data_tx_cb_set = dp_txrx_data_tx_cb_set
  4551. };
  4552. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4553. .txrx_peer_authorize = dp_peer_authorize,
  4554. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4555. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4556. #ifdef MESH_MODE_SUPPORT
  4557. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4558. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4559. #endif
  4560. .txrx_set_vdev_param = dp_set_vdev_param,
  4561. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4562. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4563. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4564. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4565. .txrx_update_filter_neighbour_peers =
  4566. dp_update_filter_neighbour_peers,
  4567. .txrx_get_sec_type = dp_get_sec_type,
  4568. /* TODO: Add other functions */
  4569. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4570. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4571. };
  4572. static struct cdp_me_ops dp_ops_me = {
  4573. #ifdef ATH_SUPPORT_IQUE
  4574. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4575. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4576. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4577. #endif
  4578. };
  4579. static struct cdp_mon_ops dp_ops_mon = {
  4580. .txrx_monitor_set_filter_ucast_data = NULL,
  4581. .txrx_monitor_set_filter_mcast_data = NULL,
  4582. .txrx_monitor_set_filter_non_data = NULL,
  4583. .txrx_monitor_get_filter_ucast_data = NULL,
  4584. .txrx_monitor_get_filter_mcast_data = NULL,
  4585. .txrx_monitor_get_filter_non_data = NULL,
  4586. .txrx_reset_monitor_mode = dp_reset_monitor_mode,
  4587. };
  4588. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4589. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4590. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4591. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4592. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4593. /* TODO */
  4594. };
  4595. static struct cdp_raw_ops dp_ops_raw = {
  4596. /* TODO */
  4597. };
  4598. #ifdef CONFIG_WIN
  4599. static struct cdp_pflow_ops dp_ops_pflow = {
  4600. /* TODO */
  4601. };
  4602. #endif /* CONFIG_WIN */
  4603. #ifdef FEATURE_RUNTIME_PM
  4604. /**
  4605. * dp_runtime_suspend() - ensure DP is ready to runtime suspend
  4606. * @opaque_pdev: DP pdev context
  4607. *
  4608. * DP is ready to runtime suspend if there are no pending TX packets.
  4609. *
  4610. * Return: QDF_STATUS
  4611. */
  4612. static QDF_STATUS dp_runtime_suspend(struct cdp_pdev *opaque_pdev)
  4613. {
  4614. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4615. struct dp_soc *soc = pdev->soc;
  4616. /* Call DP TX flow control API to check if there is any
  4617. pending packets */
  4618. if (soc->intr_mode == DP_INTR_POLL)
  4619. qdf_timer_stop(&soc->int_timer);
  4620. return QDF_STATUS_SUCCESS;
  4621. }
  4622. /**
  4623. * dp_runtime_resume() - ensure DP is ready to runtime resume
  4624. * @opaque_pdev: DP pdev context
  4625. *
  4626. * Resume DP for runtime PM.
  4627. *
  4628. * Return: QDF_STATUS
  4629. */
  4630. static QDF_STATUS dp_runtime_resume(struct cdp_pdev *opaque_pdev)
  4631. {
  4632. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4633. struct dp_soc *soc = pdev->soc;
  4634. void *hal_srng;
  4635. int i;
  4636. if (soc->intr_mode == DP_INTR_POLL)
  4637. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4638. for (i = 0; i < MAX_TCL_DATA_RINGS; i++) {
  4639. hal_srng = soc->tcl_data_ring[i].hal_srng;
  4640. if (hal_srng) {
  4641. /* We actually only need to acquire the lock */
  4642. hal_srng_access_start(soc->hal_soc, hal_srng);
  4643. /* Update SRC ring head pointer for HW to send
  4644. all pending packets */
  4645. hal_srng_access_end(soc->hal_soc, hal_srng);
  4646. }
  4647. }
  4648. return QDF_STATUS_SUCCESS;
  4649. }
  4650. #endif /* FEATURE_RUNTIME_PM */
  4651. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4652. {
  4653. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4654. struct dp_soc *soc = pdev->soc;
  4655. if (soc->intr_mode == DP_INTR_POLL)
  4656. qdf_timer_stop(&soc->int_timer);
  4657. return QDF_STATUS_SUCCESS;
  4658. }
  4659. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4660. {
  4661. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4662. struct dp_soc *soc = pdev->soc;
  4663. if (soc->intr_mode == DP_INTR_POLL)
  4664. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4665. return QDF_STATUS_SUCCESS;
  4666. }
  4667. #ifndef CONFIG_WIN
  4668. static struct cdp_misc_ops dp_ops_misc = {
  4669. .tx_non_std = dp_tx_non_std,
  4670. .get_opmode = dp_get_opmode,
  4671. #ifdef FEATURE_RUNTIME_PM
  4672. .runtime_suspend = dp_runtime_suspend,
  4673. .runtime_resume = dp_runtime_resume,
  4674. #endif /* FEATURE_RUNTIME_PM */
  4675. };
  4676. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4677. /* WIFI 3.0 DP implement as required. */
  4678. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4679. .register_pause_cb = dp_txrx_register_pause_cb,
  4680. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4681. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4682. };
  4683. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4684. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4685. };
  4686. #ifdef IPA_OFFLOAD
  4687. static struct cdp_ipa_ops dp_ops_ipa = {
  4688. .ipa_get_resource = dp_ipa_get_resource,
  4689. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4690. .ipa_op_response = dp_ipa_op_response,
  4691. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4692. .ipa_get_stat = dp_ipa_get_stat,
  4693. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4694. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4695. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4696. .ipa_setup = dp_ipa_setup,
  4697. .ipa_cleanup = dp_ipa_cleanup,
  4698. .ipa_setup_iface = dp_ipa_setup_iface,
  4699. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4700. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4701. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4702. .ipa_set_perf_level = dp_ipa_set_perf_level
  4703. };
  4704. #endif
  4705. static struct cdp_bus_ops dp_ops_bus = {
  4706. .bus_suspend = dp_bus_suspend,
  4707. .bus_resume = dp_bus_resume
  4708. };
  4709. static struct cdp_ocb_ops dp_ops_ocb = {
  4710. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4711. };
  4712. static struct cdp_throttle_ops dp_ops_throttle = {
  4713. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4714. };
  4715. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4716. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4717. };
  4718. static struct cdp_cfg_ops dp_ops_cfg = {
  4719. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4720. };
  4721. static struct cdp_peer_ops dp_ops_peer = {
  4722. .register_peer = dp_register_peer,
  4723. .clear_peer = dp_clear_peer,
  4724. .find_peer_by_addr = dp_find_peer_by_addr,
  4725. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4726. .local_peer_id = dp_local_peer_id,
  4727. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4728. .peer_state_update = dp_peer_state_update,
  4729. .get_vdevid = dp_get_vdevid,
  4730. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4731. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4732. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4733. .get_peer_state = dp_get_peer_state,
  4734. .last_assoc_received = dp_get_last_assoc_received,
  4735. .last_disassoc_received = dp_get_last_disassoc_received,
  4736. .last_deauth_received = dp_get_last_deauth_received,
  4737. };
  4738. #endif
  4739. static struct cdp_ops dp_txrx_ops = {
  4740. .cmn_drv_ops = &dp_ops_cmn,
  4741. .ctrl_ops = &dp_ops_ctrl,
  4742. .me_ops = &dp_ops_me,
  4743. .mon_ops = &dp_ops_mon,
  4744. .host_stats_ops = &dp_ops_host_stats,
  4745. .wds_ops = &dp_ops_wds,
  4746. .raw_ops = &dp_ops_raw,
  4747. #ifdef CONFIG_WIN
  4748. .pflow_ops = &dp_ops_pflow,
  4749. #endif /* CONFIG_WIN */
  4750. #ifndef CONFIG_WIN
  4751. .misc_ops = &dp_ops_misc,
  4752. .cfg_ops = &dp_ops_cfg,
  4753. .flowctl_ops = &dp_ops_flowctl,
  4754. .l_flowctl_ops = &dp_ops_l_flowctl,
  4755. #ifdef IPA_OFFLOAD
  4756. .ipa_ops = &dp_ops_ipa,
  4757. #endif
  4758. .bus_ops = &dp_ops_bus,
  4759. .ocb_ops = &dp_ops_ocb,
  4760. .peer_ops = &dp_ops_peer,
  4761. .throttle_ops = &dp_ops_throttle,
  4762. .mob_stats_ops = &dp_ops_mob_stats,
  4763. #endif
  4764. };
  4765. /*
  4766. * dp_soc_set_txrx_ring_map()
  4767. * @dp_soc: DP handler for soc
  4768. *
  4769. * Return: Void
  4770. */
  4771. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4772. {
  4773. uint32_t i;
  4774. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4775. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4776. }
  4777. }
  4778. /*
  4779. * dp_soc_attach_wifi3() - Attach txrx SOC
  4780. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4781. * @htc_handle: Opaque HTC handle
  4782. * @hif_handle: Opaque HIF handle
  4783. * @qdf_osdev: QDF device
  4784. *
  4785. * Return: DP SOC handle on success, NULL on failure
  4786. */
  4787. /*
  4788. * Local prototype added to temporarily address warning caused by
  4789. * -Wmissing-prototypes. A more correct solution, namely to expose
  4790. * a prototype in an appropriate header file, will come later.
  4791. */
  4792. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4793. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4794. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4795. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4796. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4797. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4798. {
  4799. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4800. if (!soc) {
  4801. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4802. FL("DP SOC memory allocation failed"));
  4803. goto fail0;
  4804. }
  4805. soc->cdp_soc.ops = &dp_txrx_ops;
  4806. soc->cdp_soc.ol_ops = ol_ops;
  4807. soc->osif_soc = osif_soc;
  4808. soc->osdev = qdf_osdev;
  4809. soc->hif_handle = hif_handle;
  4810. soc->psoc = psoc;
  4811. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4812. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4813. soc->hal_soc, qdf_osdev);
  4814. if (!soc->htt_handle) {
  4815. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4816. FL("HTT attach failed"));
  4817. goto fail1;
  4818. }
  4819. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4820. if (!soc->wlan_cfg_ctx) {
  4821. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4822. FL("wlan_cfg_soc_attach failed"));
  4823. goto fail2;
  4824. }
  4825. wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
  4826. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4827. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4828. CDP_CFG_MAX_PEER_ID);
  4829. if (ret != -EINVAL) {
  4830. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4831. }
  4832. }
  4833. qdf_spinlock_create(&soc->peer_ref_mutex);
  4834. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4835. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4836. /* fill the tx/rx cpu ring map*/
  4837. dp_soc_set_txrx_ring_map(soc);
  4838. qdf_spinlock_create(&soc->htt_stats.lock);
  4839. /* initialize work queue for stats processing */
  4840. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4841. return (void *)soc;
  4842. fail2:
  4843. htt_soc_detach(soc->htt_handle);
  4844. fail1:
  4845. qdf_mem_free(soc);
  4846. fail0:
  4847. return NULL;
  4848. }
  4849. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4850. /*
  4851. * dp_set_pktlog_wifi3() - attach txrx vdev
  4852. * @pdev: Datapath PDEV handle
  4853. * @event: which event's notifications are being subscribed to
  4854. * @enable: WDI event subscribe or not. (True or False)
  4855. *
  4856. * Return: Success, NULL on failure
  4857. */
  4858. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4859. bool enable)
  4860. {
  4861. struct dp_soc *soc = pdev->soc;
  4862. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4863. if (enable) {
  4864. switch (event) {
  4865. case WDI_EVENT_RX_DESC:
  4866. if (pdev->monitor_vdev) {
  4867. /* Nothing needs to be done if monitor mode is
  4868. * enabled
  4869. */
  4870. return 0;
  4871. }
  4872. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4873. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4874. htt_tlv_filter.mpdu_start = 1;
  4875. htt_tlv_filter.msdu_start = 1;
  4876. htt_tlv_filter.msdu_end = 1;
  4877. htt_tlv_filter.mpdu_end = 1;
  4878. htt_tlv_filter.packet_header = 1;
  4879. htt_tlv_filter.attention = 1;
  4880. htt_tlv_filter.ppdu_start = 1;
  4881. htt_tlv_filter.ppdu_end = 1;
  4882. htt_tlv_filter.ppdu_end_user_stats = 1;
  4883. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4884. htt_tlv_filter.ppdu_end_status_done = 1;
  4885. htt_tlv_filter.enable_fp = 1;
  4886. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4887. pdev->pdev_id,
  4888. pdev->rxdma_mon_status_ring.hal_srng,
  4889. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4890. &htt_tlv_filter);
  4891. }
  4892. break;
  4893. case WDI_EVENT_LITE_RX:
  4894. if (pdev->monitor_vdev) {
  4895. /* Nothing needs to be done if monitor mode is
  4896. * enabled
  4897. */
  4898. return 0;
  4899. }
  4900. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4901. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4902. htt_tlv_filter.ppdu_start = 1;
  4903. htt_tlv_filter.ppdu_end = 1;
  4904. htt_tlv_filter.ppdu_end_user_stats = 1;
  4905. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4906. htt_tlv_filter.ppdu_end_status_done = 1;
  4907. htt_tlv_filter.enable_fp = 1;
  4908. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4909. pdev->pdev_id,
  4910. pdev->rxdma_mon_status_ring.hal_srng,
  4911. RXDMA_MONITOR_STATUS,
  4912. RX_BUFFER_SIZE_PKTLOG_LITE,
  4913. &htt_tlv_filter);
  4914. }
  4915. break;
  4916. case WDI_EVENT_LITE_T2H:
  4917. if (pdev->monitor_vdev) {
  4918. /* Nothing needs to be done if monitor mode is
  4919. * enabled
  4920. */
  4921. return 0;
  4922. }
  4923. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4924. * passing value 0xffff. Once these macros will define in htt
  4925. * header file will use proper macros
  4926. */
  4927. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4928. break;
  4929. default:
  4930. /* Nothing needs to be done for other pktlog types */
  4931. break;
  4932. }
  4933. } else {
  4934. switch (event) {
  4935. case WDI_EVENT_RX_DESC:
  4936. case WDI_EVENT_LITE_RX:
  4937. if (pdev->monitor_vdev) {
  4938. /* Nothing needs to be done if monitor mode is
  4939. * enabled
  4940. */
  4941. return 0;
  4942. }
  4943. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4944. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4945. /* htt_tlv_filter is initialized to 0 */
  4946. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4947. pdev->pdev_id,
  4948. pdev->rxdma_mon_status_ring.hal_srng,
  4949. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4950. &htt_tlv_filter);
  4951. }
  4952. break;
  4953. case WDI_EVENT_LITE_T2H:
  4954. if (pdev->monitor_vdev) {
  4955. /* Nothing needs to be done if monitor mode is
  4956. * enabled
  4957. */
  4958. return 0;
  4959. }
  4960. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4961. * passing value 0. Once these macros will define in htt
  4962. * header file will use proper macros
  4963. */
  4964. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4965. break;
  4966. default:
  4967. /* Nothing needs to be done for other pktlog types */
  4968. break;
  4969. }
  4970. }
  4971. return 0;
  4972. }
  4973. #endif