swr-mstr-ctrl.c 93 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/irq.h>
  6. #include <linux/kernel.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/io.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/delay.h>
  13. #include <linux/kthread.h>
  14. #include <linux/bitops.h>
  15. #include <linux/clk.h>
  16. #include <linux/gpio.h>
  17. #include <linux/of_gpio.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/of.h>
  20. #include <soc/soundwire.h>
  21. #include <soc/swr-common.h>
  22. #include <linux/regmap.h>
  23. #include <dsp/msm-audio-event-notify.h>
  24. #include "swr-mstr-registers.h"
  25. #include "swr-slave-registers.h"
  26. #include "swr-mstr-ctrl.h"
  27. #define SWR_NUM_PORTS 4 /* TODO - Get this info from DT */
  28. #define SWRM_FRAME_SYNC_SEL 4000 /* 4KHz */
  29. #define SWRM_FRAME_SYNC_SEL_NATIVE 3675 /* 3.675KHz */
  30. #define SWRM_PCM_OUT 0
  31. #define SWRM_PCM_IN 1
  32. #define SWRM_SYSTEM_RESUME_TIMEOUT_MS 700
  33. #define SWRM_SYS_SUSPEND_WAIT 1
  34. #define SWRM_DSD_PARAMS_PORT 4
  35. #define SWR_BROADCAST_CMD_ID 0x0F
  36. #define SWR_AUTO_SUSPEND_DELAY 1 /* delay in sec */
  37. #define SWR_DEV_ID_MASK 0xFFFFFFFFFFFF
  38. #define SWR_REG_VAL_PACK(data, dev, id, reg) \
  39. ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
  40. #define SWR_INVALID_PARAM 0xFF
  41. #define SWR_HSTOP_MAX_VAL 0xF
  42. #define SWR_HSTART_MIN_VAL 0x0
  43. #define ERR_AUTO_SUSPEND_TIMER_VAL 0x1
  44. #define SWRM_INTERRUPT_STATUS_MASK 0x1FDFD
  45. #define SWRM_LINK_STATUS_RETRY_CNT 100
  46. #define SWRM_ROW_48 48
  47. #define SWRM_ROW_50 50
  48. #define SWRM_ROW_64 64
  49. #define SWRM_COL_02 02
  50. #define SWRM_COL_16 16
  51. #define SWRS_SCP_INT_STATUS_CLEAR_1 0x40
  52. #define SWRS_SCP_INT_STATUS_MASK_1 0x41
  53. #define SWRM_NUM_AUTO_ENUM_SLAVES 6
  54. #define SWRM_MCP_SLV_STATUS_MASK 0x03
  55. #define SWRM_ROW_CTRL_MASK 0xF8
  56. #define SWRM_COL_CTRL_MASK 0x07
  57. #define SWRM_CLK_DIV_MASK 0x700
  58. #define SWRM_SSP_PERIOD_MASK 0xff0000
  59. #define SWRM_NUM_PINGS_MASK 0x3E0000
  60. #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT 3
  61. #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT 0
  62. #define SWRM_MCP_FRAME_CTRL_BANK_CLK_DIV_VALUE_SHFT 8
  63. #define SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT 16
  64. #define SWRM_NUM_PINGS_POS 0x11
  65. #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
  66. #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
  67. #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
  68. /* pm runtime auto suspend timer in msecs */
  69. static int auto_suspend_timer = SWR_AUTO_SUSPEND_DELAY * 1000;
  70. module_param(auto_suspend_timer, int, 0664);
  71. MODULE_PARM_DESC(auto_suspend_timer, "timer for auto suspend");
  72. enum {
  73. SWR_NOT_PRESENT, /* Device is detached/not present on the bus */
  74. SWR_ATTACHED_OK, /* Device is attached */
  75. SWR_ALERT, /* Device alters master for any interrupts */
  76. SWR_RESERVED, /* Reserved */
  77. };
  78. enum {
  79. MASTER_ID_WSA = 1,
  80. MASTER_ID_RX,
  81. MASTER_ID_TX
  82. };
  83. enum {
  84. ENABLE_PENDING,
  85. DISABLE_PENDING
  86. };
  87. enum {
  88. LPASS_HW_CORE,
  89. LPASS_AUDIO_CORE,
  90. };
  91. #define TRUE 1
  92. #define FALSE 0
  93. #define SWRM_MAX_PORT_REG 120
  94. #define SWRM_MAX_INIT_REG 11
  95. #define MAX_FIFO_RD_FAIL_RETRY 3
  96. static bool swrm_lock_sleep(struct swr_mstr_ctrl *swrm);
  97. static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm);
  98. static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr);
  99. static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val);
  100. static u8 swrm_get_clk_div(int mclk_freq, int bus_clk_freq)
  101. {
  102. int clk_div = 0;
  103. u8 div_val = 0;
  104. if (!mclk_freq || !bus_clk_freq)
  105. return 0;
  106. clk_div = (mclk_freq / bus_clk_freq);
  107. switch (clk_div) {
  108. case 32:
  109. div_val = 5;
  110. break;
  111. case 16:
  112. div_val = 4;
  113. break;
  114. case 8:
  115. div_val = 3;
  116. break;
  117. case 4:
  118. div_val = 2;
  119. break;
  120. case 2:
  121. div_val = 1;
  122. break;
  123. case 1:
  124. default:
  125. div_val = 0;
  126. break;
  127. }
  128. return div_val;
  129. }
  130. static bool swrm_is_msm_variant(int val)
  131. {
  132. return (val == SWRM_VERSION_1_3);
  133. }
  134. #ifdef CONFIG_DEBUG_FS
  135. static int swrm_debug_open(struct inode *inode, struct file *file)
  136. {
  137. file->private_data = inode->i_private;
  138. return 0;
  139. }
  140. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  141. {
  142. char *token;
  143. int base, cnt;
  144. token = strsep(&buf, " ");
  145. for (cnt = 0; cnt < num_of_par; cnt++) {
  146. if (token) {
  147. if ((token[1] == 'x') || (token[1] == 'X'))
  148. base = 16;
  149. else
  150. base = 10;
  151. if (kstrtou32(token, base, &param1[cnt]) != 0)
  152. return -EINVAL;
  153. token = strsep(&buf, " ");
  154. } else
  155. return -EINVAL;
  156. }
  157. return 0;
  158. }
  159. static ssize_t swrm_reg_show(struct swr_mstr_ctrl *swrm, char __user *ubuf,
  160. size_t count, loff_t *ppos)
  161. {
  162. int i, reg_val, len;
  163. ssize_t total = 0;
  164. char tmp_buf[SWR_MSTR_MAX_BUF_LEN];
  165. int rem = 0;
  166. if (!ubuf || !ppos)
  167. return 0;
  168. i = ((int) *ppos + SWRM_BASE);
  169. rem = i%4;
  170. if (rem)
  171. i = (i - rem);
  172. for (; i <= SWRM_MAX_REGISTER; i += 4) {
  173. usleep_range(100, 150);
  174. reg_val = swr_master_read(swrm, i);
  175. len = snprintf(tmp_buf, 25, "0x%.3x: 0x%.2x\n", i, reg_val);
  176. if (len < 0) {
  177. pr_err("%s: fail to fill the buffer\n", __func__);
  178. total = -EFAULT;
  179. goto copy_err;
  180. }
  181. if ((total + len) >= count - 1)
  182. break;
  183. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  184. pr_err("%s: fail to copy reg dump\n", __func__);
  185. total = -EFAULT;
  186. goto copy_err;
  187. }
  188. *ppos += len;
  189. total += len;
  190. }
  191. copy_err:
  192. return total;
  193. }
  194. static ssize_t swrm_debug_reg_dump(struct file *file, char __user *ubuf,
  195. size_t count, loff_t *ppos)
  196. {
  197. struct swr_mstr_ctrl *swrm;
  198. if (!count || !file || !ppos || !ubuf)
  199. return -EINVAL;
  200. swrm = file->private_data;
  201. if (!swrm)
  202. return -EINVAL;
  203. if (*ppos < 0)
  204. return -EINVAL;
  205. return swrm_reg_show(swrm, ubuf, count, ppos);
  206. }
  207. static ssize_t swrm_debug_read(struct file *file, char __user *ubuf,
  208. size_t count, loff_t *ppos)
  209. {
  210. char lbuf[SWR_MSTR_RD_BUF_LEN];
  211. struct swr_mstr_ctrl *swrm = NULL;
  212. if (!count || !file || !ppos || !ubuf)
  213. return -EINVAL;
  214. swrm = file->private_data;
  215. if (!swrm)
  216. return -EINVAL;
  217. if (*ppos < 0)
  218. return -EINVAL;
  219. snprintf(lbuf, sizeof(lbuf), "0x%x\n", swrm->read_data);
  220. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  221. strnlen(lbuf, 7));
  222. }
  223. static ssize_t swrm_debug_peek_write(struct file *file, const char __user *ubuf,
  224. size_t count, loff_t *ppos)
  225. {
  226. char lbuf[SWR_MSTR_RD_BUF_LEN];
  227. int rc;
  228. u32 param[5];
  229. struct swr_mstr_ctrl *swrm = NULL;
  230. if (!count || !file || !ppos || !ubuf)
  231. return -EINVAL;
  232. swrm = file->private_data;
  233. if (!swrm)
  234. return -EINVAL;
  235. if (*ppos < 0)
  236. return -EINVAL;
  237. if (count > sizeof(lbuf) - 1)
  238. return -EINVAL;
  239. rc = copy_from_user(lbuf, ubuf, count);
  240. if (rc)
  241. return -EFAULT;
  242. lbuf[count] = '\0';
  243. rc = get_parameters(lbuf, param, 1);
  244. if ((param[0] <= SWRM_MAX_REGISTER) && (rc == 0))
  245. swrm->read_data = swr_master_read(swrm, param[0]);
  246. else
  247. rc = -EINVAL;
  248. if (rc == 0)
  249. rc = count;
  250. else
  251. dev_err(swrm->dev, "%s: rc = %d\n", __func__, rc);
  252. return rc;
  253. }
  254. static ssize_t swrm_debug_write(struct file *file,
  255. const char __user *ubuf, size_t count, loff_t *ppos)
  256. {
  257. char lbuf[SWR_MSTR_WR_BUF_LEN];
  258. int rc;
  259. u32 param[5];
  260. struct swr_mstr_ctrl *swrm;
  261. if (!file || !ppos || !ubuf)
  262. return -EINVAL;
  263. swrm = file->private_data;
  264. if (!swrm)
  265. return -EINVAL;
  266. if (count > sizeof(lbuf) - 1)
  267. return -EINVAL;
  268. rc = copy_from_user(lbuf, ubuf, count);
  269. if (rc)
  270. return -EFAULT;
  271. lbuf[count] = '\0';
  272. rc = get_parameters(lbuf, param, 2);
  273. if ((param[0] <= SWRM_MAX_REGISTER) &&
  274. (param[1] <= 0xFFFFFFFF) &&
  275. (rc == 0))
  276. swr_master_write(swrm, param[0], param[1]);
  277. else
  278. rc = -EINVAL;
  279. if (rc == 0)
  280. rc = count;
  281. else
  282. pr_err("%s: rc = %d\n", __func__, rc);
  283. return rc;
  284. }
  285. static const struct file_operations swrm_debug_read_ops = {
  286. .open = swrm_debug_open,
  287. .write = swrm_debug_peek_write,
  288. .read = swrm_debug_read,
  289. };
  290. static const struct file_operations swrm_debug_write_ops = {
  291. .open = swrm_debug_open,
  292. .write = swrm_debug_write,
  293. };
  294. static const struct file_operations swrm_debug_dump_ops = {
  295. .open = swrm_debug_open,
  296. .read = swrm_debug_reg_dump,
  297. };
  298. #endif
  299. static void swrm_reg_dump(struct swr_mstr_ctrl *swrm,
  300. u32 *reg, u32 *val, int len, const char* func)
  301. {
  302. int i = 0;
  303. for (i = 0; i < len; i++)
  304. dev_dbg(swrm->dev, "%s: reg = 0x%x val = 0x%x\n",
  305. func, reg[i], val[i]);
  306. }
  307. static bool is_swr_clk_needed(struct swr_mstr_ctrl *swrm)
  308. {
  309. return ((swrm->version <= SWRM_VERSION_1_5_1) ? true : false);
  310. }
  311. static int swrm_request_hw_vote(struct swr_mstr_ctrl *swrm,
  312. int core_type, bool enable)
  313. {
  314. int ret = 0;
  315. mutex_lock(&swrm->devlock);
  316. if (core_type == LPASS_HW_CORE) {
  317. if (swrm->lpass_core_hw_vote) {
  318. if (enable) {
  319. if (!swrm->dev_up) {
  320. dev_dbg(swrm->dev, "%s: device is down or SSR state\n",
  321. __func__);
  322. trace_printk("%s: device is down or SSR state\n",
  323. __func__);
  324. mutex_unlock(&swrm->devlock);
  325. return -ENODEV;
  326. }
  327. if (++swrm->hw_core_clk_en == 1) {
  328. ret =
  329. clk_prepare_enable(
  330. swrm->lpass_core_hw_vote);
  331. if (ret < 0) {
  332. dev_err(swrm->dev,
  333. "%s:lpass core hw enable failed\n",
  334. __func__);
  335. --swrm->hw_core_clk_en;
  336. }
  337. }
  338. } else {
  339. --swrm->hw_core_clk_en;
  340. if (swrm->hw_core_clk_en < 0)
  341. swrm->hw_core_clk_en = 0;
  342. else if (swrm->hw_core_clk_en == 0)
  343. clk_disable_unprepare(
  344. swrm->lpass_core_hw_vote);
  345. }
  346. }
  347. }
  348. if (core_type == LPASS_AUDIO_CORE) {
  349. if (swrm->lpass_core_audio) {
  350. if (enable) {
  351. if (!swrm->dev_up) {
  352. dev_dbg(swrm->dev, "%s: device is down or SSR state\n",
  353. __func__);
  354. trace_printk("%s: device is down or SSR state\n",
  355. __func__);
  356. mutex_unlock(&swrm->devlock);
  357. return -ENODEV;
  358. }
  359. if (++swrm->aud_core_clk_en == 1) {
  360. ret =
  361. clk_prepare_enable(
  362. swrm->lpass_core_audio);
  363. if (ret < 0) {
  364. dev_err(swrm->dev,
  365. "%s:lpass audio hw enable failed\n",
  366. __func__);
  367. --swrm->aud_core_clk_en;
  368. }
  369. }
  370. } else {
  371. --swrm->aud_core_clk_en;
  372. if (swrm->aud_core_clk_en < 0)
  373. swrm->aud_core_clk_en = 0;
  374. else if (swrm->aud_core_clk_en == 0)
  375. clk_disable_unprepare(
  376. swrm->lpass_core_audio);
  377. }
  378. }
  379. }
  380. mutex_unlock(&swrm->devlock);
  381. dev_dbg(swrm->dev, "%s: hw_clk_en: %d audio_core_clk_en: %d\n",
  382. __func__, swrm->hw_core_clk_en, swrm->aud_core_clk_en);
  383. trace_printk("%s: hw_clk_en: %d audio_core_clk_en: %d\n",
  384. __func__, swrm->hw_core_clk_en, swrm->aud_core_clk_en);
  385. return ret;
  386. }
  387. static int swrm_get_ssp_period(struct swr_mstr_ctrl *swrm,
  388. int row, int col,
  389. int frame_sync)
  390. {
  391. if (!swrm || !row || !col || !frame_sync)
  392. return 1;
  393. return ((swrm->bus_clk * 2) / ((row * col) * frame_sync));
  394. }
  395. static int swrm_core_vote_request(struct swr_mstr_ctrl *swrm)
  396. {
  397. int ret = 0;
  398. if (!swrm->handle)
  399. return -EINVAL;
  400. mutex_lock(&swrm->clklock);
  401. if (!swrm->dev_up) {
  402. ret = -ENODEV;
  403. goto exit;
  404. }
  405. if (swrm->core_vote) {
  406. ret = swrm->core_vote(swrm->handle, true);
  407. if (ret)
  408. dev_err_ratelimited(swrm->dev,
  409. "%s: core vote request failed\n", __func__);
  410. }
  411. exit:
  412. mutex_unlock(&swrm->clklock);
  413. return ret;
  414. }
  415. static int swrm_clk_request(struct swr_mstr_ctrl *swrm, bool enable)
  416. {
  417. int ret = 0;
  418. if (!swrm->clk || !swrm->handle)
  419. return -EINVAL;
  420. mutex_lock(&swrm->clklock);
  421. if (enable) {
  422. if (!swrm->dev_up) {
  423. ret = -ENODEV;
  424. goto exit;
  425. }
  426. if (is_swr_clk_needed(swrm)) {
  427. if (swrm->core_vote) {
  428. ret = swrm->core_vote(swrm->handle, true);
  429. if (ret) {
  430. dev_err_ratelimited(swrm->dev,
  431. "%s: core vote request failed\n",
  432. __func__);
  433. goto exit;
  434. }
  435. }
  436. }
  437. swrm->clk_ref_count++;
  438. if (swrm->clk_ref_count == 1) {
  439. trace_printk("%s: clock enable count %d",
  440. __func__, swrm->clk_ref_count);
  441. ret = swrm->clk(swrm->handle, true);
  442. if (ret) {
  443. dev_err_ratelimited(swrm->dev,
  444. "%s: clock enable req failed",
  445. __func__);
  446. --swrm->clk_ref_count;
  447. }
  448. }
  449. } else if (--swrm->clk_ref_count == 0) {
  450. trace_printk("%s: clock disable count %d",
  451. __func__, swrm->clk_ref_count);
  452. swrm->clk(swrm->handle, false);
  453. complete(&swrm->clk_off_complete);
  454. }
  455. if (swrm->clk_ref_count < 0) {
  456. dev_err(swrm->dev, "%s: swrm clk count mismatch\n", __func__);
  457. swrm->clk_ref_count = 0;
  458. }
  459. exit:
  460. mutex_unlock(&swrm->clklock);
  461. return ret;
  462. }
  463. static int swrm_ahb_write(struct swr_mstr_ctrl *swrm,
  464. u16 reg, u32 *value)
  465. {
  466. u32 temp = (u32)(*value);
  467. int ret = 0;
  468. mutex_lock(&swrm->devlock);
  469. if (!swrm->dev_up)
  470. goto err;
  471. if (is_swr_clk_needed(swrm)) {
  472. ret = swrm_clk_request(swrm, TRUE);
  473. if (ret) {
  474. dev_err_ratelimited(swrm->dev,
  475. "%s: clock request failed\n",
  476. __func__);
  477. goto err;
  478. }
  479. } else if (swrm_core_vote_request(swrm)) {
  480. goto err;
  481. }
  482. iowrite32(temp, swrm->swrm_dig_base + reg);
  483. if (is_swr_clk_needed(swrm))
  484. swrm_clk_request(swrm, FALSE);
  485. err:
  486. mutex_unlock(&swrm->devlock);
  487. return ret;
  488. }
  489. static int swrm_ahb_read(struct swr_mstr_ctrl *swrm,
  490. u16 reg, u32 *value)
  491. {
  492. u32 temp = 0;
  493. int ret = 0;
  494. mutex_lock(&swrm->devlock);
  495. if (!swrm->dev_up)
  496. goto err;
  497. if (is_swr_clk_needed(swrm)) {
  498. ret = swrm_clk_request(swrm, TRUE);
  499. if (ret) {
  500. dev_err_ratelimited(swrm->dev, "%s: clock request failed\n",
  501. __func__);
  502. goto err;
  503. }
  504. } else if (swrm_core_vote_request(swrm)) {
  505. goto err;
  506. }
  507. temp = ioread32(swrm->swrm_dig_base + reg);
  508. *value = temp;
  509. if (is_swr_clk_needed(swrm))
  510. swrm_clk_request(swrm, FALSE);
  511. err:
  512. mutex_unlock(&swrm->devlock);
  513. return ret;
  514. }
  515. static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr)
  516. {
  517. u32 val = 0;
  518. if (swrm->read)
  519. val = swrm->read(swrm->handle, reg_addr);
  520. else
  521. swrm_ahb_read(swrm, reg_addr, &val);
  522. return val;
  523. }
  524. static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val)
  525. {
  526. if (swrm->write)
  527. swrm->write(swrm->handle, reg_addr, val);
  528. else
  529. swrm_ahb_write(swrm, reg_addr, &val);
  530. }
  531. static int swr_master_bulk_write(struct swr_mstr_ctrl *swrm, u32 *reg_addr,
  532. u32 *val, unsigned int length)
  533. {
  534. int i = 0;
  535. if (swrm->bulk_write)
  536. swrm->bulk_write(swrm->handle, reg_addr, val, length);
  537. else {
  538. mutex_lock(&swrm->iolock);
  539. for (i = 0; i < length; i++) {
  540. /* wait for FIFO WR command to complete to avoid overflow */
  541. /*
  542. * Reduce sleep from 100us to 50us to meet KPIs
  543. * This still meets the hardware spec
  544. */
  545. usleep_range(50, 55);
  546. swr_master_write(swrm, reg_addr[i], val[i]);
  547. }
  548. mutex_unlock(&swrm->iolock);
  549. }
  550. return 0;
  551. }
  552. static bool swrm_check_link_status(struct swr_mstr_ctrl *swrm, bool active)
  553. {
  554. int retry = SWRM_LINK_STATUS_RETRY_CNT;
  555. int ret = false;
  556. int status = active ? 0x1 : 0x0;
  557. int comp_sts = 0x0;
  558. if ((swrm->version <= SWRM_VERSION_1_5_1))
  559. return true;
  560. do {
  561. comp_sts = swr_master_read(swrm, SWRM_COMP_STATUS) & 0x01;
  562. /* check comp status and status requested met */
  563. if ((comp_sts && status) || (!comp_sts && !status)) {
  564. ret = true;
  565. break;
  566. }
  567. retry--;
  568. usleep_range(500, 510);
  569. } while (retry);
  570. if (retry == 0)
  571. dev_err(swrm->dev, "%s: link status not %s\n", __func__,
  572. active ? "connected" : "disconnected");
  573. return ret;
  574. }
  575. static bool swrm_is_port_en(struct swr_master *mstr)
  576. {
  577. return !!(mstr->num_port);
  578. }
  579. static void copy_port_tables(struct swr_mstr_ctrl *swrm,
  580. struct port_params *params)
  581. {
  582. u8 i;
  583. struct port_params *config = params;
  584. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  585. /* wsa uses single frame structure for all configurations */
  586. if (!swrm->mport_cfg[i].port_en)
  587. continue;
  588. swrm->mport_cfg[i].sinterval = config[i].si;
  589. swrm->mport_cfg[i].offset1 = config[i].off1;
  590. swrm->mport_cfg[i].offset2 = config[i].off2;
  591. swrm->mport_cfg[i].hstart = config[i].hstart;
  592. swrm->mport_cfg[i].hstop = config[i].hstop;
  593. swrm->mport_cfg[i].blk_pack_mode = config[i].bp_mode;
  594. swrm->mport_cfg[i].blk_grp_count = config[i].bgp_ctrl;
  595. swrm->mport_cfg[i].word_length = config[i].wd_len;
  596. swrm->mport_cfg[i].lane_ctrl = config[i].lane_ctrl;
  597. swrm->mport_cfg[i].dir = config[i].dir;
  598. swrm->mport_cfg[i].stream_type = config[i].stream_type;
  599. }
  600. }
  601. static int swrm_get_port_config(struct swr_mstr_ctrl *swrm)
  602. {
  603. struct port_params *params;
  604. u32 usecase = 0;
  605. /* TODO - Send usecase information to avoid checking for master_id */
  606. if (swrm->mport_cfg[SWRM_DSD_PARAMS_PORT].port_en &&
  607. (swrm->master_id == MASTER_ID_RX))
  608. usecase = 1;
  609. params = swrm->port_param[usecase];
  610. copy_port_tables(swrm, params);
  611. return 0;
  612. }
  613. static int swrm_pcm_port_config(struct swr_mstr_ctrl *swrm, u8 port_num,
  614. bool dir, bool enable)
  615. {
  616. u16 reg_addr = 0;
  617. if (!port_num || port_num > 6) {
  618. dev_err(swrm->dev, "%s: invalid port: %d\n",
  619. __func__, port_num);
  620. return -EINVAL;
  621. }
  622. reg_addr = ((dir) ? SWRM_DIN_DP_PCM_PORT_CTRL(port_num) : \
  623. SWRM_DOUT_DP_PCM_PORT_CTRL(port_num));
  624. swr_master_write(swrm, reg_addr, enable);
  625. if (enable)
  626. swr_master_write(swrm, SWRM_COMP_FEATURE_CFG, 0x1E);
  627. else
  628. swr_master_write(swrm, SWRM_COMP_FEATURE_CFG, 0x6);
  629. return 0;
  630. }
  631. static int swrm_get_master_port(struct swr_mstr_ctrl *swrm, u8 *mstr_port_id,
  632. u8 *mstr_ch_mask, u8 mstr_prt_type,
  633. u8 slv_port_id)
  634. {
  635. int i, j;
  636. *mstr_port_id = 0;
  637. for (i = 1; i <= swrm->num_ports; i++) {
  638. for (j = 0; j < SWR_MAX_CH_PER_PORT; j++) {
  639. if (swrm->port_mapping[i][j].port_type == mstr_prt_type)
  640. goto found;
  641. }
  642. }
  643. found:
  644. if (i > swrm->num_ports || j == SWR_MAX_CH_PER_PORT) {
  645. dev_err(swrm->dev, "%s: port type not supported by master\n",
  646. __func__);
  647. return -EINVAL;
  648. }
  649. /* id 0 corresponds to master port 1 */
  650. *mstr_port_id = i - 1;
  651. *mstr_ch_mask = swrm->port_mapping[i][j].ch_mask;
  652. return 0;
  653. }
  654. static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
  655. u8 dev_addr, u16 reg_addr)
  656. {
  657. u32 val;
  658. u8 id = *cmd_id;
  659. if (id != SWR_BROADCAST_CMD_ID) {
  660. if (id < 14)
  661. id += 1;
  662. else
  663. id = 0;
  664. *cmd_id = id;
  665. }
  666. val = SWR_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
  667. return val;
  668. }
  669. static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data,
  670. u8 dev_addr, u8 cmd_id, u16 reg_addr,
  671. u32 len)
  672. {
  673. u32 val;
  674. u32 retry_attempt = 0;
  675. mutex_lock(&swrm->iolock);
  676. val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
  677. if (swrm->read) {
  678. /* skip delay if read is handled in platform driver */
  679. swr_master_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
  680. } else {
  681. /* wait for FIFO RD to complete to avoid overflow */
  682. usleep_range(100, 105);
  683. swr_master_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
  684. /* wait for FIFO RD CMD complete to avoid overflow */
  685. usleep_range(250, 255);
  686. }
  687. retry_read:
  688. *cmd_data = swr_master_read(swrm, SWRM_CMD_FIFO_RD_FIFO);
  689. dev_dbg(swrm->dev, "%s: reg: 0x%x, cmd_id: 0x%x, rcmd_id: 0x%x, \
  690. dev_num: 0x%x, cmd_data: 0x%x\n", __func__, reg_addr,
  691. cmd_id, swrm->rcmd_id, dev_addr, *cmd_data);
  692. if ((((*cmd_data) & 0xF00) >> 8) != swrm->rcmd_id) {
  693. if (retry_attempt < MAX_FIFO_RD_FAIL_RETRY) {
  694. /* wait 500 us before retry on fifo read failure */
  695. usleep_range(500, 505);
  696. if (retry_attempt == (MAX_FIFO_RD_FAIL_RETRY - 1)) {
  697. swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
  698. swr_master_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
  699. }
  700. retry_attempt++;
  701. goto retry_read;
  702. } else {
  703. dev_err_ratelimited(swrm->dev, "%s: reg: 0x%x, cmd_id: 0x%x, \
  704. rcmd_id: 0x%x, dev_num: 0x%x, cmd_data: 0x%x\n",
  705. __func__, reg_addr, cmd_id, swrm->rcmd_id,
  706. dev_addr, *cmd_data);
  707. dev_err_ratelimited(swrm->dev,
  708. "%s: failed to read fifo\n", __func__);
  709. }
  710. }
  711. mutex_unlock(&swrm->iolock);
  712. return 0;
  713. }
  714. static int swrm_cmd_fifo_wr_cmd(struct swr_mstr_ctrl *swrm, u8 cmd_data,
  715. u8 dev_addr, u8 cmd_id, u16 reg_addr)
  716. {
  717. u32 val;
  718. int ret = 0;
  719. mutex_lock(&swrm->iolock);
  720. if (!cmd_id)
  721. val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
  722. dev_addr, reg_addr);
  723. else
  724. val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
  725. dev_addr, reg_addr);
  726. dev_dbg(swrm->dev, "%s: reg: 0x%x, cmd_id: 0x%x,wcmd_id: 0x%x, \
  727. dev_num: 0x%x, cmd_data: 0x%x\n", __func__,
  728. reg_addr, cmd_id, swrm->wcmd_id,dev_addr, cmd_data);
  729. swr_master_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
  730. /*
  731. * wait for FIFO WR command to complete to avoid overflow
  732. * skip delay if write is handled in platform driver.
  733. */
  734. if(!swrm->write)
  735. usleep_range(150, 155);
  736. if (cmd_id == 0xF) {
  737. /*
  738. * sleep for 10ms for MSM soundwire variant to allow broadcast
  739. * command to complete.
  740. */
  741. if (swrm_is_msm_variant(swrm->version))
  742. usleep_range(10000, 10100);
  743. else
  744. wait_for_completion_timeout(&swrm->broadcast,
  745. (2 * HZ/10));
  746. }
  747. mutex_unlock(&swrm->iolock);
  748. return ret;
  749. }
  750. static int swrm_read(struct swr_master *master, u8 dev_num, u16 reg_addr,
  751. void *buf, u32 len)
  752. {
  753. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  754. int ret = 0;
  755. int val;
  756. u8 *reg_val = (u8 *)buf;
  757. if (!swrm) {
  758. dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
  759. return -EINVAL;
  760. }
  761. if (!dev_num) {
  762. dev_err(&master->dev, "%s: invalid slave dev num\n", __func__);
  763. return -EINVAL;
  764. }
  765. mutex_lock(&swrm->devlock);
  766. if (!swrm->dev_up) {
  767. mutex_unlock(&swrm->devlock);
  768. return 0;
  769. }
  770. mutex_unlock(&swrm->devlock);
  771. pm_runtime_get_sync(swrm->dev);
  772. ret = swrm_cmd_fifo_rd_cmd(swrm, &val, dev_num, 0, reg_addr, len);
  773. if (!ret)
  774. *reg_val = (u8)val;
  775. pm_runtime_put_autosuspend(swrm->dev);
  776. pm_runtime_mark_last_busy(swrm->dev);
  777. return ret;
  778. }
  779. static int swrm_write(struct swr_master *master, u8 dev_num, u16 reg_addr,
  780. const void *buf)
  781. {
  782. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  783. int ret = 0;
  784. u8 reg_val = *(u8 *)buf;
  785. if (!swrm) {
  786. dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
  787. return -EINVAL;
  788. }
  789. if (!dev_num) {
  790. dev_err(&master->dev, "%s: invalid slave dev num\n", __func__);
  791. return -EINVAL;
  792. }
  793. mutex_lock(&swrm->devlock);
  794. if (!swrm->dev_up) {
  795. mutex_unlock(&swrm->devlock);
  796. return 0;
  797. }
  798. mutex_unlock(&swrm->devlock);
  799. pm_runtime_get_sync(swrm->dev);
  800. ret = swrm_cmd_fifo_wr_cmd(swrm, reg_val, dev_num, 0, reg_addr);
  801. pm_runtime_put_autosuspend(swrm->dev);
  802. pm_runtime_mark_last_busy(swrm->dev);
  803. return ret;
  804. }
  805. static int swrm_bulk_write(struct swr_master *master, u8 dev_num, void *reg,
  806. const void *buf, size_t len)
  807. {
  808. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  809. int ret = 0;
  810. int i;
  811. u32 *val;
  812. u32 *swr_fifo_reg;
  813. if (!swrm || !swrm->handle) {
  814. dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
  815. return -EINVAL;
  816. }
  817. if (len <= 0)
  818. return -EINVAL;
  819. mutex_lock(&swrm->devlock);
  820. if (!swrm->dev_up) {
  821. mutex_unlock(&swrm->devlock);
  822. return 0;
  823. }
  824. mutex_unlock(&swrm->devlock);
  825. pm_runtime_get_sync(swrm->dev);
  826. if (dev_num) {
  827. swr_fifo_reg = kcalloc(len, sizeof(u32), GFP_KERNEL);
  828. if (!swr_fifo_reg) {
  829. ret = -ENOMEM;
  830. goto err;
  831. }
  832. val = kcalloc(len, sizeof(u32), GFP_KERNEL);
  833. if (!val) {
  834. ret = -ENOMEM;
  835. goto mem_fail;
  836. }
  837. for (i = 0; i < len; i++) {
  838. val[i] = swrm_get_packed_reg_val(&swrm->wcmd_id,
  839. ((u8 *)buf)[i],
  840. dev_num,
  841. ((u16 *)reg)[i]);
  842. swr_fifo_reg[i] = SWRM_CMD_FIFO_WR_CMD;
  843. }
  844. ret = swr_master_bulk_write(swrm, swr_fifo_reg, val, len);
  845. if (ret) {
  846. dev_err(&master->dev, "%s: bulk write failed\n",
  847. __func__);
  848. ret = -EINVAL;
  849. }
  850. } else {
  851. dev_err(&master->dev,
  852. "%s: No support of Bulk write for master regs\n",
  853. __func__);
  854. ret = -EINVAL;
  855. goto err;
  856. }
  857. kfree(val);
  858. mem_fail:
  859. kfree(swr_fifo_reg);
  860. err:
  861. pm_runtime_put_autosuspend(swrm->dev);
  862. pm_runtime_mark_last_busy(swrm->dev);
  863. return ret;
  864. }
  865. static u8 get_inactive_bank_num(struct swr_mstr_ctrl *swrm)
  866. {
  867. return (swr_master_read(swrm, SWRM_MCP_STATUS) & 0x01) ? 0 : 1;
  868. }
  869. static void enable_bank_switch(struct swr_mstr_ctrl *swrm, u8 bank,
  870. u8 row, u8 col)
  871. {
  872. swrm_cmd_fifo_wr_cmd(swrm, ((row << 3) | col), 0xF, 0xF,
  873. SWRS_SCP_FRAME_CTRL_BANK(bank));
  874. }
  875. static void swrm_switch_frame_shape(struct swr_mstr_ctrl *swrm, int mclk_freq)
  876. {
  877. u8 bank;
  878. u32 n_row, n_col;
  879. u32 value = 0;
  880. u32 row = 0, col = 0;
  881. u8 ssp_period = 0;
  882. int frame_sync = SWRM_FRAME_SYNC_SEL;
  883. if (mclk_freq == MCLK_FREQ_NATIVE) {
  884. n_col = SWR_MAX_COL;
  885. col = SWRM_COL_16;
  886. n_row = SWR_ROW_64;
  887. row = SWRM_ROW_64;
  888. frame_sync = SWRM_FRAME_SYNC_SEL_NATIVE;
  889. } else {
  890. n_col = SWR_MIN_COL;
  891. col = SWRM_COL_02;
  892. n_row = SWR_ROW_50;
  893. row = SWRM_ROW_50;
  894. frame_sync = SWRM_FRAME_SYNC_SEL;
  895. }
  896. bank = get_inactive_bank_num(swrm);
  897. ssp_period = swrm_get_ssp_period(swrm, row, col, frame_sync);
  898. dev_dbg(swrm->dev, "%s: ssp_period: %d\n", __func__, ssp_period);
  899. value = ((n_row << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
  900. (n_col << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
  901. ((ssp_period - 1) << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
  902. swr_master_write(swrm, SWRM_MCP_FRAME_CTRL_BANK(bank), value);
  903. enable_bank_switch(swrm, bank, n_row, n_col);
  904. }
  905. static struct swr_port_info *swrm_get_port_req(struct swrm_mports *mport,
  906. u8 slv_port, u8 dev_num)
  907. {
  908. struct swr_port_info *port_req = NULL;
  909. list_for_each_entry(port_req, &mport->port_req_list, list) {
  910. /* Store dev_id instead of dev_num if enumeration is changed run_time */
  911. if ((port_req->slave_port_id == slv_port)
  912. && (port_req->dev_num == dev_num))
  913. return port_req;
  914. }
  915. return NULL;
  916. }
  917. static bool swrm_remove_from_group(struct swr_master *master)
  918. {
  919. struct swr_device *swr_dev;
  920. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  921. bool is_removed = false;
  922. if (!swrm)
  923. goto end;
  924. mutex_lock(&swrm->mlock);
  925. if ((swrm->num_rx_chs > 1) &&
  926. (swrm->num_rx_chs == swrm->num_cfg_devs)) {
  927. list_for_each_entry(swr_dev, &master->devices,
  928. dev_list) {
  929. swr_dev->group_id = SWR_GROUP_NONE;
  930. master->gr_sid = 0;
  931. }
  932. is_removed = true;
  933. }
  934. mutex_unlock(&swrm->mlock);
  935. end:
  936. return is_removed;
  937. }
  938. int swrm_get_clk_div_rate(int mclk_freq, int bus_clk_freq)
  939. {
  940. if (!bus_clk_freq)
  941. return mclk_freq;
  942. if (mclk_freq == SWR_CLK_RATE_9P6MHZ) {
  943. if (bus_clk_freq <= SWR_CLK_RATE_0P6MHZ)
  944. bus_clk_freq = SWR_CLK_RATE_0P6MHZ;
  945. else if (bus_clk_freq <= SWR_CLK_RATE_1P2MHZ)
  946. bus_clk_freq = SWR_CLK_RATE_1P2MHZ;
  947. else if (bus_clk_freq <= SWR_CLK_RATE_2P4MHZ)
  948. bus_clk_freq = SWR_CLK_RATE_2P4MHZ;
  949. else if(bus_clk_freq <= SWR_CLK_RATE_4P8MHZ)
  950. bus_clk_freq = SWR_CLK_RATE_4P8MHZ;
  951. else if(bus_clk_freq <= SWR_CLK_RATE_9P6MHZ)
  952. bus_clk_freq = SWR_CLK_RATE_9P6MHZ;
  953. } else if (mclk_freq == SWR_CLK_RATE_11P2896MHZ)
  954. bus_clk_freq = SWR_CLK_RATE_11P2896MHZ;
  955. return bus_clk_freq;
  956. }
  957. static int swrm_update_bus_clk(struct swr_mstr_ctrl *swrm)
  958. {
  959. int ret = 0;
  960. int agg_clk = 0;
  961. int i;
  962. for (i = 0; i < SWR_MSTR_PORT_LEN; i++)
  963. agg_clk += swrm->mport_cfg[i].ch_rate;
  964. if (agg_clk)
  965. swrm->bus_clk = swrm_get_clk_div_rate(swrm->mclk_freq,
  966. agg_clk);
  967. else
  968. swrm->bus_clk = swrm->mclk_freq;
  969. dev_dbg(swrm->dev, "%s: all_port_clk: %d, bus_clk: %d\n",
  970. __func__, agg_clk, swrm->bus_clk);
  971. return ret;
  972. }
  973. static void swrm_disable_ports(struct swr_master *master,
  974. u8 bank)
  975. {
  976. u32 value;
  977. struct swr_port_info *port_req;
  978. int i;
  979. struct swrm_mports *mport;
  980. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  981. if (!swrm) {
  982. pr_err("%s: swrm is null\n", __func__);
  983. return;
  984. }
  985. dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
  986. master->num_port);
  987. for (i = 0; i < SWR_MSTR_PORT_LEN ; i++) {
  988. mport = &(swrm->mport_cfg[i]);
  989. if (!mport->port_en)
  990. continue;
  991. list_for_each_entry(port_req, &mport->port_req_list, list) {
  992. /* skip ports with no change req's*/
  993. if (port_req->req_ch == port_req->ch_en)
  994. continue;
  995. swrm_cmd_fifo_wr_cmd(swrm, port_req->req_ch,
  996. port_req->dev_num, 0x00,
  997. SWRS_DP_CHANNEL_ENABLE_BANK(port_req->slave_port_id,
  998. bank));
  999. dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x\n",
  1000. __func__, i,
  1001. (SWRM_DP_PORT_CTRL_BANK((i + 1), bank)));
  1002. }
  1003. value = ((mport->req_ch)
  1004. << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
  1005. value |= ((mport->offset2)
  1006. << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
  1007. value |= ((mport->offset1)
  1008. << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
  1009. value |= mport->sinterval;
  1010. swr_master_write(swrm,
  1011. SWRM_DP_PORT_CTRL_BANK((i + 1), bank),
  1012. value);
  1013. dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
  1014. __func__, i,
  1015. (SWRM_DP_PORT_CTRL_BANK((i + 1), bank)), value);
  1016. if (mport->stream_type == SWR_PCM)
  1017. swrm_pcm_port_config(swrm, (i + 1), mport->dir, false);
  1018. }
  1019. }
  1020. static void swrm_cleanup_disabled_port_reqs(struct swr_master *master)
  1021. {
  1022. struct swr_port_info *port_req, *next;
  1023. int i;
  1024. struct swrm_mports *mport;
  1025. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1026. if (!swrm) {
  1027. pr_err("%s: swrm is null\n", __func__);
  1028. return;
  1029. }
  1030. dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
  1031. master->num_port);
  1032. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  1033. mport = &(swrm->mport_cfg[i]);
  1034. list_for_each_entry_safe(port_req, next,
  1035. &mport->port_req_list, list) {
  1036. /* skip ports without new ch req */
  1037. if (port_req->ch_en == port_req->req_ch)
  1038. continue;
  1039. /* remove new ch req's*/
  1040. port_req->ch_en = port_req->req_ch;
  1041. /* If no streams enabled on port, remove the port req */
  1042. if (port_req->ch_en == 0) {
  1043. list_del(&port_req->list);
  1044. kfree(port_req);
  1045. }
  1046. }
  1047. /* remove new ch req's on mport*/
  1048. mport->ch_en = mport->req_ch;
  1049. if (!(mport->ch_en)) {
  1050. mport->port_en = false;
  1051. master->port_en_mask &= ~i;
  1052. }
  1053. }
  1054. }
  1055. static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
  1056. {
  1057. u32 value, slv_id;
  1058. struct swr_port_info *port_req;
  1059. int i;
  1060. struct swrm_mports *mport;
  1061. struct swrm_mports *prev_mport = NULL;
  1062. u32 reg[SWRM_MAX_PORT_REG];
  1063. u32 val[SWRM_MAX_PORT_REG];
  1064. int len = 0;
  1065. u8 hparams;
  1066. u8 offset1 = 0;
  1067. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1068. if (!swrm) {
  1069. pr_err("%s: swrm is null\n", __func__);
  1070. return;
  1071. }
  1072. dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
  1073. master->num_port);
  1074. for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
  1075. mport = &(swrm->mport_cfg[i]);
  1076. if (!mport->port_en)
  1077. continue;
  1078. if (mport->stream_type == SWR_PCM)
  1079. swrm_pcm_port_config(swrm, (i + 1), mport->dir, true);
  1080. list_for_each_entry(port_req, &mport->port_req_list, list) {
  1081. slv_id = port_req->slave_port_id;
  1082. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1083. val[len++] = SWR_REG_VAL_PACK(port_req->req_ch,
  1084. port_req->dev_num, 0x00,
  1085. SWRS_DP_CHANNEL_ENABLE_BANK(slv_id,
  1086. bank));
  1087. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1088. val[len++] = SWR_REG_VAL_PACK(mport->sinterval,
  1089. port_req->dev_num, 0x00,
  1090. SWRS_DP_SAMPLE_CONTROL_1_BANK(slv_id,
  1091. bank));
  1092. /* Assumption: If different channels in the same port
  1093. * on master is enabled for different slaves, then each
  1094. * slave offset should be configured differently.
  1095. */
  1096. if (prev_mport == mport)
  1097. offset1 += mport->offset1;
  1098. else {
  1099. offset1 = mport->offset1;
  1100. prev_mport = mport;
  1101. }
  1102. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1103. val[len++] = SWR_REG_VAL_PACK(offset1,
  1104. port_req->dev_num, 0x00,
  1105. SWRS_DP_OFFSET_CONTROL_1_BANK(slv_id,
  1106. bank));
  1107. if (mport->offset2 != SWR_INVALID_PARAM) {
  1108. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1109. val[len++] = SWR_REG_VAL_PACK(mport->offset2,
  1110. port_req->dev_num, 0x00,
  1111. SWRS_DP_OFFSET_CONTROL_2_BANK(
  1112. slv_id, bank));
  1113. }
  1114. if (mport->hstart != SWR_INVALID_PARAM
  1115. && mport->hstop != SWR_INVALID_PARAM) {
  1116. hparams = (mport->hstart << 4) | mport->hstop;
  1117. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1118. val[len++] = SWR_REG_VAL_PACK(hparams,
  1119. port_req->dev_num, 0x00,
  1120. SWRS_DP_HCONTROL_BANK(slv_id,
  1121. bank));
  1122. }
  1123. if (mport->word_length != SWR_INVALID_PARAM) {
  1124. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1125. val[len++] =
  1126. SWR_REG_VAL_PACK(mport->word_length,
  1127. port_req->dev_num, 0x00,
  1128. SWRS_DP_BLOCK_CONTROL_1(slv_id));
  1129. }
  1130. if (mport->blk_pack_mode != SWR_INVALID_PARAM
  1131. && swrm->master_id != MASTER_ID_WSA) {
  1132. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1133. val[len++] =
  1134. SWR_REG_VAL_PACK(mport->blk_pack_mode,
  1135. port_req->dev_num, 0x00,
  1136. SWRS_DP_BLOCK_CONTROL_3_BANK(slv_id,
  1137. bank));
  1138. }
  1139. if (mport->blk_grp_count != SWR_INVALID_PARAM) {
  1140. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1141. val[len++] =
  1142. SWR_REG_VAL_PACK(mport->blk_grp_count,
  1143. port_req->dev_num, 0x00,
  1144. SWRS_DP_BLOCK_CONTROL_2_BANK(slv_id,
  1145. bank));
  1146. }
  1147. if (mport->lane_ctrl != SWR_INVALID_PARAM) {
  1148. reg[len] = SWRM_CMD_FIFO_WR_CMD;
  1149. val[len++] =
  1150. SWR_REG_VAL_PACK(mport->lane_ctrl,
  1151. port_req->dev_num, 0x00,
  1152. SWRS_DP_LANE_CONTROL_BANK(slv_id,
  1153. bank));
  1154. }
  1155. port_req->ch_en = port_req->req_ch;
  1156. }
  1157. value = ((mport->req_ch)
  1158. << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
  1159. if (mport->offset2 != SWR_INVALID_PARAM)
  1160. value |= ((mport->offset2)
  1161. << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
  1162. value |= ((mport->offset1)
  1163. << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
  1164. value |= (mport->sinterval & 0xFF);
  1165. reg[len] = SWRM_DP_PORT_CTRL_BANK((i + 1), bank);
  1166. val[len++] = value;
  1167. dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
  1168. __func__, i,
  1169. (SWRM_DP_PORT_CTRL_BANK((i + 1), bank)), value);
  1170. reg[len] = SWRM_DP_SAMPLECTRL2_BANK((i + 1), bank);
  1171. val[len++] = ((mport->sinterval >> 8) & 0xFF);
  1172. if (mport->lane_ctrl != SWR_INVALID_PARAM) {
  1173. reg[len] = SWRM_DP_PORT_CTRL_2_BANK((i + 1), bank);
  1174. val[len++] = mport->lane_ctrl;
  1175. }
  1176. if (mport->word_length != SWR_INVALID_PARAM) {
  1177. reg[len] = SWRM_DP_BLOCK_CTRL_1((i + 1));
  1178. val[len++] = mport->word_length;
  1179. }
  1180. if (mport->blk_grp_count != SWR_INVALID_PARAM) {
  1181. reg[len] = SWRM_DP_BLOCK_CTRL2_BANK((i + 1), bank);
  1182. val[len++] = mport->blk_grp_count;
  1183. }
  1184. if (mport->hstart != SWR_INVALID_PARAM
  1185. && mport->hstop != SWR_INVALID_PARAM) {
  1186. reg[len] = SWRM_DP_PORT_HCTRL_BANK((i + 1), bank);
  1187. hparams = (mport->hstop << 4) | mport->hstart;
  1188. val[len++] = hparams;
  1189. } else {
  1190. reg[len] = SWRM_DP_PORT_HCTRL_BANK((i + 1), bank);
  1191. hparams = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
  1192. val[len++] = hparams;
  1193. }
  1194. if (mport->blk_pack_mode != SWR_INVALID_PARAM) {
  1195. reg[len] = SWRM_DP_BLOCK_CTRL3_BANK((i + 1), bank);
  1196. val[len++] = mport->blk_pack_mode;
  1197. }
  1198. mport->ch_en = mport->req_ch;
  1199. }
  1200. swrm_reg_dump(swrm, reg, val, len, __func__);
  1201. swr_master_bulk_write(swrm, reg, val, len);
  1202. }
  1203. static void swrm_apply_port_config(struct swr_master *master)
  1204. {
  1205. u8 bank;
  1206. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1207. if (!swrm) {
  1208. pr_err("%s: Invalid handle to swr controller\n",
  1209. __func__);
  1210. return;
  1211. }
  1212. bank = get_inactive_bank_num(swrm);
  1213. dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n",
  1214. __func__, bank, master->num_port);
  1215. if (!swrm->disable_div2_clk_switch)
  1216. swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00,
  1217. SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank));
  1218. swrm_copy_data_port_config(master, bank);
  1219. }
  1220. static int swrm_slvdev_datapath_control(struct swr_master *master, bool enable)
  1221. {
  1222. u8 bank;
  1223. u32 value = 0, n_row = 0, n_col = 0;
  1224. u32 row = 0, col = 0;
  1225. int bus_clk_div_factor;
  1226. int ret;
  1227. u8 ssp_period = 0;
  1228. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1229. int mask = (SWRM_ROW_CTRL_MASK | SWRM_COL_CTRL_MASK |
  1230. SWRM_CLK_DIV_MASK | SWRM_SSP_PERIOD_MASK);
  1231. u8 inactive_bank;
  1232. int frame_sync = SWRM_FRAME_SYNC_SEL;
  1233. if (!swrm) {
  1234. pr_err("%s: swrm is null\n", __func__);
  1235. return -EFAULT;
  1236. }
  1237. mutex_lock(&swrm->mlock);
  1238. /*
  1239. * During disable if master is already down, which implies an ssr/pdr
  1240. * scenario, just mark ports as disabled and exit
  1241. */
  1242. if (swrm->state == SWR_MSTR_SSR && !enable) {
  1243. if (!test_bit(DISABLE_PENDING, &swrm->port_req_pending)) {
  1244. dev_dbg(swrm->dev, "%s:No pending disconn port req\n",
  1245. __func__);
  1246. goto exit;
  1247. }
  1248. clear_bit(DISABLE_PENDING, &swrm->port_req_pending);
  1249. swrm_cleanup_disabled_port_reqs(master);
  1250. if (!swrm_is_port_en(master)) {
  1251. dev_dbg(&master->dev, "%s: pm_runtime auto suspend triggered\n",
  1252. __func__);
  1253. pm_runtime_mark_last_busy(swrm->dev);
  1254. pm_runtime_put_autosuspend(swrm->dev);
  1255. }
  1256. goto exit;
  1257. }
  1258. bank = get_inactive_bank_num(swrm);
  1259. if (enable) {
  1260. if (!test_bit(ENABLE_PENDING, &swrm->port_req_pending)) {
  1261. dev_dbg(swrm->dev, "%s:No pending connect port req\n",
  1262. __func__);
  1263. goto exit;
  1264. }
  1265. clear_bit(ENABLE_PENDING, &swrm->port_req_pending);
  1266. ret = swrm_get_port_config(swrm);
  1267. if (ret) {
  1268. /* cannot accommodate ports */
  1269. swrm_cleanup_disabled_port_reqs(master);
  1270. mutex_unlock(&swrm->mlock);
  1271. return -EINVAL;
  1272. }
  1273. swr_master_write(swrm, SWRM_CPU1_INTERRUPT_EN,
  1274. SWRM_INTERRUPT_STATUS_MASK);
  1275. /* apply the new port config*/
  1276. swrm_apply_port_config(master);
  1277. } else {
  1278. if (!test_bit(DISABLE_PENDING, &swrm->port_req_pending)) {
  1279. dev_dbg(swrm->dev, "%s:No pending disconn port req\n",
  1280. __func__);
  1281. goto exit;
  1282. }
  1283. clear_bit(DISABLE_PENDING, &swrm->port_req_pending);
  1284. swrm_disable_ports(master, bank);
  1285. }
  1286. dev_dbg(swrm->dev, "%s: enable: %d, cfg_devs: %d freq %d\n",
  1287. __func__, enable, swrm->num_cfg_devs, swrm->mclk_freq);
  1288. if (enable) {
  1289. /* set col = 16 */
  1290. n_col = SWR_MAX_COL;
  1291. col = SWRM_COL_16;
  1292. if (swrm->bus_clk == MCLK_FREQ_LP) {
  1293. n_col = SWR_MIN_COL;
  1294. col = SWRM_COL_02;
  1295. }
  1296. } else {
  1297. /*
  1298. * Do not change to col = 2 if there are still active ports
  1299. */
  1300. if (!master->num_port) {
  1301. n_col = SWR_MIN_COL;
  1302. col = SWRM_COL_02;
  1303. } else {
  1304. n_col = SWR_MAX_COL;
  1305. col = SWRM_COL_16;
  1306. }
  1307. }
  1308. /* Use default 50 * x, frame shape. Change based on mclk */
  1309. if (swrm->mclk_freq == MCLK_FREQ_NATIVE) {
  1310. dev_dbg(swrm->dev, "setting 64 x %d frameshape\n", col);
  1311. n_row = SWR_ROW_64;
  1312. row = SWRM_ROW_64;
  1313. frame_sync = SWRM_FRAME_SYNC_SEL_NATIVE;
  1314. } else {
  1315. dev_dbg(swrm->dev, "setting 50 x %d frameshape\n", col);
  1316. n_row = SWR_ROW_50;
  1317. row = SWRM_ROW_50;
  1318. frame_sync = SWRM_FRAME_SYNC_SEL;
  1319. }
  1320. ssp_period = swrm_get_ssp_period(swrm, row, col, frame_sync);
  1321. bus_clk_div_factor = swrm_get_clk_div(swrm->mclk_freq, swrm->bus_clk);
  1322. dev_dbg(swrm->dev, "%s: ssp_period: %d, bus_clk_div:%d \n", __func__,
  1323. ssp_period, bus_clk_div_factor);
  1324. value = swr_master_read(swrm, SWRM_MCP_FRAME_CTRL_BANK(bank));
  1325. value &= (~mask);
  1326. value |= ((n_row << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
  1327. (n_col << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
  1328. (bus_clk_div_factor <<
  1329. SWRM_MCP_FRAME_CTRL_BANK_CLK_DIV_VALUE_SHFT) |
  1330. ((ssp_period - 1) << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
  1331. swr_master_write(swrm, SWRM_MCP_FRAME_CTRL_BANK(bank), value);
  1332. dev_dbg(swrm->dev, "%s: regaddr: 0x%x, value: 0x%x\n", __func__,
  1333. SWRM_MCP_FRAME_CTRL_BANK(bank), value);
  1334. enable_bank_switch(swrm, bank, n_row, n_col);
  1335. inactive_bank = bank ? 0 : 1;
  1336. if (enable)
  1337. swrm_copy_data_port_config(master, inactive_bank);
  1338. else {
  1339. swrm_disable_ports(master, inactive_bank);
  1340. swrm_cleanup_disabled_port_reqs(master);
  1341. }
  1342. if (!swrm_is_port_en(master)) {
  1343. dev_dbg(&master->dev, "%s: pm_runtime auto suspend triggered\n",
  1344. __func__);
  1345. pm_runtime_mark_last_busy(swrm->dev);
  1346. pm_runtime_put_autosuspend(swrm->dev);
  1347. }
  1348. exit:
  1349. mutex_unlock(&swrm->mlock);
  1350. return 0;
  1351. }
  1352. static int swrm_connect_port(struct swr_master *master,
  1353. struct swr_params *portinfo)
  1354. {
  1355. int i;
  1356. struct swr_port_info *port_req;
  1357. int ret = 0;
  1358. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1359. struct swrm_mports *mport;
  1360. u8 mstr_port_id, mstr_ch_msk;
  1361. dev_dbg(&master->dev, "%s: enter\n", __func__);
  1362. if (!portinfo)
  1363. return -EINVAL;
  1364. if (!swrm) {
  1365. dev_err(&master->dev,
  1366. "%s: Invalid handle to swr controller\n",
  1367. __func__);
  1368. return -EINVAL;
  1369. }
  1370. mutex_lock(&swrm->mlock);
  1371. mutex_lock(&swrm->devlock);
  1372. if (!swrm->dev_up) {
  1373. mutex_unlock(&swrm->devlock);
  1374. mutex_unlock(&swrm->mlock);
  1375. return -EINVAL;
  1376. }
  1377. mutex_unlock(&swrm->devlock);
  1378. if (!swrm_is_port_en(master))
  1379. pm_runtime_get_sync(swrm->dev);
  1380. for (i = 0; i < portinfo->num_port; i++) {
  1381. ret = swrm_get_master_port(swrm, &mstr_port_id, &mstr_ch_msk,
  1382. portinfo->port_type[i],
  1383. portinfo->port_id[i]);
  1384. if (ret) {
  1385. dev_err(&master->dev,
  1386. "%s: mstr portid for slv port %d not found\n",
  1387. __func__, portinfo->port_id[i]);
  1388. goto port_fail;
  1389. }
  1390. mport = &(swrm->mport_cfg[mstr_port_id]);
  1391. /* get port req */
  1392. port_req = swrm_get_port_req(mport, portinfo->port_id[i],
  1393. portinfo->dev_num);
  1394. if (!port_req) {
  1395. dev_dbg(&master->dev, "%s: new req:port id %d dev %d\n",
  1396. __func__, portinfo->port_id[i],
  1397. portinfo->dev_num);
  1398. port_req = kzalloc(sizeof(struct swr_port_info),
  1399. GFP_KERNEL);
  1400. if (!port_req) {
  1401. ret = -ENOMEM;
  1402. goto mem_fail;
  1403. }
  1404. port_req->dev_num = portinfo->dev_num;
  1405. port_req->slave_port_id = portinfo->port_id[i];
  1406. port_req->num_ch = portinfo->num_ch[i];
  1407. port_req->ch_rate = portinfo->ch_rate[i];
  1408. port_req->ch_en = 0;
  1409. port_req->master_port_id = mstr_port_id;
  1410. list_add(&port_req->list, &mport->port_req_list);
  1411. }
  1412. port_req->req_ch |= portinfo->ch_en[i];
  1413. dev_dbg(&master->dev,
  1414. "%s: mstr port %d, slv port %d ch_rate %d num_ch %d\n",
  1415. __func__, port_req->master_port_id,
  1416. port_req->slave_port_id, port_req->ch_rate,
  1417. port_req->num_ch);
  1418. /* Put the port req on master port */
  1419. mport = &(swrm->mport_cfg[mstr_port_id]);
  1420. mport->port_en = true;
  1421. mport->req_ch |= mstr_ch_msk;
  1422. master->port_en_mask |= (1 << mstr_port_id);
  1423. if (swrm->clk_stop_mode0_supp &&
  1424. swrm->dynamic_port_map_supported) {
  1425. mport->ch_rate += portinfo->ch_rate[i];
  1426. swrm_update_bus_clk(swrm);
  1427. }
  1428. }
  1429. master->num_port += portinfo->num_port;
  1430. set_bit(ENABLE_PENDING, &swrm->port_req_pending);
  1431. swr_port_response(master, portinfo->tid);
  1432. mutex_unlock(&swrm->mlock);
  1433. return 0;
  1434. port_fail:
  1435. mem_fail:
  1436. /* cleanup port reqs in error condition */
  1437. swrm_cleanup_disabled_port_reqs(master);
  1438. mutex_unlock(&swrm->mlock);
  1439. return ret;
  1440. }
  1441. static int swrm_disconnect_port(struct swr_master *master,
  1442. struct swr_params *portinfo)
  1443. {
  1444. int i, ret = 0;
  1445. struct swr_port_info *port_req;
  1446. struct swrm_mports *mport;
  1447. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
  1448. u8 mstr_port_id, mstr_ch_mask;
  1449. if (!swrm) {
  1450. dev_err(&master->dev,
  1451. "%s: Invalid handle to swr controller\n",
  1452. __func__);
  1453. return -EINVAL;
  1454. }
  1455. if (!portinfo) {
  1456. dev_err(&master->dev, "%s: portinfo is NULL\n", __func__);
  1457. return -EINVAL;
  1458. }
  1459. mutex_lock(&swrm->mlock);
  1460. for (i = 0; i < portinfo->num_port; i++) {
  1461. ret = swrm_get_master_port(swrm, &mstr_port_id, &mstr_ch_mask,
  1462. portinfo->port_type[i], portinfo->port_id[i]);
  1463. if (ret) {
  1464. dev_err(&master->dev,
  1465. "%s: mstr portid for slv port %d not found\n",
  1466. __func__, portinfo->port_id[i]);
  1467. mutex_unlock(&swrm->mlock);
  1468. return -EINVAL;
  1469. }
  1470. mport = &(swrm->mport_cfg[mstr_port_id]);
  1471. /* get port req */
  1472. port_req = swrm_get_port_req(mport, portinfo->port_id[i],
  1473. portinfo->dev_num);
  1474. if (!port_req) {
  1475. dev_err(&master->dev, "%s:port not enabled : port %d\n",
  1476. __func__, portinfo->port_id[i]);
  1477. mutex_unlock(&swrm->mlock);
  1478. return -EINVAL;
  1479. }
  1480. port_req->req_ch &= ~portinfo->ch_en[i];
  1481. mport->req_ch &= ~mstr_ch_mask;
  1482. if (swrm->clk_stop_mode0_supp &&
  1483. swrm->dynamic_port_map_supported &&
  1484. !mport->req_ch) {
  1485. mport->ch_rate = 0;
  1486. swrm_update_bus_clk(swrm);
  1487. }
  1488. }
  1489. master->num_port -= portinfo->num_port;
  1490. set_bit(DISABLE_PENDING, &swrm->port_req_pending);
  1491. swr_port_response(master, portinfo->tid);
  1492. mutex_unlock(&swrm->mlock);
  1493. return 0;
  1494. }
  1495. static int swrm_find_alert_slave(struct swr_mstr_ctrl *swrm,
  1496. int status, u8 *devnum)
  1497. {
  1498. int i;
  1499. bool found = false;
  1500. for (i = 0; i < (swrm->master.num_dev + 1); i++) {
  1501. if ((status & SWRM_MCP_SLV_STATUS_MASK) == SWR_ALERT) {
  1502. *devnum = i;
  1503. found = true;
  1504. break;
  1505. }
  1506. status >>= 2;
  1507. }
  1508. if (found)
  1509. return 0;
  1510. else
  1511. return -EINVAL;
  1512. }
  1513. static void swrm_enable_slave_irq(struct swr_mstr_ctrl *swrm)
  1514. {
  1515. int i;
  1516. int status = 0;
  1517. status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS);
  1518. if (!status) {
  1519. dev_dbg_ratelimited(swrm->dev, "%s: slaves status is 0x%x\n",
  1520. __func__, status);
  1521. return;
  1522. }
  1523. dev_dbg(swrm->dev, "%s: slave status: 0x%x\n", __func__, status);
  1524. for (i = 0; i < (swrm->master.num_dev + 1); i++) {
  1525. if (status & SWRM_MCP_SLV_STATUS_MASK) {
  1526. swrm_cmd_fifo_wr_cmd(swrm, 0xFF, i, 0x0,
  1527. SWRS_SCP_INT_STATUS_CLEAR_1);
  1528. swrm_cmd_fifo_wr_cmd(swrm, 0x4, i, 0x0,
  1529. SWRS_SCP_INT_STATUS_MASK_1);
  1530. }
  1531. status >>= 2;
  1532. }
  1533. }
  1534. static int swrm_check_slave_change_status(struct swr_mstr_ctrl *swrm,
  1535. int status, u8 *devnum)
  1536. {
  1537. int i;
  1538. int new_sts = status;
  1539. int ret = SWR_NOT_PRESENT;
  1540. if (status != swrm->slave_status) {
  1541. for (i = 0; i < (swrm->master.num_dev + 1); i++) {
  1542. if ((status & SWRM_MCP_SLV_STATUS_MASK) !=
  1543. (swrm->slave_status & SWRM_MCP_SLV_STATUS_MASK)) {
  1544. ret = (status & SWRM_MCP_SLV_STATUS_MASK);
  1545. *devnum = i;
  1546. break;
  1547. }
  1548. status >>= 2;
  1549. swrm->slave_status >>= 2;
  1550. }
  1551. swrm->slave_status = new_sts;
  1552. }
  1553. return ret;
  1554. }
  1555. static irqreturn_t swr_mstr_interrupt(int irq, void *dev)
  1556. {
  1557. struct swr_mstr_ctrl *swrm = dev;
  1558. u32 value, intr_sts, intr_sts_masked;
  1559. u32 temp = 0;
  1560. u32 status, chg_sts, i;
  1561. u8 devnum = 0;
  1562. int ret = IRQ_HANDLED;
  1563. struct swr_device *swr_dev;
  1564. struct swr_master *mstr = &swrm->master;
  1565. int retry = 5;
  1566. trace_printk("%s enter\n", __func__);
  1567. if (unlikely(swrm_lock_sleep(swrm) == false)) {
  1568. dev_err(swrm->dev, "%s Failed to hold suspend\n", __func__);
  1569. return IRQ_NONE;
  1570. }
  1571. mutex_lock(&swrm->reslock);
  1572. if (swrm_request_hw_vote(swrm, LPASS_HW_CORE, true)) {
  1573. ret = IRQ_NONE;
  1574. goto exit;
  1575. }
  1576. if (swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, true)) {
  1577. ret = IRQ_NONE;
  1578. goto err_audio_hw_vote;
  1579. }
  1580. ret = swrm_clk_request(swrm, true);
  1581. if (ret) {
  1582. dev_err(dev, "%s: swrm clk failed\n", __func__);
  1583. ret = IRQ_NONE;
  1584. goto err_audio_core_vote;
  1585. }
  1586. mutex_unlock(&swrm->reslock);
  1587. intr_sts = swr_master_read(swrm, SWRM_INTERRUPT_STATUS);
  1588. intr_sts_masked = intr_sts & swrm->intr_mask;
  1589. dev_dbg(swrm->dev, "%s: status: 0x%x \n", __func__, intr_sts_masked);
  1590. trace_printk("%s: status: 0x%x \n", __func__, intr_sts_masked);
  1591. handle_irq:
  1592. for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
  1593. value = intr_sts_masked & (1 << i);
  1594. if (!value)
  1595. continue;
  1596. switch (value) {
  1597. case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
  1598. dev_dbg(swrm->dev, "%s: Trigger irq to slave device\n",
  1599. __func__);
  1600. status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS);
  1601. ret = swrm_find_alert_slave(swrm, status, &devnum);
  1602. if (ret) {
  1603. dev_err_ratelimited(swrm->dev,
  1604. "%s: no slave alert found.spurious interrupt\n",
  1605. __func__);
  1606. break;
  1607. }
  1608. swrm_cmd_fifo_rd_cmd(swrm, &temp, devnum, 0x0,
  1609. SWRS_SCP_INT_STATUS_CLEAR_1, 1);
  1610. swrm_cmd_fifo_wr_cmd(swrm, 0x4, devnum, 0x0,
  1611. SWRS_SCP_INT_STATUS_CLEAR_1);
  1612. swrm_cmd_fifo_wr_cmd(swrm, 0x0, devnum, 0x0,
  1613. SWRS_SCP_INT_STATUS_CLEAR_1);
  1614. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  1615. if (swr_dev->dev_num != devnum)
  1616. continue;
  1617. if (swr_dev->slave_irq) {
  1618. do {
  1619. swr_dev->slave_irq_pending = 0;
  1620. handle_nested_irq(
  1621. irq_find_mapping(
  1622. swr_dev->slave_irq, 0));
  1623. } while (swr_dev->slave_irq_pending);
  1624. }
  1625. }
  1626. break;
  1627. case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
  1628. dev_dbg(swrm->dev, "%s: SWR new slave attached\n",
  1629. __func__);
  1630. break;
  1631. case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
  1632. status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS);
  1633. swrm_enable_slave_irq(swrm);
  1634. if (status == swrm->slave_status) {
  1635. dev_dbg(swrm->dev,
  1636. "%s: No change in slave status: %d\n",
  1637. __func__, status);
  1638. break;
  1639. }
  1640. chg_sts = swrm_check_slave_change_status(swrm, status,
  1641. &devnum);
  1642. switch (chg_sts) {
  1643. case SWR_NOT_PRESENT:
  1644. dev_dbg(swrm->dev,
  1645. "%s: device %d got detached\n",
  1646. __func__, devnum);
  1647. if (devnum == 0) {
  1648. /*
  1649. * enable host irq if device 0 detached
  1650. * as hw will mask host_irq at slave
  1651. * but will not unmask it afterwards.
  1652. */
  1653. swrm_cmd_fifo_wr_cmd(swrm, 0xFF, devnum, 0x0,
  1654. SWRS_SCP_INT_STATUS_CLEAR_1);
  1655. swrm_cmd_fifo_wr_cmd(swrm, 0x4, devnum, 0x0,
  1656. SWRS_SCP_INT_STATUS_MASK_1);
  1657. }
  1658. break;
  1659. case SWR_ATTACHED_OK:
  1660. dev_dbg(swrm->dev,
  1661. "%s: device %d got attached\n",
  1662. __func__, devnum);
  1663. /* enable host irq from slave device*/
  1664. swrm_cmd_fifo_wr_cmd(swrm, 0xFF, devnum, 0x0,
  1665. SWRS_SCP_INT_STATUS_CLEAR_1);
  1666. swrm_cmd_fifo_wr_cmd(swrm, 0x4, devnum, 0x0,
  1667. SWRS_SCP_INT_STATUS_MASK_1);
  1668. break;
  1669. case SWR_ALERT:
  1670. dev_dbg(swrm->dev,
  1671. "%s: device %d has pending interrupt\n",
  1672. __func__, devnum);
  1673. break;
  1674. }
  1675. break;
  1676. case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
  1677. dev_err_ratelimited(swrm->dev,
  1678. "%s: SWR bus clsh detected\n",
  1679. __func__);
  1680. swrm->intr_mask &=
  1681. ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
  1682. swr_master_write(swrm,
  1683. SWRM_CPU1_INTERRUPT_EN,
  1684. swrm->intr_mask);
  1685. break;
  1686. case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
  1687. dev_dbg(swrm->dev, "%s: SWR read FIFO overflow\n",
  1688. __func__);
  1689. break;
  1690. case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
  1691. dev_dbg(swrm->dev, "%s: SWR read FIFO underflow\n",
  1692. __func__);
  1693. break;
  1694. case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
  1695. dev_dbg(swrm->dev, "%s: SWR write FIFO overflow\n",
  1696. __func__);
  1697. swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
  1698. break;
  1699. case SWRM_INTERRUPT_STATUS_CMD_ERROR:
  1700. value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS);
  1701. dev_err_ratelimited(swrm->dev,
  1702. "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
  1703. __func__, value);
  1704. swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
  1705. break;
  1706. case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
  1707. dev_err_ratelimited(swrm->dev,
  1708. "%s: SWR Port collision detected\n",
  1709. __func__);
  1710. swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
  1711. swr_master_write(swrm,
  1712. SWRM_CPU1_INTERRUPT_EN, swrm->intr_mask);
  1713. break;
  1714. case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
  1715. dev_dbg(swrm->dev,
  1716. "%s: SWR read enable valid mismatch\n",
  1717. __func__);
  1718. swrm->intr_mask &=
  1719. ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
  1720. swr_master_write(swrm,
  1721. SWRM_CPU1_INTERRUPT_EN, swrm->intr_mask);
  1722. break;
  1723. case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
  1724. complete(&swrm->broadcast);
  1725. dev_dbg(swrm->dev, "%s: SWR cmd id finished\n",
  1726. __func__);
  1727. break;
  1728. case SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED:
  1729. swr_master_write(swrm, SWRM_ENUMERATOR_CFG, 0);
  1730. while (swr_master_read(swrm, SWRM_ENUMERATOR_STATUS)) {
  1731. if (!retry) {
  1732. dev_dbg(swrm->dev,
  1733. "%s: ENUM status is not idle\n",
  1734. __func__);
  1735. break;
  1736. }
  1737. retry--;
  1738. }
  1739. swr_master_write(swrm, SWRM_ENUMERATOR_CFG, 1);
  1740. break;
  1741. case SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL:
  1742. break;
  1743. case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED:
  1744. swrm_check_link_status(swrm, 0x1);
  1745. break;
  1746. case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED:
  1747. break;
  1748. case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
  1749. if (swrm->state == SWR_MSTR_UP)
  1750. dev_dbg(swrm->dev,
  1751. "%s:SWR Master is already up\n",
  1752. __func__);
  1753. else
  1754. dev_err_ratelimited(swrm->dev,
  1755. "%s: SWR wokeup during clock stop\n",
  1756. __func__);
  1757. /* It might be possible the slave device gets reset
  1758. * and slave interrupt gets missed. So re-enable
  1759. * Host IRQ and process slave pending
  1760. * interrupts, if any.
  1761. */
  1762. swrm_enable_slave_irq(swrm);
  1763. break;
  1764. default:
  1765. dev_err_ratelimited(swrm->dev,
  1766. "%s: SWR unknown interrupt value: %d\n",
  1767. __func__, value);
  1768. ret = IRQ_NONE;
  1769. break;
  1770. }
  1771. }
  1772. swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
  1773. swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, 0x0);
  1774. intr_sts = swr_master_read(swrm, SWRM_INTERRUPT_STATUS);
  1775. intr_sts_masked = intr_sts & swrm->intr_mask;
  1776. if (intr_sts_masked) {
  1777. dev_dbg(swrm->dev, "%s: new interrupt received 0x%x\n",
  1778. __func__, intr_sts_masked);
  1779. goto handle_irq;
  1780. }
  1781. mutex_lock(&swrm->reslock);
  1782. swrm_clk_request(swrm, false);
  1783. err_audio_core_vote:
  1784. swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false);
  1785. err_audio_hw_vote:
  1786. swrm_request_hw_vote(swrm, LPASS_HW_CORE, false);
  1787. exit:
  1788. mutex_unlock(&swrm->reslock);
  1789. swrm_unlock_sleep(swrm);
  1790. trace_printk("%s exit\n", __func__);
  1791. return ret;
  1792. }
  1793. static irqreturn_t swrm_wakeup_interrupt(int irq, void *dev)
  1794. {
  1795. struct swr_mstr_ctrl *swrm = dev;
  1796. int ret = IRQ_HANDLED;
  1797. if (!swrm || !(swrm->dev)) {
  1798. pr_err("%s: swrm or dev is null\n", __func__);
  1799. return IRQ_NONE;
  1800. }
  1801. trace_printk("%s enter\n", __func__);
  1802. mutex_lock(&swrm->devlock);
  1803. if (!swrm->dev_up) {
  1804. if (swrm->wake_irq > 0) {
  1805. if (unlikely(!irq_get_irq_data(swrm->wake_irq))) {
  1806. pr_err("%s: irq data is NULL\n", __func__);
  1807. mutex_unlock(&swrm->devlock);
  1808. return IRQ_NONE;
  1809. }
  1810. mutex_lock(&swrm->irq_lock);
  1811. if (!irqd_irq_disabled(
  1812. irq_get_irq_data(swrm->wake_irq)))
  1813. disable_irq_nosync(swrm->wake_irq);
  1814. mutex_unlock(&swrm->irq_lock);
  1815. }
  1816. mutex_unlock(&swrm->devlock);
  1817. return ret;
  1818. }
  1819. mutex_unlock(&swrm->devlock);
  1820. if (unlikely(swrm_lock_sleep(swrm) == false)) {
  1821. dev_err(swrm->dev, "%s Failed to hold suspend\n", __func__);
  1822. goto exit;
  1823. }
  1824. if (swrm->wake_irq > 0) {
  1825. if (unlikely(!irq_get_irq_data(swrm->wake_irq))) {
  1826. pr_err("%s: irq data is NULL\n", __func__);
  1827. return IRQ_NONE;
  1828. }
  1829. mutex_lock(&swrm->irq_lock);
  1830. if (!irqd_irq_disabled(
  1831. irq_get_irq_data(swrm->wake_irq)))
  1832. disable_irq_nosync(swrm->wake_irq);
  1833. mutex_unlock(&swrm->irq_lock);
  1834. }
  1835. pm_runtime_get_sync(swrm->dev);
  1836. pm_runtime_mark_last_busy(swrm->dev);
  1837. pm_runtime_put_autosuspend(swrm->dev);
  1838. swrm_unlock_sleep(swrm);
  1839. exit:
  1840. trace_printk("%s exit\n", __func__);
  1841. return ret;
  1842. }
  1843. static void swrm_wakeup_work(struct work_struct *work)
  1844. {
  1845. struct swr_mstr_ctrl *swrm;
  1846. swrm = container_of(work, struct swr_mstr_ctrl,
  1847. wakeup_work);
  1848. if (!swrm || !(swrm->dev)) {
  1849. pr_err("%s: swrm or dev is null\n", __func__);
  1850. return;
  1851. }
  1852. trace_printk("%s enter\n", __func__);
  1853. mutex_lock(&swrm->devlock);
  1854. if (!swrm->dev_up) {
  1855. mutex_unlock(&swrm->devlock);
  1856. goto exit;
  1857. }
  1858. mutex_unlock(&swrm->devlock);
  1859. if (unlikely(swrm_lock_sleep(swrm) == false)) {
  1860. dev_err(swrm->dev, "%s Failed to hold suspend\n", __func__);
  1861. goto exit;
  1862. }
  1863. pm_runtime_get_sync(swrm->dev);
  1864. pm_runtime_mark_last_busy(swrm->dev);
  1865. pm_runtime_put_autosuspend(swrm->dev);
  1866. swrm_unlock_sleep(swrm);
  1867. exit:
  1868. trace_printk("%s exit\n", __func__);
  1869. pm_relax(swrm->dev);
  1870. }
  1871. static int swrm_get_device_status(struct swr_mstr_ctrl *swrm, u8 devnum)
  1872. {
  1873. u32 val;
  1874. swrm->slave_status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS);
  1875. val = (swrm->slave_status >> (devnum * 2));
  1876. val &= SWRM_MCP_SLV_STATUS_MASK;
  1877. return val;
  1878. }
  1879. static int swrm_get_logical_dev_num(struct swr_master *mstr, u64 dev_id,
  1880. u8 *dev_num)
  1881. {
  1882. int i;
  1883. u64 id = 0;
  1884. int ret = -EINVAL;
  1885. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
  1886. struct swr_device *swr_dev;
  1887. u32 num_dev = 0;
  1888. if (!swrm) {
  1889. pr_err("%s: Invalid handle to swr controller\n",
  1890. __func__);
  1891. return ret;
  1892. }
  1893. if (swrm->num_dev)
  1894. num_dev = swrm->num_dev;
  1895. else
  1896. num_dev = mstr->num_dev;
  1897. mutex_lock(&swrm->devlock);
  1898. if (!swrm->dev_up) {
  1899. mutex_unlock(&swrm->devlock);
  1900. return ret;
  1901. }
  1902. mutex_unlock(&swrm->devlock);
  1903. pm_runtime_get_sync(swrm->dev);
  1904. for (i = 1; i < (num_dev + 1); i++) {
  1905. id = ((u64)(swr_master_read(swrm,
  1906. SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i))) << 32);
  1907. id |= swr_master_read(swrm,
  1908. SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i));
  1909. /*
  1910. * As pm_runtime_get_sync() brings all slaves out of reset
  1911. * update logical device number for all slaves.
  1912. */
  1913. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  1914. if (swr_dev->addr == (id & SWR_DEV_ID_MASK)) {
  1915. u32 status = swrm_get_device_status(swrm, i);
  1916. if ((status == 0x01) || (status == 0x02)) {
  1917. swr_dev->dev_num = i;
  1918. if ((id & SWR_DEV_ID_MASK) == dev_id) {
  1919. *dev_num = i;
  1920. ret = 0;
  1921. }
  1922. dev_dbg(swrm->dev,
  1923. "%s: devnum %d is assigned for dev addr %lx\n",
  1924. __func__, i, swr_dev->addr);
  1925. }
  1926. }
  1927. }
  1928. }
  1929. if (ret)
  1930. dev_err(swrm->dev, "%s: device 0x%llx is not ready\n",
  1931. __func__, dev_id);
  1932. pm_runtime_mark_last_busy(swrm->dev);
  1933. pm_runtime_put_autosuspend(swrm->dev);
  1934. return ret;
  1935. }
  1936. static void swrm_device_wakeup_vote(struct swr_master *mstr)
  1937. {
  1938. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
  1939. if (!swrm) {
  1940. pr_err("%s: Invalid handle to swr controller\n",
  1941. __func__);
  1942. return;
  1943. }
  1944. if (unlikely(swrm_lock_sleep(swrm) == false)) {
  1945. dev_err(swrm->dev, "%s Failed to hold suspend\n", __func__);
  1946. return;
  1947. }
  1948. mutex_lock(&swrm->reslock);
  1949. if (swrm_request_hw_vote(swrm, LPASS_HW_CORE, true))
  1950. dev_err(swrm->dev, "%s:lpass core hw enable failed\n",
  1951. __func__);
  1952. if (swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, true))
  1953. dev_err(swrm->dev, "%s:lpass audio hw enable failed\n",
  1954. __func__);
  1955. mutex_unlock(&swrm->reslock);
  1956. pm_runtime_get_sync(swrm->dev);
  1957. }
  1958. static void swrm_device_wakeup_unvote(struct swr_master *mstr)
  1959. {
  1960. struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
  1961. if (!swrm) {
  1962. pr_err("%s: Invalid handle to swr controller\n",
  1963. __func__);
  1964. return;
  1965. }
  1966. pm_runtime_mark_last_busy(swrm->dev);
  1967. pm_runtime_put_autosuspend(swrm->dev);
  1968. mutex_lock(&swrm->reslock);
  1969. swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false);
  1970. swrm_request_hw_vote(swrm, LPASS_HW_CORE, false);
  1971. mutex_unlock(&swrm->reslock);
  1972. swrm_unlock_sleep(swrm);
  1973. }
  1974. static int swrm_master_init(struct swr_mstr_ctrl *swrm)
  1975. {
  1976. int ret = 0;
  1977. u32 val;
  1978. u8 row_ctrl = SWR_ROW_50;
  1979. u8 col_ctrl = SWR_MIN_COL;
  1980. u8 ssp_period = 1;
  1981. u8 retry_cmd_num = 3;
  1982. u32 reg[SWRM_MAX_INIT_REG];
  1983. u32 value[SWRM_MAX_INIT_REG];
  1984. u32 temp = 0;
  1985. int len = 0;
  1986. ssp_period = swrm_get_ssp_period(swrm, SWRM_ROW_50,
  1987. SWRM_COL_02, SWRM_FRAME_SYNC_SEL);
  1988. dev_dbg(swrm->dev, "%s: ssp_period: %d\n", __func__, ssp_period);
  1989. /* Clear Rows and Cols */
  1990. val = ((row_ctrl << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
  1991. (col_ctrl << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
  1992. ((ssp_period - 1) << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
  1993. reg[len] = SWRM_MCP_FRAME_CTRL_BANK(0);
  1994. value[len++] = val;
  1995. /* Set Auto enumeration flag */
  1996. reg[len] = SWRM_ENUMERATOR_CFG;
  1997. value[len++] = 1;
  1998. /* Configure No pings */
  1999. val = swr_master_read(swrm, SWRM_MCP_CFG);
  2000. val &= ~SWRM_NUM_PINGS_MASK;
  2001. val |= (0x1f << SWRM_NUM_PINGS_POS);
  2002. reg[len] = SWRM_MCP_CFG;
  2003. value[len++] = val;
  2004. /* Configure number of retries of a read/write cmd */
  2005. val = (retry_cmd_num);
  2006. reg[len] = SWRM_CMD_FIFO_CFG;
  2007. value[len++] = val;
  2008. reg[len] = SWRM_MCP_BUS_CTRL;
  2009. value[len++] = 0x2;
  2010. /* Set IRQ to PULSE */
  2011. reg[len] = SWRM_COMP_CFG;
  2012. value[len++] = 0x02;
  2013. reg[len] = SWRM_COMP_CFG;
  2014. value[len++] = 0x03;
  2015. reg[len] = SWRM_INTERRUPT_CLEAR;
  2016. value[len++] = 0xFFFFFFFF;
  2017. swrm->intr_mask = SWRM_INTERRUPT_STATUS_MASK;
  2018. /* Mask soundwire interrupts */
  2019. reg[len] = SWRM_INTERRUPT_EN;
  2020. value[len++] = swrm->intr_mask;
  2021. reg[len] = SWRM_CPU1_INTERRUPT_EN;
  2022. value[len++] = swrm->intr_mask;
  2023. swr_master_bulk_write(swrm, reg, value, len);
  2024. if (!swrm_check_link_status(swrm, 0x1)) {
  2025. dev_err(swrm->dev,
  2026. "%s: swr link failed to connect\n",
  2027. __func__);
  2028. return -EINVAL;
  2029. }
  2030. /* Execute it for versions >= 1.5.1 */
  2031. if (swrm->version >= SWRM_VERSION_1_5_1)
  2032. swr_master_write(swrm, SWRM_CMD_FIFO_CFG,
  2033. (swr_master_read(swrm,
  2034. SWRM_CMD_FIFO_CFG) | 0x80000000));
  2035. /* SW workaround to gate hw_ctl for SWR version >=1.6 */
  2036. if (swrm->version >= SWRM_VERSION_1_6) {
  2037. if (swrm->swrm_hctl_reg) {
  2038. temp = ioread32(swrm->swrm_hctl_reg);
  2039. temp &= 0xFFFFFFFD;
  2040. iowrite32(temp, swrm->swrm_hctl_reg);
  2041. }
  2042. }
  2043. return ret;
  2044. }
  2045. static int swrm_event_notify(struct notifier_block *self,
  2046. unsigned long action, void *data)
  2047. {
  2048. struct swr_mstr_ctrl *swrm = container_of(self, struct swr_mstr_ctrl,
  2049. event_notifier);
  2050. if (!swrm || !(swrm->dev)) {
  2051. pr_err("%s: swrm or dev is NULL\n", __func__);
  2052. return -EINVAL;
  2053. }
  2054. switch (action) {
  2055. case MSM_AUD_DC_EVENT:
  2056. schedule_work(&(swrm->dc_presence_work));
  2057. break;
  2058. case SWR_WAKE_IRQ_EVENT:
  2059. if (swrm->ipc_wakeup && !swrm->ipc_wakeup_triggered) {
  2060. swrm->ipc_wakeup_triggered = true;
  2061. pm_stay_awake(swrm->dev);
  2062. schedule_work(&swrm->wakeup_work);
  2063. }
  2064. break;
  2065. default:
  2066. dev_err(swrm->dev, "%s: invalid event type: %lu\n",
  2067. __func__, action);
  2068. return -EINVAL;
  2069. }
  2070. return 0;
  2071. }
  2072. static void swrm_notify_work_fn(struct work_struct *work)
  2073. {
  2074. struct swr_mstr_ctrl *swrm = container_of(work, struct swr_mstr_ctrl,
  2075. dc_presence_work);
  2076. if (!swrm || !swrm->pdev) {
  2077. pr_err("%s: swrm or pdev is NULL\n", __func__);
  2078. return;
  2079. }
  2080. swrm_wcd_notify(swrm->pdev, SWR_DEVICE_DOWN, NULL);
  2081. }
  2082. static int swrm_probe(struct platform_device *pdev)
  2083. {
  2084. struct swr_mstr_ctrl *swrm;
  2085. struct swr_ctrl_platform_data *pdata;
  2086. u32 i, num_ports, port_num, port_type, ch_mask, swrm_hctl_reg = 0;
  2087. u32 *temp, map_size, map_length, ch_iter = 0, old_port_num = 0;
  2088. int ret = 0;
  2089. struct clk *lpass_core_hw_vote = NULL;
  2090. struct clk *lpass_core_audio = NULL;
  2091. /* Allocate soundwire master driver structure */
  2092. swrm = devm_kzalloc(&pdev->dev, sizeof(struct swr_mstr_ctrl),
  2093. GFP_KERNEL);
  2094. if (!swrm) {
  2095. ret = -ENOMEM;
  2096. goto err_memory_fail;
  2097. }
  2098. swrm->pdev = pdev;
  2099. swrm->dev = &pdev->dev;
  2100. platform_set_drvdata(pdev, swrm);
  2101. swr_set_ctrl_data(&swrm->master, swrm);
  2102. pdata = dev_get_platdata(&pdev->dev);
  2103. if (!pdata) {
  2104. dev_err(&pdev->dev, "%s: pdata from parent is NULL\n",
  2105. __func__);
  2106. ret = -EINVAL;
  2107. goto err_pdata_fail;
  2108. }
  2109. swrm->handle = (void *)pdata->handle;
  2110. if (!swrm->handle) {
  2111. dev_err(&pdev->dev, "%s: swrm->handle is NULL\n",
  2112. __func__);
  2113. ret = -EINVAL;
  2114. goto err_pdata_fail;
  2115. }
  2116. ret = of_property_read_u32(pdev->dev.of_node, "qcom,swr_master_id",
  2117. &swrm->master_id);
  2118. if (ret) {
  2119. dev_err(&pdev->dev, "%s: failed to get master id\n", __func__);
  2120. goto err_pdata_fail;
  2121. }
  2122. ret = of_property_read_u32(pdev->dev.of_node, "qcom,dynamic-port-map-supported",
  2123. &swrm->dynamic_port_map_supported);
  2124. if (ret) {
  2125. dev_dbg(&pdev->dev,
  2126. "%s: failed to get dynamic port map support, use default\n",
  2127. __func__);
  2128. swrm->dynamic_port_map_supported = 1;
  2129. }
  2130. if (!(of_property_read_u32(pdev->dev.of_node,
  2131. "swrm-io-base", &swrm->swrm_base_reg)))
  2132. ret = of_property_read_u32(pdev->dev.of_node,
  2133. "swrm-io-base", &swrm->swrm_base_reg);
  2134. if (!swrm->swrm_base_reg) {
  2135. swrm->read = pdata->read;
  2136. if (!swrm->read) {
  2137. dev_err(&pdev->dev, "%s: swrm->read is NULL\n",
  2138. __func__);
  2139. ret = -EINVAL;
  2140. goto err_pdata_fail;
  2141. }
  2142. swrm->write = pdata->write;
  2143. if (!swrm->write) {
  2144. dev_err(&pdev->dev, "%s: swrm->write is NULL\n",
  2145. __func__);
  2146. ret = -EINVAL;
  2147. goto err_pdata_fail;
  2148. }
  2149. swrm->bulk_write = pdata->bulk_write;
  2150. if (!swrm->bulk_write) {
  2151. dev_err(&pdev->dev, "%s: swrm->bulk_write is NULL\n",
  2152. __func__);
  2153. ret = -EINVAL;
  2154. goto err_pdata_fail;
  2155. }
  2156. } else {
  2157. swrm->swrm_dig_base = devm_ioremap(&pdev->dev,
  2158. swrm->swrm_base_reg, SWRM_MAX_REGISTER);
  2159. }
  2160. swrm->core_vote = pdata->core_vote;
  2161. if (!(of_property_read_u32(pdev->dev.of_node,
  2162. "qcom,swrm-hctl-reg", &swrm_hctl_reg)))
  2163. swrm->swrm_hctl_reg = devm_ioremap(&pdev->dev,
  2164. swrm_hctl_reg, 0x4);
  2165. swrm->clk = pdata->clk;
  2166. if (!swrm->clk) {
  2167. dev_err(&pdev->dev, "%s: swrm->clk is NULL\n",
  2168. __func__);
  2169. ret = -EINVAL;
  2170. goto err_pdata_fail;
  2171. }
  2172. if (of_property_read_u32(pdev->dev.of_node,
  2173. "qcom,swr-clock-stop-mode0",
  2174. &swrm->clk_stop_mode0_supp)) {
  2175. swrm->clk_stop_mode0_supp = FALSE;
  2176. }
  2177. ret = of_property_read_u32(swrm->dev->of_node, "qcom,swr-num-dev",
  2178. &swrm->num_dev);
  2179. if (ret) {
  2180. dev_dbg(&pdev->dev, "%s: Looking up %s property failed\n",
  2181. __func__, "qcom,swr-num-dev");
  2182. } else {
  2183. if (swrm->num_dev > SWRM_NUM_AUTO_ENUM_SLAVES) {
  2184. dev_err(&pdev->dev, "%s: num_dev %d > max limit %d\n",
  2185. __func__, swrm->num_dev,
  2186. SWRM_NUM_AUTO_ENUM_SLAVES);
  2187. ret = -EINVAL;
  2188. goto err_pdata_fail;
  2189. }
  2190. }
  2191. /* Parse soundwire port mapping */
  2192. ret = of_property_read_u32(pdev->dev.of_node, "qcom,swr-num-ports",
  2193. &num_ports);
  2194. if (ret) {
  2195. dev_err(swrm->dev, "%s: Failed to get num_ports\n", __func__);
  2196. goto err_pdata_fail;
  2197. }
  2198. swrm->num_ports = num_ports;
  2199. if (!of_find_property(pdev->dev.of_node, "qcom,swr-port-mapping",
  2200. &map_size)) {
  2201. dev_err(swrm->dev, "missing port mapping\n");
  2202. goto err_pdata_fail;
  2203. }
  2204. map_length = map_size / (3 * sizeof(u32));
  2205. if (num_ports > SWR_MSTR_PORT_LEN) {
  2206. dev_err(&pdev->dev, "%s:invalid number of swr ports\n",
  2207. __func__);
  2208. ret = -EINVAL;
  2209. goto err_pdata_fail;
  2210. }
  2211. temp = devm_kzalloc(&pdev->dev, map_size, GFP_KERNEL);
  2212. if (!temp) {
  2213. ret = -ENOMEM;
  2214. goto err_pdata_fail;
  2215. }
  2216. ret = of_property_read_u32_array(pdev->dev.of_node,
  2217. "qcom,swr-port-mapping", temp, 3 * map_length);
  2218. if (ret) {
  2219. dev_err(swrm->dev, "%s: Failed to read port mapping\n",
  2220. __func__);
  2221. goto err_pdata_fail;
  2222. }
  2223. for (i = 0; i < map_length; i++) {
  2224. port_num = temp[3 * i];
  2225. port_type = temp[3 * i + 1];
  2226. ch_mask = temp[3 * i + 2];
  2227. if (port_num != old_port_num)
  2228. ch_iter = 0;
  2229. swrm->port_mapping[port_num][ch_iter].port_type = port_type;
  2230. swrm->port_mapping[port_num][ch_iter++].ch_mask = ch_mask;
  2231. old_port_num = port_num;
  2232. }
  2233. devm_kfree(&pdev->dev, temp);
  2234. swrm->reg_irq = pdata->reg_irq;
  2235. swrm->master.read = swrm_read;
  2236. swrm->master.write = swrm_write;
  2237. swrm->master.bulk_write = swrm_bulk_write;
  2238. swrm->master.get_logical_dev_num = swrm_get_logical_dev_num;
  2239. swrm->master.connect_port = swrm_connect_port;
  2240. swrm->master.disconnect_port = swrm_disconnect_port;
  2241. swrm->master.slvdev_datapath_control = swrm_slvdev_datapath_control;
  2242. swrm->master.remove_from_group = swrm_remove_from_group;
  2243. swrm->master.device_wakeup_vote = swrm_device_wakeup_vote;
  2244. swrm->master.device_wakeup_unvote = swrm_device_wakeup_unvote;
  2245. swrm->master.dev.parent = &pdev->dev;
  2246. swrm->master.dev.of_node = pdev->dev.of_node;
  2247. swrm->master.num_port = 0;
  2248. swrm->rcmd_id = 0;
  2249. swrm->wcmd_id = 0;
  2250. swrm->slave_status = 0;
  2251. swrm->num_rx_chs = 0;
  2252. swrm->clk_ref_count = 0;
  2253. swrm->swr_irq_wakeup_capable = 0;
  2254. swrm->mclk_freq = MCLK_FREQ;
  2255. swrm->bus_clk = MCLK_FREQ;
  2256. swrm->dev_up = true;
  2257. swrm->state = SWR_MSTR_UP;
  2258. swrm->ipc_wakeup = false;
  2259. swrm->ipc_wakeup_triggered = false;
  2260. swrm->disable_div2_clk_switch = FALSE;
  2261. init_completion(&swrm->reset);
  2262. init_completion(&swrm->broadcast);
  2263. init_completion(&swrm->clk_off_complete);
  2264. mutex_init(&swrm->irq_lock);
  2265. mutex_init(&swrm->mlock);
  2266. mutex_init(&swrm->reslock);
  2267. mutex_init(&swrm->force_down_lock);
  2268. mutex_init(&swrm->iolock);
  2269. mutex_init(&swrm->clklock);
  2270. mutex_init(&swrm->devlock);
  2271. mutex_init(&swrm->pm_lock);
  2272. swrm->wlock_holders = 0;
  2273. swrm->pm_state = SWRM_PM_SLEEPABLE;
  2274. init_waitqueue_head(&swrm->pm_wq);
  2275. pm_qos_add_request(&swrm->pm_qos_req,
  2276. PM_QOS_CPU_DMA_LATENCY,
  2277. PM_QOS_DEFAULT_VALUE);
  2278. for (i = 0 ; i < SWR_MSTR_PORT_LEN; i++)
  2279. INIT_LIST_HEAD(&swrm->mport_cfg[i].port_req_list);
  2280. if (of_property_read_u32(pdev->dev.of_node,
  2281. "qcom,disable-div2-clk-switch",
  2282. &swrm->disable_div2_clk_switch)) {
  2283. swrm->disable_div2_clk_switch = FALSE;
  2284. }
  2285. /* Register LPASS core hw vote */
  2286. lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote");
  2287. if (IS_ERR(lpass_core_hw_vote)) {
  2288. ret = PTR_ERR(lpass_core_hw_vote);
  2289. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  2290. __func__, "lpass_core_hw_vote", ret);
  2291. lpass_core_hw_vote = NULL;
  2292. ret = 0;
  2293. }
  2294. swrm->lpass_core_hw_vote = lpass_core_hw_vote;
  2295. /* Register LPASS audio core vote */
  2296. lpass_core_audio = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
  2297. if (IS_ERR(lpass_core_audio)) {
  2298. ret = PTR_ERR(lpass_core_audio);
  2299. dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
  2300. __func__, "lpass_core_audio", ret);
  2301. lpass_core_audio = NULL;
  2302. ret = 0;
  2303. }
  2304. swrm->lpass_core_audio = lpass_core_audio;
  2305. if (swrm->reg_irq) {
  2306. ret = swrm->reg_irq(swrm->handle, swr_mstr_interrupt, swrm,
  2307. SWR_IRQ_REGISTER);
  2308. if (ret) {
  2309. dev_err(&pdev->dev, "%s: IRQ register failed ret %d\n",
  2310. __func__, ret);
  2311. goto err_irq_fail;
  2312. }
  2313. } else {
  2314. swrm->irq = platform_get_irq_byname(pdev, "swr_master_irq");
  2315. if (swrm->irq < 0) {
  2316. dev_err(swrm->dev, "%s() error getting irq hdle: %d\n",
  2317. __func__, swrm->irq);
  2318. goto err_irq_fail;
  2319. }
  2320. ret = request_threaded_irq(swrm->irq, NULL,
  2321. swr_mstr_interrupt,
  2322. IRQF_TRIGGER_RISING | IRQF_ONESHOT,
  2323. "swr_master_irq", swrm);
  2324. if (ret) {
  2325. dev_err(swrm->dev, "%s: Failed to request irq %d\n",
  2326. __func__, ret);
  2327. goto err_irq_fail;
  2328. }
  2329. }
  2330. /* Make inband tx interrupts as wakeup capable for slave irq */
  2331. ret = of_property_read_u32(pdev->dev.of_node,
  2332. "qcom,swr-mstr-irq-wakeup-capable",
  2333. &swrm->swr_irq_wakeup_capable);
  2334. if (ret)
  2335. dev_dbg(swrm->dev, "%s: swrm irq wakeup capable not defined\n",
  2336. __func__);
  2337. if (swrm->swr_irq_wakeup_capable)
  2338. irq_set_irq_wake(swrm->irq, 1);
  2339. ret = swr_register_master(&swrm->master);
  2340. if (ret) {
  2341. dev_err(&pdev->dev, "%s: error adding swr master\n", __func__);
  2342. goto err_mstr_fail;
  2343. }
  2344. /* Add devices registered with board-info as the
  2345. * controller will be up now
  2346. */
  2347. swr_master_add_boarddevices(&swrm->master);
  2348. mutex_lock(&swrm->mlock);
  2349. swrm_clk_request(swrm, true);
  2350. swrm->version = swr_master_read(swrm, SWRM_COMP_HW_VERSION);
  2351. ret = swrm_master_init(swrm);
  2352. if (ret < 0) {
  2353. dev_err(&pdev->dev,
  2354. "%s: Error in master Initialization , err %d\n",
  2355. __func__, ret);
  2356. mutex_unlock(&swrm->mlock);
  2357. goto err_mstr_init_fail;
  2358. }
  2359. mutex_unlock(&swrm->mlock);
  2360. INIT_WORK(&swrm->wakeup_work, swrm_wakeup_work);
  2361. if (pdev->dev.of_node)
  2362. of_register_swr_devices(&swrm->master);
  2363. #ifdef CONFIG_DEBUG_FS
  2364. swrm->debugfs_swrm_dent = debugfs_create_dir(dev_name(&pdev->dev), 0);
  2365. if (!IS_ERR(swrm->debugfs_swrm_dent)) {
  2366. swrm->debugfs_peek = debugfs_create_file("swrm_peek",
  2367. S_IFREG | 0444, swrm->debugfs_swrm_dent,
  2368. (void *) swrm, &swrm_debug_read_ops);
  2369. swrm->debugfs_poke = debugfs_create_file("swrm_poke",
  2370. S_IFREG | 0444, swrm->debugfs_swrm_dent,
  2371. (void *) swrm, &swrm_debug_write_ops);
  2372. swrm->debugfs_reg_dump = debugfs_create_file("swrm_reg_dump",
  2373. S_IFREG | 0444, swrm->debugfs_swrm_dent,
  2374. (void *) swrm,
  2375. &swrm_debug_dump_ops);
  2376. }
  2377. #endif
  2378. ret = device_init_wakeup(swrm->dev, true);
  2379. if (ret) {
  2380. dev_err(swrm->dev, "Device wakeup init failed: %d\n", ret);
  2381. goto err_irq_wakeup_fail;
  2382. }
  2383. pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer);
  2384. pm_runtime_use_autosuspend(&pdev->dev);
  2385. pm_runtime_set_active(&pdev->dev);
  2386. pm_runtime_enable(&pdev->dev);
  2387. pm_runtime_mark_last_busy(&pdev->dev);
  2388. INIT_WORK(&swrm->dc_presence_work, swrm_notify_work_fn);
  2389. swrm->event_notifier.notifier_call = swrm_event_notify;
  2390. msm_aud_evt_register_client(&swrm->event_notifier);
  2391. return 0;
  2392. err_irq_wakeup_fail:
  2393. device_init_wakeup(swrm->dev, false);
  2394. err_mstr_init_fail:
  2395. swr_unregister_master(&swrm->master);
  2396. err_mstr_fail:
  2397. if (swrm->reg_irq)
  2398. swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
  2399. swrm, SWR_IRQ_FREE);
  2400. else if (swrm->irq)
  2401. free_irq(swrm->irq, swrm);
  2402. err_irq_fail:
  2403. mutex_destroy(&swrm->irq_lock);
  2404. mutex_destroy(&swrm->mlock);
  2405. mutex_destroy(&swrm->reslock);
  2406. mutex_destroy(&swrm->force_down_lock);
  2407. mutex_destroy(&swrm->iolock);
  2408. mutex_destroy(&swrm->clklock);
  2409. mutex_destroy(&swrm->pm_lock);
  2410. pm_qos_remove_request(&swrm->pm_qos_req);
  2411. err_pdata_fail:
  2412. err_memory_fail:
  2413. return ret;
  2414. }
  2415. static int swrm_remove(struct platform_device *pdev)
  2416. {
  2417. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  2418. if (swrm->reg_irq)
  2419. swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
  2420. swrm, SWR_IRQ_FREE);
  2421. else if (swrm->irq)
  2422. free_irq(swrm->irq, swrm);
  2423. else if (swrm->wake_irq > 0)
  2424. free_irq(swrm->wake_irq, swrm);
  2425. if (swrm->swr_irq_wakeup_capable)
  2426. irq_set_irq_wake(swrm->irq, 0);
  2427. cancel_work_sync(&swrm->wakeup_work);
  2428. pm_runtime_disable(&pdev->dev);
  2429. pm_runtime_set_suspended(&pdev->dev);
  2430. swr_unregister_master(&swrm->master);
  2431. msm_aud_evt_unregister_client(&swrm->event_notifier);
  2432. device_init_wakeup(swrm->dev, false);
  2433. mutex_destroy(&swrm->irq_lock);
  2434. mutex_destroy(&swrm->mlock);
  2435. mutex_destroy(&swrm->reslock);
  2436. mutex_destroy(&swrm->iolock);
  2437. mutex_destroy(&swrm->clklock);
  2438. mutex_destroy(&swrm->force_down_lock);
  2439. mutex_destroy(&swrm->pm_lock);
  2440. pm_qos_remove_request(&swrm->pm_qos_req);
  2441. devm_kfree(&pdev->dev, swrm);
  2442. return 0;
  2443. }
  2444. static int swrm_clk_pause(struct swr_mstr_ctrl *swrm)
  2445. {
  2446. u32 val;
  2447. dev_dbg(swrm->dev, "%s: state: %d\n", __func__, swrm->state);
  2448. swr_master_write(swrm, SWRM_INTERRUPT_EN, 0x1FDFD);
  2449. val = swr_master_read(swrm, SWRM_MCP_CFG);
  2450. val |= 0x02;
  2451. swr_master_write(swrm, SWRM_MCP_CFG, val);
  2452. return 0;
  2453. }
  2454. #ifdef CONFIG_PM
  2455. static int swrm_runtime_resume(struct device *dev)
  2456. {
  2457. struct platform_device *pdev = to_platform_device(dev);
  2458. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  2459. int ret = 0;
  2460. bool swrm_clk_req_err = false;
  2461. bool hw_core_err = false;
  2462. bool aud_core_err = false;
  2463. struct swr_master *mstr = &swrm->master;
  2464. struct swr_device *swr_dev;
  2465. u32 temp = 0;
  2466. dev_dbg(dev, "%s: pm_runtime: resume, state:%d\n",
  2467. __func__, swrm->state);
  2468. trace_printk("%s: pm_runtime: resume, state:%d\n",
  2469. __func__, swrm->state);
  2470. mutex_lock(&swrm->reslock);
  2471. if (swrm_request_hw_vote(swrm, LPASS_HW_CORE, true)) {
  2472. dev_err(dev, "%s:lpass core hw enable failed\n",
  2473. __func__);
  2474. hw_core_err = true;
  2475. }
  2476. if (swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, true)) {
  2477. dev_err(dev, "%s:lpass audio hw enable failed\n",
  2478. __func__);
  2479. aud_core_err = true;
  2480. }
  2481. if ((swrm->state == SWR_MSTR_DOWN) ||
  2482. (swrm->state == SWR_MSTR_SSR && swrm->dev_up)) {
  2483. if (swrm->clk_stop_mode0_supp) {
  2484. if (swrm->wake_irq > 0) {
  2485. if (unlikely(!irq_get_irq_data
  2486. (swrm->wake_irq))) {
  2487. pr_err("%s: irq data is NULL\n",
  2488. __func__);
  2489. mutex_unlock(&swrm->reslock);
  2490. return IRQ_NONE;
  2491. }
  2492. mutex_lock(&swrm->irq_lock);
  2493. if (!irqd_irq_disabled(
  2494. irq_get_irq_data(swrm->wake_irq)))
  2495. disable_irq_nosync(swrm->wake_irq);
  2496. mutex_unlock(&swrm->irq_lock);
  2497. }
  2498. if (swrm->ipc_wakeup)
  2499. msm_aud_evt_blocking_notifier_call_chain(
  2500. SWR_WAKE_IRQ_DEREGISTER, (void *)swrm);
  2501. }
  2502. if (swrm_clk_request(swrm, true)) {
  2503. /*
  2504. * Set autosuspend timer to 1 for
  2505. * master to enter into suspend.
  2506. */
  2507. swrm_clk_req_err = true;
  2508. goto exit;
  2509. }
  2510. if (!swrm->clk_stop_mode0_supp || swrm->state == SWR_MSTR_SSR) {
  2511. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  2512. ret = swr_device_up(swr_dev);
  2513. if (ret == -ENODEV) {
  2514. dev_dbg(dev,
  2515. "%s slave device up not implemented\n",
  2516. __func__);
  2517. trace_printk(
  2518. "%s slave device up not implemented\n",
  2519. __func__);
  2520. ret = 0;
  2521. } else if (ret) {
  2522. dev_err(dev,
  2523. "%s: failed to wakeup swr dev %d\n",
  2524. __func__, swr_dev->dev_num);
  2525. swrm_clk_request(swrm, false);
  2526. goto exit;
  2527. }
  2528. }
  2529. swr_master_write(swrm, SWRM_COMP_SW_RESET, 0x01);
  2530. swr_master_write(swrm, SWRM_COMP_SW_RESET, 0x01);
  2531. swr_master_write(swrm, SWRM_MCP_BUS_CTRL, 0x01);
  2532. swrm_master_init(swrm);
  2533. /* wait for hw enumeration to complete */
  2534. usleep_range(100, 105);
  2535. if (!swrm_check_link_status(swrm, 0x1))
  2536. dev_dbg(dev, "%s:failed in connecting, ssr?\n",
  2537. __func__);
  2538. swrm_cmd_fifo_wr_cmd(swrm, 0x4, 0xF, 0x0,
  2539. SWRS_SCP_INT_STATUS_MASK_1);
  2540. if (swrm->state == SWR_MSTR_SSR) {
  2541. mutex_unlock(&swrm->reslock);
  2542. enable_bank_switch(swrm, 0, SWR_ROW_50, SWR_MIN_COL);
  2543. mutex_lock(&swrm->reslock);
  2544. }
  2545. } else {
  2546. if (swrm->swrm_hctl_reg) {
  2547. temp = ioread32(swrm->swrm_hctl_reg);
  2548. temp &= 0xFFFFFFFD;
  2549. iowrite32(temp, swrm->swrm_hctl_reg);
  2550. }
  2551. /*wake up from clock stop*/
  2552. swr_master_write(swrm, SWRM_MCP_BUS_CTRL, 0x2);
  2553. /* clear and enable bus clash interrupt */
  2554. swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, 0x08);
  2555. swrm->intr_mask |= 0x08;
  2556. swr_master_write(swrm, SWRM_INTERRUPT_EN,
  2557. swrm->intr_mask);
  2558. swr_master_write(swrm,
  2559. SWRM_CPU1_INTERRUPT_EN,
  2560. swrm->intr_mask);
  2561. usleep_range(100, 105);
  2562. if (!swrm_check_link_status(swrm, 0x1))
  2563. dev_dbg(dev, "%s:failed in connecting, ssr?\n",
  2564. __func__);
  2565. }
  2566. swrm->state = SWR_MSTR_UP;
  2567. }
  2568. exit:
  2569. if (!aud_core_err)
  2570. swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false);
  2571. if (!hw_core_err)
  2572. swrm_request_hw_vote(swrm, LPASS_HW_CORE, false);
  2573. if (swrm_clk_req_err)
  2574. pm_runtime_set_autosuspend_delay(&pdev->dev,
  2575. ERR_AUTO_SUSPEND_TIMER_VAL);
  2576. else
  2577. pm_runtime_set_autosuspend_delay(&pdev->dev,
  2578. auto_suspend_timer);
  2579. mutex_unlock(&swrm->reslock);
  2580. trace_printk("%s: pm_runtime: resume done, state:%d\n",
  2581. __func__, swrm->state);
  2582. return ret;
  2583. }
  2584. static int swrm_runtime_suspend(struct device *dev)
  2585. {
  2586. struct platform_device *pdev = to_platform_device(dev);
  2587. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  2588. int ret = 0;
  2589. bool hw_core_err = false;
  2590. bool aud_core_err = false;
  2591. struct swr_master *mstr = &swrm->master;
  2592. struct swr_device *swr_dev;
  2593. int current_state = 0;
  2594. trace_printk("%s: pm_runtime: suspend state: %d\n",
  2595. __func__, swrm->state);
  2596. dev_dbg(dev, "%s: pm_runtime: suspend state: %d\n",
  2597. __func__, swrm->state);
  2598. mutex_lock(&swrm->reslock);
  2599. mutex_lock(&swrm->force_down_lock);
  2600. current_state = swrm->state;
  2601. mutex_unlock(&swrm->force_down_lock);
  2602. if (swrm_request_hw_vote(swrm, LPASS_HW_CORE, true)) {
  2603. dev_err(dev, "%s:lpass core hw enable failed\n",
  2604. __func__);
  2605. hw_core_err = true;
  2606. }
  2607. if (swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, true)) {
  2608. dev_err(dev, "%s:lpass audio hw enable failed\n",
  2609. __func__);
  2610. aud_core_err = true;
  2611. }
  2612. if ((current_state == SWR_MSTR_UP) ||
  2613. (current_state == SWR_MSTR_SSR)) {
  2614. if ((current_state != SWR_MSTR_SSR) &&
  2615. swrm_is_port_en(&swrm->master)) {
  2616. dev_dbg(dev, "%s ports are enabled\n", __func__);
  2617. trace_printk("%s ports are enabled\n", __func__);
  2618. ret = -EBUSY;
  2619. goto exit;
  2620. }
  2621. if (!swrm->clk_stop_mode0_supp || swrm->state == SWR_MSTR_SSR) {
  2622. dev_err(dev, "%s: clk stop mode not supported or SSR entry\n",
  2623. __func__);
  2624. mutex_unlock(&swrm->reslock);
  2625. enable_bank_switch(swrm, 0, SWR_ROW_50, SWR_MIN_COL);
  2626. mutex_lock(&swrm->reslock);
  2627. swrm_clk_pause(swrm);
  2628. swr_master_write(swrm, SWRM_COMP_CFG, 0x00);
  2629. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  2630. ret = swr_device_down(swr_dev);
  2631. if (ret == -ENODEV) {
  2632. dev_dbg_ratelimited(dev,
  2633. "%s slave device down not implemented\n",
  2634. __func__);
  2635. trace_printk(
  2636. "%s slave device down not implemented\n",
  2637. __func__);
  2638. ret = 0;
  2639. } else if (ret) {
  2640. dev_err(dev,
  2641. "%s: failed to shutdown swr dev %d\n",
  2642. __func__, swr_dev->dev_num);
  2643. trace_printk(
  2644. "%s: failed to shutdown swr dev %d\n",
  2645. __func__, swr_dev->dev_num);
  2646. goto exit;
  2647. }
  2648. }
  2649. trace_printk("%s: clk stop mode not supported or SSR exit\n",
  2650. __func__);
  2651. } else {
  2652. /* Mask bus clash interrupt */
  2653. swrm->intr_mask &= ~((u32)0x08);
  2654. swr_master_write(swrm, SWRM_INTERRUPT_EN,
  2655. swrm->intr_mask);
  2656. swr_master_write(swrm,
  2657. SWRM_CPU1_INTERRUPT_EN,
  2658. swrm->intr_mask);
  2659. mutex_unlock(&swrm->reslock);
  2660. /* clock stop sequence */
  2661. swrm_cmd_fifo_wr_cmd(swrm, 0x2, 0xF, 0xF,
  2662. SWRS_SCP_CONTROL);
  2663. mutex_lock(&swrm->reslock);
  2664. usleep_range(100, 105);
  2665. }
  2666. if (!swrm_check_link_status(swrm, 0x0))
  2667. dev_dbg(dev, "%s:failed in disconnecting, ssr?\n",
  2668. __func__);
  2669. ret = swrm_clk_request(swrm, false);
  2670. if (ret) {
  2671. dev_err(dev, "%s: swrmn clk failed\n", __func__);
  2672. ret = 0;
  2673. goto exit;
  2674. }
  2675. if (swrm->clk_stop_mode0_supp) {
  2676. if (swrm->wake_irq > 0) {
  2677. enable_irq(swrm->wake_irq);
  2678. } else if (swrm->ipc_wakeup) {
  2679. msm_aud_evt_blocking_notifier_call_chain(
  2680. SWR_WAKE_IRQ_REGISTER, (void *)swrm);
  2681. swrm->ipc_wakeup_triggered = false;
  2682. }
  2683. }
  2684. }
  2685. /* Retain SSR state until resume */
  2686. if (current_state != SWR_MSTR_SSR)
  2687. swrm->state = SWR_MSTR_DOWN;
  2688. exit:
  2689. if (!aud_core_err)
  2690. swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false);
  2691. if (!hw_core_err)
  2692. swrm_request_hw_vote(swrm, LPASS_HW_CORE, false);
  2693. mutex_unlock(&swrm->reslock);
  2694. trace_printk("%s: pm_runtime: suspend done state: %d\n",
  2695. __func__, swrm->state);
  2696. return ret;
  2697. }
  2698. #endif /* CONFIG_PM */
  2699. static int swrm_device_suspend(struct device *dev)
  2700. {
  2701. struct platform_device *pdev = to_platform_device(dev);
  2702. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  2703. int ret = 0;
  2704. dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state);
  2705. trace_printk("%s: swrm state: %d\n", __func__, swrm->state);
  2706. if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
  2707. ret = swrm_runtime_suspend(dev);
  2708. if (!ret) {
  2709. pm_runtime_disable(dev);
  2710. pm_runtime_set_suspended(dev);
  2711. pm_runtime_enable(dev);
  2712. }
  2713. }
  2714. return 0;
  2715. }
  2716. static int swrm_device_down(struct device *dev)
  2717. {
  2718. struct platform_device *pdev = to_platform_device(dev);
  2719. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  2720. dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state);
  2721. trace_printk("%s: swrm state: %d\n", __func__, swrm->state);
  2722. mutex_lock(&swrm->force_down_lock);
  2723. swrm->state = SWR_MSTR_SSR;
  2724. mutex_unlock(&swrm->force_down_lock);
  2725. swrm_device_suspend(dev);
  2726. return 0;
  2727. }
  2728. int swrm_register_wake_irq(struct swr_mstr_ctrl *swrm)
  2729. {
  2730. int ret = 0;
  2731. int irq, dir_apps_irq;
  2732. if (!swrm->ipc_wakeup) {
  2733. irq = of_get_named_gpio(swrm->dev->of_node,
  2734. "qcom,swr-wakeup-irq", 0);
  2735. if (gpio_is_valid(irq)) {
  2736. swrm->wake_irq = gpio_to_irq(irq);
  2737. if (swrm->wake_irq < 0) {
  2738. dev_err(swrm->dev,
  2739. "Unable to configure irq\n");
  2740. return swrm->wake_irq;
  2741. }
  2742. } else {
  2743. dir_apps_irq = platform_get_irq_byname(swrm->pdev,
  2744. "swr_wake_irq");
  2745. if (dir_apps_irq < 0) {
  2746. dev_err(swrm->dev,
  2747. "TLMM connect gpio not found\n");
  2748. return -EINVAL;
  2749. }
  2750. swrm->wake_irq = dir_apps_irq;
  2751. }
  2752. ret = request_threaded_irq(swrm->wake_irq, NULL,
  2753. swrm_wakeup_interrupt,
  2754. IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
  2755. "swr_wake_irq", swrm);
  2756. if (ret) {
  2757. dev_err(swrm->dev, "%s: Failed to request irq %d\n",
  2758. __func__, ret);
  2759. return -EINVAL;
  2760. }
  2761. irq_set_irq_wake(swrm->wake_irq, 1);
  2762. }
  2763. return ret;
  2764. }
  2765. static int swrm_alloc_port_mem(struct device *dev, struct swr_mstr_ctrl *swrm,
  2766. u32 uc, u32 size)
  2767. {
  2768. if (!swrm->port_param) {
  2769. swrm->port_param = devm_kzalloc(dev,
  2770. sizeof(swrm->port_param) * SWR_UC_MAX,
  2771. GFP_KERNEL);
  2772. if (!swrm->port_param)
  2773. return -ENOMEM;
  2774. }
  2775. if (!swrm->port_param[uc]) {
  2776. swrm->port_param[uc] = devm_kcalloc(dev, size,
  2777. sizeof(struct port_params),
  2778. GFP_KERNEL);
  2779. if (!swrm->port_param[uc])
  2780. return -ENOMEM;
  2781. } else {
  2782. dev_err_ratelimited(swrm->dev, "%s: called more than once\n",
  2783. __func__);
  2784. }
  2785. return 0;
  2786. }
  2787. static int swrm_copy_port_config(struct swr_mstr_ctrl *swrm,
  2788. struct swrm_port_config *port_cfg,
  2789. u32 size)
  2790. {
  2791. int idx;
  2792. struct port_params *params;
  2793. int uc = port_cfg->uc;
  2794. int ret = 0;
  2795. for (idx = 0; idx < size; idx++) {
  2796. params = &((struct port_params *)port_cfg->params)[idx];
  2797. if (!params) {
  2798. dev_err(swrm->dev, "%s: Invalid params\n", __func__);
  2799. ret = -EINVAL;
  2800. break;
  2801. }
  2802. memcpy(&swrm->port_param[uc][idx], params,
  2803. sizeof(struct port_params));
  2804. }
  2805. return ret;
  2806. }
  2807. /**
  2808. * swrm_wcd_notify - parent device can notify to soundwire master through
  2809. * this function
  2810. * @pdev: pointer to platform device structure
  2811. * @id: command id from parent to the soundwire master
  2812. * @data: data from parent device to soundwire master
  2813. */
  2814. int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data)
  2815. {
  2816. struct swr_mstr_ctrl *swrm;
  2817. int ret = 0;
  2818. struct swr_master *mstr;
  2819. struct swr_device *swr_dev;
  2820. struct swrm_port_config *port_cfg;
  2821. if (!pdev) {
  2822. pr_err("%s: pdev is NULL\n", __func__);
  2823. return -EINVAL;
  2824. }
  2825. swrm = platform_get_drvdata(pdev);
  2826. if (!swrm) {
  2827. dev_err(&pdev->dev, "%s: swrm is NULL\n", __func__);
  2828. return -EINVAL;
  2829. }
  2830. mstr = &swrm->master;
  2831. switch (id) {
  2832. case SWR_REQ_CLK_SWITCH:
  2833. /* This will put soundwire in clock stop mode and disable the
  2834. * clocks, if there is no active usecase running, so that the
  2835. * next activity on soundwire will request clock from new clock
  2836. * source.
  2837. */
  2838. if (!data) {
  2839. dev_err(swrm->dev, "%s: data is NULL for id:%d\n",
  2840. __func__, id);
  2841. ret = -EINVAL;
  2842. break;
  2843. }
  2844. mutex_lock(&swrm->mlock);
  2845. if (swrm->clk_src != *(int *)data) {
  2846. if (swrm->state == SWR_MSTR_UP)
  2847. swrm_device_suspend(&pdev->dev);
  2848. swrm->clk_src = *(int *)data;
  2849. }
  2850. mutex_unlock(&swrm->mlock);
  2851. break;
  2852. case SWR_CLK_FREQ:
  2853. if (!data) {
  2854. dev_err(swrm->dev, "%s: data is NULL\n", __func__);
  2855. ret = -EINVAL;
  2856. } else {
  2857. mutex_lock(&swrm->mlock);
  2858. if (swrm->mclk_freq != *(int *)data) {
  2859. dev_dbg(swrm->dev, "%s: freq change: force mstr down\n", __func__);
  2860. if (swrm->state == SWR_MSTR_DOWN)
  2861. dev_dbg(swrm->dev, "%s:SWR master is already Down:%d\n",
  2862. __func__, swrm->state);
  2863. else {
  2864. swrm->mclk_freq = *(int *)data;
  2865. swrm->bus_clk = swrm->mclk_freq;
  2866. swrm_switch_frame_shape(swrm,
  2867. swrm->bus_clk);
  2868. swrm_device_suspend(&pdev->dev);
  2869. }
  2870. /*
  2871. * add delay to ensure clk release happen
  2872. * if interrupt triggered for clk stop,
  2873. * wait for it to exit
  2874. */
  2875. usleep_range(10000, 10500);
  2876. }
  2877. swrm->mclk_freq = *(int *)data;
  2878. swrm->bus_clk = swrm->mclk_freq;
  2879. mutex_unlock(&swrm->mlock);
  2880. }
  2881. break;
  2882. case SWR_DEVICE_SSR_DOWN:
  2883. trace_printk("%s: swr device down called\n", __func__);
  2884. mutex_lock(&swrm->mlock);
  2885. if (swrm->state == SWR_MSTR_DOWN)
  2886. dev_dbg(swrm->dev, "%s:SWR master is already Down:%d\n",
  2887. __func__, swrm->state);
  2888. else
  2889. swrm_device_down(&pdev->dev);
  2890. mutex_lock(&swrm->devlock);
  2891. swrm->dev_up = false;
  2892. mutex_unlock(&swrm->devlock);
  2893. mutex_lock(&swrm->reslock);
  2894. swrm->state = SWR_MSTR_SSR;
  2895. mutex_unlock(&swrm->reslock);
  2896. mutex_unlock(&swrm->mlock);
  2897. break;
  2898. case SWR_DEVICE_SSR_UP:
  2899. /* wait for clk voting to be zero */
  2900. trace_printk("%s: swr device up called\n", __func__);
  2901. reinit_completion(&swrm->clk_off_complete);
  2902. if (swrm->clk_ref_count &&
  2903. !wait_for_completion_timeout(&swrm->clk_off_complete,
  2904. msecs_to_jiffies(500)))
  2905. dev_err(swrm->dev, "%s: clock voting not zero\n",
  2906. __func__);
  2907. mutex_lock(&swrm->devlock);
  2908. swrm->dev_up = true;
  2909. mutex_unlock(&swrm->devlock);
  2910. break;
  2911. case SWR_DEVICE_DOWN:
  2912. dev_dbg(swrm->dev, "%s: swr master down called\n", __func__);
  2913. trace_printk("%s: swr master down called\n", __func__);
  2914. mutex_lock(&swrm->mlock);
  2915. if (swrm->state == SWR_MSTR_DOWN)
  2916. dev_dbg(swrm->dev, "%s:SWR master is already Down:%d\n",
  2917. __func__, swrm->state);
  2918. else
  2919. swrm_device_down(&pdev->dev);
  2920. mutex_unlock(&swrm->mlock);
  2921. break;
  2922. case SWR_DEVICE_UP:
  2923. dev_dbg(swrm->dev, "%s: swr master up called\n", __func__);
  2924. trace_printk("%s: swr master up called\n", __func__);
  2925. mutex_lock(&swrm->devlock);
  2926. if (!swrm->dev_up) {
  2927. dev_dbg(swrm->dev, "SSR not complete yet\n");
  2928. mutex_unlock(&swrm->devlock);
  2929. return -EBUSY;
  2930. }
  2931. mutex_unlock(&swrm->devlock);
  2932. mutex_lock(&swrm->mlock);
  2933. pm_runtime_mark_last_busy(&pdev->dev);
  2934. pm_runtime_get_sync(&pdev->dev);
  2935. mutex_lock(&swrm->reslock);
  2936. list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
  2937. ret = swr_reset_device(swr_dev);
  2938. if (ret == -ENODEV) {
  2939. dev_dbg_ratelimited(swrm->dev,
  2940. "%s slave reset not implemented\n",
  2941. __func__);
  2942. ret = 0;
  2943. } else if (ret) {
  2944. dev_err(swrm->dev,
  2945. "%s: failed to reset swr device %d\n",
  2946. __func__, swr_dev->dev_num);
  2947. swrm_clk_request(swrm, false);
  2948. }
  2949. }
  2950. pm_runtime_mark_last_busy(&pdev->dev);
  2951. pm_runtime_put_autosuspend(&pdev->dev);
  2952. mutex_unlock(&swrm->reslock);
  2953. mutex_unlock(&swrm->mlock);
  2954. break;
  2955. case SWR_SET_NUM_RX_CH:
  2956. if (!data) {
  2957. dev_err(swrm->dev, "%s: data is NULL\n", __func__);
  2958. ret = -EINVAL;
  2959. } else {
  2960. mutex_lock(&swrm->mlock);
  2961. swrm->num_rx_chs = *(int *)data;
  2962. if ((swrm->num_rx_chs > 1) && !swrm->num_cfg_devs) {
  2963. list_for_each_entry(swr_dev, &mstr->devices,
  2964. dev_list) {
  2965. ret = swr_set_device_group(swr_dev,
  2966. SWR_BROADCAST);
  2967. if (ret)
  2968. dev_err(swrm->dev,
  2969. "%s: set num ch failed\n",
  2970. __func__);
  2971. }
  2972. } else {
  2973. list_for_each_entry(swr_dev, &mstr->devices,
  2974. dev_list) {
  2975. ret = swr_set_device_group(swr_dev,
  2976. SWR_GROUP_NONE);
  2977. if (ret)
  2978. dev_err(swrm->dev,
  2979. "%s: set num ch failed\n",
  2980. __func__);
  2981. }
  2982. }
  2983. mutex_unlock(&swrm->mlock);
  2984. }
  2985. break;
  2986. case SWR_REGISTER_WAKE_IRQ:
  2987. if (!data) {
  2988. dev_err(swrm->dev, "%s: reg wake irq data is NULL\n",
  2989. __func__);
  2990. ret = -EINVAL;
  2991. } else {
  2992. mutex_lock(&swrm->mlock);
  2993. swrm->ipc_wakeup = *(u32 *)data;
  2994. ret = swrm_register_wake_irq(swrm);
  2995. if (ret)
  2996. dev_err(swrm->dev, "%s: register wake_irq failed\n",
  2997. __func__);
  2998. mutex_unlock(&swrm->mlock);
  2999. }
  3000. break;
  3001. case SWR_REGISTER_WAKEUP:
  3002. msm_aud_evt_blocking_notifier_call_chain(
  3003. SWR_WAKE_IRQ_REGISTER, (void *)swrm);
  3004. break;
  3005. case SWR_DEREGISTER_WAKEUP:
  3006. msm_aud_evt_blocking_notifier_call_chain(
  3007. SWR_WAKE_IRQ_DEREGISTER, (void *)swrm);
  3008. break;
  3009. case SWR_SET_PORT_MAP:
  3010. if (!data) {
  3011. dev_err(swrm->dev, "%s: data is NULL for id=%d\n",
  3012. __func__, id);
  3013. ret = -EINVAL;
  3014. } else {
  3015. mutex_lock(&swrm->mlock);
  3016. port_cfg = (struct swrm_port_config *)data;
  3017. if (!port_cfg->size) {
  3018. ret = -EINVAL;
  3019. goto done;
  3020. }
  3021. ret = swrm_alloc_port_mem(&pdev->dev, swrm,
  3022. port_cfg->uc, port_cfg->size);
  3023. if (!ret)
  3024. swrm_copy_port_config(swrm, port_cfg,
  3025. port_cfg->size);
  3026. done:
  3027. mutex_unlock(&swrm->mlock);
  3028. }
  3029. break;
  3030. default:
  3031. dev_err(swrm->dev, "%s: swr master unknown id %d\n",
  3032. __func__, id);
  3033. break;
  3034. }
  3035. return ret;
  3036. }
  3037. EXPORT_SYMBOL(swrm_wcd_notify);
  3038. /*
  3039. * swrm_pm_cmpxchg:
  3040. * Check old state and exchange with pm new state
  3041. * if old state matches with current state
  3042. *
  3043. * @swrm: pointer to wcd core resource
  3044. * @o: pm old state
  3045. * @n: pm new state
  3046. *
  3047. * Returns old state
  3048. */
  3049. static enum swrm_pm_state swrm_pm_cmpxchg(
  3050. struct swr_mstr_ctrl *swrm,
  3051. enum swrm_pm_state o,
  3052. enum swrm_pm_state n)
  3053. {
  3054. enum swrm_pm_state old;
  3055. if (!swrm)
  3056. return o;
  3057. mutex_lock(&swrm->pm_lock);
  3058. old = swrm->pm_state;
  3059. if (old == o)
  3060. swrm->pm_state = n;
  3061. mutex_unlock(&swrm->pm_lock);
  3062. return old;
  3063. }
  3064. static bool swrm_lock_sleep(struct swr_mstr_ctrl *swrm)
  3065. {
  3066. enum swrm_pm_state os;
  3067. /*
  3068. * swrm_{lock/unlock}_sleep will be called by swr irq handler
  3069. * and slave wake up requests..
  3070. *
  3071. * If system didn't resume, we can simply return false so
  3072. * IRQ handler can return without handling IRQ.
  3073. */
  3074. mutex_lock(&swrm->pm_lock);
  3075. if (swrm->wlock_holders++ == 0) {
  3076. dev_dbg(swrm->dev, "%s: holding wake lock\n", __func__);
  3077. pm_qos_update_request(&swrm->pm_qos_req,
  3078. msm_cpuidle_get_deep_idle_latency());
  3079. pm_stay_awake(swrm->dev);
  3080. }
  3081. mutex_unlock(&swrm->pm_lock);
  3082. if (!wait_event_timeout(swrm->pm_wq,
  3083. ((os = swrm_pm_cmpxchg(swrm,
  3084. SWRM_PM_SLEEPABLE,
  3085. SWRM_PM_AWAKE)) ==
  3086. SWRM_PM_SLEEPABLE ||
  3087. (os == SWRM_PM_AWAKE)),
  3088. msecs_to_jiffies(
  3089. SWRM_SYSTEM_RESUME_TIMEOUT_MS))) {
  3090. dev_err(swrm->dev, "%s: system didn't resume within %dms, s %d, w %d\n",
  3091. __func__, SWRM_SYSTEM_RESUME_TIMEOUT_MS, swrm->pm_state,
  3092. swrm->wlock_holders);
  3093. swrm_unlock_sleep(swrm);
  3094. return false;
  3095. }
  3096. wake_up_all(&swrm->pm_wq);
  3097. return true;
  3098. }
  3099. static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm)
  3100. {
  3101. mutex_lock(&swrm->pm_lock);
  3102. if (--swrm->wlock_holders == 0) {
  3103. dev_dbg(swrm->dev, "%s: releasing wake lock pm_state %d -> %d\n",
  3104. __func__, swrm->pm_state, SWRM_PM_SLEEPABLE);
  3105. /*
  3106. * if swrm_lock_sleep failed, pm_state would be still
  3107. * swrm_PM_ASLEEP, don't overwrite
  3108. */
  3109. if (likely(swrm->pm_state == SWRM_PM_AWAKE))
  3110. swrm->pm_state = SWRM_PM_SLEEPABLE;
  3111. pm_qos_update_request(&swrm->pm_qos_req,
  3112. PM_QOS_DEFAULT_VALUE);
  3113. pm_relax(swrm->dev);
  3114. }
  3115. mutex_unlock(&swrm->pm_lock);
  3116. wake_up_all(&swrm->pm_wq);
  3117. }
  3118. #ifdef CONFIG_PM_SLEEP
  3119. static int swrm_suspend(struct device *dev)
  3120. {
  3121. int ret = -EBUSY;
  3122. struct platform_device *pdev = to_platform_device(dev);
  3123. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  3124. dev_dbg(dev, "%s: system suspend, state: %d\n", __func__, swrm->state);
  3125. mutex_lock(&swrm->pm_lock);
  3126. if (swrm->pm_state == SWRM_PM_SLEEPABLE) {
  3127. dev_dbg(swrm->dev, "%s: suspending system, state %d, wlock %d\n",
  3128. __func__, swrm->pm_state,
  3129. swrm->wlock_holders);
  3130. swrm->pm_state = SWRM_PM_ASLEEP;
  3131. } else if (swrm->pm_state == SWRM_PM_AWAKE) {
  3132. /*
  3133. * unlock to wait for pm_state == SWRM_PM_SLEEPABLE
  3134. * then set to SWRM_PM_ASLEEP
  3135. */
  3136. dev_dbg(swrm->dev, "%s: waiting to suspend system, state %d, wlock %d\n",
  3137. __func__, swrm->pm_state,
  3138. swrm->wlock_holders);
  3139. mutex_unlock(&swrm->pm_lock);
  3140. if (!(wait_event_timeout(swrm->pm_wq, swrm_pm_cmpxchg(
  3141. swrm, SWRM_PM_SLEEPABLE,
  3142. SWRM_PM_ASLEEP) ==
  3143. SWRM_PM_SLEEPABLE,
  3144. msecs_to_jiffies(
  3145. SWRM_SYS_SUSPEND_WAIT)))) {
  3146. dev_dbg(swrm->dev, "%s: suspend failed state %d, wlock %d\n",
  3147. __func__, swrm->pm_state,
  3148. swrm->wlock_holders);
  3149. return -EBUSY;
  3150. } else {
  3151. dev_dbg(swrm->dev,
  3152. "%s: done, state %d, wlock %d\n",
  3153. __func__, swrm->pm_state,
  3154. swrm->wlock_holders);
  3155. }
  3156. mutex_lock(&swrm->pm_lock);
  3157. } else if (swrm->pm_state == SWRM_PM_ASLEEP) {
  3158. dev_dbg(swrm->dev, "%s: system is already suspended, state %d, wlock %d\n",
  3159. __func__, swrm->pm_state,
  3160. swrm->wlock_holders);
  3161. }
  3162. mutex_unlock(&swrm->pm_lock);
  3163. if ((!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev))) {
  3164. ret = swrm_runtime_suspend(dev);
  3165. if (!ret) {
  3166. /*
  3167. * Synchronize runtime-pm and system-pm states:
  3168. * At this point, we are already suspended. If
  3169. * runtime-pm still thinks its active, then
  3170. * make sure its status is in sync with HW
  3171. * status. The three below calls let the
  3172. * runtime-pm know that we are suspended
  3173. * already without re-invoking the suspend
  3174. * callback
  3175. */
  3176. pm_runtime_disable(dev);
  3177. pm_runtime_set_suspended(dev);
  3178. pm_runtime_enable(dev);
  3179. }
  3180. }
  3181. if (ret == -EBUSY) {
  3182. /*
  3183. * There is a possibility that some audio stream is active
  3184. * during suspend. We dont want to return suspend failure in
  3185. * that case so that display and relevant components can still
  3186. * go to suspend.
  3187. * If there is some other error, then it should be passed-on
  3188. * to system level suspend
  3189. */
  3190. ret = 0;
  3191. }
  3192. return ret;
  3193. }
  3194. static int swrm_resume(struct device *dev)
  3195. {
  3196. int ret = 0;
  3197. struct platform_device *pdev = to_platform_device(dev);
  3198. struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
  3199. dev_dbg(dev, "%s: system resume, state: %d\n", __func__, swrm->state);
  3200. if (!pm_runtime_enabled(dev) || !pm_runtime_suspend(dev)) {
  3201. ret = swrm_runtime_resume(dev);
  3202. if (!ret) {
  3203. pm_runtime_mark_last_busy(dev);
  3204. pm_request_autosuspend(dev);
  3205. }
  3206. }
  3207. mutex_lock(&swrm->pm_lock);
  3208. if (swrm->pm_state == SWRM_PM_ASLEEP) {
  3209. dev_dbg(swrm->dev,
  3210. "%s: resuming system, state %d, wlock %d\n",
  3211. __func__, swrm->pm_state,
  3212. swrm->wlock_holders);
  3213. swrm->pm_state = SWRM_PM_SLEEPABLE;
  3214. } else {
  3215. dev_dbg(swrm->dev, "%s: system is already awake, state %d wlock %d\n",
  3216. __func__, swrm->pm_state,
  3217. swrm->wlock_holders);
  3218. }
  3219. mutex_unlock(&swrm->pm_lock);
  3220. wake_up_all(&swrm->pm_wq);
  3221. return ret;
  3222. }
  3223. #endif /* CONFIG_PM_SLEEP */
  3224. static const struct dev_pm_ops swrm_dev_pm_ops = {
  3225. SET_SYSTEM_SLEEP_PM_OPS(
  3226. swrm_suspend,
  3227. swrm_resume
  3228. )
  3229. SET_RUNTIME_PM_OPS(
  3230. swrm_runtime_suspend,
  3231. swrm_runtime_resume,
  3232. NULL
  3233. )
  3234. };
  3235. static const struct of_device_id swrm_dt_match[] = {
  3236. {
  3237. .compatible = "qcom,swr-mstr",
  3238. },
  3239. {}
  3240. };
  3241. static struct platform_driver swr_mstr_driver = {
  3242. .probe = swrm_probe,
  3243. .remove = swrm_remove,
  3244. .driver = {
  3245. .name = SWR_WCD_NAME,
  3246. .owner = THIS_MODULE,
  3247. .pm = &swrm_dev_pm_ops,
  3248. .of_match_table = swrm_dt_match,
  3249. .suppress_bind_attrs = true,
  3250. },
  3251. };
  3252. static int __init swrm_init(void)
  3253. {
  3254. return platform_driver_register(&swr_mstr_driver);
  3255. }
  3256. module_init(swrm_init);
  3257. static void __exit swrm_exit(void)
  3258. {
  3259. platform_driver_unregister(&swr_mstr_driver);
  3260. }
  3261. module_exit(swrm_exit);
  3262. MODULE_LICENSE("GPL v2");
  3263. MODULE_DESCRIPTION("SoundWire Master Controller");
  3264. MODULE_ALIAS("platform:swr-mstr");