msm_vidc_iris3.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include "msm_vidc_iris3.h"
  7. #include "msm_vidc_buffer_iris3.h"
  8. #include "msm_vidc_power_iris3.h"
  9. #include "venus_hfi.h"
  10. #include "msm_vidc_inst.h"
  11. #include "msm_vidc_core.h"
  12. #include "msm_vidc_driver.h"
  13. #include "msm_vidc_control.h"
  14. #include "msm_vidc_dt.h"
  15. #include "msm_vidc_internal.h"
  16. #include "msm_vidc_buffer.h"
  17. #include "msm_vidc_debug.h"
  18. #define VIDEO_ARCH_LX 1
  19. #define VCODEC_BASE_OFFS_IRIS3 0x00000000
  20. #define AON_MVP_NOC_RESET 0x0001F000
  21. #define CPU_BASE_OFFS_IRIS3 0x000A0000
  22. #define AON_BASE_OFFS 0x000E0000
  23. #define CPU_CS_BASE_OFFS_IRIS3 (CPU_BASE_OFFS_IRIS3)
  24. #define CPU_IC_BASE_OFFS_IRIS3 (CPU_BASE_OFFS_IRIS3)
  25. #define CPU_CS_A2HSOFTINTCLR_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x1C)
  26. #define CPU_CS_VCICMD_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x20)
  27. #define CPU_CS_VCICMDARG0_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x24)
  28. #define CPU_CS_VCICMDARG1_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x28)
  29. #define CPU_CS_VCICMDARG2_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x2C)
  30. #define CPU_CS_VCICMDARG3_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x30)
  31. #define CPU_CS_VMIMSG_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x34)
  32. #define CPU_CS_VMIMSGAG0_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x38)
  33. #define CPU_CS_VMIMSGAG1_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x3C)
  34. #define CPU_CS_SCIACMD_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x48)
  35. #define CPU_CS_H2XSOFTINTEN_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x148)
  36. /* HFI_CTRL_STATUS */
  37. #define CPU_CS_SCIACMDARG0_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x4C)
  38. #define CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK_IRIS3 0xfe
  39. #define CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY_IRIS3 0x100
  40. #define CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK_IRIS3 0x40000000
  41. /* HFI_QTBL_INFO */
  42. #define CPU_CS_SCIACMDARG1_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x50)
  43. /* HFI_QTBL_ADDR */
  44. #define CPU_CS_SCIACMDARG2_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x54)
  45. /* HFI_VERSION_INFO */
  46. #define CPU_CS_SCIACMDARG3_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x58)
  47. /* SFR_ADDR */
  48. #define CPU_CS_SCIBCMD_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x5C)
  49. /* MMAP_ADDR */
  50. #define CPU_CS_SCIBCMDARG0_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x60)
  51. /* UC_REGION_ADDR */
  52. #define CPU_CS_SCIBARG1_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x64)
  53. /* UC_REGION_ADDR */
  54. #define CPU_CS_SCIBARG2_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x68)
  55. #define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS_IRIS3 + 0x160)
  56. #define CPU_CS_AHB_BRIDGE_SYNC_RESET_STATUS (CPU_CS_BASE_OFFS_IRIS3 + 0x164)
  57. /* FAL10 Feature Control */
  58. #define CPU_CS_X2RPMh_IRIS3 (CPU_CS_BASE_OFFS_IRIS3 + 0x168)
  59. #define CPU_CS_X2RPMh_MASK0_BMSK_IRIS3 0x1
  60. #define CPU_CS_X2RPMh_MASK0_SHFT_IRIS3 0x0
  61. #define CPU_CS_X2RPMh_MASK1_BMSK_IRIS3 0x2
  62. #define CPU_CS_X2RPMh_MASK1_SHFT_IRIS3 0x1
  63. #define CPU_CS_X2RPMh_SWOVERRIDE_BMSK_IRIS3 0x4
  64. #define CPU_CS_X2RPMh_SWOVERRIDE_SHFT_IRIS3 0x3
  65. #define CPU_IC_SOFTINT_IRIS3 (CPU_IC_BASE_OFFS_IRIS3 + 0x150)
  66. #define CPU_IC_SOFTINT_H2A_SHFT_IRIS3 0x0
  67. /*
  68. * --------------------------------------------------------------------------
  69. * MODULE: AON_MVP_NOC_RESET_REGISTERS
  70. * --------------------------------------------------------------------------
  71. */
  72. #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
  73. #define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
  74. /*
  75. * --------------------------------------------------------------------------
  76. * MODULE: wrapper
  77. * --------------------------------------------------------------------------
  78. */
  79. #define WRAPPER_BASE_OFFS_IRIS3 0x000B0000
  80. #define WRAPPER_INTR_STATUS_IRIS3 (WRAPPER_BASE_OFFS_IRIS3 + 0x0C)
  81. #define WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS3 0x8
  82. #define WRAPPER_INTR_STATUS_A2H_BMSK_IRIS3 0x4
  83. #define WRAPPER_INTR_MASK_IRIS3 (WRAPPER_BASE_OFFS_IRIS3 + 0x10)
  84. #define WRAPPER_INTR_MASK_A2HWD_BMSK_IRIS3 0x8
  85. #define WRAPPER_INTR_MASK_A2HCPU_BMSK_IRIS3 0x4
  86. #define WRAPPER_CPU_CLOCK_CONFIG_IRIS3 (WRAPPER_BASE_OFFS_IRIS3 + 0x2000)
  87. #define WRAPPER_CPU_CGC_DIS_IRIS3 (WRAPPER_BASE_OFFS_IRIS3 + 0x2010)
  88. #define WRAPPER_CPU_STATUS_IRIS3 (WRAPPER_BASE_OFFS_IRIS3 + 0x2014)
  89. #define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS3 (WRAPPER_BASE_OFFS_IRIS3 + 0x54)
  90. #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS3 (WRAPPER_BASE_OFFS_IRIS3 + 0x58)
  91. #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS_IRIS3 + 0x5C)
  92. #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS_IRIS3 + 0x60)
  93. #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS_IRIS3 + 0x80)
  94. #define WRAPPER_CORE_CLOCK_CONFIG_IRIS3 (WRAPPER_BASE_OFFS_IRIS3 + 0x88)
  95. /*
  96. * --------------------------------------------------------------------------
  97. * MODULE: tz_wrapper
  98. * --------------------------------------------------------------------------
  99. */
  100. #define WRAPPER_TZ_BASE_OFFS 0x000C0000
  101. #define WRAPPER_TZ_CPU_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS)
  102. #define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
  103. #define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
  104. #define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
  105. #define CTRL_INIT_IRIS3 CPU_CS_SCIACMD_IRIS3
  106. #define CTRL_STATUS_IRIS3 CPU_CS_SCIACMDARG0_IRIS3
  107. #define CTRL_ERROR_STATUS__M_IRIS3 \
  108. CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK_IRIS3
  109. #define CTRL_INIT_IDLE_MSG_BMSK_IRIS3 \
  110. CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK_IRIS3
  111. #define CTRL_STATUS_PC_READY_IRIS3 \
  112. CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY_IRIS3
  113. #define QTBL_INFO_IRIS3 CPU_CS_SCIACMDARG1_IRIS3
  114. #define QTBL_ADDR_IRIS3 CPU_CS_SCIACMDARG2_IRIS3
  115. #define VERSION_INFO_IRIS3 CPU_CS_SCIACMDARG3_IRIS3
  116. #define SFR_ADDR_IRIS3 CPU_CS_SCIBCMD_IRIS3
  117. #define MMAP_ADDR_IRIS3 CPU_CS_SCIBCMDARG0_IRIS3
  118. #define UC_REGION_ADDR_IRIS3 CPU_CS_SCIBARG1_IRIS3
  119. #define UC_REGION_SIZE_IRIS3 CPU_CS_SCIBARG2_IRIS3
  120. #define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
  121. #define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
  122. /*
  123. * --------------------------------------------------------------------------
  124. * MODULE: VCODEC_SS registers
  125. * --------------------------------------------------------------------------
  126. */
  127. #define VCODEC_SS_IDLE_STATUSn (VCODEC_BASE_OFFS_IRIS3 + 0x70)
  128. /*
  129. * --------------------------------------------------------------------------
  130. * MODULE: vcodec noc error log registers (iris3)
  131. * --------------------------------------------------------------------------
  132. */
  133. #define VCODEC_NOC_VIDEO_A_NOC_BASE_OFFS 0x00010000
  134. #define VCODEC_NOC_ERL_MAIN_SWID_LOW 0x00011200
  135. #define VCODEC_NOC_ERL_MAIN_SWID_HIGH 0x00011204
  136. #define VCODEC_NOC_ERL_MAIN_MAINCTL_LOW 0x00011208
  137. #define VCODEC_NOC_ERL_MAIN_ERRVLD_LOW 0x00011210
  138. #define VCODEC_NOC_ERL_MAIN_ERRCLR_LOW 0x00011218
  139. #define VCODEC_NOC_ERL_MAIN_ERRLOG0_LOW 0x00011220
  140. #define VCODEC_NOC_ERL_MAIN_ERRLOG0_HIGH 0x00011224
  141. #define VCODEC_NOC_ERL_MAIN_ERRLOG1_LOW 0x00011228
  142. #define VCODEC_NOC_ERL_MAIN_ERRLOG1_HIGH 0x0001122C
  143. #define VCODEC_NOC_ERL_MAIN_ERRLOG2_LOW 0x00011230
  144. #define VCODEC_NOC_ERL_MAIN_ERRLOG2_HIGH 0x00011234
  145. #define VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW 0x00011238
  146. #define VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH 0x0001123C
  147. static int __disable_unprepare_clock_iris3(struct msm_vidc_core *core,
  148. const char *clk_name)
  149. {
  150. int rc = 0;
  151. struct clock_info *cl;
  152. bool found;
  153. if (!core || !clk_name) {
  154. d_vpr_e("%s: invalid params\n", __func__);
  155. return -EINVAL;
  156. }
  157. found = false;
  158. venus_hfi_for_each_clock(core, cl) {
  159. if (!cl->clk) {
  160. d_vpr_e("%s: invalid clock %s\n", __func__, cl->name);
  161. return -EINVAL;
  162. }
  163. if (strcmp(cl->name, clk_name))
  164. continue;
  165. found = true;
  166. clk_disable_unprepare(cl->clk);
  167. if (cl->has_scaling)
  168. __set_clk_rate(core, cl, 0);
  169. cl->prev = 0;
  170. d_vpr_h("%s: clock %s disable unprepared\n", __func__, cl->name);
  171. break;
  172. }
  173. if (!found) {
  174. d_vpr_e("%s: clock %s not found\n", __func__, clk_name);
  175. return -EINVAL;
  176. }
  177. return rc;
  178. }
  179. static int __prepare_enable_clock_iris3(struct msm_vidc_core *core,
  180. const char *clk_name)
  181. {
  182. int rc = 0;
  183. struct clock_info *cl;
  184. bool found;
  185. u64 rate = 0;
  186. if (!core || !clk_name) {
  187. d_vpr_e("%s: invalid params\n", __func__);
  188. return -EINVAL;
  189. }
  190. found = false;
  191. venus_hfi_for_each_clock(core, cl) {
  192. if (!cl->clk) {
  193. d_vpr_e("%s: invalid clock\n", __func__);
  194. return -EINVAL;
  195. }
  196. if (strcmp(cl->name, clk_name))
  197. continue;
  198. found = true;
  199. /*
  200. * For the clocks we control, set the rate prior to preparing
  201. * them. Since we don't really have a load at this point, scale
  202. * it to the lowest frequency possible
  203. */
  204. if (cl->has_scaling) {
  205. rate = clk_round_rate(cl->clk, 0);
  206. /**
  207. * source clock is already multipled with scaling ratio and __set_clk_rate
  208. * attempts to multiply again. So divide scaling ratio before calling
  209. * __set_clk_rate.
  210. */
  211. rate = rate / MSM_VIDC_CLOCK_SOURCE_SCALING_RATIO;
  212. __set_clk_rate(core, cl, rate);
  213. }
  214. rc = clk_prepare_enable(cl->clk);
  215. if (rc) {
  216. d_vpr_e("%s: failed to enable clock %s\n",
  217. __func__, cl->name);
  218. return rc;
  219. }
  220. if (!__clk_is_enabled(cl->clk)) {
  221. d_vpr_e("%s: clock %s not enabled\n",
  222. __func__, cl->name);
  223. clk_disable_unprepare(cl->clk);
  224. if (cl->has_scaling)
  225. __set_clk_rate(core, cl, 0);
  226. return -EINVAL;
  227. }
  228. d_vpr_h("%s: clock %s prepare enabled\n", __func__, cl->name);
  229. break;
  230. }
  231. if (!found) {
  232. d_vpr_e("%s: clock %s not found\n", __func__, clk_name);
  233. return -EINVAL;
  234. }
  235. return rc;
  236. }
  237. static int __disable_regulator_iris3(struct msm_vidc_core *core,
  238. const char *reg_name)
  239. {
  240. int rc = 0;
  241. struct regulator_info *rinfo;
  242. bool found;
  243. if (!core || !reg_name) {
  244. d_vpr_e("%s: invalid params\n", __func__);
  245. return -EINVAL;
  246. }
  247. found = false;
  248. venus_hfi_for_each_regulator(core, rinfo) {
  249. if (!rinfo->regulator) {
  250. d_vpr_e("%s: invalid regulator %s\n",
  251. __func__, rinfo->name);
  252. return -EINVAL;
  253. }
  254. if (strcmp(rinfo->name, reg_name))
  255. continue;
  256. found = true;
  257. rc = __acquire_regulator(core, rinfo);
  258. if (rc) {
  259. d_vpr_e("%s: failed to acquire %s, rc = %d\n",
  260. __func__, rinfo->name, rc);
  261. /* Bring attention to this issue */
  262. WARN_ON(true);
  263. return rc;
  264. }
  265. core->handoff_done = false;
  266. rc = regulator_disable(rinfo->regulator);
  267. if (rc) {
  268. d_vpr_e("%s: failed to disable %s, rc = %d\n",
  269. __func__, rinfo->name, rc);
  270. return rc;
  271. }
  272. d_vpr_h("%s: disabled regulator %s\n", __func__, rinfo->name);
  273. break;
  274. }
  275. if (!found) {
  276. d_vpr_e("%s: regulator %s not found\n", __func__, reg_name);
  277. return -EINVAL;
  278. }
  279. return rc;
  280. }
  281. static int __enable_regulator_iris3(struct msm_vidc_core *core,
  282. const char *reg_name)
  283. {
  284. int rc = 0;
  285. struct regulator_info *rinfo;
  286. bool found;
  287. if (!core || !reg_name) {
  288. d_vpr_e("%s: invalid params\n", __func__);
  289. return -EINVAL;
  290. }
  291. found = false;
  292. venus_hfi_for_each_regulator(core, rinfo) {
  293. if (!rinfo->regulator) {
  294. d_vpr_e("%s: invalid regulator %s\n",
  295. __func__, rinfo->name);
  296. return -EINVAL;
  297. }
  298. if (strcmp(rinfo->name, reg_name))
  299. continue;
  300. found = true;
  301. rc = regulator_enable(rinfo->regulator);
  302. if (rc) {
  303. d_vpr_e("%s: failed to enable %s, rc = %d\n",
  304. __func__, rinfo->name, rc);
  305. return rc;
  306. }
  307. if (!regulator_is_enabled(rinfo->regulator)) {
  308. d_vpr_e("%s: regulator %s not enabled\n",
  309. __func__, rinfo->name);
  310. regulator_disable(rinfo->regulator);
  311. return -EINVAL;
  312. }
  313. d_vpr_h("%s: enabled regulator %s\n", __func__, rinfo->name);
  314. break;
  315. }
  316. if (!found) {
  317. d_vpr_e("%s: regulator %s not found\n", __func__, reg_name);
  318. return -EINVAL;
  319. }
  320. return rc;
  321. }
  322. static int __interrupt_init_iris3(struct msm_vidc_core *vidc_core)
  323. {
  324. struct msm_vidc_core *core = vidc_core;
  325. u32 mask_val = 0;
  326. int rc = 0;
  327. if (!core) {
  328. d_vpr_e("%s: invalid params\n", __func__);
  329. return -EINVAL;
  330. }
  331. /* All interrupts should be disabled initially 0x1F6 : Reset value */
  332. rc = __read_register(core, WRAPPER_INTR_MASK_IRIS3, &mask_val);
  333. if (rc)
  334. return rc;
  335. /* Write 0 to unmask CPU and WD interrupts */
  336. mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BMSK_IRIS3|
  337. WRAPPER_INTR_MASK_A2HCPU_BMSK_IRIS3);
  338. rc = __write_register(core, WRAPPER_INTR_MASK_IRIS3, mask_val);
  339. if (rc)
  340. return rc;
  341. return 0;
  342. }
  343. static int __setup_ucregion_memory_map_iris3(struct msm_vidc_core *vidc_core)
  344. {
  345. struct msm_vidc_core *core = vidc_core;
  346. u32 value;
  347. int rc = 0;
  348. if (!core) {
  349. d_vpr_e("%s: invalid params\n", __func__);
  350. return -EINVAL;
  351. }
  352. value = (u32)core->iface_q_table.align_device_addr;
  353. rc = __write_register(core, UC_REGION_ADDR_IRIS3, value);
  354. if (rc)
  355. return rc;
  356. value = SHARED_QSIZE;
  357. rc = __write_register(core, UC_REGION_SIZE_IRIS3, value);
  358. if (rc)
  359. return rc;
  360. value = (u32)core->iface_q_table.align_device_addr;
  361. rc = __write_register(core, QTBL_ADDR_IRIS3, value);
  362. if (rc)
  363. return rc;
  364. rc = __write_register(core, QTBL_INFO_IRIS3, 0x01);
  365. if (rc)
  366. return rc;
  367. /* update queues vaddr for debug purpose */
  368. value = (u32)((u64)core->iface_q_table.align_virtual_addr);
  369. rc = __write_register(core, CPU_CS_VCICMDARG0_IRIS3, value);
  370. if (rc)
  371. return rc;
  372. value = (u32)((u64)core->iface_q_table.align_virtual_addr >> 32);
  373. rc = __write_register(core, CPU_CS_VCICMDARG1_IRIS3, value);
  374. if (rc)
  375. return rc;
  376. if (core->sfr.align_device_addr) {
  377. value = (u32)core->sfr.align_device_addr + VIDEO_ARCH_LX;
  378. rc = __write_register(core, SFR_ADDR_IRIS3, value);
  379. if (rc)
  380. return rc;
  381. }
  382. return 0;
  383. }
  384. static bool is_iris3_hw_power_collapsed(struct msm_vidc_core *core)
  385. {
  386. int rc = 0;
  387. u32 value = 0, pwr_status = 0;
  388. rc = __read_register(core, WRAPPER_CORE_POWER_STATUS, &value);
  389. if (rc)
  390. return false;
  391. /* if BIT(1) is 1 then video hw power is on else off */
  392. pwr_status = value & BIT(1);
  393. return pwr_status ? false : true;
  394. }
  395. static int __power_off_iris3_hardware(struct msm_vidc_core *core)
  396. {
  397. int rc = 0, i;
  398. u32 value = 0;
  399. bool pwr_collapsed = false;
  400. /*
  401. * Incase hw power control is enabled, when CPU WD occurred, check for power
  402. * status to decide on executing NOC reset sequence before disabling power.
  403. * If there is no CPU WD and hw_power_control is enabled, fw is expected
  404. * to power collapse video hw always.
  405. */
  406. if (core->hw_power_control) {
  407. pwr_collapsed = is_iris3_hw_power_collapsed(core);
  408. if (core->cpu_watchdog) {
  409. if (pwr_collapsed) {
  410. d_vpr_e("%s: CPU WD and video hw power collapsed\n", __func__);
  411. goto disable_power;
  412. } else {
  413. d_vpr_e("%s: CPU WD and video hw is power ON\n", __func__);
  414. }
  415. } else {
  416. if (!pwr_collapsed)
  417. d_vpr_e("%s: video hw is not power collapsed\n", __func__);
  418. goto disable_power;
  419. }
  420. }
  421. /*
  422. * check to make sure core clock branch enabled else
  423. * we cannot read vcodec top idle register
  424. */
  425. rc = __read_register(core, WRAPPER_CORE_CLOCK_CONFIG_IRIS3, &value);
  426. if (rc)
  427. return rc;
  428. if (value) {
  429. d_vpr_h("%s: core clock config not enabled, enabling it to read vcodec registers\n",
  430. __func__);
  431. rc = __write_register(core, WRAPPER_CORE_CLOCK_CONFIG_IRIS3, 0);
  432. if (rc)
  433. return rc;
  434. }
  435. /*
  436. * add MNoC idle check before collapsing MVS0 per HPG update
  437. * poll for NoC DMA idle -> HPG 6.1.1
  438. */
  439. for (i = 0; i < core->capabilities[NUM_VPP_PIPE].value; i++) {
  440. rc = __read_register_with_poll_timeout(core, VCODEC_SS_IDLE_STATUSn + 4*i,
  441. 0x400000, 0x400000, 2000, 20000);
  442. if (rc)
  443. d_vpr_h("%s: VCODEC_SS_IDLE_STATUSn (%d) is not idle (%#x)\n",
  444. __func__, i, value);
  445. }
  446. /* Apply partial reset on MSF interface and wait for ACK */
  447. rc = __write_register(core, AON_WRAPPER_MVP_NOC_RESET_REQ, 0x3);
  448. if (rc)
  449. return rc;
  450. rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_RESET_ACK,
  451. 0x3, 0x3, 200, 2000);
  452. if (rc)
  453. d_vpr_h("%s: AON_WRAPPER_MVP_NOC_RESET assert failed\n", __func__);
  454. /* De-assert partial reset on MSF interface and wait for ACK */
  455. rc = __write_register(core, AON_WRAPPER_MVP_NOC_RESET_REQ, 0x0);
  456. if (rc)
  457. return rc;
  458. rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_RESET_ACK,
  459. 0x3, 0x0, 200, 2000);
  460. if (rc)
  461. d_vpr_h("%s: AON_WRAPPER_MVP_NOC_RESET de-assert failed\n", __func__);
  462. /*
  463. * Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ)
  464. * do we need to check status register here?
  465. */
  466. rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, 0x3);
  467. if (rc)
  468. return rc;
  469. rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, 0x2);
  470. if (rc)
  471. return rc;
  472. rc = __write_register(core, CPU_CS_AHB_BRIDGE_SYNC_RESET, 0x0);
  473. if (rc)
  474. return rc;
  475. disable_power:
  476. /* power down process */
  477. rc = __disable_regulator_iris3(core, "vcodec");
  478. if (rc) {
  479. d_vpr_e("%s: disable regulator vcodec failed\n", __func__);
  480. rc = 0;
  481. }
  482. rc = __disable_unprepare_clock_iris3(core, "vcodec_clk");
  483. if (rc) {
  484. d_vpr_e("%s: disable unprepare vcodec_clk failed\n", __func__);
  485. rc = 0;
  486. }
  487. return rc;
  488. }
  489. static int __power_off_iris3_controller(struct msm_vidc_core *core)
  490. {
  491. int rc = 0;
  492. /*
  493. * mask fal10_veto QLPAC error since fal10_veto can go 1
  494. * when pwwait == 0 and clamped to 0 -> HPG 6.1.2
  495. */
  496. rc = __write_register(core, CPU_CS_X2RPMh_IRIS3, 0x3);
  497. if (rc)
  498. return rc;
  499. /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */
  500. rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
  501. 0x1, BIT(0));
  502. if (rc)
  503. return rc;
  504. rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_LPI_STATUS,
  505. 0x1, 0x1, 200, 2000);
  506. if (rc)
  507. d_vpr_h("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
  508. /* Set Iris CPU NoC to Low power */
  509. rc = __write_register_masked(core, WRAPPER_IRIS_CPU_NOC_LPI_CONTROL,
  510. 0x1, BIT(0));
  511. if (rc)
  512. return rc;
  513. rc = __read_register_with_poll_timeout(core, WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
  514. 0x1, 0x1, 200, 2000);
  515. if (rc)
  516. d_vpr_h("%s: WRAPPER_IRIS_CPU_NOC_LPI_CONTROL failed\n", __func__);
  517. /* Debug bridge LPI release */
  518. rc = __write_register(core, WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS3, 0x0);
  519. if (rc)
  520. return rc;
  521. rc = __read_register_with_poll_timeout(core, WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS3,
  522. 0xffffffff, 0x0, 200, 2000);
  523. if (rc)
  524. d_vpr_h("%s: debug bridge release failed\n", __func__);
  525. /* Reset MVP QNS4PDXFIFO */
  526. rc = __write_register(core, WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG, 0x3);
  527. if (rc)
  528. return rc;
  529. rc = __write_register(core, WRAPPER_TZ_QNS4PDXFIFO_RESET, 0x1);
  530. if (rc)
  531. return rc;
  532. rc = __write_register(core, WRAPPER_TZ_QNS4PDXFIFO_RESET, 0x0);
  533. if (rc)
  534. return rc;
  535. rc = __write_register(core, WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG, 0x0);
  536. if (rc)
  537. return rc;
  538. /* Turn off MVP MVS0C core clock */
  539. rc = __disable_unprepare_clock_iris3(core, "core_clk");
  540. if (rc) {
  541. d_vpr_e("%s: disable unprepare core_clk failed\n", __func__);
  542. rc = 0;
  543. }
  544. /* power down process */
  545. rc = __disable_regulator_iris3(core, "iris-ctl");
  546. if (rc) {
  547. d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__);
  548. rc = 0;
  549. }
  550. return rc;
  551. }
  552. static int __power_off_iris3(struct msm_vidc_core *core)
  553. {
  554. int rc = 0;
  555. if (!core || !core->capabilities) {
  556. d_vpr_e("%s: invalid params\n", __func__);
  557. return -EINVAL;
  558. }
  559. if (!core->power_enabled)
  560. return 0;
  561. /**
  562. * Reset video_cc_mvs0_clk_src value to resolve MMRM high video
  563. * clock projection issue.
  564. */
  565. rc = __set_clocks(core, 0);
  566. if (rc)
  567. d_vpr_e("%s: resetting clocks failed\n", __func__);
  568. if (__power_off_iris3_hardware(core))
  569. d_vpr_e("%s: failed to power off hardware\n", __func__);
  570. if (__power_off_iris3_controller(core))
  571. d_vpr_e("%s: failed to power off controller\n", __func__);
  572. if (__unvote_buses(core))
  573. d_vpr_e("%s: failed to unvote buses\n", __func__);
  574. if (!(core->intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS3))
  575. disable_irq_nosync(core->dt->irq);
  576. core->intr_status = 0;
  577. core->power_enabled = false;
  578. return rc;
  579. }
  580. static int __power_on_iris3_controller(struct msm_vidc_core *core)
  581. {
  582. int rc = 0;
  583. rc = __enable_regulator_iris3(core, "iris-ctl");
  584. if (rc)
  585. goto fail_regulator;
  586. rc = call_venus_op(core, reset_ahb2axi_bridge, core);
  587. if (rc)
  588. goto fail_reset_ahb2axi;
  589. rc = __prepare_enable_clock_iris3(core, "gcc_video_axi0");
  590. if (rc)
  591. goto fail_clk_axi;
  592. rc = __prepare_enable_clock_iris3(core, "core_clk");
  593. if (rc)
  594. goto fail_clk_controller;
  595. return 0;
  596. fail_clk_controller:
  597. __disable_unprepare_clock_iris3(core, "gcc_video_axi0");
  598. fail_clk_axi:
  599. fail_reset_ahb2axi:
  600. __disable_regulator_iris3(core, "iris-ctl");
  601. fail_regulator:
  602. return rc;
  603. }
  604. static int __power_on_iris3_hardware(struct msm_vidc_core *core)
  605. {
  606. int rc = 0;
  607. rc = __enable_regulator_iris3(core, "vcodec");
  608. if (rc)
  609. goto fail_regulator;
  610. rc = __prepare_enable_clock_iris3(core, "vcodec_clk");
  611. if (rc)
  612. goto fail_clk_controller;
  613. return 0;
  614. fail_clk_controller:
  615. __disable_regulator_iris3(core, "vcodec");
  616. fail_regulator:
  617. return rc;
  618. }
  619. static int __power_on_iris3(struct msm_vidc_core *core)
  620. {
  621. int rc = 0;
  622. if (core->power_enabled)
  623. return 0;
  624. /* Vote for all hardware resources */
  625. rc = __vote_buses(core, INT_MAX, INT_MAX);
  626. if (rc) {
  627. d_vpr_e("%s: failed to vote buses, rc %d\n", __func__, rc);
  628. goto fail_vote_buses;
  629. }
  630. rc = __power_on_iris3_controller(core);
  631. if (rc) {
  632. d_vpr_e("%s: failed to power on iris3 controller\n", __func__);
  633. goto fail_power_on_controller;
  634. }
  635. rc = __power_on_iris3_hardware(core);
  636. if (rc) {
  637. d_vpr_e("%s: failed to power on iris3 hardware\n", __func__);
  638. goto fail_power_on_hardware;
  639. }
  640. /* video controller and hardware powered on successfully */
  641. core->power_enabled = true;
  642. rc = __scale_clocks(core);
  643. if (rc) {
  644. d_vpr_e("%s: failed to scale clocks\n", __func__);
  645. rc = 0;
  646. }
  647. /*
  648. * Re-program all of the registers that get reset as a result of
  649. * regulator_disable() and _enable()
  650. */
  651. __set_registers(core);
  652. call_venus_op(core, interrupt_init, core);
  653. core->intr_status = 0;
  654. enable_irq(core->dt->irq);
  655. return rc;
  656. fail_power_on_hardware:
  657. __power_off_iris3_controller(core);
  658. fail_power_on_controller:
  659. __unvote_buses(core);
  660. fail_vote_buses:
  661. core->power_enabled = false;
  662. return rc;
  663. }
  664. static int __prepare_pc_iris3(struct msm_vidc_core *vidc_core)
  665. {
  666. int rc = 0;
  667. u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
  668. u32 ctrl_status = 0;
  669. struct msm_vidc_core *core = vidc_core;
  670. if (!core) {
  671. d_vpr_e("%s: invalid params\n", __func__);
  672. return -EINVAL;
  673. }
  674. rc = __read_register(core, CTRL_STATUS_IRIS3, &ctrl_status);
  675. if (rc)
  676. return rc;
  677. pc_ready = ctrl_status & CTRL_STATUS_PC_READY_IRIS3;
  678. idle_status = ctrl_status & BIT(30);
  679. if (pc_ready) {
  680. d_vpr_h("Already in pc_ready state\n");
  681. return 0;
  682. }
  683. rc = __read_register(core, WRAPPER_TZ_CPU_STATUS, &wfi_status);
  684. if (rc)
  685. return rc;
  686. wfi_status &= BIT(0);
  687. if (!wfi_status || !idle_status) {
  688. d_vpr_e("Skipping PC, wfi status not set\n");
  689. goto skip_power_off;
  690. }
  691. rc = __prepare_pc(core);
  692. if (rc) {
  693. d_vpr_e("Failed __prepare_pc %d\n", rc);
  694. goto skip_power_off;
  695. }
  696. rc = __read_register_with_poll_timeout(core, CTRL_STATUS_IRIS3,
  697. CTRL_STATUS_PC_READY_IRIS3, CTRL_STATUS_PC_READY_IRIS3, 250, 2500);
  698. if (rc) {
  699. d_vpr_e("%s: Skip PC. Ctrl status not set\n", __func__);
  700. goto skip_power_off;
  701. }
  702. rc = __read_register_with_poll_timeout(core, WRAPPER_TZ_CPU_STATUS,
  703. BIT(0), 0x1, 250, 2500);
  704. if (rc) {
  705. d_vpr_e("%s: Skip PC. Wfi status not set\n", __func__);
  706. goto skip_power_off;
  707. }
  708. return rc;
  709. skip_power_off:
  710. rc = __read_register(core, CTRL_STATUS_IRIS3, &ctrl_status);
  711. if (rc)
  712. return rc;
  713. rc = __read_register(core, WRAPPER_TZ_CPU_STATUS, &wfi_status);
  714. if (rc)
  715. return rc;
  716. wfi_status &= BIT(0);
  717. d_vpr_e("Skip PC, wfi=%#x, idle=%#x, pcr=%#x, ctrl=%#x)\n",
  718. wfi_status, idle_status, pc_ready, ctrl_status);
  719. return -EAGAIN;
  720. }
  721. static int __raise_interrupt_iris3(struct msm_vidc_core *vidc_core)
  722. {
  723. struct msm_vidc_core *core = vidc_core;
  724. int rc = 0;
  725. if (!core) {
  726. d_vpr_e("%s: invalid params\n", __func__);
  727. return -EINVAL;
  728. }
  729. rc = __write_register(core, CPU_IC_SOFTINT_IRIS3, 1 << CPU_IC_SOFTINT_H2A_SHFT_IRIS3);
  730. if (rc)
  731. return rc;
  732. return 0;
  733. }
  734. static int __watchdog_iris3(struct msm_vidc_core *vidc_core, u32 intr_status)
  735. {
  736. int rc = 0;
  737. struct msm_vidc_core *core = vidc_core;
  738. if (!core) {
  739. d_vpr_e("%s: invalid params\n", __func__);
  740. return -EINVAL;
  741. }
  742. if (intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS3) {
  743. d_vpr_e("%s: received watchdog interrupt\n", __func__);
  744. rc = 1;
  745. }
  746. return rc;
  747. }
  748. static int __noc_error_info_iris3(struct msm_vidc_core *vidc_core)
  749. {
  750. struct msm_vidc_core *core = vidc_core;
  751. if (!core) {
  752. d_vpr_e("%s: invalid params\n", __func__);
  753. return -EINVAL;
  754. }
  755. /*
  756. * we are not supposed to access vcodec subsystem registers
  757. * unless vcodec core clock WRAPPER_CORE_CLOCK_CONFIG_IRIS3 is enabled.
  758. * core clock might have been disabled by video firmware as part of
  759. * inter frame power collapse (power plane control feature).
  760. */
  761. /*
  762. val = __read_register(core, VCODEC_NOC_ERL_MAIN_SWID_LOW);
  763. d_vpr_e("VCODEC_NOC_ERL_MAIN_SWID_LOW: %#x\n", val);
  764. val = __read_register(core, VCODEC_NOC_ERL_MAIN_SWID_HIGH);
  765. d_vpr_e("VCODEC_NOC_ERL_MAIN_SWID_HIGH: %#x\n", val);
  766. val = __read_register(core, VCODEC_NOC_ERL_MAIN_MAINCTL_LOW);
  767. d_vpr_e("VCODEC_NOC_ERL_MAIN_MAINCTL_LOW: %#x\n", val);
  768. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRVLD_LOW);
  769. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRVLD_LOW: %#x\n", val);
  770. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRCLR_LOW);
  771. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRCLR_LOW: %#x\n", val);
  772. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG0_LOW);
  773. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG0_LOW: %#x\n", val);
  774. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG0_HIGH);
  775. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG0_HIGH: %#x\n", val);
  776. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG1_LOW);
  777. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG1_LOW: %#x\n", val);
  778. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG1_HIGH);
  779. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG1_HIGH: %#x\n", val);
  780. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG2_LOW);
  781. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG2_LOW: %#x\n", val);
  782. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG2_HIGH);
  783. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG2_HIGH: %#x\n", val);
  784. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW);
  785. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
  786. val = __read_register(core, VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH);
  787. d_vpr_e("VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH: %#x\n", val);
  788. */
  789. return 0;
  790. }
  791. static int __clear_interrupt_iris3(struct msm_vidc_core *vidc_core)
  792. {
  793. struct msm_vidc_core *core = vidc_core;
  794. u32 intr_status = 0, mask = 0;
  795. int rc = 0;
  796. if (!core) {
  797. d_vpr_e("%s: NULL core\n", __func__);
  798. return 0;
  799. }
  800. rc = __read_register(core, WRAPPER_INTR_STATUS_IRIS3, &intr_status);
  801. if (rc)
  802. return rc;
  803. mask = (WRAPPER_INTR_STATUS_A2H_BMSK_IRIS3|
  804. WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS3|
  805. CTRL_INIT_IDLE_MSG_BMSK_IRIS3);
  806. if (intr_status & mask) {
  807. core->intr_status |= intr_status;
  808. core->reg_count++;
  809. d_vpr_l("INTERRUPT: times: %d interrupt_status: %d\n",
  810. core->reg_count, intr_status);
  811. } else {
  812. core->spur_count++;
  813. }
  814. rc = __write_register(core, CPU_CS_A2HSOFTINTCLR_IRIS3, 1);
  815. if (rc)
  816. return rc;
  817. return 0;
  818. }
  819. static int __boot_firmware_iris3(struct msm_vidc_core *vidc_core)
  820. {
  821. int rc = 0;
  822. u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 1000;
  823. struct msm_vidc_core *core = vidc_core;
  824. if (!core) {
  825. d_vpr_e("%s: NULL core\n", __func__);
  826. return 0;
  827. }
  828. ctrl_init_val = BIT(0);
  829. rc = __write_register(core, CTRL_INIT_IRIS3, ctrl_init_val);
  830. if (rc)
  831. return rc;
  832. while (!ctrl_status && count < max_tries) {
  833. rc = __read_register(core, CTRL_STATUS_IRIS3, &ctrl_status);
  834. if (rc)
  835. return rc;
  836. if ((ctrl_status & CTRL_ERROR_STATUS__M_IRIS3) == 0x4) {
  837. d_vpr_e("invalid setting for UC_REGION\n");
  838. break;
  839. }
  840. usleep_range(50, 100);
  841. count++;
  842. }
  843. if (count >= max_tries) {
  844. d_vpr_e("Error booting up vidc firmware\n");
  845. return -ETIME;
  846. }
  847. /* Enable interrupt before sending commands to venus */
  848. rc = __write_register(core, CPU_CS_H2XSOFTINTEN_IRIS3, 0x1);
  849. if (rc)
  850. return rc;
  851. rc = __write_register(core, CPU_CS_X2RPMh_IRIS3, 0x0);
  852. if (rc)
  853. return rc;
  854. return rc;
  855. }
  856. int msm_vidc_decide_work_mode_iris3(struct msm_vidc_inst* inst)
  857. {
  858. u32 work_mode;
  859. struct v4l2_format *inp_f;
  860. u32 width, height;
  861. bool res_ok = false;
  862. if (!inst || !inst->capabilities) {
  863. d_vpr_e("%s: invalid params\n", __func__);
  864. return -EINVAL;
  865. }
  866. work_mode = MSM_VIDC_STAGE_2;
  867. inp_f = &inst->fmts[INPUT_PORT];
  868. if (is_image_decode_session(inst))
  869. work_mode = MSM_VIDC_STAGE_1;
  870. if (is_image_session(inst))
  871. goto exit;
  872. if (is_decode_session(inst)) {
  873. height = inp_f->fmt.pix_mp.height;
  874. width = inp_f->fmt.pix_mp.width;
  875. res_ok = res_is_less_than(width, height, 1280, 720);
  876. if (inst->capabilities->cap[CODED_FRAMES].value ==
  877. CODED_FRAMES_INTERLACE ||
  878. inst->capabilities->cap[LOWLATENCY_MODE].value ||
  879. res_ok) {
  880. work_mode = MSM_VIDC_STAGE_1;
  881. }
  882. } else if (is_encode_session(inst)) {
  883. height = inst->crop.height;
  884. width = inst->crop.width;
  885. res_ok = !res_is_greater_than(width, height, 4096, 2160);
  886. if (res_ok &&
  887. (inst->capabilities->cap[LOWLATENCY_MODE].value)) {
  888. work_mode = MSM_VIDC_STAGE_1;
  889. }
  890. if (inst->capabilities->cap[SLICE_MODE].value ==
  891. V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) {
  892. work_mode = MSM_VIDC_STAGE_1;
  893. }
  894. if (inst->capabilities->cap[LOSSLESS].value)
  895. work_mode = MSM_VIDC_STAGE_2;
  896. if (!inst->capabilities->cap[GOP_SIZE].value)
  897. work_mode = MSM_VIDC_STAGE_2;
  898. } else {
  899. i_vpr_e(inst, "%s: invalid session type\n", __func__);
  900. return -EINVAL;
  901. }
  902. exit:
  903. i_vpr_h(inst, "Configuring work mode = %u low latency = %u, gop size = %u\n",
  904. work_mode, inst->capabilities->cap[LOWLATENCY_MODE].value,
  905. inst->capabilities->cap[GOP_SIZE].value);
  906. msm_vidc_update_cap_value(inst, STAGE, work_mode, __func__);
  907. return 0;
  908. }
  909. int msm_vidc_decide_work_route_iris3(struct msm_vidc_inst* inst)
  910. {
  911. u32 work_route;
  912. struct msm_vidc_core* core;
  913. if (!inst || !inst->core) {
  914. d_vpr_e("%s: invalid params\n", __func__);
  915. return -EINVAL;
  916. }
  917. core = inst->core;
  918. work_route = core->capabilities[NUM_VPP_PIPE].value;
  919. if (is_image_session(inst))
  920. goto exit;
  921. if (is_decode_session(inst)) {
  922. if (inst->capabilities->cap[CODED_FRAMES].value ==
  923. CODED_FRAMES_INTERLACE)
  924. work_route = MSM_VIDC_PIPE_1;
  925. } else if (is_encode_session(inst)) {
  926. u32 slice_mode;
  927. slice_mode = inst->capabilities->cap[SLICE_MODE].value;
  928. /*TODO Pipe=1 for legacy CBR*/
  929. if (slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES)
  930. work_route = MSM_VIDC_PIPE_1;
  931. } else {
  932. i_vpr_e(inst, "%s: invalid session type\n", __func__);
  933. return -EINVAL;
  934. }
  935. exit:
  936. i_vpr_h(inst, "Configuring work route = %u", work_route);
  937. msm_vidc_update_cap_value(inst, PIPE, work_route, __func__);
  938. return 0;
  939. }
  940. int msm_vidc_decide_quality_mode_iris3(struct msm_vidc_inst* inst)
  941. {
  942. struct msm_vidc_inst_capability* capability = NULL;
  943. struct msm_vidc_core *core;
  944. u32 mbpf, mbps, max_hq_mbpf, max_hq_mbps;
  945. u32 mode = MSM_VIDC_POWER_SAVE_MODE;
  946. if (!inst || !inst->capabilities) {
  947. d_vpr_e("%s: invalid params\n", __func__);
  948. return -EINVAL;
  949. }
  950. capability = inst->capabilities;
  951. if (!is_encode_session(inst))
  952. return 0;
  953. /* image or lossless or all intra runs at quality mode */
  954. if (is_image_session(inst) || capability->cap[LOSSLESS].value ||
  955. capability->cap[ALL_INTRA].value) {
  956. mode = MSM_VIDC_MAX_QUALITY_MODE;
  957. goto decision_done;
  958. }
  959. /* for lesser complexity, make LP for all resolution */
  960. if (capability->cap[COMPLEXITY].value < DEFAULT_COMPLEXITY) {
  961. mode = MSM_VIDC_POWER_SAVE_MODE;
  962. goto decision_done;
  963. }
  964. mbpf = msm_vidc_get_mbs_per_frame(inst);
  965. mbps = mbpf * msm_vidc_get_fps(inst);
  966. core = inst->core;
  967. max_hq_mbpf = core->capabilities[MAX_MBPF_HQ].value;;
  968. max_hq_mbps = core->capabilities[MAX_MBPS_HQ].value;;
  969. if (!is_realtime_session(inst)) {
  970. if (((capability->cap[COMPLEXITY].flags & CAP_FLAG_CLIENT_SET) &&
  971. (capability->cap[COMPLEXITY].value >= DEFAULT_COMPLEXITY)) ||
  972. mbpf <= max_hq_mbpf) {
  973. mode = MSM_VIDC_MAX_QUALITY_MODE;
  974. goto decision_done;
  975. }
  976. }
  977. if (mbpf <= max_hq_mbpf && mbps <= max_hq_mbps)
  978. mode = MSM_VIDC_MAX_QUALITY_MODE;
  979. decision_done:
  980. msm_vidc_update_cap_value(inst, QUALITY_MODE, mode, __func__);
  981. return 0;
  982. }
  983. int msm_vidc_adjust_bitrate_boost_iris3(void* instance, struct v4l2_ctrl *ctrl)
  984. {
  985. struct msm_vidc_inst_capability* capability = NULL;
  986. s32 adjusted_value;
  987. struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
  988. s32 rc_type = -1;
  989. u32 width, height, frame_rate;
  990. struct v4l2_format *f;
  991. u32 max_bitrate = 0, bitrate = 0;
  992. if (!inst || !inst->capabilities) {
  993. d_vpr_e("%s: invalid params\n", __func__);
  994. return -EINVAL;
  995. }
  996. capability = inst->capabilities;
  997. adjusted_value = ctrl ? ctrl->val :
  998. capability->cap[BITRATE_BOOST].value;
  999. if (inst->bufq[OUTPUT_PORT].vb2q->streaming)
  1000. return 0;
  1001. if (msm_vidc_get_parent_value(inst, BITRATE_BOOST,
  1002. BITRATE_MODE, &rc_type, __func__))
  1003. return -EINVAL;
  1004. /*
  1005. * Bitrate Boost are supported only for VBR rc type.
  1006. * Hence, do not adjust or set to firmware for non VBR rc's
  1007. */
  1008. if (rc_type != HFI_RC_VBR_CFR) {
  1009. adjusted_value = 0;
  1010. goto adjust;
  1011. }
  1012. frame_rate = inst->capabilities->cap[FRAME_RATE].value >> 16;
  1013. f= &inst->fmts[OUTPUT_PORT];
  1014. width = f->fmt.pix_mp.width;
  1015. height = f->fmt.pix_mp.height;
  1016. /*
  1017. * honor client set bitrate boost
  1018. * if client did not set, keep max bitrate boost upto 4k@60fps
  1019. * and remove bitrate boost after 4k@60fps
  1020. */
  1021. if (capability->cap[BITRATE_BOOST].flags & CAP_FLAG_CLIENT_SET) {
  1022. /* accept client set bitrate boost value as is */
  1023. } else {
  1024. if (res_is_less_than_or_equal_to(width, height, 4096, 2176) &&
  1025. frame_rate <= 60)
  1026. adjusted_value = MAX_BITRATE_BOOST;
  1027. else
  1028. adjusted_value = 0;
  1029. }
  1030. max_bitrate = msm_vidc_get_max_bitrate(inst);
  1031. bitrate = inst->capabilities->cap[BIT_RATE].value;
  1032. if (adjusted_value) {
  1033. if ((bitrate + bitrate / (100 / adjusted_value)) > max_bitrate) {
  1034. i_vpr_h(inst,
  1035. "%s: bitrate %d is beyond max bitrate %d, remove bitrate boost\n",
  1036. __func__, max_bitrate, bitrate);
  1037. adjusted_value = 0;
  1038. }
  1039. }
  1040. adjust:
  1041. msm_vidc_update_cap_value(inst, BITRATE_BOOST, adjusted_value, __func__);
  1042. return 0;
  1043. }
  1044. static struct msm_vidc_venus_ops iris3_ops = {
  1045. .boot_firmware = __boot_firmware_iris3,
  1046. .interrupt_init = __interrupt_init_iris3,
  1047. .raise_interrupt = __raise_interrupt_iris3,
  1048. .clear_interrupt = __clear_interrupt_iris3,
  1049. .setup_ucregion_memmap = __setup_ucregion_memory_map_iris3,
  1050. .clock_config_on_enable = NULL,
  1051. .reset_ahb2axi_bridge = __reset_ahb2axi_bridge,
  1052. .power_on = __power_on_iris3,
  1053. .power_off = __power_off_iris3,
  1054. .prepare_pc = __prepare_pc_iris3,
  1055. .watchdog = __watchdog_iris3,
  1056. .noc_error_info = __noc_error_info_iris3,
  1057. };
  1058. static struct msm_vidc_session_ops msm_session_ops = {
  1059. .buffer_size = msm_buffer_size_iris3,
  1060. .min_count = msm_buffer_min_count_iris3,
  1061. .extra_count = msm_buffer_extra_count_iris3,
  1062. .calc_freq = msm_vidc_calc_freq_iris3,
  1063. .calc_bw = msm_vidc_calc_bw_iris3,
  1064. .decide_work_route = msm_vidc_decide_work_route_iris3,
  1065. .decide_work_mode = msm_vidc_decide_work_mode_iris3,
  1066. .decide_quality_mode = msm_vidc_decide_quality_mode_iris3,
  1067. };
  1068. int msm_vidc_init_iris3(struct msm_vidc_core *core)
  1069. {
  1070. if (!core) {
  1071. d_vpr_e("%s: invalid params\n", __func__);
  1072. return -EINVAL;
  1073. }
  1074. d_vpr_h("%s()\n", __func__);
  1075. core->venus_ops = &iris3_ops;
  1076. core->session_ops = &msm_session_ops;
  1077. return 0;
  1078. }
  1079. int msm_vidc_deinit_iris3(struct msm_vidc_core *core)
  1080. {
  1081. /* do nothing */
  1082. return 0;
  1083. }