cam_mem_mgr.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/types.h>
  7. #include <linux/mutex.h>
  8. #include <linux/slab.h>
  9. #include <linux/dma-buf.h>
  10. #include <linux/version.h>
  11. #include <linux/debugfs.h>
  12. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  13. #include <linux/mem-buf.h>
  14. #include <soc/qcom/secure_buffer.h>
  15. #endif
  16. #include "cam_compat.h"
  17. #include "cam_req_mgr_util.h"
  18. #include "cam_mem_mgr.h"
  19. #include "cam_smmu_api.h"
  20. #include "cam_debug_util.h"
  21. #include "cam_trace.h"
  22. #include "cam_common_util.h"
  23. #define CAM_MEM_SHARED_BUFFER_PAD_4K (4 * 1024)
  24. static struct cam_mem_table tbl;
  25. static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED);
  26. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  27. static void cam_mem_mgr_put_dma_heaps(void);
  28. static int cam_mem_mgr_get_dma_heaps(void);
  29. #endif
  30. static void cam_mem_mgr_print_tbl(void)
  31. {
  32. int i;
  33. uint64_t ms, tmp, hrs, min, sec;
  34. struct timespec64 *ts = NULL;
  35. struct timespec64 current_ts;
  36. ktime_get_real_ts64(&(current_ts));
  37. tmp = current_ts.tv_sec;
  38. ms = (current_ts.tv_nsec) / 1000000;
  39. sec = do_div(tmp, 60);
  40. min = do_div(tmp, 60);
  41. hrs = do_div(tmp, 24);
  42. CAM_INFO(CAM_MEM, "***%llu:%llu:%llu:%llu Mem mgr table dump***",
  43. hrs, min, sec, ms);
  44. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  45. if (tbl.bufq[i].active) {
  46. ts = &tbl.bufq[i].timestamp;
  47. tmp = ts->tv_sec;
  48. ms = (ts->tv_nsec) / 1000000;
  49. sec = do_div(tmp, 60);
  50. min = do_div(tmp, 60);
  51. hrs = do_div(tmp, 24);
  52. CAM_INFO(CAM_MEM,
  53. "%llu:%llu:%llu:%llu idx %d fd %d size %llu",
  54. hrs, min, sec, ms, i, tbl.bufq[i].fd,
  55. tbl.bufq[i].len);
  56. }
  57. }
  58. }
  59. static int cam_mem_util_get_dma_dir(uint32_t flags)
  60. {
  61. int rc = -EINVAL;
  62. if (flags & CAM_MEM_FLAG_HW_READ_ONLY)
  63. rc = DMA_TO_DEVICE;
  64. else if (flags & CAM_MEM_FLAG_HW_WRITE_ONLY)
  65. rc = DMA_FROM_DEVICE;
  66. else if (flags & CAM_MEM_FLAG_HW_READ_WRITE)
  67. rc = DMA_BIDIRECTIONAL;
  68. else if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  69. rc = DMA_BIDIRECTIONAL;
  70. return rc;
  71. }
  72. static int cam_mem_util_map_cpu_va(struct dma_buf *dmabuf,
  73. uintptr_t *vaddr,
  74. size_t *len)
  75. {
  76. int rc = 0;
  77. void *addr;
  78. /*
  79. * dma_buf_begin_cpu_access() and dma_buf_end_cpu_access()
  80. * need to be called in pair to avoid stability issue.
  81. */
  82. rc = dma_buf_begin_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  83. if (rc) {
  84. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  85. return rc;
  86. }
  87. addr = dma_buf_vmap(dmabuf);
  88. if (!addr) {
  89. CAM_ERR(CAM_MEM, "kernel map fail");
  90. *vaddr = 0;
  91. *len = 0;
  92. rc = -ENOSPC;
  93. goto fail;
  94. }
  95. *vaddr = (uint64_t)addr;
  96. *len = dmabuf->size;
  97. return 0;
  98. fail:
  99. dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  100. return rc;
  101. }
  102. static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf,
  103. uint64_t vaddr)
  104. {
  105. int rc = 0;
  106. if (!dmabuf || !vaddr) {
  107. CAM_ERR(CAM_MEM, "Invalid input args %pK %llX", dmabuf, vaddr);
  108. return -EINVAL;
  109. }
  110. dma_buf_vunmap(dmabuf, (void *)vaddr);
  111. /*
  112. * dma_buf_begin_cpu_access() and
  113. * dma_buf_end_cpu_access() need to be called in pair
  114. * to avoid stability issue.
  115. */
  116. rc = dma_buf_end_cpu_access(dmabuf, DMA_BIDIRECTIONAL);
  117. if (rc) {
  118. CAM_ERR(CAM_MEM, "Failed in end cpu access, dmabuf=%pK",
  119. dmabuf);
  120. return rc;
  121. }
  122. return rc;
  123. }
  124. static int cam_mem_mgr_create_debug_fs(void)
  125. {
  126. int rc = 0;
  127. struct dentry *dbgfileptr = NULL;
  128. dbgfileptr = debugfs_create_dir("camera_memmgr", NULL);
  129. if (!dbgfileptr) {
  130. CAM_ERR(CAM_MEM,"DebugFS could not create directory!");
  131. rc = -ENOENT;
  132. goto end;
  133. }
  134. /* Store parent inode for cleanup in caller */
  135. tbl.dentry = dbgfileptr;
  136. dbgfileptr = debugfs_create_bool("alloc_profile_enable", 0644,
  137. tbl.dentry, &tbl.alloc_profile_enable);
  138. if (IS_ERR(dbgfileptr)) {
  139. if (PTR_ERR(dbgfileptr) == -ENODEV)
  140. CAM_WARN(CAM_MEM, "DebugFS not enabled in kernel!");
  141. else
  142. rc = PTR_ERR(dbgfileptr);
  143. }
  144. end:
  145. return rc;
  146. }
  147. int cam_mem_mgr_init(void)
  148. {
  149. int i;
  150. int bitmap_size;
  151. int rc = 0;
  152. memset(tbl.bufq, 0, sizeof(tbl.bufq));
  153. if (cam_smmu_need_force_alloc_cached(&tbl.force_cache_allocs)) {
  154. CAM_ERR(CAM_MEM, "Error in getting force cache alloc flag");
  155. return -EINVAL;
  156. }
  157. tbl.need_shared_buffer_padding = cam_smmu_need_shared_buffer_padding();
  158. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  159. rc = cam_mem_mgr_get_dma_heaps();
  160. if (rc) {
  161. CAM_ERR(CAM_MEM, "Failed in getting dma heaps rc=%d", rc);
  162. return rc;
  163. }
  164. #endif
  165. bitmap_size = BITS_TO_LONGS(CAM_MEM_BUFQ_MAX) * sizeof(long);
  166. tbl.bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  167. if (!tbl.bitmap) {
  168. rc = -ENOMEM;
  169. goto put_heaps;
  170. }
  171. tbl.bits = bitmap_size * BITS_PER_BYTE;
  172. bitmap_zero(tbl.bitmap, tbl.bits);
  173. /* We need to reserve slot 0 because 0 is invalid */
  174. set_bit(0, tbl.bitmap);
  175. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  176. tbl.bufq[i].fd = -1;
  177. tbl.bufq[i].buf_handle = -1;
  178. }
  179. mutex_init(&tbl.m_lock);
  180. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED);
  181. cam_mem_mgr_create_debug_fs();
  182. return 0;
  183. put_heaps:
  184. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  185. cam_mem_mgr_put_dma_heaps();
  186. #endif
  187. return rc;
  188. }
  189. static int32_t cam_mem_get_slot(void)
  190. {
  191. int32_t idx;
  192. mutex_lock(&tbl.m_lock);
  193. idx = find_first_zero_bit(tbl.bitmap, tbl.bits);
  194. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  195. mutex_unlock(&tbl.m_lock);
  196. return -ENOMEM;
  197. }
  198. set_bit(idx, tbl.bitmap);
  199. tbl.bufq[idx].active = true;
  200. ktime_get_real_ts64(&(tbl.bufq[idx].timestamp));
  201. mutex_init(&tbl.bufq[idx].q_lock);
  202. mutex_unlock(&tbl.m_lock);
  203. return idx;
  204. }
  205. static void cam_mem_put_slot(int32_t idx)
  206. {
  207. mutex_lock(&tbl.m_lock);
  208. mutex_lock(&tbl.bufq[idx].q_lock);
  209. tbl.bufq[idx].active = false;
  210. tbl.bufq[idx].is_internal = false;
  211. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  212. mutex_unlock(&tbl.bufq[idx].q_lock);
  213. mutex_destroy(&tbl.bufq[idx].q_lock);
  214. clear_bit(idx, tbl.bitmap);
  215. mutex_unlock(&tbl.m_lock);
  216. }
  217. int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle,
  218. dma_addr_t *iova_ptr, size_t *len_ptr)
  219. {
  220. int rc = 0, idx;
  221. *len_ptr = 0;
  222. if (!atomic_read(&cam_mem_mgr_state)) {
  223. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  224. return -EINVAL;
  225. }
  226. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  227. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  228. return -ENOENT;
  229. if (!tbl.bufq[idx].active) {
  230. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  231. idx);
  232. return -EAGAIN;
  233. }
  234. mutex_lock(&tbl.bufq[idx].q_lock);
  235. if (buf_handle != tbl.bufq[idx].buf_handle) {
  236. rc = -EINVAL;
  237. goto handle_mismatch;
  238. }
  239. if (CAM_MEM_MGR_IS_SECURE_HDL(buf_handle))
  240. rc = cam_smmu_get_stage2_iova(mmu_handle,
  241. tbl.bufq[idx].fd,
  242. iova_ptr,
  243. len_ptr);
  244. else
  245. rc = cam_smmu_get_iova(mmu_handle,
  246. tbl.bufq[idx].fd,
  247. iova_ptr,
  248. len_ptr);
  249. if (rc) {
  250. CAM_ERR(CAM_MEM,
  251. "fail to map buf_hdl:0x%x, mmu_hdl: 0x%x for fd:%d",
  252. buf_handle, mmu_handle, tbl.bufq[idx].fd);
  253. goto handle_mismatch;
  254. }
  255. CAM_DBG(CAM_MEM,
  256. "handle:0x%x fd:%d iova_ptr:0x%llx len_ptr:%llu",
  257. mmu_handle, tbl.bufq[idx].fd, iova_ptr, *len_ptr);
  258. handle_mismatch:
  259. mutex_unlock(&tbl.bufq[idx].q_lock);
  260. return rc;
  261. }
  262. EXPORT_SYMBOL(cam_mem_get_io_buf);
  263. int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len)
  264. {
  265. int idx;
  266. if (!atomic_read(&cam_mem_mgr_state)) {
  267. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  268. return -EINVAL;
  269. }
  270. if (!atomic_read(&cam_mem_mgr_state)) {
  271. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  272. return -EINVAL;
  273. }
  274. if (!buf_handle || !vaddr_ptr || !len)
  275. return -EINVAL;
  276. idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle);
  277. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  278. return -EINVAL;
  279. if (!tbl.bufq[idx].active) {
  280. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  281. idx);
  282. return -EPERM;
  283. }
  284. if (buf_handle != tbl.bufq[idx].buf_handle)
  285. return -EINVAL;
  286. if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS))
  287. return -EINVAL;
  288. if (tbl.bufq[idx].kmdvaddr) {
  289. *vaddr_ptr = tbl.bufq[idx].kmdvaddr;
  290. *len = tbl.bufq[idx].len;
  291. } else {
  292. CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle",
  293. buf_handle);
  294. return -EINVAL;
  295. }
  296. return 0;
  297. }
  298. EXPORT_SYMBOL(cam_mem_get_cpu_buf);
  299. int cam_mem_mgr_cache_ops(struct cam_mem_cache_ops_cmd *cmd)
  300. {
  301. int rc = 0, idx;
  302. uint32_t cache_dir;
  303. unsigned long dmabuf_flag = 0;
  304. if (!atomic_read(&cam_mem_mgr_state)) {
  305. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  306. return -EINVAL;
  307. }
  308. if (!cmd)
  309. return -EINVAL;
  310. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  311. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0)
  312. return -EINVAL;
  313. mutex_lock(&tbl.bufq[idx].q_lock);
  314. if (!tbl.bufq[idx].active) {
  315. CAM_ERR(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  316. idx);
  317. rc = -EINVAL;
  318. goto end;
  319. }
  320. if (cmd->buf_handle != tbl.bufq[idx].buf_handle) {
  321. rc = -EINVAL;
  322. goto end;
  323. }
  324. rc = dma_buf_get_flags(tbl.bufq[idx].dma_buf, &dmabuf_flag);
  325. if (rc) {
  326. CAM_ERR(CAM_MEM, "cache get flags failed %d", rc);
  327. goto end;
  328. }
  329. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  330. CAM_DBG(CAM_MEM, "Calling dmap buf APIs for cache operations");
  331. cache_dir = DMA_BIDIRECTIONAL;
  332. #else
  333. if (dmabuf_flag & ION_FLAG_CACHED) {
  334. switch (cmd->mem_cache_ops) {
  335. case CAM_MEM_CLEAN_CACHE:
  336. cache_dir = DMA_TO_DEVICE;
  337. break;
  338. case CAM_MEM_INV_CACHE:
  339. cache_dir = DMA_FROM_DEVICE;
  340. break;
  341. case CAM_MEM_CLEAN_INV_CACHE:
  342. cache_dir = DMA_BIDIRECTIONAL;
  343. break;
  344. default:
  345. CAM_ERR(CAM_MEM,
  346. "invalid cache ops :%d", cmd->mem_cache_ops);
  347. rc = -EINVAL;
  348. goto end;
  349. }
  350. } else {
  351. CAM_DBG(CAM_MEM, "BUF is not cached");
  352. goto end;
  353. }
  354. #endif
  355. rc = dma_buf_begin_cpu_access(tbl.bufq[idx].dma_buf,
  356. (cmd->mem_cache_ops == CAM_MEM_CLEAN_INV_CACHE) ?
  357. DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
  358. if (rc) {
  359. CAM_ERR(CAM_MEM, "dma begin access failed rc=%d", rc);
  360. goto end;
  361. }
  362. rc = dma_buf_end_cpu_access(tbl.bufq[idx].dma_buf,
  363. cache_dir);
  364. if (rc) {
  365. CAM_ERR(CAM_MEM, "dma end access failed rc=%d", rc);
  366. goto end;
  367. }
  368. end:
  369. mutex_unlock(&tbl.bufq[idx].q_lock);
  370. return rc;
  371. }
  372. EXPORT_SYMBOL(cam_mem_mgr_cache_ops);
  373. #if IS_REACHABLE(CONFIG_DMABUF_HEAPS)
  374. #define CAM_MAX_VMIDS 4
  375. static void cam_mem_mgr_put_dma_heaps(void)
  376. {
  377. CAM_DBG(CAM_MEM, "Releasing DMA Buf heaps usage");
  378. }
  379. static int cam_mem_mgr_get_dma_heaps(void)
  380. {
  381. int rc = 0;
  382. tbl.system_heap = NULL;
  383. tbl.system_uncached_heap = NULL;
  384. tbl.camera_heap = NULL;
  385. tbl.camera_uncached_heap = NULL;
  386. tbl.secure_display_heap = NULL;
  387. tbl.system_heap = dma_heap_find("qcom,system");
  388. if (IS_ERR_OR_NULL(tbl.system_heap)) {
  389. rc = PTR_ERR(tbl.system_heap);
  390. CAM_ERR(CAM_MEM, "qcom system heap not found, rc=%d", rc);
  391. tbl.system_heap = NULL;
  392. goto put_heaps;
  393. }
  394. tbl.system_uncached_heap = dma_heap_find("qcom,system-uncached");
  395. if (IS_ERR_OR_NULL(tbl.system_uncached_heap)) {
  396. if (tbl.force_cache_allocs) {
  397. /* optional, we anyway do not use uncached */
  398. CAM_DBG(CAM_MEM,
  399. "qcom system-uncached heap not found, err=%d",
  400. PTR_ERR(tbl.system_uncached_heap));
  401. tbl.system_uncached_heap = NULL;
  402. } else {
  403. /* fatal, must need uncached heaps */
  404. rc = PTR_ERR(tbl.system_uncached_heap);
  405. CAM_ERR(CAM_MEM,
  406. "qcom system-uncached heap not found, rc=%d",
  407. rc);
  408. tbl.system_uncached_heap = NULL;
  409. goto put_heaps;
  410. }
  411. }
  412. tbl.secure_display_heap = dma_heap_find("qcom,display");
  413. if (IS_ERR_OR_NULL(tbl.secure_display_heap)) {
  414. rc = PTR_ERR(tbl.secure_display_heap);
  415. CAM_ERR(CAM_MEM, "qcom,display heap not found, rc=%d",
  416. rc);
  417. tbl.secure_display_heap = NULL;
  418. goto put_heaps;
  419. }
  420. tbl.camera_heap = dma_heap_find("qcom,camera");
  421. if (IS_ERR_OR_NULL(tbl.camera_heap)) {
  422. /* optional heap, not a fatal error */
  423. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  424. PTR_ERR(tbl.camera_heap));
  425. tbl.camera_heap = NULL;
  426. }
  427. tbl.camera_uncached_heap = dma_heap_find("qcom,camera-uncached");
  428. if (IS_ERR_OR_NULL(tbl.camera_uncached_heap)) {
  429. /* optional heap, not a fatal error */
  430. CAM_DBG(CAM_MEM, "qcom camera heap not found, err=%d",
  431. PTR_ERR(tbl.camera_uncached_heap));
  432. tbl.camera_uncached_heap = NULL;
  433. }
  434. CAM_INFO(CAM_MEM,
  435. "Heaps : system=%pK, system_uncached=%pK, camera=%pK, camera-uncached=%pK, secure_display=%pK",
  436. tbl.system_heap, tbl.system_uncached_heap,
  437. tbl.camera_heap, tbl.camera_uncached_heap,
  438. tbl.secure_display_heap);
  439. return 0;
  440. put_heaps:
  441. cam_mem_mgr_put_dma_heaps();
  442. return rc;
  443. }
  444. static int cam_mem_util_get_dma_buf(size_t len,
  445. unsigned int cam_flags,
  446. struct dma_buf **buf)
  447. {
  448. int rc = 0;
  449. struct dma_heap *heap;
  450. struct dma_heap *try_heap = NULL;
  451. struct timespec64 ts1, ts2;
  452. long microsec = 0;
  453. bool use_cached_heap = false;
  454. struct mem_buf_lend_kernel_arg arg;
  455. int vmids[CAM_MAX_VMIDS];
  456. int perms[CAM_MAX_VMIDS];
  457. int num_vmids = 0;
  458. if (!buf) {
  459. CAM_ERR(CAM_MEM, "Invalid params");
  460. return -EINVAL;
  461. }
  462. if (tbl.alloc_profile_enable)
  463. CAM_GET_TIMESTAMP(ts1);
  464. if ((cam_flags & CAM_MEM_FLAG_CACHE) ||
  465. (tbl.force_cache_allocs &&
  466. (!(cam_flags & CAM_MEM_FLAG_PROTECTED_MODE)))) {
  467. CAM_DBG(CAM_MEM,
  468. "Using CACHED heap, cam_flags=0x%x, force_cache_allocs=%d",
  469. cam_flags, tbl.force_cache_allocs);
  470. use_cached_heap = true;
  471. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  472. use_cached_heap = true;
  473. CAM_DBG(CAM_MEM,
  474. "Using CACHED heap for secure, cam_flags=0x%x, force_cache_allocs=%d",
  475. cam_flags, tbl.force_cache_allocs);
  476. } else {
  477. use_cached_heap = false;
  478. CAM_ERR(CAM_MEM,
  479. "Using UNCACHED heap not supported, cam_flags=0x%x, force_cache_allocs=%d",
  480. cam_flags, tbl.force_cache_allocs);
  481. /*
  482. * Need a better handling based on whether dma-buf-heaps support
  483. * uncached heaps or not. For now, assume not supported.
  484. */
  485. return -EINVAL;
  486. }
  487. if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  488. heap = tbl.secure_display_heap;
  489. vmids[num_vmids] = VMID_CP_CAMERA;
  490. perms[num_vmids] = PERM_READ | PERM_WRITE;
  491. num_vmids++;
  492. if (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT) {
  493. CAM_DBG(CAM_MEM, "Secure mode CDSP flags");
  494. vmids[num_vmids] = VMID_CP_CDSP;
  495. perms[num_vmids] = PERM_READ | PERM_WRITE;
  496. num_vmids++;
  497. }
  498. } else if (use_cached_heap) {
  499. try_heap = tbl.camera_heap;
  500. heap = tbl.system_heap;
  501. } else {
  502. try_heap = tbl.camera_uncached_heap;
  503. heap = tbl.system_uncached_heap;
  504. }
  505. CAM_DBG(CAM_MEM, "Using heaps : try=%pK, heap=%pK", try_heap, heap);
  506. *buf = NULL;
  507. if (!try_heap && !heap) {
  508. CAM_ERR(CAM_MEM,
  509. "No heap available for allocation, cant allocate");
  510. return -EINVAL;
  511. }
  512. if (try_heap) {
  513. *buf = dma_heap_buffer_alloc(try_heap, len, O_RDWR, 0);
  514. if (IS_ERR(*buf)) {
  515. CAM_WARN(CAM_MEM,
  516. "Failed in allocating from try heap, heap=%pK, len=%zu, err=%d",
  517. try_heap, len, PTR_ERR(*buf));
  518. *buf = NULL;
  519. }
  520. }
  521. if (*buf == NULL) {
  522. *buf = dma_heap_buffer_alloc(heap, len, O_RDWR, 0);
  523. if (IS_ERR(*buf)) {
  524. rc = PTR_ERR(*buf);
  525. CAM_ERR(CAM_MEM,
  526. "Failed in allocating from heap, heap=%pK, len=%zu, err=%d",
  527. heap, len, rc);
  528. *buf = NULL;
  529. return rc;
  530. }
  531. }
  532. if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  533. if (num_vmids >= CAM_MAX_VMIDS) {
  534. CAM_ERR(CAM_MEM, "Insufficient array size for vmids %d", num_vmids);
  535. rc = -EINVAL;
  536. goto end;
  537. }
  538. arg.nr_acl_entries = num_vmids;
  539. arg.vmids = vmids;
  540. arg.perms = perms;
  541. rc = mem_buf_lend(*buf, &arg);
  542. if (rc) {
  543. CAM_ERR(CAM_MEM,
  544. "Failed in buf lend rc=%d, buf=%pK, vmids [0]=0x%x, [1]=0x%x, [2]=0x%x",
  545. rc, *buf, vmids[0], vmids[1], vmids[2]);
  546. goto end;
  547. }
  548. }
  549. CAM_DBG(CAM_MEM, "Allocate success, len=%zu, *buf=%pK", len, *buf);
  550. if (tbl.alloc_profile_enable) {
  551. CAM_GET_TIMESTAMP(ts2);
  552. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  553. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  554. len, microsec);
  555. }
  556. return rc;
  557. end:
  558. dma_buf_put(*buf);
  559. return rc;
  560. }
  561. #else
  562. static int cam_mem_util_get_dma_buf(size_t len,
  563. unsigned int cam_flags,
  564. struct dma_buf **buf)
  565. {
  566. int rc = 0;
  567. unsigned int heap_id;
  568. int32_t ion_flag = 0;
  569. struct timespec64 ts1, ts2;
  570. long microsec = 0;
  571. if (!buf) {
  572. CAM_ERR(CAM_MEM, "Invalid params");
  573. return -EINVAL;
  574. }
  575. if (tbl.alloc_profile_enable)
  576. CAM_GET_TIMESTAMP(ts1);
  577. if ((cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) &&
  578. (cam_flags & CAM_MEM_FLAG_CDSP_OUTPUT)) {
  579. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  580. ion_flag |=
  581. ION_FLAG_SECURE | ION_FLAG_CP_CAMERA | ION_FLAG_CP_CDSP;
  582. } else if (cam_flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  583. heap_id = ION_HEAP(ION_SECURE_DISPLAY_HEAP_ID);
  584. ion_flag |= ION_FLAG_SECURE | ION_FLAG_CP_CAMERA;
  585. } else {
  586. heap_id = ION_HEAP(ION_SYSTEM_HEAP_ID) |
  587. ION_HEAP(ION_CAMERA_HEAP_ID);
  588. }
  589. if (cam_flags & CAM_MEM_FLAG_CACHE)
  590. ion_flag |= ION_FLAG_CACHED;
  591. else
  592. ion_flag &= ~ION_FLAG_CACHED;
  593. if (tbl.force_cache_allocs && (!(ion_flag & ION_FLAG_SECURE)))
  594. ion_flag |= ION_FLAG_CACHED;
  595. *buf = ion_alloc(len, heap_id, ion_flag);
  596. if (IS_ERR_OR_NULL(*buf))
  597. return -ENOMEM;
  598. if (tbl.alloc_profile_enable) {
  599. CAM_GET_TIMESTAMP(ts2);
  600. CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec);
  601. trace_cam_log_event("IONAllocProfile", "size and time in micro",
  602. len, microsec);
  603. }
  604. return rc;
  605. }
  606. #endif
  607. static int cam_mem_util_buffer_alloc(size_t len, uint32_t flags,
  608. struct dma_buf **dmabuf,
  609. int *fd)
  610. {
  611. int rc;
  612. struct dma_buf *temp_dmabuf = NULL;
  613. rc = cam_mem_util_get_dma_buf(len, flags, dmabuf);
  614. if (rc) {
  615. CAM_ERR(CAM_MEM,
  616. "Error allocating dma buf : len=%llu, flags=0x%x",
  617. len, flags);
  618. return rc;
  619. }
  620. *fd = dma_buf_fd(*dmabuf, O_CLOEXEC);
  621. if (*fd < 0) {
  622. CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd);
  623. rc = -EINVAL;
  624. goto put_buf;
  625. }
  626. CAM_DBG(CAM_MEM, "Alloc success : len=%zu, *dmabuf=%pK, fd=%d",
  627. len, *dmabuf, *fd);
  628. /*
  629. * increment the ref count so that ref count becomes 2 here
  630. * when we close fd, refcount becomes 1 and when we do
  631. * dmap_put_buf, ref count becomes 0 and memory will be freed.
  632. */
  633. temp_dmabuf = dma_buf_get(*fd);
  634. if (IS_ERR_OR_NULL(temp_dmabuf)) {
  635. CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd);
  636. rc = -EINVAL;
  637. goto put_buf;
  638. }
  639. return rc;
  640. put_buf:
  641. dma_buf_put(*dmabuf);
  642. return rc;
  643. }
  644. static int cam_mem_util_check_alloc_flags(struct cam_mem_mgr_alloc_cmd *cmd)
  645. {
  646. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  647. CAM_ERR(CAM_MEM, "Num of mmu hdl exceeded maximum(%d)",
  648. CAM_MEM_MMU_MAX_HANDLE);
  649. return -EINVAL;
  650. }
  651. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  652. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  653. CAM_ERR(CAM_MEM, "Kernel mapping in secure mode not allowed");
  654. return -EINVAL;
  655. }
  656. return 0;
  657. }
  658. static int cam_mem_util_check_map_flags(struct cam_mem_mgr_map_cmd *cmd)
  659. {
  660. if (!cmd->flags) {
  661. CAM_ERR(CAM_MEM, "Invalid flags");
  662. return -EINVAL;
  663. }
  664. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  665. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  666. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  667. return -EINVAL;
  668. }
  669. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE &&
  670. cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  671. CAM_ERR(CAM_MEM,
  672. "Kernel mapping in secure mode not allowed, flags=0x%x",
  673. cmd->flags);
  674. return -EINVAL;
  675. }
  676. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  677. CAM_ERR(CAM_MEM,
  678. "Shared memory buffers are not allowed to be mapped");
  679. return -EINVAL;
  680. }
  681. return 0;
  682. }
  683. static int cam_mem_util_map_hw_va(uint32_t flags,
  684. int32_t *mmu_hdls,
  685. int32_t num_hdls,
  686. int fd,
  687. dma_addr_t *hw_vaddr,
  688. size_t *len,
  689. enum cam_smmu_region_id region,
  690. bool is_internal)
  691. {
  692. int i;
  693. int rc = -1;
  694. int dir = cam_mem_util_get_dma_dir(flags);
  695. bool dis_delayed_unmap = false;
  696. if (dir < 0) {
  697. CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir);
  698. return dir;
  699. }
  700. if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP)
  701. dis_delayed_unmap = true;
  702. CAM_DBG(CAM_MEM,
  703. "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d",
  704. fd, flags, dir, num_hdls);
  705. for (i = 0; i < num_hdls; i++) {
  706. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  707. rc = cam_smmu_map_stage2_iova(mmu_hdls[i], fd, dir, hw_vaddr, len);
  708. else
  709. rc = cam_smmu_map_user_iova(mmu_hdls[i], fd, dis_delayed_unmap, dir,
  710. hw_vaddr, len, region, is_internal);
  711. if (rc) {
  712. CAM_ERR(CAM_MEM,
  713. "Failed %s map to smmu, i=%d, fd=%d, dir=%d, mmu_hdl=%d, rc=%d",
  714. (flags & CAM_MEM_FLAG_PROTECTED_MODE) ? "" : "secured",
  715. i, fd, dir, mmu_hdls[i], rc);
  716. goto multi_map_fail;
  717. }
  718. }
  719. return rc;
  720. multi_map_fail:
  721. for (--i; i>= 0; i--) {
  722. if (flags & CAM_MEM_FLAG_PROTECTED_MODE)
  723. cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  724. else
  725. cam_smmu_unmap_user_iova(mmu_hdls[i], fd, CAM_SMMU_REGION_IO);
  726. }
  727. return rc;
  728. }
  729. int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd)
  730. {
  731. int rc;
  732. int32_t idx;
  733. struct dma_buf *dmabuf = NULL;
  734. int fd = -1;
  735. dma_addr_t hw_vaddr = 0;
  736. size_t len;
  737. uintptr_t kvaddr = 0;
  738. size_t klen;
  739. if (!atomic_read(&cam_mem_mgr_state)) {
  740. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  741. return -EINVAL;
  742. }
  743. if (!cmd) {
  744. CAM_ERR(CAM_MEM, " Invalid argument");
  745. return -EINVAL;
  746. }
  747. len = cmd->len;
  748. if (tbl.need_shared_buffer_padding &&
  749. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)) {
  750. len += CAM_MEM_SHARED_BUFFER_PAD_4K;
  751. CAM_DBG(CAM_MEM, "Pad 4k size, actual %llu, allocating %zu",
  752. cmd->len, len);
  753. }
  754. rc = cam_mem_util_check_alloc_flags(cmd);
  755. if (rc) {
  756. CAM_ERR(CAM_MEM, "Invalid flags: flags = 0x%X, rc=%d",
  757. cmd->flags, rc);
  758. return rc;
  759. }
  760. rc = cam_mem_util_buffer_alloc(len, cmd->flags, &dmabuf, &fd);
  761. if (rc) {
  762. CAM_ERR(CAM_MEM,
  763. "Ion Alloc failed, len=%llu, align=%llu, flags=0x%x, num_hdl=%d",
  764. len, cmd->align, cmd->flags, cmd->num_hdl);
  765. cam_mem_mgr_print_tbl();
  766. return rc;
  767. }
  768. if (!dmabuf) {
  769. CAM_ERR(CAM_MEM,
  770. "Ion Alloc return NULL dmabuf! fd=%d, len=%d", fd, len);
  771. cam_mem_mgr_print_tbl();
  772. return rc;
  773. }
  774. idx = cam_mem_get_slot();
  775. if (idx < 0) {
  776. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  777. rc = -ENOMEM;
  778. goto slot_fail;
  779. }
  780. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  781. (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  782. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  783. enum cam_smmu_region_id region;
  784. if (cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  785. region = CAM_SMMU_REGION_IO;
  786. if (cmd->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  787. region = CAM_SMMU_REGION_SHARED;
  788. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  789. region = CAM_SMMU_REGION_IO;
  790. rc = cam_mem_util_map_hw_va(cmd->flags,
  791. cmd->mmu_hdls,
  792. cmd->num_hdl,
  793. fd,
  794. &hw_vaddr,
  795. &len,
  796. region,
  797. true);
  798. if (rc) {
  799. CAM_ERR(CAM_MEM,
  800. "Failed in map_hw_va len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d",
  801. len, cmd->flags,
  802. fd, region, cmd->num_hdl, rc);
  803. if (rc == -EALREADY) {
  804. if ((size_t)dmabuf->size != len)
  805. rc = -EBADR;
  806. cam_mem_mgr_print_tbl();
  807. }
  808. goto map_hw_fail;
  809. }
  810. }
  811. mutex_lock(&tbl.bufq[idx].q_lock);
  812. tbl.bufq[idx].fd = fd;
  813. tbl.bufq[idx].dma_buf = NULL;
  814. tbl.bufq[idx].flags = cmd->flags;
  815. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, fd);
  816. tbl.bufq[idx].is_internal = true;
  817. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  818. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  819. if (cmd->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  820. rc = cam_mem_util_map_cpu_va(dmabuf, &kvaddr, &klen);
  821. if (rc) {
  822. CAM_ERR(CAM_MEM, "dmabuf: %pK mapping failed: %d",
  823. dmabuf, rc);
  824. goto map_kernel_fail;
  825. }
  826. }
  827. if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG)
  828. tbl.dbg_buf_idx = idx;
  829. tbl.bufq[idx].kmdvaddr = kvaddr;
  830. tbl.bufq[idx].vaddr = hw_vaddr;
  831. tbl.bufq[idx].dma_buf = dmabuf;
  832. tbl.bufq[idx].len = len;
  833. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  834. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  835. sizeof(int32_t) * cmd->num_hdl);
  836. tbl.bufq[idx].is_imported = false;
  837. mutex_unlock(&tbl.bufq[idx].q_lock);
  838. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  839. cmd->out.fd = tbl.bufq[idx].fd;
  840. cmd->out.vaddr = 0;
  841. CAM_DBG(CAM_MEM,
  842. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  843. cmd->out.fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  844. tbl.bufq[idx].len);
  845. return rc;
  846. map_kernel_fail:
  847. mutex_unlock(&tbl.bufq[idx].q_lock);
  848. map_hw_fail:
  849. cam_mem_put_slot(idx);
  850. slot_fail:
  851. dma_buf_put(dmabuf);
  852. return rc;
  853. }
  854. static bool cam_mem_util_is_map_internal(int32_t fd)
  855. {
  856. uint32_t i;
  857. bool is_internal = false;
  858. mutex_lock(&tbl.m_lock);
  859. for_each_set_bit(i, tbl.bitmap, tbl.bits) {
  860. if (tbl.bufq[i].fd == fd) {
  861. is_internal = tbl.bufq[i].is_internal;
  862. break;
  863. }
  864. }
  865. mutex_unlock(&tbl.m_lock);
  866. return is_internal;
  867. }
  868. int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd)
  869. {
  870. int32_t idx;
  871. int rc;
  872. struct dma_buf *dmabuf;
  873. dma_addr_t hw_vaddr = 0;
  874. size_t len = 0;
  875. bool is_internal = false;
  876. if (!atomic_read(&cam_mem_mgr_state)) {
  877. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  878. return -EINVAL;
  879. }
  880. if (!cmd || (cmd->fd < 0)) {
  881. CAM_ERR(CAM_MEM, "Invalid argument");
  882. return -EINVAL;
  883. }
  884. if (cmd->num_hdl > CAM_MEM_MMU_MAX_HANDLE) {
  885. CAM_ERR(CAM_MEM, "Num of mmu hdl %d exceeded maximum(%d)",
  886. cmd->num_hdl, CAM_MEM_MMU_MAX_HANDLE);
  887. return -EINVAL;
  888. }
  889. rc = cam_mem_util_check_map_flags(cmd);
  890. if (rc) {
  891. CAM_ERR(CAM_MEM, "Invalid flags: flags = %X", cmd->flags);
  892. return rc;
  893. }
  894. dmabuf = dma_buf_get(cmd->fd);
  895. if (IS_ERR_OR_NULL((void *)(dmabuf))) {
  896. CAM_ERR(CAM_MEM, "Failed to import dma_buf fd");
  897. return -EINVAL;
  898. }
  899. is_internal = cam_mem_util_is_map_internal(cmd->fd);
  900. idx = cam_mem_get_slot();
  901. if (idx < 0) {
  902. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d, fd=%d",
  903. idx, cmd->fd);
  904. rc = -ENOMEM;
  905. goto slot_fail;
  906. }
  907. if ((cmd->flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  908. (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  909. rc = cam_mem_util_map_hw_va(cmd->flags,
  910. cmd->mmu_hdls,
  911. cmd->num_hdl,
  912. cmd->fd,
  913. &hw_vaddr,
  914. &len,
  915. CAM_SMMU_REGION_IO,
  916. is_internal);
  917. if (rc) {
  918. CAM_ERR(CAM_MEM,
  919. "Failed in map_hw_va, flags=0x%x, fd=%d, len=%llu, region=%d, num_hdl=%d, rc=%d",
  920. cmd->flags, cmd->fd, len,
  921. CAM_SMMU_REGION_IO, cmd->num_hdl, rc);
  922. if (rc == -EALREADY) {
  923. if ((size_t)dmabuf->size != len) {
  924. rc = -EBADR;
  925. cam_mem_mgr_print_tbl();
  926. }
  927. }
  928. goto map_fail;
  929. }
  930. }
  931. mutex_lock(&tbl.bufq[idx].q_lock);
  932. tbl.bufq[idx].fd = cmd->fd;
  933. tbl.bufq[idx].dma_buf = NULL;
  934. tbl.bufq[idx].flags = cmd->flags;
  935. tbl.bufq[idx].buf_handle = GET_MEM_HANDLE(idx, cmd->fd);
  936. if (cmd->flags & CAM_MEM_FLAG_PROTECTED_MODE)
  937. CAM_MEM_MGR_SET_SECURE_HDL(tbl.bufq[idx].buf_handle, true);
  938. tbl.bufq[idx].kmdvaddr = 0;
  939. if (cmd->num_hdl > 0)
  940. tbl.bufq[idx].vaddr = hw_vaddr;
  941. else
  942. tbl.bufq[idx].vaddr = 0;
  943. tbl.bufq[idx].dma_buf = dmabuf;
  944. tbl.bufq[idx].len = len;
  945. tbl.bufq[idx].num_hdl = cmd->num_hdl;
  946. memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls,
  947. sizeof(int32_t) * cmd->num_hdl);
  948. tbl.bufq[idx].is_imported = true;
  949. tbl.bufq[idx].is_internal = is_internal;
  950. mutex_unlock(&tbl.bufq[idx].q_lock);
  951. cmd->out.buf_handle = tbl.bufq[idx].buf_handle;
  952. cmd->out.vaddr = 0;
  953. cmd->out.size = (uint32_t)len;
  954. CAM_DBG(CAM_MEM,
  955. "fd=%d, flags=0x%x, num_hdl=%d, idx=%d, buf handle=%x, len=%zu",
  956. cmd->fd, cmd->flags, cmd->num_hdl, idx, cmd->out.buf_handle,
  957. tbl.bufq[idx].len);
  958. return rc;
  959. map_fail:
  960. cam_mem_put_slot(idx);
  961. slot_fail:
  962. dma_buf_put(dmabuf);
  963. return rc;
  964. }
  965. static int cam_mem_util_unmap_hw_va(int32_t idx,
  966. enum cam_smmu_region_id region,
  967. enum cam_smmu_mapping_client client)
  968. {
  969. int i;
  970. uint32_t flags;
  971. int32_t *mmu_hdls;
  972. int num_hdls;
  973. int fd;
  974. int rc = 0;
  975. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  976. CAM_ERR(CAM_MEM, "Incorrect index");
  977. return -EINVAL;
  978. }
  979. flags = tbl.bufq[idx].flags;
  980. mmu_hdls = tbl.bufq[idx].hdls;
  981. num_hdls = tbl.bufq[idx].num_hdl;
  982. fd = tbl.bufq[idx].fd;
  983. CAM_DBG(CAM_MEM,
  984. "unmap_hw_va : idx=%d, fd=%x, flags=0x%x, num_hdls=%d, client=%d",
  985. idx, fd, flags, num_hdls, client);
  986. if (flags & CAM_MEM_FLAG_PROTECTED_MODE) {
  987. for (i = 0; i < num_hdls; i++) {
  988. rc = cam_smmu_unmap_stage2_iova(mmu_hdls[i], fd);
  989. if (rc < 0) {
  990. CAM_ERR(CAM_MEM,
  991. "Failed in secure unmap, i=%d, fd=%d, mmu_hdl=%d, rc=%d",
  992. i, fd, mmu_hdls[i], rc);
  993. goto unmap_end;
  994. }
  995. }
  996. } else {
  997. for (i = 0; i < num_hdls; i++) {
  998. if (client == CAM_SMMU_MAPPING_USER) {
  999. rc = cam_smmu_unmap_user_iova(mmu_hdls[i],
  1000. fd, region);
  1001. } else if (client == CAM_SMMU_MAPPING_KERNEL) {
  1002. rc = cam_smmu_unmap_kernel_iova(mmu_hdls[i],
  1003. tbl.bufq[idx].dma_buf, region);
  1004. } else {
  1005. CAM_ERR(CAM_MEM,
  1006. "invalid caller for unmapping : %d",
  1007. client);
  1008. rc = -EINVAL;
  1009. }
  1010. if (rc < 0) {
  1011. CAM_ERR(CAM_MEM,
  1012. "Failed in unmap, i=%d, fd=%d, mmu_hdl=%d, region=%d, rc=%d",
  1013. i, fd, mmu_hdls[i], region, rc);
  1014. goto unmap_end;
  1015. }
  1016. }
  1017. }
  1018. return rc;
  1019. unmap_end:
  1020. CAM_ERR(CAM_MEM, "unmapping failed");
  1021. return rc;
  1022. }
  1023. static void cam_mem_mgr_unmap_active_buf(int idx)
  1024. {
  1025. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1026. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS)
  1027. region = CAM_SMMU_REGION_SHARED;
  1028. else if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1029. region = CAM_SMMU_REGION_IO;
  1030. cam_mem_util_unmap_hw_va(idx, region, CAM_SMMU_MAPPING_USER);
  1031. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)
  1032. cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1033. tbl.bufq[idx].kmdvaddr);
  1034. }
  1035. static int cam_mem_mgr_cleanup_table(void)
  1036. {
  1037. int i;
  1038. mutex_lock(&tbl.m_lock);
  1039. for (i = 1; i < CAM_MEM_BUFQ_MAX; i++) {
  1040. if (!tbl.bufq[i].active) {
  1041. CAM_DBG(CAM_MEM,
  1042. "Buffer inactive at idx=%d, continuing", i);
  1043. continue;
  1044. } else {
  1045. CAM_DBG(CAM_MEM,
  1046. "Active buffer at idx=%d, possible leak needs unmapping",
  1047. i);
  1048. cam_mem_mgr_unmap_active_buf(i);
  1049. }
  1050. mutex_lock(&tbl.bufq[i].q_lock);
  1051. if (tbl.bufq[i].dma_buf) {
  1052. dma_buf_put(tbl.bufq[i].dma_buf);
  1053. tbl.bufq[i].dma_buf = NULL;
  1054. }
  1055. tbl.bufq[i].fd = -1;
  1056. tbl.bufq[i].flags = 0;
  1057. tbl.bufq[i].buf_handle = -1;
  1058. tbl.bufq[i].vaddr = 0;
  1059. tbl.bufq[i].len = 0;
  1060. memset(tbl.bufq[i].hdls, 0,
  1061. sizeof(int32_t) * tbl.bufq[i].num_hdl);
  1062. tbl.bufq[i].num_hdl = 0;
  1063. tbl.bufq[i].dma_buf = NULL;
  1064. tbl.bufq[i].active = false;
  1065. tbl.bufq[i].is_internal = false;
  1066. mutex_unlock(&tbl.bufq[i].q_lock);
  1067. mutex_destroy(&tbl.bufq[i].q_lock);
  1068. }
  1069. bitmap_zero(tbl.bitmap, tbl.bits);
  1070. /* We need to reserve slot 0 because 0 is invalid */
  1071. set_bit(0, tbl.bitmap);
  1072. mutex_unlock(&tbl.m_lock);
  1073. return 0;
  1074. }
  1075. void cam_mem_mgr_deinit(void)
  1076. {
  1077. atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_UNINITIALIZED);
  1078. cam_mem_mgr_cleanup_table();
  1079. debugfs_remove_recursive(tbl.dentry);
  1080. mutex_lock(&tbl.m_lock);
  1081. bitmap_zero(tbl.bitmap, tbl.bits);
  1082. kfree(tbl.bitmap);
  1083. tbl.bitmap = NULL;
  1084. tbl.dbg_buf_idx = -1;
  1085. mutex_unlock(&tbl.m_lock);
  1086. mutex_destroy(&tbl.m_lock);
  1087. }
  1088. static int cam_mem_util_unmap(int32_t idx,
  1089. enum cam_smmu_mapping_client client)
  1090. {
  1091. int rc = 0;
  1092. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1093. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1094. CAM_ERR(CAM_MEM, "Incorrect index");
  1095. return -EINVAL;
  1096. }
  1097. CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx);
  1098. mutex_lock(&tbl.m_lock);
  1099. if ((!tbl.bufq[idx].active) &&
  1100. (tbl.bufq[idx].vaddr) == 0) {
  1101. CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,",
  1102. idx);
  1103. mutex_unlock(&tbl.m_lock);
  1104. return 0;
  1105. }
  1106. /* Deactivate the buffer queue to prevent multiple unmap */
  1107. mutex_lock(&tbl.bufq[idx].q_lock);
  1108. tbl.bufq[idx].active = false;
  1109. tbl.bufq[idx].vaddr = 0;
  1110. mutex_unlock(&tbl.bufq[idx].q_lock);
  1111. mutex_unlock(&tbl.m_lock);
  1112. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1113. if (tbl.bufq[idx].dma_buf && tbl.bufq[idx].kmdvaddr) {
  1114. rc = cam_mem_util_unmap_cpu_va(tbl.bufq[idx].dma_buf,
  1115. tbl.bufq[idx].kmdvaddr);
  1116. if (rc)
  1117. CAM_ERR(CAM_MEM,
  1118. "Failed, dmabuf=%pK, kmdvaddr=%pK",
  1119. tbl.bufq[idx].dma_buf,
  1120. (void *) tbl.bufq[idx].kmdvaddr);
  1121. }
  1122. }
  1123. /* SHARED flag gets precedence, all other flags after it */
  1124. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1125. region = CAM_SMMU_REGION_SHARED;
  1126. } else {
  1127. if (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1128. region = CAM_SMMU_REGION_IO;
  1129. }
  1130. if ((tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_READ_WRITE) ||
  1131. (tbl.bufq[idx].flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) ||
  1132. (tbl.bufq[idx].flags & CAM_MEM_FLAG_PROTECTED_MODE)) {
  1133. if (cam_mem_util_unmap_hw_va(idx, region, client))
  1134. CAM_ERR(CAM_MEM, "Failed, dmabuf=%pK",
  1135. tbl.bufq[idx].dma_buf);
  1136. if (client == CAM_SMMU_MAPPING_KERNEL)
  1137. tbl.bufq[idx].dma_buf = NULL;
  1138. }
  1139. mutex_lock(&tbl.m_lock);
  1140. mutex_lock(&tbl.bufq[idx].q_lock);
  1141. tbl.bufq[idx].flags = 0;
  1142. tbl.bufq[idx].buf_handle = -1;
  1143. memset(tbl.bufq[idx].hdls, 0,
  1144. sizeof(int32_t) * CAM_MEM_MMU_MAX_HANDLE);
  1145. CAM_DBG(CAM_MEM,
  1146. "Ion buf at idx = %d freeing fd = %d, imported %d, dma_buf %pK",
  1147. idx, tbl.bufq[idx].fd,
  1148. tbl.bufq[idx].is_imported,
  1149. tbl.bufq[idx].dma_buf);
  1150. if (tbl.bufq[idx].dma_buf)
  1151. dma_buf_put(tbl.bufq[idx].dma_buf);
  1152. tbl.bufq[idx].fd = -1;
  1153. tbl.bufq[idx].dma_buf = NULL;
  1154. tbl.bufq[idx].is_imported = false;
  1155. tbl.bufq[idx].is_internal = false;
  1156. tbl.bufq[idx].len = 0;
  1157. tbl.bufq[idx].num_hdl = 0;
  1158. memset(&tbl.bufq[idx].timestamp, 0, sizeof(struct timespec64));
  1159. mutex_unlock(&tbl.bufq[idx].q_lock);
  1160. mutex_destroy(&tbl.bufq[idx].q_lock);
  1161. clear_bit(idx, tbl.bitmap);
  1162. mutex_unlock(&tbl.m_lock);
  1163. return rc;
  1164. }
  1165. int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd)
  1166. {
  1167. int idx;
  1168. int rc;
  1169. if (!atomic_read(&cam_mem_mgr_state)) {
  1170. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1171. return -EINVAL;
  1172. }
  1173. if (!cmd) {
  1174. CAM_ERR(CAM_MEM, "Invalid argument");
  1175. return -EINVAL;
  1176. }
  1177. idx = CAM_MEM_MGR_GET_HDL_IDX(cmd->buf_handle);
  1178. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1179. CAM_ERR(CAM_MEM, "Incorrect index %d extracted from mem handle",
  1180. idx);
  1181. return -EINVAL;
  1182. }
  1183. if (!tbl.bufq[idx].active) {
  1184. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1185. return -EINVAL;
  1186. }
  1187. if (tbl.bufq[idx].buf_handle != cmd->buf_handle) {
  1188. CAM_ERR(CAM_MEM,
  1189. "Released buf handle %d not matching within table %d, idx=%d",
  1190. cmd->buf_handle, tbl.bufq[idx].buf_handle, idx);
  1191. return -EINVAL;
  1192. }
  1193. CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx);
  1194. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER);
  1195. return rc;
  1196. }
  1197. int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp,
  1198. struct cam_mem_mgr_memory_desc *out)
  1199. {
  1200. struct dma_buf *buf = NULL;
  1201. int ion_fd = -1;
  1202. int rc = 0;
  1203. uintptr_t kvaddr;
  1204. dma_addr_t iova = 0;
  1205. size_t request_len = 0;
  1206. uint32_t mem_handle;
  1207. int32_t idx;
  1208. int32_t smmu_hdl = 0;
  1209. int32_t num_hdl = 0;
  1210. enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED;
  1211. if (!atomic_read(&cam_mem_mgr_state)) {
  1212. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1213. return -EINVAL;
  1214. }
  1215. if (!inp || !out) {
  1216. CAM_ERR(CAM_MEM, "Invalid params");
  1217. return -EINVAL;
  1218. }
  1219. if (!(inp->flags & CAM_MEM_FLAG_HW_READ_WRITE ||
  1220. inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS ||
  1221. inp->flags & CAM_MEM_FLAG_CACHE)) {
  1222. CAM_ERR(CAM_MEM, "Invalid flags for request mem");
  1223. return -EINVAL;
  1224. }
  1225. rc = cam_mem_util_get_dma_buf(inp->size, inp->flags, &buf);
  1226. if (rc) {
  1227. CAM_ERR(CAM_MEM, "ION alloc failed for shared buffer");
  1228. goto ion_fail;
  1229. } else if (!buf) {
  1230. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1231. goto ion_fail;
  1232. } else {
  1233. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1234. }
  1235. /*
  1236. * we are mapping kva always here,
  1237. * update flags so that we do unmap properly
  1238. */
  1239. inp->flags |= CAM_MEM_FLAG_KMD_ACCESS;
  1240. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1241. if (rc) {
  1242. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1243. goto map_fail;
  1244. }
  1245. if (!inp->smmu_hdl) {
  1246. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1247. rc = -EINVAL;
  1248. goto smmu_fail;
  1249. }
  1250. /* SHARED flag gets precedence, all other flags after it */
  1251. if (inp->flags & CAM_MEM_FLAG_HW_SHARED_ACCESS) {
  1252. region = CAM_SMMU_REGION_SHARED;
  1253. } else {
  1254. if (inp->flags & CAM_MEM_FLAG_HW_READ_WRITE)
  1255. region = CAM_SMMU_REGION_IO;
  1256. }
  1257. rc = cam_smmu_map_kernel_iova(inp->smmu_hdl,
  1258. buf,
  1259. CAM_SMMU_MAP_RW,
  1260. &iova,
  1261. &request_len,
  1262. region);
  1263. if (rc < 0) {
  1264. CAM_ERR(CAM_MEM, "SMMU mapping failed");
  1265. goto smmu_fail;
  1266. }
  1267. smmu_hdl = inp->smmu_hdl;
  1268. num_hdl = 1;
  1269. idx = cam_mem_get_slot();
  1270. if (idx < 0) {
  1271. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1272. rc = -ENOMEM;
  1273. goto slot_fail;
  1274. }
  1275. mutex_lock(&tbl.bufq[idx].q_lock);
  1276. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1277. tbl.bufq[idx].dma_buf = buf;
  1278. tbl.bufq[idx].fd = -1;
  1279. tbl.bufq[idx].flags = inp->flags;
  1280. tbl.bufq[idx].buf_handle = mem_handle;
  1281. tbl.bufq[idx].kmdvaddr = kvaddr;
  1282. tbl.bufq[idx].vaddr = iova;
  1283. tbl.bufq[idx].len = inp->size;
  1284. tbl.bufq[idx].num_hdl = num_hdl;
  1285. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1286. sizeof(int32_t));
  1287. tbl.bufq[idx].is_imported = false;
  1288. mutex_unlock(&tbl.bufq[idx].q_lock);
  1289. out->kva = kvaddr;
  1290. out->iova = (uint32_t)iova;
  1291. out->smmu_hdl = smmu_hdl;
  1292. out->mem_handle = mem_handle;
  1293. out->len = inp->size;
  1294. out->region = region;
  1295. return rc;
  1296. slot_fail:
  1297. cam_smmu_unmap_kernel_iova(inp->smmu_hdl,
  1298. buf, region);
  1299. smmu_fail:
  1300. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1301. map_fail:
  1302. dma_buf_put(buf);
  1303. ion_fail:
  1304. return rc;
  1305. }
  1306. EXPORT_SYMBOL(cam_mem_mgr_request_mem);
  1307. int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp)
  1308. {
  1309. int32_t idx;
  1310. int rc;
  1311. if (!atomic_read(&cam_mem_mgr_state)) {
  1312. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1313. return -EINVAL;
  1314. }
  1315. if (!inp) {
  1316. CAM_ERR(CAM_MEM, "Invalid argument");
  1317. return -EINVAL;
  1318. }
  1319. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1320. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1321. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1322. return -EINVAL;
  1323. }
  1324. if (!tbl.bufq[idx].active) {
  1325. if (tbl.bufq[idx].vaddr == 0) {
  1326. CAM_ERR(CAM_MEM, "buffer is released already");
  1327. return 0;
  1328. }
  1329. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1330. return -EINVAL;
  1331. }
  1332. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1333. CAM_ERR(CAM_MEM,
  1334. "Released buf handle not matching within table");
  1335. return -EINVAL;
  1336. }
  1337. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1338. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1339. return rc;
  1340. }
  1341. EXPORT_SYMBOL(cam_mem_mgr_release_mem);
  1342. int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp,
  1343. enum cam_smmu_region_id region,
  1344. struct cam_mem_mgr_memory_desc *out)
  1345. {
  1346. struct dma_buf *buf = NULL;
  1347. int rc = 0;
  1348. int ion_fd = -1;
  1349. dma_addr_t iova = 0;
  1350. size_t request_len = 0;
  1351. uint32_t mem_handle;
  1352. int32_t idx;
  1353. int32_t smmu_hdl = 0;
  1354. int32_t num_hdl = 0;
  1355. uintptr_t kvaddr = 0;
  1356. if (!atomic_read(&cam_mem_mgr_state)) {
  1357. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1358. return -EINVAL;
  1359. }
  1360. if (!inp || !out) {
  1361. CAM_ERR(CAM_MEM, "Invalid param(s)");
  1362. return -EINVAL;
  1363. }
  1364. if (!inp->smmu_hdl) {
  1365. CAM_ERR(CAM_MEM, "Invalid SMMU handle");
  1366. return -EINVAL;
  1367. }
  1368. if ((region != CAM_SMMU_REGION_SECHEAP) &&
  1369. (region != CAM_SMMU_REGION_FWUNCACHED)) {
  1370. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1371. return -EINVAL;
  1372. }
  1373. rc = cam_mem_util_get_dma_buf(inp->size, 0, &buf);
  1374. if (rc) {
  1375. CAM_ERR(CAM_MEM, "ION alloc failed for sec heap buffer");
  1376. goto ion_fail;
  1377. } else if (!buf) {
  1378. CAM_ERR(CAM_MEM, "ION alloc returned NULL buffer");
  1379. goto ion_fail;
  1380. } else {
  1381. CAM_DBG(CAM_MEM, "Got dma_buf = %pK", buf);
  1382. }
  1383. if (inp->flags & CAM_MEM_FLAG_KMD_ACCESS) {
  1384. rc = cam_mem_util_map_cpu_va(buf, &kvaddr, &request_len);
  1385. if (rc) {
  1386. CAM_ERR(CAM_MEM, "Failed to get kernel vaddr");
  1387. goto kmap_fail;
  1388. }
  1389. }
  1390. rc = cam_smmu_reserve_buf_region(region,
  1391. inp->smmu_hdl, buf, &iova, &request_len);
  1392. if (rc) {
  1393. CAM_ERR(CAM_MEM, "Reserving secondary heap failed");
  1394. goto smmu_fail;
  1395. }
  1396. smmu_hdl = inp->smmu_hdl;
  1397. num_hdl = 1;
  1398. idx = cam_mem_get_slot();
  1399. if (idx < 0) {
  1400. CAM_ERR(CAM_MEM, "Failed in getting mem slot, idx=%d", idx);
  1401. rc = -ENOMEM;
  1402. goto slot_fail;
  1403. }
  1404. mutex_lock(&tbl.bufq[idx].q_lock);
  1405. mem_handle = GET_MEM_HANDLE(idx, ion_fd);
  1406. tbl.bufq[idx].fd = -1;
  1407. tbl.bufq[idx].dma_buf = buf;
  1408. tbl.bufq[idx].flags = inp->flags;
  1409. tbl.bufq[idx].buf_handle = mem_handle;
  1410. tbl.bufq[idx].kmdvaddr = kvaddr;
  1411. tbl.bufq[idx].vaddr = iova;
  1412. tbl.bufq[idx].len = request_len;
  1413. tbl.bufq[idx].num_hdl = num_hdl;
  1414. memcpy(tbl.bufq[idx].hdls, &smmu_hdl,
  1415. sizeof(int32_t));
  1416. tbl.bufq[idx].is_imported = false;
  1417. mutex_unlock(&tbl.bufq[idx].q_lock);
  1418. out->kva = kvaddr;
  1419. out->iova = (uint32_t)iova;
  1420. out->smmu_hdl = smmu_hdl;
  1421. out->mem_handle = mem_handle;
  1422. out->len = request_len;
  1423. out->region = region;
  1424. return rc;
  1425. slot_fail:
  1426. cam_smmu_release_buf_region(region, smmu_hdl);
  1427. smmu_fail:
  1428. if (region == CAM_SMMU_REGION_FWUNCACHED)
  1429. cam_mem_util_unmap_cpu_va(buf, kvaddr);
  1430. kmap_fail:
  1431. dma_buf_put(buf);
  1432. ion_fail:
  1433. return rc;
  1434. }
  1435. EXPORT_SYMBOL(cam_mem_mgr_reserve_memory_region);
  1436. int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp)
  1437. {
  1438. int32_t idx;
  1439. int rc;
  1440. int32_t smmu_hdl;
  1441. if (!atomic_read(&cam_mem_mgr_state)) {
  1442. CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized");
  1443. return -EINVAL;
  1444. }
  1445. if (!inp) {
  1446. CAM_ERR(CAM_MEM, "Invalid argument");
  1447. return -EINVAL;
  1448. }
  1449. if ((inp->region != CAM_SMMU_REGION_SECHEAP) &&
  1450. (inp->region != CAM_SMMU_REGION_FWUNCACHED)) {
  1451. CAM_ERR(CAM_MEM, "Only secondary heap supported");
  1452. return -EINVAL;
  1453. }
  1454. idx = CAM_MEM_MGR_GET_HDL_IDX(inp->mem_handle);
  1455. if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) {
  1456. CAM_ERR(CAM_MEM, "Incorrect index extracted from mem handle");
  1457. return -EINVAL;
  1458. }
  1459. if (!tbl.bufq[idx].active) {
  1460. if (tbl.bufq[idx].vaddr == 0) {
  1461. CAM_ERR(CAM_MEM, "buffer is released already");
  1462. return 0;
  1463. }
  1464. CAM_ERR(CAM_MEM, "Released buffer state should be active");
  1465. return -EINVAL;
  1466. }
  1467. if (tbl.bufq[idx].buf_handle != inp->mem_handle) {
  1468. CAM_ERR(CAM_MEM,
  1469. "Released buf handle not matching within table");
  1470. return -EINVAL;
  1471. }
  1472. if (tbl.bufq[idx].num_hdl != 1) {
  1473. CAM_ERR(CAM_MEM,
  1474. "Sec heap region should have only one smmu hdl");
  1475. return -ENODEV;
  1476. }
  1477. memcpy(&smmu_hdl, tbl.bufq[idx].hdls,
  1478. sizeof(int32_t));
  1479. if (inp->smmu_hdl != smmu_hdl) {
  1480. CAM_ERR(CAM_MEM,
  1481. "Passed SMMU handle doesn't match with internal hdl");
  1482. return -ENODEV;
  1483. }
  1484. rc = cam_smmu_release_buf_region(inp->region, inp->smmu_hdl);
  1485. if (rc) {
  1486. CAM_ERR(CAM_MEM,
  1487. "Sec heap region release failed");
  1488. return -ENODEV;
  1489. }
  1490. CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle);
  1491. rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL);
  1492. if (rc)
  1493. CAM_ERR(CAM_MEM, "unmapping secondary heap failed");
  1494. return rc;
  1495. }
  1496. EXPORT_SYMBOL(cam_mem_mgr_free_memory_region);