With Change-Id: I7f38b3dc6975fcc208ad85e913564dfef5cc1cb7,
Tx register write is permitted after hif bus resume during runtime pm
resume, don't wait WMI_WOW_WAKEUP_HOST_EVENTID.
In F/W, there is an race condition when exit from WOW, both
WAL_TX_TID_TQM and WAL_TX_TID_TRANSITION_TO_TQM_ONGOING are not set yet,
data frame is received from host, assert will hapen.
To fix it, host tx register write shouldn't be permitted to update hp
until receive the WMI_WOW_WAKEUP_HOST_EVENTID.
Change-Id: Ic397652a9a0c4bc81667aed11805b2ce8070ee8d
CRs-Fixed: 2858115
0f3778b424