hal_rh_generic_api.h 73 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_RH_GENERIC_API_H_
  20. #define _HAL_RH_GENERIC_API_H_
  21. #include "hal_tx.h"
  22. #include "hal_rh_tx.h"
  23. #include "hal_rh_rx.h"
  24. #include <htt.h>
  25. #ifdef QCA_UNDECODED_METADATA_SUPPORT
  26. static inline void
  27. hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
  28. struct hal_rx_ppdu_info *ppdu_info){
  29. switch (hal->target_type) {
  30. case TARGET_TYPE_QCN9000:
  31. ppdu_info->rx_status.phyrx_abort =
  32. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2,
  33. PHYRX_ABORT_REQUEST_INFO_VALID);
  34. ppdu_info->rx_status.phyrx_abort_reason =
  35. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11,
  36. PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON);
  37. break;
  38. default:
  39. break;
  40. }
  41. }
  42. static inline void
  43. hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
  44. uint8_t *ht_sig_info)
  45. {
  46. ppdu_info->rx_status.ht_length =
  47. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH);
  48. ppdu_info->rx_status.smoothing =
  49. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING);
  50. ppdu_info->rx_status.not_sounding =
  51. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING);
  52. ppdu_info->rx_status.aggregation =
  53. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION);
  54. ppdu_info->rx_status.ht_stbc =
  55. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC);
  56. ppdu_info->rx_status.ht_crc =
  57. HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC);
  58. }
  59. static inline void
  60. hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  61. uint8_t *l_sig_a_info)
  62. {
  63. ppdu_info->rx_status.l_sig_length =
  64. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH);
  65. ppdu_info->rx_status.l_sig_a_parity =
  66. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY);
  67. ppdu_info->rx_status.l_sig_a_pkt_type =
  68. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE);
  69. ppdu_info->rx_status.l_sig_a_implicit_sounding =
  70. HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0,
  71. CAPTURED_IMPLICIT_SOUNDING);
  72. }
  73. static inline void
  74. hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  75. uint8_t *vht_sig_a_info)
  76. {
  77. ppdu_info->rx_status.vht_no_txop_ps =
  78. HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
  79. TXOP_PS_NOT_ALLOWED);
  80. ppdu_info->rx_status.vht_crc =
  81. HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC);
  82. }
  83. static inline void
  84. hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
  85. uint8_t *he_sig_a_su_info) {
  86. ppdu_info->rx_status.he_crc =
  87. HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC);
  88. }
  89. static inline void
  90. hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
  91. uint8_t *he_sig_a_mu_dl_info) {
  92. ppdu_info->rx_status.he_crc =
  93. HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC);
  94. }
  95. #else
  96. static inline void
  97. hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
  98. struct hal_rx_ppdu_info *ppdu_info)
  99. {
  100. }
  101. static inline void
  102. hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
  103. uint8_t *ht_sig_info)
  104. {
  105. }
  106. static inline void
  107. hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  108. uint8_t *l_sig_a_info)
  109. {
  110. }
  111. static inline void
  112. hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
  113. uint8_t *vht_sig_a_info)
  114. {
  115. }
  116. static inline void
  117. hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
  118. uint8_t *he_sig_a_su_info)
  119. {
  120. }
  121. static inline void
  122. hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
  123. uint8_t *he_sig_a_mu_dl_info)
  124. {
  125. }
  126. #endif /* QCA_UNDECODED_METADATA_SUPPORT */
  127. /**
  128. * hal_tx_desc_set_buf_addr_generic_rh - Fill Buffer Address information
  129. * in Tx Descriptor
  130. * @desc: Handle to Tx Descriptor
  131. * @paddr: Physical Address
  132. * @rbm_id: Return Buffer Manager ID
  133. * @desc_id: Descriptor ID
  134. * @type: 0 - Address points to a MSDU buffer
  135. * 1 - Address points to MSDU extension descriptor
  136. *
  137. * Return: void
  138. */
  139. static inline void
  140. hal_tx_desc_set_buf_addr_generic_rh(void *desc, dma_addr_t paddr,
  141. uint8_t rbm_id, uint32_t desc_id,
  142. uint8_t type)
  143. {
  144. /* Set buffer_addr_info.buffer_addr_31_0 */
  145. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0,
  146. BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
  147. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
  148. /* Set buffer_addr_info.buffer_addr_39_32 */
  149. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  150. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  151. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
  152. (((uint64_t)paddr) >> 32));
  153. /* Set buffer_addr_info.return_buffer_manager = rbm id */
  154. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  155. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  156. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1,
  157. RETURN_BUFFER_MANAGER, rbm_id);
  158. /* Set buffer_addr_info.sw_buffer_cookie = desc_id */
  159. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
  160. BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
  161. HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
  162. desc_id);
  163. /* Set Buffer or Ext Descriptor Type */
  164. HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2,
  165. BUF_OR_EXT_DESC_TYPE) |=
  166. HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
  167. }
  168. #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
  169. /**
  170. * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
  171. * @tlv_tag: Taf of the TLVs
  172. * @rx_tlv: the pointer to the TLVs
  173. * @ppdu_info: pointer to ppdu_info
  174. *
  175. * Return: true if the tlv is handled, false if not
  176. */
  177. static inline bool
  178. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  179. struct hal_rx_ppdu_info *ppdu_info)
  180. {
  181. uint32_t value;
  182. switch (tlv_tag) {
  183. case WIFIPHYRX_HE_SIG_A_MU_UL_E:
  184. {
  185. uint8_t *he_sig_a_mu_ul_info =
  186. (uint8_t *)rx_tlv +
  187. HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0,
  188. HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS);
  189. ppdu_info->rx_status.he_flags = 1;
  190. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
  191. FORMAT_INDICATION);
  192. if (value == 0) {
  193. ppdu_info->rx_status.he_data1 =
  194. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  195. } else {
  196. ppdu_info->rx_status.he_data1 =
  197. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  198. }
  199. /* data1 */
  200. ppdu_info->rx_status.he_data1 |=
  201. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  202. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  203. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
  204. /* data2 */
  205. ppdu_info->rx_status.he_data2 |=
  206. QDF_MON_STATUS_TXOP_KNOWN;
  207. /*data3*/
  208. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  209. HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID);
  210. ppdu_info->rx_status.he_data3 = value;
  211. /* 1 for UL and 0 for DL */
  212. value = 1;
  213. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  214. ppdu_info->rx_status.he_data3 |= value;
  215. /*data4*/
  216. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
  217. SPATIAL_REUSE);
  218. ppdu_info->rx_status.he_data4 = value;
  219. /*data5*/
  220. value = HAL_RX_GET(he_sig_a_mu_ul_info,
  221. HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW);
  222. ppdu_info->rx_status.he_data5 = value;
  223. ppdu_info->rx_status.bw = value;
  224. /*data6*/
  225. value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1,
  226. TXOP_DURATION);
  227. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  228. ppdu_info->rx_status.he_data6 |= value;
  229. return true;
  230. }
  231. default:
  232. return false;
  233. }
  234. }
  235. #else
  236. static inline bool
  237. hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
  238. struct hal_rx_ppdu_info *ppdu_info)
  239. {
  240. return false;
  241. }
  242. #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */
  243. #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \
  244. defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
  245. static inline void
  246. hal_rx_handle_mu_ul_info(void *rx_tlv,
  247. struct mon_rx_user_status *mon_rx_user_status)
  248. {
  249. mon_rx_user_status->mu_ul_user_v0_word0 =
  250. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11,
  251. SW_RESPONSE_REFERENCE_PTR);
  252. mon_rx_user_status->mu_ul_user_v0_word1 =
  253. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22,
  254. SW_RESPONSE_REFERENCE_PTR_EXT);
  255. }
  256. static inline void
  257. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  258. struct mon_rx_user_status *mon_rx_user_status)
  259. {
  260. uint32_t mpdu_ok_byte_count;
  261. uint32_t mpdu_err_byte_count;
  262. mpdu_ok_byte_count = HAL_RX_GET(rx_tlv,
  263. RX_PPDU_END_USER_STATS_17,
  264. MPDU_OK_BYTE_COUNT);
  265. mpdu_err_byte_count = HAL_RX_GET(rx_tlv,
  266. RX_PPDU_END_USER_STATS_19,
  267. MPDU_ERR_BYTE_COUNT);
  268. mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count;
  269. mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count;
  270. }
  271. #else
  272. static inline void
  273. hal_rx_handle_mu_ul_info(void *rx_tlv,
  274. struct mon_rx_user_status *mon_rx_user_status)
  275. {
  276. }
  277. static inline void
  278. hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
  279. struct mon_rx_user_status *mon_rx_user_status)
  280. {
  281. struct hal_rx_ppdu_info *ppdu_info =
  282. (struct hal_rx_ppdu_info *)ppduinfo;
  283. /* HKV1: doesn't support mpdu byte count */
  284. mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len;
  285. mon_rx_user_status->mpdu_err_byte_count = 0;
  286. }
  287. #endif
  288. static inline void
  289. hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id,
  290. struct mon_rx_user_status *mon_rx_user_status)
  291. {
  292. struct mon_rx_info *mon_rx_info;
  293. struct mon_rx_user_info *mon_rx_user_info;
  294. struct hal_rx_ppdu_info *ppdu_info =
  295. (struct hal_rx_ppdu_info *)ppduinfo;
  296. mon_rx_info = &ppdu_info->rx_info;
  297. mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
  298. mon_rx_user_info->qos_control_info_valid =
  299. mon_rx_info->qos_control_info_valid;
  300. mon_rx_user_info->qos_control = mon_rx_info->qos_control;
  301. mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
  302. mon_rx_user_status->tid = ppdu_info->rx_status.tid;
  303. mon_rx_user_status->tcp_msdu_count =
  304. ppdu_info->rx_status.tcp_msdu_count;
  305. mon_rx_user_status->udp_msdu_count =
  306. ppdu_info->rx_status.udp_msdu_count;
  307. mon_rx_user_status->other_msdu_count =
  308. ppdu_info->rx_status.other_msdu_count;
  309. mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
  310. mon_rx_user_status->frame_control_info_valid =
  311. ppdu_info->rx_status.frame_control_info_valid;
  312. mon_rx_user_status->data_sequence_control_info_valid =
  313. ppdu_info->rx_status.data_sequence_control_info_valid;
  314. mon_rx_user_status->first_data_seq_ctrl =
  315. ppdu_info->rx_status.first_data_seq_ctrl;
  316. mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
  317. mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
  318. mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
  319. mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
  320. mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
  321. mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
  322. mon_rx_user_status->mpdu_cnt_fcs_ok =
  323. ppdu_info->com_info.mpdu_cnt_fcs_ok;
  324. mon_rx_user_status->mpdu_cnt_fcs_err =
  325. ppdu_info->com_info.mpdu_cnt_fcs_err;
  326. qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
  327. &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
  328. HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
  329. sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
  330. hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status);
  331. }
  332. #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \
  333. ppdu_info, rssi_info_tlv) \
  334. { \
  335. ppdu_info->rx_status.rssi_chain[chain][0] = \
  336. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  337. RSSI_PRI20_CHAIN##chain); \
  338. ppdu_info->rx_status.rssi_chain[chain][1] = \
  339. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  340. RSSI_EXT20_CHAIN##chain); \
  341. ppdu_info->rx_status.rssi_chain[chain][2] = \
  342. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  343. RSSI_EXT40_LOW20_CHAIN##chain); \
  344. ppdu_info->rx_status.rssi_chain[chain][3] = \
  345. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
  346. RSSI_EXT40_HIGH20_CHAIN##chain); \
  347. ppdu_info->rx_status.rssi_chain[chain][4] = \
  348. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  349. RSSI_EXT80_LOW20_CHAIN##chain); \
  350. ppdu_info->rx_status.rssi_chain[chain][5] = \
  351. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  352. RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \
  353. ppdu_info->rx_status.rssi_chain[chain][6] = \
  354. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  355. RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \
  356. ppdu_info->rx_status.rssi_chain[chain][7] = \
  357. HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
  358. RSSI_EXT80_HIGH20_CHAIN##chain); \
  359. } \
  360. #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
  361. {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \
  362. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \
  363. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \
  364. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \
  365. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \
  366. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \
  367. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \
  368. HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \
  369. static inline uint32_t
  370. hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
  371. uint8_t *rssi_info_tlv)
  372. {
  373. HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
  374. return 0;
  375. }
  376. #ifdef WLAN_TX_PKT_CAPTURE_ENH
  377. static inline void
  378. hal_get_qos_control(void *rx_tlv,
  379. struct hal_rx_ppdu_info *ppdu_info)
  380. {
  381. ppdu_info->rx_info.qos_control_info_valid =
  382. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  383. QOS_CONTROL_INFO_VALID);
  384. if (ppdu_info->rx_info.qos_control_info_valid)
  385. ppdu_info->rx_info.qos_control =
  386. HAL_RX_GET(rx_tlv,
  387. RX_PPDU_END_USER_STATS_5,
  388. QOS_CONTROL_FIELD);
  389. }
  390. static inline void
  391. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  392. struct hal_rx_ppdu_info *ppdu_info)
  393. {
  394. if ((ppdu_info->sw_frame_group_id
  395. == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
  396. (ppdu_info->sw_frame_group_id ==
  397. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
  398. ppdu_info->rx_info.mac_addr1_valid =
  399. HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start);
  400. *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
  401. HAL_RX_GET(rx_mpdu_start,
  402. RX_MPDU_INFO_15,
  403. MAC_ADDR_AD1_31_0);
  404. if (ppdu_info->sw_frame_group_id ==
  405. HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
  406. *(uint16_t *)&ppdu_info->rx_info.mac_addr1[4] =
  407. HAL_RX_GET(rx_mpdu_start,
  408. RX_MPDU_INFO_16,
  409. MAC_ADDR_AD1_47_32);
  410. }
  411. }
  412. }
  413. #else
  414. static inline void
  415. hal_get_qos_control(void *rx_tlv,
  416. struct hal_rx_ppdu_info *ppdu_info)
  417. {
  418. }
  419. static inline void
  420. hal_get_mac_addr1(uint8_t *rx_mpdu_start,
  421. struct hal_rx_ppdu_info *ppdu_info)
  422. {
  423. }
  424. #endif
  425. #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS
  426. static inline void
  427. hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
  428. struct hal_rx_ppdu_info *ppdu_info)
  429. {
  430. uint16_t frame_ctrl;
  431. uint8_t fc_type;
  432. if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) {
  433. frame_ctrl = HAL_RX_GET(rx_mpdu_start,
  434. RX_MPDU_INFO_14,
  435. MPDU_FRAME_CONTROL_FIELD);
  436. fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl);
  437. if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT)
  438. ppdu_info->frm_type_info.rx_mgmt_cnt++;
  439. else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL)
  440. ppdu_info->frm_type_info.rx_ctrl_cnt++;
  441. else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA)
  442. ppdu_info->frm_type_info.rx_data_cnt++;
  443. }
  444. }
  445. #else
  446. static inline void
  447. hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
  448. struct hal_rx_ppdu_info *ppdu_info)
  449. {
  450. }
  451. #endif
  452. /**
  453. * hal_rx_status_get_tlv_info_generic_rh() - process receive info TLV
  454. * @rx_tlv_hdr: pointer to TLV header
  455. * @ppduinfo: pointer to ppdu_info
  456. * @hal_soc_hdl: HAL SOC handle
  457. * @nbuf: pkt buffer
  458. *
  459. * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
  460. */
  461. static inline uint32_t
  462. hal_rx_status_get_tlv_info_generic_rh(void *rx_tlv_hdr, void *ppduinfo,
  463. hal_soc_handle_t hal_soc_hdl,
  464. qdf_nbuf_t nbuf)
  465. {
  466. struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
  467. uint32_t tlv_tag, user_id, tlv_len, value;
  468. uint8_t group_id = 0;
  469. uint8_t he_dcm = 0;
  470. uint8_t he_stbc = 0;
  471. uint16_t he_gi = 0;
  472. uint16_t he_ltf = 0;
  473. void *rx_tlv;
  474. bool unhandled = false;
  475. struct mon_rx_user_status *mon_rx_user_status;
  476. struct hal_rx_ppdu_info *ppdu_info =
  477. (struct hal_rx_ppdu_info *)ppduinfo;
  478. tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
  479. user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
  480. tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
  481. rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
  482. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  483. rx_tlv, tlv_len);
  484. switch (tlv_tag) {
  485. case WIFIRX_PPDU_START_E:
  486. {
  487. if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
  488. HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID)))
  489. hal_err("Matching ppdu_id(%u) detected",
  490. ppdu_info->com_info.last_ppdu_id);
  491. /* Reset ppdu_info before processing the ppdu */
  492. qdf_mem_zero(ppdu_info,
  493. sizeof(struct hal_rx_ppdu_info));
  494. ppdu_info->com_info.last_ppdu_id =
  495. ppdu_info->com_info.ppdu_id =
  496. HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
  497. PHY_PPDU_ID);
  498. /* channel number is set in PHY meta data */
  499. ppdu_info->rx_status.chan_num =
  500. (HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  501. SW_PHY_META_DATA) & 0x0000FFFF);
  502. ppdu_info->rx_status.chan_freq =
  503. (HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
  504. SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
  505. if (ppdu_info->rx_status.chan_num) {
  506. ppdu_info->rx_status.chan_freq =
  507. hal_rx_radiotap_num_to_freq(
  508. ppdu_info->rx_status.chan_num,
  509. ppdu_info->rx_status.chan_freq);
  510. }
  511. ppdu_info->com_info.ppdu_timestamp =
  512. HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
  513. PPDU_START_TIMESTAMP);
  514. ppdu_info->rx_status.ppdu_timestamp =
  515. ppdu_info->com_info.ppdu_timestamp;
  516. ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
  517. break;
  518. }
  519. case WIFIRX_PPDU_START_USER_INFO_E:
  520. break;
  521. case WIFIRX_PPDU_END_E:
  522. dp_nofl_debug("[%s][%d] ppdu_end_e len=%d",
  523. __func__, __LINE__, tlv_len);
  524. /* This is followed by sub-TLVs of PPDU_END */
  525. ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
  526. break;
  527. case WIFIPHYRX_PKT_END_E:
  528. hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
  529. break;
  530. case WIFIRXPCU_PPDU_END_INFO_E:
  531. ppdu_info->rx_status.rx_antenna =
  532. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA);
  533. ppdu_info->rx_status.tsft =
  534. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
  535. WB_TIMESTAMP_UPPER_32);
  536. ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
  537. HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
  538. WB_TIMESTAMP_LOWER_32);
  539. ppdu_info->rx_status.duration =
  540. HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
  541. RX_PPDU_DURATION);
  542. hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
  543. hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info);
  544. break;
  545. /*
  546. * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
  547. * for MU, based on num users we see this tlv that many times.
  548. */
  549. case WIFIRX_PPDU_END_USER_STATS_E:
  550. {
  551. unsigned long tid = 0;
  552. uint16_t seq = 0;
  553. ppdu_info->rx_status.ast_index =
  554. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
  555. AST_INDEX);
  556. tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
  557. RECEIVED_QOS_DATA_TID_BITMAP);
  558. ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
  559. sizeof(tid) * 8);
  560. if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
  561. ppdu_info->rx_status.tid = HAL_TID_INVALID;
  562. ppdu_info->rx_status.tcp_msdu_count =
  563. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  564. TCP_MSDU_COUNT) +
  565. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  566. TCP_ACK_MSDU_COUNT);
  567. ppdu_info->rx_status.udp_msdu_count =
  568. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
  569. UDP_MSDU_COUNT);
  570. ppdu_info->rx_status.other_msdu_count =
  571. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
  572. OTHER_MSDU_COUNT);
  573. if (ppdu_info->sw_frame_group_id
  574. != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  575. ppdu_info->rx_status.frame_control_info_valid =
  576. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  577. FRAME_CONTROL_INFO_VALID);
  578. if (ppdu_info->rx_status.frame_control_info_valid)
  579. ppdu_info->rx_status.frame_control =
  580. HAL_RX_GET(rx_tlv,
  581. RX_PPDU_END_USER_STATS_4,
  582. FRAME_CONTROL_FIELD);
  583. hal_get_qos_control(rx_tlv, ppdu_info);
  584. }
  585. ppdu_info->rx_status.data_sequence_control_info_valid =
  586. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  587. DATA_SEQUENCE_CONTROL_INFO_VALID);
  588. seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
  589. FIRST_DATA_SEQ_CTRL);
  590. if (ppdu_info->rx_status.data_sequence_control_info_valid)
  591. ppdu_info->rx_status.first_data_seq_ctrl = seq;
  592. ppdu_info->rx_status.preamble_type =
  593. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  594. HT_CONTROL_FIELD_PKT_TYPE);
  595. switch (ppdu_info->rx_status.preamble_type) {
  596. case HAL_RX_PKT_TYPE_11N:
  597. ppdu_info->rx_status.ht_flags = 1;
  598. ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
  599. break;
  600. case HAL_RX_PKT_TYPE_11AC:
  601. ppdu_info->rx_status.vht_flags = 1;
  602. break;
  603. case HAL_RX_PKT_TYPE_11AX:
  604. ppdu_info->rx_status.he_flags = 1;
  605. break;
  606. default:
  607. break;
  608. }
  609. ppdu_info->com_info.mpdu_cnt_fcs_ok =
  610. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
  611. MPDU_CNT_FCS_OK);
  612. ppdu_info->com_info.mpdu_cnt_fcs_err =
  613. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
  614. MPDU_CNT_FCS_ERR);
  615. if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
  616. ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
  617. ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
  618. else
  619. ppdu_info->rx_status.rs_flags &=
  620. (~IEEE80211_AMPDU_FLAG);
  621. ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
  622. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7,
  623. FCS_OK_BITMAP_31_0);
  624. ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
  625. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8,
  626. FCS_OK_BITMAP_63_32);
  627. if (user_id < HAL_MAX_UL_MU_USERS) {
  628. mon_rx_user_status =
  629. &ppdu_info->rx_user_status[user_id];
  630. hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status);
  631. ppdu_info->com_info.num_users++;
  632. hal_rx_populate_mu_user_info(rx_tlv, ppdu_info,
  633. user_id,
  634. mon_rx_user_status);
  635. }
  636. break;
  637. }
  638. case WIFIRX_PPDU_END_USER_STATS_EXT_E:
  639. ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
  640. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1,
  641. FCS_OK_BITMAP_95_64);
  642. ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
  643. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2,
  644. FCS_OK_BITMAP_127_96);
  645. ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
  646. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3,
  647. FCS_OK_BITMAP_159_128);
  648. ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
  649. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4,
  650. FCS_OK_BITMAP_191_160);
  651. ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
  652. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5,
  653. FCS_OK_BITMAP_223_192);
  654. ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
  655. HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6,
  656. FCS_OK_BITMAP_255_224);
  657. break;
  658. case WIFIRX_PPDU_END_STATUS_DONE_E:
  659. return HAL_TLV_STATUS_PPDU_DONE;
  660. case WIFIDUMMY_E:
  661. return HAL_TLV_STATUS_BUF_DONE;
  662. case WIFIPHYRX_HT_SIG_E:
  663. {
  664. uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
  665. HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
  666. HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
  667. value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
  668. FEC_CODING);
  669. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  670. 1 : 0;
  671. ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
  672. HT_SIG_INFO_0, MCS);
  673. ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
  674. ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
  675. HT_SIG_INFO_0, CBW);
  676. ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
  677. HT_SIG_INFO_1, SHORT_GI);
  678. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  679. ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
  680. HT_SIG_SU_NSS_SHIFT) + 1;
  681. ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
  682. hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info);
  683. break;
  684. }
  685. case WIFIPHYRX_L_SIG_B_E:
  686. {
  687. uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
  688. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
  689. L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
  690. value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
  691. ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
  692. switch (value) {
  693. case 1:
  694. ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
  695. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  696. break;
  697. case 2:
  698. ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
  699. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  700. break;
  701. case 3:
  702. ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
  703. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  704. break;
  705. case 4:
  706. ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
  707. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  708. break;
  709. case 5:
  710. ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
  711. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  712. break;
  713. case 6:
  714. ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
  715. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  716. break;
  717. case 7:
  718. ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
  719. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  720. break;
  721. default:
  722. break;
  723. }
  724. ppdu_info->rx_status.cck_flag = 1;
  725. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  726. break;
  727. }
  728. case WIFIPHYRX_L_SIG_A_E:
  729. {
  730. uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
  731. HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
  732. L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
  733. value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
  734. ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
  735. switch (value) {
  736. case 8:
  737. ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
  738. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
  739. break;
  740. case 9:
  741. ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
  742. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
  743. break;
  744. case 10:
  745. ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
  746. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
  747. break;
  748. case 11:
  749. ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
  750. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
  751. break;
  752. case 12:
  753. ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
  754. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
  755. break;
  756. case 13:
  757. ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
  758. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
  759. break;
  760. case 14:
  761. ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
  762. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
  763. break;
  764. case 15:
  765. ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
  766. ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
  767. break;
  768. default:
  769. break;
  770. }
  771. ppdu_info->rx_status.ofdm_flag = 1;
  772. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  773. hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info);
  774. break;
  775. }
  776. case WIFIPHYRX_VHT_SIG_A_E:
  777. {
  778. uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
  779. HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
  780. VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
  781. value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
  782. SU_MU_CODING);
  783. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  784. 1 : 0;
  785. group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
  786. GROUP_ID);
  787. ppdu_info->rx_status.vht_flag_values5 = group_id;
  788. ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
  789. VHT_SIG_A_INFO_1, MCS);
  790. ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
  791. VHT_SIG_A_INFO_1, GI_SETTING);
  792. switch (hal->target_type) {
  793. case TARGET_TYPE_QCA8074:
  794. case TARGET_TYPE_QCA8074V2:
  795. case TARGET_TYPE_QCA6018:
  796. case TARGET_TYPE_QCA5018:
  797. case TARGET_TYPE_QCN9000:
  798. case TARGET_TYPE_QCN6122:
  799. #ifdef QCA_WIFI_QCA6390
  800. case TARGET_TYPE_QCA6390:
  801. #endif
  802. case TARGET_TYPE_QCA6490:
  803. ppdu_info->rx_status.is_stbc =
  804. HAL_RX_GET(vht_sig_a_info,
  805. VHT_SIG_A_INFO_0, STBC);
  806. value = HAL_RX_GET(vht_sig_a_info,
  807. VHT_SIG_A_INFO_0, N_STS);
  808. value = value & VHT_SIG_SU_NSS_MASK;
  809. if (ppdu_info->rx_status.is_stbc && (value > 0))
  810. value = ((value + 1) >> 1) - 1;
  811. ppdu_info->rx_status.nss =
  812. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  813. break;
  814. case TARGET_TYPE_QCA6290:
  815. #if !defined(QCA_WIFI_QCA6290_11AX)
  816. ppdu_info->rx_status.is_stbc =
  817. HAL_RX_GET(vht_sig_a_info,
  818. VHT_SIG_A_INFO_0, STBC);
  819. value = HAL_RX_GET(vht_sig_a_info,
  820. VHT_SIG_A_INFO_0, N_STS);
  821. value = value & VHT_SIG_SU_NSS_MASK;
  822. if (ppdu_info->rx_status.is_stbc && (value > 0))
  823. value = ((value + 1) >> 1) - 1;
  824. ppdu_info->rx_status.nss =
  825. ((value & VHT_SIG_SU_NSS_MASK) + 1);
  826. #else
  827. ppdu_info->rx_status.nss = 0;
  828. #endif
  829. break;
  830. case TARGET_TYPE_QCA6750:
  831. ppdu_info->rx_status.nss = 0;
  832. break;
  833. default:
  834. break;
  835. }
  836. ppdu_info->rx_status.vht_flag_values3[0] =
  837. (((ppdu_info->rx_status.mcs) << 4)
  838. | ppdu_info->rx_status.nss);
  839. ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
  840. VHT_SIG_A_INFO_0, BANDWIDTH);
  841. ppdu_info->rx_status.vht_flag_values2 =
  842. ppdu_info->rx_status.bw;
  843. ppdu_info->rx_status.vht_flag_values4 =
  844. HAL_RX_GET(vht_sig_a_info,
  845. VHT_SIG_A_INFO_1, SU_MU_CODING);
  846. ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
  847. VHT_SIG_A_INFO_1, BEAMFORMED);
  848. if (group_id == 0 || group_id == 63)
  849. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  850. else
  851. ppdu_info->rx_status.reception_type =
  852. HAL_RX_TYPE_MU_MIMO;
  853. hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info);
  854. break;
  855. }
  856. case WIFIPHYRX_HE_SIG_A_SU_E:
  857. {
  858. uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
  859. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
  860. HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
  861. ppdu_info->rx_status.he_flags = 1;
  862. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  863. FORMAT_INDICATION);
  864. if (value == 0) {
  865. ppdu_info->rx_status.he_data1 =
  866. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  867. } else {
  868. ppdu_info->rx_status.he_data1 =
  869. QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
  870. }
  871. /* data1 */
  872. ppdu_info->rx_status.he_data1 |=
  873. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  874. QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
  875. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  876. QDF_MON_STATUS_HE_MCS_KNOWN |
  877. QDF_MON_STATUS_HE_DCM_KNOWN |
  878. QDF_MON_STATUS_HE_CODING_KNOWN |
  879. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  880. QDF_MON_STATUS_HE_STBC_KNOWN |
  881. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  882. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  883. /* data2 */
  884. ppdu_info->rx_status.he_data2 =
  885. QDF_MON_STATUS_HE_GI_KNOWN;
  886. ppdu_info->rx_status.he_data2 |=
  887. QDF_MON_STATUS_TXBF_KNOWN |
  888. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  889. QDF_MON_STATUS_TXOP_KNOWN |
  890. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  891. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  892. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  893. /* data3 */
  894. value = HAL_RX_GET(he_sig_a_su_info,
  895. HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
  896. ppdu_info->rx_status.he_data3 = value;
  897. value = HAL_RX_GET(he_sig_a_su_info,
  898. HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
  899. value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
  900. ppdu_info->rx_status.he_data3 |= value;
  901. value = HAL_RX_GET(he_sig_a_su_info,
  902. HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
  903. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  904. ppdu_info->rx_status.he_data3 |= value;
  905. value = HAL_RX_GET(he_sig_a_su_info,
  906. HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
  907. ppdu_info->rx_status.mcs = value;
  908. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  909. ppdu_info->rx_status.he_data3 |= value;
  910. value = HAL_RX_GET(he_sig_a_su_info,
  911. HE_SIG_A_SU_INFO_0, DCM);
  912. he_dcm = value;
  913. value = value << QDF_MON_STATUS_DCM_SHIFT;
  914. ppdu_info->rx_status.he_data3 |= value;
  915. value = HAL_RX_GET(he_sig_a_su_info,
  916. HE_SIG_A_SU_INFO_1, CODING);
  917. ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
  918. 1 : 0;
  919. value = value << QDF_MON_STATUS_CODING_SHIFT;
  920. ppdu_info->rx_status.he_data3 |= value;
  921. value = HAL_RX_GET(he_sig_a_su_info,
  922. HE_SIG_A_SU_INFO_1,
  923. LDPC_EXTRA_SYMBOL);
  924. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  925. ppdu_info->rx_status.he_data3 |= value;
  926. value = HAL_RX_GET(he_sig_a_su_info,
  927. HE_SIG_A_SU_INFO_1, STBC);
  928. he_stbc = value;
  929. value = value << QDF_MON_STATUS_STBC_SHIFT;
  930. ppdu_info->rx_status.he_data3 |= value;
  931. /* data4 */
  932. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
  933. SPATIAL_REUSE);
  934. ppdu_info->rx_status.he_data4 = value;
  935. /* data5 */
  936. value = HAL_RX_GET(he_sig_a_su_info,
  937. HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
  938. ppdu_info->rx_status.he_data5 = value;
  939. ppdu_info->rx_status.bw = value;
  940. value = HAL_RX_GET(he_sig_a_su_info,
  941. HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
  942. switch (value) {
  943. case 0:
  944. he_gi = HE_GI_0_8;
  945. he_ltf = HE_LTF_1_X;
  946. break;
  947. case 1:
  948. he_gi = HE_GI_0_8;
  949. he_ltf = HE_LTF_2_X;
  950. break;
  951. case 2:
  952. he_gi = HE_GI_1_6;
  953. he_ltf = HE_LTF_2_X;
  954. break;
  955. case 3:
  956. if (he_dcm && he_stbc) {
  957. he_gi = HE_GI_0_8;
  958. he_ltf = HE_LTF_4_X;
  959. } else {
  960. he_gi = HE_GI_3_2;
  961. he_ltf = HE_LTF_4_X;
  962. }
  963. break;
  964. }
  965. ppdu_info->rx_status.sgi = he_gi;
  966. ppdu_info->rx_status.ltf_size = he_ltf;
  967. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  968. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  969. ppdu_info->rx_status.he_data5 |= value;
  970. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  971. ppdu_info->rx_status.he_data5 |= value;
  972. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  973. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  974. ppdu_info->rx_status.he_data5 |= value;
  975. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  976. PACKET_EXTENSION_A_FACTOR);
  977. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  978. ppdu_info->rx_status.he_data5 |= value;
  979. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
  980. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  981. ppdu_info->rx_status.he_data5 |= value;
  982. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  983. PACKET_EXTENSION_PE_DISAMBIGUITY);
  984. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  985. ppdu_info->rx_status.he_data5 |= value;
  986. /* data6 */
  987. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
  988. value++;
  989. ppdu_info->rx_status.nss = value;
  990. ppdu_info->rx_status.he_data6 = value;
  991. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  992. DOPPLER_INDICATION);
  993. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  994. ppdu_info->rx_status.he_data6 |= value;
  995. value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
  996. TXOP_DURATION);
  997. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  998. ppdu_info->rx_status.he_data6 |= value;
  999. ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
  1000. HE_SIG_A_SU_INFO_1, TXBF);
  1001. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
  1002. hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info);
  1003. break;
  1004. }
  1005. case WIFIPHYRX_HE_SIG_A_MU_DL_E:
  1006. {
  1007. uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
  1008. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
  1009. HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
  1010. ppdu_info->rx_status.he_mu_flags = 1;
  1011. /* HE Flags */
  1012. /*data1*/
  1013. ppdu_info->rx_status.he_data1 =
  1014. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1015. ppdu_info->rx_status.he_data1 |=
  1016. QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
  1017. QDF_MON_STATUS_HE_DL_UL_KNOWN |
  1018. QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
  1019. QDF_MON_STATUS_HE_STBC_KNOWN |
  1020. QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
  1021. QDF_MON_STATUS_HE_DOPPLER_KNOWN;
  1022. /* data2 */
  1023. ppdu_info->rx_status.he_data2 =
  1024. QDF_MON_STATUS_HE_GI_KNOWN;
  1025. ppdu_info->rx_status.he_data2 |=
  1026. QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
  1027. QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
  1028. QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
  1029. QDF_MON_STATUS_TXOP_KNOWN |
  1030. QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
  1031. /*data3*/
  1032. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1033. HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
  1034. ppdu_info->rx_status.he_data3 = value;
  1035. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1036. HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
  1037. value = value << QDF_MON_STATUS_DL_UL_SHIFT;
  1038. ppdu_info->rx_status.he_data3 |= value;
  1039. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1040. HE_SIG_A_MU_DL_INFO_1,
  1041. LDPC_EXTRA_SYMBOL);
  1042. value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
  1043. ppdu_info->rx_status.he_data3 |= value;
  1044. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1045. HE_SIG_A_MU_DL_INFO_1, STBC);
  1046. he_stbc = value;
  1047. value = value << QDF_MON_STATUS_STBC_SHIFT;
  1048. ppdu_info->rx_status.he_data3 |= value;
  1049. /*data4*/
  1050. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  1051. SPATIAL_REUSE);
  1052. ppdu_info->rx_status.he_data4 = value;
  1053. /*data5*/
  1054. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1055. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  1056. ppdu_info->rx_status.he_data5 = value;
  1057. ppdu_info->rx_status.bw = value;
  1058. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1059. HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
  1060. switch (value) {
  1061. case 0:
  1062. he_gi = HE_GI_0_8;
  1063. he_ltf = HE_LTF_4_X;
  1064. break;
  1065. case 1:
  1066. he_gi = HE_GI_0_8;
  1067. he_ltf = HE_LTF_2_X;
  1068. break;
  1069. case 2:
  1070. he_gi = HE_GI_1_6;
  1071. he_ltf = HE_LTF_2_X;
  1072. break;
  1073. case 3:
  1074. he_gi = HE_GI_3_2;
  1075. he_ltf = HE_LTF_4_X;
  1076. break;
  1077. }
  1078. ppdu_info->rx_status.sgi = he_gi;
  1079. ppdu_info->rx_status.ltf_size = he_ltf;
  1080. hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
  1081. value = he_gi << QDF_MON_STATUS_GI_SHIFT;
  1082. ppdu_info->rx_status.he_data5 |= value;
  1083. value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
  1084. ppdu_info->rx_status.he_data5 |= value;
  1085. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1086. HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS);
  1087. value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
  1088. ppdu_info->rx_status.he_data5 |= value;
  1089. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  1090. PACKET_EXTENSION_A_FACTOR);
  1091. value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
  1092. ppdu_info->rx_status.he_data5 |= value;
  1093. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  1094. PACKET_EXTENSION_PE_DISAMBIGUITY);
  1095. value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
  1096. ppdu_info->rx_status.he_data5 |= value;
  1097. /*data6*/
  1098. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
  1099. DOPPLER_INDICATION);
  1100. value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
  1101. ppdu_info->rx_status.he_data6 |= value;
  1102. value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
  1103. TXOP_DURATION);
  1104. value = value << QDF_MON_STATUS_TXOP_SHIFT;
  1105. ppdu_info->rx_status.he_data6 |= value;
  1106. /* HE-MU Flags */
  1107. /* HE-MU-flags1 */
  1108. ppdu_info->rx_status.he_flags1 =
  1109. QDF_MON_STATUS_SIG_B_MCS_KNOWN |
  1110. QDF_MON_STATUS_SIG_B_DCM_KNOWN |
  1111. QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
  1112. QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
  1113. QDF_MON_STATUS_RU_0_KNOWN;
  1114. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1115. HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
  1116. ppdu_info->rx_status.he_flags1 |= value;
  1117. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1118. HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
  1119. value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
  1120. ppdu_info->rx_status.he_flags1 |= value;
  1121. /* HE-MU-flags2 */
  1122. ppdu_info->rx_status.he_flags2 =
  1123. QDF_MON_STATUS_BW_KNOWN;
  1124. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1125. HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
  1126. ppdu_info->rx_status.he_flags2 |= value;
  1127. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1128. HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
  1129. value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
  1130. ppdu_info->rx_status.he_flags2 |= value;
  1131. value = HAL_RX_GET(he_sig_a_mu_dl_info,
  1132. HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
  1133. value = value - 1;
  1134. value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
  1135. ppdu_info->rx_status.he_flags2 |= value;
  1136. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1137. hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info,
  1138. he_sig_a_mu_dl_info);
  1139. break;
  1140. }
  1141. case WIFIPHYRX_HE_SIG_B1_MU_E:
  1142. {
  1143. uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
  1144. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
  1145. HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
  1146. ppdu_info->rx_status.he_sig_b_common_known |=
  1147. QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
  1148. /* TODO: Check on the availability of other fields in
  1149. * sig_b_common
  1150. */
  1151. value = HAL_RX_GET(he_sig_b1_mu_info,
  1152. HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
  1153. ppdu_info->rx_status.he_RU[0] = value;
  1154. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
  1155. break;
  1156. }
  1157. case WIFIPHYRX_HE_SIG_B2_MU_E:
  1158. {
  1159. uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
  1160. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
  1161. HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
  1162. /*
  1163. * Not all "HE" fields can be updated from
  1164. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1165. * to populate rest of the "HE" fields for MU scenarios.
  1166. */
  1167. /* HE-data1 */
  1168. ppdu_info->rx_status.he_data1 |=
  1169. QDF_MON_STATUS_HE_MCS_KNOWN |
  1170. QDF_MON_STATUS_HE_CODING_KNOWN;
  1171. /* HE-data2 */
  1172. /* HE-data3 */
  1173. value = HAL_RX_GET(he_sig_b2_mu_info,
  1174. HE_SIG_B2_MU_INFO_0, STA_MCS);
  1175. ppdu_info->rx_status.mcs = value;
  1176. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1177. ppdu_info->rx_status.he_data3 |= value;
  1178. value = HAL_RX_GET(he_sig_b2_mu_info,
  1179. HE_SIG_B2_MU_INFO_0, STA_CODING);
  1180. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1181. ppdu_info->rx_status.he_data3 |= value;
  1182. /* HE-data4 */
  1183. value = HAL_RX_GET(he_sig_b2_mu_info,
  1184. HE_SIG_B2_MU_INFO_0, STA_ID);
  1185. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1186. ppdu_info->rx_status.he_data4 |= value;
  1187. /* HE-data5 */
  1188. /* HE-data6 */
  1189. value = HAL_RX_GET(he_sig_b2_mu_info,
  1190. HE_SIG_B2_MU_INFO_0, NSTS);
  1191. /* value n indicates n+1 spatial streams */
  1192. value++;
  1193. ppdu_info->rx_status.nss = value;
  1194. ppdu_info->rx_status.he_data6 |= value;
  1195. break;
  1196. }
  1197. case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
  1198. {
  1199. uint8_t *he_sig_b2_ofdma_info =
  1200. (uint8_t *)rx_tlv +
  1201. HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
  1202. HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
  1203. /*
  1204. * Not all "HE" fields can be updated from
  1205. * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
  1206. * to populate rest of "HE" fields for MU OFDMA scenarios.
  1207. */
  1208. /* HE-data1 */
  1209. ppdu_info->rx_status.he_data1 |=
  1210. QDF_MON_STATUS_HE_MCS_KNOWN |
  1211. QDF_MON_STATUS_HE_DCM_KNOWN |
  1212. QDF_MON_STATUS_HE_CODING_KNOWN;
  1213. /* HE-data2 */
  1214. ppdu_info->rx_status.he_data2 |=
  1215. QDF_MON_STATUS_TXBF_KNOWN;
  1216. /* HE-data3 */
  1217. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1218. HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
  1219. ppdu_info->rx_status.mcs = value;
  1220. value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
  1221. ppdu_info->rx_status.he_data3 |= value;
  1222. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1223. HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
  1224. he_dcm = value;
  1225. value = value << QDF_MON_STATUS_DCM_SHIFT;
  1226. ppdu_info->rx_status.he_data3 |= value;
  1227. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1228. HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
  1229. value = value << QDF_MON_STATUS_CODING_SHIFT;
  1230. ppdu_info->rx_status.he_data3 |= value;
  1231. /* HE-data4 */
  1232. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1233. HE_SIG_B2_OFDMA_INFO_0, STA_ID);
  1234. value = value << QDF_MON_STATUS_STA_ID_SHIFT;
  1235. ppdu_info->rx_status.he_data4 |= value;
  1236. /* HE-data5 */
  1237. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1238. HE_SIG_B2_OFDMA_INFO_0, TXBF);
  1239. value = value << QDF_MON_STATUS_TXBF_SHIFT;
  1240. ppdu_info->rx_status.he_data5 |= value;
  1241. /* HE-data6 */
  1242. value = HAL_RX_GET(he_sig_b2_ofdma_info,
  1243. HE_SIG_B2_OFDMA_INFO_0, NSTS);
  1244. /* value n indicates n+1 spatial streams */
  1245. value++;
  1246. ppdu_info->rx_status.nss = value;
  1247. ppdu_info->rx_status.he_data6 |= value;
  1248. ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
  1249. break;
  1250. }
  1251. case WIFIPHYRX_RSSI_LEGACY_E:
  1252. {
  1253. uint8_t reception_type;
  1254. int8_t rssi_value;
  1255. uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
  1256. HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
  1257. RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
  1258. ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv,
  1259. PHYRX_RSSI_LEGACY_35, RSSI_COMB);
  1260. ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
  1261. ppdu_info->rx_status.he_re = 0;
  1262. reception_type = HAL_RX_GET(rx_tlv,
  1263. PHYRX_RSSI_LEGACY_0,
  1264. RECEPTION_TYPE);
  1265. switch (reception_type) {
  1266. case QDF_RECEPTION_TYPE_ULOFMDA:
  1267. ppdu_info->rx_status.reception_type =
  1268. HAL_RX_TYPE_MU_OFDMA;
  1269. ppdu_info->rx_status.ulofdma_flag = 1;
  1270. ppdu_info->rx_status.he_data1 =
  1271. QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
  1272. break;
  1273. case QDF_RECEPTION_TYPE_ULMIMO:
  1274. ppdu_info->rx_status.reception_type =
  1275. HAL_RX_TYPE_MU_MIMO;
  1276. ppdu_info->rx_status.he_data1 =
  1277. QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
  1278. break;
  1279. default:
  1280. ppdu_info->rx_status.reception_type =
  1281. HAL_RX_TYPE_SU;
  1282. break;
  1283. }
  1284. hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
  1285. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1286. RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
  1287. ppdu_info->rx_status.rssi[0] = rssi_value;
  1288. dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value);
  1289. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1290. RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1);
  1291. ppdu_info->rx_status.rssi[1] = rssi_value;
  1292. dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value);
  1293. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1294. RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2);
  1295. ppdu_info->rx_status.rssi[2] = rssi_value;
  1296. dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value);
  1297. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1298. RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3);
  1299. ppdu_info->rx_status.rssi[3] = rssi_value;
  1300. dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value);
  1301. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1302. RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4);
  1303. ppdu_info->rx_status.rssi[4] = rssi_value;
  1304. dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value);
  1305. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1306. RECEIVE_RSSI_INFO_10,
  1307. RSSI_PRI20_CHAIN5);
  1308. ppdu_info->rx_status.rssi[5] = rssi_value;
  1309. dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value);
  1310. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1311. RECEIVE_RSSI_INFO_12,
  1312. RSSI_PRI20_CHAIN6);
  1313. ppdu_info->rx_status.rssi[6] = rssi_value;
  1314. dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value);
  1315. rssi_value = HAL_RX_GET(rssi_info_tlv,
  1316. RECEIVE_RSSI_INFO_14,
  1317. RSSI_PRI20_CHAIN7);
  1318. ppdu_info->rx_status.rssi[7] = rssi_value;
  1319. dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value);
  1320. break;
  1321. }
  1322. case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
  1323. hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
  1324. ppdu_info);
  1325. break;
  1326. case WIFIRX_HEADER_E:
  1327. {
  1328. struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
  1329. if (ppdu_info->fcs_ok_cnt >=
  1330. HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
  1331. hal_err("Number of MPDUs(%d) per status buff exceeded",
  1332. ppdu_info->fcs_ok_cnt);
  1333. break;
  1334. }
  1335. /* Update first_msdu_payload for every mpdu and increment
  1336. * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
  1337. */
  1338. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
  1339. rx_tlv;
  1340. ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
  1341. ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
  1342. ppdu_info->msdu_info.payload_len = tlv_len;
  1343. ppdu_info->user_id = user_id;
  1344. ppdu_info->hdr_len = tlv_len;
  1345. ppdu_info->data = rx_tlv;
  1346. ppdu_info->data += 4;
  1347. /* for every RX_HEADER TLV increment mpdu_cnt */
  1348. com_info->mpdu_cnt++;
  1349. return HAL_TLV_STATUS_HEADER;
  1350. }
  1351. case WIFIRX_MPDU_START_E:
  1352. {
  1353. uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv;
  1354. uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start);
  1355. uint8_t filter_category = 0;
  1356. hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info);
  1357. ppdu_info->nac_info.fc_valid =
  1358. HAL_RX_GET_FC_VALID(rx_mpdu_start);
  1359. ppdu_info->nac_info.to_ds_flag =
  1360. HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start);
  1361. ppdu_info->nac_info.frame_control =
  1362. HAL_RX_GET(rx_mpdu_start,
  1363. RX_MPDU_INFO_14,
  1364. MPDU_FRAME_CONTROL_FIELD);
  1365. ppdu_info->sw_frame_group_id =
  1366. HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start);
  1367. ppdu_info->rx_user_status[user_id].sw_peer_id =
  1368. HAL_RX_GET_SW_PEER_ID(rx_mpdu_start);
  1369. if (ppdu_info->sw_frame_group_id ==
  1370. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
  1371. ppdu_info->rx_status.frame_control_info_valid =
  1372. ppdu_info->nac_info.fc_valid;
  1373. ppdu_info->rx_status.frame_control =
  1374. ppdu_info->nac_info.frame_control;
  1375. }
  1376. hal_get_mac_addr1(rx_mpdu_start,
  1377. ppdu_info);
  1378. ppdu_info->nac_info.mac_addr2_valid =
  1379. HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start);
  1380. *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
  1381. HAL_RX_GET(rx_mpdu_start,
  1382. RX_MPDU_INFO_16,
  1383. MAC_ADDR_AD2_15_0);
  1384. *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
  1385. HAL_RX_GET(rx_mpdu_start,
  1386. RX_MPDU_INFO_17,
  1387. MAC_ADDR_AD2_47_16);
  1388. if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
  1389. ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
  1390. ppdu_info->rx_status.ppdu_len =
  1391. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1392. MPDU_LENGTH);
  1393. } else {
  1394. ppdu_info->rx_status.ppdu_len +=
  1395. HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
  1396. MPDU_LENGTH);
  1397. }
  1398. filter_category =
  1399. HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start);
  1400. if (filter_category == 0)
  1401. ppdu_info->rx_status.rxpcu_filter_pass = 1;
  1402. else if (filter_category == 1)
  1403. ppdu_info->rx_status.monitor_direct_used = 1;
  1404. ppdu_info->nac_info.mcast_bcast =
  1405. HAL_RX_GET(rx_mpdu_start,
  1406. RX_MPDU_INFO_13,
  1407. MCAST_BCAST);
  1408. break;
  1409. }
  1410. case WIFIRX_MPDU_END_E:
  1411. ppdu_info->user_id = user_id;
  1412. ppdu_info->fcs_err =
  1413. HAL_RX_GET(rx_tlv, RX_MPDU_END_1,
  1414. FCS_ERR);
  1415. return HAL_TLV_STATUS_MPDU_END;
  1416. case WIFIRX_MSDU_END_E:
  1417. if (user_id < HAL_MAX_UL_MU_USERS) {
  1418. ppdu_info->rx_msdu_info[user_id].cce_metadata =
  1419. HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv);
  1420. ppdu_info->rx_msdu_info[user_id].fse_metadata =
  1421. HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv);
  1422. ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
  1423. HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv);
  1424. ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
  1425. HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv);
  1426. ppdu_info->rx_msdu_info[user_id].flow_idx =
  1427. HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv);
  1428. }
  1429. return HAL_TLV_STATUS_MSDU_END;
  1430. case 0:
  1431. return HAL_TLV_STATUS_PPDU_DONE;
  1432. default:
  1433. if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info))
  1434. unhandled = false;
  1435. else
  1436. unhandled = true;
  1437. break;
  1438. }
  1439. if (!unhandled)
  1440. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1441. "%s TLV type: %d, TLV len:%d %s",
  1442. __func__, tlv_tag, tlv_len,
  1443. unhandled == true ? "unhandled" : "");
  1444. qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1445. rx_tlv, tlv_len);
  1446. return HAL_TLV_STATUS_PPDU_NOT_DONE;
  1447. }
  1448. /**
  1449. * hal_rx_dump_rx_attention_tlv_generic_rh: dump RX attention TLV in structured
  1450. * humman readable format.
  1451. * @pkttlvs: pointer to pkttlvs.
  1452. * @dbg_level: log level.
  1453. *
  1454. * Return: void
  1455. */
  1456. static inline void hal_rx_dump_rx_attention_tlv_generic_rh(void *pkttlvs,
  1457. uint8_t dbg_level)
  1458. {
  1459. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
  1460. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  1461. hal_verbose_debug("rx_attention tlv (1/2) - "
  1462. "rxpcu_mpdu_filter_in_category: %x "
  1463. "sw_frame_group_id: %x "
  1464. "reserved_0: %x "
  1465. "phy_ppdu_id: %x "
  1466. "first_mpdu : %x "
  1467. "reserved_1a: %x "
  1468. "mcast_bcast: %x "
  1469. "ast_index_not_found: %x "
  1470. "ast_index_timeout: %x "
  1471. "power_mgmt: %x "
  1472. "non_qos: %x "
  1473. "null_data: %x "
  1474. "mgmt_type: %x "
  1475. "ctrl_type: %x "
  1476. "more_data: %x "
  1477. "eosp: %x "
  1478. "a_msdu_error: %x "
  1479. "fragment_flag: %x "
  1480. "order: %x "
  1481. "cce_match: %x "
  1482. "overflow_err: %x "
  1483. "msdu_length_err: %x "
  1484. "tcp_udp_chksum_fail: %x "
  1485. "ip_chksum_fail: %x "
  1486. "sa_idx_invalid: %x "
  1487. "da_idx_invalid: %x "
  1488. "reserved_1b: %x "
  1489. "rx_in_tx_decrypt_byp: %x ",
  1490. rx_attn->rxpcu_mpdu_filter_in_category,
  1491. rx_attn->sw_frame_group_id,
  1492. rx_attn->reserved_0,
  1493. rx_attn->phy_ppdu_id,
  1494. rx_attn->first_mpdu,
  1495. rx_attn->reserved_1a,
  1496. rx_attn->mcast_bcast,
  1497. rx_attn->ast_index_not_found,
  1498. rx_attn->ast_index_timeout,
  1499. rx_attn->power_mgmt,
  1500. rx_attn->non_qos,
  1501. rx_attn->null_data,
  1502. rx_attn->mgmt_type,
  1503. rx_attn->ctrl_type,
  1504. rx_attn->more_data,
  1505. rx_attn->eosp,
  1506. rx_attn->a_msdu_error,
  1507. rx_attn->fragment_flag,
  1508. rx_attn->order,
  1509. rx_attn->cce_match,
  1510. rx_attn->overflow_err,
  1511. rx_attn->msdu_length_err,
  1512. rx_attn->tcp_udp_chksum_fail,
  1513. rx_attn->ip_chksum_fail,
  1514. rx_attn->sa_idx_invalid,
  1515. rx_attn->da_idx_invalid,
  1516. rx_attn->reserved_1b,
  1517. rx_attn->rx_in_tx_decrypt_byp);
  1518. hal_verbose_debug("rx_attention tlv (2/2) - "
  1519. "encrypt_required: %x "
  1520. "directed: %x "
  1521. "buffer_fragment: %x "
  1522. "mpdu_length_err: %x "
  1523. "tkip_mic_err: %x "
  1524. "decrypt_err: %x "
  1525. "unencrypted_frame_err: %x "
  1526. "fcs_err: %x "
  1527. "flow_idx_timeout: %x "
  1528. "flow_idx_invalid: %x "
  1529. "wifi_parser_error: %x "
  1530. "amsdu_parser_error: %x "
  1531. "sa_idx_timeout: %x "
  1532. "da_idx_timeout: %x "
  1533. "msdu_limit_error: %x "
  1534. "da_is_valid: %x "
  1535. "da_is_mcbc: %x "
  1536. "sa_is_valid: %x "
  1537. "decrypt_status_code: %x "
  1538. "rx_bitmap_not_updated: %x "
  1539. "reserved_2: %x "
  1540. "msdu_done: %x ",
  1541. rx_attn->encrypt_required,
  1542. rx_attn->directed,
  1543. rx_attn->buffer_fragment,
  1544. rx_attn->mpdu_length_err,
  1545. rx_attn->tkip_mic_err,
  1546. rx_attn->decrypt_err,
  1547. rx_attn->unencrypted_frame_err,
  1548. rx_attn->fcs_err,
  1549. rx_attn->flow_idx_timeout,
  1550. rx_attn->flow_idx_invalid,
  1551. rx_attn->wifi_parser_error,
  1552. rx_attn->amsdu_parser_error,
  1553. rx_attn->sa_idx_timeout,
  1554. rx_attn->da_idx_timeout,
  1555. rx_attn->msdu_limit_error,
  1556. rx_attn->da_is_valid,
  1557. rx_attn->da_is_mcbc,
  1558. rx_attn->sa_is_valid,
  1559. rx_attn->decrypt_status_code,
  1560. rx_attn->rx_bitmap_not_updated,
  1561. rx_attn->reserved_2,
  1562. rx_attn->msdu_done);
  1563. }
  1564. /**
  1565. * hal_rx_dump_mpdu_end_tlv_generic_rh: dump RX mpdu_end TLV in structured
  1566. * human readable format.
  1567. * @pkttlvs: pointer to pkttlvs.
  1568. * @dbg_level: log level.
  1569. *
  1570. * Return: void
  1571. */
  1572. static inline void hal_rx_dump_mpdu_end_tlv_generic_rh(void *pkttlvs,
  1573. uint8_t dbg_level)
  1574. {
  1575. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
  1576. struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  1577. hal_verbose_debug("rx_mpdu_end tlv - "
  1578. "rxpcu_mpdu_filter_in_category: %x "
  1579. "sw_frame_group_id: %x "
  1580. "phy_ppdu_id: %x "
  1581. "unsup_ktype_short_frame: %x "
  1582. "rx_in_tx_decrypt_byp: %x "
  1583. "overflow_err: %x "
  1584. "mpdu_length_err: %x "
  1585. "tkip_mic_err: %x "
  1586. "decrypt_err: %x "
  1587. "unencrypted_frame_err: %x "
  1588. "pn_fields_contain_valid_info: %x "
  1589. "fcs_err: %x "
  1590. "msdu_length_err: %x "
  1591. "rxdma0_destination_ring: %x "
  1592. "rxdma1_destination_ring: %x "
  1593. "decrypt_status_code: %x "
  1594. "rx_bitmap_not_updated: %x ",
  1595. mpdu_end->rxpcu_mpdu_filter_in_category,
  1596. mpdu_end->sw_frame_group_id,
  1597. mpdu_end->phy_ppdu_id,
  1598. mpdu_end->unsup_ktype_short_frame,
  1599. mpdu_end->rx_in_tx_decrypt_byp,
  1600. mpdu_end->overflow_err,
  1601. mpdu_end->mpdu_length_err,
  1602. mpdu_end->tkip_mic_err,
  1603. mpdu_end->decrypt_err,
  1604. mpdu_end->unencrypted_frame_err,
  1605. mpdu_end->pn_fields_contain_valid_info,
  1606. mpdu_end->fcs_err,
  1607. mpdu_end->msdu_length_err,
  1608. mpdu_end->rxdma0_destination_ring,
  1609. mpdu_end->rxdma1_destination_ring,
  1610. mpdu_end->decrypt_status_code,
  1611. mpdu_end->rx_bitmap_not_updated);
  1612. }
  1613. #ifdef NO_RX_PKT_HDR_TLV
  1614. static inline void hal_rx_dump_pkt_hdr_tlv_generic_rh(void *pkttlvs,
  1615. uint8_t dbg_level)
  1616. {
  1617. }
  1618. #else
  1619. /**
  1620. * hal_rx_dump_pkt_hdr_tlv_generic_rh: dump RX pkt header TLV in hex format
  1621. * @pkttlvs: pointer to pkttlvs.
  1622. * @dbg_level: log level.
  1623. *
  1624. * Return: void
  1625. */
  1626. static inline void hal_rx_dump_pkt_hdr_tlv_generic_rh(void *pkttlvs,
  1627. uint8_t dbg_level)
  1628. {
  1629. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
  1630. struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
  1631. hal_verbose_debug("\n---------------\nrx_pkt_hdr_tlv"
  1632. "\n---------------\nphy_ppdu_id %d ",
  1633. pkt_hdr_tlv->phy_ppdu_id);
  1634. hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128);
  1635. }
  1636. #endif
  1637. /**
  1638. * hal_rx_dump_mpdu_start_tlv_generic_rh: dump RX mpdu_start TLV in structured
  1639. * human readable format.
  1640. * @pkttlvs: pointer to pkttlvs.
  1641. * @dbg_level: log level.
  1642. *
  1643. * Return: void
  1644. */
  1645. static inline void hal_rx_dump_mpdu_start_tlv_generic_rh(void *pkttlvs,
  1646. uint8_t dbg_level)
  1647. {
  1648. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
  1649. struct rx_mpdu_start *mpdu_start =
  1650. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  1651. struct rx_mpdu_info *mpdu_info =
  1652. (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
  1653. hal_verbose_debug(
  1654. "rx_mpdu_start tlv (1/5) - "
  1655. "rxpcu_mpdu_filter_in_category: %x "
  1656. "sw_frame_group_id: %x "
  1657. "ndp_frame: %x "
  1658. "phy_err: %x "
  1659. "phy_err_during_mpdu_header: %x "
  1660. "protocol_version_err: %x "
  1661. "ast_based_lookup_valid: %x "
  1662. "phy_ppdu_id: %x "
  1663. "ast_index: %x "
  1664. "sw_peer_id: %x "
  1665. "mpdu_frame_control_valid: %x "
  1666. "mpdu_duration_valid: %x "
  1667. "mac_addr_ad1_valid: %x "
  1668. "mac_addr_ad2_valid: %x "
  1669. "mac_addr_ad3_valid: %x "
  1670. "mac_addr_ad4_valid: %x "
  1671. "mpdu_sequence_control_valid: %x "
  1672. "mpdu_qos_control_valid: %x "
  1673. "mpdu_ht_control_valid: %x "
  1674. "frame_encryption_info_valid: %x ",
  1675. mpdu_info->rxpcu_mpdu_filter_in_category,
  1676. mpdu_info->sw_frame_group_id,
  1677. mpdu_info->ndp_frame,
  1678. mpdu_info->phy_err,
  1679. mpdu_info->phy_err_during_mpdu_header,
  1680. mpdu_info->protocol_version_err,
  1681. mpdu_info->ast_based_lookup_valid,
  1682. mpdu_info->phy_ppdu_id,
  1683. mpdu_info->ast_index,
  1684. mpdu_info->sw_peer_id,
  1685. mpdu_info->mpdu_frame_control_valid,
  1686. mpdu_info->mpdu_duration_valid,
  1687. mpdu_info->mac_addr_ad1_valid,
  1688. mpdu_info->mac_addr_ad2_valid,
  1689. mpdu_info->mac_addr_ad3_valid,
  1690. mpdu_info->mac_addr_ad4_valid,
  1691. mpdu_info->mpdu_sequence_control_valid,
  1692. mpdu_info->mpdu_qos_control_valid,
  1693. mpdu_info->mpdu_ht_control_valid,
  1694. mpdu_info->frame_encryption_info_valid);
  1695. hal_verbose_debug(
  1696. "rx_mpdu_start tlv (2/5) - "
  1697. "fr_ds: %x "
  1698. "to_ds: %x "
  1699. "encrypted: %x "
  1700. "mpdu_retry: %x "
  1701. "mpdu_sequence_number: %x "
  1702. "epd_en: %x "
  1703. "all_frames_shall_be_encrypted: %x "
  1704. "encrypt_type: %x "
  1705. "bssid_hit: %x "
  1706. "bssid_number: %x "
  1707. "tid: %x "
  1708. "pn_31_0: %x "
  1709. "pn_63_32: %x "
  1710. "pn_95_64: %x "
  1711. "pn_127_96: %x "
  1712. "peer_meta_data: %x "
  1713. "rxpt_classify_info.reo_destination_indication: %x "
  1714. "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x "
  1715. "rx_reo_queue_desc_addr_31_0: %x ",
  1716. mpdu_info->fr_ds,
  1717. mpdu_info->to_ds,
  1718. mpdu_info->encrypted,
  1719. mpdu_info->mpdu_retry,
  1720. mpdu_info->mpdu_sequence_number,
  1721. mpdu_info->epd_en,
  1722. mpdu_info->all_frames_shall_be_encrypted,
  1723. mpdu_info->encrypt_type,
  1724. mpdu_info->bssid_hit,
  1725. mpdu_info->bssid_number,
  1726. mpdu_info->tid,
  1727. mpdu_info->pn_31_0,
  1728. mpdu_info->pn_63_32,
  1729. mpdu_info->pn_95_64,
  1730. mpdu_info->pn_127_96,
  1731. mpdu_info->peer_meta_data,
  1732. mpdu_info->rxpt_classify_info_details.reo_destination_indication,
  1733. mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy,
  1734. mpdu_info->rx_reo_queue_desc_addr_31_0);
  1735. hal_verbose_debug(
  1736. "rx_mpdu_start tlv (3/5) - "
  1737. "rx_reo_queue_desc_addr_39_32: %x "
  1738. "receive_queue_number: %x "
  1739. "pre_delim_err_warning: %x "
  1740. "first_delim_err: %x "
  1741. "key_id_octet: %x "
  1742. "new_peer_entry: %x "
  1743. "decrypt_needed: %x "
  1744. "decap_type: %x "
  1745. "rx_insert_vlan_c_tag_padding: %x "
  1746. "rx_insert_vlan_s_tag_padding: %x "
  1747. "strip_vlan_c_tag_decap: %x "
  1748. "strip_vlan_s_tag_decap: %x "
  1749. "pre_delim_count: %x "
  1750. "ampdu_flag: %x "
  1751. "bar_frame: %x "
  1752. "mpdu_length: %x "
  1753. "first_mpdu: %x "
  1754. "mcast_bcast: %x "
  1755. "ast_index_not_found: %x "
  1756. "ast_index_timeout: %x ",
  1757. mpdu_info->rx_reo_queue_desc_addr_39_32,
  1758. mpdu_info->receive_queue_number,
  1759. mpdu_info->pre_delim_err_warning,
  1760. mpdu_info->first_delim_err,
  1761. mpdu_info->key_id_octet,
  1762. mpdu_info->new_peer_entry,
  1763. mpdu_info->decrypt_needed,
  1764. mpdu_info->decap_type,
  1765. mpdu_info->rx_insert_vlan_c_tag_padding,
  1766. mpdu_info->rx_insert_vlan_s_tag_padding,
  1767. mpdu_info->strip_vlan_c_tag_decap,
  1768. mpdu_info->strip_vlan_s_tag_decap,
  1769. mpdu_info->pre_delim_count,
  1770. mpdu_info->ampdu_flag,
  1771. mpdu_info->bar_frame,
  1772. mpdu_info->mpdu_length,
  1773. mpdu_info->first_mpdu,
  1774. mpdu_info->mcast_bcast,
  1775. mpdu_info->ast_index_not_found,
  1776. mpdu_info->ast_index_timeout);
  1777. hal_verbose_debug(
  1778. "rx_mpdu_start tlv (4/5) - "
  1779. "power_mgmt: %x "
  1780. "non_qos: %x "
  1781. "null_data: %x "
  1782. "mgmt_type: %x "
  1783. "ctrl_type: %x "
  1784. "more_data: %x "
  1785. "eosp: %x "
  1786. "fragment_flag: %x "
  1787. "order: %x "
  1788. "u_apsd_trigger: %x "
  1789. "encrypt_required: %x "
  1790. "directed: %x "
  1791. "mpdu_frame_control_field: %x "
  1792. "mpdu_duration_field: %x "
  1793. "mac_addr_ad1_31_0: %x "
  1794. "mac_addr_ad1_47_32: %x "
  1795. "mac_addr_ad2_15_0: %x "
  1796. "mac_addr_ad2_47_16: %x "
  1797. "mac_addr_ad3_31_0: %x "
  1798. "mac_addr_ad3_47_32: %x ",
  1799. mpdu_info->power_mgmt,
  1800. mpdu_info->non_qos,
  1801. mpdu_info->null_data,
  1802. mpdu_info->mgmt_type,
  1803. mpdu_info->ctrl_type,
  1804. mpdu_info->more_data,
  1805. mpdu_info->eosp,
  1806. mpdu_info->fragment_flag,
  1807. mpdu_info->order,
  1808. mpdu_info->u_apsd_trigger,
  1809. mpdu_info->encrypt_required,
  1810. mpdu_info->directed,
  1811. mpdu_info->mpdu_frame_control_field,
  1812. mpdu_info->mpdu_duration_field,
  1813. mpdu_info->mac_addr_ad1_31_0,
  1814. mpdu_info->mac_addr_ad1_47_32,
  1815. mpdu_info->mac_addr_ad2_15_0,
  1816. mpdu_info->mac_addr_ad2_47_16,
  1817. mpdu_info->mac_addr_ad3_31_0,
  1818. mpdu_info->mac_addr_ad3_47_32);
  1819. hal_verbose_debug(
  1820. "rx_mpdu_start tlv (5/5) - "
  1821. "mpdu_sequence_control_field: %x "
  1822. "mac_addr_ad4_31_0: %x "
  1823. "mac_addr_ad4_47_32: %x "
  1824. "mpdu_qos_control_field: %x "
  1825. "mpdu_ht_control_field: %x ",
  1826. mpdu_info->mpdu_sequence_control_field,
  1827. mpdu_info->mac_addr_ad4_31_0,
  1828. mpdu_info->mac_addr_ad4_47_32,
  1829. mpdu_info->mpdu_qos_control_field,
  1830. mpdu_info->mpdu_ht_control_field);
  1831. }
  1832. static void
  1833. hal_tx_set_pcp_tid_map_generic_rh(struct hal_soc *soc, uint8_t *map)
  1834. {
  1835. }
  1836. static void
  1837. hal_tx_update_pcp_tid_generic_rh(struct hal_soc *soc,
  1838. uint8_t pcp, uint8_t tid)
  1839. {
  1840. }
  1841. static void
  1842. hal_tx_update_tidmap_prty_generic_rh(struct hal_soc *soc, uint8_t value)
  1843. {
  1844. }
  1845. /**
  1846. * hal_rx_msdu_packet_metadata_get_generic_rh(): API to get the
  1847. * msdu information from rx_msdu_end TLV
  1848. *
  1849. * @buf: pointer to the start of RX PKT TLV headers
  1850. * @pkt_msdu_metadata: pointer to the msdu metadata
  1851. */
  1852. static void
  1853. hal_rx_msdu_packet_metadata_get_generic_rh(uint8_t *buf,
  1854. void *pkt_msdu_metadata)
  1855. {
  1856. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1857. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1858. struct hal_rx_msdu_metadata *msdu_metadata =
  1859. (struct hal_rx_msdu_metadata *)pkt_msdu_metadata;
  1860. msdu_metadata->l3_hdr_pad =
  1861. HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
  1862. msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
  1863. msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
  1864. msdu_metadata->sa_sw_peer_id =
  1865. HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
  1866. }
  1867. /**
  1868. * hal_rx_msdu_end_offset_get_generic(): API to get the
  1869. * msdu_end structure offset rx_pkt_tlv structure
  1870. *
  1871. * NOTE: API returns offset of msdu_end TLV from structure
  1872. * rx_pkt_tlvs
  1873. */
  1874. static uint32_t hal_rx_msdu_end_offset_get_generic(void)
  1875. {
  1876. return RX_PKT_TLV_OFFSET(msdu_end_tlv);
  1877. }
  1878. /**
  1879. * hal_rx_attn_offset_get_generic(): API to get the
  1880. * msdu_end structure offset rx_pkt_tlv structure
  1881. *
  1882. * NOTE: API returns offset of attn TLV from structure
  1883. * rx_pkt_tlvs
  1884. */
  1885. static uint32_t hal_rx_attn_offset_get_generic(void)
  1886. {
  1887. return RX_PKT_TLV_OFFSET(attn_tlv);
  1888. }
  1889. /**
  1890. * hal_rx_msdu_start_offset_get_generic(): API to get the
  1891. * msdu_start structure offset rx_pkt_tlv structure
  1892. *
  1893. * NOTE: API returns offset of attn TLV from structure
  1894. * rx_pkt_tlvs
  1895. */
  1896. static uint32_t hal_rx_msdu_start_offset_get_generic(void)
  1897. {
  1898. return RX_PKT_TLV_OFFSET(msdu_start_tlv);
  1899. }
  1900. /**
  1901. * hal_rx_mpdu_start_offset_get_generic(): API to get the
  1902. * mpdu_start structure offset rx_pkt_tlv structure
  1903. *
  1904. * NOTE: API returns offset of attn TLV from structure
  1905. * rx_pkt_tlvs
  1906. */
  1907. static uint32_t hal_rx_mpdu_start_offset_get_generic(void)
  1908. {
  1909. return RX_PKT_TLV_OFFSET(mpdu_start_tlv);
  1910. }
  1911. /**
  1912. * hal_rx_mpdu_end_offset_get_generic(): API to get the
  1913. * mpdu_end structure offset rx_pkt_tlv structure
  1914. *
  1915. * NOTE: API returns offset of attn TLV from structure
  1916. * rx_pkt_tlvs
  1917. */
  1918. static uint32_t hal_rx_mpdu_end_offset_get_generic(void)
  1919. {
  1920. return RX_PKT_TLV_OFFSET(mpdu_end_tlv);
  1921. }
  1922. #ifndef NO_RX_PKT_HDR_TLV
  1923. static uint32_t hal_rx_pkt_tlv_offset_get_generic(void)
  1924. {
  1925. return RX_PKT_TLV_OFFSET(pkt_hdr_tlv);
  1926. }
  1927. #endif
  1928. #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET
  1929. /**
  1930. * hal_tx_desc_set_search_type_generic_rh - Set the search type value
  1931. * @desc: Handle to Tx Descriptor
  1932. * @search_type: search type
  1933. * 0 – Normal search
  1934. * 1 – Index based address search
  1935. * 2 – Index based flow search
  1936. *
  1937. * Return: void
  1938. */
  1939. static inline
  1940. void hal_tx_desc_set_search_type_generic_rh(void *desc, uint8_t search_type)
  1941. {
  1942. HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |=
  1943. HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type);
  1944. }
  1945. #else
  1946. static inline
  1947. void hal_tx_desc_set_search_type_generic_rh(void *desc, uint8_t search_type)
  1948. {
  1949. }
  1950. #endif
  1951. #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET
  1952. /**
  1953. * hal_tx_desc_set_search_index_generic_rh - Set the search index value
  1954. * @desc: Handle to Tx Descriptor
  1955. * @search_index: The index that will be used for index based address or
  1956. * flow search. The field is valid when 'search_type' is
  1957. * 1 0r 2
  1958. *
  1959. * Return: void
  1960. */
  1961. static inline
  1962. void hal_tx_desc_set_search_index_generic_rh(void *desc, uint32_t search_index)
  1963. {
  1964. HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |=
  1965. HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index);
  1966. }
  1967. #else
  1968. static inline
  1969. void hal_tx_desc_set_search_index_generic_rh(void *desc, uint32_t search_index)
  1970. {
  1971. }
  1972. #endif
  1973. #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET
  1974. /**
  1975. * hal_tx_desc_set_cache_set_num_generic_rh - Set the cache-set-num value
  1976. * @desc: Handle to Tx Descriptor
  1977. * @cache_num: Cache set number that should be used to cache the index
  1978. * based search results, for address and flow search.
  1979. * This value should be equal to LSB four bits of the hash value
  1980. * of match data, in case of search index points to an entry
  1981. * which may be used in content based search also. The value can
  1982. * be anything when the entry pointed by search index will not be
  1983. * used for content based search.
  1984. *
  1985. * Return: void
  1986. */
  1987. static inline
  1988. void hal_tx_desc_set_cache_set_num_generic_rh(void *desc, uint8_t cache_num)
  1989. {
  1990. HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |=
  1991. HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num);
  1992. }
  1993. #else
  1994. static inline
  1995. void hal_tx_desc_set_cache_set_num_generic_rh(void *desc, uint8_t cache_num)
  1996. {
  1997. }
  1998. #endif
  1999. #ifdef WLAN_SUPPORT_RX_FISA
  2000. /**
  2001. * hal_rx_flow_get_tuple_info_rh() - Setup a flow search entry in HW FST
  2002. * @rx_fst: Pointer to the Rx Flow Search Table
  2003. * @hal_hash: HAL 5 tuple hash
  2004. * @flow_tuple_info: 5-tuple info of the flow returned to the caller
  2005. *
  2006. * Return: Success/Failure
  2007. */
  2008. static void *
  2009. hal_rx_flow_get_tuple_info_rh(uint8_t *rx_fst, uint32_t hal_hash,
  2010. uint8_t *flow_tuple_info)
  2011. {
  2012. struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
  2013. void *hal_fse = NULL;
  2014. struct hal_flow_tuple_info *tuple_info
  2015. = (struct hal_flow_tuple_info *)flow_tuple_info;
  2016. hal_fse = (uint8_t *)fst->base_vaddr +
  2017. (hal_hash * HAL_RX_FST_ENTRY_SIZE);
  2018. if (!hal_fse || !tuple_info)
  2019. return NULL;
  2020. if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
  2021. return NULL;
  2022. tuple_info->src_ip_127_96 =
  2023. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2024. RX_FLOW_SEARCH_ENTRY_0,
  2025. SRC_IP_127_96));
  2026. tuple_info->src_ip_95_64 =
  2027. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2028. RX_FLOW_SEARCH_ENTRY_1,
  2029. SRC_IP_95_64));
  2030. tuple_info->src_ip_63_32 =
  2031. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2032. RX_FLOW_SEARCH_ENTRY_2,
  2033. SRC_IP_63_32));
  2034. tuple_info->src_ip_31_0 =
  2035. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2036. RX_FLOW_SEARCH_ENTRY_3,
  2037. SRC_IP_31_0));
  2038. tuple_info->dest_ip_127_96 =
  2039. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2040. RX_FLOW_SEARCH_ENTRY_4,
  2041. DEST_IP_127_96));
  2042. tuple_info->dest_ip_95_64 =
  2043. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2044. RX_FLOW_SEARCH_ENTRY_5,
  2045. DEST_IP_95_64));
  2046. tuple_info->dest_ip_63_32 =
  2047. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2048. RX_FLOW_SEARCH_ENTRY_6,
  2049. DEST_IP_63_32));
  2050. tuple_info->dest_ip_31_0 =
  2051. qdf_ntohl(HAL_GET_FLD(hal_fse,
  2052. RX_FLOW_SEARCH_ENTRY_7,
  2053. DEST_IP_31_0));
  2054. tuple_info->dest_port = HAL_GET_FLD(hal_fse,
  2055. RX_FLOW_SEARCH_ENTRY_8,
  2056. DEST_PORT);
  2057. tuple_info->src_port = HAL_GET_FLD(hal_fse,
  2058. RX_FLOW_SEARCH_ENTRY_8,
  2059. SRC_PORT);
  2060. tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
  2061. RX_FLOW_SEARCH_ENTRY_9,
  2062. L4_PROTOCOL);
  2063. return hal_fse;
  2064. }
  2065. /**
  2066. * hal_rx_flow_delete_entry_rh() - Setup a flow search entry in HW FST
  2067. * @rx_fst: Pointer to the Rx Flow Search Table
  2068. * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
  2069. *
  2070. * Return: Success/Failure
  2071. */
  2072. static QDF_STATUS
  2073. hal_rx_flow_delete_entry_rh(uint8_t *rx_fst, void *hal_rx_fse)
  2074. {
  2075. uint8_t *fse = (uint8_t *)hal_rx_fse;
  2076. if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
  2077. return QDF_STATUS_E_NOENT;
  2078. HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
  2079. return QDF_STATUS_SUCCESS;
  2080. }
  2081. /**
  2082. * hal_rx_fst_get_fse_size_rh() - Retrieve the size of each entry
  2083. *
  2084. * Return: size of each entry/flow in Rx FST
  2085. */
  2086. static inline uint32_t
  2087. hal_rx_fst_get_fse_size_rh(void)
  2088. {
  2089. return HAL_RX_FST_ENTRY_SIZE;
  2090. }
  2091. #else
  2092. static inline void *
  2093. hal_rx_flow_get_tuple_info_rh(uint8_t *rx_fst, uint32_t hal_hash,
  2094. uint8_t *flow_tuple_info)
  2095. {
  2096. return NULL;
  2097. }
  2098. static inline QDF_STATUS
  2099. hal_rx_flow_delete_entry_rh(uint8_t *rx_fst, void *hal_rx_fse)
  2100. {
  2101. return QDF_STATUS_SUCCESS;
  2102. }
  2103. static inline uint32_t
  2104. hal_rx_fst_get_fse_size_rh(void)
  2105. {
  2106. return 0;
  2107. }
  2108. #endif /* WLAN_SUPPORT_RX_FISA */
  2109. /**
  2110. * hal_rx_get_frame_ctrl_field_rh(): Function to retrieve frame control field
  2111. *
  2112. * @buf: Network buffer
  2113. *
  2114. * Returns: rx more fragment bit
  2115. */
  2116. static uint16_t hal_rx_get_frame_ctrl_field_rh(uint8_t *buf)
  2117. {
  2118. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  2119. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  2120. uint16_t frame_ctrl = 0;
  2121. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
  2122. return frame_ctrl;
  2123. }
  2124. #if defined(WLAN_FEATURE_TSF_UPLINK_DELAY) || defined(WLAN_CONFIG_TX_DELAY)
  2125. static inline void
  2126. hal_tx_comp_get_buffer_timestamp_rh(void *desc,
  2127. struct hal_tx_completion_status *ts)
  2128. {
  2129. uint32_t *msg_word = (struct uint32_t *)desc;
  2130. ts->buffer_timestamp =
  2131. HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_GET(*(msg_word + 4));
  2132. }
  2133. #else /* !WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
  2134. static inline void
  2135. hal_tx_comp_get_buffer_timestamp_rh(void *desc,
  2136. struct hal_tx_completion_status *ts)
  2137. {
  2138. }
  2139. #endif /* WLAN_FEATURE_TSF_UPLINK_DELAY || WLAN_CONFIG_TX_DELAY */
  2140. static inline uint8_t hal_tx_get_compl_status_rh(uint8_t tx_status)
  2141. {
  2142. switch (tx_status) {
  2143. case HTT_TX_MSDU_RELEASE_REASON_FRAME_ACKED:
  2144. return HAL_TX_TQM_RR_FRAME_ACKED;
  2145. case HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_TX:
  2146. return HAL_TX_TQM_RR_REM_CMD_TX;
  2147. case HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_NOTX:
  2148. return HAL_TX_TQM_RR_REM_CMD_NOTX;
  2149. case HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_AGED:
  2150. return HAL_TX_TQM_RR_REM_CMD_AGED;
  2151. case HTT_TX_MSDU_RELEASE_FW_REASON1:
  2152. return HAL_TX_TQM_RR_FW_REASON1;
  2153. case HTT_TX_MSDU_RELEASE_FW_REASON2:
  2154. return HAL_TX_TQM_RR_FW_REASON2;
  2155. case HTT_TX_MSDU_RELEASE_FW_REASON3:
  2156. return HAL_TX_TQM_RR_FW_REASON3;
  2157. case HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_DISABLEQ:
  2158. return HAL_TX_TQM_RR_REM_CMD_DISABLE_QUEUE;
  2159. default:
  2160. return HAL_TX_TQM_RR_REM_CMD_REM;
  2161. }
  2162. }
  2163. static inline void
  2164. hal_tx_comp_get_status_generic_rh(void *desc, void *ts1, struct hal_soc *hal)
  2165. {
  2166. uint8_t tx_status;
  2167. struct hal_tx_completion_status *ts =
  2168. (struct hal_tx_completion_status *)ts1;
  2169. uint32_t *msg_word = (uint32_t *)desc;
  2170. if (HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_GET(*(msg_word + 1)) ==
  2171. HTT_TX_MSDU_RELEASE_SOURCE_FW)
  2172. ts->release_src = HAL_TX_COMP_RELEASE_SOURCE_FW;
  2173. else
  2174. ts->release_src = HAL_TX_COMP_RELEASE_SOURCE_TQM;
  2175. if (HTT_TX_MSDU_INFO_VALID_GET(*(msg_word + 2))) {
  2176. ts->peer_id = HTT_TX_MSDU_INFO_SW_PEER_ID_GET(*(msg_word + 2));
  2177. ts->tid = HTT_TX_MSDU_INFO_TID_GET(*(msg_word + 2));
  2178. } else {
  2179. ts->peer_id = HTT_INVALID_PEER;
  2180. ts->tid = HTT_INVALID_TID;
  2181. }
  2182. ts->transmit_cnt = HTT_TX_MSDU_INFO_TRANSMIT_CNT_GET(*(msg_word + 2));
  2183. tx_status = HTT_TX_MSDU_INFO_RELEASE_REASON_GET(*(msg_word + 3));
  2184. ts->status = hal_tx_get_compl_status_rh(tx_status);
  2185. ts->ppdu_id = HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_GET(*(msg_word + 3));
  2186. ts->ack_frame_rssi =
  2187. HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_GET(*(msg_word + 4));
  2188. ts->first_msdu = HTT_TX_MSDU_INFO_FIRST_MSDU_GET(*(msg_word + 4));
  2189. ts->last_msdu = HTT_TX_MSDU_INFO_LAST_MSDU_GET(*(msg_word + 4));
  2190. ts->msdu_part_of_amsdu =
  2191. HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_GET(*(msg_word + 4));
  2192. ts->valid = HTT_TX_RATE_STATS_INFO_VALID_GET(*(msg_word + 5));
  2193. if (ts->valid) {
  2194. ts->bw = HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_GET(*(msg_word + 5));
  2195. ts->pkt_type =
  2196. HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_GET(*(msg_word + 5));
  2197. ts->stbc = HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_GET(*(msg_word + 5));
  2198. ts->ldpc = HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_GET(*(msg_word + 5));
  2199. ts->sgi = HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_GET(*(msg_word + 5));
  2200. ts->mcs = HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_GET(*(msg_word + 5));
  2201. ts->ofdma =
  2202. HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_GET(*(msg_word + 5));
  2203. ts->tones_in_ru = HTT_TX_RATE_STATS_INFO_TONES_IN_RU_GET(*(msg_word + 5));
  2204. }
  2205. ts->tsf = HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_GET(*(msg_word + 6));
  2206. hal_tx_comp_get_buffer_timestamp_rh(desc, ts);
  2207. }
  2208. #endif /* _HAL_RH_GENERIC_API_H_ */