hal_be_api.h 4.9 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #ifndef _HAL_BE_API_H_
  20. #define _HAL_BE_API_H_
  21. #include "hal_hw_headers.h"
  22. #include "hal_rx.h"
  23. #define HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr) \
  24. ((struct rx_msdu_ext_desc_info *) \
  25. _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
  26. RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
  27. /**
  28. * hal_reo_setup_generic_be - Initialize HW REO block
  29. *
  30. * @soc: Opaque HAL SOC handle
  31. * @reoparams: parameters needed by HAL for REO config
  32. * @qref_reset: reset qref
  33. */
  34. void hal_reo_setup_generic_be(struct hal_soc *soc,
  35. void *reoparams, int qref_reset);
  36. /**
  37. * hal_rx_msdu_ext_desc_info_get_ptr_be() - Get the msdu extension
  38. * descriptor pointer.
  39. * @msdu_details_ptr: msdu details
  40. *
  41. * Return: msdu exntension descriptor pointer.
  42. */
  43. void *hal_rx_msdu_ext_desc_info_get_ptr_be(void *msdu_details_ptr);
  44. /**
  45. * hal_set_link_desc_addr_be - Setup link descriptor in a buffer_addr_info
  46. * HW structure
  47. *
  48. * @desc: Descriptor entry (from WBM_IDLE_LINK ring)
  49. * @cookie: SW cookie for the buffer/descriptor
  50. * @link_desc_paddr: Physical address of link descriptor entry
  51. * @bm_id: idle link BM id
  52. *
  53. */
  54. void hal_set_link_desc_addr_be(void *desc, uint32_t cookie,
  55. qdf_dma_addr_t link_desc_paddr,
  56. uint8_t bm_id);
  57. /**
  58. * hal_hw_txrx_default_ops_attach_be() - Add default ops for BE chips
  59. * @soc: hal_soc handle
  60. *
  61. * Return: None
  62. */
  63. void hal_hw_txrx_default_ops_attach_be(struct hal_soc *soc);
  64. uint32_t hal_tx_comp_get_buffer_source_generic_be(void *hal_desc);
  65. /**
  66. * hal_rx_ret_buf_manager_get_be() - Get return buffer manager from ring desc
  67. * @ring_desc: ring descriptor
  68. *
  69. * Return: rbm
  70. */
  71. uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc);
  72. /**
  73. * hal_rx_wbm_err_info_get_generic_be() - Retrieves WBM error code and reason and
  74. * save it to hal_wbm_err_desc_info structure passed by caller
  75. * @wbm_desc: wbm ring descriptor
  76. * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter.
  77. *
  78. * Return: void
  79. */
  80. void hal_rx_wbm_err_info_get_generic_be(void *wbm_desc, void *wbm_er_info1);
  81. /**
  82. * hal_reo_qdesc_setup_be() - Setup HW REO queue descriptor
  83. * @hal_soc_hdl: Opaque HAL SOC handle
  84. * @tid: TID
  85. * @ba_window_size: BlockAck window size
  86. * @start_seq: Starting sequence number
  87. * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
  88. * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
  89. * @pn_type: PN type (one of the types defined in 'enum hal_pn_type')
  90. * @vdev_stats_id: vdev_stats_id to be programmed in REO Queue Descriptor
  91. */
  92. void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl,
  93. int tid, uint32_t ba_window_size,
  94. uint32_t start_seq, void *hw_qdesc_vaddr,
  95. qdf_dma_addr_t hw_qdesc_paddr,
  96. int pn_type, uint8_t vdev_stats_id);
  97. /**
  98. * hal_cookie_conversion_reg_cfg_be() - set cookie conversion relevant register
  99. * for REO/WBM
  100. * @hal_soc_hdl: Handle to HAL SoC structure
  101. * @cc_cfg: structure pointer for HW cookie conversion configuration
  102. *
  103. * Return: None
  104. */
  105. void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,
  106. struct hal_hw_cc_config *cc_cfg);
  107. /**
  108. * hal_reo_ix_remap_value_get_be() - Calculate reo remap register value from
  109. * ring_id_mask which is used for hash based
  110. * reo distribution
  111. * @hal_soc_hdl: Handle to HAL SoC structure
  112. * @rx_ring_mask: mask value indicating the rx rings 0th bit set indicate
  113. * REO2SW1 is included in hash distribution
  114. *
  115. * Return: REO remap value
  116. */
  117. uint32_t
  118. hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl,
  119. uint8_t rx_ring_mask);
  120. /**
  121. * hal_reo_ring_remap_value_get_be() - return REO remap value
  122. * @rx_ring_id: REO2SW ring mask
  123. *
  124. * Return: REO remap value
  125. */
  126. uint8_t
  127. hal_reo_ring_remap_value_get_be(uint8_t rx_ring_id);
  128. /**
  129. * hal_setup_reo_swap() - Set the swap flag for big endian machines
  130. * @soc: HAL soc handle
  131. *
  132. * Return: None
  133. */
  134. void hal_setup_reo_swap(struct hal_soc *soc);
  135. /**
  136. * hal_get_idle_link_bm_id_be() - Get idle link BM id from chid_id
  137. * @chip_id: mlo chip_id
  138. *
  139. * Returns: RBM ID
  140. */
  141. uint8_t hal_get_idle_link_bm_id_be(uint8_t chip_id);
  142. #endif /* _HAL_BE_API_H_ */