sde_kms.c 114 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <drm/drm_panel.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/dma-buf.h>
  26. #include <linux/memblock.h>
  27. #include <drm/drm_atomic_uapi.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "msm_drv.h"
  30. #include "msm_mmu.h"
  31. #include "msm_gem.h"
  32. #include "dsi_display.h"
  33. #include "dsi_drm.h"
  34. #include "sde_wb.h"
  35. #include "dp_display.h"
  36. #include "dp_drm.h"
  37. #include "dp_mst_drm.h"
  38. #include "sde_kms.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_formats.h"
  41. #include "sde_hw_vbif.h"
  42. #include "sde_vbif.h"
  43. #include "sde_encoder.h"
  44. #include "sde_plane.h"
  45. #include "sde_crtc.h"
  46. #include "sde_color_processing.h"
  47. #include "sde_reg_dma.h"
  48. #include "sde_connector.h"
  49. #include "sde_vm.h"
  50. #include <linux/qcom_scm.h>
  51. #include "soc/qcom/secure_buffer.h"
  52. #include <linux/qtee_shmbridge.h>
  53. #include <linux/haven/hh_irq_lend.h>
  54. #define CREATE_TRACE_POINTS
  55. #include "sde_trace.h"
  56. /* defines for secure channel call */
  57. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  58. #define MDP_DEVICE_ID 0x1A
  59. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  60. static const char * const iommu_ports[] = {
  61. "mdp_0",
  62. };
  63. /**
  64. * Controls size of event log buffer. Specified as a power of 2.
  65. */
  66. #define SDE_EVTLOG_SIZE 1024
  67. /*
  68. * To enable overall DRM driver logging
  69. * # echo 0x2 > /sys/module/drm/parameters/debug
  70. *
  71. * To enable DRM driver h/w logging
  72. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  73. *
  74. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  75. */
  76. #define SDE_DEBUGFS_DIR "msm_sde"
  77. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  78. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  79. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  80. /**
  81. * sdecustom - enable certain driver customizations for sde clients
  82. * Enabling this modifies the standard DRM behavior slightly and assumes
  83. * that the clients have specific knowledge about the modifications that
  84. * are involved, so don't enable this unless you know what you're doing.
  85. *
  86. * Parts of the driver that are affected by this setting may be located by
  87. * searching for invocations of the 'sde_is_custom_client()' function.
  88. *
  89. * This is disabled by default.
  90. */
  91. static bool sdecustom = true;
  92. module_param(sdecustom, bool, 0400);
  93. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  94. static int sde_kms_hw_init(struct msm_kms *kms);
  95. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  96. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  97. static int _sde_kms_register_events(struct msm_kms *kms,
  98. struct drm_mode_object *obj, u32 event, bool en);
  99. bool sde_is_custom_client(void)
  100. {
  101. return sdecustom;
  102. }
  103. #ifdef CONFIG_DEBUG_FS
  104. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  105. {
  106. struct msm_drm_private *priv;
  107. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  108. return NULL;
  109. priv = sde_kms->dev->dev_private;
  110. return priv->debug_root;
  111. }
  112. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  113. {
  114. void *p;
  115. int rc;
  116. void *debugfs_root;
  117. p = sde_hw_util_get_log_mask_ptr();
  118. if (!sde_kms || !p)
  119. return -EINVAL;
  120. debugfs_root = sde_debugfs_get_root(sde_kms);
  121. if (!debugfs_root)
  122. return -EINVAL;
  123. /* allow debugfs_root to be NULL */
  124. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  125. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  126. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  127. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  128. if (rc) {
  129. SDE_ERROR("failed to init perf %d\n", rc);
  130. return rc;
  131. }
  132. if (sde_kms->catalog->qdss_count)
  133. debugfs_create_u32("qdss", 0600, debugfs_root,
  134. (u32 *)&sde_kms->qdss_enabled);
  135. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  136. (u32 *)&sde_kms->pm_suspend_clk_dump);
  137. return 0;
  138. }
  139. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  140. {
  141. struct sde_kms *sde_kms = to_sde_kms(kms);
  142. /* don't need to NULL check debugfs_root */
  143. if (sde_kms) {
  144. sde_debugfs_vbif_destroy(sde_kms);
  145. sde_debugfs_core_irq_destroy(sde_kms);
  146. }
  147. }
  148. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  149. {
  150. int i;
  151. struct device *dev = sde_kms->dev->dev;
  152. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  153. for (i = 0; i < sde_kms->dsi_display_count; i++)
  154. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  155. return 0;
  156. }
  157. #else
  158. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  159. {
  160. return 0;
  161. }
  162. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  163. {
  164. }
  165. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  166. {
  167. return 0;
  168. }
  169. #endif
  170. static bool _sde_kms_skip_vblank_op(struct sde_kms *sde_kms)
  171. {
  172. struct sde_vm_ops *vm_ops = sde_vm_get_ops(sde_kms);
  173. if (vm_ops && vm_ops->vm_owns_hw
  174. && !vm_ops->vm_owns_hw(sde_kms))
  175. return true;
  176. return false;
  177. }
  178. static int sde_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  179. {
  180. int ret = 0;
  181. struct sde_kms *sde_kms;
  182. if (!kms)
  183. return -EINVAL;
  184. sde_kms = to_sde_kms(kms);
  185. sde_vm_lock(sde_kms);
  186. if (_sde_kms_skip_vblank_op(sde_kms)) {
  187. SDE_DEBUG("skipping vblank enable due to HW unavailablity\n");
  188. goto done;
  189. }
  190. SDE_ATRACE_BEGIN("sde_kms_enable_vblank");
  191. ret = sde_crtc_vblank(crtc, true);
  192. SDE_ATRACE_END("sde_kms_enable_vblank");
  193. done:
  194. sde_vm_unlock(sde_kms);
  195. return ret;
  196. }
  197. static void sde_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
  198. {
  199. struct sde_kms *sde_kms;
  200. if (!kms)
  201. return;
  202. sde_kms = to_sde_kms(kms);
  203. sde_vm_lock(sde_kms);
  204. if (_sde_kms_skip_vblank_op(sde_kms)) {
  205. SDE_DEBUG("skipping vblank disable due to HW unavailablity\n");
  206. goto done;
  207. }
  208. SDE_ATRACE_BEGIN("sde_kms_disable_vblank");
  209. sde_crtc_vblank(crtc, false);
  210. SDE_ATRACE_END("sde_kms_disable_vblank");
  211. done:
  212. sde_vm_unlock(sde_kms);
  213. }
  214. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  215. struct drm_crtc *crtc)
  216. {
  217. struct drm_encoder *encoder;
  218. struct drm_device *dev;
  219. int ret;
  220. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  221. SDE_ERROR("invalid params\n");
  222. return;
  223. }
  224. if (!crtc->state->enable) {
  225. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  226. return;
  227. }
  228. if (!crtc->state->active) {
  229. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  230. return;
  231. }
  232. dev = crtc->dev;
  233. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  234. if (encoder->crtc != crtc)
  235. continue;
  236. /*
  237. * Video Mode - Wait for VSYNC
  238. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  239. * complete
  240. */
  241. SDE_EVT32_VERBOSE(DRMID(crtc));
  242. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  243. if (ret && ret != -EWOULDBLOCK) {
  244. SDE_ERROR(
  245. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  246. crtc->base.id, encoder->base.id, ret);
  247. break;
  248. }
  249. }
  250. }
  251. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  252. struct drm_crtc *crtc, bool enable)
  253. {
  254. struct drm_device *dev;
  255. struct msm_drm_private *priv;
  256. struct sde_mdss_cfg *sde_cfg;
  257. struct drm_plane *plane;
  258. int i, ret;
  259. dev = sde_kms->dev;
  260. priv = dev->dev_private;
  261. sde_cfg = sde_kms->catalog;
  262. ret = sde_vbif_halt_xin_mask(sde_kms,
  263. sde_cfg->sui_block_xin_mask, enable);
  264. if (ret) {
  265. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  266. return ret;
  267. }
  268. if (enable) {
  269. for (i = 0; i < priv->num_planes; i++) {
  270. plane = priv->planes[i];
  271. sde_plane_secure_ctrl_xin_client(plane, crtc);
  272. }
  273. }
  274. return 0;
  275. }
  276. /**
  277. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  278. * @sde_kms: Pointer to sde_kms struct
  279. * @vimd: switch the stage 2 translation to this VMID
  280. */
  281. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  282. {
  283. struct device dummy = {};
  284. dma_addr_t dma_handle;
  285. uint32_t num_sids;
  286. uint32_t *sec_sid;
  287. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  288. int ret = 0, i;
  289. struct qtee_shm shm;
  290. bool qtee_en = qtee_shmbridge_is_enabled();
  291. phys_addr_t mem_addr;
  292. u64 mem_size;
  293. num_sids = sde_cfg->sec_sid_mask_count;
  294. if (!num_sids) {
  295. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  296. return -EINVAL;
  297. }
  298. if (qtee_en) {
  299. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  300. &shm);
  301. if (ret)
  302. return -ENOMEM;
  303. sec_sid = (uint32_t *) shm.vaddr;
  304. mem_addr = shm.paddr;
  305. /**
  306. * SMMUSecureModeSwitch requires the size to be number of SID's
  307. * but shm allocates size in pages. Modify the args as per
  308. * client requirement.
  309. */
  310. mem_size = sizeof(uint32_t) * num_sids;
  311. } else {
  312. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  313. if (!sec_sid)
  314. return -ENOMEM;
  315. mem_addr = virt_to_phys(sec_sid);
  316. mem_size = sizeof(uint32_t) * num_sids;
  317. }
  318. for (i = 0; i < num_sids; i++) {
  319. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  320. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  321. }
  322. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  323. if (ret) {
  324. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  325. goto map_error;
  326. }
  327. set_dma_ops(&dummy, NULL);
  328. dma_handle = dma_map_single(&dummy, sec_sid,
  329. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  330. if (dma_mapping_error(&dummy, dma_handle)) {
  331. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  332. vmid);
  333. goto map_error;
  334. }
  335. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  336. vmid, num_sids, qtee_en);
  337. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  338. mem_size, vmid);
  339. if (ret)
  340. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  341. vmid, ret);
  342. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  343. vmid, qtee_en, num_sids, ret);
  344. dma_unmap_single(&dummy, dma_handle,
  345. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  346. map_error:
  347. if (qtee_en)
  348. qtee_shmbridge_free_shm(&shm);
  349. else
  350. kfree(sec_sid);
  351. return ret;
  352. }
  353. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  354. {
  355. u32 ret;
  356. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  357. return 0;
  358. /* detach_all_contexts */
  359. ret = sde_kms_mmu_detach(sde_kms, false);
  360. if (ret) {
  361. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  362. goto mmu_error;
  363. }
  364. ret = _sde_kms_scm_call(sde_kms, vmid);
  365. if (ret) {
  366. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  367. goto scm_error;
  368. }
  369. return 0;
  370. scm_error:
  371. sde_kms_mmu_attach(sde_kms, false);
  372. mmu_error:
  373. atomic_dec(&sde_kms->detach_all_cb);
  374. return ret;
  375. }
  376. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  377. u32 old_vmid)
  378. {
  379. u32 ret;
  380. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  381. return 0;
  382. ret = _sde_kms_scm_call(sde_kms, vmid);
  383. if (ret) {
  384. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  385. goto scm_error;
  386. }
  387. /* attach_all_contexts */
  388. ret = sde_kms_mmu_attach(sde_kms, false);
  389. if (ret) {
  390. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  391. goto mmu_error;
  392. }
  393. return 0;
  394. mmu_error:
  395. _sde_kms_scm_call(sde_kms, old_vmid);
  396. scm_error:
  397. atomic_inc(&sde_kms->detach_all_cb);
  398. return ret;
  399. }
  400. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  401. {
  402. u32 ret;
  403. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  404. return 0;
  405. /* detach secure_context */
  406. ret = sde_kms_mmu_detach(sde_kms, true);
  407. if (ret) {
  408. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  409. goto mmu_error;
  410. }
  411. ret = _sde_kms_scm_call(sde_kms, vmid);
  412. if (ret) {
  413. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  414. goto scm_error;
  415. }
  416. return 0;
  417. scm_error:
  418. sde_kms_mmu_attach(sde_kms, true);
  419. mmu_error:
  420. atomic_dec(&sde_kms->detach_sec_cb);
  421. return ret;
  422. }
  423. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  424. u32 old_vmid)
  425. {
  426. u32 ret;
  427. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  428. return 0;
  429. ret = _sde_kms_scm_call(sde_kms, vmid);
  430. if (ret) {
  431. goto scm_error;
  432. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  433. }
  434. ret = sde_kms_mmu_attach(sde_kms, true);
  435. if (ret) {
  436. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  437. goto mmu_error;
  438. }
  439. return 0;
  440. mmu_error:
  441. _sde_kms_scm_call(sde_kms, old_vmid);
  442. scm_error:
  443. atomic_inc(&sde_kms->detach_sec_cb);
  444. return ret;
  445. }
  446. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  447. struct drm_crtc *crtc, bool enable)
  448. {
  449. int ret;
  450. if (enable) {
  451. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  452. if (ret < 0) {
  453. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  454. return ret;
  455. }
  456. sde_crtc_misr_setup(crtc, true, 1);
  457. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  458. if (ret) {
  459. sde_crtc_misr_setup(crtc, false, 0);
  460. pm_runtime_put_sync(sde_kms->dev->dev);
  461. return ret;
  462. }
  463. } else {
  464. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  465. sde_crtc_misr_setup(crtc, false, 0);
  466. pm_runtime_put_sync(sde_kms->dev->dev);
  467. }
  468. return 0;
  469. }
  470. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  471. bool post_commit)
  472. {
  473. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  474. int old_smmu_state = smmu_state->state;
  475. int ret = 0;
  476. u32 vmid;
  477. if (!sde_kms || !crtc) {
  478. SDE_ERROR("invalid argument(s)\n");
  479. return -EINVAL;
  480. }
  481. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  482. post_commit, smmu_state->sui_misr_state,
  483. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  484. if ((!smmu_state->transition_type) ||
  485. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  486. /* Bail out */
  487. return 0;
  488. /* enable sui misr if requested, before the transition */
  489. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  490. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  491. if (ret) {
  492. smmu_state->sui_misr_state = NONE;
  493. goto end;
  494. }
  495. }
  496. mutex_lock(&sde_kms->secure_transition_lock);
  497. switch (smmu_state->state) {
  498. case DETACH_ALL_REQ:
  499. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  500. if (!ret)
  501. smmu_state->state = DETACHED;
  502. break;
  503. case ATTACH_ALL_REQ:
  504. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  505. VMID_CP_SEC_DISPLAY);
  506. if (!ret) {
  507. smmu_state->state = ATTACHED;
  508. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  509. }
  510. break;
  511. case DETACH_SEC_REQ:
  512. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  513. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  514. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  515. if (!ret)
  516. smmu_state->state = DETACHED_SEC;
  517. break;
  518. case ATTACH_SEC_REQ:
  519. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  520. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  521. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  522. if (!ret) {
  523. smmu_state->state = ATTACHED;
  524. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  525. }
  526. break;
  527. default:
  528. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  529. DRMID(crtc), smmu_state->state,
  530. smmu_state->transition_type);
  531. ret = -EINVAL;
  532. break;
  533. }
  534. mutex_unlock(&sde_kms->secure_transition_lock);
  535. /* disable sui misr if requested, after the transition */
  536. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  537. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  538. if (ret)
  539. goto end;
  540. }
  541. end:
  542. smmu_state->transition_error = false;
  543. if (ret) {
  544. smmu_state->transition_error = true;
  545. SDE_ERROR(
  546. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  547. DRMID(crtc), old_smmu_state, smmu_state->state,
  548. smmu_state->secure_level, ret);
  549. smmu_state->state = smmu_state->prev_state;
  550. smmu_state->secure_level = smmu_state->prev_secure_level;
  551. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  552. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  553. }
  554. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  555. DRMID(crtc), old_smmu_state, smmu_state->state,
  556. smmu_state->secure_level, ret);
  557. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  558. smmu_state->transition_type,
  559. smmu_state->transition_error,
  560. smmu_state->secure_level, smmu_state->prev_secure_level,
  561. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  562. smmu_state->sui_misr_state = NONE;
  563. smmu_state->transition_type = NONE;
  564. return ret;
  565. }
  566. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  567. struct drm_atomic_state *state)
  568. {
  569. struct drm_crtc *crtc;
  570. struct drm_crtc_state *old_crtc_state;
  571. struct drm_plane_state *old_plane_state, *new_plane_state;
  572. struct drm_plane *plane;
  573. struct drm_plane_state *plane_state;
  574. struct sde_kms *sde_kms = to_sde_kms(kms);
  575. struct drm_device *dev = sde_kms->dev;
  576. int i, ops = 0, ret = 0;
  577. bool old_valid_fb = false;
  578. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  579. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  580. if (!crtc->state || !crtc->state->active)
  581. continue;
  582. /*
  583. * It is safe to assume only one active crtc,
  584. * and compatible translation modes on the
  585. * planes staged on this crtc.
  586. * otherwise validation would have failed.
  587. * For this CRTC,
  588. */
  589. /*
  590. * 1. Check if old state on the CRTC has planes
  591. * staged with valid fbs
  592. */
  593. for_each_old_plane_in_state(state, plane, plane_state, i) {
  594. if (!plane_state->crtc)
  595. continue;
  596. if (plane_state->fb) {
  597. old_valid_fb = true;
  598. break;
  599. }
  600. }
  601. /*
  602. * 2.Get the operations needed to be performed before
  603. * secure transition can be initiated.
  604. */
  605. ops = sde_crtc_get_secure_transition_ops(crtc,
  606. old_crtc_state, old_valid_fb);
  607. if (ops < 0) {
  608. SDE_ERROR("invalid secure operations %x\n", ops);
  609. return ops;
  610. }
  611. if (!ops) {
  612. smmu_state->transition_error = false;
  613. goto no_ops;
  614. }
  615. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  616. crtc->base.id, ops, crtc->state);
  617. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  618. /* 3. Perform operations needed for secure transition */
  619. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  620. SDE_DEBUG("wait_for_transfer_done\n");
  621. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  622. }
  623. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  624. SDE_DEBUG("cleanup planes\n");
  625. drm_atomic_helper_cleanup_planes(dev, state);
  626. for_each_oldnew_plane_in_state(state, plane,
  627. old_plane_state, new_plane_state, i)
  628. sde_plane_destroy_fb(old_plane_state);
  629. }
  630. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  631. SDE_DEBUG("secure ctrl\n");
  632. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  633. }
  634. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  635. SDE_DEBUG("prepare planes %d",
  636. crtc->state->plane_mask);
  637. drm_atomic_crtc_for_each_plane(plane,
  638. crtc) {
  639. const struct drm_plane_helper_funcs *funcs;
  640. plane_state = plane->state;
  641. funcs = plane->helper_private;
  642. SDE_DEBUG("psde:%d FB[%u]\n",
  643. plane->base.id,
  644. plane->fb->base.id);
  645. if (!funcs)
  646. continue;
  647. if (funcs->prepare_fb(plane, plane_state)) {
  648. ret = funcs->prepare_fb(plane,
  649. plane_state);
  650. if (ret)
  651. return ret;
  652. }
  653. }
  654. }
  655. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  656. SDE_DEBUG("secure operations completed\n");
  657. }
  658. no_ops:
  659. return 0;
  660. }
  661. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  662. unsigned int splash_buffer_size,
  663. unsigned int ramdump_base,
  664. unsigned int ramdump_buffer_size)
  665. {
  666. unsigned long pfn_start, pfn_end, pfn_idx;
  667. int ret = 0;
  668. if (!mem_addr || !splash_buffer_size) {
  669. SDE_ERROR("invalid params\n");
  670. return -EINVAL;
  671. }
  672. /* leave ramdump memory only if base address matches */
  673. if (ramdump_base == mem_addr &&
  674. ramdump_buffer_size <= splash_buffer_size) {
  675. mem_addr += ramdump_buffer_size;
  676. splash_buffer_size -= ramdump_buffer_size;
  677. }
  678. pfn_start = mem_addr >> PAGE_SHIFT;
  679. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  680. ret = memblock_free(mem_addr, splash_buffer_size);
  681. if (ret) {
  682. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  683. return ret;
  684. }
  685. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  686. free_reserved_page(pfn_to_page(pfn_idx));
  687. return ret;
  688. }
  689. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  690. struct sde_splash_mem *splash)
  691. {
  692. struct msm_mmu *mmu = NULL;
  693. int ret = 0;
  694. if (!sde_kms->aspace[0]) {
  695. SDE_ERROR("aspace not found for sde kms node\n");
  696. return -EINVAL;
  697. }
  698. mmu = sde_kms->aspace[0]->mmu;
  699. if (!mmu) {
  700. SDE_ERROR("mmu not found for aspace\n");
  701. return -EINVAL;
  702. }
  703. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  704. SDE_ERROR("invalid input params for map\n");
  705. return -EINVAL;
  706. }
  707. if (!splash->ref_cnt) {
  708. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  709. splash->splash_buf_base,
  710. splash->splash_buf_size,
  711. IOMMU_READ | IOMMU_NOEXEC);
  712. if (ret)
  713. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  714. }
  715. splash->ref_cnt++;
  716. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  717. splash->splash_buf_base,
  718. splash->splash_buf_size,
  719. splash->ref_cnt);
  720. return ret;
  721. }
  722. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  723. {
  724. int i = 0;
  725. int ret = 0;
  726. if (!sde_kms)
  727. return -EINVAL;
  728. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  729. ret = _sde_kms_splash_mem_get(sde_kms,
  730. sde_kms->splash_data.splash_display[i].splash);
  731. if (ret)
  732. return ret;
  733. }
  734. return ret;
  735. }
  736. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  737. struct sde_splash_mem *splash)
  738. {
  739. struct msm_mmu *mmu = NULL;
  740. int rc = 0;
  741. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  742. SDE_ERROR("invalid params\n");
  743. return -EINVAL;
  744. }
  745. mmu = sde_kms->aspace[0]->mmu;
  746. if (!splash || !splash->ref_cnt ||
  747. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  748. return -EINVAL;
  749. splash->ref_cnt--;
  750. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  751. splash->splash_buf_base, splash->ref_cnt);
  752. if (!splash->ref_cnt) {
  753. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  754. splash->splash_buf_size);
  755. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  756. splash->splash_buf_size, splash->ramdump_base,
  757. splash->ramdump_size);
  758. splash->splash_buf_base = 0;
  759. splash->splash_buf_size = 0;
  760. }
  761. return rc;
  762. }
  763. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  764. {
  765. int i = 0;
  766. int ret = 0;
  767. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  768. return -EINVAL;
  769. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  770. ret = _sde_kms_splash_mem_put(sde_kms,
  771. sde_kms->splash_data.splash_display[i].splash);
  772. if (ret)
  773. return ret;
  774. }
  775. return ret;
  776. }
  777. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  778. struct drm_connector_state *conn_state)
  779. {
  780. int lp_mode, blank;
  781. if (crtc_state->active)
  782. lp_mode = sde_connector_get_property(conn_state,
  783. CONNECTOR_PROP_LP);
  784. else
  785. lp_mode = SDE_MODE_DPMS_OFF;
  786. switch (lp_mode) {
  787. case SDE_MODE_DPMS_ON:
  788. blank = DRM_PANEL_BLANK_UNBLANK;
  789. break;
  790. case SDE_MODE_DPMS_LP1:
  791. case SDE_MODE_DPMS_LP2:
  792. blank = DRM_PANEL_BLANK_LP;
  793. break;
  794. case SDE_MODE_DPMS_OFF:
  795. default:
  796. blank = DRM_PANEL_BLANK_POWERDOWN;
  797. break;
  798. }
  799. return blank;
  800. }
  801. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  802. unsigned long event)
  803. {
  804. struct drm_connector *connector;
  805. struct drm_connector_state *old_conn_state;
  806. struct drm_crtc_state *old_crtc_state;
  807. struct drm_crtc *crtc;
  808. int i, old_mode, new_mode, old_fps, new_fps;
  809. for_each_old_connector_in_state(old_state, connector,
  810. old_conn_state, i) {
  811. crtc = connector->state->crtc ? connector->state->crtc :
  812. old_conn_state->crtc;
  813. if (!crtc)
  814. continue;
  815. new_fps = crtc->state->mode.vrefresh;
  816. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  817. if (old_conn_state->crtc) {
  818. old_crtc_state = drm_atomic_get_existing_crtc_state(
  819. old_state, old_conn_state->crtc);
  820. old_fps = old_crtc_state->mode.vrefresh;
  821. old_mode = _sde_kms_get_blank(old_crtc_state,
  822. old_conn_state);
  823. } else {
  824. old_fps = 0;
  825. old_mode = DRM_PANEL_BLANK_POWERDOWN;
  826. }
  827. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  828. struct drm_panel_notifier notifier_data;
  829. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  830. connector->panel, crtc->state->active,
  831. old_conn_state->crtc, event);
  832. pr_debug("change detected (power mode %d->%d, fps %d->%d)\n",
  833. old_mode, new_mode, old_fps, new_fps);
  834. /* If suspend resume and fps change are happening
  835. * at the same time, give preference to power mode
  836. * changes rather than fps change.
  837. */
  838. if ((old_mode == new_mode) && (old_fps != new_fps))
  839. new_mode = DRM_PANEL_BLANK_FPS_CHANGE;
  840. notifier_data.data = &new_mode;
  841. notifier_data.refresh_rate = new_fps;
  842. notifier_data.id = connector->base.id;
  843. if (connector->panel)
  844. drm_panel_notifier_call_chain(connector->panel,
  845. event, &notifier_data);
  846. }
  847. }
  848. }
  849. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  850. struct drm_atomic_state *state)
  851. {
  852. struct drm_device *ddev;
  853. struct drm_crtc *crtc;
  854. struct drm_encoder *encoder;
  855. struct drm_connector *connector;
  856. struct sde_vm_ops *vm_ops;
  857. struct sde_crtc_state *cstate;
  858. enum sde_crtc_vm_req vm_req;
  859. int rc = 0;
  860. ddev = sde_kms->dev;
  861. vm_ops = sde_vm_get_ops(sde_kms);
  862. if (!vm_ops)
  863. return -EINVAL;
  864. crtc = state->crtcs[0].ptr;
  865. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  866. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  867. if (vm_req != VM_REQ_ACQUIRE)
  868. return 0;
  869. /* enable MDSS irq line */
  870. sde_irq_update(&sde_kms->base, true);
  871. /* clear the stale IRQ status bits */
  872. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  873. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  874. /* enable the display path IRQ's */
  875. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  876. sde_encoder_irq_control(encoder, true);
  877. /* Schedule ESD work */
  878. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  879. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  880. sde_connector_schedule_status_work(connector, true);
  881. /* handle non-SDE pre_acquire */
  882. if (vm_ops->vm_client_post_acquire)
  883. rc = vm_ops->vm_client_post_acquire(sde_kms);
  884. return rc;
  885. }
  886. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  887. struct drm_atomic_state *state)
  888. {
  889. struct drm_device *ddev;
  890. struct drm_plane *plane;
  891. struct sde_crtc_state *cstate;
  892. enum sde_crtc_vm_req vm_req;
  893. ddev = sde_kms->dev;
  894. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  895. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  896. if (vm_req != VM_REQ_ACQUIRE)
  897. return 0;
  898. /* Clear the stale IRQ status bits */
  899. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  900. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  901. /* Program the SID's for the trusted VM */
  902. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  903. sde_plane_set_sid(plane, 1);
  904. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  905. return 0;
  906. }
  907. static void sde_kms_prepare_commit(struct msm_kms *kms,
  908. struct drm_atomic_state *state)
  909. {
  910. struct sde_kms *sde_kms;
  911. struct msm_drm_private *priv;
  912. struct drm_device *dev;
  913. struct drm_encoder *encoder;
  914. struct drm_crtc *crtc;
  915. struct drm_crtc_state *crtc_state;
  916. struct sde_vm_ops *vm_ops;
  917. int i, rc;
  918. if (!kms)
  919. return;
  920. sde_kms = to_sde_kms(kms);
  921. dev = sde_kms->dev;
  922. if (!dev || !dev->dev_private)
  923. return;
  924. priv = dev->dev_private;
  925. SDE_ATRACE_BEGIN("prepare_commit");
  926. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  927. if (rc < 0) {
  928. SDE_ERROR("failed to enable power resources %d\n", rc);
  929. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  930. goto end;
  931. }
  932. if (sde_kms->first_kickoff) {
  933. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  934. sde_kms->first_kickoff = false;
  935. }
  936. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  937. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  938. head) {
  939. if (encoder->crtc != crtc)
  940. continue;
  941. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  942. SDE_ERROR("crtc:%d, initiating hw reset\n",
  943. DRMID(crtc));
  944. sde_encoder_needs_hw_reset(encoder);
  945. sde_crtc_set_needs_hw_reset(crtc);
  946. }
  947. }
  948. }
  949. /*
  950. * NOTE: for secure use cases we want to apply the new HW
  951. * configuration only after completing preparation for secure
  952. * transitions prepare below if any transtions is required.
  953. */
  954. sde_kms_prepare_secure_transition(kms, state);
  955. vm_ops = sde_vm_get_ops(sde_kms);
  956. if (!vm_ops)
  957. goto end_vm;
  958. if (vm_ops->vm_prepare_commit)
  959. vm_ops->vm_prepare_commit(sde_kms, state);
  960. end_vm:
  961. _sde_kms_drm_check_dpms(state, DRM_PANEL_EARLY_EVENT_BLANK);
  962. end:
  963. SDE_ATRACE_END("prepare_commit");
  964. }
  965. static void sde_kms_commit(struct msm_kms *kms,
  966. struct drm_atomic_state *old_state)
  967. {
  968. struct sde_kms *sde_kms;
  969. struct drm_crtc *crtc;
  970. struct drm_crtc_state *old_crtc_state;
  971. int i;
  972. if (!kms || !old_state)
  973. return;
  974. sde_kms = to_sde_kms(kms);
  975. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  976. SDE_ERROR("power resource is not enabled\n");
  977. return;
  978. }
  979. SDE_ATRACE_BEGIN("sde_kms_commit");
  980. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  981. if (crtc->state->active) {
  982. SDE_EVT32(DRMID(crtc));
  983. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  984. }
  985. }
  986. SDE_ATRACE_END("sde_kms_commit");
  987. }
  988. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  989. struct sde_splash_display *splash_display)
  990. {
  991. if (!sde_kms || !splash_display ||
  992. !sde_kms->splash_data.num_splash_displays)
  993. return;
  994. if (sde_kms->splash_data.num_splash_regions)
  995. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  996. sde_kms->splash_data.num_splash_displays--;
  997. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  998. sde_kms->splash_data.num_splash_displays);
  999. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  1000. }
  1001. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  1002. struct drm_crtc *crtc)
  1003. {
  1004. struct msm_drm_private *priv;
  1005. struct sde_splash_display *splash_display;
  1006. int i;
  1007. if (!sde_kms || !crtc)
  1008. return;
  1009. priv = sde_kms->dev->dev_private;
  1010. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1011. return;
  1012. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1013. sde_kms->splash_data.num_splash_displays);
  1014. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1015. splash_display = &sde_kms->splash_data.splash_display[i];
  1016. if (splash_display->encoder &&
  1017. crtc == splash_display->encoder->crtc)
  1018. break;
  1019. }
  1020. if (i >= MAX_DSI_DISPLAYS)
  1021. return;
  1022. if (splash_display->cont_splash_enabled) {
  1023. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1024. splash_display, false);
  1025. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1026. }
  1027. /* remove the votes if all displays are done with splash */
  1028. if (!sde_kms->splash_data.num_splash_displays) {
  1029. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1030. sde_power_data_bus_set_quota(&priv->phandle, i,
  1031. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1032. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1033. pm_runtime_put_sync(sde_kms->dev->dev);
  1034. }
  1035. }
  1036. void _sde_kms_program_mode_info(struct sde_kms *sde_kms)
  1037. {
  1038. struct drm_encoder *encoder;
  1039. struct drm_crtc *crtc;
  1040. struct drm_connector *connector;
  1041. struct drm_connector_list_iter conn_iter;
  1042. struct dsi_display *dsi_display;
  1043. struct drm_display_mode *drm_mode;
  1044. int i;
  1045. struct drm_device *dev;
  1046. u32 mode_index = 0;
  1047. if (!sde_kms->dev || !sde_kms->hw_mdp)
  1048. return;
  1049. dev = sde_kms->dev;
  1050. sde_kms->hw_mdp->ops.clear_mode_index(sde_kms->hw_mdp);
  1051. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  1052. dsi_display = (struct dsi_display *)sde_kms->dsi_displays[i];
  1053. if (dsi_display->bridge->base.encoder) {
  1054. encoder = dsi_display->bridge->base.encoder;
  1055. crtc = encoder->crtc;
  1056. if (!crtc->state->active)
  1057. continue;
  1058. mutex_lock(&dev->mode_config.mutex);
  1059. drm_connector_list_iter_begin(dev, &conn_iter);
  1060. drm_for_each_connector_iter(connector, &conn_iter) {
  1061. if (connector->encoder_ids[0]
  1062. == encoder->base.id)
  1063. break;
  1064. }
  1065. drm_connector_list_iter_end(&conn_iter);
  1066. mutex_unlock(&dev->mode_config.mutex);
  1067. list_for_each_entry(drm_mode, &connector->modes, head) {
  1068. if (drm_mode_equal(
  1069. &crtc->state->mode, drm_mode))
  1070. break;
  1071. mode_index++;
  1072. }
  1073. sde_kms->hw_mdp->ops.set_mode_index(
  1074. sde_kms->hw_mdp, i, mode_index);
  1075. SDE_DEBUG("crtc:%d, display_idx:%d, mode_index:%d\n",
  1076. DRMID(crtc), i, mode_index);
  1077. }
  1078. }
  1079. }
  1080. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1081. struct drm_atomic_state *state)
  1082. {
  1083. struct sde_vm_ops *vm_ops;
  1084. struct drm_device *ddev;
  1085. struct drm_crtc *crtc;
  1086. struct drm_plane *plane;
  1087. struct drm_encoder *encoder;
  1088. struct sde_crtc_state *cstate;
  1089. struct drm_crtc_state *new_cstate;
  1090. enum sde_crtc_vm_req vm_req;
  1091. int rc = 0;
  1092. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1093. return -EINVAL;
  1094. vm_ops = sde_vm_get_ops(sde_kms);
  1095. ddev = sde_kms->dev;
  1096. crtc = state->crtcs[0].ptr;
  1097. new_cstate = state->crtcs[0].new_state;
  1098. cstate = to_sde_crtc_state(new_cstate);
  1099. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1100. if (vm_req != VM_REQ_RELEASE)
  1101. return rc;
  1102. if (!new_cstate->active && !new_cstate->active_changed)
  1103. return rc;
  1104. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1105. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1106. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1107. sde_encoder_irq_control(encoder, false);
  1108. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1109. sde_plane_set_sid(plane, 0);
  1110. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1111. sde_vm_lock(sde_kms);
  1112. if (vm_ops->vm_release)
  1113. rc = vm_ops->vm_release(sde_kms);
  1114. sde_vm_unlock(sde_kms);
  1115. return rc;
  1116. }
  1117. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1118. struct drm_atomic_state *state)
  1119. {
  1120. struct drm_device *ddev;
  1121. struct drm_crtc *crtc;
  1122. struct drm_encoder *encoder;
  1123. struct drm_connector *connector;
  1124. int rc = 0;
  1125. ddev = sde_kms->dev;
  1126. crtc = state->crtcs[0].ptr;
  1127. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1128. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1129. /* disable ESD work */
  1130. list_for_each_entry(connector,
  1131. &ddev->mode_config.connector_list, head) {
  1132. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1133. sde_connector_schedule_status_work(connector, false);
  1134. }
  1135. /* disable SDE irq's */
  1136. drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
  1137. sde_encoder_irq_control(encoder, false);
  1138. /* disable IRQ line */
  1139. sde_irq_update(&sde_kms->base, false);
  1140. return rc;
  1141. }
  1142. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1143. struct drm_atomic_state *state)
  1144. {
  1145. struct sde_vm_ops *vm_ops;
  1146. struct sde_crtc_state *cstate;
  1147. struct drm_crtc *crtc;
  1148. enum sde_crtc_vm_req vm_req;
  1149. int rc = 0;
  1150. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1151. return -EINVAL;
  1152. vm_ops = sde_vm_get_ops(sde_kms);
  1153. crtc = state->crtcs[0].ptr;
  1154. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  1155. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1156. if (vm_req != VM_REQ_RELEASE)
  1157. goto exit;
  1158. /* handle SDE pre-release */
  1159. sde_kms_vm_pre_release(sde_kms, state);
  1160. /* properly handoff color processing features */
  1161. sde_cp_crtc_vm_primary_handoff(crtc);
  1162. /* program the current drm mode info to scratch reg */
  1163. _sde_kms_program_mode_info(sde_kms);
  1164. /* handle non-SDE clients pre-release */
  1165. if (vm_ops->vm_client_pre_release) {
  1166. rc = vm_ops->vm_client_pre_release(sde_kms);
  1167. if (rc) {
  1168. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1169. goto exit;
  1170. }
  1171. }
  1172. sde_vm_lock(sde_kms);
  1173. /* release HW */
  1174. if (vm_ops->vm_release) {
  1175. rc = vm_ops->vm_release(sde_kms);
  1176. if (rc)
  1177. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1178. }
  1179. sde_vm_unlock(sde_kms);
  1180. exit:
  1181. return rc;
  1182. }
  1183. static void sde_kms_complete_commit(struct msm_kms *kms,
  1184. struct drm_atomic_state *old_state)
  1185. {
  1186. struct sde_kms *sde_kms;
  1187. struct msm_drm_private *priv;
  1188. struct drm_crtc *crtc;
  1189. struct drm_crtc_state *old_crtc_state;
  1190. struct drm_connector *connector;
  1191. struct drm_connector_state *old_conn_state;
  1192. struct msm_display_conn_params params;
  1193. struct sde_vm_ops *vm_ops;
  1194. int i, rc = 0;
  1195. if (!kms || !old_state)
  1196. return;
  1197. sde_kms = to_sde_kms(kms);
  1198. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1199. return;
  1200. priv = sde_kms->dev->dev_private;
  1201. if (sde_kms_power_resource_is_enabled(sde_kms->dev) < 0) {
  1202. SDE_ERROR("power resource is not enabled\n");
  1203. return;
  1204. }
  1205. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1206. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1207. sde_crtc_complete_commit(crtc, old_crtc_state);
  1208. /* complete secure transitions if any */
  1209. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1210. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1211. }
  1212. for_each_old_connector_in_state(old_state, connector,
  1213. old_conn_state, i) {
  1214. struct sde_connector *c_conn;
  1215. c_conn = to_sde_connector(connector);
  1216. if (!c_conn->ops.post_kickoff)
  1217. continue;
  1218. memset(&params, 0, sizeof(params));
  1219. sde_connector_complete_qsync_commit(connector, &params);
  1220. rc = c_conn->ops.post_kickoff(connector, &params);
  1221. if (rc) {
  1222. pr_err("Connector Post kickoff failed rc=%d\n",
  1223. rc);
  1224. }
  1225. }
  1226. vm_ops = sde_vm_get_ops(sde_kms);
  1227. if (vm_ops && vm_ops->vm_post_commit) {
  1228. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1229. if (rc)
  1230. SDE_ERROR("vm post commit failed, rc = %d\n",
  1231. rc);
  1232. }
  1233. _sde_kms_drm_check_dpms(old_state, DRM_PANEL_EVENT_BLANK);
  1234. pm_runtime_put_sync(sde_kms->dev->dev);
  1235. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1236. _sde_kms_release_splash_resource(sde_kms, crtc);
  1237. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1238. SDE_ATRACE_END("sde_kms_complete_commit");
  1239. }
  1240. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1241. struct drm_crtc *crtc)
  1242. {
  1243. struct drm_encoder *encoder;
  1244. struct drm_device *dev;
  1245. int ret;
  1246. if (!kms || !crtc || !crtc->state) {
  1247. SDE_ERROR("invalid params\n");
  1248. return;
  1249. }
  1250. dev = crtc->dev;
  1251. if (!crtc->state->enable) {
  1252. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1253. return;
  1254. }
  1255. if (!crtc->state->active) {
  1256. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1257. return;
  1258. }
  1259. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1260. SDE_ERROR("power resource is not enabled\n");
  1261. return;
  1262. }
  1263. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1264. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1265. if (encoder->crtc != crtc)
  1266. continue;
  1267. /*
  1268. * Wait for post-flush if necessary to delay before
  1269. * plane_cleanup. For example, wait for vsync in case of video
  1270. * mode panels. This may be a no-op for command mode panels.
  1271. */
  1272. SDE_EVT32_VERBOSE(DRMID(crtc));
  1273. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1274. if (ret && ret != -EWOULDBLOCK) {
  1275. SDE_ERROR("wait for commit done returned %d\n", ret);
  1276. sde_crtc_request_frame_reset(crtc);
  1277. break;
  1278. }
  1279. sde_crtc_complete_flip(crtc, NULL);
  1280. }
  1281. sde_crtc_static_cache_read_kickoff(crtc);
  1282. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1283. }
  1284. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1285. struct drm_atomic_state *old_state)
  1286. {
  1287. struct drm_crtc *crtc;
  1288. struct drm_crtc_state *old_crtc_state;
  1289. int i, rc;
  1290. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1291. SDE_ERROR("invalid argument(s)\n");
  1292. return;
  1293. }
  1294. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1295. retry:
  1296. /* attempt to acquire ww mutex for connection */
  1297. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1298. old_state->acquire_ctx);
  1299. if (rc == -EDEADLK) {
  1300. drm_modeset_backoff(old_state->acquire_ctx);
  1301. goto retry;
  1302. }
  1303. /* old_state actually contains updated crtc pointers */
  1304. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1305. if (crtc->state->active || crtc->state->active_changed)
  1306. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1307. }
  1308. SDE_ATRACE_END("sde_kms_prepare_fence");
  1309. }
  1310. /**
  1311. * _sde_kms_get_displays - query for underlying display handles and cache them
  1312. * @sde_kms: Pointer to sde kms structure
  1313. * Returns: Zero on success
  1314. */
  1315. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1316. {
  1317. int rc = -ENOMEM;
  1318. if (!sde_kms) {
  1319. SDE_ERROR("invalid sde kms\n");
  1320. return -EINVAL;
  1321. }
  1322. /* dsi */
  1323. sde_kms->dsi_displays = NULL;
  1324. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1325. if (sde_kms->dsi_display_count) {
  1326. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1327. sizeof(void *),
  1328. GFP_KERNEL);
  1329. if (!sde_kms->dsi_displays) {
  1330. SDE_ERROR("failed to allocate dsi displays\n");
  1331. goto exit_deinit_dsi;
  1332. }
  1333. sde_kms->dsi_display_count =
  1334. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1335. sde_kms->dsi_display_count);
  1336. }
  1337. /* wb */
  1338. sde_kms->wb_displays = NULL;
  1339. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1340. if (sde_kms->wb_display_count) {
  1341. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1342. sizeof(void *),
  1343. GFP_KERNEL);
  1344. if (!sde_kms->wb_displays) {
  1345. SDE_ERROR("failed to allocate wb displays\n");
  1346. goto exit_deinit_wb;
  1347. }
  1348. sde_kms->wb_display_count =
  1349. wb_display_get_displays(sde_kms->wb_displays,
  1350. sde_kms->wb_display_count);
  1351. }
  1352. /* dp */
  1353. sde_kms->dp_displays = NULL;
  1354. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1355. if (sde_kms->dp_display_count) {
  1356. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1357. sizeof(void *), GFP_KERNEL);
  1358. if (!sde_kms->dp_displays) {
  1359. SDE_ERROR("failed to allocate dp displays\n");
  1360. goto exit_deinit_dp;
  1361. }
  1362. sde_kms->dp_display_count =
  1363. dp_display_get_displays(sde_kms->dp_displays,
  1364. sde_kms->dp_display_count);
  1365. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1366. }
  1367. return 0;
  1368. exit_deinit_dp:
  1369. kfree(sde_kms->dp_displays);
  1370. sde_kms->dp_stream_count = 0;
  1371. sde_kms->dp_display_count = 0;
  1372. sde_kms->dp_displays = NULL;
  1373. exit_deinit_wb:
  1374. kfree(sde_kms->wb_displays);
  1375. sde_kms->wb_display_count = 0;
  1376. sde_kms->wb_displays = NULL;
  1377. exit_deinit_dsi:
  1378. kfree(sde_kms->dsi_displays);
  1379. sde_kms->dsi_display_count = 0;
  1380. sde_kms->dsi_displays = NULL;
  1381. return rc;
  1382. }
  1383. /**
  1384. * _sde_kms_release_displays - release cache of underlying display handles
  1385. * @sde_kms: Pointer to sde kms structure
  1386. */
  1387. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1388. {
  1389. if (!sde_kms) {
  1390. SDE_ERROR("invalid sde kms\n");
  1391. return;
  1392. }
  1393. kfree(sde_kms->wb_displays);
  1394. sde_kms->wb_displays = NULL;
  1395. sde_kms->wb_display_count = 0;
  1396. kfree(sde_kms->dsi_displays);
  1397. sde_kms->dsi_displays = NULL;
  1398. sde_kms->dsi_display_count = 0;
  1399. }
  1400. /**
  1401. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1402. * for underlying displays
  1403. * @dev: Pointer to drm device structure
  1404. * @priv: Pointer to private drm device data
  1405. * @sde_kms: Pointer to sde kms structure
  1406. * Returns: Zero on success
  1407. */
  1408. static int _sde_kms_setup_displays(struct drm_device *dev,
  1409. struct msm_drm_private *priv,
  1410. struct sde_kms *sde_kms)
  1411. {
  1412. static const struct sde_connector_ops dsi_ops = {
  1413. .set_info_blob = dsi_conn_set_info_blob,
  1414. .detect = dsi_conn_detect,
  1415. .get_modes = dsi_connector_get_modes,
  1416. .pre_destroy = dsi_connector_put_modes,
  1417. .mode_valid = dsi_conn_mode_valid,
  1418. .get_info = dsi_display_get_info,
  1419. .set_backlight = dsi_display_set_backlight,
  1420. .soft_reset = dsi_display_soft_reset,
  1421. .pre_kickoff = dsi_conn_pre_kickoff,
  1422. .clk_ctrl = dsi_display_clk_ctrl,
  1423. .set_power = dsi_display_set_power,
  1424. .get_mode_info = dsi_conn_get_mode_info,
  1425. .get_dst_format = dsi_display_get_dst_format,
  1426. .post_kickoff = dsi_conn_post_kickoff,
  1427. .check_status = dsi_display_check_status,
  1428. .enable_event = dsi_conn_enable_event,
  1429. .cmd_transfer = dsi_display_cmd_transfer,
  1430. .cont_splash_config = dsi_display_cont_splash_config,
  1431. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1432. .get_panel_vfp = dsi_display_get_panel_vfp,
  1433. .get_default_lms = dsi_display_get_default_lms,
  1434. .cmd_receive = dsi_display_cmd_receive,
  1435. .install_properties = NULL,
  1436. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1437. };
  1438. static const struct sde_connector_ops wb_ops = {
  1439. .post_init = sde_wb_connector_post_init,
  1440. .set_info_blob = sde_wb_connector_set_info_blob,
  1441. .detect = sde_wb_connector_detect,
  1442. .get_modes = sde_wb_connector_get_modes,
  1443. .set_property = sde_wb_connector_set_property,
  1444. .get_info = sde_wb_get_info,
  1445. .soft_reset = NULL,
  1446. .get_mode_info = sde_wb_get_mode_info,
  1447. .get_dst_format = NULL,
  1448. .check_status = NULL,
  1449. .cmd_transfer = NULL,
  1450. .cont_splash_config = NULL,
  1451. .cont_splash_res_disable = NULL,
  1452. .get_panel_vfp = NULL,
  1453. .cmd_receive = NULL,
  1454. .install_properties = NULL,
  1455. .set_allowed_mode_switch = NULL,
  1456. };
  1457. static const struct sde_connector_ops dp_ops = {
  1458. .post_init = dp_connector_post_init,
  1459. .detect = dp_connector_detect,
  1460. .get_modes = dp_connector_get_modes,
  1461. .atomic_check = dp_connector_atomic_check,
  1462. .mode_valid = dp_connector_mode_valid,
  1463. .get_info = dp_connector_get_info,
  1464. .get_mode_info = dp_connector_get_mode_info,
  1465. .post_open = dp_connector_post_open,
  1466. .check_status = NULL,
  1467. .set_colorspace = dp_connector_set_colorspace,
  1468. .config_hdr = dp_connector_config_hdr,
  1469. .cmd_transfer = NULL,
  1470. .cont_splash_config = NULL,
  1471. .cont_splash_res_disable = NULL,
  1472. .get_panel_vfp = NULL,
  1473. .update_pps = dp_connector_update_pps,
  1474. .cmd_receive = NULL,
  1475. .install_properties = dp_connector_install_properties,
  1476. .set_allowed_mode_switch = NULL,
  1477. };
  1478. struct msm_display_info info;
  1479. struct drm_encoder *encoder;
  1480. void *display, *connector;
  1481. int i, max_encoders;
  1482. int rc = 0;
  1483. u32 dsc_count = 0, mixer_count = 0;
  1484. u32 max_dp_dsc_count, max_dp_mixer_count;
  1485. if (!dev || !priv || !sde_kms) {
  1486. SDE_ERROR("invalid argument(s)\n");
  1487. return -EINVAL;
  1488. }
  1489. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1490. sde_kms->dp_display_count +
  1491. sde_kms->dp_stream_count;
  1492. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1493. max_encoders = ARRAY_SIZE(priv->encoders);
  1494. SDE_ERROR("capping number of displays to %d", max_encoders);
  1495. }
  1496. /* wb */
  1497. for (i = 0; i < sde_kms->wb_display_count &&
  1498. priv->num_encoders < max_encoders; ++i) {
  1499. display = sde_kms->wb_displays[i];
  1500. encoder = NULL;
  1501. memset(&info, 0x0, sizeof(info));
  1502. rc = sde_wb_get_info(NULL, &info, display);
  1503. if (rc) {
  1504. SDE_ERROR("wb get_info %d failed\n", i);
  1505. continue;
  1506. }
  1507. encoder = sde_encoder_init(dev, &info);
  1508. if (IS_ERR_OR_NULL(encoder)) {
  1509. SDE_ERROR("encoder init failed for wb %d\n", i);
  1510. continue;
  1511. }
  1512. rc = sde_wb_drm_init(display, encoder);
  1513. if (rc) {
  1514. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1515. sde_encoder_destroy(encoder);
  1516. continue;
  1517. }
  1518. connector = sde_connector_init(dev,
  1519. encoder,
  1520. 0,
  1521. display,
  1522. &wb_ops,
  1523. DRM_CONNECTOR_POLL_HPD,
  1524. DRM_MODE_CONNECTOR_VIRTUAL);
  1525. if (connector) {
  1526. priv->encoders[priv->num_encoders++] = encoder;
  1527. priv->connectors[priv->num_connectors++] = connector;
  1528. } else {
  1529. SDE_ERROR("wb %d connector init failed\n", i);
  1530. sde_wb_drm_deinit(display);
  1531. sde_encoder_destroy(encoder);
  1532. }
  1533. }
  1534. /* dsi */
  1535. for (i = 0; i < sde_kms->dsi_display_count &&
  1536. priv->num_encoders < max_encoders; ++i) {
  1537. display = sde_kms->dsi_displays[i];
  1538. encoder = NULL;
  1539. memset(&info, 0x0, sizeof(info));
  1540. rc = dsi_display_get_info(NULL, &info, display);
  1541. if (rc) {
  1542. SDE_ERROR("dsi get_info %d failed\n", i);
  1543. continue;
  1544. }
  1545. encoder = sde_encoder_init(dev, &info);
  1546. if (IS_ERR_OR_NULL(encoder)) {
  1547. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1548. continue;
  1549. }
  1550. rc = dsi_display_drm_bridge_init(display, encoder);
  1551. if (rc) {
  1552. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1553. sde_encoder_destroy(encoder);
  1554. continue;
  1555. }
  1556. connector = sde_connector_init(dev,
  1557. encoder,
  1558. dsi_display_get_drm_panel(display),
  1559. display,
  1560. &dsi_ops,
  1561. DRM_CONNECTOR_POLL_HPD,
  1562. DRM_MODE_CONNECTOR_DSI);
  1563. if (connector) {
  1564. priv->encoders[priv->num_encoders++] = encoder;
  1565. priv->connectors[priv->num_connectors++] = connector;
  1566. } else {
  1567. SDE_ERROR("dsi %d connector init failed\n", i);
  1568. dsi_display_drm_bridge_deinit(display);
  1569. sde_encoder_destroy(encoder);
  1570. continue;
  1571. }
  1572. rc = dsi_display_drm_ext_bridge_init(display,
  1573. encoder, connector);
  1574. if (rc) {
  1575. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1576. dsi_display_drm_bridge_deinit(display);
  1577. sde_connector_destroy(connector);
  1578. sde_encoder_destroy(encoder);
  1579. }
  1580. dsc_count += info.dsc_count;
  1581. mixer_count += info.lm_count;
  1582. }
  1583. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1584. sde_kms->catalog->mixer_count - mixer_count : 0;
  1585. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1586. sde_kms->catalog->dsc_count - dsc_count : 0;
  1587. /* dp */
  1588. for (i = 0; i < sde_kms->dp_display_count &&
  1589. priv->num_encoders < max_encoders; ++i) {
  1590. int idx;
  1591. display = sde_kms->dp_displays[i];
  1592. encoder = NULL;
  1593. memset(&info, 0x0, sizeof(info));
  1594. rc = dp_connector_get_info(NULL, &info, display);
  1595. if (rc) {
  1596. SDE_ERROR("dp get_info %d failed\n", i);
  1597. continue;
  1598. }
  1599. encoder = sde_encoder_init(dev, &info);
  1600. if (IS_ERR_OR_NULL(encoder)) {
  1601. SDE_ERROR("dp encoder init failed %d\n", i);
  1602. continue;
  1603. }
  1604. rc = dp_drm_bridge_init(display, encoder,
  1605. max_dp_mixer_count, max_dp_dsc_count);
  1606. if (rc) {
  1607. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1608. sde_encoder_destroy(encoder);
  1609. continue;
  1610. }
  1611. connector = sde_connector_init(dev,
  1612. encoder,
  1613. NULL,
  1614. display,
  1615. &dp_ops,
  1616. DRM_CONNECTOR_POLL_HPD,
  1617. DRM_MODE_CONNECTOR_DisplayPort);
  1618. if (connector) {
  1619. priv->encoders[priv->num_encoders++] = encoder;
  1620. priv->connectors[priv->num_connectors++] = connector;
  1621. } else {
  1622. SDE_ERROR("dp %d connector init failed\n", i);
  1623. dp_drm_bridge_deinit(display);
  1624. sde_encoder_destroy(encoder);
  1625. }
  1626. /* update display cap to MST_MODE for DP MST encoders */
  1627. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1628. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1629. priv->num_encoders < max_encoders; idx++) {
  1630. info.h_tile_instance[0] = idx;
  1631. encoder = sde_encoder_init(dev, &info);
  1632. if (IS_ERR_OR_NULL(encoder)) {
  1633. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1634. continue;
  1635. }
  1636. rc = dp_mst_drm_bridge_init(display, encoder);
  1637. if (rc) {
  1638. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1639. i, rc);
  1640. sde_encoder_destroy(encoder);
  1641. continue;
  1642. }
  1643. priv->encoders[priv->num_encoders++] = encoder;
  1644. }
  1645. }
  1646. return 0;
  1647. }
  1648. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1649. {
  1650. struct msm_drm_private *priv;
  1651. int i;
  1652. if (!sde_kms) {
  1653. SDE_ERROR("invalid sde_kms\n");
  1654. return;
  1655. } else if (!sde_kms->dev) {
  1656. SDE_ERROR("invalid dev\n");
  1657. return;
  1658. } else if (!sde_kms->dev->dev_private) {
  1659. SDE_ERROR("invalid dev_private\n");
  1660. return;
  1661. }
  1662. priv = sde_kms->dev->dev_private;
  1663. for (i = 0; i < priv->num_crtcs; i++)
  1664. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1665. priv->num_crtcs = 0;
  1666. for (i = 0; i < priv->num_planes; i++)
  1667. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1668. priv->num_planes = 0;
  1669. for (i = 0; i < priv->num_connectors; i++)
  1670. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1671. priv->num_connectors = 0;
  1672. for (i = 0; i < priv->num_encoders; i++)
  1673. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1674. priv->num_encoders = 0;
  1675. _sde_kms_release_displays(sde_kms);
  1676. }
  1677. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1678. {
  1679. struct drm_device *dev;
  1680. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1681. struct drm_crtc *crtc;
  1682. struct msm_drm_private *priv;
  1683. struct sde_mdss_cfg *catalog;
  1684. int primary_planes_idx = 0, i, ret;
  1685. int max_crtc_count;
  1686. u32 sspp_id[MAX_PLANES];
  1687. u32 master_plane_id[MAX_PLANES];
  1688. u32 num_virt_planes = 0;
  1689. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1690. SDE_ERROR("invalid sde_kms\n");
  1691. return -EINVAL;
  1692. }
  1693. dev = sde_kms->dev;
  1694. priv = dev->dev_private;
  1695. catalog = sde_kms->catalog;
  1696. ret = sde_core_irq_domain_add(sde_kms);
  1697. if (ret)
  1698. goto fail_irq;
  1699. /*
  1700. * Query for underlying display drivers, and create connectors,
  1701. * bridges and encoders for them.
  1702. */
  1703. if (!_sde_kms_get_displays(sde_kms))
  1704. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1705. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1706. /* Create the planes */
  1707. for (i = 0; i < catalog->sspp_count; i++) {
  1708. bool primary = true;
  1709. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1710. || primary_planes_idx >= max_crtc_count)
  1711. primary = false;
  1712. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1713. (1UL << max_crtc_count) - 1, 0);
  1714. if (IS_ERR(plane)) {
  1715. SDE_ERROR("sde_plane_init failed\n");
  1716. ret = PTR_ERR(plane);
  1717. goto fail;
  1718. }
  1719. priv->planes[priv->num_planes++] = plane;
  1720. if (primary)
  1721. primary_planes[primary_planes_idx++] = plane;
  1722. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1723. sde_is_custom_client()) {
  1724. int priority =
  1725. catalog->sspp[i].sblk->smart_dma_priority;
  1726. sspp_id[priority - 1] = catalog->sspp[i].id;
  1727. master_plane_id[priority - 1] = plane->base.id;
  1728. num_virt_planes++;
  1729. }
  1730. }
  1731. /* Initialize smart DMA virtual planes */
  1732. for (i = 0; i < num_virt_planes; i++) {
  1733. plane = sde_plane_init(dev, sspp_id[i], false,
  1734. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1735. if (IS_ERR(plane)) {
  1736. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1737. ret = PTR_ERR(plane);
  1738. goto fail;
  1739. }
  1740. priv->planes[priv->num_planes++] = plane;
  1741. }
  1742. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1743. /* Create one CRTC per encoder */
  1744. for (i = 0; i < max_crtc_count; i++) {
  1745. crtc = sde_crtc_init(dev, primary_planes[i]);
  1746. if (IS_ERR(crtc)) {
  1747. ret = PTR_ERR(crtc);
  1748. goto fail;
  1749. }
  1750. priv->crtcs[priv->num_crtcs++] = crtc;
  1751. }
  1752. if (sde_is_custom_client()) {
  1753. /* All CRTCs are compatible with all planes */
  1754. for (i = 0; i < priv->num_planes; i++)
  1755. priv->planes[i]->possible_crtcs =
  1756. (1 << priv->num_crtcs) - 1;
  1757. }
  1758. /* All CRTCs are compatible with all encoders */
  1759. for (i = 0; i < priv->num_encoders; i++)
  1760. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1761. return 0;
  1762. fail:
  1763. _sde_kms_drm_obj_destroy(sde_kms);
  1764. fail_irq:
  1765. sde_core_irq_domain_fini(sde_kms);
  1766. return ret;
  1767. }
  1768. /**
  1769. * sde_kms_timeline_status - provides current timeline status
  1770. * This API should be called without mode config lock.
  1771. * @dev: Pointer to drm device
  1772. */
  1773. void sde_kms_timeline_status(struct drm_device *dev)
  1774. {
  1775. struct drm_crtc *crtc;
  1776. struct drm_connector *conn;
  1777. struct drm_connector_list_iter conn_iter;
  1778. if (!dev) {
  1779. SDE_ERROR("invalid drm device node\n");
  1780. return;
  1781. }
  1782. drm_for_each_crtc(crtc, dev)
  1783. sde_crtc_timeline_status(crtc);
  1784. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1785. /*
  1786. *Probably locked from last close dumping status anyway
  1787. */
  1788. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1789. drm_connector_list_iter_begin(dev, &conn_iter);
  1790. drm_for_each_connector_iter(conn, &conn_iter)
  1791. sde_conn_timeline_status(conn);
  1792. drm_connector_list_iter_end(&conn_iter);
  1793. return;
  1794. }
  1795. mutex_lock(&dev->mode_config.mutex);
  1796. drm_connector_list_iter_begin(dev, &conn_iter);
  1797. drm_for_each_connector_iter(conn, &conn_iter)
  1798. sde_conn_timeline_status(conn);
  1799. drm_connector_list_iter_end(&conn_iter);
  1800. mutex_unlock(&dev->mode_config.mutex);
  1801. }
  1802. static int sde_kms_postinit(struct msm_kms *kms)
  1803. {
  1804. struct sde_kms *sde_kms = to_sde_kms(kms);
  1805. struct drm_device *dev;
  1806. struct drm_crtc *crtc;
  1807. int rc;
  1808. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1809. SDE_ERROR("invalid sde_kms\n");
  1810. return -EINVAL;
  1811. }
  1812. dev = sde_kms->dev;
  1813. rc = _sde_debugfs_init(sde_kms);
  1814. if (rc)
  1815. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1816. drm_for_each_crtc(crtc, dev)
  1817. sde_crtc_post_init(dev, crtc);
  1818. return rc;
  1819. }
  1820. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1821. struct drm_encoder *encoder)
  1822. {
  1823. return rate;
  1824. }
  1825. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1826. struct platform_device *pdev)
  1827. {
  1828. struct drm_device *dev;
  1829. struct msm_drm_private *priv;
  1830. struct sde_vm_ops *vm_ops;
  1831. int i;
  1832. if (!sde_kms || !pdev)
  1833. return;
  1834. dev = sde_kms->dev;
  1835. if (!dev)
  1836. return;
  1837. priv = dev->dev_private;
  1838. if (!priv)
  1839. return;
  1840. if (sde_kms->genpd_init) {
  1841. sde_kms->genpd_init = false;
  1842. pm_genpd_remove(&sde_kms->genpd);
  1843. of_genpd_del_provider(pdev->dev.of_node);
  1844. }
  1845. vm_ops = sde_vm_get_ops(sde_kms);
  1846. if (vm_ops && vm_ops->vm_deinit)
  1847. vm_ops->vm_deinit(sde_kms, vm_ops);
  1848. if (sde_kms->hw_intr)
  1849. sde_hw_intr_destroy(sde_kms->hw_intr);
  1850. sde_kms->hw_intr = NULL;
  1851. if (sde_kms->power_event)
  1852. sde_power_handle_unregister_event(
  1853. &priv->phandle, sde_kms->power_event);
  1854. _sde_kms_release_displays(sde_kms);
  1855. _sde_kms_unmap_all_splash_regions(sde_kms);
  1856. if (sde_kms->catalog) {
  1857. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1858. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1859. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1860. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1861. }
  1862. }
  1863. if (sde_kms->rm_init)
  1864. sde_rm_destroy(&sde_kms->rm);
  1865. sde_kms->rm_init = false;
  1866. if (sde_kms->catalog)
  1867. sde_hw_catalog_deinit(sde_kms->catalog);
  1868. sde_kms->catalog = NULL;
  1869. if (sde_kms->sid)
  1870. msm_iounmap(pdev, sde_kms->sid);
  1871. sde_kms->sid = NULL;
  1872. if (sde_kms->reg_dma)
  1873. msm_iounmap(pdev, sde_kms->reg_dma);
  1874. sde_kms->reg_dma = NULL;
  1875. if (sde_kms->vbif[VBIF_NRT])
  1876. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1877. sde_kms->vbif[VBIF_NRT] = NULL;
  1878. if (sde_kms->vbif[VBIF_RT])
  1879. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1880. sde_kms->vbif[VBIF_RT] = NULL;
  1881. if (sde_kms->mmio)
  1882. msm_iounmap(pdev, sde_kms->mmio);
  1883. sde_kms->mmio = NULL;
  1884. sde_reg_dma_deinit();
  1885. _sde_kms_mmu_destroy(sde_kms);
  1886. }
  1887. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1888. {
  1889. int i;
  1890. if (!sde_kms)
  1891. return -EINVAL;
  1892. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1893. struct msm_mmu *mmu;
  1894. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1895. if (!aspace)
  1896. continue;
  1897. mmu = sde_kms->aspace[i]->mmu;
  1898. if (secure_only &&
  1899. !aspace->mmu->funcs->is_domain_secure(mmu))
  1900. continue;
  1901. /* cleanup aspace before detaching */
  1902. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1903. SDE_DEBUG("Detaching domain:%d\n", i);
  1904. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1905. ARRAY_SIZE(iommu_ports));
  1906. aspace->domain_attached = false;
  1907. }
  1908. return 0;
  1909. }
  1910. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1911. {
  1912. int i;
  1913. if (!sde_kms)
  1914. return -EINVAL;
  1915. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1916. struct msm_mmu *mmu;
  1917. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1918. if (!aspace)
  1919. continue;
  1920. mmu = sde_kms->aspace[i]->mmu;
  1921. if (secure_only &&
  1922. !aspace->mmu->funcs->is_domain_secure(mmu))
  1923. continue;
  1924. SDE_DEBUG("Attaching domain:%d\n", i);
  1925. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1926. ARRAY_SIZE(iommu_ports));
  1927. aspace->domain_attached = true;
  1928. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1929. }
  1930. return 0;
  1931. }
  1932. static void sde_kms_destroy(struct msm_kms *kms)
  1933. {
  1934. struct sde_kms *sde_kms;
  1935. struct drm_device *dev;
  1936. if (!kms) {
  1937. SDE_ERROR("invalid kms\n");
  1938. return;
  1939. }
  1940. sde_kms = to_sde_kms(kms);
  1941. dev = sde_kms->dev;
  1942. if (!dev || !dev->dev) {
  1943. SDE_ERROR("invalid device\n");
  1944. return;
  1945. }
  1946. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1947. kfree(sde_kms);
  1948. }
  1949. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1950. struct drm_atomic_state *state)
  1951. {
  1952. struct drm_device *dev = sde_kms->dev;
  1953. struct drm_plane *plane;
  1954. struct drm_plane_state *plane_state;
  1955. struct drm_crtc *crtc;
  1956. struct drm_crtc_state *crtc_state;
  1957. struct drm_connector *conn;
  1958. struct drm_connector_state *conn_state;
  1959. struct drm_connector_list_iter conn_iter;
  1960. int ret = 0;
  1961. drm_for_each_plane(plane, dev) {
  1962. plane_state = drm_atomic_get_plane_state(state, plane);
  1963. if (IS_ERR(plane_state)) {
  1964. ret = PTR_ERR(plane_state);
  1965. SDE_ERROR("error %d getting plane %d state\n",
  1966. ret, DRMID(plane));
  1967. return ret;
  1968. }
  1969. ret = sde_plane_helper_reset_custom_properties(plane,
  1970. plane_state);
  1971. if (ret) {
  1972. SDE_ERROR("error %d resetting plane props %d\n",
  1973. ret, DRMID(plane));
  1974. return ret;
  1975. }
  1976. }
  1977. drm_for_each_crtc(crtc, dev) {
  1978. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1979. if (IS_ERR(crtc_state)) {
  1980. ret = PTR_ERR(crtc_state);
  1981. SDE_ERROR("error %d getting crtc %d state\n",
  1982. ret, DRMID(crtc));
  1983. return ret;
  1984. }
  1985. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1986. if (ret) {
  1987. SDE_ERROR("error %d resetting crtc props %d\n",
  1988. ret, DRMID(crtc));
  1989. return ret;
  1990. }
  1991. }
  1992. drm_connector_list_iter_begin(dev, &conn_iter);
  1993. drm_for_each_connector_iter(conn, &conn_iter) {
  1994. conn_state = drm_atomic_get_connector_state(state, conn);
  1995. if (IS_ERR(conn_state)) {
  1996. ret = PTR_ERR(conn_state);
  1997. SDE_ERROR("error %d getting connector %d state\n",
  1998. ret, DRMID(conn));
  1999. return ret;
  2000. }
  2001. ret = sde_connector_helper_reset_custom_properties(conn,
  2002. conn_state);
  2003. if (ret) {
  2004. SDE_ERROR("error %d resetting connector props %d\n",
  2005. ret, DRMID(conn));
  2006. return ret;
  2007. }
  2008. }
  2009. drm_connector_list_iter_end(&conn_iter);
  2010. return ret;
  2011. }
  2012. static void sde_kms_lastclose(struct msm_kms *kms)
  2013. {
  2014. struct sde_kms *sde_kms;
  2015. struct drm_device *dev;
  2016. struct drm_atomic_state *state;
  2017. struct drm_modeset_acquire_ctx ctx;
  2018. int ret;
  2019. if (!kms) {
  2020. SDE_ERROR("invalid argument\n");
  2021. return;
  2022. }
  2023. sde_kms = to_sde_kms(kms);
  2024. dev = sde_kms->dev;
  2025. drm_modeset_acquire_init(&ctx, 0);
  2026. state = drm_atomic_state_alloc(dev);
  2027. if (!state) {
  2028. ret = -ENOMEM;
  2029. goto out_ctx;
  2030. }
  2031. state->acquire_ctx = &ctx;
  2032. retry:
  2033. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2034. if (ret)
  2035. goto out_state;
  2036. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2037. if (ret)
  2038. goto out_state;
  2039. ret = drm_atomic_commit(state);
  2040. out_state:
  2041. if (ret == -EDEADLK)
  2042. goto backoff;
  2043. drm_atomic_state_put(state);
  2044. out_ctx:
  2045. drm_modeset_drop_locks(&ctx);
  2046. drm_modeset_acquire_fini(&ctx);
  2047. if (ret)
  2048. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2049. return;
  2050. backoff:
  2051. drm_atomic_state_clear(state);
  2052. drm_modeset_backoff(&ctx);
  2053. goto retry;
  2054. }
  2055. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2056. struct drm_atomic_state *state)
  2057. {
  2058. struct sde_kms *sde_kms;
  2059. struct drm_device *dev;
  2060. struct drm_crtc *crtc;
  2061. struct drm_crtc_state *new_cstate, *old_cstate;
  2062. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2063. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  2064. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2065. struct sde_vm_ops *vm_ops;
  2066. bool vm_req_active = false;
  2067. enum sde_crtc_idle_pc_state idle_pc_state;
  2068. int rc = 0;
  2069. if (!kms || !state)
  2070. return -EINVAL;
  2071. sde_kms = to_sde_kms(kms);
  2072. dev = sde_kms->dev;
  2073. vm_ops = sde_vm_get_ops(sde_kms);
  2074. if (!vm_ops)
  2075. return 0;
  2076. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2077. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2078. new_state = to_sde_crtc_state(new_cstate);
  2079. if (!new_cstate->active && !new_cstate->active_changed)
  2080. continue;
  2081. new_vm_req = sde_crtc_get_property(new_state,
  2082. CRTC_PROP_VM_REQ_STATE);
  2083. commit_crtc_cnt++;
  2084. if (old_cstate) {
  2085. old_state = to_sde_crtc_state(old_cstate);
  2086. old_vm_req = sde_crtc_get_property(old_state,
  2087. CRTC_PROP_VM_REQ_STATE);
  2088. }
  2089. /**
  2090. * No active request if the transition is from
  2091. * VM_REQ_NONE to VM_REQ_NONE
  2092. */
  2093. if (new_vm_req || (old_state && old_vm_req))
  2094. vm_req_active = true;
  2095. idle_pc_state = sde_crtc_get_property(new_state,
  2096. CRTC_PROP_IDLE_PC_STATE);
  2097. active_crtc = crtc;
  2098. }
  2099. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2100. if (!crtc->state->active)
  2101. continue;
  2102. global_crtc_cnt++;
  2103. global_active_crtc = crtc;
  2104. }
  2105. /* Check for single crtc commits only on valid VM requests */
  2106. if (vm_req_active && active_crtc && global_active_crtc &&
  2107. (commit_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2108. global_crtc_cnt > sde_kms->catalog->max_trusted_vm_displays ||
  2109. active_crtc != global_active_crtc)) {
  2110. SDE_ERROR(
  2111. "failed to switch VM due to CRTC concurrencies: MAX_CNT: %d active_cnt: %d global_cnt: %d active_crtc: %d global_crtc: %d\n",
  2112. sde_kms->catalog->max_trusted_vm_displays,
  2113. commit_crtc_cnt, global_crtc_cnt, active_crtc,
  2114. global_active_crtc);
  2115. return -E2BIG;
  2116. }
  2117. if (!vm_req_active)
  2118. return 0;
  2119. /* disable idle-pc before releasing the HW */
  2120. if ((new_vm_req == VM_REQ_RELEASE) &&
  2121. (idle_pc_state == IDLE_PC_ENABLE)) {
  2122. SDE_ERROR("failed to switch VM since idle-pc is enabled\n");
  2123. return -EINVAL;
  2124. }
  2125. sde_vm_lock(sde_kms);
  2126. if (vm_ops->vm_request_valid)
  2127. rc = vm_ops->vm_request_valid(sde_kms, old_vm_req, new_vm_req);
  2128. if (rc)
  2129. SDE_ERROR(
  2130. "failed to complete vm transition request. old_state = %d, new_state = %d, hw_ownership: %d\n",
  2131. old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2132. sde_vm_unlock(sde_kms);
  2133. return rc;
  2134. }
  2135. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2136. struct drm_atomic_state *state)
  2137. {
  2138. struct sde_kms *sde_kms;
  2139. struct drm_device *dev;
  2140. struct drm_crtc *crtc;
  2141. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2142. struct drm_crtc_state *crtc_state;
  2143. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2144. bool sec_session = false, global_sec_session = false;
  2145. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2146. int i;
  2147. if (!kms || !state) {
  2148. return -EINVAL;
  2149. SDE_ERROR("invalid arguments\n");
  2150. }
  2151. sde_kms = to_sde_kms(kms);
  2152. dev = sde_kms->dev;
  2153. /* iterate state object for active secure/non-secure crtc */
  2154. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2155. if (!crtc_state->active)
  2156. continue;
  2157. active_crtc_cnt++;
  2158. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2159. &fb_sec, &fb_sec_dir);
  2160. if (fb_sec_dir)
  2161. sec_session = true;
  2162. cur_crtc = crtc;
  2163. }
  2164. /* iterate global list for active and secure/non-secure crtc */
  2165. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2166. if (!crtc->state->active)
  2167. continue;
  2168. global_active_crtc_cnt++;
  2169. /* update only when crtc is not the same as current crtc */
  2170. if (crtc != cur_crtc) {
  2171. fb_ns = fb_sec = fb_sec_dir = 0;
  2172. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2173. &fb_sec, &fb_sec_dir);
  2174. if (fb_sec_dir)
  2175. global_sec_session = true;
  2176. global_crtc = crtc;
  2177. }
  2178. }
  2179. if (!global_sec_session && !sec_session)
  2180. return 0;
  2181. /*
  2182. * - fail crtc commit, if secure-camera/secure-ui session is
  2183. * in-progress in any other display
  2184. * - fail secure-camera/secure-ui crtc commit, if any other display
  2185. * session is in-progress
  2186. */
  2187. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2188. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2189. SDE_ERROR(
  2190. "crtc%d secure check failed global_active:%d active:%d\n",
  2191. cur_crtc ? cur_crtc->base.id : -1,
  2192. global_active_crtc_cnt, active_crtc_cnt);
  2193. return -EPERM;
  2194. /*
  2195. * As only one crtc is allowed during secure session, the crtc
  2196. * in this commit should match with the global crtc
  2197. */
  2198. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2199. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2200. cur_crtc->base.id, sec_session,
  2201. global_crtc->base.id, global_sec_session);
  2202. return -EPERM;
  2203. }
  2204. return 0;
  2205. }
  2206. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2207. struct drm_atomic_state *state)
  2208. {
  2209. struct drm_crtc *crtc;
  2210. struct drm_crtc_state *crtc_state;
  2211. struct sde_vm_ops *vm_ops;
  2212. enum sde_crtc_vm_req vm_req;
  2213. struct sde_kms *sde_kms = to_sde_kms(kms);
  2214. int i;
  2215. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2216. struct sde_crtc_state *cstate;
  2217. cstate = to_sde_crtc_state(state->crtcs[0].new_state);
  2218. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2219. if (vm_req != VM_REQ_ACQUIRE)
  2220. return;
  2221. }
  2222. vm_ops = sde_vm_get_ops(sde_kms);
  2223. if (!vm_ops)
  2224. return;
  2225. sde_vm_lock(sde_kms);
  2226. if (vm_ops->vm_acquire_fail_handler)
  2227. vm_ops->vm_acquire_fail_handler(sde_kms);
  2228. sde_vm_unlock(sde_kms);
  2229. }
  2230. static int sde_kms_atomic_check(struct msm_kms *kms,
  2231. struct drm_atomic_state *state)
  2232. {
  2233. struct sde_kms *sde_kms;
  2234. struct drm_device *dev;
  2235. int ret;
  2236. if (!kms || !state)
  2237. return -EINVAL;
  2238. sde_kms = to_sde_kms(kms);
  2239. dev = sde_kms->dev;
  2240. SDE_ATRACE_BEGIN("atomic_check");
  2241. if (sde_kms_is_suspend_blocked(dev)) {
  2242. SDE_DEBUG("suspended, skip atomic_check\n");
  2243. ret = -EBUSY;
  2244. goto end;
  2245. }
  2246. ret = sde_kms_check_vm_request(kms, state);
  2247. if (ret) {
  2248. SDE_ERROR("vm switch request checks failed\n");
  2249. goto end;
  2250. }
  2251. ret = drm_atomic_helper_check(dev, state);
  2252. if (ret)
  2253. goto vm_clean_up;
  2254. /*
  2255. * Check if any secure transition(moving CRTC between secure and
  2256. * non-secure state and vice-versa) is allowed or not. when moving
  2257. * to secure state, planes with fb_mode set to dir_translated only can
  2258. * be staged on the CRTC, and only one CRTC can be active during
  2259. * Secure state
  2260. */
  2261. ret = sde_kms_check_secure_transition(kms, state);
  2262. if (ret)
  2263. goto vm_clean_up;
  2264. goto end;
  2265. vm_clean_up:
  2266. sde_kms_vm_res_release(kms, state);
  2267. end:
  2268. SDE_ATRACE_END("atomic_check");
  2269. return ret;
  2270. }
  2271. static struct msm_gem_address_space*
  2272. _sde_kms_get_address_space(struct msm_kms *kms,
  2273. unsigned int domain)
  2274. {
  2275. struct sde_kms *sde_kms;
  2276. if (!kms) {
  2277. SDE_ERROR("invalid kms\n");
  2278. return NULL;
  2279. }
  2280. sde_kms = to_sde_kms(kms);
  2281. if (!sde_kms) {
  2282. SDE_ERROR("invalid sde_kms\n");
  2283. return NULL;
  2284. }
  2285. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2286. return NULL;
  2287. return (sde_kms->aspace[domain] &&
  2288. sde_kms->aspace[domain]->domain_attached) ?
  2289. sde_kms->aspace[domain] : NULL;
  2290. }
  2291. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2292. unsigned int domain)
  2293. {
  2294. struct sde_kms *sde_kms;
  2295. struct msm_gem_address_space *aspace;
  2296. if (!kms) {
  2297. SDE_ERROR("invalid kms\n");
  2298. return NULL;
  2299. }
  2300. sde_kms = to_sde_kms(kms);
  2301. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2302. SDE_ERROR("invalid params\n");
  2303. return NULL;
  2304. }
  2305. aspace = _sde_kms_get_address_space(kms, domain);
  2306. return (aspace && aspace->domain_attached) ?
  2307. msm_gem_get_aspace_device(aspace) : NULL;
  2308. }
  2309. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2310. {
  2311. struct drm_device *dev = NULL;
  2312. struct sde_kms *sde_kms = NULL;
  2313. struct drm_connector *connector = NULL;
  2314. struct drm_connector_list_iter conn_iter;
  2315. struct sde_connector *sde_conn = NULL;
  2316. if (!kms) {
  2317. SDE_ERROR("invalid kms\n");
  2318. return;
  2319. }
  2320. sde_kms = to_sde_kms(kms);
  2321. dev = sde_kms->dev;
  2322. if (!dev) {
  2323. SDE_ERROR("invalid device\n");
  2324. return;
  2325. }
  2326. if (!dev->mode_config.poll_enabled)
  2327. return;
  2328. mutex_lock(&dev->mode_config.mutex);
  2329. drm_connector_list_iter_begin(dev, &conn_iter);
  2330. drm_for_each_connector_iter(connector, &conn_iter) {
  2331. /* Only handle HPD capable connectors. */
  2332. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2333. continue;
  2334. sde_conn = to_sde_connector(connector);
  2335. if (sde_conn->ops.post_open)
  2336. sde_conn->ops.post_open(&sde_conn->base,
  2337. sde_conn->display);
  2338. }
  2339. drm_connector_list_iter_end(&conn_iter);
  2340. mutex_unlock(&dev->mode_config.mutex);
  2341. }
  2342. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2343. struct sde_splash_display *splash_display,
  2344. struct drm_crtc *crtc)
  2345. {
  2346. struct msm_drm_private *priv;
  2347. struct drm_plane *plane;
  2348. struct sde_splash_mem *splash;
  2349. enum sde_sspp plane_id;
  2350. bool is_virtual;
  2351. int i, j;
  2352. if (!sde_kms || !splash_display || !crtc) {
  2353. SDE_ERROR("invalid input args\n");
  2354. return -EINVAL;
  2355. }
  2356. priv = sde_kms->dev->dev_private;
  2357. for (i = 0; i < priv->num_planes; i++) {
  2358. plane = priv->planes[i];
  2359. plane_id = sde_plane_pipe(plane);
  2360. is_virtual = is_sde_plane_virtual(plane);
  2361. splash = splash_display->splash;
  2362. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2363. if ((plane_id != splash_display->pipes[j].sspp) ||
  2364. (splash_display->pipes[j].is_virtual
  2365. != is_virtual))
  2366. continue;
  2367. if (splash && sde_plane_validate_src_addr(plane,
  2368. splash->splash_buf_base,
  2369. splash->splash_buf_size)) {
  2370. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2371. plane_id, crtc->base.id);
  2372. }
  2373. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2374. crtc->base.id, plane_id, is_virtual);
  2375. }
  2376. }
  2377. return 0;
  2378. }
  2379. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2380. struct sde_kms *sde_kms, struct drm_connector *connector,
  2381. u32 display_idx)
  2382. {
  2383. struct drm_display_mode *drm_mode = NULL, *curr_mode = NULL;
  2384. u32 i = 0, mode_index;
  2385. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2386. /* currently consider modes[0] as the preferred mode */
  2387. curr_mode = list_first_entry(&connector->modes,
  2388. struct drm_display_mode, head);
  2389. } else if (sde_kms->hw_mdp && sde_kms->hw_mdp->ops.get_mode_index) {
  2390. mode_index = sde_kms->hw_mdp->ops.get_mode_index(
  2391. sde_kms->hw_mdp, display_idx);
  2392. list_for_each_entry(drm_mode, &connector->modes, head) {
  2393. if (mode_index == i) {
  2394. curr_mode = drm_mode;
  2395. break;
  2396. }
  2397. i++;
  2398. }
  2399. }
  2400. return curr_mode;
  2401. }
  2402. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2403. struct dsi_display *dsi_display)
  2404. {
  2405. void *display;
  2406. struct drm_encoder *encoder = NULL;
  2407. struct msm_display_info info;
  2408. struct drm_device *dev;
  2409. struct sde_kms *sde_kms;
  2410. struct drm_connector_list_iter conn_iter;
  2411. struct drm_connector *connector = NULL;
  2412. struct sde_connector *sde_conn = NULL;
  2413. int rc = 0;
  2414. sde_kms = to_sde_kms(kms);
  2415. dev = sde_kms->dev;
  2416. display = dsi_display;
  2417. if (dsi_display) {
  2418. if (dsi_display->bridge->base.encoder) {
  2419. encoder = dsi_display->bridge->base.encoder;
  2420. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2421. }
  2422. memset(&info, 0x0, sizeof(info));
  2423. rc = dsi_display_get_info(NULL, &info, display);
  2424. if (rc) {
  2425. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2426. rc, __func__);
  2427. encoder = NULL;
  2428. }
  2429. }
  2430. drm_connector_list_iter_begin(dev, &conn_iter);
  2431. drm_for_each_connector_iter(connector, &conn_iter) {
  2432. /**
  2433. * Inform cont_splash is disabled to each interface/connector.
  2434. * This is currently supported for DSI interface.
  2435. */
  2436. sde_conn = to_sde_connector(connector);
  2437. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2438. if (!dsi_display || !encoder) {
  2439. sde_conn->ops.cont_splash_res_disable
  2440. (sde_conn->display);
  2441. } else if (connector->encoder_ids[0]
  2442. == encoder->base.id) {
  2443. /**
  2444. * This handles dual DSI
  2445. * configuration where one DSI
  2446. * interface has cont_splash
  2447. * enabled and the other doesn't.
  2448. */
  2449. sde_conn->ops.cont_splash_res_disable
  2450. (sde_conn->display);
  2451. break;
  2452. }
  2453. }
  2454. }
  2455. drm_connector_list_iter_end(&conn_iter);
  2456. return 0;
  2457. }
  2458. static int sde_kms_cont_splash_config(struct msm_kms *kms)
  2459. {
  2460. void *display;
  2461. struct dsi_display *dsi_display;
  2462. struct msm_display_info info;
  2463. struct drm_encoder *encoder = NULL;
  2464. struct drm_crtc *crtc = NULL;
  2465. int i, rc = 0;
  2466. struct drm_display_mode *drm_mode = NULL;
  2467. struct drm_device *dev;
  2468. struct msm_drm_private *priv;
  2469. struct sde_kms *sde_kms;
  2470. struct drm_connector_list_iter conn_iter;
  2471. struct drm_connector *connector = NULL;
  2472. struct sde_connector *sde_conn = NULL;
  2473. struct sde_splash_display *splash_display;
  2474. if (!kms) {
  2475. SDE_ERROR("invalid kms\n");
  2476. return -EINVAL;
  2477. }
  2478. sde_kms = to_sde_kms(kms);
  2479. dev = sde_kms->dev;
  2480. if (!dev) {
  2481. SDE_ERROR("invalid device\n");
  2482. return -EINVAL;
  2483. }
  2484. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2485. && (!sde_kms->splash_data.num_splash_regions)) ||
  2486. !sde_kms->splash_data.num_splash_displays) {
  2487. DRM_INFO("cont_splash feature not enabled\n");
  2488. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2489. return rc;
  2490. }
  2491. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2492. sde_kms->splash_data.num_splash_displays,
  2493. sde_kms->dsi_display_count);
  2494. /* dsi */
  2495. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2496. display = sde_kms->dsi_displays[i];
  2497. dsi_display = (struct dsi_display *)display;
  2498. splash_display = &sde_kms->splash_data.splash_display[i];
  2499. if (!splash_display->cont_splash_enabled) {
  2500. SDE_DEBUG("display->name = %s splash not enabled\n",
  2501. dsi_display->name);
  2502. sde_kms_inform_cont_splash_res_disable(kms,
  2503. dsi_display);
  2504. continue;
  2505. }
  2506. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2507. if (dsi_display->bridge->base.encoder) {
  2508. encoder = dsi_display->bridge->base.encoder;
  2509. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2510. }
  2511. memset(&info, 0x0, sizeof(info));
  2512. rc = dsi_display_get_info(NULL, &info, display);
  2513. if (rc) {
  2514. SDE_ERROR("dsi get_info %d failed\n", i);
  2515. encoder = NULL;
  2516. continue;
  2517. }
  2518. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2519. ((info.is_connected) ? "true" : "false"),
  2520. info.display_type);
  2521. if (!encoder) {
  2522. SDE_ERROR("encoder not initialized\n");
  2523. return -EINVAL;
  2524. }
  2525. priv = sde_kms->dev->dev_private;
  2526. encoder->crtc = priv->crtcs[i];
  2527. crtc = encoder->crtc;
  2528. splash_display->encoder = encoder;
  2529. SDE_DEBUG("for dsi-display:%d crtc id = %d enc id =%d\n",
  2530. i, crtc->base.id, encoder->base.id);
  2531. mutex_lock(&dev->mode_config.mutex);
  2532. drm_connector_list_iter_begin(dev, &conn_iter);
  2533. drm_for_each_connector_iter(connector, &conn_iter) {
  2534. /**
  2535. * SDE_KMS doesn't attach more than one encoder to
  2536. * a DSI connector. So it is safe to check only with
  2537. * the first encoder entry. Revisit this logic if we
  2538. * ever have to support continuous splash for
  2539. * external displays in MST configuration.
  2540. */
  2541. if (connector->encoder_ids[0] == encoder->base.id)
  2542. break;
  2543. }
  2544. drm_connector_list_iter_end(&conn_iter);
  2545. if (!connector) {
  2546. SDE_ERROR("connector not initialized\n");
  2547. mutex_unlock(&dev->mode_config.mutex);
  2548. return -EINVAL;
  2549. }
  2550. if (connector->funcs->fill_modes) {
  2551. connector->funcs->fill_modes(connector,
  2552. dev->mode_config.max_width,
  2553. dev->mode_config.max_height);
  2554. } else {
  2555. SDE_ERROR("fill_modes api not defined\n");
  2556. mutex_unlock(&dev->mode_config.mutex);
  2557. return -EINVAL;
  2558. }
  2559. mutex_unlock(&dev->mode_config.mutex);
  2560. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2561. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, i);
  2562. if (!drm_mode) {
  2563. SDE_ERROR("invalid drm-mode type:%d, index:%d\n",
  2564. sde_kms->splash_data.type, i);
  2565. return -EINVAL;
  2566. }
  2567. SDE_DEBUG("drm_mode->name = %s, type=0x%x, flags=0x%x\n",
  2568. drm_mode->name, drm_mode->type,
  2569. drm_mode->flags);
  2570. /* Update CRTC drm structure */
  2571. crtc->state->active = true;
  2572. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2573. if (rc) {
  2574. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2575. return rc;
  2576. }
  2577. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2578. drm_mode_copy(&crtc->mode, drm_mode);
  2579. /* Update encoder structure */
  2580. sde_encoder_update_caps_for_cont_splash(encoder,
  2581. splash_display, true);
  2582. sde_crtc_update_cont_splash_settings(crtc);
  2583. sde_conn = to_sde_connector(connector);
  2584. if (sde_conn && sde_conn->ops.cont_splash_config)
  2585. sde_conn->ops.cont_splash_config(sde_conn->display);
  2586. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2587. splash_display, crtc);
  2588. if (rc) {
  2589. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2590. return rc;
  2591. }
  2592. }
  2593. return rc;
  2594. }
  2595. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2596. {
  2597. struct sde_kms *sde_kms;
  2598. if (!kms) {
  2599. SDE_ERROR("invalid kms\n");
  2600. return false;
  2601. }
  2602. sde_kms = to_sde_kms(kms);
  2603. return sde_kms->splash_data.num_splash_displays;
  2604. }
  2605. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2606. const struct drm_display_mode *mode,
  2607. const struct msm_resource_caps_info *res, u32 *num_lm)
  2608. {
  2609. struct sde_kms *sde_kms;
  2610. s64 mode_clock_hz = 0;
  2611. s64 max_mdp_clock_hz = 0;
  2612. s64 max_lm_width = 0;
  2613. s64 hdisplay_fp = 0;
  2614. s64 htotal_fp = 0;
  2615. s64 vtotal_fp = 0;
  2616. s64 vrefresh_fp = 0;
  2617. s64 mdp_fudge_factor = 0;
  2618. s64 num_lm_fp = 0;
  2619. s64 lm_clk_fp = 0;
  2620. s64 lm_width_fp = 0;
  2621. int rc = 0;
  2622. if (!num_lm) {
  2623. SDE_ERROR("invalid num_lm pointer\n");
  2624. return -EINVAL;
  2625. }
  2626. /* default to 1 layer mixer */
  2627. *num_lm = 1;
  2628. if (!kms || !mode || !res) {
  2629. SDE_ERROR("invalid input args\n");
  2630. return -EINVAL;
  2631. }
  2632. sde_kms = to_sde_kms(kms);
  2633. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2634. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2635. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2636. htotal_fp = drm_int2fixp(mode->htotal);
  2637. vtotal_fp = drm_int2fixp(mode->vtotal);
  2638. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2639. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2640. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2641. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2642. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2643. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2644. if (mode_clock_hz > max_mdp_clock_hz ||
  2645. hdisplay_fp > max_lm_width) {
  2646. *num_lm = 0;
  2647. do {
  2648. *num_lm += 2;
  2649. num_lm_fp = drm_int2fixp(*num_lm);
  2650. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2651. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2652. if (*num_lm > 4) {
  2653. rc = -EINVAL;
  2654. goto error;
  2655. }
  2656. } while (lm_clk_fp > max_mdp_clock_hz ||
  2657. lm_width_fp > max_lm_width);
  2658. mode_clock_hz = lm_clk_fp;
  2659. }
  2660. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2661. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2662. *num_lm, drm_fixp2int(mode_clock_hz),
  2663. sde_kms->perf.max_core_clk_rate);
  2664. return 0;
  2665. error:
  2666. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2667. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2668. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2669. *num_lm, drm_fixp2int(mode_clock_hz),
  2670. sde_kms->perf.max_core_clk_rate);
  2671. return rc;
  2672. }
  2673. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2674. u32 hdisplay, u32 *num_dsc)
  2675. {
  2676. struct sde_kms *sde_kms;
  2677. uint32_t max_dsc_width;
  2678. if (!num_dsc) {
  2679. SDE_ERROR("invalid num_dsc pointer\n");
  2680. return -EINVAL;
  2681. }
  2682. *num_dsc = 0;
  2683. if (!kms || !hdisplay) {
  2684. SDE_ERROR("invalid input args\n");
  2685. return -EINVAL;
  2686. }
  2687. sde_kms = to_sde_kms(kms);
  2688. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2689. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2690. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2691. hdisplay, max_dsc_width,
  2692. *num_dsc);
  2693. return 0;
  2694. }
  2695. static void _sde_kms_null_commit(struct drm_device *dev,
  2696. struct drm_encoder *enc)
  2697. {
  2698. struct drm_modeset_acquire_ctx ctx;
  2699. struct drm_connector *conn = NULL;
  2700. struct drm_connector *tmp_conn = NULL;
  2701. struct drm_connector_list_iter conn_iter;
  2702. struct drm_atomic_state *state = NULL;
  2703. struct drm_crtc_state *crtc_state = NULL;
  2704. struct drm_connector_state *conn_state = NULL;
  2705. int retry_cnt = 0;
  2706. int ret = 0;
  2707. drm_modeset_acquire_init(&ctx, 0);
  2708. retry:
  2709. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2710. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2711. drm_modeset_backoff(&ctx);
  2712. retry_cnt++;
  2713. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2714. goto retry;
  2715. } else if (WARN_ON(ret)) {
  2716. goto end;
  2717. }
  2718. state = drm_atomic_state_alloc(dev);
  2719. if (!state) {
  2720. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2721. goto end;
  2722. }
  2723. state->acquire_ctx = &ctx;
  2724. drm_connector_list_iter_begin(dev, &conn_iter);
  2725. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2726. if (enc == tmp_conn->state->best_encoder) {
  2727. conn = tmp_conn;
  2728. break;
  2729. }
  2730. }
  2731. drm_connector_list_iter_end(&conn_iter);
  2732. if (!conn) {
  2733. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2734. goto end;
  2735. }
  2736. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2737. conn_state = drm_atomic_get_connector_state(state, conn);
  2738. if (IS_ERR(conn_state)) {
  2739. SDE_ERROR("error %d getting connector %d state\n",
  2740. ret, DRMID(conn));
  2741. goto end;
  2742. }
  2743. crtc_state->active = true;
  2744. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2745. if (ret)
  2746. SDE_ERROR("error %d setting the crtc\n", ret);
  2747. ret = drm_atomic_commit(state);
  2748. if (ret)
  2749. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2750. end:
  2751. if (state)
  2752. drm_atomic_state_put(state);
  2753. drm_modeset_drop_locks(&ctx);
  2754. drm_modeset_acquire_fini(&ctx);
  2755. }
  2756. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2757. const int32_t connector_id)
  2758. {
  2759. struct drm_connector_list_iter conn_iter;
  2760. struct drm_connector *conn;
  2761. struct drm_encoder *drm_enc;
  2762. drm_connector_list_iter_begin(dev, &conn_iter);
  2763. drm_for_each_connector_iter(conn, &conn_iter) {
  2764. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2765. connector_id != conn->base.id)
  2766. continue;
  2767. if (conn->state && conn->state->best_encoder)
  2768. drm_enc = conn->state->best_encoder;
  2769. else
  2770. drm_enc = conn->encoder;
  2771. if (drm_enc)
  2772. sde_encoder_early_wakeup(drm_enc);
  2773. }
  2774. drm_connector_list_iter_end(&conn_iter);
  2775. }
  2776. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2777. struct device *dev)
  2778. {
  2779. int i, ret, crtc_id = 0;
  2780. struct drm_device *ddev = dev_get_drvdata(dev);
  2781. struct drm_connector *conn;
  2782. struct drm_connector_list_iter conn_iter;
  2783. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2784. drm_connector_list_iter_begin(ddev, &conn_iter);
  2785. drm_for_each_connector_iter(conn, &conn_iter) {
  2786. uint64_t lp;
  2787. lp = sde_connector_get_lp(conn);
  2788. if (lp != SDE_MODE_DPMS_LP2)
  2789. continue;
  2790. if (sde_encoder_in_clone_mode(conn->encoder))
  2791. continue;
  2792. ret = sde_encoder_wait_for_event(conn->encoder,
  2793. MSM_ENC_TX_COMPLETE);
  2794. if (ret && ret != -EWOULDBLOCK) {
  2795. SDE_ERROR(
  2796. "[conn: %d] wait for commit done returned %d\n",
  2797. conn->base.id, ret);
  2798. } else if (!ret) {
  2799. crtc_id = drm_crtc_index(conn->state->crtc);
  2800. if (priv->event_thread[crtc_id].thread)
  2801. kthread_flush_worker(
  2802. &priv->event_thread[crtc_id].worker);
  2803. sde_encoder_idle_request(conn->encoder);
  2804. }
  2805. }
  2806. drm_connector_list_iter_end(&conn_iter);
  2807. for (i = 0; i < priv->num_crtcs; i++) {
  2808. if (priv->disp_thread[i].thread)
  2809. kthread_flush_worker(
  2810. &priv->disp_thread[i].worker);
  2811. if (priv->event_thread[i].thread)
  2812. kthread_flush_worker(
  2813. &priv->event_thread[i].worker);
  2814. }
  2815. kthread_flush_worker(&priv->pp_event_worker);
  2816. }
  2817. static int sde_kms_pm_suspend(struct device *dev)
  2818. {
  2819. struct drm_device *ddev;
  2820. struct drm_modeset_acquire_ctx ctx;
  2821. struct drm_connector *conn;
  2822. struct drm_encoder *enc;
  2823. struct drm_connector_list_iter conn_iter;
  2824. struct drm_atomic_state *state = NULL;
  2825. struct sde_kms *sde_kms;
  2826. int ret = 0, num_crtcs = 0;
  2827. if (!dev)
  2828. return -EINVAL;
  2829. ddev = dev_get_drvdata(dev);
  2830. if (!ddev || !ddev_to_msm_kms(ddev))
  2831. return -EINVAL;
  2832. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2833. SDE_EVT32(0);
  2834. /* disable hot-plug polling */
  2835. drm_kms_helper_poll_disable(ddev);
  2836. /* if a display stuck in CS trigger a null commit to complete handoff */
  2837. drm_for_each_encoder(enc, ddev) {
  2838. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2839. _sde_kms_null_commit(ddev, enc);
  2840. }
  2841. /* acquire modeset lock(s) */
  2842. drm_modeset_acquire_init(&ctx, 0);
  2843. retry:
  2844. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2845. if (ret)
  2846. goto unlock;
  2847. /* save current state for resume */
  2848. if (sde_kms->suspend_state)
  2849. drm_atomic_state_put(sde_kms->suspend_state);
  2850. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2851. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2852. ret = PTR_ERR(sde_kms->suspend_state);
  2853. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2854. sde_kms->suspend_state = NULL;
  2855. goto unlock;
  2856. }
  2857. /* create atomic state to disable all CRTCs */
  2858. state = drm_atomic_state_alloc(ddev);
  2859. if (!state) {
  2860. ret = -ENOMEM;
  2861. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2862. goto unlock;
  2863. }
  2864. state->acquire_ctx = &ctx;
  2865. drm_connector_list_iter_begin(ddev, &conn_iter);
  2866. drm_for_each_connector_iter(conn, &conn_iter) {
  2867. struct drm_crtc_state *crtc_state;
  2868. uint64_t lp;
  2869. if (!conn->state || !conn->state->crtc ||
  2870. conn->dpms != DRM_MODE_DPMS_ON ||
  2871. sde_encoder_in_clone_mode(conn->encoder))
  2872. continue;
  2873. lp = sde_connector_get_lp(conn);
  2874. if (lp == SDE_MODE_DPMS_LP1) {
  2875. /* transition LP1->LP2 on pm suspend */
  2876. ret = sde_connector_set_property_for_commit(conn, state,
  2877. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2878. if (ret) {
  2879. DRM_ERROR("failed to set lp2 for conn %d\n",
  2880. conn->base.id);
  2881. drm_connector_list_iter_end(&conn_iter);
  2882. goto unlock;
  2883. }
  2884. }
  2885. if (lp != SDE_MODE_DPMS_LP2) {
  2886. /* force CRTC to be inactive */
  2887. crtc_state = drm_atomic_get_crtc_state(state,
  2888. conn->state->crtc);
  2889. if (IS_ERR_OR_NULL(crtc_state)) {
  2890. DRM_ERROR("failed to get crtc %d state\n",
  2891. conn->state->crtc->base.id);
  2892. drm_connector_list_iter_end(&conn_iter);
  2893. goto unlock;
  2894. }
  2895. if (lp != SDE_MODE_DPMS_LP1)
  2896. crtc_state->active = false;
  2897. ++num_crtcs;
  2898. }
  2899. }
  2900. drm_connector_list_iter_end(&conn_iter);
  2901. /* check for nothing to do */
  2902. if (num_crtcs == 0) {
  2903. DRM_DEBUG("all crtcs are already in the off state\n");
  2904. sde_kms->suspend_block = true;
  2905. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2906. goto unlock;
  2907. }
  2908. /* commit the "disable all" state */
  2909. ret = drm_atomic_commit(state);
  2910. if (ret < 0) {
  2911. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  2912. goto unlock;
  2913. }
  2914. sde_kms->suspend_block = true;
  2915. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  2916. unlock:
  2917. if (state) {
  2918. drm_atomic_state_put(state);
  2919. state = NULL;
  2920. }
  2921. if (ret == -EDEADLK) {
  2922. drm_modeset_backoff(&ctx);
  2923. goto retry;
  2924. }
  2925. drm_modeset_drop_locks(&ctx);
  2926. drm_modeset_acquire_fini(&ctx);
  2927. /*
  2928. * pm runtime driver avoids multiple runtime_suspend API call by
  2929. * checking runtime_status. However, this call helps when there is a
  2930. * race condition between pm_suspend call and doze_suspend/power_off
  2931. * commit. It removes the extra vote from suspend and adds it back
  2932. * later to allow power collapse during pm_suspend call
  2933. */
  2934. pm_runtime_put_sync(dev);
  2935. pm_runtime_get_noresume(dev);
  2936. /* dump clock state before entering suspend */
  2937. if (sde_kms->pm_suspend_clk_dump)
  2938. _sde_kms_dump_clks_state(sde_kms);
  2939. return ret;
  2940. }
  2941. static int sde_kms_pm_resume(struct device *dev)
  2942. {
  2943. struct drm_device *ddev;
  2944. struct sde_kms *sde_kms;
  2945. struct drm_modeset_acquire_ctx ctx;
  2946. int ret, i;
  2947. if (!dev)
  2948. return -EINVAL;
  2949. ddev = dev_get_drvdata(dev);
  2950. if (!ddev || !ddev_to_msm_kms(ddev))
  2951. return -EINVAL;
  2952. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2953. SDE_EVT32(sde_kms->suspend_state != NULL);
  2954. drm_mode_config_reset(ddev);
  2955. drm_modeset_acquire_init(&ctx, 0);
  2956. retry:
  2957. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2958. if (ret == -EDEADLK) {
  2959. drm_modeset_backoff(&ctx);
  2960. goto retry;
  2961. } else if (WARN_ON(ret)) {
  2962. goto end;
  2963. }
  2964. sde_kms->suspend_block = false;
  2965. if (sde_kms->suspend_state) {
  2966. sde_kms->suspend_state->acquire_ctx = &ctx;
  2967. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  2968. ret = drm_atomic_helper_commit_duplicated_state(
  2969. sde_kms->suspend_state, &ctx);
  2970. if (ret != -EDEADLK)
  2971. break;
  2972. drm_modeset_backoff(&ctx);
  2973. }
  2974. if (ret < 0)
  2975. DRM_ERROR("failed to restore state, %d\n", ret);
  2976. drm_atomic_state_put(sde_kms->suspend_state);
  2977. sde_kms->suspend_state = NULL;
  2978. }
  2979. end:
  2980. drm_modeset_drop_locks(&ctx);
  2981. drm_modeset_acquire_fini(&ctx);
  2982. /* enable hot-plug polling */
  2983. drm_kms_helper_poll_enable(ddev);
  2984. return 0;
  2985. }
  2986. static const struct msm_kms_funcs kms_funcs = {
  2987. .hw_init = sde_kms_hw_init,
  2988. .postinit = sde_kms_postinit,
  2989. .irq_preinstall = sde_irq_preinstall,
  2990. .irq_postinstall = sde_irq_postinstall,
  2991. .irq_uninstall = sde_irq_uninstall,
  2992. .irq = sde_irq,
  2993. .lastclose = sde_kms_lastclose,
  2994. .prepare_fence = sde_kms_prepare_fence,
  2995. .prepare_commit = sde_kms_prepare_commit,
  2996. .commit = sde_kms_commit,
  2997. .complete_commit = sde_kms_complete_commit,
  2998. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  2999. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3000. .enable_vblank = sde_kms_enable_vblank,
  3001. .disable_vblank = sde_kms_disable_vblank,
  3002. .check_modified_format = sde_format_check_modified_format,
  3003. .atomic_check = sde_kms_atomic_check,
  3004. .get_format = sde_get_msm_format,
  3005. .round_pixclk = sde_kms_round_pixclk,
  3006. .display_early_wakeup = sde_kms_display_early_wakeup,
  3007. .pm_suspend = sde_kms_pm_suspend,
  3008. .pm_resume = sde_kms_pm_resume,
  3009. .destroy = sde_kms_destroy,
  3010. .debugfs_destroy = sde_kms_debugfs_destroy,
  3011. .cont_splash_config = sde_kms_cont_splash_config,
  3012. .register_events = _sde_kms_register_events,
  3013. .get_address_space = _sde_kms_get_address_space,
  3014. .get_address_space_device = _sde_kms_get_address_space_device,
  3015. .postopen = _sde_kms_post_open,
  3016. .check_for_splash = sde_kms_check_for_splash,
  3017. .get_mixer_count = sde_kms_get_mixer_count,
  3018. .get_dsc_count = sde_kms_get_dsc_count,
  3019. };
  3020. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3021. {
  3022. int i;
  3023. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3024. if (!sde_kms->aspace[i])
  3025. continue;
  3026. msm_gem_address_space_put(sde_kms->aspace[i]);
  3027. sde_kms->aspace[i] = NULL;
  3028. }
  3029. return 0;
  3030. }
  3031. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3032. {
  3033. struct msm_mmu *mmu;
  3034. int i, ret;
  3035. int early_map = 0;
  3036. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3037. return -EINVAL;
  3038. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3039. struct msm_gem_address_space *aspace;
  3040. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3041. if (IS_ERR(mmu)) {
  3042. ret = PTR_ERR(mmu);
  3043. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3044. i, ret);
  3045. continue;
  3046. }
  3047. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3048. mmu, "sde");
  3049. if (IS_ERR(aspace)) {
  3050. ret = PTR_ERR(aspace);
  3051. mmu->funcs->destroy(mmu);
  3052. goto fail;
  3053. }
  3054. sde_kms->aspace[i] = aspace;
  3055. aspace->domain_attached = true;
  3056. /* Mapping splash memory block */
  3057. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3058. sde_kms->splash_data.num_splash_regions) {
  3059. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3060. if (ret) {
  3061. SDE_ERROR("failed to map ret:%d\n", ret);
  3062. goto fail;
  3063. }
  3064. }
  3065. /*
  3066. * disable early-map which would have been enabled during
  3067. * bootup by smmu through the device-tree hint for cont-spash
  3068. */
  3069. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3070. &early_map);
  3071. if (ret) {
  3072. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3073. ret, early_map);
  3074. goto early_map_fail;
  3075. }
  3076. }
  3077. sde_kms->base.aspace = sde_kms->aspace[0];
  3078. return 0;
  3079. early_map_fail:
  3080. _sde_kms_unmap_all_splash_regions(sde_kms);
  3081. fail:
  3082. _sde_kms_mmu_destroy(sde_kms);
  3083. return ret;
  3084. }
  3085. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3086. {
  3087. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3088. return;
  3089. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3090. }
  3091. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3092. {
  3093. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3094. return;
  3095. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3096. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3097. sde_kms->catalog);
  3098. }
  3099. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3100. {
  3101. struct sde_vbif_set_qos_params qos_params;
  3102. struct sde_mdss_cfg *catalog;
  3103. if (!sde_kms->catalog)
  3104. return;
  3105. catalog = sde_kms->catalog;
  3106. memset(&qos_params, 0, sizeof(qos_params));
  3107. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3108. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3109. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3110. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3111. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3112. }
  3113. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3114. {
  3115. struct sde_hw_uidle *uidle;
  3116. if (!sde_kms) {
  3117. SDE_ERROR("invalid kms\n");
  3118. return -EINVAL;
  3119. }
  3120. uidle = sde_kms->hw_uidle;
  3121. if (uidle && uidle->ops.active_override_enable)
  3122. uidle->ops.active_override_enable(uidle, enable);
  3123. return 0;
  3124. }
  3125. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3126. {
  3127. struct device *cpu_dev;
  3128. int cpu = 0;
  3129. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3130. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3131. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3132. return;
  3133. }
  3134. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3135. cpu_dev = get_cpu_device(cpu);
  3136. if (!cpu_dev) {
  3137. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3138. cpu);
  3139. continue;
  3140. }
  3141. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3142. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3143. cpu_irq_latency);
  3144. else
  3145. dev_pm_qos_add_request(cpu_dev,
  3146. &sde_kms->pm_qos_irq_req[cpu],
  3147. DEV_PM_QOS_RESUME_LATENCY,
  3148. cpu_irq_latency);
  3149. }
  3150. }
  3151. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3152. {
  3153. struct device *cpu_dev;
  3154. int cpu = 0;
  3155. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3156. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3157. return;
  3158. }
  3159. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3160. cpu_dev = get_cpu_device(cpu);
  3161. if (!cpu_dev) {
  3162. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3163. cpu);
  3164. continue;
  3165. }
  3166. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3167. dev_pm_qos_remove_request(
  3168. &sde_kms->pm_qos_irq_req[cpu]);
  3169. }
  3170. }
  3171. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3172. {
  3173. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3174. mutex_lock(&priv->phandle.phandle_lock);
  3175. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3176. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3177. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3178. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3179. mutex_unlock(&priv->phandle.phandle_lock);
  3180. }
  3181. static void sde_kms_irq_affinity_notify(
  3182. struct irq_affinity_notify *affinity_notify,
  3183. const cpumask_t *mask)
  3184. {
  3185. struct msm_drm_private *priv;
  3186. struct sde_kms *sde_kms = container_of(affinity_notify,
  3187. struct sde_kms, affinity_notify);
  3188. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3189. return;
  3190. priv = sde_kms->dev->dev_private;
  3191. mutex_lock(&priv->phandle.phandle_lock);
  3192. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3193. // save irq cpu mask
  3194. sde_kms->irq_cpu_mask = *mask;
  3195. // request vote with updated irq cpu mask
  3196. if (atomic_read(&sde_kms->irq_vote_count))
  3197. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3198. mutex_unlock(&priv->phandle.phandle_lock);
  3199. }
  3200. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3201. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3202. {
  3203. struct sde_kms *sde_kms = usr;
  3204. struct msm_kms *msm_kms;
  3205. msm_kms = &sde_kms->base;
  3206. if (!sde_kms)
  3207. return;
  3208. SDE_DEBUG("event_type:%d\n", event_type);
  3209. SDE_EVT32_VERBOSE(event_type);
  3210. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3211. sde_irq_update(msm_kms, true);
  3212. sde_kms->first_kickoff = true;
  3213. /**
  3214. * Rotator sid needs to be programmed since uefi doesn't
  3215. * configure it during continuous splash
  3216. */
  3217. sde_kms_init_rot_sid_hw(sde_kms);
  3218. if (sde_kms->splash_data.num_splash_displays ||
  3219. sde_in_trusted_vm(sde_kms))
  3220. return;
  3221. sde_vbif_init_memtypes(sde_kms);
  3222. sde_kms_init_shared_hw(sde_kms);
  3223. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3224. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3225. sde_irq_update(msm_kms, false);
  3226. sde_kms->first_kickoff = false;
  3227. if (sde_in_trusted_vm(sde_kms))
  3228. return;
  3229. _sde_kms_active_override(sde_kms, true);
  3230. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3231. sde_vbif_axi_halt_request(sde_kms);
  3232. }
  3233. }
  3234. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3235. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3236. {
  3237. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3238. int rc = -EINVAL;
  3239. SDE_DEBUG("\n");
  3240. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3241. if (rc > 0)
  3242. rc = 0;
  3243. SDE_EVT32(rc, genpd->device_count);
  3244. return rc;
  3245. }
  3246. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3247. {
  3248. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3249. SDE_DEBUG("\n");
  3250. pm_runtime_put_sync(sde_kms->dev->dev);
  3251. SDE_EVT32(genpd->device_count);
  3252. return 0;
  3253. }
  3254. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3255. struct sde_splash_data *data)
  3256. {
  3257. int i = 0;
  3258. int ret = 0;
  3259. struct device_node *parent, *node, *node1;
  3260. struct resource r, r1;
  3261. const char *node_name = "splash_region";
  3262. struct sde_splash_mem *mem;
  3263. bool share_splash_mem = false;
  3264. int num_displays, num_regions;
  3265. struct sde_splash_display *splash_display;
  3266. if (!data)
  3267. return -EINVAL;
  3268. memset(data, 0, sizeof(*data));
  3269. parent = of_find_node_by_path("/reserved-memory");
  3270. if (!parent) {
  3271. SDE_ERROR("failed to find reserved-memory node\n");
  3272. return -EINVAL;
  3273. }
  3274. node = of_find_node_by_name(parent, node_name);
  3275. if (!node) {
  3276. SDE_DEBUG("failed to find node %s\n", node_name);
  3277. return -EINVAL;
  3278. }
  3279. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3280. if (!node1)
  3281. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3282. /**
  3283. * Support sharing a single splash memory for all the built in displays
  3284. * and also independent splash region per displays. Incase of
  3285. * independent splash region for each connected display, dtsi node of
  3286. * cont_splash_region should be collection of all memory regions
  3287. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3288. */
  3289. num_displays = dsi_display_get_num_of_displays();
  3290. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3291. data->num_splash_displays = num_displays;
  3292. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3293. if (num_displays > num_regions) {
  3294. share_splash_mem = true;
  3295. pr_info(":%d displays share same splash buf\n", num_displays);
  3296. }
  3297. for (i = 0; i < num_displays; i++) {
  3298. splash_display = &data->splash_display[i];
  3299. if (!i || !share_splash_mem) {
  3300. if (of_address_to_resource(node, i, &r)) {
  3301. SDE_ERROR("invalid data for:%s\n", node_name);
  3302. return -EINVAL;
  3303. }
  3304. mem = &data->splash_mem[i];
  3305. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3306. SDE_DEBUG("failed to find ramdump memory\n");
  3307. mem->ramdump_base = 0;
  3308. mem->ramdump_size = 0;
  3309. } else {
  3310. mem->ramdump_base = (unsigned long)r1.start;
  3311. mem->ramdump_size = (r1.end - r1.start) + 1;
  3312. }
  3313. mem->splash_buf_base = (unsigned long)r.start;
  3314. mem->splash_buf_size = (r.end - r.start) + 1;
  3315. mem->ref_cnt = 0;
  3316. splash_display->splash = mem;
  3317. data->num_splash_regions++;
  3318. } else {
  3319. data->splash_display[i].splash = &data->splash_mem[0];
  3320. }
  3321. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3322. splash_display->splash->splash_buf_base,
  3323. splash_display->splash->splash_buf_size);
  3324. }
  3325. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3326. return ret;
  3327. }
  3328. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3329. struct platform_device *platformdev)
  3330. {
  3331. int rc = -EINVAL;
  3332. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3333. if (IS_ERR(sde_kms->mmio)) {
  3334. rc = PTR_ERR(sde_kms->mmio);
  3335. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3336. sde_kms->mmio = NULL;
  3337. goto error;
  3338. }
  3339. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3340. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3341. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3342. sde_kms->mmio_len);
  3343. if (rc)
  3344. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3345. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3346. "vbif_phys");
  3347. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3348. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3349. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3350. sde_kms->vbif[VBIF_RT] = NULL;
  3351. goto error;
  3352. }
  3353. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3354. "vbif_phys");
  3355. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3356. sde_kms->vbif_len[VBIF_RT]);
  3357. if (rc)
  3358. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3359. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3360. "vbif_nrt_phys");
  3361. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3362. sde_kms->vbif[VBIF_NRT] = NULL;
  3363. SDE_DEBUG("VBIF NRT is not defined");
  3364. } else {
  3365. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3366. "vbif_nrt_phys");
  3367. rc = sde_dbg_reg_register_base("vbif_nrt",
  3368. sde_kms->vbif[VBIF_NRT],
  3369. sde_kms->vbif_len[VBIF_NRT]);
  3370. if (rc)
  3371. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3372. rc);
  3373. }
  3374. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3375. "regdma_phys");
  3376. if (IS_ERR(sde_kms->reg_dma)) {
  3377. sde_kms->reg_dma = NULL;
  3378. SDE_DEBUG("REG_DMA is not defined");
  3379. } else {
  3380. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3381. "regdma_phys");
  3382. rc = sde_dbg_reg_register_base("reg_dma",
  3383. sde_kms->reg_dma,
  3384. sde_kms->reg_dma_len);
  3385. if (rc)
  3386. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3387. rc);
  3388. }
  3389. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3390. "sid_phys");
  3391. if (IS_ERR(sde_kms->sid)) {
  3392. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3393. sde_kms->sid = NULL;
  3394. } else {
  3395. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3396. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3397. sde_kms->sid_len);
  3398. if (rc)
  3399. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3400. }
  3401. error:
  3402. return rc;
  3403. }
  3404. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3405. struct sde_kms *sde_kms)
  3406. {
  3407. int rc = 0;
  3408. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3409. sde_kms->genpd.name = dev->unique;
  3410. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3411. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3412. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3413. if (rc < 0) {
  3414. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3415. sde_kms->genpd.name, rc);
  3416. return rc;
  3417. }
  3418. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3419. &sde_kms->genpd);
  3420. if (rc < 0) {
  3421. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3422. sde_kms->genpd.name, rc);
  3423. pm_genpd_remove(&sde_kms->genpd);
  3424. return rc;
  3425. }
  3426. sde_kms->genpd_init = true;
  3427. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3428. }
  3429. return rc;
  3430. }
  3431. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3432. struct drm_device *dev,
  3433. struct msm_drm_private *priv)
  3434. {
  3435. struct sde_rm *rm = NULL;
  3436. int i, rc = -EINVAL;
  3437. sde_kms->catalog = sde_hw_catalog_init(dev);
  3438. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3439. rc = PTR_ERR(sde_kms->catalog);
  3440. if (!sde_kms->catalog)
  3441. rc = -EINVAL;
  3442. SDE_ERROR("catalog init failed: %d\n", rc);
  3443. sde_kms->catalog = NULL;
  3444. goto power_error;
  3445. }
  3446. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3447. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3448. /* initialize power domain if defined */
  3449. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3450. if (rc) {
  3451. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3452. goto genpd_err;
  3453. }
  3454. rc = _sde_kms_mmu_init(sde_kms);
  3455. if (rc) {
  3456. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3457. goto power_error;
  3458. }
  3459. /* Initialize reg dma block which is a singleton */
  3460. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3461. sde_kms->dev);
  3462. if (rc) {
  3463. SDE_ERROR("failed: reg dma init failed\n");
  3464. goto power_error;
  3465. }
  3466. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3467. rm = &sde_kms->rm;
  3468. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3469. sde_kms->dev);
  3470. if (rc) {
  3471. SDE_ERROR("rm init failed: %d\n", rc);
  3472. goto power_error;
  3473. }
  3474. sde_kms->rm_init = true;
  3475. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3476. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3477. rc = PTR_ERR(sde_kms->hw_intr);
  3478. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3479. sde_kms->hw_intr = NULL;
  3480. goto hw_intr_init_err;
  3481. }
  3482. /*
  3483. * Attempt continuous splash handoff only if reserved
  3484. * splash memory is found & release resources on any error
  3485. * in finding display hw config in splash
  3486. */
  3487. if (sde_kms->splash_data.num_splash_regions) {
  3488. struct sde_splash_display *display;
  3489. int ret, display_count =
  3490. sde_kms->splash_data.num_splash_displays;
  3491. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3492. &sde_kms->splash_data, sde_kms->catalog);
  3493. for (i = 0; i < display_count; i++) {
  3494. display = &sde_kms->splash_data.splash_display[i];
  3495. /*
  3496. * free splash region on resource init failure and
  3497. * cont-splash disabled case
  3498. */
  3499. if (!display->cont_splash_enabled || ret)
  3500. _sde_kms_free_splash_display_data(
  3501. sde_kms, display);
  3502. }
  3503. }
  3504. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3505. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3506. rc = PTR_ERR(sde_kms->hw_mdp);
  3507. if (!sde_kms->hw_mdp)
  3508. rc = -EINVAL;
  3509. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3510. sde_kms->hw_mdp = NULL;
  3511. goto power_error;
  3512. }
  3513. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3514. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3515. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3516. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3517. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3518. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3519. if (!sde_kms->hw_vbif[vbif_idx])
  3520. rc = -EINVAL;
  3521. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3522. sde_kms->hw_vbif[vbif_idx] = NULL;
  3523. goto power_error;
  3524. }
  3525. }
  3526. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3527. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3528. sde_kms->mmio_len, sde_kms->catalog);
  3529. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3530. rc = PTR_ERR(sde_kms->hw_uidle);
  3531. if (!sde_kms->hw_uidle)
  3532. rc = -EINVAL;
  3533. /* uidle is optional, so do not make it a fatal error */
  3534. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3535. sde_kms->hw_uidle = NULL;
  3536. rc = 0;
  3537. }
  3538. } else {
  3539. sde_kms->hw_uidle = NULL;
  3540. }
  3541. if (sde_kms->sid) {
  3542. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3543. sde_kms->sid_len, sde_kms->catalog);
  3544. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3545. rc = PTR_ERR(sde_kms->hw_sid);
  3546. SDE_ERROR("failed to init sid %ld\n", rc);
  3547. sde_kms->hw_sid = NULL;
  3548. goto power_error;
  3549. }
  3550. }
  3551. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3552. &priv->phandle, "core_clk");
  3553. if (rc) {
  3554. SDE_ERROR("failed to init perf %d\n", rc);
  3555. goto perf_err;
  3556. }
  3557. /*
  3558. * _sde_kms_drm_obj_init should create the DRM related objects
  3559. * i.e. CRTCs, planes, encoders, connectors and so forth
  3560. */
  3561. rc = _sde_kms_drm_obj_init(sde_kms);
  3562. if (rc) {
  3563. SDE_ERROR("modeset init failed: %d\n", rc);
  3564. goto drm_obj_init_err;
  3565. }
  3566. return 0;
  3567. genpd_err:
  3568. drm_obj_init_err:
  3569. sde_core_perf_destroy(&sde_kms->perf);
  3570. hw_intr_init_err:
  3571. perf_err:
  3572. power_error:
  3573. return rc;
  3574. }
  3575. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3576. {
  3577. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3578. int rc = 0;
  3579. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3580. if (rc) {
  3581. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3582. return rc;
  3583. }
  3584. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3585. if (rc) {
  3586. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3587. return rc;
  3588. }
  3589. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3590. if (rc) {
  3591. SDE_ERROR("failed to get io irq for KMS");
  3592. return rc;
  3593. }
  3594. return rc;
  3595. }
  3596. static int sde_kms_hw_init(struct msm_kms *kms)
  3597. {
  3598. struct sde_kms *sde_kms;
  3599. struct drm_device *dev;
  3600. struct msm_drm_private *priv;
  3601. struct platform_device *platformdev;
  3602. int i, irq_num, rc = -EINVAL;
  3603. if (!kms) {
  3604. SDE_ERROR("invalid kms\n");
  3605. goto end;
  3606. }
  3607. sde_kms = to_sde_kms(kms);
  3608. dev = sde_kms->dev;
  3609. if (!dev || !dev->dev) {
  3610. SDE_ERROR("invalid device\n");
  3611. goto end;
  3612. }
  3613. platformdev = to_platform_device(dev->dev);
  3614. priv = dev->dev_private;
  3615. if (!priv) {
  3616. SDE_ERROR("invalid private data\n");
  3617. goto end;
  3618. }
  3619. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3620. if (rc)
  3621. goto error;
  3622. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3623. if (rc)
  3624. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3625. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3626. if (rc)
  3627. goto error;
  3628. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3629. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3630. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3631. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3632. mutex_init(&sde_kms->secure_transition_lock);
  3633. atomic_set(&sde_kms->detach_sec_cb, 0);
  3634. atomic_set(&sde_kms->detach_all_cb, 0);
  3635. atomic_set(&sde_kms->irq_vote_count, 0);
  3636. /*
  3637. * Support format modifiers for compression etc.
  3638. */
  3639. dev->mode_config.allow_fb_modifiers = true;
  3640. /*
  3641. * Handle (re)initializations during power enable
  3642. */
  3643. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3644. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3645. SDE_POWER_EVENT_POST_ENABLE |
  3646. SDE_POWER_EVENT_PRE_DISABLE,
  3647. sde_kms_handle_power_event, sde_kms, "kms");
  3648. if (sde_kms->splash_data.num_splash_displays) {
  3649. SDE_DEBUG("Skipping MDP Resources disable\n");
  3650. } else {
  3651. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3652. sde_power_data_bus_set_quota(&priv->phandle, i,
  3653. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3654. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3655. pm_runtime_put_sync(sde_kms->dev->dev);
  3656. }
  3657. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3658. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3659. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3660. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3661. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3662. if (sde_in_trusted_vm(sde_kms))
  3663. rc = sde_vm_trusted_init(sde_kms);
  3664. else
  3665. rc = sde_vm_primary_init(sde_kms);
  3666. if (rc) {
  3667. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3668. goto error;
  3669. }
  3670. return 0;
  3671. error:
  3672. _sde_kms_hw_destroy(sde_kms, platformdev);
  3673. end:
  3674. return rc;
  3675. }
  3676. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3677. {
  3678. struct msm_drm_private *priv;
  3679. struct sde_kms *sde_kms;
  3680. if (!dev || !dev->dev_private) {
  3681. SDE_ERROR("drm device node invalid\n");
  3682. return ERR_PTR(-EINVAL);
  3683. }
  3684. priv = dev->dev_private;
  3685. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3686. if (!sde_kms) {
  3687. SDE_ERROR("failed to allocate sde kms\n");
  3688. return ERR_PTR(-ENOMEM);
  3689. }
  3690. msm_kms_init(&sde_kms->base, &kms_funcs);
  3691. sde_kms->dev = dev;
  3692. return &sde_kms->base;
  3693. }
  3694. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3695. {
  3696. struct dsi_display *display;
  3697. struct sde_splash_display *handoff_display;
  3698. int i;
  3699. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3700. handoff_display = &sde_kms->splash_data.splash_display[i];
  3701. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3702. if (handoff_display->cont_splash_enabled)
  3703. _sde_kms_free_splash_display_data(sde_kms,
  3704. handoff_display);
  3705. dsi_display_set_active_state(display, false);
  3706. }
  3707. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3708. }
  3709. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms)
  3710. {
  3711. struct drm_device *dev;
  3712. struct msm_drm_private *priv;
  3713. struct sde_splash_display *handoff_display;
  3714. struct dsi_display *display;
  3715. int ret, i;
  3716. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3717. SDE_ERROR("invalid params\n");
  3718. return -EINVAL;
  3719. }
  3720. if (sde_kms->dsi_display_count != 1) {
  3721. SDE_ERROR("no. of displays not supported:%d\n",
  3722. sde_kms->dsi_display_count);
  3723. return -EINVAL;
  3724. }
  3725. dev = sde_kms->dev;
  3726. priv = dev->dev_private;
  3727. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3728. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3729. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3730. &sde_kms->splash_data, sde_kms->catalog);
  3731. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3732. handoff_display = &sde_kms->splash_data.splash_display[i];
  3733. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3734. if (!handoff_display->cont_splash_enabled || ret)
  3735. _sde_kms_free_splash_display_data(sde_kms,
  3736. handoff_display);
  3737. else
  3738. dsi_display_set_active_state(display, true);
  3739. }
  3740. ret = sde_kms_cont_splash_config(&sde_kms->base);
  3741. if (ret) {
  3742. SDE_ERROR("error in setting handoff configs\n");
  3743. goto error;
  3744. }
  3745. /**
  3746. * fill-in vote for the continuous splash hanodff path, which will be
  3747. * removed on the successful first commit.
  3748. */
  3749. pm_runtime_get_sync(sde_kms->dev->dev);
  3750. return 0;
  3751. error:
  3752. sde_kms_vm_trusted_resource_deinit(sde_kms);
  3753. return ret;
  3754. }
  3755. static int _sde_kms_register_events(struct msm_kms *kms,
  3756. struct drm_mode_object *obj, u32 event, bool en)
  3757. {
  3758. int ret = 0;
  3759. struct drm_crtc *crtc = NULL;
  3760. struct drm_connector *conn = NULL;
  3761. struct sde_kms *sde_kms = NULL;
  3762. if (!kms || !obj) {
  3763. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3764. return -EINVAL;
  3765. }
  3766. sde_kms = to_sde_kms(kms);
  3767. switch (obj->type) {
  3768. case DRM_MODE_OBJECT_CRTC:
  3769. crtc = obj_to_crtc(obj);
  3770. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3771. break;
  3772. case DRM_MODE_OBJECT_CONNECTOR:
  3773. conn = obj_to_connector(obj);
  3774. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3775. en);
  3776. break;
  3777. }
  3778. return ret;
  3779. }
  3780. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3781. {
  3782. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3783. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3784. }