dp_main.c 150 KB

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  1. /*
  2. * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #include <qdf_types.h>
  19. #include <qdf_lock.h>
  20. #include <qdf_net_types.h>
  21. #include <qdf_lro.h>
  22. #include <hal_api.h>
  23. #include <hif.h>
  24. #include <htt.h>
  25. #include <wdi_event.h>
  26. #include <queue.h>
  27. #include "dp_htt.h"
  28. #include "dp_types.h"
  29. #include "dp_internal.h"
  30. #include "dp_tx.h"
  31. #include "dp_tx_desc.h"
  32. #include "dp_rx.h"
  33. #include <cdp_txrx_handle.h>
  34. #include <wlan_cfg.h>
  35. #include "cdp_txrx_cmn_struct.h"
  36. #include <qdf_util.h>
  37. #include "dp_peer.h"
  38. #include "dp_rx_mon.h"
  39. #include "htt_stats.h"
  40. #include "qdf_mem.h" /* qdf_mem_malloc,free */
  41. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  42. #include "cdp_txrx_flow_ctrl_v2.h"
  43. #else
  44. static inline void
  45. cdp_dump_flow_pool_info(struct cdp_soc_t *soc)
  46. {
  47. return;
  48. }
  49. #endif
  50. #include <ol_cfg.h>
  51. #include "dp_ipa.h"
  52. #define DP_INTR_POLL_TIMER_MS 10
  53. #define DP_WDS_AGING_TIMER_DEFAULT_MS 120000
  54. #define DP_MCS_LENGTH (6*MAX_MCS)
  55. #define DP_NSS_LENGTH (6*SS_COUNT)
  56. #define DP_RXDMA_ERR_LENGTH (6*HAL_RXDMA_ERR_MAX)
  57. #define DP_REO_ERR_LENGTH (6*HAL_REO_ERR_MAX)
  58. #define DP_MAX_MCS_STRING_LEN 30
  59. #define DP_CURR_FW_STATS_AVAIL 19
  60. #define DP_HTT_DBG_EXT_STATS_MAX 256
  61. #ifdef IPA_OFFLOAD
  62. /* Exclude IPA rings from the interrupt context */
  63. #define TX_RING_MASK_VAL 0x7
  64. #define RX_RING_MASK_VAL 0x7
  65. #else
  66. #define TX_RING_MASK_VAL 0xF
  67. #define RX_RING_MASK_VAL 0xF
  68. #endif
  69. unsigned int napi_budget = 128;
  70. module_param(napi_budget, uint, 0644);
  71. MODULE_PARM_DESC(napi_budget,
  72. "tasklet mode: more than 0xffff , napi budget if <= 0xffff");
  73. /**
  74. * default_dscp_tid_map - Default DSCP-TID mapping
  75. *
  76. * DSCP TID AC
  77. * 000000 0 WME_AC_BE
  78. * 001000 1 WME_AC_BK
  79. * 010000 1 WME_AC_BK
  80. * 011000 0 WME_AC_BE
  81. * 100000 5 WME_AC_VI
  82. * 101000 5 WME_AC_VI
  83. * 110000 6 WME_AC_VO
  84. * 111000 6 WME_AC_VO
  85. */
  86. static uint8_t default_dscp_tid_map[DSCP_TID_MAP_MAX] = {
  87. 0, 0, 0, 0, 0, 0, 0, 0,
  88. 1, 1, 1, 1, 1, 1, 1, 1,
  89. 1, 1, 1, 1, 1, 1, 1, 1,
  90. 0, 0, 0, 0, 0, 0, 0, 0,
  91. 5, 5, 5, 5, 5, 5, 5, 5,
  92. 5, 5, 5, 5, 5, 5, 5, 5,
  93. 6, 6, 6, 6, 6, 6, 6, 6,
  94. 6, 6, 6, 6, 6, 6, 6, 6,
  95. };
  96. /*
  97. * struct dp_rate_debug
  98. *
  99. * @mcs_type: print string for a given mcs
  100. * @valid: valid mcs rate?
  101. */
  102. struct dp_rate_debug {
  103. char mcs_type[DP_MAX_MCS_STRING_LEN];
  104. uint8_t valid;
  105. };
  106. #define MCS_VALID 1
  107. #define MCS_INVALID 0
  108. static const struct dp_rate_debug dp_rate_string[DOT11_MAX][MAX_MCS] = {
  109. {
  110. {"CCK 11 Mbps Long ", MCS_VALID},
  111. {"CCK 5.5 Mbps Long ", MCS_VALID},
  112. {"CCK 2 Mbps Long ", MCS_VALID},
  113. {"CCK 1 Mbps Long ", MCS_VALID},
  114. {"CCK 11 Mbps Short ", MCS_VALID},
  115. {"CCK 5.5 Mbps Short", MCS_VALID},
  116. {"CCK 2 Mbps Short ", MCS_VALID},
  117. {"INVALID ", MCS_INVALID},
  118. {"INVALID ", MCS_INVALID},
  119. {"INVALID ", MCS_INVALID},
  120. {"INVALID ", MCS_INVALID},
  121. {"INVALID ", MCS_INVALID},
  122. {"INVALID ", MCS_VALID},
  123. },
  124. {
  125. {"OFDM 48 Mbps", MCS_VALID},
  126. {"OFDM 24 Mbps", MCS_VALID},
  127. {"OFDM 12 Mbps", MCS_VALID},
  128. {"OFDM 6 Mbps ", MCS_VALID},
  129. {"OFDM 54 Mbps", MCS_VALID},
  130. {"OFDM 36 Mbps", MCS_VALID},
  131. {"OFDM 18 Mbps", MCS_VALID},
  132. {"OFDM 9 Mbps ", MCS_VALID},
  133. {"INVALID ", MCS_INVALID},
  134. {"INVALID ", MCS_INVALID},
  135. {"INVALID ", MCS_INVALID},
  136. {"INVALID ", MCS_INVALID},
  137. {"INVALID ", MCS_VALID},
  138. },
  139. {
  140. {"HT MCS 0 (BPSK 1/2) ", MCS_VALID},
  141. {"HT MCS 1 (QPSK 1/2) ", MCS_VALID},
  142. {"HT MCS 2 (QPSK 3/4) ", MCS_VALID},
  143. {"HT MCS 3 (16-QAM 1/2)", MCS_VALID},
  144. {"HT MCS 4 (16-QAM 3/4)", MCS_VALID},
  145. {"HT MCS 5 (64-QAM 2/3)", MCS_VALID},
  146. {"HT MCS 6 (64-QAM 3/4)", MCS_VALID},
  147. {"HT MCS 7 (64-QAM 5/6)", MCS_VALID},
  148. {"INVALID ", MCS_INVALID},
  149. {"INVALID ", MCS_INVALID},
  150. {"INVALID ", MCS_INVALID},
  151. {"INVALID ", MCS_INVALID},
  152. {"INVALID ", MCS_VALID},
  153. },
  154. {
  155. {"VHT MCS 0 (BPSK 1/2) ", MCS_VALID},
  156. {"VHT MCS 1 (QPSK 1/2) ", MCS_VALID},
  157. {"VHT MCS 2 (QPSK 3/4) ", MCS_VALID},
  158. {"VHT MCS 3 (16-QAM 1/2) ", MCS_VALID},
  159. {"VHT MCS 4 (16-QAM 3/4) ", MCS_VALID},
  160. {"VHT MCS 5 (64-QAM 2/3) ", MCS_VALID},
  161. {"VHT MCS 6 (64-QAM 3/4) ", MCS_VALID},
  162. {"VHT MCS 7 (64-QAM 5/6) ", MCS_VALID},
  163. {"VHT MCS 8 (256-QAM 3/4) ", MCS_VALID},
  164. {"VHT MCS 9 (256-QAM 5/6) ", MCS_VALID},
  165. {"VHT MCS 10 (1024-QAM 3/4)", MCS_VALID},
  166. {"VHT MCS 10 (1024-QAM 5/6)", MCS_VALID},
  167. {"INVALID ", MCS_VALID},
  168. },
  169. {
  170. {"HE MCS 0 (BPSK 1/2) ", MCS_VALID},
  171. {"HE MCS 1 (QPSK 1/2) ", MCS_VALID},
  172. {"HE MCS 2 (QPSK 3/4) ", MCS_VALID},
  173. {"HE MCS 3 (16-QAM 1/2) ", MCS_VALID},
  174. {"HE MCS 4 (16-QAM 3/4) ", MCS_VALID},
  175. {"HE MCS 5 (64-QAM 2/3) ", MCS_VALID},
  176. {"HE MCS 6 (64-QAM 3/4) ", MCS_VALID},
  177. {"HE MCS 7 (64-QAM 5/6) ", MCS_VALID},
  178. {"HE MCS 8 (256-QAM 3/4) ", MCS_VALID},
  179. {"HE MCS 9 (256-QAM 5/6) ", MCS_VALID},
  180. {"HE MCS 10 (1024-QAM 3/4)", MCS_VALID},
  181. {"HE MCS 10 (1024-QAM 5/6)", MCS_VALID},
  182. {"INVALID ", MCS_VALID},
  183. }
  184. };
  185. /**
  186. * @brief Cpu ring map types
  187. */
  188. enum dp_cpu_ring_map_types {
  189. DP_DEFAULT_MAP,
  190. DP_NSS_FIRST_RADIO_OFFLOADED_MAP,
  191. DP_NSS_SECOND_RADIO_OFFLOADED_MAP,
  192. DP_NSS_ALL_RADIO_OFFLOADED_MAP,
  193. DP_CPU_RING_MAP_MAX
  194. };
  195. /**
  196. * @brief Cpu to tx ring map
  197. */
  198. static uint8_t dp_cpu_ring_map[DP_CPU_RING_MAP_MAX][WLAN_CFG_INT_NUM_CONTEXTS] = {
  199. {0x0, 0x1, 0x2, 0x0},
  200. {0x1, 0x2, 0x1, 0x2},
  201. {0x0, 0x2, 0x0, 0x2},
  202. {0x2, 0x2, 0x2, 0x2}
  203. };
  204. /**
  205. * @brief Select the type of statistics
  206. */
  207. enum dp_stats_type {
  208. STATS_FW = 0,
  209. STATS_HOST = 1,
  210. STATS_TYPE_MAX = 2,
  211. };
  212. /**
  213. * @brief General Firmware statistics options
  214. *
  215. */
  216. enum dp_fw_stats {
  217. TXRX_FW_STATS_INVALID = -1,
  218. };
  219. /**
  220. * dp_stats_mapping_table - Firmware and Host statistics
  221. * currently supported
  222. */
  223. const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
  224. {HTT_DBG_EXT_STATS_RESET, TXRX_HOST_STATS_INVALID},
  225. {HTT_DBG_EXT_STATS_PDEV_TX, TXRX_HOST_STATS_INVALID},
  226. {HTT_DBG_EXT_STATS_PDEV_RX, TXRX_HOST_STATS_INVALID},
  227. {HTT_DBG_EXT_STATS_PDEV_TX_HWQ, TXRX_HOST_STATS_INVALID},
  228. {HTT_DBG_EXT_STATS_PDEV_TX_SCHED, TXRX_HOST_STATS_INVALID},
  229. {HTT_DBG_EXT_STATS_PDEV_ERROR, TXRX_HOST_STATS_INVALID},
  230. {HTT_DBG_EXT_STATS_PDEV_TQM, TXRX_HOST_STATS_INVALID},
  231. {HTT_DBG_EXT_STATS_TQM_CMDQ, TXRX_HOST_STATS_INVALID},
  232. {HTT_DBG_EXT_STATS_TX_DE_INFO, TXRX_HOST_STATS_INVALID},
  233. {HTT_DBG_EXT_STATS_PDEV_TX_RATE, TXRX_HOST_STATS_INVALID},
  234. {HTT_DBG_EXT_STATS_PDEV_RX_RATE, TXRX_HOST_STATS_INVALID},
  235. {TXRX_FW_STATS_INVALID, TXRX_HOST_STATS_INVALID},
  236. {HTT_DBG_EXT_STATS_TX_SELFGEN_INFO, TXRX_HOST_STATS_INVALID},
  237. {HTT_DBG_EXT_STATS_TX_MU_HWQ, TXRX_HOST_STATS_INVALID},
  238. {HTT_DBG_EXT_STATS_RING_IF_INFO, TXRX_HOST_STATS_INVALID},
  239. {HTT_DBG_EXT_STATS_SRNG_INFO, TXRX_HOST_STATS_INVALID},
  240. {HTT_DBG_EXT_STATS_SFM_INFO, TXRX_HOST_STATS_INVALID},
  241. {HTT_DBG_EXT_STATS_PDEV_TX_MU, TXRX_HOST_STATS_INVALID},
  242. {HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST, TXRX_HOST_STATS_INVALID},
  243. /* Last ENUM for HTT FW STATS */
  244. {DP_HTT_DBG_EXT_STATS_MAX, TXRX_HOST_STATS_INVALID},
  245. {TXRX_FW_STATS_INVALID, TXRX_CLEAR_STATS},
  246. {TXRX_FW_STATS_INVALID, TXRX_RX_RATE_STATS},
  247. {TXRX_FW_STATS_INVALID, TXRX_TX_RATE_STATS},
  248. {TXRX_FW_STATS_INVALID, TXRX_TX_HOST_STATS},
  249. {TXRX_FW_STATS_INVALID, TXRX_RX_HOST_STATS},
  250. {TXRX_FW_STATS_INVALID, TXRX_AST_STATS},
  251. };
  252. /**
  253. * dp_srng_find_ring_in_mask() - find which ext_group a ring belongs
  254. * @ring_num: ring num of the ring being queried
  255. * @grp_mask: the grp_mask array for the ring type in question.
  256. *
  257. * The grp_mask array is indexed by group number and the bit fields correspond
  258. * to ring numbers. We are finding which interrupt group a ring belongs to.
  259. *
  260. * Return: the index in the grp_mask array with the ring number.
  261. * -QDF_STATUS_E_NOENT if no entry is found
  262. */
  263. static int dp_srng_find_ring_in_mask(int ring_num, int *grp_mask)
  264. {
  265. int ext_group_num;
  266. int mask = 1 << ring_num;
  267. for (ext_group_num = 0; ext_group_num < WLAN_CFG_INT_NUM_CONTEXTS;
  268. ext_group_num++) {
  269. if (mask & grp_mask[ext_group_num])
  270. return ext_group_num;
  271. }
  272. return -QDF_STATUS_E_NOENT;
  273. }
  274. static int dp_srng_calculate_msi_group(struct dp_soc *soc,
  275. enum hal_ring_type ring_type,
  276. int ring_num)
  277. {
  278. int *grp_mask;
  279. switch (ring_type) {
  280. case WBM2SW_RELEASE:
  281. /* dp_tx_comp_handler - soc->tx_comp_ring */
  282. if (ring_num < 3)
  283. grp_mask = &soc->wlan_cfg_ctx->int_tx_ring_mask[0];
  284. /* dp_rx_wbm_err_process - soc->rx_rel_ring */
  285. else if (ring_num == 3) {
  286. /* sw treats this as a separate ring type */
  287. grp_mask = &soc->wlan_cfg_ctx->
  288. int_rx_wbm_rel_ring_mask[0];
  289. ring_num = 0;
  290. } else {
  291. qdf_assert(0);
  292. return -QDF_STATUS_E_NOENT;
  293. }
  294. break;
  295. case REO_EXCEPTION:
  296. /* dp_rx_err_process - &soc->reo_exception_ring */
  297. grp_mask = &soc->wlan_cfg_ctx->int_rx_err_ring_mask[0];
  298. break;
  299. case REO_DST:
  300. /* dp_rx_process - soc->reo_dest_ring */
  301. grp_mask = &soc->wlan_cfg_ctx->int_rx_ring_mask[0];
  302. break;
  303. case REO_STATUS:
  304. /* dp_reo_status_ring_handler - soc->reo_status_ring */
  305. grp_mask = &soc->wlan_cfg_ctx->int_reo_status_ring_mask[0];
  306. break;
  307. /* dp_rx_mon_status_srng_process - pdev->rxdma_mon_status_ring*/
  308. case RXDMA_MONITOR_STATUS:
  309. /* dp_rx_mon_dest_process - pdev->rxdma_mon_dst_ring */
  310. case RXDMA_MONITOR_DST:
  311. /* dp_mon_process */
  312. grp_mask = &soc->wlan_cfg_ctx->int_rx_mon_ring_mask[0];
  313. break;
  314. case RXDMA_MONITOR_BUF:
  315. case RXDMA_BUF:
  316. /* TODO: support low_thresh interrupt */
  317. return -QDF_STATUS_E_NOENT;
  318. break;
  319. case TCL_DATA:
  320. case TCL_CMD:
  321. case REO_CMD:
  322. case SW2WBM_RELEASE:
  323. case WBM_IDLE_LINK:
  324. /* normally empty SW_TO_HW rings */
  325. return -QDF_STATUS_E_NOENT;
  326. break;
  327. case TCL_STATUS:
  328. case REO_REINJECT:
  329. case RXDMA_DST:
  330. /* misc unused rings */
  331. return -QDF_STATUS_E_NOENT;
  332. break;
  333. case CE_SRC:
  334. case CE_DST:
  335. case CE_DST_STATUS:
  336. /* CE_rings - currently handled by hif */
  337. default:
  338. return -QDF_STATUS_E_NOENT;
  339. break;
  340. }
  341. return dp_srng_find_ring_in_mask(ring_num, grp_mask);
  342. }
  343. static void dp_srng_msi_setup(struct dp_soc *soc, struct hal_srng_params
  344. *ring_params, int ring_type, int ring_num)
  345. {
  346. int msi_group_number;
  347. int msi_data_count;
  348. int ret;
  349. uint32_t msi_data_start, msi_irq_start, addr_low, addr_high;
  350. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  351. &msi_data_count, &msi_data_start,
  352. &msi_irq_start);
  353. if (ret)
  354. return;
  355. msi_group_number = dp_srng_calculate_msi_group(soc, ring_type,
  356. ring_num);
  357. if (msi_group_number < 0) {
  358. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  359. FL("ring not part of an ext_group; ring_type: %d,ring_num %d"),
  360. ring_type, ring_num);
  361. ring_params->msi_addr = 0;
  362. ring_params->msi_data = 0;
  363. return;
  364. }
  365. if (msi_group_number > msi_data_count) {
  366. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  367. FL("2 msi_groups will share an msi; msi_group_num %d"),
  368. msi_group_number);
  369. QDF_ASSERT(0);
  370. }
  371. pld_get_msi_address(soc->osdev->dev, &addr_low, &addr_high);
  372. ring_params->msi_addr = addr_low;
  373. ring_params->msi_addr |= (qdf_dma_addr_t)(((uint64_t)addr_high) << 32);
  374. ring_params->msi_data = (msi_group_number % msi_data_count)
  375. + msi_data_start;
  376. ring_params->flags |= HAL_SRNG_MSI_INTR;
  377. }
  378. /**
  379. * dp_print_ast_stats() - Dump AST table contents
  380. * @soc: Datapath soc handle
  381. *
  382. * return void
  383. */
  384. #ifdef FEATURE_WDS
  385. static void dp_print_ast_stats(struct dp_soc *soc)
  386. {
  387. uint8_t i;
  388. uint8_t num_entries = 0;
  389. struct dp_vdev *vdev;
  390. struct dp_pdev *pdev;
  391. struct dp_peer *peer;
  392. struct dp_ast_entry *ase, *tmp_ase;
  393. DP_PRINT_STATS("AST Stats:");
  394. DP_PRINT_STATS(" Entries Added = %d", soc->stats.ast.added);
  395. DP_PRINT_STATS(" Entries Deleted = %d", soc->stats.ast.deleted);
  396. DP_PRINT_STATS(" Entries Agedout = %d", soc->stats.ast.aged_out);
  397. DP_PRINT_STATS("AST Table:");
  398. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  399. pdev = soc->pdev_list[i];
  400. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  401. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  402. DP_PEER_ITERATE_ASE_LIST(peer, ase, tmp_ase) {
  403. DP_PRINT_STATS("%6d mac_addr = %pM"
  404. " peer_mac_addr = %pM"
  405. " type = %d"
  406. " next_hop = %d"
  407. " is_active = %d"
  408. " is_bss = %d",
  409. ++num_entries,
  410. ase->mac_addr.raw,
  411. ase->peer->mac_addr.raw,
  412. ase->type,
  413. ase->next_hop,
  414. ase->is_active,
  415. ase->is_bss);
  416. }
  417. }
  418. }
  419. }
  420. }
  421. #else
  422. static void dp_print_ast_stats(struct dp_soc *soc)
  423. {
  424. DP_PRINT_STATS("AST Stats not available.Enable FEATURE_WDS");
  425. return;
  426. }
  427. #endif
  428. /*
  429. * dp_setup_srng - Internal function to setup SRNG rings used by data path
  430. */
  431. static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
  432. int ring_type, int ring_num, int mac_id, uint32_t num_entries)
  433. {
  434. void *hal_soc = soc->hal_soc;
  435. uint32_t entry_size = hal_srng_get_entrysize(hal_soc, ring_type);
  436. /* TODO: See if we should get align size from hal */
  437. uint32_t ring_base_align = 8;
  438. struct hal_srng_params ring_params;
  439. uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
  440. /* TODO: Currently hal layer takes care of endianness related settings.
  441. * See if these settings need to passed from DP layer
  442. */
  443. ring_params.flags = 0;
  444. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  445. FL("Ring type: %d, num:%d"), ring_type, ring_num);
  446. num_entries = (num_entries > max_entries) ? max_entries : num_entries;
  447. srng->hal_srng = NULL;
  448. srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
  449. srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
  450. soc->osdev, soc->osdev->dev, srng->alloc_size,
  451. &(srng->base_paddr_unaligned));
  452. if (!srng->base_vaddr_unaligned) {
  453. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  454. FL("alloc failed - ring_type: %d, ring_num %d"),
  455. ring_type, ring_num);
  456. return QDF_STATUS_E_NOMEM;
  457. }
  458. ring_params.ring_base_vaddr = srng->base_vaddr_unaligned +
  459. ((unsigned long)srng->base_vaddr_unaligned % ring_base_align);
  460. ring_params.ring_base_paddr = srng->base_paddr_unaligned +
  461. ((unsigned long)(ring_params.ring_base_vaddr) -
  462. (unsigned long)srng->base_vaddr_unaligned);
  463. ring_params.num_entries = num_entries;
  464. if (soc->intr_mode == DP_INTR_MSI) {
  465. dp_srng_msi_setup(soc, &ring_params, ring_type, ring_num);
  466. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  467. FL("Using MSI for ring_type: %d, ring_num %d"),
  468. ring_type, ring_num);
  469. } else {
  470. ring_params.msi_data = 0;
  471. ring_params.msi_addr = 0;
  472. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  473. FL("Skipping MSI for ring_type: %d, ring_num %d"),
  474. ring_type, ring_num);
  475. }
  476. /*
  477. * Setup interrupt timer and batch counter thresholds for
  478. * interrupt mitigation based on ring type
  479. */
  480. if (ring_type == REO_DST) {
  481. ring_params.intr_timer_thres_us =
  482. wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
  483. ring_params.intr_batch_cntr_thres_entries =
  484. wlan_cfg_get_int_batch_threshold_rx(soc->wlan_cfg_ctx);
  485. } else if (ring_type == WBM2SW_RELEASE && (ring_num < 3)) {
  486. ring_params.intr_timer_thres_us =
  487. wlan_cfg_get_int_timer_threshold_tx(soc->wlan_cfg_ctx);
  488. ring_params.intr_batch_cntr_thres_entries =
  489. wlan_cfg_get_int_batch_threshold_tx(soc->wlan_cfg_ctx);
  490. } else {
  491. ring_params.intr_timer_thres_us =
  492. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  493. ring_params.intr_batch_cntr_thres_entries =
  494. wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
  495. }
  496. /* Enable low threshold interrupts for rx buffer rings (regular and
  497. * monitor buffer rings.
  498. * TODO: See if this is required for any other ring
  499. */
  500. if ((ring_type == RXDMA_BUF) || (ring_type == RXDMA_MONITOR_BUF)) {
  501. /* TODO: Setting low threshold to 1/8th of ring size
  502. * see if this needs to be configurable
  503. */
  504. ring_params.low_threshold = num_entries >> 3;
  505. ring_params.flags |= HAL_SRNG_LOW_THRES_INTR_ENABLE;
  506. ring_params.intr_timer_thres_us = 0x1000;
  507. }
  508. srng->hal_srng = hal_srng_setup(hal_soc, ring_type, ring_num,
  509. mac_id, &ring_params);
  510. return 0;
  511. }
  512. /**
  513. * dp_srng_cleanup - Internal function to cleanup SRNG rings used by data path
  514. * Any buffers allocated and attached to ring entries are expected to be freed
  515. * before calling this function.
  516. */
  517. static void dp_srng_cleanup(struct dp_soc *soc, struct dp_srng *srng,
  518. int ring_type, int ring_num)
  519. {
  520. if (!srng->hal_srng) {
  521. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  522. FL("Ring type: %d, num:%d not setup"),
  523. ring_type, ring_num);
  524. return;
  525. }
  526. hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
  527. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  528. srng->alloc_size,
  529. srng->base_vaddr_unaligned,
  530. srng->base_paddr_unaligned, 0);
  531. srng->hal_srng = NULL;
  532. }
  533. #ifdef IPA_OFFLOAD
  534. /**
  535. * dp_tx_ipa_uc_detach - Free autonomy TX resources
  536. * @soc: data path instance
  537. * @pdev: core txrx pdev context
  538. *
  539. * Free allocated TX buffers with WBM SRNG
  540. *
  541. * Return: none
  542. */
  543. static void dp_tx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  544. {
  545. int idx;
  546. for (idx = 0; idx < soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt; idx++) {
  547. if (soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx])
  548. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[idx]);
  549. }
  550. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  551. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = NULL;
  552. }
  553. /**
  554. * dp_rx_ipa_uc_detach - free autonomy RX resources
  555. * @soc: data path instance
  556. * @pdev: core txrx pdev context
  557. *
  558. * This function will detach DP RX into main device context
  559. * will free DP Rx resources.
  560. *
  561. * Return: none
  562. */
  563. static void dp_rx_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  564. {
  565. }
  566. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  567. {
  568. /* TX resource detach */
  569. dp_tx_ipa_uc_detach(soc, pdev);
  570. /* RX resource detach */
  571. dp_rx_ipa_uc_detach(soc, pdev);
  572. dp_srng_cleanup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2);
  573. return QDF_STATUS_SUCCESS; /* success */
  574. }
  575. /* Hard coded config parameters until dp_ops_cfg.cfg_attach implemented */
  576. #define CFG_IPA_UC_TX_BUF_SIZE_DEFAULT (2048)
  577. /**
  578. * dp_tx_ipa_uc_attach - Allocate autonomy TX resources
  579. * @soc: data path instance
  580. * @pdev: Physical device handle
  581. *
  582. * Allocate TX buffer from non-cacheable memory
  583. * Attache allocated TX buffers with WBM SRNG
  584. *
  585. * Return: int
  586. */
  587. static int dp_tx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  588. {
  589. uint32_t tx_buffer_count;
  590. uint32_t ring_base_align = 8;
  591. void *buffer_vaddr_unaligned;
  592. void *buffer_vaddr;
  593. qdf_dma_addr_t buffer_paddr_unaligned;
  594. qdf_dma_addr_t buffer_paddr;
  595. void *wbm_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  596. uint32_t paddr_lo;
  597. uint32_t paddr_hi;
  598. void *ring_entry;
  599. int ring_size = ((struct hal_srng *)wbm_srng)->ring_size;
  600. int retval = QDF_STATUS_SUCCESS;
  601. /*
  602. * Uncomment when dp_ops_cfg.cfg_attach is implemented
  603. * unsigned int uc_tx_buf_sz =
  604. * dp_cfg_ipa_uc_tx_buf_size(pdev->osif_pdev);
  605. */
  606. unsigned int uc_tx_buf_sz = CFG_IPA_UC_TX_BUF_SIZE_DEFAULT;
  607. unsigned int alloc_size = uc_tx_buf_sz + ring_base_align - 1;
  608. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  609. "requested %d buffers to be posted to wbm ring",
  610. ring_size);
  611. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr = qdf_mem_malloc(ring_size *
  612. sizeof(*soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr));
  613. if (!soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr) {
  614. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  615. "%s: IPA WBM Ring mem_info alloc fail", __func__);
  616. return -ENOMEM;
  617. }
  618. hal_srng_access_start(soc->hal_soc, wbm_srng);
  619. /* Allocate TX buffers as many as possible */
  620. for (tx_buffer_count = 0;
  621. tx_buffer_count < ring_size; tx_buffer_count++) {
  622. ring_entry = hal_srng_src_get_next(soc->hal_soc, wbm_srng);
  623. if (!ring_entry) {
  624. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  625. "Failed to get WBM ring entry\n");
  626. goto fail;
  627. }
  628. buffer_vaddr_unaligned = qdf_mem_alloc_consistent(soc->osdev,
  629. soc->osdev->dev, alloc_size, &buffer_paddr_unaligned);
  630. if (!buffer_vaddr_unaligned) {
  631. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  632. "IPA WDI TX buffer alloc fail %d allocated\n",
  633. tx_buffer_count);
  634. break;
  635. }
  636. buffer_vaddr = buffer_vaddr_unaligned +
  637. ((unsigned long)buffer_vaddr_unaligned %
  638. ring_base_align);
  639. buffer_paddr = buffer_paddr_unaligned +
  640. ((unsigned long)(buffer_vaddr) -
  641. (unsigned long)buffer_vaddr_unaligned);
  642. paddr_lo = ((u64)buffer_paddr & 0x00000000ffffffff);
  643. paddr_hi = ((u64)buffer_paddr & 0x0000001f00000000) >> 32;
  644. HAL_WBM_PADDR_LO_SET(ring_entry, paddr_lo);
  645. HAL_WBM_PADDR_HI_SET(ring_entry, paddr_hi);
  646. soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr[tx_buffer_count] =
  647. buffer_vaddr;
  648. }
  649. hal_srng_access_end(soc->hal_soc, wbm_srng);
  650. soc->ipa_uc_tx_rsc.alloc_tx_buf_cnt = tx_buffer_count;
  651. return retval;
  652. fail:
  653. qdf_mem_free(soc->ipa_uc_tx_rsc.tx_buf_pool_vaddr);
  654. return retval;
  655. }
  656. /**
  657. * dp_rx_ipa_uc_attach - Allocate autonomy RX resources
  658. * @soc: data path instance
  659. * @pdev: core txrx pdev context
  660. *
  661. * This function will attach a DP RX instance into the main
  662. * device (SOC) context.
  663. *
  664. * Return: QDF_STATUS_SUCCESS: success
  665. * QDF_STATUS_E_RESOURCES: Error return
  666. */
  667. static int dp_rx_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  668. {
  669. return QDF_STATUS_SUCCESS;
  670. }
  671. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  672. {
  673. int error;
  674. /* TX resource attach */
  675. error = dp_tx_ipa_uc_attach(soc, pdev);
  676. if (error) {
  677. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  678. "DP IPA UC TX attach fail code %d\n", error);
  679. return error;
  680. }
  681. /* RX resource attach */
  682. error = dp_rx_ipa_uc_attach(soc, pdev);
  683. if (error) {
  684. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  685. "DP IPA UC RX attach fail code %d\n", error);
  686. dp_tx_ipa_uc_detach(soc, pdev);
  687. return error;
  688. }
  689. return QDF_STATUS_SUCCESS; /* success */
  690. }
  691. #else
  692. static int dp_ipa_uc_detach(struct dp_soc *soc, struct dp_pdev *pdev)
  693. {
  694. return QDF_STATUS_SUCCESS;
  695. }
  696. static int dp_ipa_uc_attach(struct dp_soc *soc, struct dp_pdev *pdev)
  697. {
  698. return QDF_STATUS_SUCCESS;
  699. }
  700. #endif
  701. /* TODO: Need this interface from HIF */
  702. void *hif_get_hal_handle(void *hif_handle);
  703. /*
  704. * dp_service_srngs() - Top level interrupt handler for DP Ring interrupts
  705. * @dp_ctx: DP SOC handle
  706. * @budget: Number of frames/descriptors that can be processed in one shot
  707. *
  708. * Return: remaining budget/quota for the soc device
  709. */
  710. static uint32_t dp_service_srngs(void *dp_ctx, uint32_t dp_budget)
  711. {
  712. struct dp_intr *int_ctx = (struct dp_intr *)dp_ctx;
  713. struct dp_soc *soc = int_ctx->soc;
  714. int ring = 0;
  715. uint32_t work_done = 0;
  716. int budget = dp_budget;
  717. uint8_t tx_mask = int_ctx->tx_ring_mask;
  718. uint8_t rx_mask = int_ctx->rx_ring_mask;
  719. uint8_t rx_err_mask = int_ctx->rx_err_ring_mask;
  720. uint8_t rx_wbm_rel_mask = int_ctx->rx_wbm_rel_ring_mask;
  721. uint8_t reo_status_mask = int_ctx->reo_status_ring_mask;
  722. uint32_t remaining_quota = dp_budget;
  723. /* Process Tx completion interrupts first to return back buffers */
  724. while (tx_mask) {
  725. if (tx_mask & 0x1) {
  726. work_done =
  727. dp_tx_comp_handler(soc,
  728. soc->tx_comp_ring[ring].hal_srng,
  729. remaining_quota);
  730. QDF_TRACE(QDF_MODULE_ID_DP,
  731. QDF_TRACE_LEVEL_INFO,
  732. "tx mask 0x%x ring %d,"
  733. "budget %d, work_done %d",
  734. tx_mask, ring, budget, work_done);
  735. budget -= work_done;
  736. if (budget <= 0)
  737. goto budget_done;
  738. remaining_quota = budget;
  739. }
  740. tx_mask = tx_mask >> 1;
  741. ring++;
  742. }
  743. /* Process REO Exception ring interrupt */
  744. if (rx_err_mask) {
  745. work_done = dp_rx_err_process(soc,
  746. soc->reo_exception_ring.hal_srng,
  747. remaining_quota);
  748. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  749. "REO Exception Ring: work_done %d budget %d",
  750. work_done, budget);
  751. budget -= work_done;
  752. if (budget <= 0) {
  753. goto budget_done;
  754. }
  755. remaining_quota = budget;
  756. }
  757. /* Process Rx WBM release ring interrupt */
  758. if (rx_wbm_rel_mask) {
  759. work_done = dp_rx_wbm_err_process(soc,
  760. soc->rx_rel_ring.hal_srng, remaining_quota);
  761. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  762. "WBM Release Ring: work_done %d budget %d",
  763. work_done, budget);
  764. budget -= work_done;
  765. if (budget <= 0) {
  766. goto budget_done;
  767. }
  768. remaining_quota = budget;
  769. }
  770. /* Process Rx interrupts */
  771. if (rx_mask) {
  772. for (ring = 0; ring < soc->num_reo_dest_rings; ring++) {
  773. if (rx_mask & (1 << ring)) {
  774. work_done =
  775. dp_rx_process(int_ctx,
  776. soc->reo_dest_ring[ring].hal_srng,
  777. remaining_quota);
  778. QDF_TRACE(QDF_MODULE_ID_DP,
  779. QDF_TRACE_LEVEL_INFO,
  780. "rx mask 0x%x ring %d,"
  781. "work_done %d budget %d",
  782. rx_mask, ring, work_done,
  783. budget);
  784. budget -= work_done;
  785. if (budget <= 0)
  786. goto budget_done;
  787. remaining_quota = budget;
  788. }
  789. }
  790. }
  791. if (reo_status_mask)
  792. dp_reo_status_ring_handler(soc);
  793. /* Process LMAC interrupts */
  794. for (ring = 0 ; ring < MAX_PDEV_CNT; ring++) {
  795. if (soc->pdev_list[ring] == NULL)
  796. continue;
  797. if (int_ctx->rx_mon_ring_mask & (1 << ring)) {
  798. work_done =
  799. dp_mon_process(soc, ring, remaining_quota);
  800. budget -= work_done;
  801. remaining_quota = budget;
  802. }
  803. if (int_ctx->rxdma2host_ring_mask & (1 << ring)) {
  804. work_done =
  805. dp_rxdma_err_process(soc, ring,
  806. remaining_quota);
  807. budget -= work_done;
  808. }
  809. }
  810. qdf_lro_flush(int_ctx->lro_ctx);
  811. budget_done:
  812. return dp_budget - budget;
  813. }
  814. #ifdef DP_INTR_POLL_BASED
  815. /* dp_interrupt_timer()- timer poll for interrupts
  816. *
  817. * @arg: SoC Handle
  818. *
  819. * Return:
  820. *
  821. */
  822. static void dp_interrupt_timer(void *arg)
  823. {
  824. struct dp_soc *soc = (struct dp_soc *) arg;
  825. int i;
  826. if (qdf_atomic_read(&soc->cmn_init_done)) {
  827. for (i = 0;
  828. i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++)
  829. dp_service_srngs(&soc->intr_ctx[i], 0xffff);
  830. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  831. }
  832. }
  833. /*
  834. * dp_soc_interrupt_attach_poll() - Register handlers for DP interrupts
  835. * @txrx_soc: DP SOC handle
  836. *
  837. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  838. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  839. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  840. *
  841. * Return: 0 for success. nonzero for failure.
  842. */
  843. static QDF_STATUS dp_soc_interrupt_attach_poll(void *txrx_soc)
  844. {
  845. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  846. int i;
  847. soc->intr_mode = DP_INTR_POLL;
  848. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  849. soc->intr_ctx[i].dp_intr_id = i;
  850. soc->intr_ctx[i].tx_ring_mask = TX_RING_MASK_VAL;
  851. soc->intr_ctx[i].rx_ring_mask = RX_RING_MASK_VAL;
  852. soc->intr_ctx[i].rx_mon_ring_mask = 0x1;
  853. soc->intr_ctx[i].rx_err_ring_mask = 0x1;
  854. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0x1;
  855. soc->intr_ctx[i].reo_status_ring_mask = 0x1;
  856. soc->intr_ctx[i].rxdma2host_ring_mask = 0x1;
  857. soc->intr_ctx[i].soc = soc;
  858. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  859. }
  860. qdf_timer_init(soc->osdev, &soc->int_timer,
  861. dp_interrupt_timer, (void *)soc,
  862. QDF_TIMER_TYPE_WAKE_APPS);
  863. return QDF_STATUS_SUCCESS;
  864. }
  865. #ifdef CONFIG_MCL
  866. extern int con_mode_monitor;
  867. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc);
  868. /*
  869. * dp_soc_interrupt_attach_wrapper() - Register handlers for DP interrupts
  870. * @txrx_soc: DP SOC handle
  871. *
  872. * Call the appropriate attach function based on the mode of operation.
  873. * This is a WAR for enabling monitor mode.
  874. *
  875. * Return: 0 for success. nonzero for failure.
  876. */
  877. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  878. {
  879. if (con_mode_monitor == QDF_GLOBAL_MONITOR_MODE) {
  880. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  881. FL("Attach interrupts in Poll mode"));
  882. return dp_soc_interrupt_attach_poll(txrx_soc);
  883. } else {
  884. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  885. FL("Attach interrupts in MSI mode"));
  886. return dp_soc_interrupt_attach(txrx_soc);
  887. }
  888. }
  889. #else
  890. static QDF_STATUS dp_soc_interrupt_attach_wrapper(void *txrx_soc)
  891. {
  892. return dp_soc_interrupt_attach_poll(txrx_soc);
  893. }
  894. #endif
  895. #endif
  896. static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
  897. int intr_ctx_num, int *irq_id_map, int *num_irq_r)
  898. {
  899. int j;
  900. int num_irq = 0;
  901. int tx_mask =
  902. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  903. int rx_mask =
  904. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  905. int rx_mon_mask =
  906. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, intr_ctx_num);
  907. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  908. soc->wlan_cfg_ctx, intr_ctx_num);
  909. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  910. soc->wlan_cfg_ctx, intr_ctx_num);
  911. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  912. soc->wlan_cfg_ctx, intr_ctx_num);
  913. for (j = 0; j < HIF_MAX_GRP_IRQ; j++) {
  914. if (tx_mask & (1 << j)) {
  915. irq_id_map[num_irq++] =
  916. (wbm2host_tx_completions_ring1 - j);
  917. }
  918. if (rx_mask & (1 << j)) {
  919. irq_id_map[num_irq++] =
  920. (reo2host_destination_ring1 - j);
  921. }
  922. if (rx_mon_mask & (1 << j)) {
  923. irq_id_map[num_irq++] =
  924. (ppdu_end_interrupts_mac1 - j);
  925. }
  926. if (rx_wbm_rel_ring_mask & (1 << j))
  927. irq_id_map[num_irq++] = wbm2host_rx_release;
  928. if (rx_err_ring_mask & (1 << j))
  929. irq_id_map[num_irq++] = reo2host_exception;
  930. if (reo_status_ring_mask & (1 << j))
  931. irq_id_map[num_irq++] = reo2host_status;
  932. }
  933. *num_irq_r = num_irq;
  934. }
  935. static void dp_soc_interrupt_map_calculate_msi(struct dp_soc *soc,
  936. int intr_ctx_num, int *irq_id_map, int *num_irq_r,
  937. int msi_vector_count, int msi_vector_start)
  938. {
  939. int tx_mask = wlan_cfg_get_tx_ring_mask(
  940. soc->wlan_cfg_ctx, intr_ctx_num);
  941. int rx_mask = wlan_cfg_get_rx_ring_mask(
  942. soc->wlan_cfg_ctx, intr_ctx_num);
  943. int rx_mon_mask = wlan_cfg_get_rx_mon_ring_mask(
  944. soc->wlan_cfg_ctx, intr_ctx_num);
  945. int rx_err_ring_mask = wlan_cfg_get_rx_err_ring_mask(
  946. soc->wlan_cfg_ctx, intr_ctx_num);
  947. int rx_wbm_rel_ring_mask = wlan_cfg_get_rx_wbm_rel_ring_mask(
  948. soc->wlan_cfg_ctx, intr_ctx_num);
  949. int reo_status_ring_mask = wlan_cfg_get_reo_status_ring_mask(
  950. soc->wlan_cfg_ctx, intr_ctx_num);
  951. unsigned int vector =
  952. (intr_ctx_num % msi_vector_count) + msi_vector_start;
  953. int num_irq = 0;
  954. soc->intr_mode = DP_INTR_MSI;
  955. if (tx_mask | rx_mask | rx_mon_mask | rx_err_ring_mask |
  956. rx_wbm_rel_ring_mask | reo_status_ring_mask)
  957. irq_id_map[num_irq++] =
  958. pld_get_msi_irq(soc->osdev->dev, vector);
  959. *num_irq_r = num_irq;
  960. }
  961. static void dp_soc_interrupt_map_calculate(struct dp_soc *soc, int intr_ctx_num,
  962. int *irq_id_map, int *num_irq)
  963. {
  964. int msi_vector_count, ret;
  965. uint32_t msi_base_data, msi_vector_start;
  966. ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
  967. &msi_vector_count,
  968. &msi_base_data,
  969. &msi_vector_start);
  970. if (ret)
  971. return dp_soc_interrupt_map_calculate_integrated(soc,
  972. intr_ctx_num, irq_id_map, num_irq);
  973. else
  974. dp_soc_interrupt_map_calculate_msi(soc,
  975. intr_ctx_num, irq_id_map, num_irq,
  976. msi_vector_count, msi_vector_start);
  977. }
  978. /*
  979. * dp_soc_interrupt_attach() - Register handlers for DP interrupts
  980. * @txrx_soc: DP SOC handle
  981. *
  982. * Host driver will register for “DP_NUM_INTERRUPT_CONTEXTS” number of NAPI
  983. * contexts. Each NAPI context will have a tx_ring_mask , rx_ring_mask ,and
  984. * rx_monitor_ring mask to indicate the rings that are processed by the handler.
  985. *
  986. * Return: 0 for success. nonzero for failure.
  987. */
  988. static QDF_STATUS dp_soc_interrupt_attach(void *txrx_soc)
  989. {
  990. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  991. int i = 0;
  992. int num_irq = 0;
  993. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  994. int ret = 0;
  995. /* Map of IRQ ids registered with one interrupt context */
  996. int irq_id_map[HIF_MAX_GRP_IRQ];
  997. int tx_mask =
  998. wlan_cfg_get_tx_ring_mask(soc->wlan_cfg_ctx, i);
  999. int rx_mask =
  1000. wlan_cfg_get_rx_ring_mask(soc->wlan_cfg_ctx, i);
  1001. int rx_mon_mask =
  1002. wlan_cfg_get_rx_mon_ring_mask(soc->wlan_cfg_ctx, i);
  1003. int rx_err_ring_mask =
  1004. wlan_cfg_get_rx_err_ring_mask(soc->wlan_cfg_ctx, i);
  1005. int rx_wbm_rel_ring_mask =
  1006. wlan_cfg_get_rx_wbm_rel_ring_mask(soc->wlan_cfg_ctx, i);
  1007. int reo_status_ring_mask =
  1008. wlan_cfg_get_reo_status_ring_mask(soc->wlan_cfg_ctx, i);
  1009. int rxdma2host_ring_mask =
  1010. wlan_cfg_get_rxdma2host_ring_mask(soc->wlan_cfg_ctx, i);
  1011. soc->intr_ctx[i].dp_intr_id = i;
  1012. soc->intr_ctx[i].tx_ring_mask = tx_mask;
  1013. soc->intr_ctx[i].rx_ring_mask = rx_mask;
  1014. soc->intr_ctx[i].rx_mon_ring_mask = rx_mon_mask;
  1015. soc->intr_ctx[i].rx_err_ring_mask = rx_err_ring_mask;
  1016. soc->intr_ctx[i].rxdma2host_ring_mask = rxdma2host_ring_mask;
  1017. soc->intr_ctx[i].rx_wbm_rel_ring_mask = rx_wbm_rel_ring_mask;
  1018. soc->intr_ctx[i].reo_status_ring_mask = reo_status_ring_mask;
  1019. soc->intr_ctx[i].soc = soc;
  1020. num_irq = 0;
  1021. dp_soc_interrupt_map_calculate(soc, i, &irq_id_map[0],
  1022. &num_irq);
  1023. ret = hif_register_ext_group(soc->hif_handle,
  1024. num_irq, irq_id_map, dp_service_srngs,
  1025. &soc->intr_ctx[i], "dp_intr",
  1026. napi_budget);
  1027. if (ret) {
  1028. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1029. FL("failed, ret = %d"), ret);
  1030. return QDF_STATUS_E_FAILURE;
  1031. }
  1032. soc->intr_ctx[i].lro_ctx = qdf_lro_init();
  1033. }
  1034. hif_configure_ext_group_interrupts(soc->hif_handle);
  1035. return QDF_STATUS_SUCCESS;
  1036. }
  1037. /*
  1038. * dp_soc_interrupt_detach() - Deregister any allocations done for interrupts
  1039. * @txrx_soc: DP SOC handle
  1040. *
  1041. * Return: void
  1042. */
  1043. static void dp_soc_interrupt_detach(void *txrx_soc)
  1044. {
  1045. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1046. int i;
  1047. if (soc->intr_mode == DP_INTR_POLL) {
  1048. qdf_timer_stop(&soc->int_timer);
  1049. qdf_timer_free(&soc->int_timer);
  1050. } else {
  1051. hif_deregister_exec_group(soc->hif_handle, "dp_intr");
  1052. }
  1053. for (i = 0; i < wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx); i++) {
  1054. soc->intr_ctx[i].tx_ring_mask = 0;
  1055. soc->intr_ctx[i].rx_ring_mask = 0;
  1056. soc->intr_ctx[i].rx_mon_ring_mask = 0;
  1057. soc->intr_ctx[i].rx_err_ring_mask = 0;
  1058. soc->intr_ctx[i].rx_wbm_rel_ring_mask = 0;
  1059. soc->intr_ctx[i].reo_status_ring_mask = 0;
  1060. qdf_lro_deinit(soc->intr_ctx[i].lro_ctx);
  1061. }
  1062. }
  1063. #define AVG_MAX_MPDUS_PER_TID 128
  1064. #define AVG_TIDS_PER_CLIENT 2
  1065. #define AVG_FLOWS_PER_TID 2
  1066. #define AVG_MSDUS_PER_FLOW 128
  1067. #define AVG_MSDUS_PER_MPDU 4
  1068. /*
  1069. * Allocate and setup link descriptor pool that will be used by HW for
  1070. * various link and queue descriptors and managed by WBM
  1071. */
  1072. static int dp_hw_link_desc_pool_setup(struct dp_soc *soc)
  1073. {
  1074. int link_desc_size = hal_get_link_desc_size(soc->hal_soc);
  1075. int link_desc_align = hal_get_link_desc_align(soc->hal_soc);
  1076. uint32_t max_clients = wlan_cfg_get_max_clients(soc->wlan_cfg_ctx);
  1077. uint32_t num_mpdus_per_link_desc =
  1078. hal_num_mpdus_per_link_desc(soc->hal_soc);
  1079. uint32_t num_msdus_per_link_desc =
  1080. hal_num_msdus_per_link_desc(soc->hal_soc);
  1081. uint32_t num_mpdu_links_per_queue_desc =
  1082. hal_num_mpdu_links_per_queue_desc(soc->hal_soc);
  1083. uint32_t max_alloc_size = wlan_cfg_max_alloc_size(soc->wlan_cfg_ctx);
  1084. uint32_t total_link_descs, total_mem_size;
  1085. uint32_t num_mpdu_link_descs, num_mpdu_queue_descs;
  1086. uint32_t num_tx_msdu_link_descs, num_rx_msdu_link_descs;
  1087. uint32_t num_link_desc_banks;
  1088. uint32_t last_bank_size = 0;
  1089. uint32_t entry_size, num_entries;
  1090. int i;
  1091. uint32_t desc_id = 0;
  1092. /* Only Tx queue descriptors are allocated from common link descriptor
  1093. * pool Rx queue descriptors are not included in this because (REO queue
  1094. * extension descriptors) they are expected to be allocated contiguously
  1095. * with REO queue descriptors
  1096. */
  1097. num_mpdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1098. AVG_MAX_MPDUS_PER_TID) / num_mpdus_per_link_desc;
  1099. num_mpdu_queue_descs = num_mpdu_link_descs /
  1100. num_mpdu_links_per_queue_desc;
  1101. num_tx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1102. AVG_FLOWS_PER_TID * AVG_MSDUS_PER_FLOW) /
  1103. num_msdus_per_link_desc;
  1104. num_rx_msdu_link_descs = (max_clients * AVG_TIDS_PER_CLIENT *
  1105. AVG_MAX_MPDUS_PER_TID * AVG_MSDUS_PER_MPDU) / 6;
  1106. num_entries = num_mpdu_link_descs + num_mpdu_queue_descs +
  1107. num_tx_msdu_link_descs + num_rx_msdu_link_descs;
  1108. /* Round up to power of 2 */
  1109. total_link_descs = 1;
  1110. while (total_link_descs < num_entries)
  1111. total_link_descs <<= 1;
  1112. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1113. FL("total_link_descs: %u, link_desc_size: %d"),
  1114. total_link_descs, link_desc_size);
  1115. total_mem_size = total_link_descs * link_desc_size;
  1116. total_mem_size += link_desc_align;
  1117. if (total_mem_size <= max_alloc_size) {
  1118. num_link_desc_banks = 0;
  1119. last_bank_size = total_mem_size;
  1120. } else {
  1121. num_link_desc_banks = (total_mem_size) /
  1122. (max_alloc_size - link_desc_align);
  1123. last_bank_size = total_mem_size %
  1124. (max_alloc_size - link_desc_align);
  1125. }
  1126. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  1127. FL("total_mem_size: %d, num_link_desc_banks: %u"),
  1128. total_mem_size, num_link_desc_banks);
  1129. for (i = 0; i < num_link_desc_banks; i++) {
  1130. soc->link_desc_banks[i].base_vaddr_unaligned =
  1131. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1132. max_alloc_size,
  1133. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1134. soc->link_desc_banks[i].size = max_alloc_size;
  1135. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)(
  1136. soc->link_desc_banks[i].base_vaddr_unaligned) +
  1137. ((unsigned long)(
  1138. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1139. link_desc_align));
  1140. soc->link_desc_banks[i].base_paddr = (unsigned long)(
  1141. soc->link_desc_banks[i].base_paddr_unaligned) +
  1142. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1143. (unsigned long)(
  1144. soc->link_desc_banks[i].base_vaddr_unaligned));
  1145. if (!soc->link_desc_banks[i].base_vaddr_unaligned) {
  1146. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1147. FL("Link descriptor memory alloc failed"));
  1148. goto fail;
  1149. }
  1150. }
  1151. if (last_bank_size) {
  1152. /* Allocate last bank in case total memory required is not exact
  1153. * multiple of max_alloc_size
  1154. */
  1155. soc->link_desc_banks[i].base_vaddr_unaligned =
  1156. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1157. last_bank_size,
  1158. &(soc->link_desc_banks[i].base_paddr_unaligned));
  1159. soc->link_desc_banks[i].size = last_bank_size;
  1160. soc->link_desc_banks[i].base_vaddr = (void *)((unsigned long)
  1161. (soc->link_desc_banks[i].base_vaddr_unaligned) +
  1162. ((unsigned long)(
  1163. soc->link_desc_banks[i].base_vaddr_unaligned) %
  1164. link_desc_align));
  1165. soc->link_desc_banks[i].base_paddr =
  1166. (unsigned long)(
  1167. soc->link_desc_banks[i].base_paddr_unaligned) +
  1168. ((unsigned long)(soc->link_desc_banks[i].base_vaddr) -
  1169. (unsigned long)(
  1170. soc->link_desc_banks[i].base_vaddr_unaligned));
  1171. }
  1172. /* Allocate and setup link descriptor idle list for HW internal use */
  1173. entry_size = hal_srng_get_entrysize(soc->hal_soc, WBM_IDLE_LINK);
  1174. total_mem_size = entry_size * total_link_descs;
  1175. if (total_mem_size <= max_alloc_size) {
  1176. void *desc;
  1177. if (dp_srng_setup(soc, &soc->wbm_idle_link_ring,
  1178. WBM_IDLE_LINK, 0, 0, total_link_descs)) {
  1179. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1180. FL("Link desc idle ring setup failed"));
  1181. goto fail;
  1182. }
  1183. hal_srng_access_start_unlocked(soc->hal_soc,
  1184. soc->wbm_idle_link_ring.hal_srng);
  1185. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1186. soc->link_desc_banks[i].base_paddr; i++) {
  1187. uint32_t num_entries = (soc->link_desc_banks[i].size -
  1188. ((unsigned long)(
  1189. soc->link_desc_banks[i].base_vaddr) -
  1190. (unsigned long)(
  1191. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1192. / link_desc_size;
  1193. unsigned long paddr = (unsigned long)(
  1194. soc->link_desc_banks[i].base_paddr);
  1195. while (num_entries && (desc = hal_srng_src_get_next(
  1196. soc->hal_soc,
  1197. soc->wbm_idle_link_ring.hal_srng))) {
  1198. hal_set_link_desc_addr(desc,
  1199. LINK_DESC_COOKIE(desc_id, i), paddr);
  1200. num_entries--;
  1201. desc_id++;
  1202. paddr += link_desc_size;
  1203. }
  1204. }
  1205. hal_srng_access_end_unlocked(soc->hal_soc,
  1206. soc->wbm_idle_link_ring.hal_srng);
  1207. } else {
  1208. uint32_t num_scatter_bufs;
  1209. uint32_t num_entries_per_buf;
  1210. uint32_t rem_entries;
  1211. uint8_t *scatter_buf_ptr;
  1212. uint16_t scatter_buf_num;
  1213. soc->wbm_idle_scatter_buf_size =
  1214. hal_idle_list_scatter_buf_size(soc->hal_soc);
  1215. num_entries_per_buf = hal_idle_scatter_buf_num_entries(
  1216. soc->hal_soc, soc->wbm_idle_scatter_buf_size);
  1217. num_scatter_bufs = hal_idle_list_num_scatter_bufs(
  1218. soc->hal_soc, total_mem_size,
  1219. soc->wbm_idle_scatter_buf_size);
  1220. for (i = 0; i < num_scatter_bufs; i++) {
  1221. soc->wbm_idle_scatter_buf_base_vaddr[i] =
  1222. qdf_mem_alloc_consistent(soc->osdev, soc->osdev->dev,
  1223. soc->wbm_idle_scatter_buf_size,
  1224. &(soc->wbm_idle_scatter_buf_base_paddr[i]));
  1225. if (soc->wbm_idle_scatter_buf_base_vaddr[i] == NULL) {
  1226. QDF_TRACE(QDF_MODULE_ID_DP,
  1227. QDF_TRACE_LEVEL_ERROR,
  1228. FL("Scatter list memory alloc failed"));
  1229. goto fail;
  1230. }
  1231. }
  1232. /* Populate idle list scatter buffers with link descriptor
  1233. * pointers
  1234. */
  1235. scatter_buf_num = 0;
  1236. scatter_buf_ptr = (uint8_t *)(
  1237. soc->wbm_idle_scatter_buf_base_vaddr[scatter_buf_num]);
  1238. rem_entries = num_entries_per_buf;
  1239. for (i = 0; i < MAX_LINK_DESC_BANKS &&
  1240. soc->link_desc_banks[i].base_paddr; i++) {
  1241. uint32_t num_link_descs =
  1242. (soc->link_desc_banks[i].size -
  1243. ((unsigned long)(
  1244. soc->link_desc_banks[i].base_vaddr) -
  1245. (unsigned long)(
  1246. soc->link_desc_banks[i].base_vaddr_unaligned)))
  1247. / link_desc_size;
  1248. unsigned long paddr = (unsigned long)(
  1249. soc->link_desc_banks[i].base_paddr);
  1250. while (num_link_descs) {
  1251. hal_set_link_desc_addr((void *)scatter_buf_ptr,
  1252. LINK_DESC_COOKIE(desc_id, i), paddr);
  1253. num_link_descs--;
  1254. desc_id++;
  1255. paddr += link_desc_size;
  1256. rem_entries--;
  1257. if (rem_entries) {
  1258. scatter_buf_ptr += entry_size;
  1259. } else {
  1260. rem_entries = num_entries_per_buf;
  1261. scatter_buf_num++;
  1262. if (scatter_buf_num >= num_scatter_bufs)
  1263. break;
  1264. scatter_buf_ptr = (uint8_t *)(
  1265. soc->wbm_idle_scatter_buf_base_vaddr[
  1266. scatter_buf_num]);
  1267. }
  1268. }
  1269. }
  1270. /* Setup link descriptor idle list in HW */
  1271. hal_setup_link_idle_list(soc->hal_soc,
  1272. soc->wbm_idle_scatter_buf_base_paddr,
  1273. soc->wbm_idle_scatter_buf_base_vaddr,
  1274. num_scatter_bufs, soc->wbm_idle_scatter_buf_size,
  1275. (uint32_t)(scatter_buf_ptr -
  1276. (uint8_t *)(soc->wbm_idle_scatter_buf_base_vaddr[
  1277. scatter_buf_num-1])), total_link_descs);
  1278. }
  1279. return 0;
  1280. fail:
  1281. if (soc->wbm_idle_link_ring.hal_srng) {
  1282. dp_srng_cleanup(soc->hal_soc, &soc->wbm_idle_link_ring,
  1283. WBM_IDLE_LINK, 0);
  1284. }
  1285. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1286. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1287. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1288. soc->wbm_idle_scatter_buf_size,
  1289. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1290. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1291. }
  1292. }
  1293. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1294. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1295. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1296. soc->link_desc_banks[i].size,
  1297. soc->link_desc_banks[i].base_vaddr_unaligned,
  1298. soc->link_desc_banks[i].base_paddr_unaligned,
  1299. 0);
  1300. }
  1301. }
  1302. return QDF_STATUS_E_FAILURE;
  1303. }
  1304. /*
  1305. * Free link descriptor pool that was setup HW
  1306. */
  1307. static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
  1308. {
  1309. int i;
  1310. if (soc->wbm_idle_link_ring.hal_srng) {
  1311. dp_srng_cleanup(soc, &soc->wbm_idle_link_ring,
  1312. WBM_IDLE_LINK, 0);
  1313. }
  1314. for (i = 0; i < MAX_IDLE_SCATTER_BUFS; i++) {
  1315. if (soc->wbm_idle_scatter_buf_base_vaddr[i]) {
  1316. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1317. soc->wbm_idle_scatter_buf_size,
  1318. soc->wbm_idle_scatter_buf_base_vaddr[i],
  1319. soc->wbm_idle_scatter_buf_base_paddr[i], 0);
  1320. }
  1321. }
  1322. for (i = 0; i < MAX_LINK_DESC_BANKS; i++) {
  1323. if (soc->link_desc_banks[i].base_vaddr_unaligned) {
  1324. qdf_mem_free_consistent(soc->osdev, soc->osdev->dev,
  1325. soc->link_desc_banks[i].size,
  1326. soc->link_desc_banks[i].base_vaddr_unaligned,
  1327. soc->link_desc_banks[i].base_paddr_unaligned,
  1328. 0);
  1329. }
  1330. }
  1331. }
  1332. /* TODO: Following should be configurable */
  1333. #define WBM_RELEASE_RING_SIZE 64
  1334. #define TCL_CMD_RING_SIZE 32
  1335. #define TCL_STATUS_RING_SIZE 32
  1336. #if defined(QCA_WIFI_QCA6290)
  1337. #define REO_DST_RING_SIZE 1024
  1338. #else
  1339. #define REO_DST_RING_SIZE 2048
  1340. #endif
  1341. #define REO_REINJECT_RING_SIZE 32
  1342. #define RX_RELEASE_RING_SIZE 1024
  1343. #define REO_EXCEPTION_RING_SIZE 128
  1344. #define REO_CMD_RING_SIZE 32
  1345. #define REO_STATUS_RING_SIZE 32
  1346. #define RXDMA_BUF_RING_SIZE 1024
  1347. #define RXDMA_REFILL_RING_SIZE 2048
  1348. #define RXDMA_MONITOR_BUF_RING_SIZE 1024
  1349. #define RXDMA_MONITOR_DST_RING_SIZE 1024
  1350. #define RXDMA_MONITOR_STATUS_RING_SIZE 1024
  1351. #define RXDMA_MONITOR_DESC_RING_SIZE 1024
  1352. #define RXDMA_ERR_DST_RING_SIZE 1024
  1353. /*
  1354. * dp_wds_aging_timer_fn() - Timer callback function for WDS aging
  1355. * @soc: Datapath SOC handle
  1356. *
  1357. * This is a timer function used to age out stale WDS nodes from
  1358. * AST table
  1359. */
  1360. #ifdef FEATURE_WDS
  1361. static void dp_wds_aging_timer_fn(void *soc_hdl)
  1362. {
  1363. struct dp_soc *soc = (struct dp_soc *) soc_hdl;
  1364. struct dp_pdev *pdev;
  1365. struct dp_vdev *vdev;
  1366. struct dp_peer *peer;
  1367. struct dp_ast_entry *ase, *temp_ase;
  1368. int i;
  1369. qdf_spin_lock_bh(&soc->ast_lock);
  1370. for (i = 0; i < MAX_PDEV_CNT && soc->pdev_list[i]; i++) {
  1371. pdev = soc->pdev_list[i];
  1372. DP_PDEV_ITERATE_VDEV_LIST(pdev, vdev) {
  1373. DP_VDEV_ITERATE_PEER_LIST(vdev, peer) {
  1374. DP_PEER_ITERATE_ASE_LIST(peer, ase, temp_ase) {
  1375. /*
  1376. * Do not expire static ast entries
  1377. */
  1378. if (ase->type == CDP_TXRX_AST_TYPE_STATIC)
  1379. continue;
  1380. if (ase->is_active) {
  1381. ase->is_active = FALSE;
  1382. continue;
  1383. }
  1384. DP_STATS_INC(soc, ast.aged_out, 1);
  1385. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  1386. pdev->osif_pdev,
  1387. ase->mac_addr.raw);
  1388. dp_peer_del_ast(soc, ase);
  1389. }
  1390. }
  1391. }
  1392. }
  1393. qdf_spin_unlock_bh(&soc->ast_lock);
  1394. if (qdf_atomic_read(&soc->cmn_init_done))
  1395. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1396. }
  1397. /*
  1398. * dp_soc_wds_attach() - Setup WDS timer and AST table
  1399. * @soc: Datapath SOC handle
  1400. *
  1401. * Return: None
  1402. */
  1403. static void dp_soc_wds_attach(struct dp_soc *soc)
  1404. {
  1405. qdf_spinlock_create(&soc->ast_lock);
  1406. qdf_timer_init(soc->osdev, &soc->wds_aging_timer,
  1407. dp_wds_aging_timer_fn, (void *)soc,
  1408. QDF_TIMER_TYPE_WAKE_APPS);
  1409. qdf_timer_mod(&soc->wds_aging_timer, DP_WDS_AGING_TIMER_DEFAULT_MS);
  1410. }
  1411. /*
  1412. * dp_soc_wds_detach() - Detach WDS data structures and timers
  1413. * @txrx_soc: DP SOC handle
  1414. *
  1415. * Return: None
  1416. */
  1417. static void dp_soc_wds_detach(struct dp_soc *soc)
  1418. {
  1419. qdf_timer_stop(&soc->wds_aging_timer);
  1420. qdf_timer_free(&soc->wds_aging_timer);
  1421. qdf_spinlock_destroy(&soc->ast_lock);
  1422. }
  1423. #else
  1424. static void dp_soc_wds_attach(struct dp_soc *soc)
  1425. {
  1426. }
  1427. static void dp_soc_wds_detach(struct dp_soc *soc)
  1428. {
  1429. }
  1430. #endif
  1431. /*
  1432. * dp_soc_reset_ring_map() - Reset cpu ring map
  1433. * @soc: Datapath soc handler
  1434. *
  1435. * This api resets the default cpu ring map
  1436. */
  1437. static void dp_soc_reset_cpu_ring_map(struct dp_soc *soc)
  1438. {
  1439. uint8_t i;
  1440. int nss_config = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1441. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  1442. if (nss_config == 1) {
  1443. /*
  1444. * Setting Tx ring map for one nss offloaded radio
  1445. */
  1446. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_FIRST_RADIO_OFFLOADED_MAP][i];
  1447. } else if (nss_config == 2) {
  1448. /*
  1449. * Setting Tx ring for two nss offloaded radios
  1450. */
  1451. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_SECOND_RADIO_OFFLOADED_MAP][i];
  1452. } else {
  1453. /*
  1454. * Setting Tx ring map for all nss offloaded radios
  1455. */
  1456. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_NSS_ALL_RADIO_OFFLOADED_MAP][i];
  1457. }
  1458. }
  1459. }
  1460. #ifdef IPA_OFFLOAD
  1461. /**
  1462. * dp_reo_remap_config() - configure reo remap register value based
  1463. * nss configuration.
  1464. * based on offload_radio value below remap configuration
  1465. * get applied.
  1466. * 0 - both Radios handled by host (remap rings 1, 2, 3 & 4)
  1467. * 1 - 1st Radio handled by NSS (remap rings 2, 3 & 4)
  1468. * 2 - 2nd Radio handled by NSS (remap rings 1, 2 & 4)
  1469. * 3 - both Radios handled by NSS (remap not required)
  1470. * 4 - IPA OFFLOAD enabled (remap rings 1,2 & 3)
  1471. *
  1472. * @remap1: output parameter indicates reo remap 1 register value
  1473. * @remap2: output parameter indicates reo remap 2 register value
  1474. * Return: bool type, true if remap is configured else false.
  1475. */
  1476. static bool dp_reo_remap_config(struct dp_soc *soc,
  1477. uint32_t *remap1,
  1478. uint32_t *remap2)
  1479. {
  1480. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) | (0x1 << 9) |
  1481. (0x2 << 12) | (0x3 << 15) | (0x1 << 18) | (0x2 << 21)) << 8;
  1482. *remap2 = ((0x3 << 0) | (0x1 << 3) | (0x2 << 6) | (0x3 << 9) |
  1483. (0x1 << 12) | (0x2 << 15) | (0x3 << 18) | (0x1 << 21)) << 8;
  1484. return true;
  1485. }
  1486. #else
  1487. static bool dp_reo_remap_config(struct dp_soc *soc,
  1488. uint32_t *remap1,
  1489. uint32_t *remap2)
  1490. {
  1491. uint8_t offload_radio = wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx);
  1492. switch (offload_radio) {
  1493. case 0:
  1494. *remap1 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1495. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1496. (0x3 << 18) | (0x4 << 21)) << 8;
  1497. *remap2 = ((0x1 << 0) | (0x2 << 3) | (0x3 << 6) |
  1498. (0x4 << 9) | (0x1 << 12) | (0x2 << 15) |
  1499. (0x3 << 18) | (0x4 << 21)) << 8;
  1500. break;
  1501. case 1:
  1502. *remap1 = ((0x2 << 0) | (0x3 << 3) | (0x4 << 6) |
  1503. (0x2 << 9) | (0x3 << 12) | (0x4 << 15) |
  1504. (0x2 << 18) | (0x3 << 21)) << 8;
  1505. *remap2 = ((0x4 << 0) | (0x2 << 3) | (0x3 << 6) |
  1506. (0x4 << 9) | (0x2 << 12) | (0x3 << 15) |
  1507. (0x4 << 18) | (0x2 << 21)) << 8;
  1508. break;
  1509. case 2:
  1510. *remap1 = ((0x1 << 0) | (0x3 << 3) | (0x4 << 6) |
  1511. (0x1 << 9) | (0x3 << 12) | (0x4 << 15) |
  1512. (0x1 << 18) | (0x3 << 21)) << 8;
  1513. *remap2 = ((0x4 << 0) | (0x1 << 3) | (0x3 << 6) |
  1514. (0x4 << 9) | (0x1 << 12) | (0x3 << 15) |
  1515. (0x4 << 18) | (0x1 << 21)) << 8;
  1516. break;
  1517. case 3:
  1518. /* return false if both radios are offloaded to NSS */
  1519. return false;
  1520. }
  1521. return true;
  1522. }
  1523. #endif
  1524. /*
  1525. * dp_soc_cmn_setup() - Common SoC level initializion
  1526. * @soc: Datapath SOC handle
  1527. *
  1528. * This is an internal function used to setup common SOC data structures,
  1529. * to be called from PDEV attach after receiving HW mode capabilities from FW
  1530. */
  1531. static int dp_soc_cmn_setup(struct dp_soc *soc)
  1532. {
  1533. int i;
  1534. struct hal_reo_params reo_params;
  1535. int tx_ring_size;
  1536. int tx_comp_ring_size;
  1537. if (qdf_atomic_read(&soc->cmn_init_done))
  1538. return 0;
  1539. if (dp_peer_find_attach(soc))
  1540. goto fail0;
  1541. if (dp_hw_link_desc_pool_setup(soc))
  1542. goto fail1;
  1543. /* Setup SRNG rings */
  1544. /* Common rings */
  1545. if (dp_srng_setup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0, 0,
  1546. WBM_RELEASE_RING_SIZE)) {
  1547. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1548. FL("dp_srng_setup failed for wbm_desc_rel_ring"));
  1549. goto fail1;
  1550. }
  1551. soc->num_tcl_data_rings = 0;
  1552. /* Tx data rings */
  1553. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1554. soc->num_tcl_data_rings =
  1555. wlan_cfg_num_tcl_data_rings(soc->wlan_cfg_ctx);
  1556. tx_comp_ring_size =
  1557. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1558. tx_ring_size =
  1559. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1560. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  1561. if (dp_srng_setup(soc, &soc->tcl_data_ring[i],
  1562. TCL_DATA, i, 0, tx_ring_size)) {
  1563. QDF_TRACE(QDF_MODULE_ID_DP,
  1564. QDF_TRACE_LEVEL_ERROR,
  1565. FL("dp_srng_setup failed for tcl_data_ring[%d]"), i);
  1566. goto fail1;
  1567. }
  1568. /*
  1569. * TBD: Set IPA WBM ring size with ini IPA UC tx buffer
  1570. * count
  1571. */
  1572. if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
  1573. WBM2SW_RELEASE, i, 0, tx_comp_ring_size)) {
  1574. QDF_TRACE(QDF_MODULE_ID_DP,
  1575. QDF_TRACE_LEVEL_ERROR,
  1576. FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
  1577. goto fail1;
  1578. }
  1579. }
  1580. } else {
  1581. /* This will be incremented during per pdev ring setup */
  1582. soc->num_tcl_data_rings = 0;
  1583. }
  1584. if (dp_tx_soc_attach(soc)) {
  1585. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1586. FL("dp_tx_soc_attach failed"));
  1587. goto fail1;
  1588. }
  1589. /* TCL command and status rings */
  1590. if (dp_srng_setup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0, 0,
  1591. TCL_CMD_RING_SIZE)) {
  1592. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1593. FL("dp_srng_setup failed for tcl_cmd_ring"));
  1594. goto fail1;
  1595. }
  1596. if (dp_srng_setup(soc, &soc->tcl_status_ring, TCL_STATUS, 0, 0,
  1597. TCL_STATUS_RING_SIZE)) {
  1598. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1599. FL("dp_srng_setup failed for tcl_status_ring"));
  1600. goto fail1;
  1601. }
  1602. /* TBD: call dp_tx_init to setup Tx SW descriptors and MSDU extension
  1603. * descriptors
  1604. */
  1605. /* Rx data rings */
  1606. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1607. soc->num_reo_dest_rings =
  1608. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  1609. QDF_TRACE(QDF_MODULE_ID_DP,
  1610. QDF_TRACE_LEVEL_ERROR,
  1611. FL("num_reo_dest_rings %d\n"), soc->num_reo_dest_rings);
  1612. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  1613. if (dp_srng_setup(soc, &soc->reo_dest_ring[i], REO_DST,
  1614. i, 0, REO_DST_RING_SIZE)) {
  1615. QDF_TRACE(QDF_MODULE_ID_DP,
  1616. QDF_TRACE_LEVEL_ERROR,
  1617. FL("dp_srng_setup failed for reo_dest_ring[%d]"), i);
  1618. goto fail1;
  1619. }
  1620. }
  1621. } else {
  1622. /* This will be incremented during per pdev ring setup */
  1623. soc->num_reo_dest_rings = 0;
  1624. }
  1625. /* TBD: call dp_rx_init to setup Rx SW descriptors */
  1626. /* REO reinjection ring */
  1627. if (dp_srng_setup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0, 0,
  1628. REO_REINJECT_RING_SIZE)) {
  1629. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1630. FL("dp_srng_setup failed for reo_reinject_ring"));
  1631. goto fail1;
  1632. }
  1633. /* Rx release ring */
  1634. if (dp_srng_setup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 3, 0,
  1635. RX_RELEASE_RING_SIZE)) {
  1636. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1637. FL("dp_srng_setup failed for rx_rel_ring"));
  1638. goto fail1;
  1639. }
  1640. /* Rx exception ring */
  1641. if (dp_srng_setup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0,
  1642. MAX_REO_DEST_RINGS, REO_EXCEPTION_RING_SIZE)) {
  1643. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1644. FL("dp_srng_setup failed for reo_exception_ring"));
  1645. goto fail1;
  1646. }
  1647. /* REO command and status rings */
  1648. if (dp_srng_setup(soc, &soc->reo_cmd_ring, REO_CMD, 0, 0,
  1649. REO_CMD_RING_SIZE)) {
  1650. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1651. FL("dp_srng_setup failed for reo_cmd_ring"));
  1652. goto fail1;
  1653. }
  1654. hal_reo_init_cmd_ring(soc->hal_soc, soc->reo_cmd_ring.hal_srng);
  1655. TAILQ_INIT(&soc->rx.reo_cmd_list);
  1656. qdf_spinlock_create(&soc->rx.reo_cmd_lock);
  1657. if (dp_srng_setup(soc, &soc->reo_status_ring, REO_STATUS, 0, 0,
  1658. REO_STATUS_RING_SIZE)) {
  1659. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1660. FL("dp_srng_setup failed for reo_status_ring"));
  1661. goto fail1;
  1662. }
  1663. dp_soc_wds_attach(soc);
  1664. /* Reset the cpu ring map if radio is NSS offloaded */
  1665. if (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx)) {
  1666. dp_soc_reset_cpu_ring_map(soc);
  1667. }
  1668. /* Setup HW REO */
  1669. qdf_mem_zero(&reo_params, sizeof(reo_params));
  1670. if (wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1671. /*
  1672. * Reo ring remap is not required if both radios
  1673. * are offloaded to NSS
  1674. */
  1675. if (!dp_reo_remap_config(soc,
  1676. &reo_params.remap1,
  1677. &reo_params.remap2))
  1678. goto out;
  1679. reo_params.rx_hash_enabled = true;
  1680. }
  1681. out:
  1682. hal_reo_setup(soc->hal_soc, &reo_params);
  1683. qdf_atomic_set(&soc->cmn_init_done, 1);
  1684. qdf_nbuf_queue_init(&soc->htt_stats.msg);
  1685. return 0;
  1686. fail1:
  1687. /*
  1688. * Cleanup will be done as part of soc_detach, which will
  1689. * be called on pdev attach failure
  1690. */
  1691. fail0:
  1692. return QDF_STATUS_E_FAILURE;
  1693. }
  1694. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force);
  1695. static void dp_lro_hash_setup(struct dp_soc *soc)
  1696. {
  1697. struct cdp_lro_hash_config lro_hash;
  1698. if (!wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  1699. !wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx)) {
  1700. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1701. FL("LRO disabled RX hash disabled"));
  1702. return;
  1703. }
  1704. qdf_mem_zero(&lro_hash, sizeof(lro_hash));
  1705. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx)) {
  1706. lro_hash.lro_enable = 1;
  1707. lro_hash.tcp_flag = QDF_TCPHDR_ACK;
  1708. lro_hash.tcp_flag_mask = QDF_TCPHDR_FIN | QDF_TCPHDR_SYN |
  1709. QDF_TCPHDR_RST | QDF_TCPHDR_ACK | QDF_TCPHDR_URG |
  1710. QDF_TCPHDR_ECE | QDF_TCPHDR_CWR;
  1711. }
  1712. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, FL("enabled"));
  1713. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv4,
  1714. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1715. LRO_IPV4_SEED_ARR_SZ));
  1716. qdf_get_random_bytes(lro_hash.toeplitz_hash_ipv6,
  1717. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1718. LRO_IPV6_SEED_ARR_SZ));
  1719. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1720. "lro_hash: lro_enable: 0x%x"
  1721. "lro_hash: tcp_flag 0x%x tcp_flag_mask 0x%x",
  1722. lro_hash.lro_enable, lro_hash.tcp_flag,
  1723. lro_hash.tcp_flag_mask);
  1724. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1725. FL("lro_hash: toeplitz_hash_ipv4:"));
  1726. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1727. QDF_TRACE_LEVEL_ERROR,
  1728. (void *)lro_hash.toeplitz_hash_ipv4,
  1729. (sizeof(lro_hash.toeplitz_hash_ipv4[0]) *
  1730. LRO_IPV4_SEED_ARR_SZ));
  1731. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1732. FL("lro_hash: toeplitz_hash_ipv6:"));
  1733. qdf_trace_hex_dump(QDF_MODULE_ID_DP,
  1734. QDF_TRACE_LEVEL_ERROR,
  1735. (void *)lro_hash.toeplitz_hash_ipv6,
  1736. (sizeof(lro_hash.toeplitz_hash_ipv6[0]) *
  1737. LRO_IPV6_SEED_ARR_SZ));
  1738. qdf_assert(soc->cdp_soc.ol_ops->lro_hash_config);
  1739. if (soc->cdp_soc.ol_ops->lro_hash_config)
  1740. (void)soc->cdp_soc.ol_ops->lro_hash_config
  1741. (soc->osif_soc, &lro_hash);
  1742. }
  1743. /*
  1744. * dp_rxdma_ring_setup() - configure the RX DMA rings
  1745. * @soc: data path SoC handle
  1746. * @pdev: Physical device handle
  1747. *
  1748. * Return: 0 - success, > 0 - failure
  1749. */
  1750. #ifdef QCA_HOST2FW_RXBUF_RING
  1751. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1752. struct dp_pdev *pdev)
  1753. {
  1754. int max_mac_rings =
  1755. wlan_cfg_get_num_mac_rings
  1756. (pdev->wlan_cfg_ctx);
  1757. int i;
  1758. for (i = 0; i < max_mac_rings; i++) {
  1759. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1760. "%s: pdev_id %d mac_id %d\n",
  1761. __func__, pdev->pdev_id, i);
  1762. if (dp_srng_setup(soc, &pdev->rx_mac_buf_ring[i],
  1763. RXDMA_BUF, 1, i, RXDMA_BUF_RING_SIZE)) {
  1764. QDF_TRACE(QDF_MODULE_ID_DP,
  1765. QDF_TRACE_LEVEL_ERROR,
  1766. FL("failed rx mac ring setup"));
  1767. return QDF_STATUS_E_FAILURE;
  1768. }
  1769. }
  1770. return QDF_STATUS_SUCCESS;
  1771. }
  1772. #else
  1773. static int dp_rxdma_ring_setup(struct dp_soc *soc,
  1774. struct dp_pdev *pdev)
  1775. {
  1776. return QDF_STATUS_SUCCESS;
  1777. }
  1778. #endif
  1779. /**
  1780. * dp_dscp_tid_map_setup(): Initialize the dscp-tid maps
  1781. * @pdev - DP_PDEV handle
  1782. *
  1783. * Return: void
  1784. */
  1785. static inline void
  1786. dp_dscp_tid_map_setup(struct dp_pdev *pdev)
  1787. {
  1788. uint8_t map_id;
  1789. for (map_id = 0; map_id < DP_MAX_TID_MAPS; map_id++) {
  1790. qdf_mem_copy(pdev->dscp_tid_map[map_id], default_dscp_tid_map,
  1791. sizeof(default_dscp_tid_map));
  1792. }
  1793. for (map_id = 0; map_id < HAL_MAX_HW_DSCP_TID_MAPS; map_id++) {
  1794. hal_tx_set_dscp_tid_map(pdev->soc->hal_soc,
  1795. pdev->dscp_tid_map[map_id],
  1796. map_id);
  1797. }
  1798. }
  1799. /*
  1800. * dp_reset_intr_mask() - reset interrupt mask
  1801. * @dp_soc - DP Soc handle
  1802. * @dp_pdev - DP pdev handle
  1803. *
  1804. * Return: Return void
  1805. */
  1806. static inline
  1807. void dp_soc_reset_intr_mask(struct dp_soc *soc, struct dp_pdev *pdev)
  1808. {
  1809. /*
  1810. * We will set the interrupt mask to zero for NSS offloaded radio
  1811. */
  1812. wlan_cfg_set_tx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1813. wlan_cfg_set_rx_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1814. wlan_cfg_set_rxdma2host_ring_mask(soc->wlan_cfg_ctx, pdev->pdev_id, 0x0);
  1815. }
  1816. /*
  1817. * dp_ipa_ring_resource_setup() - setup IPA ring resources
  1818. * @soc: data path SoC handle
  1819. *
  1820. * Return: none
  1821. */
  1822. #ifdef IPA_OFFLOAD
  1823. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1824. struct dp_pdev *pdev)
  1825. {
  1826. void *hal_srng;
  1827. struct hal_srng_params srng_params;
  1828. qdf_dma_addr_t hp_addr, tp_addr;
  1829. /* IPA TCL_DATA Ring - HAL_SRNG_SW2TCL4 */
  1830. hal_srng = soc->tcl_data_ring[IPA_TCL_DATA_RING_IDX].hal_srng;
  1831. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1832. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_paddr =
  1833. srng_params.ring_base_paddr;
  1834. soc->ipa_uc_tx_rsc.ipa_tcl_ring_base_vaddr =
  1835. srng_params.ring_base_vaddr;
  1836. soc->ipa_uc_tx_rsc.ipa_tcl_ring_size =
  1837. srng_params.num_entries * srng_params.entry_size;
  1838. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1839. soc->ipa_uc_tx_rsc.ipa_tcl_hp_paddr = hp_addr;
  1840. /* IPA TX COMP Ring - HAL_SRNG_WBM2SW3_RELEASE */
  1841. hal_srng = soc->tx_comp_ring[IPA_TX_COMP_RING_IDX].hal_srng;
  1842. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1843. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_paddr =
  1844. srng_params.ring_base_paddr;
  1845. soc->ipa_uc_tx_rsc.ipa_wbm_ring_base_vaddr =
  1846. srng_params.ring_base_vaddr;
  1847. soc->ipa_uc_tx_rsc.ipa_wbm_ring_size =
  1848. srng_params.num_entries * srng_params.entry_size;
  1849. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1850. soc->ipa_uc_tx_rsc.ipa_wbm_tp_paddr = tp_addr;
  1851. /* IPA REO_DEST Ring - HAL_SRNG_REO2SW4 */
  1852. hal_srng = soc->reo_dest_ring[IPA_REO_DEST_RING_IDX].hal_srng;
  1853. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1854. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_paddr =
  1855. srng_params.ring_base_paddr;
  1856. soc->ipa_uc_rx_rsc.ipa_reo_ring_base_vaddr =
  1857. srng_params.ring_base_vaddr;
  1858. soc->ipa_uc_rx_rsc.ipa_reo_ring_size =
  1859. srng_params.num_entries * srng_params.entry_size;
  1860. tp_addr = hal_srng_get_tp_addr(soc->hal_soc, hal_srng);
  1861. soc->ipa_uc_rx_rsc.ipa_reo_tp_paddr = tp_addr;
  1862. /* IPA RX_REFILL_BUF Ring - ipa_rx_refill_buf_ring */
  1863. if (dp_srng_setup(soc, &pdev->ipa_rx_refill_buf_ring, RXDMA_BUF, 2,
  1864. pdev->pdev_id, RXDMA_BUF_RING_SIZE)) {
  1865. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1866. "%s: dp_srng_setup failed IPA rx refill ring\n",
  1867. __func__);
  1868. return -EFAULT;
  1869. }
  1870. hal_srng = pdev->ipa_rx_refill_buf_ring.hal_srng;
  1871. hal_get_srng_params(soc->hal_soc, hal_srng, &srng_params);
  1872. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_paddr =
  1873. srng_params.ring_base_paddr;
  1874. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_base_vaddr =
  1875. srng_params.ring_base_vaddr;
  1876. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_ring_size =
  1877. srng_params.num_entries * srng_params.entry_size;
  1878. hp_addr = hal_srng_get_hp_addr(soc->hal_soc, hal_srng);
  1879. soc->ipa_uc_rx_rsc.ipa_rx_refill_buf_hp_paddr = hp_addr;
  1880. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  1881. "%s: ring_base_paddr:%p, ring_base_vaddr:%p"
  1882. "_entries:%d, hp_addr:%p\n",
  1883. __func__,
  1884. (void *)srng_params.ring_base_paddr,
  1885. (void *)srng_params.ring_base_vaddr,
  1886. srng_params.num_entries,
  1887. (void *)hp_addr);
  1888. return 0;
  1889. }
  1890. #else
  1891. static inline int dp_ipa_ring_resource_setup(struct dp_soc *soc,
  1892. struct dp_pdev *pdev)
  1893. {
  1894. return 0;
  1895. }
  1896. #endif
  1897. /*
  1898. * dp_pdev_attach_wifi3() - attach txrx pdev
  1899. * @osif_pdev: Opaque PDEV handle from OSIF/HDD
  1900. * @txrx_soc: Datapath SOC handle
  1901. * @htc_handle: HTC handle for host-target interface
  1902. * @qdf_osdev: QDF OS device
  1903. * @pdev_id: PDEV ID
  1904. *
  1905. * Return: DP PDEV handle on success, NULL on failure
  1906. */
  1907. static struct cdp_pdev *dp_pdev_attach_wifi3(struct cdp_soc_t *txrx_soc,
  1908. struct cdp_cfg *ctrl_pdev,
  1909. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev, uint8_t pdev_id)
  1910. {
  1911. int tx_ring_size;
  1912. int tx_comp_ring_size;
  1913. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  1914. struct dp_pdev *pdev = qdf_mem_malloc(sizeof(*pdev));
  1915. if (!pdev) {
  1916. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1917. FL("DP PDEV memory allocation failed"));
  1918. goto fail0;
  1919. }
  1920. pdev->wlan_cfg_ctx = wlan_cfg_pdev_attach();
  1921. if (!pdev->wlan_cfg_ctx) {
  1922. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1923. FL("pdev cfg_attach failed"));
  1924. qdf_mem_free(pdev);
  1925. goto fail0;
  1926. }
  1927. /*
  1928. * set nss pdev config based on soc config
  1929. */
  1930. wlan_cfg_set_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx,
  1931. (wlan_cfg_get_dp_soc_nss_cfg(soc->wlan_cfg_ctx) & (1 << pdev_id)));
  1932. pdev->soc = soc;
  1933. pdev->osif_pdev = ctrl_pdev;
  1934. pdev->pdev_id = pdev_id;
  1935. soc->pdev_list[pdev_id] = pdev;
  1936. soc->pdev_count++;
  1937. TAILQ_INIT(&pdev->vdev_list);
  1938. pdev->vdev_count = 0;
  1939. qdf_spinlock_create(&pdev->tx_mutex);
  1940. qdf_spinlock_create(&pdev->neighbour_peer_mutex);
  1941. TAILQ_INIT(&pdev->neighbour_peers_list);
  1942. if (dp_soc_cmn_setup(soc)) {
  1943. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1944. FL("dp_soc_cmn_setup failed"));
  1945. goto fail1;
  1946. }
  1947. /* Setup per PDEV TCL rings if configured */
  1948. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  1949. tx_ring_size =
  1950. wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  1951. tx_comp_ring_size =
  1952. wlan_cfg_tx_comp_ring_size(soc->wlan_cfg_ctx);
  1953. if (dp_srng_setup(soc, &soc->tcl_data_ring[pdev_id], TCL_DATA,
  1954. pdev_id, pdev_id, tx_ring_size)) {
  1955. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1956. FL("dp_srng_setup failed for tcl_data_ring"));
  1957. goto fail1;
  1958. }
  1959. if (dp_srng_setup(soc, &soc->tx_comp_ring[pdev_id],
  1960. WBM2SW_RELEASE, pdev_id, pdev_id, tx_comp_ring_size)) {
  1961. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1962. FL("dp_srng_setup failed for tx_comp_ring"));
  1963. goto fail1;
  1964. }
  1965. soc->num_tcl_data_rings++;
  1966. }
  1967. /* Tx specific init */
  1968. if (dp_tx_pdev_attach(pdev)) {
  1969. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1970. FL("dp_tx_pdev_attach failed"));
  1971. goto fail1;
  1972. }
  1973. /* Setup per PDEV REO rings if configured */
  1974. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  1975. if (dp_srng_setup(soc, &soc->reo_dest_ring[pdev_id], REO_DST,
  1976. pdev_id, pdev_id, REO_DST_RING_SIZE)) {
  1977. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1978. FL("dp_srng_setup failed for reo_dest_ringn"));
  1979. goto fail1;
  1980. }
  1981. soc->num_reo_dest_rings++;
  1982. }
  1983. if (dp_srng_setup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0, pdev_id,
  1984. RXDMA_REFILL_RING_SIZE)) {
  1985. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1986. FL("dp_srng_setup failed rx refill ring"));
  1987. goto fail1;
  1988. }
  1989. if (dp_rxdma_ring_setup(soc, pdev)) {
  1990. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1991. FL("RXDMA ring config failed"));
  1992. goto fail1;
  1993. }
  1994. if (dp_srng_setup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0,
  1995. pdev_id, RXDMA_MONITOR_BUF_RING_SIZE)) {
  1996. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  1997. FL("dp_srng_setup failed for rxdma_mon_buf_ring"));
  1998. goto fail1;
  1999. }
  2000. if (dp_srng_setup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0,
  2001. pdev_id, RXDMA_MONITOR_DST_RING_SIZE)) {
  2002. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2003. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2004. goto fail1;
  2005. }
  2006. if (dp_srng_setup(soc, &pdev->rxdma_mon_status_ring,
  2007. RXDMA_MONITOR_STATUS, 0, pdev_id,
  2008. RXDMA_MONITOR_STATUS_RING_SIZE)) {
  2009. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2010. FL("dp_srng_setup failed for rxdma_mon_status_ring"));
  2011. goto fail1;
  2012. }
  2013. if (dp_srng_setup(soc, &pdev->rxdma_mon_desc_ring,
  2014. RXDMA_MONITOR_DESC, 0, pdev_id, RXDMA_MONITOR_DESC_RING_SIZE)) {
  2015. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2016. "dp_srng_setup failed for rxdma_mon_desc_ring\n");
  2017. goto fail1;
  2018. }
  2019. if (dp_srng_setup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0,
  2020. pdev_id, RXDMA_ERR_DST_RING_SIZE)) {
  2021. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2022. FL("dp_srng_setup failed for rxdma_mon_dst_ring"));
  2023. goto fail1;
  2024. }
  2025. if (dp_ipa_ring_resource_setup(soc, pdev))
  2026. goto fail1;
  2027. if (dp_ipa_uc_attach(soc, pdev) != QDF_STATUS_SUCCESS) {
  2028. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2029. "%s: dp_ipa_uc_attach failed\n", __func__);
  2030. goto fail1;
  2031. }
  2032. /* Rx specific init */
  2033. if (dp_rx_pdev_attach(pdev)) {
  2034. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2035. FL("dp_rx_pdev_attach failed "));
  2036. goto fail0;
  2037. }
  2038. DP_STATS_INIT(pdev);
  2039. #ifndef CONFIG_WIN
  2040. /* MCL */
  2041. dp_local_peer_id_pool_init(pdev);
  2042. #endif
  2043. dp_dscp_tid_map_setup(pdev);
  2044. /* Rx monitor mode specific init */
  2045. if (dp_rx_pdev_mon_attach(pdev)) {
  2046. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2047. "dp_rx_pdev_attach failed\n");
  2048. goto fail1;
  2049. }
  2050. if (dp_wdi_event_attach(pdev)) {
  2051. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2052. "dp_wdi_evet_attach failed\n");
  2053. goto fail1;
  2054. }
  2055. /* set the reo destination during initialization */
  2056. pdev->reo_dest = pdev->pdev_id + 1;
  2057. /*
  2058. * reset the interrupt mask for offloaded radio
  2059. */
  2060. if (wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx)) {
  2061. dp_soc_reset_intr_mask(soc, pdev);
  2062. }
  2063. return (struct cdp_pdev *)pdev;
  2064. fail1:
  2065. dp_pdev_detach_wifi3((struct cdp_pdev *)pdev, 0);
  2066. fail0:
  2067. return NULL;
  2068. }
  2069. /*
  2070. * dp_rxdma_ring_cleanup() - configure the RX DMA rings
  2071. * @soc: data path SoC handle
  2072. * @pdev: Physical device handle
  2073. *
  2074. * Return: void
  2075. */
  2076. #ifdef QCA_HOST2FW_RXBUF_RING
  2077. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2078. struct dp_pdev *pdev)
  2079. {
  2080. int max_mac_rings =
  2081. wlan_cfg_get_num_mac_rings(pdev->wlan_cfg_ctx);
  2082. int i;
  2083. max_mac_rings = max_mac_rings < MAX_RX_MAC_RINGS ?
  2084. max_mac_rings : MAX_RX_MAC_RINGS;
  2085. for (i = 0; i < MAX_RX_MAC_RINGS; i++)
  2086. dp_srng_cleanup(soc, &pdev->rx_mac_buf_ring[i],
  2087. RXDMA_BUF, 1);
  2088. }
  2089. #else
  2090. static void dp_rxdma_ring_cleanup(struct dp_soc *soc,
  2091. struct dp_pdev *pdev)
  2092. {
  2093. }
  2094. #endif
  2095. /*
  2096. * dp_neighbour_peers_detach() - Detach neighbour peers(nac clients)
  2097. * @pdev: device object
  2098. *
  2099. * Return: void
  2100. */
  2101. static void dp_neighbour_peers_detach(struct dp_pdev *pdev)
  2102. {
  2103. struct dp_neighbour_peer *peer = NULL;
  2104. struct dp_neighbour_peer *temp_peer = NULL;
  2105. TAILQ_FOREACH_SAFE(peer, &pdev->neighbour_peers_list,
  2106. neighbour_peer_list_elem, temp_peer) {
  2107. /* delete this peer from the list */
  2108. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2109. peer, neighbour_peer_list_elem);
  2110. qdf_mem_free(peer);
  2111. }
  2112. qdf_spinlock_destroy(&pdev->neighbour_peer_mutex);
  2113. }
  2114. /*
  2115. * dp_pdev_detach_wifi3() - detach txrx pdev
  2116. * @txrx_pdev: Datapath PDEV handle
  2117. * @force: Force detach
  2118. *
  2119. */
  2120. static void dp_pdev_detach_wifi3(struct cdp_pdev *txrx_pdev, int force)
  2121. {
  2122. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2123. struct dp_soc *soc = pdev->soc;
  2124. dp_wdi_event_detach(pdev);
  2125. dp_tx_pdev_detach(pdev);
  2126. if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2127. dp_srng_cleanup(soc, &soc->tcl_data_ring[pdev->pdev_id],
  2128. TCL_DATA, pdev->pdev_id);
  2129. dp_srng_cleanup(soc, &soc->tx_comp_ring[pdev->pdev_id],
  2130. WBM2SW_RELEASE, pdev->pdev_id);
  2131. }
  2132. dp_rx_pdev_detach(pdev);
  2133. dp_rx_pdev_mon_detach(pdev);
  2134. dp_neighbour_peers_detach(pdev);
  2135. qdf_spinlock_destroy(&pdev->tx_mutex);
  2136. dp_ipa_uc_detach(soc, pdev);
  2137. /* Cleanup per PDEV REO rings if configured */
  2138. if (wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2139. dp_srng_cleanup(soc, &soc->reo_dest_ring[pdev->pdev_id],
  2140. REO_DST, pdev->pdev_id);
  2141. }
  2142. dp_srng_cleanup(soc, &pdev->rx_refill_buf_ring, RXDMA_BUF, 0);
  2143. dp_rxdma_ring_cleanup(soc, pdev);
  2144. dp_srng_cleanup(soc, &pdev->rxdma_mon_buf_ring, RXDMA_MONITOR_BUF, 0);
  2145. dp_srng_cleanup(soc, &pdev->rxdma_mon_dst_ring, RXDMA_MONITOR_DST, 0);
  2146. dp_srng_cleanup(soc, &pdev->rxdma_mon_status_ring,
  2147. RXDMA_MONITOR_STATUS, 0);
  2148. dp_srng_cleanup(soc, &pdev->rxdma_mon_desc_ring,
  2149. RXDMA_MONITOR_DESC, 0);
  2150. dp_srng_cleanup(soc, &pdev->rxdma_err_dst_ring, RXDMA_DST, 0);
  2151. soc->pdev_list[pdev->pdev_id] = NULL;
  2152. soc->pdev_count--;
  2153. wlan_cfg_pdev_detach(pdev->wlan_cfg_ctx);
  2154. qdf_mem_free(pdev);
  2155. }
  2156. /*
  2157. * dp_reo_desc_freelist_destroy() - Flush REO descriptors from deferred freelist
  2158. * @soc: DP SOC handle
  2159. */
  2160. static inline void dp_reo_desc_freelist_destroy(struct dp_soc *soc)
  2161. {
  2162. struct reo_desc_list_node *desc;
  2163. struct dp_rx_tid *rx_tid;
  2164. qdf_spin_lock_bh(&soc->reo_desc_freelist_lock);
  2165. while (qdf_list_remove_front(&soc->reo_desc_freelist,
  2166. (qdf_list_node_t **)&desc) == QDF_STATUS_SUCCESS) {
  2167. rx_tid = &desc->rx_tid;
  2168. qdf_mem_unmap_nbytes_single(soc->osdev,
  2169. rx_tid->hw_qdesc_paddr,
  2170. QDF_DMA_BIDIRECTIONAL,
  2171. rx_tid->hw_qdesc_alloc_size);
  2172. qdf_mem_free(rx_tid->hw_qdesc_vaddr_unaligned);
  2173. qdf_mem_free(desc);
  2174. }
  2175. qdf_spin_unlock_bh(&soc->reo_desc_freelist_lock);
  2176. qdf_list_destroy(&soc->reo_desc_freelist);
  2177. qdf_spinlock_destroy(&soc->reo_desc_freelist_lock);
  2178. }
  2179. /*
  2180. * dp_soc_detach_wifi3() - Detach txrx SOC
  2181. * @txrx_soc: DP SOC handle, struct cdp_soc_t is first element of struct dp_soc.
  2182. */
  2183. static void dp_soc_detach_wifi3(void *txrx_soc)
  2184. {
  2185. struct dp_soc *soc = (struct dp_soc *)txrx_soc;
  2186. int i;
  2187. qdf_atomic_set(&soc->cmn_init_done, 0);
  2188. qdf_flush_work(0, &soc->htt_stats.work);
  2189. qdf_disable_work(0, &soc->htt_stats.work);
  2190. /* Free pending htt stats messages */
  2191. qdf_nbuf_queue_free(&soc->htt_stats.msg);
  2192. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2193. if (soc->pdev_list[i])
  2194. dp_pdev_detach_wifi3(
  2195. (struct cdp_pdev *)soc->pdev_list[i], 1);
  2196. }
  2197. dp_peer_find_detach(soc);
  2198. /* TBD: Call Tx and Rx cleanup functions to free buffers and
  2199. * SW descriptors
  2200. */
  2201. /* Free the ring memories */
  2202. /* Common rings */
  2203. dp_srng_cleanup(soc, &soc->wbm_desc_rel_ring, SW2WBM_RELEASE, 0);
  2204. dp_tx_soc_detach(soc);
  2205. /* Tx data rings */
  2206. if (!wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
  2207. for (i = 0; i < soc->num_tcl_data_rings; i++) {
  2208. dp_srng_cleanup(soc, &soc->tcl_data_ring[i],
  2209. TCL_DATA, i);
  2210. dp_srng_cleanup(soc, &soc->tx_comp_ring[i],
  2211. WBM2SW_RELEASE, i);
  2212. }
  2213. }
  2214. /* TCL command and status rings */
  2215. dp_srng_cleanup(soc, &soc->tcl_cmd_ring, TCL_CMD, 0);
  2216. dp_srng_cleanup(soc, &soc->tcl_status_ring, TCL_STATUS, 0);
  2217. /* Rx data rings */
  2218. if (!wlan_cfg_per_pdev_rx_ring(soc->wlan_cfg_ctx)) {
  2219. soc->num_reo_dest_rings =
  2220. wlan_cfg_num_reo_dest_rings(soc->wlan_cfg_ctx);
  2221. for (i = 0; i < soc->num_reo_dest_rings; i++) {
  2222. /* TODO: Get number of rings and ring sizes
  2223. * from wlan_cfg
  2224. */
  2225. dp_srng_cleanup(soc, &soc->reo_dest_ring[i],
  2226. REO_DST, i);
  2227. }
  2228. }
  2229. /* REO reinjection ring */
  2230. dp_srng_cleanup(soc, &soc->reo_reinject_ring, REO_REINJECT, 0);
  2231. /* Rx release ring */
  2232. dp_srng_cleanup(soc, &soc->rx_rel_ring, WBM2SW_RELEASE, 0);
  2233. /* Rx exception ring */
  2234. /* TODO: Better to store ring_type and ring_num in
  2235. * dp_srng during setup
  2236. */
  2237. dp_srng_cleanup(soc, &soc->reo_exception_ring, REO_EXCEPTION, 0);
  2238. /* REO command and status rings */
  2239. dp_srng_cleanup(soc, &soc->reo_cmd_ring, REO_CMD, 0);
  2240. dp_srng_cleanup(soc, &soc->reo_status_ring, REO_STATUS, 0);
  2241. dp_hw_link_desc_pool_cleanup(soc);
  2242. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2243. qdf_spinlock_destroy(&soc->peer_ref_mutex);
  2244. qdf_spinlock_destroy(&soc->htt_stats.lock);
  2245. htt_soc_detach(soc->htt_handle);
  2246. dp_reo_cmdlist_destroy(soc);
  2247. qdf_spinlock_destroy(&soc->rx.reo_cmd_lock);
  2248. dp_reo_desc_freelist_destroy(soc);
  2249. wlan_cfg_soc_detach(soc->wlan_cfg_ctx);
  2250. dp_soc_wds_detach(soc);
  2251. qdf_mem_free(soc);
  2252. }
  2253. /*
  2254. * dp_setup_ipa_rx_refill_buf_ring() - setup IPA RX Refill buffer ring
  2255. * @soc: data path SoC handle
  2256. * @pdev: physical device handle
  2257. *
  2258. * Return: void
  2259. */
  2260. #ifdef IPA_OFFLOAD
  2261. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2262. struct dp_pdev *pdev)
  2263. {
  2264. htt_srng_setup(soc->htt_handle, 0,
  2265. pdev->ipa_rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2266. }
  2267. #else
  2268. static inline void dp_config_ipa_rx_refill_buf_ring(struct dp_soc *soc,
  2269. struct dp_pdev *pdev)
  2270. {
  2271. }
  2272. #endif
  2273. /*
  2274. * dp_rxdma_ring_config() - configure the RX DMA rings
  2275. *
  2276. * This function is used to configure the MAC rings.
  2277. * On MCL host provides buffers in Host2FW ring
  2278. * FW refills (copies) buffers to the ring and updates
  2279. * ring_idx in register
  2280. *
  2281. * @soc: data path SoC handle
  2282. *
  2283. * Return: void
  2284. */
  2285. #ifdef QCA_HOST2FW_RXBUF_RING
  2286. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2287. {
  2288. int i;
  2289. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2290. struct dp_pdev *pdev = soc->pdev_list[i];
  2291. if (pdev) {
  2292. int mac_id = 0;
  2293. int j;
  2294. bool dbs_enable = 0;
  2295. int max_mac_rings =
  2296. wlan_cfg_get_num_mac_rings
  2297. (pdev->wlan_cfg_ctx);
  2298. htt_srng_setup(soc->htt_handle, 0,
  2299. pdev->rx_refill_buf_ring.hal_srng,
  2300. RXDMA_BUF);
  2301. dp_config_ipa_rx_refill_buf_ring(soc, pdev);
  2302. if (soc->cdp_soc.ol_ops->
  2303. is_hw_dbs_2x2_capable) {
  2304. dbs_enable = soc->cdp_soc.ol_ops->
  2305. is_hw_dbs_2x2_capable(soc->psoc);
  2306. }
  2307. if (dbs_enable) {
  2308. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2309. QDF_TRACE_LEVEL_ERROR,
  2310. FL("DBS enabled max_mac_rings %d\n"),
  2311. max_mac_rings);
  2312. } else {
  2313. max_mac_rings = 1;
  2314. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2315. QDF_TRACE_LEVEL_ERROR,
  2316. FL("DBS disabled, max_mac_rings %d\n"),
  2317. max_mac_rings);
  2318. }
  2319. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2320. FL("pdev_id %d max_mac_rings %d\n"),
  2321. pdev->pdev_id, max_mac_rings);
  2322. for (j = 0; j < max_mac_rings; j++) {
  2323. QDF_TRACE(QDF_MODULE_ID_TXRX,
  2324. QDF_TRACE_LEVEL_ERROR,
  2325. FL("mac_id %d\n"), mac_id);
  2326. htt_srng_setup(soc->htt_handle, mac_id,
  2327. pdev->rx_mac_buf_ring[j]
  2328. .hal_srng,
  2329. RXDMA_BUF);
  2330. mac_id++;
  2331. }
  2332. /* Configure monitor mode rings */
  2333. htt_srng_setup(soc->htt_handle, i,
  2334. pdev->rxdma_mon_buf_ring.hal_srng,
  2335. RXDMA_MONITOR_BUF);
  2336. htt_srng_setup(soc->htt_handle, i,
  2337. pdev->rxdma_mon_dst_ring.hal_srng,
  2338. RXDMA_MONITOR_DST);
  2339. htt_srng_setup(soc->htt_handle, i,
  2340. pdev->rxdma_mon_status_ring.hal_srng,
  2341. RXDMA_MONITOR_STATUS);
  2342. htt_srng_setup(soc->htt_handle, i,
  2343. pdev->rxdma_mon_desc_ring.hal_srng,
  2344. RXDMA_MONITOR_DESC);
  2345. htt_srng_setup(soc->htt_handle, i,
  2346. pdev->rxdma_err_dst_ring.hal_srng,
  2347. RXDMA_DST);
  2348. }
  2349. }
  2350. }
  2351. #else
  2352. static void dp_rxdma_ring_config(struct dp_soc *soc)
  2353. {
  2354. int i;
  2355. for (i = 0; i < MAX_PDEV_CNT; i++) {
  2356. struct dp_pdev *pdev = soc->pdev_list[i];
  2357. if (pdev) {
  2358. htt_srng_setup(soc->htt_handle, i,
  2359. pdev->rx_refill_buf_ring.hal_srng, RXDMA_BUF);
  2360. htt_srng_setup(soc->htt_handle, i,
  2361. pdev->rxdma_mon_buf_ring.hal_srng,
  2362. RXDMA_MONITOR_BUF);
  2363. htt_srng_setup(soc->htt_handle, i,
  2364. pdev->rxdma_mon_dst_ring.hal_srng,
  2365. RXDMA_MONITOR_DST);
  2366. htt_srng_setup(soc->htt_handle, i,
  2367. pdev->rxdma_mon_status_ring.hal_srng,
  2368. RXDMA_MONITOR_STATUS);
  2369. htt_srng_setup(soc->htt_handle, i,
  2370. pdev->rxdma_mon_desc_ring.hal_srng,
  2371. RXDMA_MONITOR_DESC);
  2372. htt_srng_setup(soc->htt_handle, i,
  2373. pdev->rxdma_err_dst_ring.hal_srng,
  2374. RXDMA_DST);
  2375. }
  2376. }
  2377. }
  2378. #endif
  2379. /*
  2380. * dp_soc_attach_target_wifi3() - SOC initialization in the target
  2381. * @txrx_soc: Datapath SOC handle
  2382. */
  2383. static int dp_soc_attach_target_wifi3(struct cdp_soc_t *cdp_soc)
  2384. {
  2385. struct dp_soc *soc = (struct dp_soc *)cdp_soc;
  2386. htt_soc_attach_target(soc->htt_handle);
  2387. dp_rxdma_ring_config(soc);
  2388. DP_STATS_INIT(soc);
  2389. /* initialize work queue for stats processing */
  2390. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  2391. return 0;
  2392. }
  2393. /*
  2394. * dp_soc_get_nss_cfg_wifi3() - SOC get nss config
  2395. * @txrx_soc: Datapath SOC handle
  2396. */
  2397. static int dp_soc_get_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc)
  2398. {
  2399. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2400. return wlan_cfg_get_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx);
  2401. }
  2402. /*
  2403. * dp_soc_set_nss_cfg_wifi3() - SOC set nss config
  2404. * @txrx_soc: Datapath SOC handle
  2405. * @nss_cfg: nss config
  2406. */
  2407. static void dp_soc_set_nss_cfg_wifi3(struct cdp_soc_t *cdp_soc, int config)
  2408. {
  2409. struct dp_soc *dsoc = (struct dp_soc *)cdp_soc;
  2410. wlan_cfg_set_dp_soc_nss_cfg(dsoc->wlan_cfg_ctx, config);
  2411. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2412. FL("nss-wifi<0> nss config is enabled"));
  2413. }
  2414. /*
  2415. * dp_vdev_attach_wifi3() - attach txrx vdev
  2416. * @txrx_pdev: Datapath PDEV handle
  2417. * @vdev_mac_addr: MAC address of the virtual interface
  2418. * @vdev_id: VDEV Id
  2419. * @wlan_op_mode: VDEV operating mode
  2420. *
  2421. * Return: DP VDEV handle on success, NULL on failure
  2422. */
  2423. static struct cdp_vdev *dp_vdev_attach_wifi3(struct cdp_pdev *txrx_pdev,
  2424. uint8_t *vdev_mac_addr, uint8_t vdev_id, enum wlan_op_mode op_mode)
  2425. {
  2426. struct dp_pdev *pdev = (struct dp_pdev *)txrx_pdev;
  2427. struct dp_soc *soc = pdev->soc;
  2428. struct dp_vdev *vdev = qdf_mem_malloc(sizeof(*vdev));
  2429. int tx_ring_size;
  2430. if (!vdev) {
  2431. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2432. FL("DP VDEV memory allocation failed"));
  2433. goto fail0;
  2434. }
  2435. vdev->pdev = pdev;
  2436. vdev->vdev_id = vdev_id;
  2437. vdev->opmode = op_mode;
  2438. vdev->osdev = soc->osdev;
  2439. vdev->osif_rx = NULL;
  2440. vdev->osif_rsim_rx_decap = NULL;
  2441. vdev->osif_get_key = NULL;
  2442. vdev->osif_rx_mon = NULL;
  2443. vdev->osif_tx_free_ext = NULL;
  2444. vdev->osif_vdev = NULL;
  2445. vdev->delete.pending = 0;
  2446. vdev->safemode = 0;
  2447. vdev->drop_unenc = 1;
  2448. #ifdef notyet
  2449. vdev->filters_num = 0;
  2450. #endif
  2451. qdf_mem_copy(
  2452. &vdev->mac_addr.raw[0], vdev_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2453. vdev->tx_encap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2454. vdev->rx_decap_type = wlan_cfg_pkt_type(soc->wlan_cfg_ctx);
  2455. vdev->dscp_tid_map_id = 0;
  2456. vdev->mcast_enhancement_en = 0;
  2457. tx_ring_size = wlan_cfg_tx_ring_size(soc->wlan_cfg_ctx);
  2458. /* TODO: Initialize default HTT meta data that will be used in
  2459. * TCL descriptors for packets transmitted from this VDEV
  2460. */
  2461. TAILQ_INIT(&vdev->peer_list);
  2462. /* add this vdev into the pdev's list */
  2463. TAILQ_INSERT_TAIL(&pdev->vdev_list, vdev, vdev_list_elem);
  2464. pdev->vdev_count++;
  2465. dp_tx_vdev_attach(vdev);
  2466. if (QDF_STATUS_SUCCESS != dp_tx_flow_pool_map_handler(pdev, vdev_id,
  2467. FLOW_TYPE_VDEV, vdev_id, tx_ring_size))
  2468. goto fail1;
  2469. if ((soc->intr_mode == DP_INTR_POLL) &&
  2470. wlan_cfg_get_num_contexts(soc->wlan_cfg_ctx) != 0) {
  2471. if (pdev->vdev_count == 1)
  2472. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  2473. }
  2474. dp_lro_hash_setup(soc);
  2475. /* LRO */
  2476. if (wlan_cfg_is_lro_enabled(soc->wlan_cfg_ctx) &&
  2477. wlan_op_mode_sta == vdev->opmode)
  2478. vdev->lro_enable = true;
  2479. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2480. "LRO: vdev_id %d lro_enable %d", vdev_id, vdev->lro_enable);
  2481. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2482. "Created vdev %p (%pM)", vdev, vdev->mac_addr.raw);
  2483. DP_STATS_INIT(vdev);
  2484. return (struct cdp_vdev *)vdev;
  2485. fail1:
  2486. dp_tx_vdev_detach(vdev);
  2487. qdf_mem_free(vdev);
  2488. fail0:
  2489. return NULL;
  2490. }
  2491. /**
  2492. * dp_vdev_register_wifi3() - Register VDEV operations from osif layer
  2493. * @vdev: Datapath VDEV handle
  2494. * @osif_vdev: OSIF vdev handle
  2495. * @txrx_ops: Tx and Rx operations
  2496. *
  2497. * Return: DP VDEV handle on success, NULL on failure
  2498. */
  2499. static void dp_vdev_register_wifi3(struct cdp_vdev *vdev_handle,
  2500. void *osif_vdev,
  2501. struct ol_txrx_ops *txrx_ops)
  2502. {
  2503. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2504. vdev->osif_vdev = osif_vdev;
  2505. vdev->osif_rx = txrx_ops->rx.rx;
  2506. vdev->osif_rsim_rx_decap = txrx_ops->rx.rsim_rx_decap;
  2507. vdev->osif_get_key = txrx_ops->get_key;
  2508. vdev->osif_rx_mon = txrx_ops->rx.mon;
  2509. vdev->osif_tx_free_ext = txrx_ops->tx.tx_free_ext;
  2510. #ifdef notyet
  2511. #if ATH_SUPPORT_WAPI
  2512. vdev->osif_check_wai = txrx_ops->rx.wai_check;
  2513. #endif
  2514. #endif
  2515. #ifdef UMAC_SUPPORT_PROXY_ARP
  2516. vdev->osif_proxy_arp = txrx_ops->proxy_arp;
  2517. #endif
  2518. vdev->me_convert = txrx_ops->me_convert;
  2519. /* TODO: Enable the following once Tx code is integrated */
  2520. txrx_ops->tx.tx = dp_tx_send;
  2521. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2522. "DP Vdev Register success");
  2523. }
  2524. /*
  2525. * dp_vdev_detach_wifi3() - Detach txrx vdev
  2526. * @txrx_vdev: Datapath VDEV handle
  2527. * @callback: Callback OL_IF on completion of detach
  2528. * @cb_context: Callback context
  2529. *
  2530. */
  2531. static void dp_vdev_detach_wifi3(struct cdp_vdev *vdev_handle,
  2532. ol_txrx_vdev_delete_cb callback, void *cb_context)
  2533. {
  2534. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2535. struct dp_pdev *pdev = vdev->pdev;
  2536. struct dp_soc *soc = pdev->soc;
  2537. /* preconditions */
  2538. qdf_assert(vdev);
  2539. /* remove the vdev from its parent pdev's list */
  2540. TAILQ_REMOVE(&pdev->vdev_list, vdev, vdev_list_elem);
  2541. /*
  2542. * Use peer_ref_mutex while accessing peer_list, in case
  2543. * a peer is in the process of being removed from the list.
  2544. */
  2545. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2546. /* check that the vdev has no peers allocated */
  2547. if (!TAILQ_EMPTY(&vdev->peer_list)) {
  2548. /* debug print - will be removed later */
  2549. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2550. FL("not deleting vdev object %p (%pM)"
  2551. "until deletion finishes for all its peers"),
  2552. vdev, vdev->mac_addr.raw);
  2553. /* indicate that the vdev needs to be deleted */
  2554. vdev->delete.pending = 1;
  2555. vdev->delete.callback = callback;
  2556. vdev->delete.context = cb_context;
  2557. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2558. return;
  2559. }
  2560. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2561. dp_tx_flow_pool_unmap_handler(pdev, vdev->vdev_id, FLOW_TYPE_VDEV,
  2562. vdev->vdev_id);
  2563. dp_tx_vdev_detach(vdev);
  2564. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2565. FL("deleting vdev object %p (%pM)"), vdev, vdev->mac_addr.raw);
  2566. qdf_mem_free(vdev);
  2567. if (callback)
  2568. callback(cb_context);
  2569. }
  2570. /*
  2571. * dp_peer_create_wifi3() - attach txrx peer
  2572. * @txrx_vdev: Datapath VDEV handle
  2573. * @peer_mac_addr: Peer MAC address
  2574. *
  2575. * Return: DP peeer handle on success, NULL on failure
  2576. */
  2577. static void *dp_peer_create_wifi3(struct cdp_vdev *vdev_handle,
  2578. uint8_t *peer_mac_addr)
  2579. {
  2580. struct dp_peer *peer;
  2581. int i;
  2582. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2583. struct dp_pdev *pdev;
  2584. struct dp_soc *soc;
  2585. /* preconditions */
  2586. qdf_assert(vdev);
  2587. qdf_assert(peer_mac_addr);
  2588. pdev = vdev->pdev;
  2589. soc = pdev->soc;
  2590. #ifdef notyet
  2591. peer = (struct dp_peer *)qdf_mempool_alloc(soc->osdev,
  2592. soc->mempool_ol_ath_peer);
  2593. #else
  2594. peer = (struct dp_peer *)qdf_mem_malloc(sizeof(*peer));
  2595. #endif
  2596. if (!peer)
  2597. return NULL; /* failure */
  2598. qdf_mem_zero(peer, sizeof(struct dp_peer));
  2599. TAILQ_INIT(&peer->ast_entry_list);
  2600. /* store provided params */
  2601. peer->vdev = vdev;
  2602. dp_peer_add_ast(soc, peer, peer_mac_addr, 1);
  2603. qdf_spinlock_create(&peer->peer_info_lock);
  2604. qdf_mem_copy(
  2605. &peer->mac_addr.raw[0], peer_mac_addr, OL_TXRX_MAC_ADDR_LEN);
  2606. /* TODO: See of rx_opt_proc is really required */
  2607. peer->rx_opt_proc = soc->rx_opt_proc;
  2608. /* initialize the peer_id */
  2609. for (i = 0; i < MAX_NUM_PEER_ID_PER_PEER; i++)
  2610. peer->peer_ids[i] = HTT_INVALID_PEER;
  2611. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2612. qdf_atomic_init(&peer->ref_cnt);
  2613. /* keep one reference for attach */
  2614. qdf_atomic_inc(&peer->ref_cnt);
  2615. /* add this peer into the vdev's list */
  2616. TAILQ_INSERT_TAIL(&vdev->peer_list, peer, peer_list_elem);
  2617. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2618. /* TODO: See if hash based search is required */
  2619. dp_peer_find_hash_add(soc, peer);
  2620. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2621. "vdev %p created peer %p (%pM) ref_cnt: %d",
  2622. vdev, peer, peer->mac_addr.raw,
  2623. qdf_atomic_read(&peer->ref_cnt));
  2624. /*
  2625. * For every peer MAp message search and set if bss_peer
  2626. */
  2627. if (memcmp(peer->mac_addr.raw, vdev->mac_addr.raw, 6) == 0) {
  2628. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2629. "vdev bss_peer!!!!");
  2630. peer->bss_peer = 1;
  2631. vdev->vap_bss_peer = peer;
  2632. }
  2633. #ifndef CONFIG_WIN
  2634. dp_local_peer_id_alloc(pdev, peer);
  2635. #endif
  2636. DP_STATS_INIT(peer);
  2637. return (void *)peer;
  2638. }
  2639. /*
  2640. * dp_peer_setup_wifi3() - initialize the peer
  2641. * @vdev_hdl: virtual device object
  2642. * @peer: Peer object
  2643. *
  2644. * Return: void
  2645. */
  2646. static void dp_peer_setup_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  2647. {
  2648. struct dp_peer *peer = (struct dp_peer *)peer_hdl;
  2649. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  2650. struct dp_pdev *pdev;
  2651. struct dp_soc *soc;
  2652. bool hash_based = 0;
  2653. enum cdp_host_reo_dest_ring reo_dest;
  2654. /* preconditions */
  2655. qdf_assert(vdev);
  2656. qdf_assert(peer);
  2657. pdev = vdev->pdev;
  2658. soc = pdev->soc;
  2659. dp_peer_rx_init(pdev, peer);
  2660. peer->last_assoc_rcvd = 0;
  2661. peer->last_disassoc_rcvd = 0;
  2662. peer->last_deauth_rcvd = 0;
  2663. /*
  2664. * hash based steering is disabled for Radios which are offloaded
  2665. * to NSS
  2666. */
  2667. if (!wlan_cfg_get_dp_pdev_nss_enabled(pdev->wlan_cfg_ctx))
  2668. hash_based = wlan_cfg_is_rx_hash_enabled(soc->wlan_cfg_ctx);
  2669. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  2670. FL("hash based steering for pdev: %d is %d\n"),
  2671. pdev->pdev_id, hash_based);
  2672. if (!hash_based)
  2673. reo_dest = pdev->reo_dest;
  2674. else
  2675. reo_dest = 1;
  2676. if (soc->cdp_soc.ol_ops->peer_set_default_routing) {
  2677. /* TODO: Check the destination ring number to be passed to FW */
  2678. soc->cdp_soc.ol_ops->peer_set_default_routing(
  2679. pdev->osif_pdev, peer->mac_addr.raw,
  2680. peer->vdev->vdev_id, hash_based, reo_dest);
  2681. }
  2682. return;
  2683. }
  2684. /*
  2685. * dp_set_vdev_tx_encap_type() - set the encap type of the vdev
  2686. * @vdev_handle: virtual device object
  2687. * @htt_pkt_type: type of pkt
  2688. *
  2689. * Return: void
  2690. */
  2691. static void dp_set_vdev_tx_encap_type(struct cdp_vdev *vdev_handle,
  2692. enum htt_cmn_pkt_type val)
  2693. {
  2694. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2695. vdev->tx_encap_type = val;
  2696. }
  2697. /*
  2698. * dp_set_vdev_rx_decap_type() - set the decap type of the vdev
  2699. * @vdev_handle: virtual device object
  2700. * @htt_pkt_type: type of pkt
  2701. *
  2702. * Return: void
  2703. */
  2704. static void dp_set_vdev_rx_decap_type(struct cdp_vdev *vdev_handle,
  2705. enum htt_cmn_pkt_type val)
  2706. {
  2707. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  2708. vdev->rx_decap_type = val;
  2709. }
  2710. /*
  2711. * dp_set_pdev_reo_dest() - set the reo destination ring for this pdev
  2712. * @pdev_handle: physical device object
  2713. * @val: reo destination ring index (1 - 4)
  2714. *
  2715. * Return: void
  2716. */
  2717. static void dp_set_pdev_reo_dest(struct cdp_pdev *pdev_handle,
  2718. enum cdp_host_reo_dest_ring val)
  2719. {
  2720. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2721. if (pdev)
  2722. pdev->reo_dest = val;
  2723. }
  2724. /*
  2725. * dp_get_pdev_reo_dest() - get the reo destination for this pdev
  2726. * @pdev_handle: physical device object
  2727. *
  2728. * Return: reo destination ring index
  2729. */
  2730. static enum cdp_host_reo_dest_ring
  2731. dp_get_pdev_reo_dest(struct cdp_pdev *pdev_handle)
  2732. {
  2733. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2734. if (pdev)
  2735. return pdev->reo_dest;
  2736. else
  2737. return cdp_host_reo_dest_ring_unknown;
  2738. }
  2739. #ifdef QCA_SUPPORT_SON
  2740. static void dp_son_peer_authorize(struct dp_peer *peer)
  2741. {
  2742. struct dp_soc *soc;
  2743. soc = peer->vdev->pdev->soc;
  2744. peer->peer_bs_inact_flag = 0;
  2745. peer->peer_bs_inact = soc->pdev_bs_inact_reload;
  2746. return;
  2747. }
  2748. #else
  2749. static void dp_son_peer_authorize(struct dp_peer *peer)
  2750. {
  2751. return;
  2752. }
  2753. #endif
  2754. /*
  2755. * dp_set_filter_neighbour_peers() - set filter neighbour peers for smart mesh
  2756. * @pdev_handle: device object
  2757. * @val: value to be set
  2758. *
  2759. * Return: void
  2760. */
  2761. static int dp_set_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2762. uint32_t val)
  2763. {
  2764. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2765. /* Enable/Disable smart mesh filtering. This flag will be checked
  2766. * during rx processing to check if packets are from NAC clients.
  2767. */
  2768. pdev->filter_neighbour_peers = val;
  2769. return 0;
  2770. }
  2771. /*
  2772. * dp_update_filter_neighbour_peers() - set neighbour peers(nac clients)
  2773. * address for smart mesh filtering
  2774. * @pdev_handle: device object
  2775. * @cmd: Add/Del command
  2776. * @macaddr: nac client mac address
  2777. *
  2778. * Return: void
  2779. */
  2780. static int dp_update_filter_neighbour_peers(struct cdp_pdev *pdev_handle,
  2781. uint32_t cmd, uint8_t *macaddr)
  2782. {
  2783. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  2784. struct dp_neighbour_peer *peer = NULL;
  2785. if (!macaddr)
  2786. goto fail0;
  2787. /* Store address of NAC (neighbour peer) which will be checked
  2788. * against TA of received packets.
  2789. */
  2790. if (cmd == DP_NAC_PARAM_ADD) {
  2791. peer = (struct dp_neighbour_peer *) qdf_mem_malloc(
  2792. sizeof(*peer));
  2793. if (!peer) {
  2794. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  2795. FL("DP neighbour peer node memory allocation failed"));
  2796. goto fail0;
  2797. }
  2798. qdf_mem_copy(&peer->neighbour_peers_macaddr.raw[0],
  2799. macaddr, DP_MAC_ADDR_LEN);
  2800. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2801. /* add this neighbour peer into the list */
  2802. TAILQ_INSERT_TAIL(&pdev->neighbour_peers_list, peer,
  2803. neighbour_peer_list_elem);
  2804. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2805. return 1;
  2806. } else if (cmd == DP_NAC_PARAM_DEL) {
  2807. qdf_spin_lock_bh(&pdev->neighbour_peer_mutex);
  2808. TAILQ_FOREACH(peer, &pdev->neighbour_peers_list,
  2809. neighbour_peer_list_elem) {
  2810. if (!qdf_mem_cmp(&peer->neighbour_peers_macaddr.raw[0],
  2811. macaddr, DP_MAC_ADDR_LEN)) {
  2812. /* delete this peer from the list */
  2813. TAILQ_REMOVE(&pdev->neighbour_peers_list,
  2814. peer, neighbour_peer_list_elem);
  2815. qdf_mem_free(peer);
  2816. break;
  2817. }
  2818. }
  2819. qdf_spin_unlock_bh(&pdev->neighbour_peer_mutex);
  2820. return 1;
  2821. }
  2822. fail0:
  2823. return 0;
  2824. }
  2825. /*
  2826. * dp_get_sec_type() - Get the security type
  2827. * @peer: Datapath peer handle
  2828. * @sec_idx: Security id (mcast, ucast)
  2829. *
  2830. * return sec_type: Security type
  2831. */
  2832. static int dp_get_sec_type(struct cdp_peer *peer, uint8_t sec_idx)
  2833. {
  2834. struct dp_peer *dpeer = (struct dp_peer *)peer;
  2835. return dpeer->security[sec_idx].sec_type;
  2836. }
  2837. /*
  2838. * dp_peer_authorize() - authorize txrx peer
  2839. * @peer_handle: Datapath peer handle
  2840. * @authorize
  2841. *
  2842. */
  2843. static void dp_peer_authorize(struct cdp_peer *peer_handle, uint32_t authorize)
  2844. {
  2845. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2846. struct dp_soc *soc;
  2847. if (peer != NULL) {
  2848. soc = peer->vdev->pdev->soc;
  2849. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2850. dp_son_peer_authorize(peer);
  2851. peer->authorize = authorize ? 1 : 0;
  2852. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2853. }
  2854. }
  2855. /*
  2856. * dp_peer_unref_delete() - unref and delete peer
  2857. * @peer_handle: Datapath peer handle
  2858. *
  2859. */
  2860. void dp_peer_unref_delete(void *peer_handle)
  2861. {
  2862. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2863. struct dp_vdev *vdev = peer->vdev;
  2864. struct dp_pdev *pdev = vdev->pdev;
  2865. struct dp_soc *soc = pdev->soc;
  2866. struct dp_peer *tmppeer;
  2867. int found = 0;
  2868. uint16_t peer_id;
  2869. /*
  2870. * Hold the lock all the way from checking if the peer ref count
  2871. * is zero until the peer references are removed from the hash
  2872. * table and vdev list (if the peer ref count is zero).
  2873. * This protects against a new HL tx operation starting to use the
  2874. * peer object just after this function concludes it's done being used.
  2875. * Furthermore, the lock needs to be held while checking whether the
  2876. * vdev's list of peers is empty, to make sure that list is not modified
  2877. * concurrently with the empty check.
  2878. */
  2879. qdf_spin_lock_bh(&soc->peer_ref_mutex);
  2880. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  2881. "%s: peer %p ref_cnt(before decrement): %d\n", __func__,
  2882. peer, qdf_atomic_read(&peer->ref_cnt));
  2883. if (qdf_atomic_dec_and_test(&peer->ref_cnt)) {
  2884. peer_id = peer->peer_ids[0];
  2885. /*
  2886. * Make sure that the reference to the peer in
  2887. * peer object map is removed
  2888. */
  2889. if (peer_id != HTT_INVALID_PEER)
  2890. soc->peer_id_to_obj_map[peer_id] = NULL;
  2891. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2892. "Deleting peer %p (%pM)", peer, peer->mac_addr.raw);
  2893. /* remove the reference to the peer from the hash table */
  2894. dp_peer_find_hash_remove(soc, peer);
  2895. TAILQ_FOREACH(tmppeer, &peer->vdev->peer_list, peer_list_elem) {
  2896. if (tmppeer == peer) {
  2897. found = 1;
  2898. break;
  2899. }
  2900. }
  2901. if (found) {
  2902. TAILQ_REMOVE(&peer->vdev->peer_list, peer,
  2903. peer_list_elem);
  2904. } else {
  2905. /*Ignoring the remove operation as peer not found*/
  2906. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_WARN,
  2907. "peer %p not found in vdev (%p)->peer_list:%p",
  2908. peer, vdev, &peer->vdev->peer_list);
  2909. }
  2910. /* cleanup the peer data */
  2911. dp_peer_cleanup(vdev, peer);
  2912. /* check whether the parent vdev has no peers left */
  2913. if (TAILQ_EMPTY(&vdev->peer_list)) {
  2914. /*
  2915. * Now that there are no references to the peer, we can
  2916. * release the peer reference lock.
  2917. */
  2918. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2919. /*
  2920. * Check if the parent vdev was waiting for its peers
  2921. * to be deleted, in order for it to be deleted too.
  2922. */
  2923. if (vdev->delete.pending) {
  2924. ol_txrx_vdev_delete_cb vdev_delete_cb =
  2925. vdev->delete.callback;
  2926. void *vdev_delete_context =
  2927. vdev->delete.context;
  2928. QDF_TRACE(QDF_MODULE_ID_DP,
  2929. QDF_TRACE_LEVEL_INFO_HIGH,
  2930. FL("deleting vdev object %p (%pM)"
  2931. " - its last peer is done"),
  2932. vdev, vdev->mac_addr.raw);
  2933. /* all peers are gone, go ahead and delete it */
  2934. qdf_mem_free(vdev);
  2935. if (vdev_delete_cb)
  2936. vdev_delete_cb(vdev_delete_context);
  2937. }
  2938. } else {
  2939. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2940. }
  2941. #ifdef notyet
  2942. qdf_mempool_free(soc->osdev, soc->mempool_ol_ath_peer, peer);
  2943. #else
  2944. qdf_mem_free(peer);
  2945. #endif
  2946. if (soc->cdp_soc.ol_ops->peer_unref_delete) {
  2947. soc->cdp_soc.ol_ops->peer_unref_delete(pdev->osif_pdev,
  2948. vdev->vdev_id, peer->mac_addr.raw);
  2949. }
  2950. } else {
  2951. qdf_spin_unlock_bh(&soc->peer_ref_mutex);
  2952. }
  2953. }
  2954. /*
  2955. * dp_peer_detach_wifi3() – Detach txrx peer
  2956. * @peer_handle: Datapath peer handle
  2957. *
  2958. */
  2959. static void dp_peer_delete_wifi3(void *peer_handle)
  2960. {
  2961. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  2962. /* redirect the peer's rx delivery function to point to a
  2963. * discard func
  2964. */
  2965. peer->rx_opt_proc = dp_rx_discard;
  2966. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO_HIGH,
  2967. FL("peer %p (%pM)"), peer, peer->mac_addr.raw);
  2968. #ifndef CONFIG_WIN
  2969. dp_local_peer_id_free(peer->vdev->pdev, peer);
  2970. #endif
  2971. qdf_spinlock_destroy(&peer->peer_info_lock);
  2972. /*
  2973. * Remove the reference added during peer_attach.
  2974. * The peer will still be left allocated until the
  2975. * PEER_UNMAP message arrives to remove the other
  2976. * reference, added by the PEER_MAP message.
  2977. */
  2978. dp_peer_unref_delete(peer_handle);
  2979. }
  2980. /*
  2981. * dp_get_vdev_mac_addr_wifi3() – Detach txrx peer
  2982. * @peer_handle: Datapath peer handle
  2983. *
  2984. */
  2985. static uint8 *dp_get_vdev_mac_addr_wifi3(struct cdp_vdev *pvdev)
  2986. {
  2987. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  2988. return vdev->mac_addr.raw;
  2989. }
  2990. /*
  2991. * dp_vdev_set_wds() - Enable per packet stats
  2992. * @vdev_handle: DP VDEV handle
  2993. * @val: value
  2994. *
  2995. * Return: none
  2996. */
  2997. static int dp_vdev_set_wds(void *vdev_handle, uint32_t val)
  2998. {
  2999. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3000. vdev->wds_enabled = val;
  3001. return 0;
  3002. }
  3003. /*
  3004. * dp_get_vdev_from_vdev_id_wifi3() – Detach txrx peer
  3005. * @peer_handle: Datapath peer handle
  3006. *
  3007. */
  3008. static struct cdp_vdev *dp_get_vdev_from_vdev_id_wifi3(struct cdp_pdev *dev,
  3009. uint8_t vdev_id)
  3010. {
  3011. struct dp_pdev *pdev = (struct dp_pdev *)dev;
  3012. struct dp_vdev *vdev = NULL;
  3013. if (qdf_unlikely(!pdev))
  3014. return NULL;
  3015. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3016. if (vdev->vdev_id == vdev_id)
  3017. break;
  3018. }
  3019. return (struct cdp_vdev *)vdev;
  3020. }
  3021. static int dp_get_opmode(struct cdp_vdev *vdev_handle)
  3022. {
  3023. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3024. return vdev->opmode;
  3025. }
  3026. static struct cdp_cfg *dp_get_ctrl_pdev_from_vdev_wifi3(struct cdp_vdev *pvdev)
  3027. {
  3028. struct dp_vdev *vdev = (struct dp_vdev *)pvdev;
  3029. struct dp_pdev *pdev = vdev->pdev;
  3030. return (struct cdp_cfg *)pdev->wlan_cfg_ctx;
  3031. }
  3032. /**
  3033. * dp_vdev_set_monitor_mode() - Set DP VDEV to monitor mode
  3034. * @vdev_handle: Datapath VDEV handle
  3035. * @smart_monitor: Flag to denote if its smart monitor mode
  3036. *
  3037. * Return: 0 on success, not 0 on failure
  3038. */
  3039. static int dp_vdev_set_monitor_mode(struct cdp_vdev *vdev_handle,
  3040. uint8_t smart_monitor)
  3041. {
  3042. /* Many monitor VAPs can exists in a system but only one can be up at
  3043. * anytime
  3044. */
  3045. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3046. struct dp_pdev *pdev;
  3047. struct htt_rx_ring_tlv_filter htt_tlv_filter;
  3048. struct dp_soc *soc;
  3049. uint8_t pdev_id;
  3050. qdf_assert(vdev);
  3051. pdev = vdev->pdev;
  3052. pdev_id = pdev->pdev_id;
  3053. soc = pdev->soc;
  3054. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_WARN,
  3055. "pdev=%p, pdev_id=%d, soc=%p vdev=%p\n",
  3056. pdev, pdev_id, soc, vdev);
  3057. /*Check if current pdev's monitor_vdev exists */
  3058. if (pdev->monitor_vdev) {
  3059. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3060. "vdev=%p\n", vdev);
  3061. qdf_assert(vdev);
  3062. }
  3063. pdev->monitor_vdev = vdev;
  3064. /* If smart monitor mode, do not configure monitor ring */
  3065. if (smart_monitor)
  3066. return QDF_STATUS_SUCCESS;
  3067. htt_tlv_filter.mpdu_start = 1;
  3068. htt_tlv_filter.msdu_start = 1;
  3069. htt_tlv_filter.packet = 1;
  3070. htt_tlv_filter.msdu_end = 1;
  3071. htt_tlv_filter.mpdu_end = 1;
  3072. htt_tlv_filter.packet_header = 1;
  3073. htt_tlv_filter.attention = 1;
  3074. htt_tlv_filter.ppdu_start = 0;
  3075. htt_tlv_filter.ppdu_end = 0;
  3076. htt_tlv_filter.ppdu_end_user_stats = 0;
  3077. htt_tlv_filter.ppdu_end_user_stats_ext = 0;
  3078. htt_tlv_filter.ppdu_end_status_done = 0;
  3079. htt_tlv_filter.enable_fp = 1;
  3080. htt_tlv_filter.enable_md = 0;
  3081. htt_tlv_filter.enable_mo = 1;
  3082. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3083. pdev->rxdma_mon_buf_ring.hal_srng,
  3084. RXDMA_MONITOR_BUF, RX_BUFFER_SIZE, &htt_tlv_filter);
  3085. htt_tlv_filter.mpdu_start = 1;
  3086. htt_tlv_filter.msdu_start = 1;
  3087. htt_tlv_filter.packet = 0;
  3088. htt_tlv_filter.msdu_end = 1;
  3089. htt_tlv_filter.mpdu_end = 1;
  3090. htt_tlv_filter.packet_header = 1;
  3091. htt_tlv_filter.attention = 1;
  3092. htt_tlv_filter.ppdu_start = 1;
  3093. htt_tlv_filter.ppdu_end = 1;
  3094. htt_tlv_filter.ppdu_end_user_stats = 1;
  3095. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  3096. htt_tlv_filter.ppdu_end_status_done = 1;
  3097. htt_tlv_filter.enable_fp = 1;
  3098. htt_tlv_filter.enable_md = 0;
  3099. htt_tlv_filter.enable_mo = 1;
  3100. htt_h2t_rx_ring_cfg(soc->htt_handle, pdev_id,
  3101. pdev->rxdma_mon_status_ring.hal_srng, RXDMA_MONITOR_STATUS,
  3102. RX_BUFFER_SIZE, &htt_tlv_filter);
  3103. return QDF_STATUS_SUCCESS;
  3104. }
  3105. #ifdef MESH_MODE_SUPPORT
  3106. void dp_peer_set_mesh_mode(struct cdp_vdev *vdev_hdl, uint32_t val)
  3107. {
  3108. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3109. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3110. FL("val %d"), val);
  3111. vdev->mesh_vdev = val;
  3112. }
  3113. /*
  3114. * dp_peer_set_mesh_rx_filter() - to set the mesh rx filter
  3115. * @vdev_hdl: virtual device object
  3116. * @val: value to be set
  3117. *
  3118. * Return: void
  3119. */
  3120. void dp_peer_set_mesh_rx_filter(struct cdp_vdev *vdev_hdl, uint32_t val)
  3121. {
  3122. struct dp_vdev *vdev = (struct dp_vdev *)vdev_hdl;
  3123. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  3124. FL("val %d"), val);
  3125. vdev->mesh_rx_filter = val;
  3126. }
  3127. #endif
  3128. /**
  3129. * dp_aggregate_vdev_stats(): Consolidate stats at VDEV level
  3130. * @vdev: DP VDEV handle
  3131. *
  3132. * return: void
  3133. */
  3134. void dp_aggregate_vdev_stats(struct dp_vdev *vdev)
  3135. {
  3136. struct dp_peer *peer = NULL;
  3137. struct dp_soc *soc = vdev->pdev->soc;
  3138. int i;
  3139. qdf_mem_set(&(vdev->stats.tx), sizeof(vdev->stats.tx), 0x0);
  3140. qdf_mem_set(&(vdev->stats.rx), sizeof(vdev->stats.rx), 0x0);
  3141. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3142. if (!peer)
  3143. return;
  3144. for (i = 0; i < MAX_MCS; i++) {
  3145. DP_STATS_AGGR(vdev, peer, tx.pkt_type[0].mcs_count[i]);
  3146. DP_STATS_AGGR(vdev, peer, tx.pkt_type[1].mcs_count[i]);
  3147. DP_STATS_AGGR(vdev, peer, tx.pkt_type[2].mcs_count[i]);
  3148. DP_STATS_AGGR(vdev, peer, tx.pkt_type[3].mcs_count[i]);
  3149. DP_STATS_AGGR(vdev, peer, tx.pkt_type[4].mcs_count[i]);
  3150. DP_STATS_AGGR(vdev, peer, rx.pkt_type[0].mcs_count[i]);
  3151. DP_STATS_AGGR(vdev, peer, rx.pkt_type[1].mcs_count[i]);
  3152. DP_STATS_AGGR(vdev, peer, rx.pkt_type[2].mcs_count[i]);
  3153. DP_STATS_AGGR(vdev, peer, rx.pkt_type[3].mcs_count[i]);
  3154. DP_STATS_AGGR(vdev, peer, rx.pkt_type[4].mcs_count[i]);
  3155. }
  3156. for (i = 0; i < MAX_BW; i++) {
  3157. DP_STATS_AGGR(vdev, peer, tx.bw[i]);
  3158. DP_STATS_AGGR(vdev, peer, rx.bw[i]);
  3159. }
  3160. for (i = 0; i < SS_COUNT; i++)
  3161. DP_STATS_AGGR(vdev, peer, rx.nss[i]);
  3162. for (i = 0; i < WME_AC_MAX; i++) {
  3163. DP_STATS_AGGR(vdev, peer, tx.wme_ac_type[i]);
  3164. DP_STATS_AGGR(vdev, peer, rx.wme_ac_type[i]);
  3165. DP_STATS_AGGR(vdev, peer, tx.excess_retries_ac[i]);
  3166. }
  3167. for (i = 0; i < MAX_GI; i++) {
  3168. DP_STATS_AGGR(vdev, peer, tx.sgi_count[i]);
  3169. DP_STATS_AGGR(vdev, peer, rx.sgi_count[i]);
  3170. }
  3171. DP_STATS_AGGR_PKT(vdev, peer, tx.comp_pkt);
  3172. DP_STATS_AGGR_PKT(vdev, peer, tx.ucast);
  3173. DP_STATS_AGGR_PKT(vdev, peer, tx.mcast);
  3174. DP_STATS_AGGR_PKT(vdev, peer, tx.tx_success);
  3175. DP_STATS_AGGR(vdev, peer, tx.tx_failed);
  3176. DP_STATS_AGGR(vdev, peer, tx.ofdma);
  3177. DP_STATS_AGGR(vdev, peer, tx.stbc);
  3178. DP_STATS_AGGR(vdev, peer, tx.ldpc);
  3179. DP_STATS_AGGR(vdev, peer, tx.retries);
  3180. DP_STATS_AGGR(vdev, peer, tx.non_amsdu_cnt);
  3181. DP_STATS_AGGR(vdev, peer, tx.amsdu_cnt);
  3182. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem);
  3183. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_tx);
  3184. DP_STATS_AGGR(vdev, peer, tx.dropped.fw_rem_notx);
  3185. DP_STATS_AGGR(vdev, peer, tx.dropped.age_out);
  3186. DP_STATS_AGGR(vdev, peer, rx.err.mic_err);
  3187. DP_STATS_AGGR(vdev, peer, rx.err.decrypt_err);
  3188. DP_STATS_AGGR(vdev, peer, rx.non_ampdu_cnt);
  3189. DP_STATS_AGGR(vdev, peer, rx.ampdu_cnt);
  3190. DP_STATS_AGGR(vdev, peer, rx.non_amsdu_cnt);
  3191. DP_STATS_AGGR(vdev, peer, rx.amsdu_cnt);
  3192. DP_STATS_AGGR_PKT(vdev, peer, rx.to_stack);
  3193. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  3194. DP_STATS_AGGR_PKT(vdev, peer, rx.rcvd_reo[i]);
  3195. peer->stats.rx.unicast.num = peer->stats.rx.to_stack.num -
  3196. peer->stats.rx.multicast.num;
  3197. peer->stats.rx.unicast.bytes = peer->stats.rx.to_stack.bytes -
  3198. peer->stats.rx.multicast.bytes;
  3199. DP_STATS_AGGR_PKT(vdev, peer, rx.unicast);
  3200. DP_STATS_AGGR_PKT(vdev, peer, rx.multicast);
  3201. DP_STATS_AGGR_PKT(vdev, peer, rx.wds);
  3202. DP_STATS_AGGR_PKT(vdev, peer, rx.raw);
  3203. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.pkts);
  3204. DP_STATS_AGGR_PKT(vdev, peer, rx.intra_bss.fail);
  3205. vdev->stats.tx.last_ack_rssi =
  3206. peer->stats.tx.last_ack_rssi;
  3207. }
  3208. soc->cdp_soc.ol_ops->update_dp_stats(vdev->pdev->osif_pdev,
  3209. &vdev->stats, vdev->vdev_id, UPDATE_VDEV_STATS);
  3210. }
  3211. /**
  3212. * dp_aggregate_pdev_stats(): Consolidate stats at PDEV level
  3213. * @pdev: DP PDEV handle
  3214. *
  3215. * return: void
  3216. */
  3217. static inline void dp_aggregate_pdev_stats(struct dp_pdev *pdev)
  3218. {
  3219. struct dp_vdev *vdev = NULL;
  3220. uint8_t i;
  3221. qdf_mem_set(&(pdev->stats.tx), sizeof(pdev->stats.tx), 0x0);
  3222. qdf_mem_set(&(pdev->stats.rx), sizeof(pdev->stats.rx), 0x0);
  3223. qdf_mem_set(&(pdev->stats.tx_i), sizeof(pdev->stats.tx_i), 0x0);
  3224. TAILQ_FOREACH(vdev, &pdev->vdev_list, vdev_list_elem) {
  3225. if (!vdev)
  3226. return;
  3227. dp_aggregate_vdev_stats(vdev);
  3228. for (i = 0; i < MAX_MCS; i++) {
  3229. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[0].mcs_count[i]);
  3230. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[1].mcs_count[i]);
  3231. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[2].mcs_count[i]);
  3232. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[3].mcs_count[i]);
  3233. DP_STATS_AGGR(pdev, vdev, tx.pkt_type[4].mcs_count[i]);
  3234. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[0].mcs_count[i]);
  3235. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[1].mcs_count[i]);
  3236. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[2].mcs_count[i]);
  3237. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[3].mcs_count[i]);
  3238. DP_STATS_AGGR(pdev, vdev, rx.pkt_type[4].mcs_count[i]);
  3239. }
  3240. for (i = 0; i < MAX_BW; i++) {
  3241. DP_STATS_AGGR(pdev, vdev, tx.bw[i]);
  3242. DP_STATS_AGGR(pdev, vdev, rx.bw[i]);
  3243. }
  3244. for (i = 0; i < SS_COUNT; i++)
  3245. DP_STATS_AGGR(pdev, vdev, rx.nss[i]);
  3246. for (i = 0; i < WME_AC_MAX; i++) {
  3247. DP_STATS_AGGR(pdev, vdev, tx.wme_ac_type[i]);
  3248. DP_STATS_AGGR(pdev, vdev, rx.wme_ac_type[i]);
  3249. DP_STATS_AGGR(pdev, vdev,
  3250. tx.excess_retries_ac[i]);
  3251. }
  3252. for (i = 0; i < MAX_GI; i++) {
  3253. DP_STATS_AGGR(pdev, vdev, tx.sgi_count[i]);
  3254. DP_STATS_AGGR(pdev, vdev, rx.sgi_count[i]);
  3255. }
  3256. DP_STATS_AGGR_PKT(pdev, vdev, tx.comp_pkt);
  3257. DP_STATS_AGGR_PKT(pdev, vdev, tx.ucast);
  3258. DP_STATS_AGGR_PKT(pdev, vdev, tx.mcast);
  3259. DP_STATS_AGGR_PKT(pdev, vdev, tx.tx_success);
  3260. DP_STATS_AGGR(pdev, vdev, tx.tx_failed);
  3261. DP_STATS_AGGR(pdev, vdev, tx.ofdma);
  3262. DP_STATS_AGGR(pdev, vdev, tx.stbc);
  3263. DP_STATS_AGGR(pdev, vdev, tx.ldpc);
  3264. DP_STATS_AGGR(pdev, vdev, tx.retries);
  3265. DP_STATS_AGGR(pdev, vdev, tx.non_amsdu_cnt);
  3266. DP_STATS_AGGR(pdev, vdev, tx.amsdu_cnt);
  3267. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem);
  3268. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_tx);
  3269. DP_STATS_AGGR(pdev, vdev, tx.dropped.fw_rem_notx);
  3270. DP_STATS_AGGR(pdev, vdev, tx.dropped.age_out);
  3271. DP_STATS_AGGR(pdev, vdev, rx.err.mic_err);
  3272. DP_STATS_AGGR(pdev, vdev, rx.err.decrypt_err);
  3273. DP_STATS_AGGR(pdev, vdev, rx.non_ampdu_cnt);
  3274. DP_STATS_AGGR(pdev, vdev, rx.ampdu_cnt);
  3275. DP_STATS_AGGR(pdev, vdev, rx.non_amsdu_cnt);
  3276. DP_STATS_AGGR(pdev, vdev, rx.amsdu_cnt);
  3277. DP_STATS_AGGR_PKT(pdev, vdev, rx.to_stack);
  3278. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[0]);
  3279. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[1]);
  3280. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[2]);
  3281. DP_STATS_AGGR_PKT(pdev, vdev, rx.rcvd_reo[3]);
  3282. DP_STATS_AGGR_PKT(pdev, vdev, rx.unicast);
  3283. DP_STATS_AGGR_PKT(pdev, vdev, rx.multicast);
  3284. DP_STATS_AGGR_PKT(pdev, vdev, rx.wds);
  3285. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.pkts);
  3286. DP_STATS_AGGR_PKT(pdev, vdev, rx.intra_bss.fail);
  3287. DP_STATS_AGGR_PKT(pdev, vdev, rx.raw);
  3288. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.rcvd);
  3289. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.processed);
  3290. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.reinject_pkts);
  3291. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.inspect_pkts);
  3292. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.raw.raw_pkt);
  3293. DP_STATS_AGGR(pdev, vdev, tx_i.raw.dma_map_error);
  3294. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.tso.tso_pkt);
  3295. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_host);
  3296. DP_STATS_AGGR(pdev, vdev, tx_i.tso.dropped_target);
  3297. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_host);
  3298. DP_STATS_AGGR(pdev, vdev, tx_i.sg.dropped_target);
  3299. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.sg.sg_pkt);
  3300. DP_STATS_AGGR_PKT(pdev, vdev, tx_i.mcast_en.mcast_pkt);
  3301. DP_STATS_AGGR(pdev, vdev,
  3302. tx_i.mcast_en.dropped_map_error);
  3303. DP_STATS_AGGR(pdev, vdev,
  3304. tx_i.mcast_en.dropped_self_mac);
  3305. DP_STATS_AGGR(pdev, vdev,
  3306. tx_i.mcast_en.dropped_send_fail);
  3307. DP_STATS_AGGR(pdev, vdev, tx_i.mcast_en.ucast);
  3308. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.dma_error);
  3309. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.ring_full);
  3310. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.enqueue_fail);
  3311. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.desc_na);
  3312. DP_STATS_AGGR(pdev, vdev, tx_i.dropped.res_full);
  3313. pdev->stats.tx_i.dropped.dropped_pkt.num =
  3314. pdev->stats.tx_i.dropped.dma_error +
  3315. pdev->stats.tx_i.dropped.ring_full +
  3316. pdev->stats.tx_i.dropped.enqueue_fail +
  3317. pdev->stats.tx_i.dropped.desc_na +
  3318. pdev->stats.tx_i.dropped.res_full;
  3319. pdev->stats.tx.last_ack_rssi =
  3320. vdev->stats.tx.last_ack_rssi;
  3321. pdev->stats.tx_i.tso.num_seg =
  3322. vdev->stats.tx_i.tso.num_seg;
  3323. }
  3324. }
  3325. /**
  3326. * dp_print_pdev_tx_stats(): Print Pdev level TX stats
  3327. * @pdev: DP_PDEV Handle
  3328. *
  3329. * Return:void
  3330. */
  3331. static inline void
  3332. dp_print_pdev_tx_stats(struct dp_pdev *pdev)
  3333. {
  3334. DP_PRINT_STATS("PDEV Tx Stats:\n");
  3335. DP_PRINT_STATS("Received From Stack:");
  3336. DP_PRINT_STATS(" Packets = %d",
  3337. pdev->stats.tx_i.rcvd.num);
  3338. DP_PRINT_STATS(" Bytes = %d",
  3339. pdev->stats.tx_i.rcvd.bytes);
  3340. DP_PRINT_STATS("Processed:");
  3341. DP_PRINT_STATS(" Packets = %d",
  3342. pdev->stats.tx_i.processed.num);
  3343. DP_PRINT_STATS(" Bytes = %d",
  3344. pdev->stats.tx_i.processed.bytes);
  3345. DP_PRINT_STATS("Completions:");
  3346. DP_PRINT_STATS(" Packets = %d",
  3347. pdev->stats.tx.comp_pkt.num);
  3348. DP_PRINT_STATS(" Bytes = %d",
  3349. pdev->stats.tx.comp_pkt.bytes);
  3350. DP_PRINT_STATS("Dropped:");
  3351. DP_PRINT_STATS(" Total = %d",
  3352. pdev->stats.tx_i.dropped.dropped_pkt.num);
  3353. DP_PRINT_STATS(" Dma_map_error = %d",
  3354. pdev->stats.tx_i.dropped.dma_error);
  3355. DP_PRINT_STATS(" Ring Full = %d",
  3356. pdev->stats.tx_i.dropped.ring_full);
  3357. DP_PRINT_STATS(" Descriptor Not available = %d",
  3358. pdev->stats.tx_i.dropped.desc_na);
  3359. DP_PRINT_STATS(" HW enqueue failed= %d",
  3360. pdev->stats.tx_i.dropped.enqueue_fail);
  3361. DP_PRINT_STATS(" Resources Full = %d",
  3362. pdev->stats.tx_i.dropped.res_full);
  3363. DP_PRINT_STATS(" FW removed = %d",
  3364. pdev->stats.tx.dropped.fw_rem);
  3365. DP_PRINT_STATS(" FW removed transmitted = %d",
  3366. pdev->stats.tx.dropped.fw_rem_tx);
  3367. DP_PRINT_STATS(" FW removed untransmitted = %d",
  3368. pdev->stats.tx.dropped.fw_rem_notx);
  3369. DP_PRINT_STATS(" Aged Out from msdu/mpdu queues = %d",
  3370. pdev->stats.tx.dropped.age_out);
  3371. DP_PRINT_STATS("Scatter Gather:");
  3372. DP_PRINT_STATS(" Packets = %d",
  3373. pdev->stats.tx_i.sg.sg_pkt.num);
  3374. DP_PRINT_STATS(" Bytes = %d",
  3375. pdev->stats.tx_i.sg.sg_pkt.bytes);
  3376. DP_PRINT_STATS(" Dropped By Host = %d",
  3377. pdev->stats.tx_i.sg.dropped_host);
  3378. DP_PRINT_STATS(" Dropped By Target = %d",
  3379. pdev->stats.tx_i.sg.dropped_target);
  3380. DP_PRINT_STATS("TSO:");
  3381. DP_PRINT_STATS(" Number of Segments = %d",
  3382. pdev->stats.tx_i.tso.num_seg);
  3383. DP_PRINT_STATS(" Packets = %d",
  3384. pdev->stats.tx_i.tso.tso_pkt.num);
  3385. DP_PRINT_STATS(" Bytes = %d",
  3386. pdev->stats.tx_i.tso.tso_pkt.bytes);
  3387. DP_PRINT_STATS(" Dropped By Host = %d",
  3388. pdev->stats.tx_i.tso.dropped_host);
  3389. DP_PRINT_STATS("Mcast Enhancement:");
  3390. DP_PRINT_STATS(" Packets = %d",
  3391. pdev->stats.tx_i.mcast_en.mcast_pkt.num);
  3392. DP_PRINT_STATS(" Bytes = %d",
  3393. pdev->stats.tx_i.mcast_en.mcast_pkt.bytes);
  3394. DP_PRINT_STATS(" Dropped: Map Errors = %d",
  3395. pdev->stats.tx_i.mcast_en.dropped_map_error);
  3396. DP_PRINT_STATS(" Dropped: Self Mac = %d",
  3397. pdev->stats.tx_i.mcast_en.dropped_self_mac);
  3398. DP_PRINT_STATS(" Dropped: Send Fail = %d",
  3399. pdev->stats.tx_i.mcast_en.dropped_send_fail);
  3400. DP_PRINT_STATS(" Unicast sent = %d",
  3401. pdev->stats.tx_i.mcast_en.ucast);
  3402. DP_PRINT_STATS("Raw:");
  3403. DP_PRINT_STATS(" Packets = %d",
  3404. pdev->stats.tx_i.raw.raw_pkt.num);
  3405. DP_PRINT_STATS(" Bytes = %d",
  3406. pdev->stats.tx_i.raw.raw_pkt.bytes);
  3407. DP_PRINT_STATS(" DMA map error = %d",
  3408. pdev->stats.tx_i.raw.dma_map_error);
  3409. DP_PRINT_STATS("Reinjected:");
  3410. DP_PRINT_STATS(" Packets = %d",
  3411. pdev->stats.tx_i.reinject_pkts.num);
  3412. DP_PRINT_STATS("Bytes = %d\n",
  3413. pdev->stats.tx_i.reinject_pkts.bytes);
  3414. DP_PRINT_STATS("Inspected:");
  3415. DP_PRINT_STATS(" Packets = %d",
  3416. pdev->stats.tx_i.inspect_pkts.num);
  3417. DP_PRINT_STATS(" Bytes = %d",
  3418. pdev->stats.tx_i.inspect_pkts.bytes);
  3419. }
  3420. /**
  3421. * dp_print_pdev_rx_stats(): Print Pdev level RX stats
  3422. * @pdev: DP_PDEV Handle
  3423. *
  3424. * Return: void
  3425. */
  3426. static inline void
  3427. dp_print_pdev_rx_stats(struct dp_pdev *pdev)
  3428. {
  3429. DP_PRINT_STATS("PDEV Rx Stats:\n");
  3430. DP_PRINT_STATS("Received From HW (Per Rx Ring):");
  3431. DP_PRINT_STATS(" Packets = %d %d %d %d",
  3432. pdev->stats.rx.rcvd_reo[0].num,
  3433. pdev->stats.rx.rcvd_reo[1].num,
  3434. pdev->stats.rx.rcvd_reo[2].num,
  3435. pdev->stats.rx.rcvd_reo[3].num);
  3436. DP_PRINT_STATS(" Bytes = %d %d %d %d",
  3437. pdev->stats.rx.rcvd_reo[0].bytes,
  3438. pdev->stats.rx.rcvd_reo[1].bytes,
  3439. pdev->stats.rx.rcvd_reo[2].bytes,
  3440. pdev->stats.rx.rcvd_reo[3].bytes);
  3441. DP_PRINT_STATS("Replenished:");
  3442. DP_PRINT_STATS(" Packets = %d",
  3443. pdev->stats.replenish.pkts.num);
  3444. DP_PRINT_STATS(" Bytes = %d",
  3445. pdev->stats.replenish.pkts.bytes);
  3446. DP_PRINT_STATS(" Buffers Added To Freelist = %d",
  3447. pdev->stats.buf_freelist);
  3448. DP_PRINT_STATS("Dropped:");
  3449. DP_PRINT_STATS(" msdu_not_done = %d",
  3450. pdev->stats.dropped.msdu_not_done);
  3451. DP_PRINT_STATS("Sent To Stack:");
  3452. DP_PRINT_STATS(" Packets = %d",
  3453. pdev->stats.rx.to_stack.num);
  3454. DP_PRINT_STATS(" Bytes = %d",
  3455. pdev->stats.rx.to_stack.bytes);
  3456. DP_PRINT_STATS("Multicast/Broadcast:");
  3457. DP_PRINT_STATS(" Packets = %d",
  3458. pdev->stats.rx.multicast.num);
  3459. DP_PRINT_STATS(" Bytes = %d",
  3460. pdev->stats.rx.multicast.bytes);
  3461. DP_PRINT_STATS("Errors:");
  3462. DP_PRINT_STATS(" Rxdma Ring Un-inititalized = %d",
  3463. pdev->stats.replenish.rxdma_err);
  3464. DP_PRINT_STATS(" Desc Alloc Failed: = %d",
  3465. pdev->stats.err.desc_alloc_fail);
  3466. }
  3467. /**
  3468. * dp_print_soc_tx_stats(): Print SOC level stats
  3469. * @soc DP_SOC Handle
  3470. *
  3471. * Return: void
  3472. */
  3473. static inline void
  3474. dp_print_soc_tx_stats(struct dp_soc *soc)
  3475. {
  3476. DP_PRINT_STATS("SOC Tx Stats:\n");
  3477. DP_PRINT_STATS("Tx Descriptors In Use = %d",
  3478. soc->stats.tx.desc_in_use);
  3479. DP_PRINT_STATS("Invalid peer:");
  3480. DP_PRINT_STATS(" Packets = %d",
  3481. soc->stats.tx.tx_invalid_peer.num);
  3482. DP_PRINT_STATS(" Bytes = %d",
  3483. soc->stats.tx.tx_invalid_peer.bytes);
  3484. DP_PRINT_STATS("Packets dropped due to TCL ring full = %d %d %d",
  3485. soc->stats.tx.tcl_ring_full[0],
  3486. soc->stats.tx.tcl_ring_full[1],
  3487. soc->stats.tx.tcl_ring_full[2]);
  3488. }
  3489. /**
  3490. * dp_print_soc_rx_stats: Print SOC level Rx stats
  3491. * @soc: DP_SOC Handle
  3492. *
  3493. * Return:void
  3494. */
  3495. static inline void
  3496. dp_print_soc_rx_stats(struct dp_soc *soc)
  3497. {
  3498. uint32_t i;
  3499. char reo_error[DP_REO_ERR_LENGTH];
  3500. char rxdma_error[DP_RXDMA_ERR_LENGTH];
  3501. uint8_t index = 0;
  3502. DP_PRINT_STATS("SOC Rx Stats:\n");
  3503. DP_PRINT_STATS("Errors:\n");
  3504. DP_PRINT_STATS("Rx Decrypt Errors = %d",
  3505. (soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_DECRYPT] +
  3506. soc->stats.rx.err.rxdma_error[HAL_RXDMA_ERR_TKIP_MIC]));
  3507. DP_PRINT_STATS("Invalid RBM = %d",
  3508. soc->stats.rx.err.invalid_rbm);
  3509. DP_PRINT_STATS("Invalid Vdev = %d",
  3510. soc->stats.rx.err.invalid_vdev);
  3511. DP_PRINT_STATS("Invalid Pdev = %d",
  3512. soc->stats.rx.err.invalid_pdev);
  3513. DP_PRINT_STATS("Invalid Peer = %d",
  3514. soc->stats.rx.err.rx_invalid_peer.num);
  3515. DP_PRINT_STATS("HAL Ring Access Fail = %d",
  3516. soc->stats.rx.err.hal_ring_access_fail);
  3517. for (i = 0; i < HAL_RXDMA_ERR_MAX; i++) {
  3518. index += qdf_snprint(&rxdma_error[index],
  3519. DP_RXDMA_ERR_LENGTH - index,
  3520. " %d", soc->stats.rx.err.rxdma_error[i]);
  3521. }
  3522. DP_PRINT_STATS("RXDMA Error (0-31):%s",
  3523. rxdma_error);
  3524. index = 0;
  3525. for (i = 0; i < HAL_REO_ERR_MAX; i++) {
  3526. index += qdf_snprint(&reo_error[index],
  3527. DP_REO_ERR_LENGTH - index,
  3528. " %d", soc->stats.rx.err.reo_error[i]);
  3529. }
  3530. DP_PRINT_STATS("REO Error(0-14):%s",
  3531. reo_error);
  3532. }
  3533. /**
  3534. * dp_txrx_host_stats_clr(): Reinitialize the txrx stats
  3535. * @vdev: DP_VDEV handle
  3536. *
  3537. * Return:void
  3538. */
  3539. static inline void
  3540. dp_txrx_host_stats_clr(struct dp_vdev *vdev)
  3541. {
  3542. struct dp_peer *peer = NULL;
  3543. DP_STATS_CLR(vdev->pdev);
  3544. DP_STATS_CLR(vdev->pdev->soc);
  3545. DP_STATS_CLR(vdev);
  3546. TAILQ_FOREACH(peer, &vdev->peer_list, peer_list_elem) {
  3547. if (!peer)
  3548. return;
  3549. DP_STATS_CLR(peer);
  3550. }
  3551. }
  3552. /**
  3553. * dp_print_rx_rates(): Print Rx rate stats
  3554. * @vdev: DP_VDEV handle
  3555. *
  3556. * Return:void
  3557. */
  3558. static inline void
  3559. dp_print_rx_rates(struct dp_vdev *vdev)
  3560. {
  3561. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3562. uint8_t i, mcs, pkt_type;
  3563. uint8_t index = 0;
  3564. char nss[DP_NSS_LENGTH];
  3565. DP_PRINT_STATS("Rx Rate Info:\n");
  3566. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3567. index = 0;
  3568. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3569. if (!dp_rate_string[pkt_type][mcs].valid)
  3570. continue;
  3571. DP_PRINT_STATS(" %s = %d",
  3572. dp_rate_string[pkt_type][mcs].mcs_type,
  3573. pdev->stats.rx.pkt_type[pkt_type].
  3574. mcs_count[mcs]);
  3575. }
  3576. DP_PRINT_STATS("\n");
  3577. }
  3578. index = 0;
  3579. for (i = 0; i < SS_COUNT; i++) {
  3580. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3581. " %d", pdev->stats.rx.nss[i]);
  3582. }
  3583. DP_PRINT_STATS("NSS(0-7) = %s",
  3584. nss);
  3585. DP_PRINT_STATS("SGI ="
  3586. " 0.8us %d,"
  3587. " 0.4us %d,"
  3588. " 1.6us %d,"
  3589. " 3.2us %d,",
  3590. pdev->stats.rx.sgi_count[0],
  3591. pdev->stats.rx.sgi_count[1],
  3592. pdev->stats.rx.sgi_count[2],
  3593. pdev->stats.rx.sgi_count[3]);
  3594. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3595. pdev->stats.rx.bw[0], pdev->stats.rx.bw[1],
  3596. pdev->stats.rx.bw[2], pdev->stats.rx.bw[3]);
  3597. DP_PRINT_STATS("Reception Type ="
  3598. " SU: %d,"
  3599. " MU_MIMO:%d,"
  3600. " MU_OFDMA:%d,"
  3601. " MU_OFDMA_MIMO:%d\n",
  3602. pdev->stats.rx.reception_type[0],
  3603. pdev->stats.rx.reception_type[1],
  3604. pdev->stats.rx.reception_type[2],
  3605. pdev->stats.rx.reception_type[3]);
  3606. DP_PRINT_STATS("Aggregation:\n");
  3607. DP_PRINT_STATS("Number of Msdu's Part of Ampdus = %d",
  3608. pdev->stats.rx.ampdu_cnt);
  3609. DP_PRINT_STATS("Number of Msdu's With No Mpdu Level Aggregation : %d",
  3610. pdev->stats.rx.non_ampdu_cnt);
  3611. DP_PRINT_STATS("Number of Msdu's Part of Amsdu: %d",
  3612. pdev->stats.rx.amsdu_cnt);
  3613. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation: %d",
  3614. pdev->stats.rx.non_amsdu_cnt);
  3615. }
  3616. /**
  3617. * dp_print_tx_rates(): Print tx rates
  3618. * @vdev: DP_VDEV handle
  3619. *
  3620. * Return:void
  3621. */
  3622. static inline void
  3623. dp_print_tx_rates(struct dp_vdev *vdev)
  3624. {
  3625. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3626. uint8_t mcs, pkt_type;
  3627. uint32_t index;
  3628. DP_PRINT_STATS("Tx Rate Info:\n");
  3629. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3630. index = 0;
  3631. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3632. if (!dp_rate_string[pkt_type][mcs].valid)
  3633. continue;
  3634. DP_PRINT_STATS(" %s = %d",
  3635. dp_rate_string[pkt_type][mcs].mcs_type,
  3636. pdev->stats.tx.pkt_type[pkt_type].
  3637. mcs_count[mcs]);
  3638. }
  3639. DP_PRINT_STATS("\n");
  3640. }
  3641. DP_PRINT_STATS("SGI ="
  3642. " 0.8us %d"
  3643. " 0.4us %d"
  3644. " 1.6us %d"
  3645. " 3.2us %d",
  3646. pdev->stats.tx.sgi_count[0],
  3647. pdev->stats.tx.sgi_count[1],
  3648. pdev->stats.tx.sgi_count[2],
  3649. pdev->stats.tx.sgi_count[3]);
  3650. DP_PRINT_STATS("BW Counts = 20MHZ %d, 40MHZ %d, 80MHZ %d, 160MHZ %d",
  3651. pdev->stats.tx.bw[0], pdev->stats.tx.bw[1],
  3652. pdev->stats.tx.bw[2], pdev->stats.tx.bw[3]);
  3653. DP_PRINT_STATS("OFDMA = %d", pdev->stats.tx.ofdma);
  3654. DP_PRINT_STATS("STBC = %d", pdev->stats.tx.stbc);
  3655. DP_PRINT_STATS("LDPC = %d", pdev->stats.tx.ldpc);
  3656. DP_PRINT_STATS("Retries = %d", pdev->stats.tx.retries);
  3657. DP_PRINT_STATS("Last ack rssi = %d\n", pdev->stats.tx.last_ack_rssi);
  3658. DP_PRINT_STATS("Aggregation:\n");
  3659. DP_PRINT_STATS("Number of Msdu's Part of Amsdu = %d",
  3660. pdev->stats.tx.amsdu_cnt);
  3661. DP_PRINT_STATS("Number of Msdu's With No Msdu Level Aggregation = %d",
  3662. pdev->stats.tx.non_amsdu_cnt);
  3663. }
  3664. /**
  3665. * dp_print_peer_stats():print peer stats
  3666. * @peer: DP_PEER handle
  3667. *
  3668. * return void
  3669. */
  3670. static inline void dp_print_peer_stats(struct dp_peer *peer)
  3671. {
  3672. uint8_t i, mcs, pkt_type;
  3673. uint32_t index;
  3674. char nss[DP_NSS_LENGTH];
  3675. DP_PRINT_STATS("Node Tx Stats:\n");
  3676. DP_PRINT_STATS("Total Packet Completions = %d",
  3677. peer->stats.tx.comp_pkt.num);
  3678. DP_PRINT_STATS("Total Bytes Completions = %d",
  3679. peer->stats.tx.comp_pkt.bytes);
  3680. DP_PRINT_STATS("Success Packets = %d",
  3681. peer->stats.tx.tx_success.num);
  3682. DP_PRINT_STATS("Success Bytes = %d",
  3683. peer->stats.tx.tx_success.bytes);
  3684. DP_PRINT_STATS("Packets Failed = %d",
  3685. peer->stats.tx.tx_failed);
  3686. DP_PRINT_STATS("Packets In OFDMA = %d",
  3687. peer->stats.tx.ofdma);
  3688. DP_PRINT_STATS("Packets In STBC = %d",
  3689. peer->stats.tx.stbc);
  3690. DP_PRINT_STATS("Packets In LDPC = %d",
  3691. peer->stats.tx.ldpc);
  3692. DP_PRINT_STATS("Packet Retries = %d",
  3693. peer->stats.tx.retries);
  3694. DP_PRINT_STATS("MSDU's Part of AMSDU = %d",
  3695. peer->stats.tx.amsdu_cnt);
  3696. DP_PRINT_STATS("Last Packet RSSI = %d",
  3697. peer->stats.tx.last_ack_rssi);
  3698. DP_PRINT_STATS("Dropped At FW: Removed = %d",
  3699. peer->stats.tx.dropped.fw_rem);
  3700. DP_PRINT_STATS("Dropped At FW: Removed transmitted = %d",
  3701. peer->stats.tx.dropped.fw_rem_tx);
  3702. DP_PRINT_STATS("Dropped At FW: Removed Untransmitted = %d",
  3703. peer->stats.tx.dropped.fw_rem_notx);
  3704. DP_PRINT_STATS("Dropped : Age Out = %d",
  3705. peer->stats.tx.dropped.age_out);
  3706. DP_PRINT_STATS("Rate Info:");
  3707. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3708. index = 0;
  3709. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3710. if (!dp_rate_string[pkt_type][mcs].valid)
  3711. continue;
  3712. DP_PRINT_STATS(" %s = %d",
  3713. dp_rate_string[pkt_type][mcs].mcs_type,
  3714. peer->stats.tx.pkt_type[pkt_type].
  3715. mcs_count[mcs]);
  3716. }
  3717. DP_PRINT_STATS("\n");
  3718. }
  3719. DP_PRINT_STATS("SGI = "
  3720. " 0.8us %d"
  3721. " 0.4us %d"
  3722. " 1.6us %d"
  3723. " 3.2us %d",
  3724. peer->stats.tx.sgi_count[0],
  3725. peer->stats.tx.sgi_count[1],
  3726. peer->stats.tx.sgi_count[2],
  3727. peer->stats.tx.sgi_count[3]);
  3728. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d\n",
  3729. peer->stats.tx.bw[0], peer->stats.tx.bw[1],
  3730. peer->stats.tx.bw[2], peer->stats.tx.bw[3]);
  3731. DP_PRINT_STATS("Aggregation:");
  3732. DP_PRINT_STATS(" Number of Msdu's Part of Amsdu = %d",
  3733. peer->stats.tx.amsdu_cnt);
  3734. DP_PRINT_STATS(" Number of Msdu's With No Msdu Level Aggregation = %d\n",
  3735. peer->stats.tx.non_amsdu_cnt);
  3736. DP_PRINT_STATS("Node Rx Stats:");
  3737. DP_PRINT_STATS("Packets Sent To Stack = %d",
  3738. peer->stats.rx.to_stack.num);
  3739. DP_PRINT_STATS("Bytes Sent To Stack = %d",
  3740. peer->stats.rx.to_stack.bytes);
  3741. for (i = 0; i < CDP_MAX_RX_RINGS; i++) {
  3742. DP_PRINT_STATS("Packets Received = %d",
  3743. peer->stats.rx.rcvd_reo[i].num);
  3744. DP_PRINT_STATS("Bytes Received = %d",
  3745. peer->stats.rx.rcvd_reo[i].bytes);
  3746. }
  3747. DP_PRINT_STATS("Multicast Packets Received = %d",
  3748. peer->stats.rx.multicast.num);
  3749. DP_PRINT_STATS("Multicast Bytes Received = %d",
  3750. peer->stats.rx.multicast.bytes);
  3751. DP_PRINT_STATS("WDS Packets Received = %d",
  3752. peer->stats.rx.wds.num);
  3753. DP_PRINT_STATS("WDS Bytes Received = %d",
  3754. peer->stats.rx.wds.bytes);
  3755. DP_PRINT_STATS("Intra BSS Packets Received = %d",
  3756. peer->stats.rx.intra_bss.pkts.num);
  3757. DP_PRINT_STATS("Intra BSS Bytes Received = %d",
  3758. peer->stats.rx.intra_bss.pkts.bytes);
  3759. DP_PRINT_STATS("Raw Packets Received = %d",
  3760. peer->stats.rx.raw.num);
  3761. DP_PRINT_STATS("Raw Bytes Received = %d",
  3762. peer->stats.rx.raw.bytes);
  3763. DP_PRINT_STATS("Errors: MIC Errors = %d",
  3764. peer->stats.rx.err.mic_err);
  3765. DP_PRINT_STATS("Erros: Decryption Errors = %d",
  3766. peer->stats.rx.err.decrypt_err);
  3767. DP_PRINT_STATS("Msdu's Received As Part of Ampdu = %d",
  3768. peer->stats.rx.non_ampdu_cnt);
  3769. DP_PRINT_STATS("Msdu's Recived As Ampdu = %d",
  3770. peer->stats.rx.ampdu_cnt);
  3771. DP_PRINT_STATS("Msdu's Received Not Part of Amsdu's = %d",
  3772. peer->stats.rx.non_amsdu_cnt);
  3773. DP_PRINT_STATS("MSDUs Received As Part of Amsdu = %d",
  3774. peer->stats.rx.amsdu_cnt);
  3775. DP_PRINT_STATS("SGI ="
  3776. " 0.8us %d"
  3777. " 0.4us %d"
  3778. " 1.6us %d"
  3779. " 3.2us %d",
  3780. peer->stats.rx.sgi_count[0],
  3781. peer->stats.rx.sgi_count[1],
  3782. peer->stats.rx.sgi_count[2],
  3783. peer->stats.rx.sgi_count[3]);
  3784. DP_PRINT_STATS("BW Counts = 20MHZ %d 40MHZ %d 80MHZ %d 160MHZ %d",
  3785. peer->stats.rx.bw[0], peer->stats.rx.bw[1],
  3786. peer->stats.rx.bw[2], peer->stats.rx.bw[3]);
  3787. DP_PRINT_STATS("Reception Type ="
  3788. " SU %d,"
  3789. " MU_MIMO %d,"
  3790. " MU_OFDMA %d,"
  3791. " MU_OFDMA_MIMO %d",
  3792. peer->stats.rx.reception_type[0],
  3793. peer->stats.rx.reception_type[1],
  3794. peer->stats.rx.reception_type[2],
  3795. peer->stats.rx.reception_type[3]);
  3796. for (pkt_type = 0; pkt_type < DOT11_MAX; pkt_type++) {
  3797. index = 0;
  3798. for (mcs = 0; mcs < MAX_MCS; mcs++) {
  3799. if (!dp_rate_string[pkt_type][mcs].valid)
  3800. continue;
  3801. DP_PRINT_STATS(" %s = %d",
  3802. dp_rate_string[pkt_type][mcs].mcs_type,
  3803. peer->stats.rx.pkt_type[pkt_type].
  3804. mcs_count[mcs]);
  3805. }
  3806. DP_PRINT_STATS("\n");
  3807. }
  3808. index = 0;
  3809. for (i = 0; i < SS_COUNT; i++) {
  3810. index += qdf_snprint(&nss[index], DP_NSS_LENGTH - index,
  3811. " %d", peer->stats.rx.nss[i]);
  3812. }
  3813. DP_PRINT_STATS("NSS(0-7) = %s",
  3814. nss);
  3815. DP_PRINT_STATS("Aggregation:");
  3816. DP_PRINT_STATS(" Msdu's Part of Ampdu = %d",
  3817. peer->stats.rx.ampdu_cnt);
  3818. DP_PRINT_STATS(" Msdu's With No Mpdu Level Aggregation = %d",
  3819. peer->stats.rx.non_ampdu_cnt);
  3820. DP_PRINT_STATS(" Msdu's Part of Amsdu = %d",
  3821. peer->stats.rx.amsdu_cnt);
  3822. DP_PRINT_STATS(" Msdu's With No Msdu Level Aggregation = %d",
  3823. peer->stats.rx.non_amsdu_cnt);
  3824. }
  3825. /**
  3826. * dp_print_host_stats()- Function to print the stats aggregated at host
  3827. * @vdev_handle: DP_VDEV handle
  3828. * @type: host stats type
  3829. *
  3830. * Available Stat types
  3831. * TXRX_CLEAR_STATS : Clear the stats
  3832. * TXRX_RX_RATE_STATS: Print Rx Rate Info
  3833. * TXRX_TX_RATE_STATS: Print Tx Rate Info
  3834. * TXRX_TX_HOST_STATS: Print Tx Stats
  3835. * TXRX_RX_HOST_STATS: Print Rx Stats
  3836. * TXRX_AST_STATS: Print AST Stats
  3837. *
  3838. * Return: 0 on success, print error message in case of failure
  3839. */
  3840. static int
  3841. dp_print_host_stats(struct cdp_vdev *vdev_handle, enum cdp_host_txrx_stats type)
  3842. {
  3843. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3844. struct dp_pdev *pdev = (struct dp_pdev *)vdev->pdev;
  3845. dp_aggregate_pdev_stats(pdev);
  3846. switch (type) {
  3847. case TXRX_CLEAR_STATS:
  3848. dp_txrx_host_stats_clr(vdev);
  3849. break;
  3850. case TXRX_RX_RATE_STATS:
  3851. dp_print_rx_rates(vdev);
  3852. break;
  3853. case TXRX_TX_RATE_STATS:
  3854. dp_print_tx_rates(vdev);
  3855. break;
  3856. case TXRX_TX_HOST_STATS:
  3857. dp_print_pdev_tx_stats(pdev);
  3858. dp_print_soc_tx_stats(pdev->soc);
  3859. break;
  3860. case TXRX_RX_HOST_STATS:
  3861. dp_print_pdev_rx_stats(pdev);
  3862. dp_print_soc_rx_stats(pdev->soc);
  3863. break;
  3864. case TXRX_AST_STATS:
  3865. dp_print_ast_stats(pdev->soc);
  3866. break;
  3867. default:
  3868. DP_TRACE(FATAL, "Wrong Input For TxRx Host Stats");
  3869. break;
  3870. }
  3871. return 0;
  3872. }
  3873. /*
  3874. * dp_get_host_peer_stats()- function to print peer stats
  3875. * @pdev_handle: DP_PDEV handle
  3876. * @mac_addr: mac address of the peer
  3877. *
  3878. * Return: void
  3879. */
  3880. static void
  3881. dp_get_host_peer_stats(struct cdp_pdev *pdev_handle, char *mac_addr)
  3882. {
  3883. struct dp_peer *peer;
  3884. uint8_t local_id;
  3885. peer = (struct dp_peer *)dp_find_peer_by_addr(pdev_handle, mac_addr,
  3886. &local_id);
  3887. if (!peer) {
  3888. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  3889. "%s: Invalid peer\n", __func__);
  3890. return;
  3891. }
  3892. dp_print_peer_stats(peer);
  3893. dp_peer_rxtid_stats(peer);
  3894. return;
  3895. }
  3896. /*
  3897. * dp_enable_enhanced_stats()- API to enable enhanced statistcs
  3898. * @pdev_handle: DP_PDEV handle
  3899. *
  3900. * Return: void
  3901. */
  3902. static void
  3903. dp_enable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3904. {
  3905. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3906. pdev->enhanced_stats_en = 1;
  3907. }
  3908. /*
  3909. * dp_disable_enhanced_stats()- API to disable enhanced statistcs
  3910. * @pdev_handle: DP_PDEV handle
  3911. *
  3912. * Return: void
  3913. */
  3914. static void
  3915. dp_disable_enhanced_stats(struct cdp_pdev *pdev_handle)
  3916. {
  3917. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3918. pdev->enhanced_stats_en = 0;
  3919. }
  3920. /*
  3921. * dp_get_fw_peer_stats()- function to print peer stats
  3922. * @pdev_handle: DP_PDEV handle
  3923. * @mac_addr: mac address of the peer
  3924. * @cap: Type of htt stats requested
  3925. *
  3926. * Currently Supporting only MAC ID based requests Only
  3927. * 1: HTT_PEER_STATS_REQ_MODE_NO_QUERY
  3928. * 2: HTT_PEER_STATS_REQ_MODE_QUERY_TQM
  3929. * 3: HTT_PEER_STATS_REQ_MODE_FLUSH_TQM
  3930. *
  3931. * Return: void
  3932. */
  3933. static void
  3934. dp_get_fw_peer_stats(struct cdp_pdev *pdev_handle, uint8_t *mac_addr,
  3935. uint32_t cap)
  3936. {
  3937. struct dp_pdev *pdev = (struct dp_pdev *)pdev_handle;
  3938. uint32_t config_param0 = 0;
  3939. uint32_t config_param1 = 0;
  3940. uint32_t config_param2 = 0;
  3941. uint32_t config_param3 = 0;
  3942. HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(config_param0, 1);
  3943. config_param0 |= (1 << (cap + 1));
  3944. config_param1 = 0x8f;
  3945. config_param2 |= (mac_addr[0] & 0x000000ff);
  3946. config_param2 |= ((mac_addr[1] << 8) & 0x0000ff00);
  3947. config_param2 |= ((mac_addr[2] << 16) & 0x00ff0000);
  3948. config_param2 |= ((mac_addr[3] << 24) & 0xff000000);
  3949. config_param3 |= (mac_addr[4] & 0x000000ff);
  3950. config_param3 |= ((mac_addr[5] << 8) & 0x0000ff00);
  3951. dp_h2t_ext_stats_msg_send(pdev, HTT_DBG_EXT_STATS_PEER_INFO,
  3952. config_param0, config_param1, config_param2,
  3953. config_param3);
  3954. }
  3955. /*
  3956. * dp_set_vdev_param: function to set parameters in vdev
  3957. * @param: parameter type to be set
  3958. * @val: value of parameter to be set
  3959. *
  3960. * return: void
  3961. */
  3962. static void dp_set_vdev_param(struct cdp_vdev *vdev_handle,
  3963. enum cdp_vdev_param_type param, uint32_t val)
  3964. {
  3965. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  3966. switch (param) {
  3967. case CDP_ENABLE_WDS:
  3968. vdev->wds_enabled = val;
  3969. break;
  3970. case CDP_ENABLE_NAWDS:
  3971. vdev->nawds_enabled = val;
  3972. break;
  3973. case CDP_ENABLE_MCAST_EN:
  3974. vdev->mcast_enhancement_en = val;
  3975. break;
  3976. case CDP_ENABLE_PROXYSTA:
  3977. vdev->proxysta_vdev = val;
  3978. break;
  3979. case CDP_UPDATE_TDLS_FLAGS:
  3980. vdev->tdls_link_connected = val;
  3981. break;
  3982. case CDP_CFG_WDS_AGING_TIMER:
  3983. if (val == 0)
  3984. qdf_timer_stop(&vdev->pdev->soc->wds_aging_timer);
  3985. else if (val != vdev->wds_aging_timer_val)
  3986. qdf_timer_mod(&vdev->pdev->soc->wds_aging_timer, val);
  3987. vdev->wds_aging_timer_val = val;
  3988. break;
  3989. case CDP_ENABLE_AP_BRIDGE:
  3990. if (wlan_op_mode_sta != vdev->opmode)
  3991. vdev->ap_bridge_enabled = val;
  3992. else
  3993. vdev->ap_bridge_enabled = false;
  3994. break;
  3995. default:
  3996. break;
  3997. }
  3998. dp_tx_vdev_update_search_flags(vdev);
  3999. }
  4000. /**
  4001. * dp_peer_set_nawds: set nawds bit in peer
  4002. * @peer_handle: pointer to peer
  4003. * @value: enable/disable nawds
  4004. *
  4005. * return: void
  4006. */
  4007. static void dp_peer_set_nawds(struct cdp_peer *peer_handle, uint8_t value)
  4008. {
  4009. struct dp_peer *peer = (struct dp_peer *)peer_handle;
  4010. peer->nawds_enabled = value;
  4011. }
  4012. /*
  4013. * dp_set_vdev_dscp_tid_map_wifi3(): Update Map ID selected for particular vdev
  4014. * @vdev_handle: DP_VDEV handle
  4015. * @map_id:ID of map that needs to be updated
  4016. *
  4017. * Return: void
  4018. */
  4019. static void dp_set_vdev_dscp_tid_map_wifi3(struct cdp_vdev *vdev_handle,
  4020. uint8_t map_id)
  4021. {
  4022. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4023. vdev->dscp_tid_map_id = map_id;
  4024. return;
  4025. }
  4026. /**
  4027. * dp_set_pdev_dscp_tid_map_wifi3(): update dscp tid map in pdev
  4028. * @pdev: DP_PDEV handle
  4029. * @map_id: ID of map that needs to be updated
  4030. * @tos: index value in map
  4031. * @tid: tid value passed by the user
  4032. *
  4033. * Return: void
  4034. */
  4035. static void dp_set_pdev_dscp_tid_map_wifi3(struct cdp_pdev *pdev_handle,
  4036. uint8_t map_id, uint8_t tos, uint8_t tid)
  4037. {
  4038. uint8_t dscp;
  4039. struct dp_pdev *pdev = (struct dp_pdev *) pdev_handle;
  4040. dscp = (tos >> DP_IP_DSCP_SHIFT) & DP_IP_DSCP_MASK;
  4041. pdev->dscp_tid_map[map_id][dscp] = tid;
  4042. if (map_id < HAL_MAX_HW_DSCP_TID_MAPS)
  4043. hal_tx_update_dscp_tid(pdev->soc->hal_soc, tid,
  4044. map_id, dscp);
  4045. return;
  4046. }
  4047. /**
  4048. * dp_fw_stats_process(): Process TxRX FW stats request
  4049. * @vdev_handle: DP VDEV handle
  4050. * @val: value passed by user
  4051. *
  4052. * return: int
  4053. */
  4054. static int dp_fw_stats_process(struct cdp_vdev *vdev_handle, uint32_t val)
  4055. {
  4056. struct dp_vdev *vdev = (struct dp_vdev *)vdev_handle;
  4057. struct dp_pdev *pdev = NULL;
  4058. if (!vdev) {
  4059. DP_TRACE(NONE, "VDEV not found");
  4060. return 1;
  4061. }
  4062. pdev = vdev->pdev;
  4063. return dp_h2t_ext_stats_msg_send(pdev, val, 0, 0, 0, 0);
  4064. }
  4065. /*
  4066. * dp_txrx_stats() - function to map to firmware and host stats
  4067. * @vdev: virtual handle
  4068. * @stats: type of statistics requested
  4069. *
  4070. * Return: integer
  4071. */
  4072. static int dp_txrx_stats(struct cdp_vdev *vdev, enum cdp_stats stats)
  4073. {
  4074. int host_stats;
  4075. int fw_stats;
  4076. if (stats >= CDP_TXRX_MAX_STATS)
  4077. return 0;
  4078. /*
  4079. * DP_CURR_FW_STATS_AVAIL: no of FW stats currently available
  4080. * has to be updated if new FW HTT stats added
  4081. */
  4082. if (stats > CDP_TXRX_STATS_HTT_MAX)
  4083. stats = stats + DP_CURR_FW_STATS_AVAIL - DP_HTT_DBG_EXT_STATS_MAX;
  4084. fw_stats = dp_stats_mapping_table[stats][STATS_FW];
  4085. host_stats = dp_stats_mapping_table[stats][STATS_HOST];
  4086. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4087. "stats: %u fw_stats_type: %d host_stats_type: %d",
  4088. stats, fw_stats, host_stats);
  4089. if (fw_stats != TXRX_FW_STATS_INVALID)
  4090. return dp_fw_stats_process(vdev, fw_stats);
  4091. if ((host_stats != TXRX_HOST_STATS_INVALID) &&
  4092. (host_stats <= TXRX_HOST_STATS_MAX))
  4093. return dp_print_host_stats(vdev, host_stats);
  4094. else
  4095. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_INFO,
  4096. "Wrong Input for TxRx Stats");
  4097. return 0;
  4098. }
  4099. /*
  4100. * dp_print_napi_stats(): NAPI stats
  4101. * @soc - soc handle
  4102. */
  4103. static void dp_print_napi_stats(struct dp_soc *soc)
  4104. {
  4105. hif_print_napi_stats(soc->hif_handle);
  4106. }
  4107. /*
  4108. * dp_print_per_ring_stats(): Packet count per ring
  4109. * @soc - soc handle
  4110. */
  4111. static void dp_print_per_ring_stats(struct dp_soc *soc)
  4112. {
  4113. uint8_t core, ring;
  4114. uint64_t total_packets;
  4115. DP_TRACE(FATAL, "Reo packets per ring:");
  4116. for (ring = 0; ring < MAX_REO_DEST_RINGS; ring++) {
  4117. total_packets = 0;
  4118. DP_TRACE(FATAL, "Packets on ring %u:", ring);
  4119. for (core = 0; core < NR_CPUS; core++) {
  4120. DP_TRACE(FATAL, "Packets arriving on core %u: %llu",
  4121. core, soc->stats.rx.ring_packets[core][ring]);
  4122. total_packets += soc->stats.rx.ring_packets[core][ring];
  4123. }
  4124. DP_TRACE(FATAL, "Total packets on ring %u: %llu",
  4125. ring, total_packets);
  4126. }
  4127. }
  4128. /*
  4129. * dp_txrx_path_stats() - Function to display dump stats
  4130. * @soc - soc handle
  4131. *
  4132. * return: none
  4133. */
  4134. static void dp_txrx_path_stats(struct dp_soc *soc)
  4135. {
  4136. uint8_t error_code;
  4137. uint8_t loop_pdev;
  4138. struct dp_pdev *pdev;
  4139. uint8_t i;
  4140. for (loop_pdev = 0; loop_pdev < soc->pdev_count; loop_pdev++) {
  4141. pdev = soc->pdev_list[loop_pdev];
  4142. dp_aggregate_pdev_stats(pdev);
  4143. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4144. "Tx path Statistics:");
  4145. DP_TRACE(FATAL, "from stack: %u msdus (%u bytes)",
  4146. pdev->stats.tx_i.rcvd.num,
  4147. pdev->stats.tx_i.rcvd.bytes);
  4148. DP_TRACE(FATAL, "processed from host: %u msdus (%u bytes)",
  4149. pdev->stats.tx_i.processed.num,
  4150. pdev->stats.tx_i.processed.bytes);
  4151. DP_TRACE(FATAL, "successfully transmitted: %u msdus (%u bytes)",
  4152. pdev->stats.tx.tx_success.num,
  4153. pdev->stats.tx.tx_success.bytes);
  4154. DP_TRACE(FATAL, "Dropped in host:");
  4155. DP_TRACE(FATAL, "Total packets dropped: %u,",
  4156. pdev->stats.tx_i.dropped.dropped_pkt.num);
  4157. DP_TRACE(FATAL, "Descriptor not available: %u",
  4158. pdev->stats.tx_i.dropped.desc_na);
  4159. DP_TRACE(FATAL, "Ring full: %u",
  4160. pdev->stats.tx_i.dropped.ring_full);
  4161. DP_TRACE(FATAL, "Enqueue fail: %u",
  4162. pdev->stats.tx_i.dropped.enqueue_fail);
  4163. DP_TRACE(FATAL, "DMA Error: %u",
  4164. pdev->stats.tx_i.dropped.dma_error);
  4165. DP_TRACE(FATAL, "Dropped in hardware:");
  4166. DP_TRACE(FATAL, "total packets dropped: %u",
  4167. pdev->stats.tx.tx_failed);
  4168. DP_TRACE(FATAL, "mpdu age out: %u",
  4169. pdev->stats.tx.dropped.age_out);
  4170. DP_TRACE(FATAL, "firmware removed: %u",
  4171. pdev->stats.tx.dropped.fw_rem);
  4172. DP_TRACE(FATAL, "firmware removed tx: %u",
  4173. pdev->stats.tx.dropped.fw_rem_tx);
  4174. DP_TRACE(FATAL, "firmware removed notx %u",
  4175. pdev->stats.tx.dropped.fw_rem_notx);
  4176. DP_TRACE(FATAL, "peer_invalid: %u",
  4177. pdev->soc->stats.tx.tx_invalid_peer.num);
  4178. DP_TRACE(FATAL, "Tx packets sent per interrupt:");
  4179. DP_TRACE(FATAL, "Single Packet: %u",
  4180. pdev->stats.tx_comp_histogram.pkts_1);
  4181. DP_TRACE(FATAL, "2-20 Packets: %u",
  4182. pdev->stats.tx_comp_histogram.pkts_2_20);
  4183. DP_TRACE(FATAL, "21-40 Packets: %u",
  4184. pdev->stats.tx_comp_histogram.pkts_21_40);
  4185. DP_TRACE(FATAL, "41-60 Packets: %u",
  4186. pdev->stats.tx_comp_histogram.pkts_41_60);
  4187. DP_TRACE(FATAL, "61-80 Packets: %u",
  4188. pdev->stats.tx_comp_histogram.pkts_61_80);
  4189. DP_TRACE(FATAL, "81-100 Packets: %u",
  4190. pdev->stats.tx_comp_histogram.pkts_81_100);
  4191. DP_TRACE(FATAL, "101-200 Packets: %u",
  4192. pdev->stats.tx_comp_histogram.pkts_101_200);
  4193. DP_TRACE(FATAL, " 201+ Packets: %u",
  4194. pdev->stats.tx_comp_histogram.pkts_201_plus);
  4195. DP_TRACE(FATAL, "Rx path statistics");
  4196. DP_TRACE(FATAL, "delivered %u msdus ( %u bytes),",
  4197. pdev->stats.rx.to_stack.num,
  4198. pdev->stats.rx.to_stack.bytes);
  4199. for (i = 0; i < CDP_MAX_RX_RINGS; i++)
  4200. DP_TRACE(FATAL, "received on reo[%d] %u msdus ( %u bytes),",
  4201. i, pdev->stats.rx.rcvd_reo[i].num,
  4202. pdev->stats.rx.rcvd_reo[i].bytes);
  4203. DP_TRACE(FATAL, "intra-bss packets %u msdus ( %u bytes),",
  4204. pdev->stats.rx.intra_bss.pkts.num,
  4205. pdev->stats.rx.intra_bss.pkts.bytes);
  4206. DP_TRACE(FATAL, "raw packets %u msdus ( %u bytes),",
  4207. pdev->stats.rx.raw.num,
  4208. pdev->stats.rx.raw.bytes);
  4209. DP_TRACE(FATAL, "dropped: error %u msdus",
  4210. pdev->stats.rx.err.mic_err);
  4211. DP_TRACE(FATAL, "peer invalid %u",
  4212. pdev->soc->stats.rx.err.rx_invalid_peer.num);
  4213. DP_TRACE(FATAL, "Reo Statistics");
  4214. DP_TRACE(FATAL, "rbm error: %u msdus",
  4215. pdev->soc->stats.rx.err.invalid_rbm);
  4216. DP_TRACE(FATAL, "hal ring access fail: %u msdus",
  4217. pdev->soc->stats.rx.err.hal_ring_access_fail);
  4218. DP_TRACE(FATAL, "Reo errors");
  4219. for (error_code = 0; error_code < HAL_REO_ERR_MAX;
  4220. error_code++) {
  4221. DP_TRACE(FATAL, "Reo error number (%u): %u msdus",
  4222. error_code,
  4223. pdev->soc->stats.rx.err.reo_error[error_code]);
  4224. }
  4225. for (error_code = 0; error_code < HAL_RXDMA_ERR_MAX;
  4226. error_code++) {
  4227. DP_TRACE(FATAL, "Rxdma error number (%u): %u msdus",
  4228. error_code,
  4229. pdev->soc->stats.rx.err
  4230. .rxdma_error[error_code]);
  4231. }
  4232. DP_TRACE(FATAL, "Rx packets reaped per interrupt:");
  4233. DP_TRACE(FATAL, "Single Packet: %u",
  4234. pdev->stats.rx_ind_histogram.pkts_1);
  4235. DP_TRACE(FATAL, "2-20 Packets: %u",
  4236. pdev->stats.rx_ind_histogram.pkts_2_20);
  4237. DP_TRACE(FATAL, "21-40 Packets: %u",
  4238. pdev->stats.rx_ind_histogram.pkts_21_40);
  4239. DP_TRACE(FATAL, "41-60 Packets: %u",
  4240. pdev->stats.rx_ind_histogram.pkts_41_60);
  4241. DP_TRACE(FATAL, "61-80 Packets: %u",
  4242. pdev->stats.rx_ind_histogram.pkts_61_80);
  4243. DP_TRACE(FATAL, "81-100 Packets: %u",
  4244. pdev->stats.rx_ind_histogram.pkts_81_100);
  4245. DP_TRACE(FATAL, "101-200 Packets: %u",
  4246. pdev->stats.rx_ind_histogram.pkts_101_200);
  4247. DP_TRACE(FATAL, " 201+ Packets: %u",
  4248. pdev->stats.rx_ind_histogram.pkts_201_plus);
  4249. }
  4250. }
  4251. /*
  4252. * dp_txrx_dump_stats() - Dump statistics
  4253. * @value - Statistics option
  4254. */
  4255. static QDF_STATUS dp_txrx_dump_stats(void *psoc, uint16_t value)
  4256. {
  4257. struct dp_soc *soc =
  4258. (struct dp_soc *)psoc;
  4259. QDF_STATUS status = QDF_STATUS_SUCCESS;
  4260. if (!soc) {
  4261. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4262. "%s: soc is NULL", __func__);
  4263. return QDF_STATUS_E_INVAL;
  4264. }
  4265. switch (value) {
  4266. case CDP_TXRX_PATH_STATS:
  4267. dp_txrx_path_stats(soc);
  4268. break;
  4269. case CDP_RX_RING_STATS:
  4270. dp_print_per_ring_stats(soc);
  4271. break;
  4272. case CDP_TXRX_TSO_STATS:
  4273. /* TODO: NOT IMPLEMENTED */
  4274. break;
  4275. case CDP_DUMP_TX_FLOW_POOL_INFO:
  4276. cdp_dump_flow_pool_info((struct cdp_soc_t *)soc);
  4277. break;
  4278. case CDP_DP_NAPI_STATS:
  4279. dp_print_napi_stats(soc);
  4280. break;
  4281. case CDP_TXRX_DESC_STATS:
  4282. /* TODO: NOT IMPLEMENTED */
  4283. break;
  4284. default:
  4285. status = QDF_STATUS_E_INVAL;
  4286. break;
  4287. }
  4288. return status;
  4289. }
  4290. static struct cdp_wds_ops dp_ops_wds = {
  4291. .vdev_set_wds = dp_vdev_set_wds,
  4292. };
  4293. /*
  4294. * dp_peer_delete_ast_entries(): Delete all AST entries for a peer
  4295. * @soc - datapath soc handle
  4296. * @peer - datapath peer handle
  4297. *
  4298. * Delete the AST entries belonging to a peer
  4299. */
  4300. #ifdef FEATURE_WDS
  4301. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4302. struct dp_peer *peer)
  4303. {
  4304. struct dp_ast_entry *ast_entry, *temp_ast_entry;
  4305. qdf_spin_lock_bh(&soc->ast_lock);
  4306. DP_PEER_ITERATE_ASE_LIST(peer, ast_entry, temp_ast_entry) {
  4307. if (ast_entry->next_hop) {
  4308. soc->cdp_soc.ol_ops->peer_del_wds_entry(
  4309. peer->vdev->pdev->osif_pdev,
  4310. ast_entry->mac_addr.raw);
  4311. }
  4312. dp_peer_del_ast(soc, ast_entry);
  4313. }
  4314. qdf_spin_unlock_bh(&soc->ast_lock);
  4315. }
  4316. #else
  4317. static inline void dp_peer_delete_ast_entries(struct dp_soc *soc,
  4318. struct dp_peer *peer)
  4319. {
  4320. }
  4321. #endif
  4322. #ifdef CONFIG_WIN
  4323. static void dp_peer_teardown_wifi3(struct cdp_vdev *vdev_hdl, void *peer_hdl)
  4324. {
  4325. struct dp_vdev *vdev = (struct dp_vdev *) vdev_hdl;
  4326. struct dp_peer *peer = (struct dp_peer *) peer_hdl;
  4327. struct dp_soc *soc = (struct dp_soc *) vdev->pdev->soc;
  4328. dp_peer_delete_ast_entries(soc, peer);
  4329. }
  4330. #endif
  4331. static struct cdp_cmn_ops dp_ops_cmn = {
  4332. .txrx_soc_attach_target = dp_soc_attach_target_wifi3,
  4333. .txrx_vdev_attach = dp_vdev_attach_wifi3,
  4334. .txrx_vdev_detach = dp_vdev_detach_wifi3,
  4335. .txrx_pdev_attach = dp_pdev_attach_wifi3,
  4336. .txrx_pdev_detach = dp_pdev_detach_wifi3,
  4337. .txrx_peer_create = dp_peer_create_wifi3,
  4338. .txrx_peer_setup = dp_peer_setup_wifi3,
  4339. #ifdef CONFIG_WIN
  4340. .txrx_peer_teardown = dp_peer_teardown_wifi3,
  4341. #else
  4342. .txrx_peer_teardown = NULL,
  4343. #endif
  4344. .txrx_peer_delete = dp_peer_delete_wifi3,
  4345. .txrx_vdev_register = dp_vdev_register_wifi3,
  4346. .txrx_soc_detach = dp_soc_detach_wifi3,
  4347. .txrx_get_vdev_mac_addr = dp_get_vdev_mac_addr_wifi3,
  4348. .txrx_get_vdev_from_vdev_id = dp_get_vdev_from_vdev_id_wifi3,
  4349. .txrx_get_ctrl_pdev_from_vdev = dp_get_ctrl_pdev_from_vdev_wifi3,
  4350. .addba_requestprocess = dp_addba_requestprocess_wifi3,
  4351. .addba_responsesetup = dp_addba_responsesetup_wifi3,
  4352. .delba_process = dp_delba_process_wifi3,
  4353. .get_peer_mac_addr_frm_id = dp_get_peer_mac_addr_frm_id,
  4354. .flush_cache_rx_queue = NULL,
  4355. /* TODO: get API's for dscp-tid need to be added*/
  4356. .set_vdev_dscp_tid_map = dp_set_vdev_dscp_tid_map_wifi3,
  4357. .set_pdev_dscp_tid_map = dp_set_pdev_dscp_tid_map_wifi3,
  4358. .txrx_stats = dp_txrx_stats,
  4359. .txrx_set_monitor_mode = dp_vdev_set_monitor_mode,
  4360. .display_stats = dp_txrx_dump_stats,
  4361. .txrx_soc_set_nss_cfg = dp_soc_set_nss_cfg_wifi3,
  4362. .txrx_soc_get_nss_cfg = dp_soc_get_nss_cfg_wifi3,
  4363. #ifdef DP_INTR_POLL_BASED
  4364. .txrx_intr_attach = dp_soc_interrupt_attach_wrapper,
  4365. #else
  4366. .txrx_intr_attach = dp_soc_interrupt_attach,
  4367. #endif
  4368. .txrx_intr_detach = dp_soc_interrupt_detach,
  4369. .set_pn_check = dp_set_pn_check_wifi3,
  4370. /* TODO: Add other functions */
  4371. };
  4372. static struct cdp_ctrl_ops dp_ops_ctrl = {
  4373. .txrx_peer_authorize = dp_peer_authorize,
  4374. .txrx_set_vdev_rx_decap_type = dp_set_vdev_rx_decap_type,
  4375. .txrx_set_tx_encap_type = dp_set_vdev_tx_encap_type,
  4376. #ifdef MESH_MODE_SUPPORT
  4377. .txrx_set_mesh_mode = dp_peer_set_mesh_mode,
  4378. .txrx_set_mesh_rx_filter = dp_peer_set_mesh_rx_filter,
  4379. #endif
  4380. .txrx_set_vdev_param = dp_set_vdev_param,
  4381. .txrx_peer_set_nawds = dp_peer_set_nawds,
  4382. .txrx_set_pdev_reo_dest = dp_set_pdev_reo_dest,
  4383. .txrx_get_pdev_reo_dest = dp_get_pdev_reo_dest,
  4384. .txrx_set_filter_neighbour_peers = dp_set_filter_neighbour_peers,
  4385. .txrx_update_filter_neighbour_peers =
  4386. dp_update_filter_neighbour_peers,
  4387. .txrx_get_sec_type = dp_get_sec_type,
  4388. /* TODO: Add other functions */
  4389. .txrx_wdi_event_sub = dp_wdi_event_sub,
  4390. .txrx_wdi_event_unsub = dp_wdi_event_unsub,
  4391. };
  4392. static struct cdp_me_ops dp_ops_me = {
  4393. #ifdef ATH_SUPPORT_IQUE
  4394. .tx_me_alloc_descriptor = dp_tx_me_alloc_descriptor,
  4395. .tx_me_free_descriptor = dp_tx_me_free_descriptor,
  4396. .tx_me_convert_ucast = dp_tx_me_send_convert_ucast,
  4397. #endif
  4398. };
  4399. static struct cdp_mon_ops dp_ops_mon = {
  4400. .txrx_monitor_set_filter_ucast_data = NULL,
  4401. .txrx_monitor_set_filter_mcast_data = NULL,
  4402. .txrx_monitor_set_filter_non_data = NULL,
  4403. .txrx_monitor_get_filter_ucast_data = NULL,
  4404. .txrx_monitor_get_filter_mcast_data = NULL,
  4405. .txrx_monitor_get_filter_non_data = NULL,
  4406. .txrx_reset_monitor_mode = NULL,
  4407. };
  4408. static struct cdp_host_stats_ops dp_ops_host_stats = {
  4409. .txrx_per_peer_stats = dp_get_host_peer_stats,
  4410. .get_fw_peer_stats = dp_get_fw_peer_stats,
  4411. .txrx_enable_enhanced_stats = dp_enable_enhanced_stats,
  4412. .txrx_disable_enhanced_stats = dp_disable_enhanced_stats,
  4413. /* TODO */
  4414. };
  4415. static struct cdp_raw_ops dp_ops_raw = {
  4416. /* TODO */
  4417. };
  4418. #ifdef CONFIG_WIN
  4419. static struct cdp_pflow_ops dp_ops_pflow = {
  4420. /* TODO */
  4421. };
  4422. #endif /* CONFIG_WIN */
  4423. static QDF_STATUS dp_bus_suspend(struct cdp_pdev *opaque_pdev)
  4424. {
  4425. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4426. struct dp_soc *soc = pdev->soc;
  4427. if (soc->intr_mode == DP_INTR_POLL)
  4428. qdf_timer_stop(&soc->int_timer);
  4429. return QDF_STATUS_SUCCESS;
  4430. }
  4431. static QDF_STATUS dp_bus_resume(struct cdp_pdev *opaque_pdev)
  4432. {
  4433. struct dp_pdev *pdev = (struct dp_pdev *)opaque_pdev;
  4434. struct dp_soc *soc = pdev->soc;
  4435. if (soc->intr_mode == DP_INTR_POLL)
  4436. qdf_timer_mod(&soc->int_timer, DP_INTR_POLL_TIMER_MS);
  4437. return QDF_STATUS_SUCCESS;
  4438. }
  4439. #ifndef CONFIG_WIN
  4440. static struct cdp_misc_ops dp_ops_misc = {
  4441. .get_opmode = dp_get_opmode,
  4442. #ifdef FEATURE_RUNTIME_PM
  4443. .runtime_suspend = dp_bus_suspend,
  4444. .runtime_resume = dp_bus_resume,
  4445. #endif
  4446. };
  4447. static struct cdp_flowctl_ops dp_ops_flowctl = {
  4448. /* WIFI 3.0 DP implement as required. */
  4449. #ifdef QCA_LL_TX_FLOW_CONTROL_V2
  4450. .register_pause_cb = dp_txrx_register_pause_cb,
  4451. .dump_flow_pool_info = dp_tx_dump_flow_pool_info,
  4452. #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
  4453. };
  4454. static struct cdp_lflowctl_ops dp_ops_l_flowctl = {
  4455. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4456. };
  4457. #ifdef IPA_OFFLOAD
  4458. static struct cdp_ipa_ops dp_ops_ipa = {
  4459. .ipa_get_resource = dp_ipa_get_resource,
  4460. .ipa_set_doorbell_paddr = dp_ipa_set_doorbell_paddr,
  4461. .ipa_op_response = dp_ipa_op_response,
  4462. .ipa_register_op_cb = dp_ipa_register_op_cb,
  4463. .ipa_get_stat = dp_ipa_get_stat,
  4464. .ipa_tx_data_frame = dp_tx_send_ipa_data_frame,
  4465. .ipa_enable_autonomy = dp_ipa_enable_autonomy,
  4466. .ipa_disable_autonomy = dp_ipa_disable_autonomy,
  4467. .ipa_setup = dp_ipa_setup,
  4468. .ipa_cleanup = dp_ipa_cleanup,
  4469. .ipa_setup_iface = dp_ipa_setup_iface,
  4470. .ipa_cleanup_iface = dp_ipa_cleanup_iface,
  4471. .ipa_enable_pipes = dp_ipa_enable_pipes,
  4472. .ipa_disable_pipes = dp_ipa_disable_pipes,
  4473. .ipa_set_perf_level = dp_ipa_set_perf_level
  4474. };
  4475. #endif
  4476. static struct cdp_bus_ops dp_ops_bus = {
  4477. .bus_suspend = dp_bus_suspend,
  4478. .bus_resume = dp_bus_resume
  4479. };
  4480. static struct cdp_ocb_ops dp_ops_ocb = {
  4481. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4482. };
  4483. static struct cdp_throttle_ops dp_ops_throttle = {
  4484. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4485. };
  4486. static struct cdp_mob_stats_ops dp_ops_mob_stats = {
  4487. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4488. };
  4489. static struct cdp_cfg_ops dp_ops_cfg = {
  4490. /* WIFI 3.0 DP NOT IMPLEMENTED YET */
  4491. };
  4492. static struct cdp_peer_ops dp_ops_peer = {
  4493. .register_peer = dp_register_peer,
  4494. .clear_peer = dp_clear_peer,
  4495. .find_peer_by_addr = dp_find_peer_by_addr,
  4496. .find_peer_by_addr_and_vdev = dp_find_peer_by_addr_and_vdev,
  4497. .local_peer_id = dp_local_peer_id,
  4498. .peer_find_by_local_id = dp_peer_find_by_local_id,
  4499. .peer_state_update = dp_peer_state_update,
  4500. .get_vdevid = dp_get_vdevid,
  4501. .get_vdev_by_sta_id = dp_get_vdev_by_sta_id,
  4502. .peer_get_peer_mac_addr = dp_peer_get_peer_mac_addr,
  4503. .get_vdev_for_peer = dp_get_vdev_for_peer,
  4504. .get_peer_state = dp_get_peer_state,
  4505. .last_assoc_received = dp_get_last_assoc_received,
  4506. .last_disassoc_received = dp_get_last_disassoc_received,
  4507. .last_deauth_received = dp_get_last_deauth_received,
  4508. };
  4509. #endif
  4510. static struct cdp_ops dp_txrx_ops = {
  4511. .cmn_drv_ops = &dp_ops_cmn,
  4512. .ctrl_ops = &dp_ops_ctrl,
  4513. .me_ops = &dp_ops_me,
  4514. .mon_ops = &dp_ops_mon,
  4515. .host_stats_ops = &dp_ops_host_stats,
  4516. .wds_ops = &dp_ops_wds,
  4517. .raw_ops = &dp_ops_raw,
  4518. #ifdef CONFIG_WIN
  4519. .pflow_ops = &dp_ops_pflow,
  4520. #endif /* CONFIG_WIN */
  4521. #ifndef CONFIG_WIN
  4522. .misc_ops = &dp_ops_misc,
  4523. .cfg_ops = &dp_ops_cfg,
  4524. .flowctl_ops = &dp_ops_flowctl,
  4525. .l_flowctl_ops = &dp_ops_l_flowctl,
  4526. #ifdef IPA_OFFLOAD
  4527. .ipa_ops = &dp_ops_ipa,
  4528. #endif
  4529. .bus_ops = &dp_ops_bus,
  4530. .ocb_ops = &dp_ops_ocb,
  4531. .peer_ops = &dp_ops_peer,
  4532. .throttle_ops = &dp_ops_throttle,
  4533. .mob_stats_ops = &dp_ops_mob_stats,
  4534. #endif
  4535. };
  4536. /*
  4537. * dp_soc_set_txrx_ring_map()
  4538. * @dp_soc: DP handler for soc
  4539. *
  4540. * Return: Void
  4541. */
  4542. static void dp_soc_set_txrx_ring_map(struct dp_soc *soc)
  4543. {
  4544. uint32_t i;
  4545. for (i = 0; i < WLAN_CFG_INT_NUM_CONTEXTS; i++) {
  4546. soc->tx_ring_map[i] = dp_cpu_ring_map[DP_DEFAULT_MAP][i];
  4547. }
  4548. }
  4549. /*
  4550. * dp_soc_attach_wifi3() - Attach txrx SOC
  4551. * @osif_soc: Opaque SOC handle from OSIF/HDD
  4552. * @htc_handle: Opaque HTC handle
  4553. * @hif_handle: Opaque HIF handle
  4554. * @qdf_osdev: QDF device
  4555. *
  4556. * Return: DP SOC handle on success, NULL on failure
  4557. */
  4558. /*
  4559. * Local prototype added to temporarily address warning caused by
  4560. * -Wmissing-prototypes. A more correct solution, namely to expose
  4561. * a prototype in an appropriate header file, will come later.
  4562. */
  4563. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4564. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4565. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc);
  4566. void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
  4567. HTC_HANDLE htc_handle, qdf_device_t qdf_osdev,
  4568. struct ol_if_ops *ol_ops, struct wlan_objmgr_psoc *psoc)
  4569. {
  4570. struct dp_soc *soc = qdf_mem_malloc(sizeof(*soc));
  4571. if (!soc) {
  4572. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4573. FL("DP SOC memory allocation failed"));
  4574. goto fail0;
  4575. }
  4576. soc->cdp_soc.ops = &dp_txrx_ops;
  4577. soc->cdp_soc.ol_ops = ol_ops;
  4578. soc->osif_soc = osif_soc;
  4579. soc->osdev = qdf_osdev;
  4580. soc->hif_handle = hif_handle;
  4581. soc->psoc = psoc;
  4582. soc->hal_soc = hif_get_hal_handle(hif_handle);
  4583. soc->htt_handle = htt_soc_attach(soc, osif_soc, htc_handle,
  4584. soc->hal_soc, qdf_osdev);
  4585. if (!soc->htt_handle) {
  4586. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4587. FL("HTT attach failed"));
  4588. goto fail1;
  4589. }
  4590. soc->wlan_cfg_ctx = wlan_cfg_soc_attach();
  4591. if (!soc->wlan_cfg_ctx) {
  4592. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
  4593. FL("wlan_cfg_soc_attach failed"));
  4594. goto fail2;
  4595. }
  4596. if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
  4597. int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
  4598. CDP_CFG_MAX_PEER_ID);
  4599. if (ret != -EINVAL) {
  4600. wlan_cfg_set_max_peer_id(soc->wlan_cfg_ctx, ret);
  4601. }
  4602. }
  4603. qdf_spinlock_create(&soc->peer_ref_mutex);
  4604. qdf_spinlock_create(&soc->reo_desc_freelist_lock);
  4605. qdf_list_create(&soc->reo_desc_freelist, REO_DESC_FREELIST_SIZE);
  4606. /* fill the tx/rx cpu ring map*/
  4607. dp_soc_set_txrx_ring_map(soc);
  4608. qdf_spinlock_create(&soc->htt_stats.lock);
  4609. /* initialize work queue for stats processing */
  4610. qdf_create_work(0, &soc->htt_stats.work, htt_t2h_stats_handler, soc);
  4611. return (void *)soc;
  4612. fail2:
  4613. htt_soc_detach(soc->htt_handle);
  4614. fail1:
  4615. qdf_mem_free(soc);
  4616. fail0:
  4617. return NULL;
  4618. }
  4619. #if defined(CONFIG_WIN) && WDI_EVENT_ENABLE
  4620. /*
  4621. * dp_set_pktlog_wifi3() - attach txrx vdev
  4622. * @pdev: Datapath PDEV handle
  4623. * @event: which event's notifications are being subscribed to
  4624. * @enable: WDI event subscribe or not. (True or False)
  4625. *
  4626. * Return: Success, NULL on failure
  4627. */
  4628. int dp_set_pktlog_wifi3(struct dp_pdev *pdev, uint32_t event,
  4629. bool enable)
  4630. {
  4631. struct dp_soc *soc = pdev->soc;
  4632. struct htt_rx_ring_tlv_filter htt_tlv_filter = {0};
  4633. if (enable) {
  4634. switch (event) {
  4635. case WDI_EVENT_RX_DESC:
  4636. if (pdev->monitor_vdev) {
  4637. /* Nothing needs to be done if monitor mode is
  4638. * enabled
  4639. */
  4640. return 0;
  4641. }
  4642. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_FULL) {
  4643. pdev->rx_pktlog_mode = DP_RX_PKTLOG_FULL;
  4644. htt_tlv_filter.mpdu_start = 1;
  4645. htt_tlv_filter.msdu_start = 1;
  4646. htt_tlv_filter.msdu_end = 1;
  4647. htt_tlv_filter.mpdu_end = 1;
  4648. htt_tlv_filter.packet_header = 1;
  4649. htt_tlv_filter.attention = 1;
  4650. htt_tlv_filter.ppdu_start = 1;
  4651. htt_tlv_filter.ppdu_end = 1;
  4652. htt_tlv_filter.ppdu_end_user_stats = 1;
  4653. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4654. htt_tlv_filter.ppdu_end_status_done = 1;
  4655. htt_tlv_filter.enable_fp = 1;
  4656. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4657. pdev->pdev_id,
  4658. pdev->rxdma_mon_status_ring.hal_srng,
  4659. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4660. &htt_tlv_filter);
  4661. }
  4662. break;
  4663. case WDI_EVENT_LITE_RX:
  4664. if (pdev->monitor_vdev) {
  4665. /* Nothing needs to be done if monitor mode is
  4666. * enabled
  4667. */
  4668. return 0;
  4669. }
  4670. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_LITE) {
  4671. pdev->rx_pktlog_mode = DP_RX_PKTLOG_LITE;
  4672. htt_tlv_filter.ppdu_start = 1;
  4673. htt_tlv_filter.ppdu_end = 1;
  4674. htt_tlv_filter.ppdu_end_user_stats = 1;
  4675. htt_tlv_filter.ppdu_end_user_stats_ext = 1;
  4676. htt_tlv_filter.ppdu_end_status_done = 1;
  4677. htt_tlv_filter.enable_fp = 1;
  4678. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4679. pdev->pdev_id,
  4680. pdev->rxdma_mon_status_ring.hal_srng,
  4681. RXDMA_MONITOR_STATUS,
  4682. RX_BUFFER_SIZE_PKTLOG_LITE,
  4683. &htt_tlv_filter);
  4684. }
  4685. break;
  4686. case WDI_EVENT_LITE_T2H:
  4687. if (pdev->monitor_vdev) {
  4688. /* Nothing needs to be done if monitor mode is
  4689. * enabled
  4690. */
  4691. return 0;
  4692. }
  4693. /* To enable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4694. * passing value 0xffff. Once these macros will define in htt
  4695. * header file will use proper macros
  4696. */
  4697. dp_h2t_cfg_stats_msg_send(pdev, 0xffff);
  4698. break;
  4699. default:
  4700. /* Nothing needs to be done for other pktlog types */
  4701. break;
  4702. }
  4703. } else {
  4704. switch (event) {
  4705. case WDI_EVENT_RX_DESC:
  4706. case WDI_EVENT_LITE_RX:
  4707. if (pdev->monitor_vdev) {
  4708. /* Nothing needs to be done if monitor mode is
  4709. * enabled
  4710. */
  4711. return 0;
  4712. }
  4713. if (pdev->rx_pktlog_mode != DP_RX_PKTLOG_DISABLED) {
  4714. pdev->rx_pktlog_mode = DP_RX_PKTLOG_DISABLED;
  4715. /* htt_tlv_filter is initialized to 0 */
  4716. htt_h2t_rx_ring_cfg(soc->htt_handle,
  4717. pdev->pdev_id,
  4718. pdev->rxdma_mon_status_ring.hal_srng,
  4719. RXDMA_MONITOR_STATUS, RX_BUFFER_SIZE,
  4720. &htt_tlv_filter);
  4721. }
  4722. break;
  4723. case WDI_EVENT_LITE_T2H:
  4724. if (pdev->monitor_vdev) {
  4725. /* Nothing needs to be done if monitor mode is
  4726. * enabled
  4727. */
  4728. return 0;
  4729. }
  4730. /* To disable HTT_H2T_MSG_TYPE_PPDU_STATS_CFG in FW
  4731. * passing value 0. Once these macros will define in htt
  4732. * header file will use proper macros
  4733. */
  4734. dp_h2t_cfg_stats_msg_send(pdev, 0);
  4735. break;
  4736. default:
  4737. /* Nothing needs to be done for other pktlog types */
  4738. break;
  4739. }
  4740. }
  4741. return 0;
  4742. }
  4743. #endif