debug.c 28 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
  3. /* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */
  4. #include <linux/err.h>
  5. #include <linux/seq_file.h>
  6. #include <linux/debugfs.h>
  7. #include "main.h"
  8. #include "bus.h"
  9. #include "debug.h"
  10. #include "pci.h"
  11. #define MMIO_REG_ACCESS_MEM_TYPE 0xFF
  12. #define MMIO_REG_RAW_ACCESS_MEM_TYPE 0xFE
  13. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  14. void *cnss_ipc_log_context;
  15. void *cnss_ipc_log_long_context;
  16. #endif
  17. static int cnss_pin_connect_show(struct seq_file *s, void *data)
  18. {
  19. struct cnss_plat_data *cnss_priv = s->private;
  20. seq_puts(s, "Pin connect results\n");
  21. seq_printf(s, "FW power pin result: %04x\n",
  22. cnss_priv->pin_result.fw_pwr_pin_result);
  23. seq_printf(s, "FW PHY IO pin result: %04x\n",
  24. cnss_priv->pin_result.fw_phy_io_pin_result);
  25. seq_printf(s, "FW RF pin result: %04x\n",
  26. cnss_priv->pin_result.fw_rf_pin_result);
  27. seq_printf(s, "Host pin result: %04x\n",
  28. cnss_priv->pin_result.host_pin_result);
  29. seq_puts(s, "\n");
  30. return 0;
  31. }
  32. static int cnss_pin_connect_open(struct inode *inode, struct file *file)
  33. {
  34. return single_open(file, cnss_pin_connect_show, inode->i_private);
  35. }
  36. static const struct file_operations cnss_pin_connect_fops = {
  37. .read = seq_read,
  38. .release = single_release,
  39. .open = cnss_pin_connect_open,
  40. .owner = THIS_MODULE,
  41. .llseek = seq_lseek,
  42. };
  43. static int cnss_stats_show_state(struct seq_file *s,
  44. struct cnss_plat_data *plat_priv)
  45. {
  46. enum cnss_driver_state i;
  47. int skip = 0;
  48. unsigned long state;
  49. seq_printf(s, "\nState: 0x%lx(", plat_priv->driver_state);
  50. for (i = 0, state = plat_priv->driver_state; state != 0;
  51. state >>= 1, i++) {
  52. if (!(state & 0x1))
  53. continue;
  54. if (skip++)
  55. seq_puts(s, " | ");
  56. switch (i) {
  57. case CNSS_QMI_WLFW_CONNECTED:
  58. seq_puts(s, "QMI_WLFW_CONNECTED");
  59. continue;
  60. case CNSS_FW_MEM_READY:
  61. seq_puts(s, "FW_MEM_READY");
  62. continue;
  63. case CNSS_FW_READY:
  64. seq_puts(s, "FW_READY");
  65. continue;
  66. case CNSS_IN_COLD_BOOT_CAL:
  67. seq_puts(s, "IN_COLD_BOOT_CAL");
  68. continue;
  69. case CNSS_DRIVER_LOADING:
  70. seq_puts(s, "DRIVER_LOADING");
  71. continue;
  72. case CNSS_DRIVER_UNLOADING:
  73. seq_puts(s, "DRIVER_UNLOADING");
  74. continue;
  75. case CNSS_DRIVER_IDLE_RESTART:
  76. seq_puts(s, "IDLE_RESTART");
  77. continue;
  78. case CNSS_DRIVER_IDLE_SHUTDOWN:
  79. seq_puts(s, "IDLE_SHUTDOWN");
  80. continue;
  81. case CNSS_DRIVER_PROBED:
  82. seq_puts(s, "DRIVER_PROBED");
  83. continue;
  84. case CNSS_DRIVER_RECOVERY:
  85. seq_puts(s, "DRIVER_RECOVERY");
  86. continue;
  87. case CNSS_FW_BOOT_RECOVERY:
  88. seq_puts(s, "FW_BOOT_RECOVERY");
  89. continue;
  90. case CNSS_DEV_ERR_NOTIFY:
  91. seq_puts(s, "DEV_ERR");
  92. continue;
  93. case CNSS_DRIVER_DEBUG:
  94. seq_puts(s, "DRIVER_DEBUG");
  95. continue;
  96. case CNSS_COEX_CONNECTED:
  97. seq_puts(s, "COEX_CONNECTED");
  98. continue;
  99. case CNSS_IMS_CONNECTED:
  100. seq_puts(s, "IMS_CONNECTED");
  101. continue;
  102. case CNSS_IN_SUSPEND_RESUME:
  103. seq_puts(s, "IN_SUSPEND_RESUME");
  104. continue;
  105. case CNSS_IN_REBOOT:
  106. seq_puts(s, "IN_REBOOT");
  107. continue;
  108. case CNSS_COLD_BOOT_CAL_DONE:
  109. seq_puts(s, "COLD_BOOT_CAL_DONE");
  110. continue;
  111. case CNSS_IN_PANIC:
  112. seq_puts(s, "IN_PANIC");
  113. continue;
  114. case CNSS_QMI_DEL_SERVER:
  115. seq_puts(s, "DEL_SERVER_IN_PROGRESS");
  116. continue;
  117. case CNSS_QMI_DMS_CONNECTED:
  118. seq_puts(s, "DMS_CONNECTED");
  119. continue;
  120. case CNSS_DAEMON_CONNECTED:
  121. seq_puts(s, "DAEMON_CONNECTED");
  122. continue;
  123. case CNSS_PCI_PROBE_DONE:
  124. seq_puts(s, "PCI PROBE DONE");
  125. continue;
  126. case CNSS_DRIVER_REGISTER:
  127. seq_puts(s, "DRIVER REGISTERED");
  128. continue;
  129. case CNSS_WLAN_HW_DISABLED:
  130. seq_puts(s, "WLAN HW DISABLED");
  131. continue;
  132. case CNSS_FS_READY:
  133. seq_puts(s, "FS READY");
  134. continue;
  135. case CNSS_DRIVER_REGISTERED:
  136. seq_puts(s, "DRIVER REGISTERED");
  137. continue;
  138. }
  139. seq_printf(s, "UNKNOWN-%d", i);
  140. }
  141. seq_puts(s, ")\n");
  142. return 0;
  143. }
  144. static int cnss_stats_show_gpio_state(struct seq_file *s,
  145. struct cnss_plat_data *plat_priv)
  146. {
  147. seq_printf(s, "\nHost SOL: %d", cnss_get_host_sol_value(plat_priv));
  148. seq_printf(s, "\nDev SOL: %d", cnss_get_dev_sol_value(plat_priv));
  149. return 0;
  150. }
  151. static int cnss_stats_show(struct seq_file *s, void *data)
  152. {
  153. struct cnss_plat_data *plat_priv = s->private;
  154. cnss_stats_show_state(s, plat_priv);
  155. cnss_stats_show_gpio_state(s, plat_priv);
  156. return 0;
  157. }
  158. static int cnss_stats_open(struct inode *inode, struct file *file)
  159. {
  160. return single_open(file, cnss_stats_show, inode->i_private);
  161. }
  162. static const struct file_operations cnss_stats_fops = {
  163. .read = seq_read,
  164. .release = single_release,
  165. .open = cnss_stats_open,
  166. .owner = THIS_MODULE,
  167. .llseek = seq_lseek,
  168. };
  169. static ssize_t cnss_dev_boot_debug_write(struct file *fp,
  170. const char __user *user_buf,
  171. size_t count, loff_t *off)
  172. {
  173. struct cnss_plat_data *plat_priv =
  174. ((struct seq_file *)fp->private_data)->private;
  175. struct cnss_pci_data *pci_priv;
  176. char buf[64];
  177. char *cmd;
  178. unsigned int len = 0;
  179. char *sptr, *token;
  180. const char *delim = " ";
  181. int ret = 0;
  182. if (!plat_priv)
  183. return -ENODEV;
  184. len = min(count, sizeof(buf) - 1);
  185. if (copy_from_user(buf, user_buf, len))
  186. return -EFAULT;
  187. buf[len] = '\0';
  188. sptr = buf;
  189. token = strsep(&sptr, delim);
  190. if (!token)
  191. return -EINVAL;
  192. cmd = token;
  193. cnss_pr_dbg("Received dev_boot debug command: %s\n", cmd);
  194. if (sysfs_streq(cmd, "on")) {
  195. ret = cnss_power_on_device(plat_priv);
  196. } else if (sysfs_streq(cmd, "off")) {
  197. cnss_power_off_device(plat_priv);
  198. } else if (sysfs_streq(cmd, "enumerate")) {
  199. ret = cnss_pci_init(plat_priv);
  200. } else if (sysfs_streq(cmd, "powerup")) {
  201. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  202. ret = cnss_driver_event_post(plat_priv,
  203. CNSS_DRIVER_EVENT_POWER_UP,
  204. CNSS_EVENT_SYNC, NULL);
  205. } else if (sysfs_streq(cmd, "shutdown")) {
  206. ret = cnss_driver_event_post(plat_priv,
  207. CNSS_DRIVER_EVENT_POWER_DOWN,
  208. 0, NULL);
  209. clear_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  210. } else if (sysfs_streq(cmd, "assert_host_sol")) {
  211. ret = cnss_set_host_sol_value(plat_priv, 1);
  212. } else if (sysfs_streq(cmd, "deassert_host_sol")) {
  213. ret = cnss_set_host_sol_value(plat_priv, 0);
  214. } else if (sysfs_streq(cmd, "pdc_update")) {
  215. if (!sptr)
  216. return -EINVAL;
  217. ret = cnss_aop_send_msg(plat_priv, sptr);
  218. } else if (sysfs_streq(cmd, "dev_check")) {
  219. cnss_wlan_hw_disable_check(plat_priv);
  220. } else if (sysfs_streq(cmd, "dev_enable")) {
  221. cnss_wlan_hw_enable();
  222. } else {
  223. pci_priv = plat_priv->bus_priv;
  224. if (!pci_priv)
  225. return -ENODEV;
  226. if (sysfs_streq(cmd, "download")) {
  227. set_bit(CNSS_DRIVER_DEBUG, &plat_priv->driver_state);
  228. ret = cnss_pci_start_mhi(pci_priv);
  229. } else if (sysfs_streq(cmd, "linkup")) {
  230. ret = cnss_resume_pci_link(pci_priv);
  231. } else if (sysfs_streq(cmd, "linkdown")) {
  232. ret = cnss_suspend_pci_link(pci_priv);
  233. } else if (sysfs_streq(cmd, "assert")) {
  234. cnss_pr_info("FW Assert triggered for debug\n");
  235. ret = cnss_force_fw_assert(&pci_priv->pci_dev->dev);
  236. } else if (sysfs_streq(cmd, "set_cbc_done")) {
  237. cnss_pr_dbg("Force set cold boot cal done status\n");
  238. set_bit(CNSS_COLD_BOOT_CAL_DONE,
  239. &plat_priv->driver_state);
  240. } else {
  241. cnss_pr_err("Device boot debugfs command is invalid\n");
  242. ret = -EINVAL;
  243. }
  244. }
  245. if (ret < 0)
  246. return ret;
  247. return count;
  248. }
  249. static int cnss_dev_boot_debug_show(struct seq_file *s, void *data)
  250. {
  251. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/dev_boot\n");
  252. seq_puts(s, "<action> can be one of below:\n");
  253. seq_puts(s, "on: turn on device power, assert WLAN_EN\n");
  254. seq_puts(s, "off: de-assert WLAN_EN, turn off device power\n");
  255. seq_puts(s, "enumerate: de-assert PERST, enumerate PCIe\n");
  256. seq_puts(s, "download: download FW and do QMI handshake with FW\n");
  257. seq_puts(s, "linkup: bring up PCIe link\n");
  258. seq_puts(s, "linkdown: bring down PCIe link\n");
  259. seq_puts(s, "powerup: full power on sequence to boot device, download FW and do QMI handshake with FW\n");
  260. seq_puts(s, "shutdown: full power off sequence to shutdown device\n");
  261. seq_puts(s, "assert: trigger firmware assert\n");
  262. seq_puts(s, "set_cbc_done: Set cold boot calibration done status\n");
  263. seq_puts(s, "\npdc_update usage:");
  264. seq_puts(s, "1. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: <vreg>.<mode>, <seq>: <val>} > <debugfs_path>/cnss/dev_boot\n");
  265. seq_puts(s, "2. echo pdc_update {class: wlan_pdc ss: <pdc_ss>, res: pdc, enable: <val>} > <debugfs_path>/cnss/dev_boot\n");
  266. return 0;
  267. }
  268. static int cnss_dev_boot_debug_open(struct inode *inode, struct file *file)
  269. {
  270. return single_open(file, cnss_dev_boot_debug_show, inode->i_private);
  271. }
  272. static const struct file_operations cnss_dev_boot_debug_fops = {
  273. .read = seq_read,
  274. .write = cnss_dev_boot_debug_write,
  275. .release = single_release,
  276. .open = cnss_dev_boot_debug_open,
  277. .owner = THIS_MODULE,
  278. .llseek = seq_lseek,
  279. };
  280. static int cnss_reg_read_debug_show(struct seq_file *s, void *data)
  281. {
  282. struct cnss_plat_data *plat_priv = s->private;
  283. mutex_lock(&plat_priv->dev_lock);
  284. if (!plat_priv->diag_reg_read_buf) {
  285. seq_puts(s, "\nUsage: echo <mem_type> <offset> <data_len> > <debugfs_path>/cnss/reg_read\n");
  286. seq_puts(s, "Use mem_type = 0xff for register read by IO access, data_len will be ignored\n");
  287. seq_puts(s, "Use mem_type = 0xfe for register read by raw IO access which skips sanity checks, data_len will be ignored\n");
  288. seq_puts(s, "Use other mem_type for register read by QMI\n");
  289. mutex_unlock(&plat_priv->dev_lock);
  290. return 0;
  291. }
  292. seq_printf(s, "\nRegister read, address: 0x%x memory type: 0x%x length: 0x%x\n\n",
  293. plat_priv->diag_reg_read_addr,
  294. plat_priv->diag_reg_read_mem_type,
  295. plat_priv->diag_reg_read_len);
  296. seq_hex_dump(s, "", DUMP_PREFIX_OFFSET, 32, 4,
  297. plat_priv->diag_reg_read_buf,
  298. plat_priv->diag_reg_read_len, false);
  299. plat_priv->diag_reg_read_len = 0;
  300. kfree(plat_priv->diag_reg_read_buf);
  301. plat_priv->diag_reg_read_buf = NULL;
  302. mutex_unlock(&plat_priv->dev_lock);
  303. return 0;
  304. }
  305. static ssize_t cnss_reg_read_debug_write(struct file *fp,
  306. const char __user *user_buf,
  307. size_t count, loff_t *off)
  308. {
  309. struct cnss_plat_data *plat_priv =
  310. ((struct seq_file *)fp->private_data)->private;
  311. char buf[64];
  312. char *sptr, *token;
  313. unsigned int len = 0;
  314. u32 reg_offset, mem_type;
  315. u32 data_len = 0, reg_val = 0;
  316. u8 *reg_buf = NULL;
  317. const char *delim = " ";
  318. int ret = 0;
  319. len = min(count, sizeof(buf) - 1);
  320. if (copy_from_user(buf, user_buf, len))
  321. return -EFAULT;
  322. buf[len] = '\0';
  323. sptr = buf;
  324. token = strsep(&sptr, delim);
  325. if (!token)
  326. return -EINVAL;
  327. if (!sptr)
  328. return -EINVAL;
  329. if (kstrtou32(token, 0, &mem_type))
  330. return -EINVAL;
  331. token = strsep(&sptr, delim);
  332. if (!token)
  333. return -EINVAL;
  334. if (!sptr)
  335. return -EINVAL;
  336. if (kstrtou32(token, 0, &reg_offset))
  337. return -EINVAL;
  338. token = strsep(&sptr, delim);
  339. if (!token)
  340. return -EINVAL;
  341. if (kstrtou32(token, 0, &data_len))
  342. return -EINVAL;
  343. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  344. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  345. ret = cnss_bus_debug_reg_read(plat_priv, reg_offset, &reg_val,
  346. mem_type ==
  347. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  348. if (ret)
  349. return ret;
  350. cnss_pr_dbg("Read 0x%x from register offset 0x%x\n", reg_val,
  351. reg_offset);
  352. return count;
  353. }
  354. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  355. cnss_pr_err("Firmware is not ready yet\n");
  356. return -EINVAL;
  357. }
  358. mutex_lock(&plat_priv->dev_lock);
  359. kfree(plat_priv->diag_reg_read_buf);
  360. plat_priv->diag_reg_read_buf = NULL;
  361. reg_buf = kzalloc(data_len, GFP_KERNEL);
  362. if (!reg_buf) {
  363. mutex_unlock(&plat_priv->dev_lock);
  364. return -ENOMEM;
  365. }
  366. ret = cnss_wlfw_athdiag_read_send_sync(plat_priv, reg_offset,
  367. mem_type, data_len,
  368. reg_buf);
  369. if (ret) {
  370. kfree(reg_buf);
  371. mutex_unlock(&plat_priv->dev_lock);
  372. return ret;
  373. }
  374. plat_priv->diag_reg_read_addr = reg_offset;
  375. plat_priv->diag_reg_read_mem_type = mem_type;
  376. plat_priv->diag_reg_read_len = data_len;
  377. plat_priv->diag_reg_read_buf = reg_buf;
  378. mutex_unlock(&plat_priv->dev_lock);
  379. return count;
  380. }
  381. static int cnss_reg_read_debug_open(struct inode *inode, struct file *file)
  382. {
  383. return single_open(file, cnss_reg_read_debug_show, inode->i_private);
  384. }
  385. static const struct file_operations cnss_reg_read_debug_fops = {
  386. .read = seq_read,
  387. .write = cnss_reg_read_debug_write,
  388. .open = cnss_reg_read_debug_open,
  389. .owner = THIS_MODULE,
  390. .llseek = seq_lseek,
  391. };
  392. static int cnss_reg_write_debug_show(struct seq_file *s, void *data)
  393. {
  394. seq_puts(s, "\nUsage: echo <mem_type> <offset> <reg_val> > <debugfs_path>/cnss/reg_write\n");
  395. seq_puts(s, "Use mem_type = 0xff for register write by IO access\n");
  396. seq_puts(s, "Use mem_type = 0xfe for register write by raw IO access which skips sanity checks\n");
  397. seq_puts(s, "Use other mem_type for register write by QMI\n");
  398. return 0;
  399. }
  400. static ssize_t cnss_reg_write_debug_write(struct file *fp,
  401. const char __user *user_buf,
  402. size_t count, loff_t *off)
  403. {
  404. struct cnss_plat_data *plat_priv =
  405. ((struct seq_file *)fp->private_data)->private;
  406. char buf[64];
  407. char *sptr, *token;
  408. unsigned int len = 0;
  409. u32 reg_offset, mem_type, reg_val;
  410. const char *delim = " ";
  411. int ret = 0;
  412. len = min(count, sizeof(buf) - 1);
  413. if (copy_from_user(buf, user_buf, len))
  414. return -EFAULT;
  415. buf[len] = '\0';
  416. sptr = buf;
  417. token = strsep(&sptr, delim);
  418. if (!token)
  419. return -EINVAL;
  420. if (!sptr)
  421. return -EINVAL;
  422. if (kstrtou32(token, 0, &mem_type))
  423. return -EINVAL;
  424. token = strsep(&sptr, delim);
  425. if (!token)
  426. return -EINVAL;
  427. if (!sptr)
  428. return -EINVAL;
  429. if (kstrtou32(token, 0, &reg_offset))
  430. return -EINVAL;
  431. token = strsep(&sptr, delim);
  432. if (!token)
  433. return -EINVAL;
  434. if (kstrtou32(token, 0, &reg_val))
  435. return -EINVAL;
  436. if (mem_type == MMIO_REG_ACCESS_MEM_TYPE ||
  437. mem_type == MMIO_REG_RAW_ACCESS_MEM_TYPE) {
  438. ret = cnss_bus_debug_reg_write(plat_priv, reg_offset, reg_val,
  439. mem_type ==
  440. MMIO_REG_RAW_ACCESS_MEM_TYPE);
  441. if (ret)
  442. return ret;
  443. cnss_pr_dbg("Wrote 0x%x to register offset 0x%x\n", reg_val,
  444. reg_offset);
  445. return count;
  446. }
  447. if (!test_bit(CNSS_FW_READY, &plat_priv->driver_state)) {
  448. cnss_pr_err("Firmware is not ready yet\n");
  449. return -EINVAL;
  450. }
  451. ret = cnss_wlfw_athdiag_write_send_sync(plat_priv, reg_offset, mem_type,
  452. sizeof(u32),
  453. (u8 *)&reg_val);
  454. if (ret)
  455. return ret;
  456. return count;
  457. }
  458. static int cnss_reg_write_debug_open(struct inode *inode, struct file *file)
  459. {
  460. return single_open(file, cnss_reg_write_debug_show, inode->i_private);
  461. }
  462. static const struct file_operations cnss_reg_write_debug_fops = {
  463. .read = seq_read,
  464. .write = cnss_reg_write_debug_write,
  465. .open = cnss_reg_write_debug_open,
  466. .owner = THIS_MODULE,
  467. .llseek = seq_lseek,
  468. };
  469. static ssize_t cnss_runtime_pm_debug_write(struct file *fp,
  470. const char __user *user_buf,
  471. size_t count, loff_t *off)
  472. {
  473. struct cnss_plat_data *plat_priv =
  474. ((struct seq_file *)fp->private_data)->private;
  475. struct cnss_pci_data *pci_priv;
  476. char buf[64];
  477. char *cmd;
  478. unsigned int len = 0;
  479. int ret = 0;
  480. if (!plat_priv)
  481. return -ENODEV;
  482. pci_priv = plat_priv->bus_priv;
  483. if (!pci_priv)
  484. return -ENODEV;
  485. len = min(count, sizeof(buf) - 1);
  486. if (copy_from_user(buf, user_buf, len))
  487. return -EFAULT;
  488. buf[len] = '\0';
  489. cmd = buf;
  490. if (sysfs_streq(cmd, "usage_count")) {
  491. cnss_pci_pm_runtime_show_usage_count(pci_priv);
  492. } else if (sysfs_streq(cmd, "request_resume")) {
  493. ret = cnss_pci_pm_request_resume(pci_priv);
  494. } else if (sysfs_streq(cmd, "resume")) {
  495. ret = cnss_pci_pm_runtime_resume(pci_priv);
  496. } else if (sysfs_streq(cmd, "get")) {
  497. ret = cnss_pci_pm_runtime_get(pci_priv, RTPM_ID_CNSS);
  498. } else if (sysfs_streq(cmd, "get_noresume")) {
  499. cnss_pci_pm_runtime_get_noresume(pci_priv, RTPM_ID_CNSS);
  500. } else if (sysfs_streq(cmd, "put_autosuspend")) {
  501. ret = cnss_pci_pm_runtime_put_autosuspend(pci_priv,
  502. RTPM_ID_CNSS);
  503. } else if (sysfs_streq(cmd, "put_noidle")) {
  504. cnss_pci_pm_runtime_put_noidle(pci_priv, RTPM_ID_CNSS);
  505. } else if (sysfs_streq(cmd, "mark_last_busy")) {
  506. cnss_pci_pm_runtime_mark_last_busy(pci_priv);
  507. } else if (sysfs_streq(cmd, "resume_bus")) {
  508. cnss_pci_resume_bus(pci_priv);
  509. } else if (sysfs_streq(cmd, "suspend_bus")) {
  510. cnss_pci_suspend_bus(pci_priv);
  511. } else {
  512. cnss_pr_err("Runtime PM debugfs command is invalid\n");
  513. ret = -EINVAL;
  514. }
  515. if (ret < 0)
  516. return ret;
  517. return count;
  518. }
  519. static int cnss_runtime_pm_debug_show(struct seq_file *s, void *data)
  520. {
  521. struct cnss_plat_data *plat_priv = s->private;
  522. struct cnss_pci_data *pci_priv;
  523. int i;
  524. if (!plat_priv)
  525. return -ENODEV;
  526. pci_priv = plat_priv->bus_priv;
  527. if (!pci_priv)
  528. return -ENODEV;
  529. seq_puts(s, "\nUsage: echo <action> > <debugfs_path>/cnss/runtime_pm\n");
  530. seq_puts(s, "<action> can be one of below:\n");
  531. seq_puts(s, "usage_count: get runtime PM usage count\n");
  532. seq_puts(s, "reques_resume: do async runtime PM resume\n");
  533. seq_puts(s, "resume: do sync runtime PM resume\n");
  534. seq_puts(s, "get: do runtime PM get\n");
  535. seq_puts(s, "get_noresume: do runtime PM get noresume\n");
  536. seq_puts(s, "put_noidle: do runtime PM put noidle\n");
  537. seq_puts(s, "put_autosuspend: do runtime PM put autosuspend\n");
  538. seq_puts(s, "mark_last_busy: do runtime PM mark last busy\n");
  539. seq_puts(s, "resume_bus: do bus resume only\n");
  540. seq_puts(s, "suspend_bus: do bus suspend only\n");
  541. seq_puts(s, "\nStats:\n");
  542. seq_printf(s, "%s: %u\n", "get count",
  543. atomic_read(&pci_priv->pm_stats.runtime_get));
  544. seq_printf(s, "%s: %u\n", "put count",
  545. atomic_read(&pci_priv->pm_stats.runtime_put));
  546. seq_printf(s, "%-10s%-10s%-10s%-15s%-15s\n",
  547. "id:", "get", "put", "get time(us)", "put time(us)");
  548. for (i = 0; i < RTPM_ID_MAX; i++) {
  549. seq_printf(s, "%d%-9s", i, ":");
  550. seq_printf(s, "%-10d",
  551. atomic_read(&pci_priv->pm_stats.runtime_get_id[i]));
  552. seq_printf(s, "%-10d",
  553. atomic_read(&pci_priv->pm_stats.runtime_put_id[i]));
  554. seq_printf(s, "%-15llu",
  555. pci_priv->pm_stats.runtime_get_timestamp_id[i]);
  556. seq_printf(s, "%-15llu\n",
  557. pci_priv->pm_stats.runtime_put_timestamp_id[i]);
  558. }
  559. return 0;
  560. }
  561. static int cnss_runtime_pm_debug_open(struct inode *inode, struct file *file)
  562. {
  563. return single_open(file, cnss_runtime_pm_debug_show, inode->i_private);
  564. }
  565. static const struct file_operations cnss_runtime_pm_debug_fops = {
  566. .read = seq_read,
  567. .write = cnss_runtime_pm_debug_write,
  568. .open = cnss_runtime_pm_debug_open,
  569. .owner = THIS_MODULE,
  570. .llseek = seq_lseek,
  571. };
  572. static int process_drv(struct cnss_plat_data *plat_priv, bool enabled)
  573. {
  574. if (test_bit(CNSS_QMI_WLFW_CONNECTED, &plat_priv->driver_state)) {
  575. cnss_pr_err("DRV cmd must be used before QMI ready\n");
  576. return -EINVAL;
  577. }
  578. enabled ? cnss_set_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01) :
  579. cnss_clear_feature_list(plat_priv, CNSS_DRV_SUPPORT_V01);
  580. cnss_pr_info("%s DRV suspend\n", enabled ? "enable" : "disable");
  581. return 0;
  582. }
  583. static int process_quirks(struct cnss_plat_data *plat_priv, u32 val)
  584. {
  585. enum cnss_debug_quirks i;
  586. int ret = 0;
  587. unsigned long state;
  588. unsigned long quirks = 0;
  589. for (i = 0, state = val; i < QUIRK_MAX_VALUE; state >>= 1, i++) {
  590. switch (i) {
  591. case DISABLE_DRV:
  592. ret = process_drv(plat_priv, !(state & 0x1));
  593. if (!ret)
  594. quirks |= (state & 0x1) << i;
  595. continue;
  596. default:
  597. quirks |= (state & 0x1) << i;
  598. continue;
  599. }
  600. }
  601. plat_priv->ctrl_params.quirks = quirks;
  602. return 0;
  603. }
  604. static ssize_t cnss_control_params_debug_write(struct file *fp,
  605. const char __user *user_buf,
  606. size_t count, loff_t *off)
  607. {
  608. struct cnss_plat_data *plat_priv =
  609. ((struct seq_file *)fp->private_data)->private;
  610. char buf[64];
  611. char *sptr, *token;
  612. char *cmd;
  613. u32 val;
  614. unsigned int len = 0;
  615. const char *delim = " ";
  616. if (!plat_priv)
  617. return -ENODEV;
  618. len = min(count, sizeof(buf) - 1);
  619. if (copy_from_user(buf, user_buf, len))
  620. return -EFAULT;
  621. buf[len] = '\0';
  622. sptr = buf;
  623. token = strsep(&sptr, delim);
  624. if (!token)
  625. return -EINVAL;
  626. if (!sptr)
  627. return -EINVAL;
  628. cmd = token;
  629. token = strsep(&sptr, delim);
  630. if (!token)
  631. return -EINVAL;
  632. if (kstrtou32(token, 0, &val))
  633. return -EINVAL;
  634. if (strcmp(cmd, "quirks") == 0)
  635. process_quirks(plat_priv, val);
  636. else if (strcmp(cmd, "mhi_timeout") == 0)
  637. plat_priv->ctrl_params.mhi_timeout = val;
  638. else if (strcmp(cmd, "mhi_m2_timeout") == 0)
  639. plat_priv->ctrl_params.mhi_m2_timeout = val;
  640. else if (strcmp(cmd, "qmi_timeout") == 0)
  641. plat_priv->ctrl_params.qmi_timeout = val;
  642. else if (strcmp(cmd, "bdf_type") == 0)
  643. plat_priv->ctrl_params.bdf_type = val;
  644. else if (strcmp(cmd, "time_sync_period") == 0)
  645. plat_priv->ctrl_params.time_sync_period = val;
  646. else
  647. return -EINVAL;
  648. return count;
  649. }
  650. static int cnss_show_quirks_state(struct seq_file *s,
  651. struct cnss_plat_data *plat_priv)
  652. {
  653. enum cnss_debug_quirks i;
  654. int skip = 0;
  655. unsigned long state;
  656. seq_printf(s, "quirks: 0x%lx (", plat_priv->ctrl_params.quirks);
  657. for (i = 0, state = plat_priv->ctrl_params.quirks;
  658. state != 0; state >>= 1, i++) {
  659. if (!(state & 0x1))
  660. continue;
  661. if (skip++)
  662. seq_puts(s, " | ");
  663. switch (i) {
  664. case LINK_DOWN_SELF_RECOVERY:
  665. seq_puts(s, "LINK_DOWN_SELF_RECOVERY");
  666. continue;
  667. case SKIP_DEVICE_BOOT:
  668. seq_puts(s, "SKIP_DEVICE_BOOT");
  669. continue;
  670. case USE_CORE_ONLY_FW:
  671. seq_puts(s, "USE_CORE_ONLY_FW");
  672. continue;
  673. case SKIP_RECOVERY:
  674. seq_puts(s, "SKIP_RECOVERY");
  675. continue;
  676. case QMI_BYPASS:
  677. seq_puts(s, "QMI_BYPASS");
  678. continue;
  679. case ENABLE_WALTEST:
  680. seq_puts(s, "WALTEST");
  681. continue;
  682. case ENABLE_PCI_LINK_DOWN_PANIC:
  683. seq_puts(s, "PCI_LINK_DOWN_PANIC");
  684. continue;
  685. case FBC_BYPASS:
  686. seq_puts(s, "FBC_BYPASS");
  687. continue;
  688. case ENABLE_DAEMON_SUPPORT:
  689. seq_puts(s, "DAEMON_SUPPORT");
  690. continue;
  691. case DISABLE_DRV:
  692. seq_puts(s, "DISABLE_DRV");
  693. continue;
  694. case DISABLE_IO_COHERENCY:
  695. seq_puts(s, "DISABLE_IO_COHERENCY");
  696. continue;
  697. case IGNORE_PCI_LINK_FAILURE:
  698. seq_puts(s, "IGNORE_PCI_LINK_FAILURE");
  699. continue;
  700. case DISABLE_TIME_SYNC:
  701. seq_puts(s, "DISABLE_TIME_SYNC");
  702. continue;
  703. default:
  704. continue;
  705. }
  706. }
  707. seq_puts(s, ")\n");
  708. return 0;
  709. }
  710. static int cnss_control_params_debug_show(struct seq_file *s, void *data)
  711. {
  712. struct cnss_plat_data *cnss_priv = s->private;
  713. seq_puts(s, "\nUsage: echo <params_name> <value> > <debugfs_path>/cnss/control_params\n");
  714. seq_puts(s, "<params_name> can be one of below:\n");
  715. seq_puts(s, "quirks: Debug quirks for driver\n");
  716. seq_puts(s, "mhi_timeout: Timeout for MHI operation in milliseconds\n");
  717. seq_puts(s, "qmi_timeout: Timeout for QMI message in milliseconds\n");
  718. seq_puts(s, "bdf_type: Type of board data file to be downloaded\n");
  719. seq_puts(s, "time_sync_period: Time period to do time sync with device in milliseconds\n");
  720. seq_puts(s, "\nCurrent value:\n");
  721. cnss_show_quirks_state(s, cnss_priv);
  722. seq_printf(s, "mhi_timeout: %u\n", cnss_priv->ctrl_params.mhi_timeout);
  723. seq_printf(s, "mhi_m2_timeout: %u\n",
  724. cnss_priv->ctrl_params.mhi_m2_timeout);
  725. seq_printf(s, "qmi_timeout: %u\n", cnss_priv->ctrl_params.qmi_timeout);
  726. seq_printf(s, "bdf_type: %u\n", cnss_priv->ctrl_params.bdf_type);
  727. seq_printf(s, "time_sync_period: %u\n",
  728. cnss_priv->ctrl_params.time_sync_period);
  729. return 0;
  730. }
  731. static int cnss_control_params_debug_open(struct inode *inode,
  732. struct file *file)
  733. {
  734. return single_open(file, cnss_control_params_debug_show,
  735. inode->i_private);
  736. }
  737. static const struct file_operations cnss_control_params_debug_fops = {
  738. .read = seq_read,
  739. .write = cnss_control_params_debug_write,
  740. .open = cnss_control_params_debug_open,
  741. .owner = THIS_MODULE,
  742. .llseek = seq_lseek,
  743. };
  744. static ssize_t cnss_dynamic_feature_write(struct file *fp,
  745. const char __user *user_buf,
  746. size_t count, loff_t *off)
  747. {
  748. struct cnss_plat_data *plat_priv =
  749. ((struct seq_file *)fp->private_data)->private;
  750. int ret = 0;
  751. u64 val;
  752. ret = kstrtou64_from_user(user_buf, count, 0, &val);
  753. if (ret)
  754. return ret;
  755. plat_priv->dynamic_feature = val;
  756. ret = cnss_wlfw_dynamic_feature_mask_send_sync(plat_priv);
  757. if (ret < 0)
  758. return ret;
  759. return count;
  760. }
  761. static int cnss_dynamic_feature_show(struct seq_file *s, void *data)
  762. {
  763. struct cnss_plat_data *cnss_priv = s->private;
  764. seq_printf(s, "dynamic_feature: 0x%llx\n", cnss_priv->dynamic_feature);
  765. return 0;
  766. }
  767. static int cnss_dynamic_feature_open(struct inode *inode,
  768. struct file *file)
  769. {
  770. return single_open(file, cnss_dynamic_feature_show,
  771. inode->i_private);
  772. }
  773. static const struct file_operations cnss_dynamic_feature_fops = {
  774. .read = seq_read,
  775. .write = cnss_dynamic_feature_write,
  776. .open = cnss_dynamic_feature_open,
  777. .owner = THIS_MODULE,
  778. .llseek = seq_lseek,
  779. };
  780. #ifdef CONFIG_DEBUG_FS
  781. #ifdef CONFIG_CNSS2_DEBUG
  782. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  783. {
  784. struct dentry *root_dentry = plat_priv->root_dentry;
  785. debugfs_create_file("dev_boot", 0600, root_dentry, plat_priv,
  786. &cnss_dev_boot_debug_fops);
  787. debugfs_create_file("reg_read", 0600, root_dentry, plat_priv,
  788. &cnss_reg_read_debug_fops);
  789. debugfs_create_file("reg_write", 0600, root_dentry, plat_priv,
  790. &cnss_reg_write_debug_fops);
  791. debugfs_create_file("runtime_pm", 0600, root_dentry, plat_priv,
  792. &cnss_runtime_pm_debug_fops);
  793. debugfs_create_file("control_params", 0600, root_dentry, plat_priv,
  794. &cnss_control_params_debug_fops);
  795. debugfs_create_file("dynamic_feature", 0600, root_dentry, plat_priv,
  796. &cnss_dynamic_feature_fops);
  797. return 0;
  798. }
  799. #else
  800. static int cnss_create_debug_only_node(struct cnss_plat_data *plat_priv)
  801. {
  802. return 0;
  803. }
  804. #endif
  805. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  806. {
  807. int ret = 0;
  808. struct dentry *root_dentry;
  809. root_dentry = debugfs_create_dir("cnss", 0);
  810. if (IS_ERR(root_dentry)) {
  811. ret = PTR_ERR(root_dentry);
  812. cnss_pr_err("Unable to create debugfs %d\n", ret);
  813. goto out;
  814. }
  815. plat_priv->root_dentry = root_dentry;
  816. debugfs_create_file("pin_connect_result", 0644, root_dentry, plat_priv,
  817. &cnss_pin_connect_fops);
  818. debugfs_create_file("stats", 0644, root_dentry, plat_priv,
  819. &cnss_stats_fops);
  820. cnss_create_debug_only_node(plat_priv);
  821. out:
  822. return ret;
  823. }
  824. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  825. {
  826. debugfs_remove_recursive(plat_priv->root_dentry);
  827. }
  828. #else
  829. int cnss_debugfs_create(struct cnss_plat_data *plat_priv)
  830. {
  831. plat_priv->root_dentry = NULL;
  832. return 0;
  833. }
  834. void cnss_debugfs_destroy(struct cnss_plat_data *plat_priv)
  835. {
  836. }
  837. #endif
  838. #if IS_ENABLED(CONFIG_IPC_LOGGING)
  839. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  840. const char *log_level, char *fmt, ...)
  841. {
  842. struct va_format vaf;
  843. va_list va_args;
  844. va_start(va_args, fmt);
  845. vaf.fmt = fmt;
  846. vaf.va = &va_args;
  847. if (log_level)
  848. printk("%scnss: %pV", log_level, &vaf);
  849. ipc_log_string(log_ctx, "[%s] %s: %pV", process, fn, &vaf);
  850. va_end(va_args);
  851. }
  852. static int cnss_ipc_logging_init(void)
  853. {
  854. cnss_ipc_log_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  855. "cnss", 0);
  856. if (!cnss_ipc_log_context) {
  857. cnss_pr_err("Unable to create IPC log context\n");
  858. return -EINVAL;
  859. }
  860. cnss_ipc_log_long_context = ipc_log_context_create(CNSS_IPC_LOG_PAGES,
  861. "cnss-long", 0);
  862. if (!cnss_ipc_log_long_context) {
  863. cnss_pr_err("Unable to create IPC long log context\n");
  864. ipc_log_context_destroy(cnss_ipc_log_context);
  865. return -EINVAL;
  866. }
  867. return 0;
  868. }
  869. static void cnss_ipc_logging_deinit(void)
  870. {
  871. if (cnss_ipc_log_long_context) {
  872. ipc_log_context_destroy(cnss_ipc_log_long_context);
  873. cnss_ipc_log_long_context = NULL;
  874. }
  875. if (cnss_ipc_log_context) {
  876. ipc_log_context_destroy(cnss_ipc_log_context);
  877. cnss_ipc_log_context = NULL;
  878. }
  879. }
  880. #else
  881. static int cnss_ipc_logging_init(void) { return 0; }
  882. static void cnss_ipc_logging_deinit(void) {}
  883. void cnss_debug_ipc_log_print(void *log_ctx, char *process, const char *fn,
  884. const char *log_level, char *fmt, ...)
  885. {
  886. struct va_format vaf;
  887. va_list va_args;
  888. va_start(va_args, fmt);
  889. vaf.fmt = fmt;
  890. vaf.va = &va_args;
  891. if (log_level)
  892. printk("%scnss: %pV", log_level, &vaf);
  893. va_end(va_args);
  894. }
  895. #endif
  896. int cnss_debug_init(void)
  897. {
  898. return cnss_ipc_logging_init();
  899. }
  900. void cnss_debug_deinit(void)
  901. {
  902. cnss_ipc_logging_deinit();
  903. }