dp_be_rx.c 40 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413
  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_types.h"
  22. #include "dp_rx.h"
  23. #include "dp_be_rx.h"
  24. #include "dp_peer.h"
  25. #include "hal_rx.h"
  26. #include "hal_be_rx.h"
  27. #include "hal_api.h"
  28. #include "hal_be_api.h"
  29. #include "qdf_nbuf.h"
  30. #ifdef MESH_MODE_SUPPORT
  31. #include "if_meta_hdr.h"
  32. #endif
  33. #include "dp_internal.h"
  34. #include "dp_ipa.h"
  35. #ifdef FEATURE_WDS
  36. #include "dp_txrx_wds.h"
  37. #endif
  38. #include "dp_hist.h"
  39. #include "dp_rx_buffer_pool.h"
  40. #ifndef AST_OFFLOAD_ENABLE
  41. static void
  42. dp_rx_wds_learn(struct dp_soc *soc,
  43. struct dp_vdev *vdev,
  44. uint8_t *rx_tlv_hdr,
  45. struct dp_txrx_peer *txrx_peer,
  46. qdf_nbuf_t nbuf,
  47. struct hal_rx_msdu_metadata msdu_metadata)
  48. {
  49. /* WDS Source Port Learning */
  50. if (qdf_likely(vdev->wds_enabled))
  51. dp_rx_wds_srcport_learn(soc,
  52. rx_tlv_hdr,
  53. txrx_peer,
  54. nbuf,
  55. msdu_metadata);
  56. }
  57. #else
  58. #ifdef QCA_SUPPORT_WDS_EXTENDED
  59. /**
  60. * dp_wds_ext_peer_learn_be() - function to send event to control
  61. * path on receiving 1st 4-address frame from backhaul.
  62. * @soc: DP soc
  63. * @ta_txrx_peer: WDS repeater txrx peer
  64. * @rx_tlv_hdr : start address of rx tlvs
  65. *
  66. * Return: void
  67. */
  68. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  69. struct dp_txrx_peer *ta_txrx_peer,
  70. uint8_t *rx_tlv_hdr)
  71. {
  72. uint8_t wds_ext_src_mac[QDF_MAC_ADDR_SIZE];
  73. struct dp_peer *ta_base_peer;
  74. /* instead of checking addr4 is valid or not in per packet path
  75. * check for init bit, which will be set on reception of
  76. * first addr4 valid packet.
  77. */
  78. if (!ta_txrx_peer->vdev->wds_ext_enabled ||
  79. qdf_atomic_test_bit(WDS_EXT_PEER_INIT_BIT,
  80. &ta_txrx_peer->wds_ext.init))
  81. return;
  82. if (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc, rx_tlv_hdr)) {
  83. qdf_atomic_test_and_set_bit(WDS_EXT_PEER_INIT_BIT,
  84. &ta_txrx_peer->wds_ext.init);
  85. ta_base_peer = dp_peer_get_ref_by_id(soc, ta_txrx_peer->peer_id,
  86. DP_MOD_ID_RX);
  87. if (!ta_base_peer)
  88. return;
  89. qdf_mem_copy(wds_ext_src_mac, &ta_base_peer->mac_addr.raw[0],
  90. QDF_MAC_ADDR_SIZE);
  91. dp_peer_unref_delete(ta_base_peer, DP_MOD_ID_RX);
  92. soc->cdp_soc.ol_ops->rx_wds_ext_peer_learn(
  93. soc->ctrl_psoc,
  94. ta_txrx_peer->peer_id,
  95. ta_txrx_peer->vdev->vdev_id,
  96. wds_ext_src_mac);
  97. }
  98. }
  99. #else
  100. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  101. struct dp_txrx_peer *ta_txrx_peer,
  102. uint8_t *rx_tlv_hdr)
  103. {
  104. }
  105. #endif
  106. static void
  107. dp_rx_wds_learn(struct dp_soc *soc,
  108. struct dp_vdev *vdev,
  109. uint8_t *rx_tlv_hdr,
  110. struct dp_txrx_peer *ta_txrx_peer,
  111. qdf_nbuf_t nbuf,
  112. struct hal_rx_msdu_metadata msdu_metadata)
  113. {
  114. dp_wds_ext_peer_learn_be(soc, ta_txrx_peer, rx_tlv_hdr);
  115. }
  116. #endif
  117. /**
  118. * dp_rx_process_be() - Brain of the Rx processing functionality
  119. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  120. * @int_ctx: per interrupt context
  121. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  122. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  123. * @quota: No. of units (packets) that can be serviced in one shot.
  124. *
  125. * This function implements the core of Rx functionality. This is
  126. * expected to handle only non-error frames.
  127. *
  128. * Return: uint32_t: No. of elements processed
  129. */
  130. uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
  131. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  132. uint32_t quota)
  133. {
  134. hal_ring_desc_t ring_desc;
  135. hal_soc_handle_t hal_soc;
  136. struct dp_rx_desc *rx_desc = NULL;
  137. qdf_nbuf_t nbuf, next;
  138. bool near_full;
  139. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  140. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  141. uint32_t num_pending;
  142. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  143. uint16_t msdu_len = 0;
  144. uint16_t peer_id;
  145. uint8_t vdev_id;
  146. struct dp_txrx_peer *txrx_peer;
  147. dp_txrx_ref_handle txrx_ref_handle;
  148. struct dp_vdev *vdev;
  149. uint32_t pkt_len = 0;
  150. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  151. struct hal_rx_msdu_desc_info msdu_desc_info;
  152. enum hal_reo_error_status error;
  153. uint32_t peer_mdata;
  154. uint8_t *rx_tlv_hdr;
  155. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  156. uint8_t mac_id = 0;
  157. struct dp_pdev *rx_pdev;
  158. bool enh_flag;
  159. struct dp_srng *dp_rxdma_srng;
  160. struct rx_desc_pool *rx_desc_pool;
  161. struct dp_soc *soc = int_ctx->soc;
  162. uint8_t core_id = 0;
  163. struct cdp_tid_rx_stats *tid_stats;
  164. qdf_nbuf_t nbuf_head;
  165. qdf_nbuf_t nbuf_tail;
  166. qdf_nbuf_t deliver_list_head;
  167. qdf_nbuf_t deliver_list_tail;
  168. uint32_t num_rx_bufs_reaped = 0;
  169. uint32_t intr_id;
  170. struct hif_opaque_softc *scn;
  171. int32_t tid = 0;
  172. bool is_prev_msdu_last = true;
  173. uint32_t num_entries_avail = 0;
  174. uint32_t rx_ol_pkt_cnt = 0;
  175. uint32_t num_entries = 0;
  176. struct hal_rx_msdu_metadata msdu_metadata;
  177. QDF_STATUS status;
  178. qdf_nbuf_t ebuf_head;
  179. qdf_nbuf_t ebuf_tail;
  180. uint8_t pkt_capture_offload = 0;
  181. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  182. int max_reap_limit, ring_near_full;
  183. struct dp_soc *replenish_soc;
  184. DP_HIST_INIT();
  185. qdf_assert_always(soc && hal_ring_hdl);
  186. hal_soc = soc->hal_soc;
  187. qdf_assert_always(hal_soc);
  188. scn = soc->hif_handle;
  189. hif_pm_runtime_mark_dp_rx_busy(scn);
  190. intr_id = int_ctx->dp_intr_id;
  191. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  192. more_data:
  193. /* reset local variables here to be re-used in the function */
  194. nbuf_head = NULL;
  195. nbuf_tail = NULL;
  196. deliver_list_head = NULL;
  197. deliver_list_tail = NULL;
  198. txrx_peer = NULL;
  199. vdev = NULL;
  200. num_rx_bufs_reaped = 0;
  201. ebuf_head = NULL;
  202. ebuf_tail = NULL;
  203. ring_near_full = 0;
  204. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  205. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  206. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  207. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  208. qdf_mem_zero(head, sizeof(head));
  209. qdf_mem_zero(tail, sizeof(tail));
  210. ring_near_full = _dp_srng_test_and_update_nf_params(soc, rx_ring,
  211. &max_reap_limit);
  212. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  213. /*
  214. * Need API to convert from hal_ring pointer to
  215. * Ring Type / Ring Id combo
  216. */
  217. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  218. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  219. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  220. goto done;
  221. }
  222. /*
  223. * start reaping the buffers from reo ring and queue
  224. * them in per vdev queue.
  225. * Process the received pkts in a different per vdev loop.
  226. */
  227. while (qdf_likely(quota &&
  228. (ring_desc = hal_srng_dst_peek(hal_soc,
  229. hal_ring_hdl)))) {
  230. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  231. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  232. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  233. soc, hal_ring_hdl, error);
  234. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  235. 1);
  236. /* Don't know how to deal with this -- assert */
  237. qdf_assert(0);
  238. }
  239. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  240. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  241. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  242. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  243. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  244. break;
  245. }
  246. rx_desc = (struct dp_rx_desc *)
  247. hal_rx_get_reo_desc_va(ring_desc);
  248. dp_rx_desc_sw_cc_check(soc, rx_buf_cookie, &rx_desc);
  249. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  250. ring_desc, rx_desc);
  251. if (QDF_IS_STATUS_ERROR(status)) {
  252. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  253. qdf_assert_always(!rx_desc->unmapped);
  254. dp_rx_nbuf_unmap(soc, rx_desc, reo_ring_num);
  255. rx_desc->unmapped = 1;
  256. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  257. rx_desc->pool_id);
  258. dp_rx_add_to_free_desc_list(
  259. &head[rx_desc->pool_id],
  260. &tail[rx_desc->pool_id],
  261. rx_desc);
  262. }
  263. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  264. continue;
  265. }
  266. /*
  267. * this is a unlikely scenario where the host is reaping
  268. * a descriptor which it already reaped just a while ago
  269. * but is yet to replenish it back to HW.
  270. * In this case host will dump the last 128 descriptors
  271. * including the software descriptor rx_desc and assert.
  272. */
  273. if (qdf_unlikely(!rx_desc->in_use)) {
  274. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  275. dp_info_rl("Reaping rx_desc not in use!");
  276. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  277. ring_desc, rx_desc);
  278. /* ignore duplicate RX desc and continue to process */
  279. /* Pop out the descriptor */
  280. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  281. continue;
  282. }
  283. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  284. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  285. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  286. dp_info_rl("Nbuf sanity check failure!");
  287. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  288. ring_desc, rx_desc);
  289. rx_desc->in_err_state = 1;
  290. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  291. continue;
  292. }
  293. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  294. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  295. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  296. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  297. ring_desc, rx_desc);
  298. }
  299. /* Get MPDU DESC info */
  300. hal_rx_mpdu_desc_info_get_be(ring_desc, &mpdu_desc_info);
  301. /* Get MSDU DESC info */
  302. hal_rx_msdu_desc_info_get_be(ring_desc, &msdu_desc_info);
  303. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  304. HAL_MSDU_F_MSDU_CONTINUATION)) {
  305. /* previous msdu has end bit set, so current one is
  306. * the new MPDU
  307. */
  308. if (is_prev_msdu_last) {
  309. /* Get number of entries available in HW ring */
  310. num_entries_avail =
  311. hal_srng_dst_num_valid(hal_soc,
  312. hal_ring_hdl, 1);
  313. /* For new MPDU check if we can read complete
  314. * MPDU by comparing the number of buffers
  315. * available and number of buffers needed to
  316. * reap this MPDU
  317. */
  318. if ((msdu_desc_info.msdu_len /
  319. (RX_DATA_BUFFER_SIZE -
  320. soc->rx_pkt_tlv_size) + 1) >
  321. num_entries_avail) {
  322. DP_STATS_INC(soc,
  323. rx.msdu_scatter_wait_break,
  324. 1);
  325. dp_rx_cookie_reset_invalid_bit(
  326. ring_desc);
  327. break;
  328. }
  329. is_prev_msdu_last = false;
  330. }
  331. }
  332. core_id = smp_processor_id();
  333. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  334. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  335. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  336. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  337. HAL_MPDU_F_RAW_AMPDU))
  338. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  339. if (!is_prev_msdu_last &&
  340. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  341. is_prev_msdu_last = true;
  342. /* Pop out the descriptor*/
  343. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  344. rx_bufs_reaped[rx_desc->pool_id]++;
  345. peer_mdata = mpdu_desc_info.peer_meta_data;
  346. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  347. dp_rx_peer_metadata_peer_id_get_be(soc, peer_mdata);
  348. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  349. dp_rx_peer_metadata_vdev_id_get_be(soc, peer_mdata);
  350. /* to indicate whether this msdu is rx offload */
  351. pkt_capture_offload =
  352. DP_PEER_METADATA_OFFLOAD_GET_BE(peer_mdata);
  353. /*
  354. * save msdu flags first, last and continuation msdu in
  355. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  356. * length to nbuf->cb. This ensures the info required for
  357. * per pkt processing is always in the same cache line.
  358. * This helps in improving throughput for smaller pkt
  359. * sizes.
  360. */
  361. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  362. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  363. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  364. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  365. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  366. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  367. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  368. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  369. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  370. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  371. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  372. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  373. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_INTRA_BSS)
  374. qdf_nbuf_set_intra_bss(rx_desc->nbuf, 1);
  375. if (qdf_likely(mpdu_desc_info.mpdu_flags &
  376. HAL_MPDU_F_QOS_CONTROL_VALID))
  377. qdf_nbuf_set_tid_val(rx_desc->nbuf, mpdu_desc_info.tid);
  378. /* set sw exception */
  379. qdf_nbuf_set_rx_reo_dest_ind_or_sw_excpt(
  380. rx_desc->nbuf,
  381. hal_rx_sw_exception_get_be(ring_desc));
  382. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  383. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  384. /*
  385. * move unmap after scattered msdu waiting break logic
  386. * in case double skb unmap happened.
  387. */
  388. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  389. dp_rx_nbuf_unmap(soc, rx_desc, reo_ring_num);
  390. rx_desc->unmapped = 1;
  391. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  392. ebuf_tail, rx_desc);
  393. /*
  394. * if continuation bit is set then we have MSDU spread
  395. * across multiple buffers, let us not decrement quota
  396. * till we reap all buffers of that MSDU.
  397. */
  398. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  399. quota -= 1;
  400. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  401. &tail[rx_desc->pool_id], rx_desc);
  402. num_rx_bufs_reaped++;
  403. /*
  404. * only if complete msdu is received for scatter case,
  405. * then allow break.
  406. */
  407. if (is_prev_msdu_last &&
  408. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  409. max_reap_limit))
  410. break;
  411. }
  412. done:
  413. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  414. replenish_soc = dp_rx_replensih_soc_get(soc, reo_ring_num);
  415. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  416. /*
  417. * continue with next mac_id if no pkts were reaped
  418. * from that pool
  419. */
  420. if (!rx_bufs_reaped[mac_id])
  421. continue;
  422. dp_rxdma_srng = &replenish_soc->rx_refill_buf_ring[mac_id];
  423. rx_desc_pool = &replenish_soc->rx_desc_buf[mac_id];
  424. dp_rx_buffers_replenish(replenish_soc, mac_id, dp_rxdma_srng,
  425. rx_desc_pool, rx_bufs_reaped[mac_id],
  426. &head[mac_id], &tail[mac_id]);
  427. }
  428. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  429. /* Peer can be NULL is case of LFR */
  430. if (qdf_likely(txrx_peer))
  431. vdev = NULL;
  432. /*
  433. * BIG loop where each nbuf is dequeued from global queue,
  434. * processed and queued back on a per vdev basis. These nbufs
  435. * are sent to stack as and when we run out of nbufs
  436. * or a new nbuf dequeued from global queue has a different
  437. * vdev when compared to previous nbuf.
  438. */
  439. nbuf = nbuf_head;
  440. while (nbuf) {
  441. next = nbuf->next;
  442. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  443. nbuf = next;
  444. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  445. continue;
  446. }
  447. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  448. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  449. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  450. if (dp_rx_is_list_ready(deliver_list_head, vdev, txrx_peer,
  451. peer_id, vdev_id)) {
  452. dp_rx_deliver_to_stack(soc, vdev, txrx_peer,
  453. deliver_list_head,
  454. deliver_list_tail);
  455. deliver_list_head = NULL;
  456. deliver_list_tail = NULL;
  457. }
  458. /* Get TID from struct cb->tid_val, save to tid */
  459. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  460. tid = qdf_nbuf_get_tid_val(nbuf);
  461. if (qdf_unlikely(!txrx_peer)) {
  462. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  463. &txrx_ref_handle,
  464. DP_MOD_ID_RX);
  465. } else if (txrx_peer && txrx_peer->peer_id != peer_id) {
  466. dp_txrx_peer_unref_delete(txrx_ref_handle,
  467. DP_MOD_ID_RX);
  468. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  469. &txrx_ref_handle,
  470. DP_MOD_ID_RX);
  471. }
  472. if (txrx_peer) {
  473. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  474. qdf_dp_trace_set_track(nbuf, QDF_RX);
  475. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  476. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  477. QDF_NBUF_RX_PKT_DATA_TRACK;
  478. }
  479. rx_bufs_used++;
  480. if (qdf_likely(txrx_peer)) {
  481. vdev = txrx_peer->vdev;
  482. } else {
  483. nbuf->next = NULL;
  484. dp_rx_deliver_to_pkt_capture_no_peer(
  485. soc, nbuf, pkt_capture_offload);
  486. if (!pkt_capture_offload)
  487. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  488. nbuf = next;
  489. continue;
  490. }
  491. if (qdf_unlikely(!vdev)) {
  492. dp_rx_nbuf_free(nbuf);
  493. nbuf = next;
  494. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  495. continue;
  496. }
  497. /* when hlos tid override is enabled, save tid in
  498. * skb->priority
  499. */
  500. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  501. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  502. qdf_nbuf_set_priority(nbuf, tid);
  503. rx_pdev = vdev->pdev;
  504. DP_RX_TID_SAVE(nbuf, tid);
  505. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  506. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  507. soc->wlan_cfg_ctx)))
  508. qdf_nbuf_set_timestamp(nbuf);
  509. enh_flag = rx_pdev->enhanced_stats_en;
  510. tid_stats =
  511. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  512. /*
  513. * Check if DMA completed -- msdu_done is the last bit
  514. * to be written
  515. */
  516. if (qdf_unlikely(!qdf_nbuf_is_rx_chfrag_cont(nbuf) &&
  517. !hal_rx_attn_msdu_done_get(hal_soc,
  518. rx_tlv_hdr))) {
  519. dp_err("MSDU DONE failure");
  520. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  521. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  522. QDF_TRACE_LEVEL_INFO);
  523. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  524. dp_rx_nbuf_free(nbuf);
  525. qdf_assert(0);
  526. nbuf = next;
  527. continue;
  528. }
  529. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  530. /*
  531. * First IF condition:
  532. * 802.11 Fragmented pkts are reinjected to REO
  533. * HW block as SG pkts and for these pkts we only
  534. * need to pull the RX TLVS header length.
  535. * Second IF condition:
  536. * The below condition happens when an MSDU is spread
  537. * across multiple buffers. This can happen in two cases
  538. * 1. The nbuf size is smaller then the received msdu.
  539. * ex: we have set the nbuf size to 2048 during
  540. * nbuf_alloc. but we received an msdu which is
  541. * 2304 bytes in size then this msdu is spread
  542. * across 2 nbufs.
  543. *
  544. * 2. AMSDUs when RAW mode is enabled.
  545. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  546. * across 1st nbuf and 2nd nbuf and last MSDU is
  547. * spread across 2nd nbuf and 3rd nbuf.
  548. *
  549. * for these scenarios let us create a skb frag_list and
  550. * append these buffers till the last MSDU of the AMSDU
  551. * Third condition:
  552. * This is the most likely case, we receive 802.3 pkts
  553. * decapsulated by HW, here we need to set the pkt length.
  554. */
  555. hal_rx_msdu_metadata_get(hal_soc, rx_tlv_hdr, &msdu_metadata);
  556. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  557. bool is_mcbc, is_sa_vld, is_da_vld;
  558. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  559. rx_tlv_hdr);
  560. is_sa_vld =
  561. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  562. rx_tlv_hdr);
  563. is_da_vld =
  564. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  565. rx_tlv_hdr);
  566. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  567. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  568. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  569. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  570. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  571. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  572. nbuf = dp_rx_sg_create(soc, nbuf);
  573. next = nbuf->next;
  574. if (qdf_nbuf_is_raw_frame(nbuf)) {
  575. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  576. DP_STATS_INC_PKT(peer, rx.raw, 1, msdu_len);
  577. } else {
  578. dp_rx_nbuf_free(nbuf);
  579. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  580. dp_info_rl("scatter msdu len %d, dropped",
  581. msdu_len);
  582. nbuf = next;
  583. continue;
  584. }
  585. } else {
  586. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  587. pkt_len = msdu_len +
  588. msdu_metadata.l3_hdr_pad +
  589. soc->rx_pkt_tlv_size;
  590. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  591. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  592. }
  593. /*
  594. * process frame for mulitpass phrase processing
  595. */
  596. if (qdf_unlikely(vdev->multipass_en)) {
  597. if (dp_rx_multipass_process(txrx_peer, nbuf,
  598. tid) == false) {
  599. DP_STATS_INC(peer, rx.multipass_rx_pkt_drop, 1);
  600. dp_rx_nbuf_free(nbuf);
  601. nbuf = next;
  602. continue;
  603. }
  604. }
  605. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, txrx_peer)) {
  606. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  607. DP_STATS_INC(peer, rx.policy_check_drop, 1);
  608. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  609. /* Drop & free packet */
  610. dp_rx_nbuf_free(nbuf);
  611. /* Statistics */
  612. nbuf = next;
  613. continue;
  614. }
  615. if (qdf_unlikely(txrx_peer && (txrx_peer->nawds_enabled) &&
  616. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  617. (hal_rx_get_mpdu_mac_ad4_valid(soc->hal_soc,
  618. rx_tlv_hdr) ==
  619. false))) {
  620. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  621. DP_STATS_INC(peer, rx.nawds_mcast_drop, 1);
  622. dp_rx_nbuf_free(nbuf);
  623. nbuf = next;
  624. continue;
  625. }
  626. /*
  627. * Drop non-EAPOL frames from unauthorized peer.
  628. */
  629. if (qdf_likely(txrx_peer) &&
  630. qdf_unlikely(!txrx_peer->authorize) &&
  631. !qdf_nbuf_is_raw_frame(nbuf)) {
  632. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  633. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  634. if (!is_eapol) {
  635. DP_STATS_INC(peer,
  636. rx.peer_unauth_rx_pkt_drop, 1);
  637. dp_rx_nbuf_free(nbuf);
  638. nbuf = next;
  639. continue;
  640. }
  641. }
  642. if (soc->process_rx_status)
  643. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  644. /* Update the protocol tag in SKB based on CCE metadata */
  645. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  646. reo_ring_num, false, true);
  647. /* Update the flow tag in SKB based on FSE metadata */
  648. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  649. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, peer,
  650. reo_ring_num, tid_stats);
  651. if (qdf_unlikely(vdev->mesh_vdev)) {
  652. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  653. == QDF_STATUS_SUCCESS) {
  654. dp_rx_info("%pK: mesh pkt filtered", soc);
  655. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  656. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  657. 1);
  658. dp_rx_nbuf_free(nbuf);
  659. nbuf = next;
  660. continue;
  661. }
  662. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr, peer);
  663. }
  664. if (qdf_likely(vdev->rx_decap_type ==
  665. htt_cmn_pkt_type_ethernet) &&
  666. qdf_likely(!vdev->mesh_vdev)) {
  667. dp_rx_wds_learn(soc, vdev,
  668. rx_tlv_hdr,
  669. txrx_peer,
  670. nbuf,
  671. msdu_metadata);
  672. /* Intrabss-fwd */
  673. if (dp_rx_check_ap_bridge(vdev))
  674. if (dp_rx_intrabss_fwd_be(soc, txrx_peer,
  675. rx_tlv_hdr,
  676. nbuf,
  677. msdu_metadata)) {
  678. nbuf = next;
  679. tid_stats->intrabss_cnt++;
  680. continue; /* Get next desc */
  681. }
  682. }
  683. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  684. dp_rx_update_stats(soc, nbuf);
  685. DP_RX_LIST_APPEND(deliver_list_head,
  686. deliver_list_tail,
  687. nbuf);
  688. DP_PEER_TO_STACK_INCC_PKT(peer, 1, QDF_NBUF_CB_RX_PKT_LEN(nbuf),
  689. enh_flag);
  690. if (qdf_unlikely(txrx_peer->in_twt))
  691. DP_STATS_INC_PKT(peer, rx.to_stack_twt, 1,
  692. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  693. tid_stats->delivered_to_stack++;
  694. nbuf = next;
  695. }
  696. if (qdf_likely(deliver_list_head)) {
  697. if (qdf_likely(txrx_peer)) {
  698. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  699. pkt_capture_offload,
  700. deliver_list_head);
  701. if (!pkt_capture_offload)
  702. dp_rx_deliver_to_stack(soc, vdev, txrx_peer,
  703. deliver_list_head,
  704. deliver_list_tail);
  705. } else {
  706. nbuf = deliver_list_head;
  707. while (nbuf) {
  708. next = nbuf->next;
  709. nbuf->next = NULL;
  710. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  711. nbuf = next;
  712. }
  713. }
  714. }
  715. if (qdf_likely(txrx_peer))
  716. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  717. /*
  718. * If we are processing in near-full condition, there are 3 scenario
  719. * 1) Ring entries has reached critical state
  720. * 2) Ring entries are still near high threshold
  721. * 3) Ring entries are below the safe level
  722. *
  723. * One more loop will move the state to normal processing and yield
  724. */
  725. if (ring_near_full && quota)
  726. goto more_data;
  727. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  728. if (quota) {
  729. num_pending =
  730. dp_rx_srng_get_num_pending(hal_soc,
  731. hal_ring_hdl,
  732. num_entries,
  733. &near_full);
  734. if (num_pending) {
  735. DP_STATS_INC(soc, rx.hp_oos2, 1);
  736. if (!hif_exec_should_yield(scn, intr_id))
  737. goto more_data;
  738. if (qdf_unlikely(near_full)) {
  739. DP_STATS_INC(soc, rx.near_full, 1);
  740. goto more_data;
  741. }
  742. }
  743. }
  744. if (vdev && vdev->osif_fisa_flush)
  745. vdev->osif_fisa_flush(soc, reo_ring_num);
  746. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  747. vdev->osif_gro_flush(vdev->osif_vdev,
  748. reo_ring_num);
  749. }
  750. }
  751. /* Update histogram statistics by looping through pdev's */
  752. DP_RX_HIST_STATS_PER_PDEV();
  753. return rx_bufs_used; /* Assume no scale factor for now */
  754. }
  755. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  756. /**
  757. * dp_rx_desc_pool_init_be_cc() - initial RX desc pool for cookie conversion
  758. * @soc: Handle to DP Soc structure
  759. * @rx_desc_pool: Rx descriptor pool handler
  760. * @pool_id: Rx descriptor pool ID
  761. *
  762. * Return: QDF_STATUS_SUCCESS - succeeded, others - failed
  763. */
  764. static QDF_STATUS
  765. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  766. struct rx_desc_pool *rx_desc_pool,
  767. uint32_t pool_id)
  768. {
  769. struct dp_hw_cookie_conversion_t *cc_ctx;
  770. struct dp_soc_be *be_soc;
  771. union dp_rx_desc_list_elem_t *rx_desc_elem;
  772. struct dp_spt_page_desc *page_desc;
  773. uint32_t ppt_idx = 0;
  774. uint32_t avail_entry_index = 0;
  775. if (!rx_desc_pool->pool_size) {
  776. dp_err("desc_num 0 !!");
  777. return QDF_STATUS_E_FAILURE;
  778. }
  779. be_soc = dp_get_be_soc_from_dp_soc(soc);
  780. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  781. page_desc = &cc_ctx->page_desc_base[0];
  782. rx_desc_elem = rx_desc_pool->freelist;
  783. while (rx_desc_elem) {
  784. if (avail_entry_index == 0) {
  785. if (ppt_idx >= cc_ctx->total_page_num) {
  786. dp_alert("insufficient secondary page tables");
  787. qdf_assert_always(0);
  788. }
  789. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  790. }
  791. /* put each RX Desc VA to SPT pages and
  792. * get corresponding ID
  793. */
  794. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  795. avail_entry_index,
  796. &rx_desc_elem->rx_desc);
  797. rx_desc_elem->rx_desc.cookie =
  798. dp_cc_desc_id_generate(page_desc->ppt_index,
  799. avail_entry_index);
  800. rx_desc_elem->rx_desc.pool_id = pool_id;
  801. rx_desc_elem->rx_desc.in_use = 0;
  802. rx_desc_elem = rx_desc_elem->next;
  803. avail_entry_index = (avail_entry_index + 1) &
  804. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  805. }
  806. return QDF_STATUS_SUCCESS;
  807. }
  808. #else
  809. static QDF_STATUS
  810. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  811. struct rx_desc_pool *rx_desc_pool,
  812. uint32_t pool_id)
  813. {
  814. struct dp_hw_cookie_conversion_t *cc_ctx;
  815. struct dp_soc_be *be_soc;
  816. struct dp_spt_page_desc *page_desc;
  817. uint32_t ppt_idx = 0;
  818. uint32_t avail_entry_index = 0;
  819. int i = 0;
  820. if (!rx_desc_pool->pool_size) {
  821. dp_err("desc_num 0 !!");
  822. return QDF_STATUS_E_FAILURE;
  823. }
  824. be_soc = dp_get_be_soc_from_dp_soc(soc);
  825. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  826. page_desc = &cc_ctx->page_desc_base[0];
  827. for (i = 0; i <= rx_desc_pool->pool_size - 1; i++) {
  828. if (i == rx_desc_pool->pool_size - 1)
  829. rx_desc_pool->array[i].next = NULL;
  830. else
  831. rx_desc_pool->array[i].next =
  832. &rx_desc_pool->array[i + 1];
  833. if (avail_entry_index == 0) {
  834. if (ppt_idx >= cc_ctx->total_page_num) {
  835. dp_alert("insufficient secondary page tables");
  836. qdf_assert_always(0);
  837. }
  838. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  839. }
  840. /* put each RX Desc VA to SPT pages and
  841. * get corresponding ID
  842. */
  843. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  844. avail_entry_index,
  845. &rx_desc_pool->array[i].rx_desc);
  846. rx_desc_pool->array[i].rx_desc.cookie =
  847. dp_cc_desc_id_generate(page_desc->ppt_index,
  848. avail_entry_index);
  849. rx_desc_pool->array[i].rx_desc.pool_id = pool_id;
  850. rx_desc_pool->array[i].rx_desc.in_use = 0;
  851. avail_entry_index = (avail_entry_index + 1) &
  852. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  853. }
  854. return QDF_STATUS_SUCCESS;
  855. }
  856. #endif
  857. static void
  858. dp_rx_desc_pool_deinit_be_cc(struct dp_soc *soc,
  859. struct rx_desc_pool *rx_desc_pool,
  860. uint32_t pool_id)
  861. {
  862. struct dp_spt_page_desc *page_desc;
  863. struct dp_soc_be *be_soc;
  864. int i = 0;
  865. struct dp_hw_cookie_conversion_t *cc_ctx;
  866. be_soc = dp_get_be_soc_from_dp_soc(soc);
  867. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  868. for (i = 0; i < cc_ctx->total_page_num; i++) {
  869. page_desc = &cc_ctx->page_desc_base[i];
  870. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  871. }
  872. }
  873. QDF_STATUS dp_rx_desc_pool_init_be(struct dp_soc *soc,
  874. struct rx_desc_pool *rx_desc_pool,
  875. uint32_t pool_id)
  876. {
  877. QDF_STATUS status = QDF_STATUS_SUCCESS;
  878. /* Only regular RX buffer desc pool use HW cookie conversion */
  879. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE) {
  880. dp_info("rx_desc_buf pool init");
  881. status = dp_rx_desc_pool_init_be_cc(soc,
  882. rx_desc_pool,
  883. pool_id);
  884. } else {
  885. dp_info("non_rx_desc_buf_pool init");
  886. status = dp_rx_desc_pool_init_generic(soc, rx_desc_pool,
  887. pool_id);
  888. }
  889. return status;
  890. }
  891. void dp_rx_desc_pool_deinit_be(struct dp_soc *soc,
  892. struct rx_desc_pool *rx_desc_pool,
  893. uint32_t pool_id)
  894. {
  895. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE)
  896. dp_rx_desc_pool_deinit_be_cc(soc, rx_desc_pool, pool_id);
  897. }
  898. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  899. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  900. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  901. void *ring_desc,
  902. struct dp_rx_desc **r_rx_desc)
  903. {
  904. if (hal_rx_wbm_get_cookie_convert_done(ring_desc)) {
  905. /* HW cookie conversion done */
  906. *r_rx_desc = (struct dp_rx_desc *)
  907. hal_rx_wbm_get_desc_va(ring_desc);
  908. } else {
  909. /* SW do cookie conversion */
  910. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  911. *r_rx_desc = (struct dp_rx_desc *)
  912. dp_cc_desc_find(soc, cookie);
  913. }
  914. return QDF_STATUS_SUCCESS;
  915. }
  916. #else
  917. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  918. void *ring_desc,
  919. struct dp_rx_desc **r_rx_desc)
  920. {
  921. *r_rx_desc = (struct dp_rx_desc *)
  922. hal_rx_wbm_get_desc_va(ring_desc);
  923. return QDF_STATUS_SUCCESS;
  924. }
  925. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  926. #else
  927. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  928. void *ring_desc,
  929. struct dp_rx_desc **r_rx_desc)
  930. {
  931. /* SW do cookie conversion */
  932. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  933. *r_rx_desc = (struct dp_rx_desc *)
  934. dp_cc_desc_find(soc, cookie);
  935. return QDF_STATUS_SUCCESS;
  936. }
  937. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  938. struct dp_rx_desc *dp_rx_desc_cookie_2_va_be(struct dp_soc *soc,
  939. uint32_t cookie)
  940. {
  941. return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie);
  942. }
  943. #if defined(WLAN_FEATURE_11BE_MLO)
  944. #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO)
  945. static inline void dp_rx_dummy_src_mac(qdf_nbuf_t nbuf)
  946. {
  947. qdf_ether_header_t *eh =
  948. (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  949. eh->ether_shost[0] = 0x4d; /* M */
  950. eh->ether_shost[1] = 0x4c; /* L */
  951. eh->ether_shost[2] = 0x4d; /* M */
  952. eh->ether_shost[3] = 0x43; /* C */
  953. eh->ether_shost[4] = 0x41; /* A */
  954. eh->ether_shost[5] = 0x53; /* S */
  955. }
  956. bool dp_rx_mlo_igmp_handler(struct dp_soc *soc,
  957. struct dp_vdev *vdev,
  958. struct dp_txrx_peer *peer,
  959. qdf_nbuf_t nbuf)
  960. {
  961. struct dp_vdev *mcast_primary_vdev = NULL;
  962. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  963. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  964. if (!(qdf_nbuf_is_ipv4_igmp_pkt(buf) ||
  965. qdf_nbuf_is_ipv6_igmp_pkt(buf)))
  966. return false;
  967. if (vdev->mcast_enhancement_en || be_vdev->mcast_primary)
  968. goto send_pkt;
  969. mcast_primary_vdev = dp_mlo_get_mcast_primary_vdev(be_soc, be_vdev,
  970. DP_MOD_ID_RX);
  971. if (!mcast_primary_vdev) {
  972. dp_rx_debug("Non mlo vdev");
  973. goto send_pkt;
  974. }
  975. dp_rx_dummy_src_mac(nbuf);
  976. dp_rx_deliver_to_stack(mcast_primary_vdev->pdev->soc,
  977. mcast_primary_vdev,
  978. peer,
  979. nbuf,
  980. NULL);
  981. dp_vdev_unref_delete(mcast_primary_vdev->pdev->soc,
  982. mcast_primary_vdev,
  983. DP_MOD_ID_RX);
  984. return true;
  985. send_pkt:
  986. dp_rx_deliver_to_stack(be_vdev->vdev.pdev->soc,
  987. &be_vdev->vdev,
  988. peer,
  989. nbuf,
  990. NULL);
  991. return true;
  992. }
  993. #else
  994. bool dp_rx_mlo_igmp_handler(struct dp_soc *soc,
  995. struct dp_vdev *vdev,
  996. struct dp_peer *peer,
  997. qdf_nbuf_t nbuf)
  998. {
  999. return false;
  1000. }
  1001. #endif
  1002. #endif
  1003. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1004. uint32_t dp_rx_nf_process(struct dp_intr *int_ctx,
  1005. hal_ring_handle_t hal_ring_hdl,
  1006. uint8_t reo_ring_num,
  1007. uint32_t quota)
  1008. {
  1009. struct dp_soc *soc = int_ctx->soc;
  1010. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  1011. uint32_t work_done = 0;
  1012. if (dp_srng_get_near_full_level(soc, rx_ring) <
  1013. DP_SRNG_THRESH_NEAR_FULL)
  1014. return 0;
  1015. qdf_atomic_set(&rx_ring->near_full, 1);
  1016. work_done++;
  1017. return work_done;
  1018. }
  1019. #endif
  1020. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1021. #ifdef WLAN_FEATURE_11BE_MLO
  1022. /**
  1023. * dp_rx_intrabss_fwd_mlo_allow() - check if MLO forwarding is allowed
  1024. * @ta_peer: transmitter peer handle
  1025. * @da_peer: destination peer handle
  1026. *
  1027. * Return: true - MLO forwarding case, false: not
  1028. */
  1029. static inline bool
  1030. dp_rx_intrabss_fwd_mlo_allow(struct dp_txrx_peer *ta_peer,
  1031. struct dp_txrx_peer *da_peer)
  1032. {
  1033. /* one of TA/DA peer should belong to MLO connection peer,
  1034. * only MLD peer type is as expected
  1035. */
  1036. if (!IS_MLO_DP_MLD_TXRX_PEER(ta_peer) &&
  1037. !IS_MLO_DP_MLD_TXRX_PEER(da_peer))
  1038. return false;
  1039. /* TA peer and DA peer's vdev should be partner MLO vdevs */
  1040. if (dp_peer_find_mac_addr_cmp(&ta_peer->vdev->mld_mac_addr,
  1041. &da_peer->vdev->mld_mac_addr))
  1042. return false;
  1043. return true;
  1044. }
  1045. #else
  1046. static inline bool
  1047. dp_rx_intrabss_fwd_mlo_allow(struct dp_txrx_peer *ta_peer,
  1048. struct dp_txrx_peer *da_peer)
  1049. {
  1050. return false;
  1051. }
  1052. #endif
  1053. #ifdef INTRA_BSS_FWD_OFFLOAD
  1054. /**
  1055. * dp_rx_intrabss_ucast_check_be() - Check if intrabss is allowed
  1056. for unicast frame
  1057. * @soc: SOC hanlde
  1058. * @nbuf: RX packet buffer
  1059. * @ta_peer: transmitter DP peer handle
  1060. * @msdu_metadata: MSDU meta data info
  1061. * @p_tx_vdev_id: get vdev id for Intra-BSS TX
  1062. *
  1063. * Return: true - intrabss allowed
  1064. false - not allow
  1065. */
  1066. static bool
  1067. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1068. struct dp_txrx_peer *ta_peer,
  1069. struct hal_rx_msdu_metadata *msdu_metadata,
  1070. struct dp_be_intrabss_params *params)
  1071. {
  1072. uint16_t da_peer_id;
  1073. struct dp_txrx_peer *da_peer;
  1074. dp_txrx_ref_handle txrx_ref_handle;
  1075. if (!qdf_nbuf_is_intra_bss(nbuf))
  1076. return false;
  1077. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1078. params->dest_soc,
  1079. msdu_metadata->da_idx);
  1080. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1081. &txrx_ref_handle, DP_MOD_ID_RX);
  1082. if (!da_peer)
  1083. return false;
  1084. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1085. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1086. return true;
  1087. }
  1088. #else
  1089. #ifdef WLAN_MLO_MULTI_CHIP
  1090. static bool
  1091. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1092. struct dp_txrx_peer *ta_peer,
  1093. struct hal_rx_msdu_metadata *msdu_metadata,
  1094. struct dp_be_intrabss_params *params)
  1095. {
  1096. uint16_t da_peer_id;
  1097. struct dp_txrx_peer *da_peer;
  1098. bool ret = false;
  1099. uint8_t dest_chip_id;
  1100. uint8_t soc_idx;
  1101. dp_txrx_ref_handle txrx_ref_handle;
  1102. struct dp_vdev_be *be_vdev =
  1103. dp_get_be_vdev_from_dp_vdev(ta_peer->vdev);
  1104. struct dp_soc_be *be_soc =
  1105. dp_get_be_soc_from_dp_soc(params->dest_soc);
  1106. if (!(qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf)))
  1107. return false;
  1108. dest_chip_id = HAL_RX_DEST_CHIP_ID_GET(msdu_metadata);
  1109. qdf_assert_always(dest_chip_id <= (DP_MLO_MAX_DEST_CHIP_ID - 1));
  1110. if (be_soc->mlo_enabled) {
  1111. /* validate chip_id, get a ref, and re-assign soc */
  1112. params->dest_soc =
  1113. dp_mlo_get_soc_ref_by_chip_id(be_soc->ml_ctxt,
  1114. dest_chip_id);
  1115. if (!params->dest_soc)
  1116. return false;
  1117. }
  1118. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(params->dest_soc,
  1119. msdu_metadata->da_idx);
  1120. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1121. &txrx_ref_handle, DP_MOD_ID_RX);
  1122. if (!da_peer)
  1123. return false;
  1124. /* soc unref if needed */
  1125. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1126. /* If the source or destination peer in the isolation
  1127. * list then dont forward instead push to bridge stack.
  1128. */
  1129. if (dp_get_peer_isolation(ta_peer) ||
  1130. dp_get_peer_isolation(da_peer))
  1131. goto rel_da_peer;
  1132. if (da_peer->bss_peer || da_peer == ta_peer)
  1133. goto rel_da_peer;
  1134. /* Same vdev, support Inra-BSS */
  1135. if (da_peer->vdev == ta_peer->vdev) {
  1136. ret = true;
  1137. goto rel_da_peer;
  1138. }
  1139. /* MLO specific Intra-BSS check */
  1140. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1141. /* index of soc in the array */
  1142. soc_idx = dest_chip_id << DP_MLO_DEST_CHIP_ID_SHIFT;
  1143. if (!(be_vdev->partner_vdev_list[soc_idx][0] ==
  1144. params->tx_vdev_id) &&
  1145. !(be_vdev->partner_vdev_list[soc_idx][1] ==
  1146. params->tx_vdev_id)) {
  1147. /*dp_soc_unref_delete(soc);*/
  1148. goto rel_da_peer;
  1149. }
  1150. ret = true;
  1151. }
  1152. rel_da_peer:
  1153. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1154. return ret;
  1155. }
  1156. #else
  1157. static bool
  1158. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1159. struct dp_txrx_peer *ta_peer,
  1160. struct hal_rx_msdu_metadata *msdu_metadata,
  1161. struct dp_be_intrabss_params *params)
  1162. {
  1163. uint16_t da_peer_id;
  1164. struct dp_txrx_peer *da_peer;
  1165. bool ret = false;
  1166. dp_txrx_ref_handle txrx_ref_handle;
  1167. if (!qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf))
  1168. return false;
  1169. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1170. params->dest_soc,
  1171. msdu_metadata->da_idx);
  1172. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1173. &txrx_ref_handle, DP_MOD_ID_RX);
  1174. if (!da_peer)
  1175. return false;
  1176. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1177. /* If the source or destination peer in the isolation
  1178. * list then dont forward instead push to bridge stack.
  1179. */
  1180. if (dp_get_peer_isolation(ta_peer) ||
  1181. dp_get_peer_isolation(da_peer))
  1182. goto rel_da_peer;
  1183. if (da_peer->bss_peer || da_peer == ta_peer)
  1184. goto rel_da_peer;
  1185. /* Same vdev, support Inra-BSS */
  1186. if (da_peer->vdev == ta_peer->vdev) {
  1187. ret = true;
  1188. goto rel_da_peer;
  1189. }
  1190. /* MLO specific Intra-BSS check */
  1191. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1192. ret = true;
  1193. goto rel_da_peer;
  1194. }
  1195. rel_da_peer:
  1196. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1197. return ret;
  1198. }
  1199. #endif /* WLAN_MLO_MULTI_CHIP */
  1200. #endif /* INTRA_BSS_FWD_OFFLOAD */
  1201. /*
  1202. * dp_rx_intrabss_fwd_be() - API for intrabss fwd. For EAPOL
  1203. * pkt with DA not equal to vdev mac addr, fwd is not allowed.
  1204. * @soc: core txrx main context
  1205. * @ta_peer: source peer entry
  1206. * @rx_tlv_hdr: start address of rx tlvs
  1207. * @nbuf: nbuf that has to be intrabss forwarded
  1208. * @msdu_metadata: msdu metadata
  1209. *
  1210. * Return: true if it is forwarded else false
  1211. */
  1212. bool dp_rx_intrabss_fwd_be(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
  1213. uint8_t *rx_tlv_hdr, qdf_nbuf_t nbuf,
  1214. struct hal_rx_msdu_metadata msdu_metadata)
  1215. {
  1216. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  1217. uint8_t ring_id = QDF_NBUF_CB_RX_CTX_ID(nbuf);
  1218. struct cdp_tid_rx_stats *tid_stats = &ta_peer->vdev->pdev->stats.
  1219. tid_stats.tid_rx_stats[ring_id][tid];
  1220. bool ret = false;
  1221. struct dp_be_intrabss_params params;
  1222. /* if it is a broadcast pkt (eg: ARP) and it is not its own
  1223. * source, then clone the pkt and send the cloned pkt for
  1224. * intra BSS forwarding and original pkt up the network stack
  1225. * Note: how do we handle multicast pkts. do we forward
  1226. * all multicast pkts as is or let a higher layer module
  1227. * like igmpsnoop decide whether to forward or not with
  1228. * Mcast enhancement.
  1229. */
  1230. if (qdf_nbuf_is_da_mcbc(nbuf) && !ta_peer->bss_peer) {
  1231. return dp_rx_intrabss_mcbc_fwd(soc, ta_peer, rx_tlv_hdr,
  1232. nbuf, tid_stats);
  1233. }
  1234. if (dp_rx_intrabss_eapol_drop_check(soc, ta_peer, rx_tlv_hdr,
  1235. nbuf))
  1236. return true;
  1237. params.dest_soc = soc;
  1238. if (dp_rx_intrabss_ucast_check_be(nbuf, ta_peer,
  1239. &msdu_metadata, &params)) {
  1240. ret = dp_rx_intrabss_ucast_fwd(params.dest_soc, ta_peer,
  1241. params.tx_vdev_id,
  1242. rx_tlv_hdr, nbuf, tid_stats);
  1243. }
  1244. return ret;
  1245. }
  1246. #endif