98ac941a1b
Change updates frame transfer time calculations. Frame threshold is provided as input to decide on the final transfer time. Panel dsi clock node followed by mdp transfer time node will take priority in selecting final transfer time than frame threshold time. Change-Id: I40c3abfc635cd9b338b705535612ac32e047ce6e Signed-off-by: Vara Reddy <varar@codeaurora.org>
805 lines
26 KiB
C
805 lines
26 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DSI_CTRL_H_
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#define _DSI_CTRL_H_
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#include <linux/debugfs.h>
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#include "dsi_defs.h"
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#include "dsi_ctrl_hw.h"
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#include "dsi_clk.h"
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#include "dsi_pwr.h"
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#include "drm_mipi_dsi.h"
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/*
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* DSI Command transfer modifiers
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* @DSI_CTRL_CMD_READ: The current transfer involves reading data.
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* @DSI_CTRL_CMD_BROADCAST: The current transfer needs to be done in
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* broadcast mode to multiple slaves.
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* @DSI_CTRL_CMD_BROADCAST_MASTER: This controller is the master and the slaves
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* sync to this trigger.
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* @DSI_CTRL_CMD_DEFER_TRIGGER: Defer the command trigger to later.
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* @DSI_CTRL_CMD_FIFO_STORE: Use FIFO for command transfer in place of
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* reading data from memory.
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* @DSI_CTRL_CMD_FETCH_MEMORY: Fetch command from memory through AXI bus
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* and transfer it.
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* @DSI_CTRL_CMD_LAST_COMMAND: Trigger the DMA cmd transfer if this is last
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* command in the batch.
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* @DSI_CTRL_CMD_NON_EMBEDDED_MODE:Transfer cmd packets in non embedded mode.
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* @DSI_CTRL_CMD_CUSTOM_DMA_SCHED: Use the dma scheduling line number defined in
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* display panel dtsi file instead of default.
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*/
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#define DSI_CTRL_CMD_READ 0x1
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#define DSI_CTRL_CMD_BROADCAST 0x2
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#define DSI_CTRL_CMD_BROADCAST_MASTER 0x4
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#define DSI_CTRL_CMD_DEFER_TRIGGER 0x8
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#define DSI_CTRL_CMD_FIFO_STORE 0x10
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#define DSI_CTRL_CMD_FETCH_MEMORY 0x20
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#define DSI_CTRL_CMD_LAST_COMMAND 0x40
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#define DSI_CTRL_CMD_NON_EMBEDDED_MODE 0x80
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#define DSI_CTRL_CMD_CUSTOM_DMA_SCHED 0x100
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/* DSI embedded mode fifo size
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* If the command is greater than 256 bytes it is sent in non-embedded mode.
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*/
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#define DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES 256
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/* max size supported for dsi cmd transfer using TPG */
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#define DSI_CTRL_MAX_CMD_FIFO_STORE_SIZE 64
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/**
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* enum dsi_power_state - defines power states for dsi controller.
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* @DSI_CTRL_POWER_VREG_OFF: Digital and analog supplies for DSI controller
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turned off
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* @DSI_CTRL_POWER_VREG_ON: Digital and analog supplies for DSI controller
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* @DSI_CTRL_POWER_MAX: Maximum value.
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*/
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enum dsi_power_state {
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DSI_CTRL_POWER_VREG_OFF = 0,
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DSI_CTRL_POWER_VREG_ON,
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DSI_CTRL_POWER_MAX,
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};
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/**
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* enum dsi_engine_state - define engine status for dsi controller.
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* @DSI_CTRL_ENGINE_OFF: Engine is turned off.
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* @DSI_CTRL_ENGINE_ON: Engine is turned on.
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* @DSI_CTRL_ENGINE_MAX: Maximum value.
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*/
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enum dsi_engine_state {
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DSI_CTRL_ENGINE_OFF = 0,
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DSI_CTRL_ENGINE_ON,
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DSI_CTRL_ENGINE_MAX,
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};
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/**
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* struct dsi_ctrl_power_info - digital and analog power supplies for dsi host
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* @digital: Digital power supply required to turn on DSI controller hardware.
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* @host_pwr: Analog power supplies required to turn on DSI controller hardware.
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* Even though DSI controller it self does not require an analog
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* power supply, supplies required for PLL can be defined here to
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* allow proper control over these supplies.
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*/
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struct dsi_ctrl_power_info {
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struct dsi_regulator_info digital;
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struct dsi_regulator_info host_pwr;
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};
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/**
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* struct dsi_ctrl_clk_info - clock information for DSI controller
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* @core_clks: Core clocks needed to access DSI controller registers.
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* @hs_link_clks: Clocks required to transmit high speed data over DSI
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* @lp_link_clks: Clocks required to perform low power ops over DSI
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* @rcg_clks: Root clock generation clocks generated in MMSS_CC. The
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* output of the PLL is set as parent for these root
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* clocks. These clocks are specific to controller
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* instance.
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* @mux_clks: Mux clocks used for Dynamic refresh feature.
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* @ext_clks: External byte/pixel clocks from the MMSS block. These
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* clocks are set as parent to rcg clocks.
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* @pll_op_clks: TODO:
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* @shadow_clks: TODO:
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*/
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struct dsi_ctrl_clk_info {
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/* Clocks parsed from DT */
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struct dsi_core_clk_info core_clks;
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struct dsi_link_hs_clk_info hs_link_clks;
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struct dsi_link_lp_clk_info lp_link_clks;
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struct dsi_clk_link_set rcg_clks;
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/* Clocks set by DSI Manager */
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struct dsi_clk_link_set mux_clks;
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struct dsi_clk_link_set ext_clks;
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struct dsi_clk_link_set pll_op_clks;
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struct dsi_clk_link_set shadow_clks;
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};
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/**
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* struct dsi_ctrl_bus_scale_info - Bus scale info for msm-bus bandwidth voting
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* @bus_scale_table: Bus scale voting usecases.
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* @bus_handle: Handle used for voting bandwidth.
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*/
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struct dsi_ctrl_bus_scale_info {
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struct msm_bus_scale_pdata *bus_scale_table;
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u32 bus_handle;
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};
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/**
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* struct dsi_ctrl_state_info - current driver state information
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* @power_state: Status of power states on DSI controller.
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* @cmd_engine_state: Status of DSI command engine.
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* @vid_engine_state: Status of DSI video engine.
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* @controller_state: Status of DSI Controller engine.
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* @host_initialized: Boolean to indicate status of DSi host Initialization
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* @tpg_enabled: Boolean to indicate whether tpg is enabled.
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*/
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struct dsi_ctrl_state_info {
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enum dsi_power_state power_state;
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enum dsi_engine_state cmd_engine_state;
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enum dsi_engine_state vid_engine_state;
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enum dsi_engine_state controller_state;
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bool host_initialized;
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bool tpg_enabled;
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};
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/**
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* struct dsi_ctrl_interrupts - define interrupt information
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* @irq_lock: Spinlock for ISR handler.
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* @irq_num: Linux interrupt number associated with device.
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* @irq_stat_mask: Hardware mask of currently enabled interrupts.
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* @irq_stat_refcount: Number of times each interrupt has been requested.
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* @irq_stat_cb: Status IRQ callback definitions.
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* @irq_err_cb: IRQ callback definition to handle DSI ERRORs.
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* @cmd_dma_done: Completion signal for DSI_CMD_MODE_DMA_DONE interrupt
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* @vid_frame_done: Completion signal for DSI_VIDEO_MODE_FRAME_DONE int.
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* @cmd_frame_done: Completion signal for DSI_CMD_FRAME_DONE interrupt.
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*/
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struct dsi_ctrl_interrupts {
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spinlock_t irq_lock;
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int irq_num;
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uint32_t irq_stat_mask;
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int irq_stat_refcount[DSI_STATUS_INTERRUPT_COUNT];
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struct dsi_event_cb_info irq_stat_cb[DSI_STATUS_INTERRUPT_COUNT];
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struct dsi_event_cb_info irq_err_cb;
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struct completion cmd_dma_done;
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struct completion vid_frame_done;
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struct completion cmd_frame_done;
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struct completion bta_done;
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};
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/**
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* struct dsi_ctrl - DSI controller object
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* @pdev: Pointer to platform device.
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* @cell_index: Instance cell id.
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* @horiz_index: Index in physical horizontal CTRL layout, 0 = leftmost
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* @name: Name of the controller instance.
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* @refcount: ref counter.
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* @ctrl_lock: Mutex for hardware and object access.
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* @drm_dev: Pointer to DRM device.
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* @version: DSI controller version.
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* @hw: DSI controller hardware object.
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* @current_state: Current driver and hardware state.
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* @clk_cb: Callback for DSI clock control.
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* @irq_info: Interrupt information.
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* @recovery_cb: Recovery call back to SDE.
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* @clk_info: Clock information.
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* @clk_freq: DSi Link clock frequency information.
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* @pwr_info: Power information.
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* @axi_bus_info: AXI bus information.
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* @host_config: Current host configuration.
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* @mode_bounds: Boundaries of the default mode ROI.
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* Origin is at top left of all CTRLs.
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* @roi: Partial update region of interest.
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* Origin is top left of this CTRL.
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* @tx_cmd_buf: Tx command buffer.
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* @cmd_buffer_iova: cmd buffer mapped address.
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* @cmd_buffer_size: Size of command buffer.
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* @vaddr: CPU virtual address of cmd buffer.
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* @secure_mode: Indicates if secure-session is in progress
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* @esd_check_underway: Indicates if esd status check is in progress
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* @debugfs_root: Root for debugfs entries.
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* @misr_enable: Frame MISR enable/disable
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* @misr_cache: Cached Frame MISR value
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* @frame_threshold_time_us: Frame threshold time in microseconds, where
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* dsi data lane will be idle i.e from pingpong done to
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* next TE for command mode.
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* @phy_isolation_enabled: A boolean property allows to isolate the phy from
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* dsi controller and run only dsi controller.
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* @null_insertion_enabled: A boolean property to allow dsi controller to
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* insert null packet.
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* @modeupdated: Boolean to send new roi if mode is updated.
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*/
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struct dsi_ctrl {
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struct platform_device *pdev;
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u32 cell_index;
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u32 horiz_index;
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const char *name;
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u32 refcount;
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struct mutex ctrl_lock;
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struct drm_device *drm_dev;
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enum dsi_ctrl_version version;
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struct dsi_ctrl_hw hw;
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/* Current state */
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struct dsi_ctrl_state_info current_state;
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struct clk_ctrl_cb clk_cb;
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struct dsi_ctrl_interrupts irq_info;
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struct dsi_event_cb_info recovery_cb;
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/* Clock and power states */
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struct dsi_ctrl_clk_info clk_info;
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struct link_clk_freq clk_freq;
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struct dsi_ctrl_power_info pwr_info;
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struct dsi_ctrl_bus_scale_info axi_bus_info;
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struct dsi_host_config host_config;
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struct dsi_rect mode_bounds;
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struct dsi_rect roi;
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/* Command tx and rx */
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struct drm_gem_object *tx_cmd_buf;
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u32 cmd_buffer_size;
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u32 cmd_buffer_iova;
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u32 cmd_len;
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void *vaddr;
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bool secure_mode;
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bool esd_check_underway;
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/* Debug Information */
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struct dentry *debugfs_root;
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/* MISR */
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bool misr_enable;
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u32 misr_cache;
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u32 frame_threshold_time_us;
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/* Check for spurious interrupts */
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unsigned long jiffies_start;
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unsigned int error_interrupt_count;
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bool phy_isolation_enabled;
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bool null_insertion_enabled;
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bool modeupdated;
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};
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/**
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* dsi_ctrl_get() - get a dsi_ctrl handle from an of_node
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* @of_node: of_node of the DSI controller.
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*
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* Gets the DSI controller handle for the corresponding of_node. The ref count
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* is incremented to one and all subsequent gets will fail until the original
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* clients calls a put.
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*
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* Return: DSI Controller handle.
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*/
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struct dsi_ctrl *dsi_ctrl_get(struct device_node *of_node);
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/**
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* dsi_ctrl_put() - releases a dsi controller handle.
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* @dsi_ctrl: DSI controller handle.
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*
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* Releases the DSI controller. Driver will clean up all resources and puts back
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* the DSI controller into reset state.
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*/
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void dsi_ctrl_put(struct dsi_ctrl *dsi_ctrl);
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/**
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* dsi_ctrl_drv_init() - initialize dsi controller driver.
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* @dsi_ctrl: DSI controller handle.
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* @parent: Parent directory for debug fs.
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*
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* Initializes DSI controller driver. Driver should be initialized after
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* dsi_ctrl_get() succeeds.
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*
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* Return: error code.
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*/
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int dsi_ctrl_drv_init(struct dsi_ctrl *dsi_ctrl, struct dentry *parent);
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/**
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* dsi_ctrl_drv_deinit() - de-initializes dsi controller driver
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* @dsi_ctrl: DSI controller handle.
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*
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* Releases all resources acquired by dsi_ctrl_drv_init().
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*
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* Return: error code.
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*/
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int dsi_ctrl_drv_deinit(struct dsi_ctrl *dsi_ctrl);
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/**
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* dsi_ctrl_validate_timing() - validate a video timing configuration
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* @dsi_ctrl: DSI controller handle.
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* @timing: Pointer to timing data.
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*
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* Driver will validate if the timing configuration is supported on the
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* controller hardware.
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*
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* Return: error code if timing is not supported.
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*/
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int dsi_ctrl_validate_timing(struct dsi_ctrl *dsi_ctrl,
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struct dsi_mode_info *timing);
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/**
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* dsi_ctrl_update_host_config() - update dsi host configuration
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* @dsi_ctrl: DSI controller handle.
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* @config: DSI host configuration.
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* @mode: DSI host mode selected.
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* @flags: dsi_mode_flags modifying the behavior
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* @clk_handle: Clock handle for DSI clocks
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*
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* Updates driver with new Host configuration to use for host initialization.
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* This function call will only update the software context. The stored
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* configuration information will be used when the host is initialized.
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*
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* Return: error code.
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*/
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int dsi_ctrl_update_host_config(struct dsi_ctrl *dsi_ctrl,
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struct dsi_host_config *config,
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struct dsi_display_mode *mode, int flags,
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void *clk_handle);
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/**
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* dsi_ctrl_timing_db_update() - update only controller Timing DB
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* @dsi_ctrl: DSI controller handle.
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* @enable: Enable/disable Timing DB register
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*
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* Update timing db register value during dfps usecases
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*
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* Return: error code.
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*/
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int dsi_ctrl_timing_db_update(struct dsi_ctrl *dsi_ctrl,
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bool enable);
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/**
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* dsi_ctrl_async_timing_update() - update only controller timing
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* @dsi_ctrl: DSI controller handle.
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* @timing: New DSI timing info
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*
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* Updates host timing values to asynchronously transition to new timing
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* For example, to update the porch values in a seamless/dynamic fps switch.
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*
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* Return: error code.
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*/
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int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl,
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struct dsi_mode_info *timing);
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/**
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* dsi_ctrl_phy_sw_reset() - perform a PHY software reset
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* @dsi_ctrl: DSI controller handle.
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*
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* Performs a PHY software reset on the DSI controller. Reset should be done
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* when the controller power state is DSI_CTRL_POWER_CORE_CLK_ON and the PHY is
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* not enabled.
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*
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* This function will fail if driver is in any other state.
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*
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* Return: error code.
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*/
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int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl);
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/**
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* dsi_ctrl_phy_reset_config() - Mask/unmask propagation of ahb reset signal
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* to DSI PHY hardware.
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* @dsi_ctrl: DSI controller handle.
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* @enable: Mask/unmask the PHY reset signal.
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*
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* Return: error code.
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*/
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int dsi_ctrl_phy_reset_config(struct dsi_ctrl *dsi_ctrl, bool enable);
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/**
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* dsi_ctrl_config_clk_gating() - Enable/Disable DSI PHY clk gating
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* @dsi_ctrl: DSI controller handle.
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* @enable: Enable/disable DSI PHY clk gating
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* @clk_selection: clock selection for gating
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*
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* Return: error code.
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*/
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int dsi_ctrl_config_clk_gating(struct dsi_ctrl *dsi_ctrl, bool enable,
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enum dsi_clk_gate_type clk_selection);
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/**
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* dsi_ctrl_soft_reset() - perform a soft reset on DSI controller
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* @dsi_ctrl: DSI controller handle.
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*
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* The video, command and controller engines will be disabled before the
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* reset is triggered. After, the engines will be re-enabled to the same state
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* as before the reset.
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*
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* If the reset is done while MDP timing engine is turned on, the video
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* engine should be re-enabled only during the vertical blanking time.
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*
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* Return: error code
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*/
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int dsi_ctrl_soft_reset(struct dsi_ctrl *dsi_ctrl);
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/**
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* dsi_ctrl_host_timing_update - reinitialize host with new timing values
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* @dsi_ctrl: DSI controller handle.
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*
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* Reinitialize DSI controller hardware with new display timing values
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* when resolution is switched dynamically.
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*
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* Return: error code
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*/
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int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl);
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/**
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* dsi_ctrl_host_init() - Initialize DSI host hardware.
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* @dsi_ctrl: DSI controller handle.
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* @is_splash_enabled: boolean signifying splash status.
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*
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* Initializes DSI controller hardware with host configuration provided by
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* dsi_ctrl_update_host_config(). Initialization can be performed only during
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* DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been
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* performed.
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*
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* Return: error code.
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*/
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int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl, bool is_splash_enabled);
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/**
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* dsi_ctrl_host_deinit() - De-Initialize DSI host hardware.
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* @dsi_ctrl: DSI controller handle.
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*
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* De-initializes DSI controller hardware. It can be performed only during
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* DSI_CTRL_POWER_CORE_CLK_ON state after LINK clocks have been turned off.
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*
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* Return: error code.
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*/
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int dsi_ctrl_host_deinit(struct dsi_ctrl *dsi_ctrl);
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/**
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* dsi_ctrl_set_ulps() - set ULPS state for DSI lanes.
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* @dsi_ctrl: DSI controller handle.
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* @enable: enable/disable ULPS.
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*
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* ULPS can be enabled/disabled after DSI host engine is turned on.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable);
|
|
|
|
/**
|
|
* dsi_ctrl_setup() - Setup DSI host hardware while coming out of idle screen.
|
|
* @dsi_ctrl: DSI controller handle.
|
|
*
|
|
* Initializes DSI controller hardware with host configuration provided by
|
|
* dsi_ctrl_update_host_config(). Initialization can be performed only during
|
|
* DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been
|
|
* performed.
|
|
*
|
|
* Also used to program the video mode timing values.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_setup(struct dsi_ctrl *dsi_ctrl);
|
|
|
|
/**
|
|
* dsi_ctrl_set_roi() - Set DSI controller's region of interest
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @roi: Region of interest rectangle, must be less than mode bounds
|
|
* @changed: Output parameter, set to true of the controller's ROI was
|
|
* dirtied by setting the new ROI, and DCS cmd update needed
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_roi(struct dsi_ctrl *dsi_ctrl, struct dsi_rect *roi,
|
|
bool *changed);
|
|
|
|
/**
|
|
* dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @on: enable/disable test pattern.
|
|
*
|
|
* Test pattern can be enabled only after Video engine (for video mode panels)
|
|
* or command engine (for cmd mode panels) is enabled.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_tpg_state(struct dsi_ctrl *dsi_ctrl, bool on);
|
|
|
|
/**
|
|
* dsi_ctrl_cmd_transfer() - Transfer commands on DSI link
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @msg: Message to transfer on DSI link.
|
|
* @flags: Modifiers for message transfer.
|
|
*
|
|
* Command transfer can be done only when command engine is enabled. The
|
|
* transfer API will until either the command transfer finishes or the timeout
|
|
* value is reached. If the trigger is deferred, it will return without
|
|
* triggering the transfer. Command parameters are programmed to hardware.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl,
|
|
const struct mipi_dsi_msg *msg,
|
|
u32 flags);
|
|
|
|
/**
|
|
* dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command.
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @flags: Modifiers.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags);
|
|
|
|
/**
|
|
* dsi_ctrl_update_host_engine_state_for_cont_splash() - update engine
|
|
* states for cont splash usecase
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @state: DSI engine state
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_update_host_engine_state_for_cont_splash(struct dsi_ctrl *dsi_ctrl,
|
|
enum dsi_engine_state state);
|
|
|
|
/**
|
|
* dsi_ctrl_set_power_state() - set power state for dsi controller
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @state: Power state.
|
|
*
|
|
* Set power state for DSI controller. Power state can be changed only when
|
|
* Controller, Video and Command engines are turned off.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl,
|
|
enum dsi_power_state state);
|
|
|
|
/**
|
|
* dsi_ctrl_set_cmd_engine_state() - set command engine state
|
|
* @dsi_ctrl: DSI Controller handle.
|
|
* @state: Engine state.
|
|
*
|
|
* Command engine state can be modified only when DSI controller power state is
|
|
* set to DSI_CTRL_POWER_LINK_CLK_ON.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_cmd_engine_state(struct dsi_ctrl *dsi_ctrl,
|
|
enum dsi_engine_state state);
|
|
|
|
/**
|
|
* dsi_ctrl_validate_host_state() - validate DSI ctrl host state
|
|
* @dsi_ctrl: DSI Controller handle.
|
|
*
|
|
* Validate DSI cotroller host state
|
|
*
|
|
* Return: boolean indicating whether host is not initialized.
|
|
*/
|
|
bool dsi_ctrl_validate_host_state(struct dsi_ctrl *dsi_ctrl);
|
|
|
|
/**
|
|
* dsi_ctrl_set_vid_engine_state() - set video engine state
|
|
* @dsi_ctrl: DSI Controller handle.
|
|
* @state: Engine state.
|
|
*
|
|
* Video engine state can be modified only when DSI controller power state is
|
|
* set to DSI_CTRL_POWER_LINK_CLK_ON.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl,
|
|
enum dsi_engine_state state);
|
|
|
|
/**
|
|
* dsi_ctrl_set_host_engine_state() - set host engine state
|
|
* @dsi_ctrl: DSI Controller handle.
|
|
* @state: Engine state.
|
|
*
|
|
* Host engine state can be modified only when DSI controller power state is
|
|
* set to DSI_CTRL_POWER_LINK_CLK_ON and cmd, video engines are disabled.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_host_engine_state(struct dsi_ctrl *dsi_ctrl,
|
|
enum dsi_engine_state state);
|
|
|
|
/**
|
|
* dsi_ctrl_set_ulps() - set ULPS state for DSI lanes.
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @enable: enable/disable ULPS.
|
|
*
|
|
* ULPS can be enabled/disabled after DSI host engine is turned on.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable);
|
|
|
|
/**
|
|
* dsi_ctrl_clk_cb_register() - Register DSI controller clk control callback
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @clk__cb: Structure containing callback for clock control.
|
|
*
|
|
* Register call for DSI clock control
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_clk_cb_register(struct dsi_ctrl *dsi_ctrl,
|
|
struct clk_ctrl_cb *clk_cb);
|
|
|
|
/**
|
|
* dsi_ctrl_set_clamp_state() - set clamp state for DSI phy
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @enable: enable/disable clamping.
|
|
* @ulps_enabled: ulps state.
|
|
*
|
|
* Clamps can be enabled/disabled while DSI controller is still turned on.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_clamp_state(struct dsi_ctrl *dsi_Ctrl,
|
|
bool enable, bool ulps_enabled);
|
|
|
|
/**
|
|
* dsi_ctrl_set_clock_source() - set clock source fpr dsi link clocks
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @source_clks: Source clocks for DSI link clocks.
|
|
*
|
|
* Clock source should be changed while link clocks are disabled.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_set_clock_source(struct dsi_ctrl *dsi_ctrl,
|
|
struct dsi_clk_link_set *source_clks);
|
|
|
|
/**
|
|
* dsi_ctrl_enable_status_interrupt() - enable status interrupts
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @intr_idx: Index interrupt to disable.
|
|
* @event_info: Pointer to event callback definition
|
|
*/
|
|
void dsi_ctrl_enable_status_interrupt(struct dsi_ctrl *dsi_ctrl,
|
|
uint32_t intr_idx, struct dsi_event_cb_info *event_info);
|
|
|
|
/**
|
|
* dsi_ctrl_disable_status_interrupt() - disable status interrupts
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @intr_idx: Index interrupt to disable.
|
|
*/
|
|
void dsi_ctrl_disable_status_interrupt(
|
|
struct dsi_ctrl *dsi_ctrl, uint32_t intr_idx);
|
|
|
|
/**
|
|
* dsi_ctrl_setup_misr() - Setup frame MISR
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @enable: enable/disable MISR.
|
|
* @frame_count: Number of frames to accumulate MISR.
|
|
*
|
|
* Return: error code.
|
|
*/
|
|
int dsi_ctrl_setup_misr(struct dsi_ctrl *dsi_ctrl,
|
|
bool enable,
|
|
u32 frame_count);
|
|
|
|
/**
|
|
* dsi_ctrl_collect_misr() - Read frame MISR
|
|
* @dsi_ctrl: DSI controller handle.
|
|
*
|
|
* Return: MISR value.
|
|
*/
|
|
u32 dsi_ctrl_collect_misr(struct dsi_ctrl *dsi_ctrl);
|
|
|
|
/**
|
|
* dsi_ctrl_cache_misr - Cache frame MISR value
|
|
* @dsi_ctrl: DSI controller handle.
|
|
*/
|
|
void dsi_ctrl_cache_misr(struct dsi_ctrl *dsi_ctrl);
|
|
|
|
/**
|
|
* dsi_ctrl_drv_register() - register platform driver for dsi controller
|
|
*/
|
|
void dsi_ctrl_drv_register(void);
|
|
|
|
/**
|
|
* dsi_ctrl_drv_unregister() - unregister platform driver
|
|
*/
|
|
void dsi_ctrl_drv_unregister(void);
|
|
|
|
/**
|
|
* dsi_ctrl_reset() - Reset DSI PHY CLK/DATA lane
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @mask: Mask to indicate if CLK and/or DATA lane needs reset.
|
|
*/
|
|
int dsi_ctrl_reset(struct dsi_ctrl *dsi_ctrl, int mask);
|
|
|
|
/**
|
|
* dsi_ctrl_get_hw_version() - read dsi controller hw revision
|
|
* @dsi_ctrl: DSI controller handle.
|
|
*/
|
|
int dsi_ctrl_get_hw_version(struct dsi_ctrl *dsi_ctrl);
|
|
|
|
/**
|
|
* dsi_ctrl_vid_engine_en() - Control DSI video engine HW state
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @on: variable to control video engine ON/OFF.
|
|
*/
|
|
int dsi_ctrl_vid_engine_en(struct dsi_ctrl *dsi_ctrl, bool on);
|
|
|
|
/**
|
|
* dsi_ctrl_setup_avr() - Set/Clear the AVR_SUPPORT_ENABLE bit
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @enable: variable to control AVR support ON/OFF.
|
|
*/
|
|
int dsi_ctrl_setup_avr(struct dsi_ctrl *dsi_ctrl, bool enable);
|
|
|
|
/**
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* cmd_len: Length of command.
|
|
* flags: Config mode flags.
|
|
*/
|
|
void dsi_message_setup_tx_mode(struct dsi_ctrl *dsi_ctrl, u32 cmd_len,
|
|
u32 *flags);
|
|
|
|
/**
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* cmd_len: Length of command.
|
|
* flags: Config mode flags.
|
|
*/
|
|
int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl, u32 cmd_len,
|
|
u32 *flags);
|
|
|
|
/**
|
|
* dsi_ctrl_isr_configure() - API to register/deregister dsi isr
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @enable: variable to control register/deregister isr
|
|
*/
|
|
void dsi_ctrl_isr_configure(struct dsi_ctrl *dsi_ctrl, bool enable);
|
|
|
|
/**
|
|
* dsi_ctrl_mask_error_status_interrupts() - API to mask dsi ctrl error status
|
|
* interrupts
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @idx: id indicating which interrupts to enable/disable.
|
|
* @mask_enable: boolean to enable/disable masking.
|
|
*/
|
|
void dsi_ctrl_mask_error_status_interrupts(struct dsi_ctrl *dsi_ctrl, u32 idx,
|
|
bool mask_enable);
|
|
|
|
/**
|
|
* dsi_ctrl_irq_update() - Put a irq vote to process DSI error
|
|
* interrupts at any time.
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @enable: variable to control enable/disable irq line
|
|
*/
|
|
void dsi_ctrl_irq_update(struct dsi_ctrl *dsi_ctrl, bool enable);
|
|
|
|
/**
|
|
* dsi_ctrl_get_host_engine_init_state() - Return host init state
|
|
*/
|
|
int dsi_ctrl_get_host_engine_init_state(struct dsi_ctrl *dsi_ctrl,
|
|
bool *state);
|
|
|
|
/**
|
|
* dsi_ctrl_wait_for_cmd_mode_mdp_idle() - Wait for command mode engine not to
|
|
* be busy sending data from display engine.
|
|
* @dsi_ctrl: DSI controller handle.
|
|
*/
|
|
int dsi_ctrl_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl *dsi_ctrl);
|
|
/**
|
|
* dsi_ctrl_update_host_init_state() - Set the host initialization state
|
|
*/
|
|
int dsi_ctrl_update_host_init_state(struct dsi_ctrl *dsi_ctrl, bool en);
|
|
|
|
/**
|
|
* dsi_ctrl_pixel_format_to_bpp() - returns number of bits per pxl
|
|
*/
|
|
int dsi_ctrl_pixel_format_to_bpp(enum dsi_pixel_format dst_format);
|
|
|
|
/**
|
|
* dsi_ctrl_set_continuous_clk() - API to set/unset force clock lane HS request.
|
|
* @dsi_ctrl: DSI controller handle.
|
|
* @enable: variable to control continuous clock.
|
|
*/
|
|
void dsi_ctrl_set_continuous_clk(struct dsi_ctrl *dsi_ctrl, bool enable);
|
|
#endif /* _DSI_CTRL_H_ */
|