kona.c 220 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/clk.h>
  6. #include <linux/delay.h>
  7. #include <linux/gpio.h>
  8. #include <linux/of_gpio.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/input.h>
  14. #include <linux/of_device.h>
  15. #include <linux/soc/qcom/fsa4480-i2c.h>
  16. #include <sound/core.h>
  17. #include <sound/soc.h>
  18. #include <sound/soc-dapm.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/info.h>
  22. #include <soc/snd_event.h>
  23. #include <dsp/audio_notifier.h>
  24. #include <soc/swr-common.h>
  25. #include <dsp/q6afe-v2.h>
  26. #include <dsp/q6core.h>
  27. #include "device_event.h"
  28. #include "msm-pcm-routing-v2.h"
  29. #include "asoc/msm-cdc-pinctrl.h"
  30. #include "asoc/wcd-mbhc-v2.h"
  31. #include "codecs/wcd938x/wcd938x-mbhc.h"
  32. #include "codecs/wsa881x.h"
  33. #include "codecs/wcd938x/wcd938x.h"
  34. #include "codecs/bolero/bolero-cdc.h"
  35. #include <dt-bindings/sound/audio-codec-port-types.h>
  36. #include "codecs/bolero/wsa-macro.h"
  37. #include "kona-port-config.h"
  38. #define DRV_NAME "kona-asoc-snd"
  39. #define __CHIPSET__ "KONA "
  40. #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
  41. #define SAMPLING_RATE_8KHZ 8000
  42. #define SAMPLING_RATE_11P025KHZ 11025
  43. #define SAMPLING_RATE_16KHZ 16000
  44. #define SAMPLING_RATE_22P05KHZ 22050
  45. #define SAMPLING_RATE_32KHZ 32000
  46. #define SAMPLING_RATE_44P1KHZ 44100
  47. #define SAMPLING_RATE_48KHZ 48000
  48. #define SAMPLING_RATE_88P2KHZ 88200
  49. #define SAMPLING_RATE_96KHZ 96000
  50. #define SAMPLING_RATE_176P4KHZ 176400
  51. #define SAMPLING_RATE_192KHZ 192000
  52. #define SAMPLING_RATE_352P8KHZ 352800
  53. #define SAMPLING_RATE_384KHZ 384000
  54. #define WCD9XXX_MBHC_DEF_RLOADS 5
  55. #define WCD9XXX_MBHC_DEF_BUTTONS 8
  56. #define CODEC_EXT_CLK_RATE 9600000
  57. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  58. #define DEV_NAME_STR_LEN 32
  59. #define WCD_MBHC_HS_V_MAX 1600
  60. #define TDM_CHANNEL_MAX 8
  61. #define DEV_NAME_STR_LEN 32
  62. #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
  63. #define ADSP_STATE_READY_TIMEOUT_MS 3000
  64. #define WSA8810_NAME_1 "wsa881x.20170211"
  65. #define WSA8810_NAME_2 "wsa881x.20170212"
  66. #define WCN_CDC_SLIM_RX_CH_MAX 2
  67. #define WCN_CDC_SLIM_TX_CH_MAX 2
  68. #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3
  69. enum {
  70. TDM_0 = 0,
  71. TDM_1,
  72. TDM_2,
  73. TDM_3,
  74. TDM_4,
  75. TDM_5,
  76. TDM_6,
  77. TDM_7,
  78. TDM_PORT_MAX,
  79. };
  80. enum {
  81. TDM_PRI = 0,
  82. TDM_SEC,
  83. TDM_TERT,
  84. TDM_QUAT,
  85. TDM_QUIN,
  86. TDM_SEN,
  87. TDM_INTERFACE_MAX,
  88. };
  89. enum {
  90. PRIM_AUX_PCM = 0,
  91. SEC_AUX_PCM,
  92. TERT_AUX_PCM,
  93. QUAT_AUX_PCM,
  94. QUIN_AUX_PCM,
  95. SEN_AUX_PCM,
  96. AUX_PCM_MAX,
  97. };
  98. enum {
  99. PRIM_MI2S = 0,
  100. SEC_MI2S,
  101. TERT_MI2S,
  102. QUAT_MI2S,
  103. QUIN_MI2S,
  104. SEN_MI2S,
  105. MI2S_MAX,
  106. };
  107. enum {
  108. WSA_CDC_DMA_RX_0 = 0,
  109. WSA_CDC_DMA_RX_1,
  110. RX_CDC_DMA_RX_0,
  111. RX_CDC_DMA_RX_1,
  112. RX_CDC_DMA_RX_2,
  113. RX_CDC_DMA_RX_3,
  114. RX_CDC_DMA_RX_5,
  115. CDC_DMA_RX_MAX,
  116. };
  117. enum {
  118. WSA_CDC_DMA_TX_0 = 0,
  119. WSA_CDC_DMA_TX_1,
  120. WSA_CDC_DMA_TX_2,
  121. TX_CDC_DMA_TX_0,
  122. TX_CDC_DMA_TX_3,
  123. TX_CDC_DMA_TX_4,
  124. VA_CDC_DMA_TX_0,
  125. VA_CDC_DMA_TX_1,
  126. VA_CDC_DMA_TX_2,
  127. CDC_DMA_TX_MAX,
  128. };
  129. enum {
  130. SLIM_RX_7 = 0,
  131. SLIM_RX_MAX,
  132. };
  133. enum {
  134. SLIM_TX_7 = 0,
  135. SLIM_TX_8,
  136. SLIM_TX_MAX,
  137. };
  138. enum {
  139. AFE_LOOPBACK_TX_IDX = 0,
  140. AFE_LOOPBACK_TX_IDX_MAX,
  141. };
  142. struct msm_asoc_mach_data {
  143. struct snd_info_entry *codec_root;
  144. int usbc_en2_gpio; /* used by gpio driver API */
  145. struct device_node *dmic01_gpio_p; /* used by pinctrl API */
  146. struct device_node *dmic23_gpio_p; /* used by pinctrl API */
  147. struct device_node *dmic45_gpio_p; /* used by pinctrl API */
  148. struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
  149. atomic_t mi2s_gpio_ref_count[MI2S_MAX]; /* used by pinctrl API */
  150. struct device_node *us_euro_gpio_p; /* used by pinctrl API */
  151. struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
  152. struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
  153. struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
  154. bool is_afe_config_done;
  155. struct device_node *fsa_handle;
  156. };
  157. struct tdm_port {
  158. u32 mode;
  159. u32 channel;
  160. };
  161. enum {
  162. EXT_DISP_RX_IDX_DP = 0,
  163. EXT_DISP_RX_IDX_MAX,
  164. };
  165. struct msm_wsa881x_dev_info {
  166. struct device_node *of_node;
  167. u32 index;
  168. };
  169. struct aux_codec_dev_info {
  170. struct device_node *of_node;
  171. u32 index;
  172. };
  173. struct dev_config {
  174. u32 sample_rate;
  175. u32 bit_format;
  176. u32 channels;
  177. };
  178. /* Default configuration of slimbus channels */
  179. static struct dev_config slim_rx_cfg[] = {
  180. [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  181. };
  182. static struct dev_config slim_tx_cfg[] = {
  183. [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  184. [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  185. };
  186. /* Default configuration of external display BE */
  187. static struct dev_config ext_disp_rx_cfg[] = {
  188. [EXT_DISP_RX_IDX_DP] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  189. };
  190. static struct dev_config usb_rx_cfg = {
  191. .sample_rate = SAMPLING_RATE_48KHZ,
  192. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  193. .channels = 2,
  194. };
  195. static struct dev_config usb_tx_cfg = {
  196. .sample_rate = SAMPLING_RATE_48KHZ,
  197. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  198. .channels = 1,
  199. };
  200. static struct dev_config proxy_rx_cfg = {
  201. .sample_rate = SAMPLING_RATE_48KHZ,
  202. .bit_format = SNDRV_PCM_FORMAT_S16_LE,
  203. .channels = 2,
  204. };
  205. static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
  206. {
  207. AFE_API_VERSION_I2S_CONFIG,
  208. Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
  209. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  210. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  211. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  212. 0,
  213. },
  214. {
  215. AFE_API_VERSION_I2S_CONFIG,
  216. Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
  217. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  218. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  219. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  220. 0,
  221. },
  222. {
  223. AFE_API_VERSION_I2S_CONFIG,
  224. Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
  225. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  226. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  227. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  228. 0,
  229. },
  230. {
  231. AFE_API_VERSION_I2S_CONFIG,
  232. Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
  233. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  234. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  235. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  236. 0,
  237. },
  238. {
  239. AFE_API_VERSION_I2S_CONFIG,
  240. Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
  241. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  242. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  243. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  244. 0,
  245. },
  246. {
  247. AFE_API_VERSION_I2S_CONFIG,
  248. Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT,
  249. Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
  250. Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
  251. Q6AFE_LPASS_CLK_ROOT_DEFAULT,
  252. 0,
  253. },
  254. };
  255. struct mi2s_conf {
  256. struct mutex lock;
  257. u32 ref_cnt;
  258. u32 msm_is_mi2s_master;
  259. };
  260. static u32 mi2s_ebit_clk[MI2S_MAX] = {
  261. Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
  262. Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
  263. Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
  264. };
  265. static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
  266. /* Default configuration of TDM channels */
  267. static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  268. { /* PRI TDM */
  269. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  270. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  271. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  272. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  273. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  274. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  275. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  276. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  277. },
  278. { /* SEC TDM */
  279. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  280. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  281. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  282. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  283. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  284. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  285. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  286. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  287. },
  288. { /* TERT TDM */
  289. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  290. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  291. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  292. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  293. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  294. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  295. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  296. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  297. },
  298. { /* QUAT TDM */
  299. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  300. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  301. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  302. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  303. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  304. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  305. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  306. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  307. },
  308. { /* QUIN TDM */
  309. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  310. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  311. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  312. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  313. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  314. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  315. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  316. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  317. },
  318. { /* SEN TDM */
  319. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
  320. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
  321. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
  322. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
  323. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
  324. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
  325. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
  326. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
  327. },
  328. };
  329. static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
  330. { /* PRI TDM */
  331. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  332. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  333. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  334. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  335. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  336. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  337. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  338. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  339. },
  340. { /* SEC TDM */
  341. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  342. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  343. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  344. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  345. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  346. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  347. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  348. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  349. },
  350. { /* TERT TDM */
  351. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  352. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  353. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  354. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  355. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  356. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  357. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  358. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  359. },
  360. { /* QUAT TDM */
  361. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  362. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  363. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  364. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  365. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  366. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  367. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  368. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  369. },
  370. { /* QUIN TDM */
  371. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  372. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  373. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  374. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  375. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  376. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  377. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  378. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  379. },
  380. { /* SEN TDM */
  381. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
  382. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
  383. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
  384. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
  385. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
  386. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
  387. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
  388. {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
  389. },
  390. };
  391. /* Default configuration of AUX PCM channels */
  392. static struct dev_config aux_pcm_rx_cfg[] = {
  393. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  394. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  395. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  396. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  397. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  398. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  399. };
  400. static struct dev_config aux_pcm_tx_cfg[] = {
  401. [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  402. [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  403. [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  404. [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  405. [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  406. [SEN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  407. };
  408. /* Default configuration of MI2S channels */
  409. static struct dev_config mi2s_rx_cfg[] = {
  410. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  411. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  412. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  413. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  414. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  415. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  416. };
  417. static struct dev_config mi2s_tx_cfg[] = {
  418. [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  419. [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  420. [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  421. [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  422. [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  423. [SEN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  424. };
  425. /* Default configuration of Codec DMA Interface RX */
  426. static struct dev_config cdc_dma_rx_cfg[] = {
  427. [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  428. [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  429. [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  430. [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  431. [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  432. [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  433. [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  434. };
  435. /* Default configuration of Codec DMA Interface TX */
  436. static struct dev_config cdc_dma_tx_cfg[] = {
  437. [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  438. [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  439. [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  440. [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  441. [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  442. [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
  443. [VA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  444. [VA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  445. [VA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 8},
  446. };
  447. static struct dev_config afe_loopback_tx_cfg[] = {
  448. [AFE_LOOPBACK_TX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
  449. };
  450. static int msm_vi_feed_tx_ch = 2;
  451. static const char *const vi_feed_ch_text[] = {"One", "Two"};
  452. static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
  453. "S32_LE"};
  454. static char const *ch_text[] = {"Two", "Three", "Four", "Five",
  455. "Six", "Seven", "Eight"};
  456. static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  457. "KHZ_16", "KHZ_22P05",
  458. "KHZ_32", "KHZ_44P1", "KHZ_48",
  459. "KHZ_88P2", "KHZ_96", "KHZ_176P4",
  460. "KHZ_192", "KHZ_352P8", "KHZ_384"};
  461. static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
  462. "Five", "Six", "Seven",
  463. "Eight"};
  464. static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
  465. "KHZ_48", "KHZ_176P4",
  466. "KHZ_352P8"};
  467. static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
  468. static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
  469. "Five", "Six", "Seven", "Eight"};
  470. static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
  471. static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
  472. "KHZ_22P05", "KHZ_32", "KHZ_44P1",
  473. "KHZ_48", "KHZ_96", "KHZ_192"};
  474. static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
  475. "Five", "Six", "Seven",
  476. "Eight"};
  477. static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
  478. static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
  479. "Five", "Six", "Seven",
  480. "Eight"};
  481. static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
  482. "KHZ_16", "KHZ_22P05",
  483. "KHZ_32", "KHZ_44P1", "KHZ_48",
  484. "KHZ_88P2", "KHZ_96",
  485. "KHZ_176P4", "KHZ_192",
  486. "KHZ_352P8", "KHZ_384"};
  487. static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
  488. "S24_3LE"};
  489. static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
  490. "KHZ_192", "KHZ_32", "KHZ_44P1",
  491. "KHZ_88P2", "KHZ_176P4"};
  492. static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
  493. "KHZ_44P1", "KHZ_48",
  494. "KHZ_88P2", "KHZ_96"};
  495. static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
  496. "KHZ_44P1", "KHZ_48",
  497. "KHZ_88P2", "KHZ_96"};
  498. static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
  499. "KHZ_44P1", "KHZ_48",
  500. "KHZ_88P2", "KHZ_96"};
  501. static const char *const afe_loopback_tx_ch_text[] = {"One", "Two"};
  502. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
  503. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
  504. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
  505. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
  506. static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
  507. static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
  508. static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
  509. static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
  510. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
  511. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
  512. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
  513. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
  514. static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
  515. static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
  516. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  517. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  518. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  519. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  520. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  521. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_rx_sample_rate, auxpcm_rate_text);
  522. static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  523. static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  524. static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  525. static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  526. static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  527. static SOC_ENUM_SINGLE_EXT_DECL(sen_aux_pcm_tx_sample_rate, auxpcm_rate_text);
  528. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
  529. static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
  530. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
  531. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
  532. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
  533. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
  534. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
  535. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_sample_rate, mi2s_rate_text);
  536. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
  537. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
  538. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
  539. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
  540. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
  541. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_sample_rate, mi2s_rate_text);
  542. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
  543. static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
  544. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
  545. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
  546. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
  547. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
  548. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
  549. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_rx_chs, mi2s_ch_text);
  550. static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
  551. static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
  552. static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
  553. static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
  554. static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
  555. static SOC_ENUM_SINGLE_EXT_DECL(sen_mi2s_tx_chs, mi2s_ch_text);
  556. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  557. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  558. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
  559. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
  560. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
  561. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
  562. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
  563. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  564. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  565. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  566. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  567. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
  568. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
  569. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
  570. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
  571. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
  572. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
  573. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
  574. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
  575. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
  576. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
  577. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
  578. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
  579. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
  580. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
  581. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
  582. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
  583. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
  584. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_format, bit_format_text);
  585. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_format, bit_format_text);
  586. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_format, bit_format_text);
  587. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
  588. cdc_dma_sample_rate_text);
  589. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
  590. cdc_dma_sample_rate_text);
  591. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
  592. cdc_dma_sample_rate_text);
  593. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
  594. cdc_dma_sample_rate_text);
  595. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
  596. cdc_dma_sample_rate_text);
  597. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
  598. cdc_dma_sample_rate_text);
  599. static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
  600. cdc_dma_sample_rate_text);
  601. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
  602. cdc_dma_sample_rate_text);
  603. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
  604. cdc_dma_sample_rate_text);
  605. static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
  606. cdc_dma_sample_rate_text);
  607. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
  608. cdc_dma_sample_rate_text);
  609. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
  610. cdc_dma_sample_rate_text);
  611. static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
  612. cdc_dma_sample_rate_text);
  613. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_0_sample_rate,
  614. cdc_dma_sample_rate_text);
  615. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_1_sample_rate,
  616. cdc_dma_sample_rate_text);
  617. static SOC_ENUM_SINGLE_EXT_DECL(va_cdc_dma_tx_2_sample_rate,
  618. cdc_dma_sample_rate_text);
  619. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
  620. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
  621. static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
  622. ext_disp_sample_rate_text);
  623. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
  624. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
  625. static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
  626. static SOC_ENUM_SINGLE_EXT_DECL(afe_loopback_tx_chs, afe_loopback_tx_ch_text);
  627. static bool is_initial_boot;
  628. static bool codec_reg_done;
  629. static struct snd_soc_aux_dev *msm_aux_dev;
  630. static struct snd_soc_codec_conf *msm_codec_conf;
  631. static struct snd_soc_card snd_soc_card_kona_msm;
  632. static int dmic_0_1_gpio_cnt;
  633. static int dmic_2_3_gpio_cnt;
  634. static int dmic_4_5_gpio_cnt;
  635. static void *def_wcd_mbhc_cal(void);
  636. /*
  637. * Need to report LINEIN
  638. * if R/L channel impedance is larger than 5K ohm
  639. */
  640. static struct wcd_mbhc_config wcd_mbhc_cfg = {
  641. .read_fw_bin = false,
  642. .calibration = NULL,
  643. .detect_extn_cable = true,
  644. .mono_stero_detection = false,
  645. .swap_gnd_mic = NULL,
  646. .hs_ext_micbias = true,
  647. .key_code[0] = KEY_MEDIA,
  648. .key_code[1] = KEY_VOICECOMMAND,
  649. .key_code[2] = KEY_VOLUMEUP,
  650. .key_code[3] = KEY_VOLUMEDOWN,
  651. .key_code[4] = 0,
  652. .key_code[5] = 0,
  653. .key_code[6] = 0,
  654. .key_code[7] = 0,
  655. .linein_th = 5000,
  656. .moisture_en = true,
  657. .mbhc_micbias = MIC_BIAS_2,
  658. .anc_micbias = MIC_BIAS_2,
  659. .enable_anc_mic_detect = false,
  660. };
  661. static inline int param_is_mask(int p)
  662. {
  663. return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
  664. (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
  665. }
  666. static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
  667. int n)
  668. {
  669. return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
  670. }
  671. static void param_set_mask(struct snd_pcm_hw_params *p, int n,
  672. unsigned int bit)
  673. {
  674. if (bit >= SNDRV_MASK_MAX)
  675. return;
  676. if (param_is_mask(n)) {
  677. struct snd_mask *m = param_to_mask(p, n);
  678. m->bits[0] = 0;
  679. m->bits[1] = 0;
  680. m->bits[bit >> 5] |= (1 << (bit & 31));
  681. }
  682. }
  683. static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  684. struct snd_ctl_elem_value *ucontrol)
  685. {
  686. int sample_rate_val = 0;
  687. switch (usb_rx_cfg.sample_rate) {
  688. case SAMPLING_RATE_384KHZ:
  689. sample_rate_val = 12;
  690. break;
  691. case SAMPLING_RATE_352P8KHZ:
  692. sample_rate_val = 11;
  693. break;
  694. case SAMPLING_RATE_192KHZ:
  695. sample_rate_val = 10;
  696. break;
  697. case SAMPLING_RATE_176P4KHZ:
  698. sample_rate_val = 9;
  699. break;
  700. case SAMPLING_RATE_96KHZ:
  701. sample_rate_val = 8;
  702. break;
  703. case SAMPLING_RATE_88P2KHZ:
  704. sample_rate_val = 7;
  705. break;
  706. case SAMPLING_RATE_48KHZ:
  707. sample_rate_val = 6;
  708. break;
  709. case SAMPLING_RATE_44P1KHZ:
  710. sample_rate_val = 5;
  711. break;
  712. case SAMPLING_RATE_32KHZ:
  713. sample_rate_val = 4;
  714. break;
  715. case SAMPLING_RATE_22P05KHZ:
  716. sample_rate_val = 3;
  717. break;
  718. case SAMPLING_RATE_16KHZ:
  719. sample_rate_val = 2;
  720. break;
  721. case SAMPLING_RATE_11P025KHZ:
  722. sample_rate_val = 1;
  723. break;
  724. case SAMPLING_RATE_8KHZ:
  725. default:
  726. sample_rate_val = 0;
  727. break;
  728. }
  729. ucontrol->value.integer.value[0] = sample_rate_val;
  730. pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
  731. usb_rx_cfg.sample_rate);
  732. return 0;
  733. }
  734. static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  735. struct snd_ctl_elem_value *ucontrol)
  736. {
  737. switch (ucontrol->value.integer.value[0]) {
  738. case 12:
  739. usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  740. break;
  741. case 11:
  742. usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  743. break;
  744. case 10:
  745. usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  746. break;
  747. case 9:
  748. usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  749. break;
  750. case 8:
  751. usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  752. break;
  753. case 7:
  754. usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  755. break;
  756. case 6:
  757. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  758. break;
  759. case 5:
  760. usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  761. break;
  762. case 4:
  763. usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  764. break;
  765. case 3:
  766. usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  767. break;
  768. case 2:
  769. usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  770. break;
  771. case 1:
  772. usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  773. break;
  774. case 0:
  775. usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  776. break;
  777. default:
  778. usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  779. break;
  780. }
  781. pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
  782. __func__, ucontrol->value.integer.value[0],
  783. usb_rx_cfg.sample_rate);
  784. return 0;
  785. }
  786. static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  787. struct snd_ctl_elem_value *ucontrol)
  788. {
  789. int sample_rate_val = 0;
  790. switch (usb_tx_cfg.sample_rate) {
  791. case SAMPLING_RATE_384KHZ:
  792. sample_rate_val = 12;
  793. break;
  794. case SAMPLING_RATE_352P8KHZ:
  795. sample_rate_val = 11;
  796. break;
  797. case SAMPLING_RATE_192KHZ:
  798. sample_rate_val = 10;
  799. break;
  800. case SAMPLING_RATE_176P4KHZ:
  801. sample_rate_val = 9;
  802. break;
  803. case SAMPLING_RATE_96KHZ:
  804. sample_rate_val = 8;
  805. break;
  806. case SAMPLING_RATE_88P2KHZ:
  807. sample_rate_val = 7;
  808. break;
  809. case SAMPLING_RATE_48KHZ:
  810. sample_rate_val = 6;
  811. break;
  812. case SAMPLING_RATE_44P1KHZ:
  813. sample_rate_val = 5;
  814. break;
  815. case SAMPLING_RATE_32KHZ:
  816. sample_rate_val = 4;
  817. break;
  818. case SAMPLING_RATE_22P05KHZ:
  819. sample_rate_val = 3;
  820. break;
  821. case SAMPLING_RATE_16KHZ:
  822. sample_rate_val = 2;
  823. break;
  824. case SAMPLING_RATE_11P025KHZ:
  825. sample_rate_val = 1;
  826. break;
  827. case SAMPLING_RATE_8KHZ:
  828. sample_rate_val = 0;
  829. break;
  830. default:
  831. sample_rate_val = 6;
  832. break;
  833. }
  834. ucontrol->value.integer.value[0] = sample_rate_val;
  835. pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
  836. usb_tx_cfg.sample_rate);
  837. return 0;
  838. }
  839. static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  840. struct snd_ctl_elem_value *ucontrol)
  841. {
  842. switch (ucontrol->value.integer.value[0]) {
  843. case 12:
  844. usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
  845. break;
  846. case 11:
  847. usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
  848. break;
  849. case 10:
  850. usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
  851. break;
  852. case 9:
  853. usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
  854. break;
  855. case 8:
  856. usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
  857. break;
  858. case 7:
  859. usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
  860. break;
  861. case 6:
  862. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  863. break;
  864. case 5:
  865. usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
  866. break;
  867. case 4:
  868. usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
  869. break;
  870. case 3:
  871. usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
  872. break;
  873. case 2:
  874. usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
  875. break;
  876. case 1:
  877. usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
  878. break;
  879. case 0:
  880. usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
  881. break;
  882. default:
  883. usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
  884. break;
  885. }
  886. pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
  887. __func__, ucontrol->value.integer.value[0],
  888. usb_tx_cfg.sample_rate);
  889. return 0;
  890. }
  891. static int afe_loopback_tx_ch_get(struct snd_kcontrol *kcontrol,
  892. struct snd_ctl_elem_value *ucontrol)
  893. {
  894. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  895. afe_loopback_tx_cfg[0].channels);
  896. ucontrol->value.enumerated.item[0] =
  897. afe_loopback_tx_cfg[0].channels - 1;
  898. return 0;
  899. }
  900. static int afe_loopback_tx_ch_put(struct snd_kcontrol *kcontrol,
  901. struct snd_ctl_elem_value *ucontrol)
  902. {
  903. afe_loopback_tx_cfg[0].channels =
  904. ucontrol->value.enumerated.item[0] + 1;
  905. pr_debug("%s: afe_loopback_tx_ch = %d\n", __func__,
  906. afe_loopback_tx_cfg[0].channels);
  907. return 1;
  908. }
  909. static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
  910. struct snd_ctl_elem_value *ucontrol)
  911. {
  912. switch (usb_rx_cfg.bit_format) {
  913. case SNDRV_PCM_FORMAT_S32_LE:
  914. ucontrol->value.integer.value[0] = 3;
  915. break;
  916. case SNDRV_PCM_FORMAT_S24_3LE:
  917. ucontrol->value.integer.value[0] = 2;
  918. break;
  919. case SNDRV_PCM_FORMAT_S24_LE:
  920. ucontrol->value.integer.value[0] = 1;
  921. break;
  922. case SNDRV_PCM_FORMAT_S16_LE:
  923. default:
  924. ucontrol->value.integer.value[0] = 0;
  925. break;
  926. }
  927. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  928. __func__, usb_rx_cfg.bit_format,
  929. ucontrol->value.integer.value[0]);
  930. return 0;
  931. }
  932. static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
  933. struct snd_ctl_elem_value *ucontrol)
  934. {
  935. int rc = 0;
  936. switch (ucontrol->value.integer.value[0]) {
  937. case 3:
  938. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  939. break;
  940. case 2:
  941. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  942. break;
  943. case 1:
  944. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  945. break;
  946. case 0:
  947. default:
  948. usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  949. break;
  950. }
  951. pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
  952. __func__, usb_rx_cfg.bit_format,
  953. ucontrol->value.integer.value[0]);
  954. return rc;
  955. }
  956. static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
  957. struct snd_ctl_elem_value *ucontrol)
  958. {
  959. switch (usb_tx_cfg.bit_format) {
  960. case SNDRV_PCM_FORMAT_S32_LE:
  961. ucontrol->value.integer.value[0] = 3;
  962. break;
  963. case SNDRV_PCM_FORMAT_S24_3LE:
  964. ucontrol->value.integer.value[0] = 2;
  965. break;
  966. case SNDRV_PCM_FORMAT_S24_LE:
  967. ucontrol->value.integer.value[0] = 1;
  968. break;
  969. case SNDRV_PCM_FORMAT_S16_LE:
  970. default:
  971. ucontrol->value.integer.value[0] = 0;
  972. break;
  973. }
  974. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  975. __func__, usb_tx_cfg.bit_format,
  976. ucontrol->value.integer.value[0]);
  977. return 0;
  978. }
  979. static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
  980. struct snd_ctl_elem_value *ucontrol)
  981. {
  982. int rc = 0;
  983. switch (ucontrol->value.integer.value[0]) {
  984. case 3:
  985. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
  986. break;
  987. case 2:
  988. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  989. break;
  990. case 1:
  991. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
  992. break;
  993. case 0:
  994. default:
  995. usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
  996. break;
  997. }
  998. pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
  999. __func__, usb_tx_cfg.bit_format,
  1000. ucontrol->value.integer.value[0]);
  1001. return rc;
  1002. }
  1003. static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
  1004. struct snd_ctl_elem_value *ucontrol)
  1005. {
  1006. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
  1007. usb_rx_cfg.channels);
  1008. ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
  1009. return 0;
  1010. }
  1011. static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
  1012. struct snd_ctl_elem_value *ucontrol)
  1013. {
  1014. usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1015. pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
  1016. return 1;
  1017. }
  1018. static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
  1019. struct snd_ctl_elem_value *ucontrol)
  1020. {
  1021. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
  1022. usb_tx_cfg.channels);
  1023. ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
  1024. return 0;
  1025. }
  1026. static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
  1027. struct snd_ctl_elem_value *ucontrol)
  1028. {
  1029. usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
  1030. pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
  1031. return 1;
  1032. }
  1033. static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
  1034. struct snd_ctl_elem_value *ucontrol)
  1035. {
  1036. ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
  1037. pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
  1038. ucontrol->value.integer.value[0]);
  1039. return 0;
  1040. }
  1041. static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
  1042. struct snd_ctl_elem_value *ucontrol)
  1043. {
  1044. msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
  1045. pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
  1046. return 1;
  1047. }
  1048. static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
  1049. {
  1050. int idx = 0;
  1051. if (strnstr(kcontrol->id.name, "Display Port RX",
  1052. sizeof("Display Port RX"))) {
  1053. idx = EXT_DISP_RX_IDX_DP;
  1054. } else {
  1055. pr_err("%s: unsupported BE: %s\n",
  1056. __func__, kcontrol->id.name);
  1057. idx = -EINVAL;
  1058. }
  1059. return idx;
  1060. }
  1061. static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
  1062. struct snd_ctl_elem_value *ucontrol)
  1063. {
  1064. int idx = ext_disp_get_port_idx(kcontrol);
  1065. if (idx < 0)
  1066. return idx;
  1067. switch (ext_disp_rx_cfg[idx].bit_format) {
  1068. case SNDRV_PCM_FORMAT_S24_3LE:
  1069. ucontrol->value.integer.value[0] = 2;
  1070. break;
  1071. case SNDRV_PCM_FORMAT_S24_LE:
  1072. ucontrol->value.integer.value[0] = 1;
  1073. break;
  1074. case SNDRV_PCM_FORMAT_S16_LE:
  1075. default:
  1076. ucontrol->value.integer.value[0] = 0;
  1077. break;
  1078. }
  1079. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1080. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1081. ucontrol->value.integer.value[0]);
  1082. return 0;
  1083. }
  1084. static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
  1085. struct snd_ctl_elem_value *ucontrol)
  1086. {
  1087. int idx = ext_disp_get_port_idx(kcontrol);
  1088. if (idx < 0)
  1089. return idx;
  1090. switch (ucontrol->value.integer.value[0]) {
  1091. case 2:
  1092. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  1093. break;
  1094. case 1:
  1095. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  1096. break;
  1097. case 0:
  1098. default:
  1099. ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  1100. break;
  1101. }
  1102. pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
  1103. __func__, idx, ext_disp_rx_cfg[idx].bit_format,
  1104. ucontrol->value.integer.value[0]);
  1105. return 0;
  1106. }
  1107. static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
  1108. struct snd_ctl_elem_value *ucontrol)
  1109. {
  1110. int idx = ext_disp_get_port_idx(kcontrol);
  1111. if (idx < 0)
  1112. return idx;
  1113. ucontrol->value.integer.value[0] =
  1114. ext_disp_rx_cfg[idx].channels - 2;
  1115. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1116. idx, ext_disp_rx_cfg[idx].channels);
  1117. return 0;
  1118. }
  1119. static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
  1120. struct snd_ctl_elem_value *ucontrol)
  1121. {
  1122. int idx = ext_disp_get_port_idx(kcontrol);
  1123. if (idx < 0)
  1124. return idx;
  1125. ext_disp_rx_cfg[idx].channels =
  1126. ucontrol->value.integer.value[0] + 2;
  1127. pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
  1128. idx, ext_disp_rx_cfg[idx].channels);
  1129. return 1;
  1130. }
  1131. static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1132. struct snd_ctl_elem_value *ucontrol)
  1133. {
  1134. int sample_rate_val;
  1135. int idx = ext_disp_get_port_idx(kcontrol);
  1136. if (idx < 0)
  1137. return idx;
  1138. switch (ext_disp_rx_cfg[idx].sample_rate) {
  1139. case SAMPLING_RATE_176P4KHZ:
  1140. sample_rate_val = 6;
  1141. break;
  1142. case SAMPLING_RATE_88P2KHZ:
  1143. sample_rate_val = 5;
  1144. break;
  1145. case SAMPLING_RATE_44P1KHZ:
  1146. sample_rate_val = 4;
  1147. break;
  1148. case SAMPLING_RATE_32KHZ:
  1149. sample_rate_val = 3;
  1150. break;
  1151. case SAMPLING_RATE_192KHZ:
  1152. sample_rate_val = 2;
  1153. break;
  1154. case SAMPLING_RATE_96KHZ:
  1155. sample_rate_val = 1;
  1156. break;
  1157. case SAMPLING_RATE_48KHZ:
  1158. default:
  1159. sample_rate_val = 0;
  1160. break;
  1161. }
  1162. ucontrol->value.integer.value[0] = sample_rate_val;
  1163. pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
  1164. idx, ext_disp_rx_cfg[idx].sample_rate);
  1165. return 0;
  1166. }
  1167. static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1168. struct snd_ctl_elem_value *ucontrol)
  1169. {
  1170. int idx = ext_disp_get_port_idx(kcontrol);
  1171. if (idx < 0)
  1172. return idx;
  1173. switch (ucontrol->value.integer.value[0]) {
  1174. case 6:
  1175. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
  1176. break;
  1177. case 5:
  1178. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
  1179. break;
  1180. case 4:
  1181. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
  1182. break;
  1183. case 3:
  1184. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
  1185. break;
  1186. case 2:
  1187. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
  1188. break;
  1189. case 1:
  1190. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
  1191. break;
  1192. case 0:
  1193. default:
  1194. ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
  1195. break;
  1196. }
  1197. pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
  1198. __func__, ucontrol->value.integer.value[0], idx,
  1199. ext_disp_rx_cfg[idx].sample_rate);
  1200. return 0;
  1201. }
  1202. static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
  1203. struct snd_ctl_elem_value *ucontrol)
  1204. {
  1205. pr_debug("%s: proxy_rx channels = %d\n",
  1206. __func__, proxy_rx_cfg.channels);
  1207. ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
  1208. return 0;
  1209. }
  1210. static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
  1211. struct snd_ctl_elem_value *ucontrol)
  1212. {
  1213. proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
  1214. pr_debug("%s: proxy_rx channels = %d\n",
  1215. __func__, proxy_rx_cfg.channels);
  1216. return 1;
  1217. }
  1218. static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
  1219. struct tdm_port *port)
  1220. {
  1221. if (port) {
  1222. if (strnstr(kcontrol->id.name, "PRI",
  1223. sizeof(kcontrol->id.name))) {
  1224. port->mode = TDM_PRI;
  1225. } else if (strnstr(kcontrol->id.name, "SEC",
  1226. sizeof(kcontrol->id.name))) {
  1227. port->mode = TDM_SEC;
  1228. } else if (strnstr(kcontrol->id.name, "TERT",
  1229. sizeof(kcontrol->id.name))) {
  1230. port->mode = TDM_TERT;
  1231. } else if (strnstr(kcontrol->id.name, "QUAT",
  1232. sizeof(kcontrol->id.name))) {
  1233. port->mode = TDM_QUAT;
  1234. } else if (strnstr(kcontrol->id.name, "QUIN",
  1235. sizeof(kcontrol->id.name))) {
  1236. port->mode = TDM_QUIN;
  1237. } else if (strnstr(kcontrol->id.name, "SEN",
  1238. sizeof(kcontrol->id.name))) {
  1239. port->mode = TDM_SEN;
  1240. } else {
  1241. pr_err("%s: unsupported mode in: %s\n",
  1242. __func__, kcontrol->id.name);
  1243. return -EINVAL;
  1244. }
  1245. if (strnstr(kcontrol->id.name, "RX_0",
  1246. sizeof(kcontrol->id.name)) ||
  1247. strnstr(kcontrol->id.name, "TX_0",
  1248. sizeof(kcontrol->id.name))) {
  1249. port->channel = TDM_0;
  1250. } else if (strnstr(kcontrol->id.name, "RX_1",
  1251. sizeof(kcontrol->id.name)) ||
  1252. strnstr(kcontrol->id.name, "TX_1",
  1253. sizeof(kcontrol->id.name))) {
  1254. port->channel = TDM_1;
  1255. } else if (strnstr(kcontrol->id.name, "RX_2",
  1256. sizeof(kcontrol->id.name)) ||
  1257. strnstr(kcontrol->id.name, "TX_2",
  1258. sizeof(kcontrol->id.name))) {
  1259. port->channel = TDM_2;
  1260. } else if (strnstr(kcontrol->id.name, "RX_3",
  1261. sizeof(kcontrol->id.name)) ||
  1262. strnstr(kcontrol->id.name, "TX_3",
  1263. sizeof(kcontrol->id.name))) {
  1264. port->channel = TDM_3;
  1265. } else if (strnstr(kcontrol->id.name, "RX_4",
  1266. sizeof(kcontrol->id.name)) ||
  1267. strnstr(kcontrol->id.name, "TX_4",
  1268. sizeof(kcontrol->id.name))) {
  1269. port->channel = TDM_4;
  1270. } else if (strnstr(kcontrol->id.name, "RX_5",
  1271. sizeof(kcontrol->id.name)) ||
  1272. strnstr(kcontrol->id.name, "TX_5",
  1273. sizeof(kcontrol->id.name))) {
  1274. port->channel = TDM_5;
  1275. } else if (strnstr(kcontrol->id.name, "RX_6",
  1276. sizeof(kcontrol->id.name)) ||
  1277. strnstr(kcontrol->id.name, "TX_6",
  1278. sizeof(kcontrol->id.name))) {
  1279. port->channel = TDM_6;
  1280. } else if (strnstr(kcontrol->id.name, "RX_7",
  1281. sizeof(kcontrol->id.name)) ||
  1282. strnstr(kcontrol->id.name, "TX_7",
  1283. sizeof(kcontrol->id.name))) {
  1284. port->channel = TDM_7;
  1285. } else {
  1286. pr_err("%s: unsupported channel in: %s\n",
  1287. __func__, kcontrol->id.name);
  1288. return -EINVAL;
  1289. }
  1290. } else {
  1291. return -EINVAL;
  1292. }
  1293. return 0;
  1294. }
  1295. static int tdm_get_sample_rate(int value)
  1296. {
  1297. int sample_rate = 0;
  1298. switch (value) {
  1299. case 0:
  1300. sample_rate = SAMPLING_RATE_8KHZ;
  1301. break;
  1302. case 1:
  1303. sample_rate = SAMPLING_RATE_16KHZ;
  1304. break;
  1305. case 2:
  1306. sample_rate = SAMPLING_RATE_32KHZ;
  1307. break;
  1308. case 3:
  1309. sample_rate = SAMPLING_RATE_48KHZ;
  1310. break;
  1311. case 4:
  1312. sample_rate = SAMPLING_RATE_176P4KHZ;
  1313. break;
  1314. case 5:
  1315. sample_rate = SAMPLING_RATE_352P8KHZ;
  1316. break;
  1317. default:
  1318. sample_rate = SAMPLING_RATE_48KHZ;
  1319. break;
  1320. }
  1321. return sample_rate;
  1322. }
  1323. static int tdm_get_sample_rate_val(int sample_rate)
  1324. {
  1325. int sample_rate_val = 0;
  1326. switch (sample_rate) {
  1327. case SAMPLING_RATE_8KHZ:
  1328. sample_rate_val = 0;
  1329. break;
  1330. case SAMPLING_RATE_16KHZ:
  1331. sample_rate_val = 1;
  1332. break;
  1333. case SAMPLING_RATE_32KHZ:
  1334. sample_rate_val = 2;
  1335. break;
  1336. case SAMPLING_RATE_48KHZ:
  1337. sample_rate_val = 3;
  1338. break;
  1339. case SAMPLING_RATE_176P4KHZ:
  1340. sample_rate_val = 4;
  1341. break;
  1342. case SAMPLING_RATE_352P8KHZ:
  1343. sample_rate_val = 5;
  1344. break;
  1345. default:
  1346. sample_rate_val = 3;
  1347. break;
  1348. }
  1349. return sample_rate_val;
  1350. }
  1351. static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1352. struct snd_ctl_elem_value *ucontrol)
  1353. {
  1354. struct tdm_port port;
  1355. int ret = tdm_get_port_idx(kcontrol, &port);
  1356. if (ret) {
  1357. pr_err("%s: unsupported control: %s\n",
  1358. __func__, kcontrol->id.name);
  1359. } else {
  1360. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1361. tdm_rx_cfg[port.mode][port.channel].sample_rate);
  1362. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1363. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1364. ucontrol->value.enumerated.item[0]);
  1365. }
  1366. return ret;
  1367. }
  1368. static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1369. struct snd_ctl_elem_value *ucontrol)
  1370. {
  1371. struct tdm_port port;
  1372. int ret = tdm_get_port_idx(kcontrol, &port);
  1373. if (ret) {
  1374. pr_err("%s: unsupported control: %s\n",
  1375. __func__, kcontrol->id.name);
  1376. } else {
  1377. tdm_rx_cfg[port.mode][port.channel].sample_rate =
  1378. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1379. pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
  1380. tdm_rx_cfg[port.mode][port.channel].sample_rate,
  1381. ucontrol->value.enumerated.item[0]);
  1382. }
  1383. return ret;
  1384. }
  1385. static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1386. struct snd_ctl_elem_value *ucontrol)
  1387. {
  1388. struct tdm_port port;
  1389. int ret = tdm_get_port_idx(kcontrol, &port);
  1390. if (ret) {
  1391. pr_err("%s: unsupported control: %s\n",
  1392. __func__, kcontrol->id.name);
  1393. } else {
  1394. ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
  1395. tdm_tx_cfg[port.mode][port.channel].sample_rate);
  1396. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1397. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1398. ucontrol->value.enumerated.item[0]);
  1399. }
  1400. return ret;
  1401. }
  1402. static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1403. struct snd_ctl_elem_value *ucontrol)
  1404. {
  1405. struct tdm_port port;
  1406. int ret = tdm_get_port_idx(kcontrol, &port);
  1407. if (ret) {
  1408. pr_err("%s: unsupported control: %s\n",
  1409. __func__, kcontrol->id.name);
  1410. } else {
  1411. tdm_tx_cfg[port.mode][port.channel].sample_rate =
  1412. tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1413. pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
  1414. tdm_tx_cfg[port.mode][port.channel].sample_rate,
  1415. ucontrol->value.enumerated.item[0]);
  1416. }
  1417. return ret;
  1418. }
  1419. static int tdm_get_format(int value)
  1420. {
  1421. int format = 0;
  1422. switch (value) {
  1423. case 0:
  1424. format = SNDRV_PCM_FORMAT_S16_LE;
  1425. break;
  1426. case 1:
  1427. format = SNDRV_PCM_FORMAT_S24_LE;
  1428. break;
  1429. case 2:
  1430. format = SNDRV_PCM_FORMAT_S32_LE;
  1431. break;
  1432. default:
  1433. format = SNDRV_PCM_FORMAT_S16_LE;
  1434. break;
  1435. }
  1436. return format;
  1437. }
  1438. static int tdm_get_format_val(int format)
  1439. {
  1440. int value = 0;
  1441. switch (format) {
  1442. case SNDRV_PCM_FORMAT_S16_LE:
  1443. value = 0;
  1444. break;
  1445. case SNDRV_PCM_FORMAT_S24_LE:
  1446. value = 1;
  1447. break;
  1448. case SNDRV_PCM_FORMAT_S32_LE:
  1449. value = 2;
  1450. break;
  1451. default:
  1452. value = 0;
  1453. break;
  1454. }
  1455. return value;
  1456. }
  1457. static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
  1458. struct snd_ctl_elem_value *ucontrol)
  1459. {
  1460. struct tdm_port port;
  1461. int ret = tdm_get_port_idx(kcontrol, &port);
  1462. if (ret) {
  1463. pr_err("%s: unsupported control: %s\n",
  1464. __func__, kcontrol->id.name);
  1465. } else {
  1466. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1467. tdm_rx_cfg[port.mode][port.channel].bit_format);
  1468. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1469. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1470. ucontrol->value.enumerated.item[0]);
  1471. }
  1472. return ret;
  1473. }
  1474. static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
  1475. struct snd_ctl_elem_value *ucontrol)
  1476. {
  1477. struct tdm_port port;
  1478. int ret = tdm_get_port_idx(kcontrol, &port);
  1479. if (ret) {
  1480. pr_err("%s: unsupported control: %s\n",
  1481. __func__, kcontrol->id.name);
  1482. } else {
  1483. tdm_rx_cfg[port.mode][port.channel].bit_format =
  1484. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1485. pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
  1486. tdm_rx_cfg[port.mode][port.channel].bit_format,
  1487. ucontrol->value.enumerated.item[0]);
  1488. }
  1489. return ret;
  1490. }
  1491. static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
  1492. struct snd_ctl_elem_value *ucontrol)
  1493. {
  1494. struct tdm_port port;
  1495. int ret = tdm_get_port_idx(kcontrol, &port);
  1496. if (ret) {
  1497. pr_err("%s: unsupported control: %s\n",
  1498. __func__, kcontrol->id.name);
  1499. } else {
  1500. ucontrol->value.enumerated.item[0] = tdm_get_format_val(
  1501. tdm_tx_cfg[port.mode][port.channel].bit_format);
  1502. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1503. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1504. ucontrol->value.enumerated.item[0]);
  1505. }
  1506. return ret;
  1507. }
  1508. static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
  1509. struct snd_ctl_elem_value *ucontrol)
  1510. {
  1511. struct tdm_port port;
  1512. int ret = tdm_get_port_idx(kcontrol, &port);
  1513. if (ret) {
  1514. pr_err("%s: unsupported control: %s\n",
  1515. __func__, kcontrol->id.name);
  1516. } else {
  1517. tdm_tx_cfg[port.mode][port.channel].bit_format =
  1518. tdm_get_format(ucontrol->value.enumerated.item[0]);
  1519. pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
  1520. tdm_tx_cfg[port.mode][port.channel].bit_format,
  1521. ucontrol->value.enumerated.item[0]);
  1522. }
  1523. return ret;
  1524. }
  1525. static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
  1526. struct snd_ctl_elem_value *ucontrol)
  1527. {
  1528. struct tdm_port port;
  1529. int ret = tdm_get_port_idx(kcontrol, &port);
  1530. if (ret) {
  1531. pr_err("%s: unsupported control: %s\n",
  1532. __func__, kcontrol->id.name);
  1533. } else {
  1534. ucontrol->value.enumerated.item[0] =
  1535. tdm_rx_cfg[port.mode][port.channel].channels - 1;
  1536. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1537. tdm_rx_cfg[port.mode][port.channel].channels - 1,
  1538. ucontrol->value.enumerated.item[0]);
  1539. }
  1540. return ret;
  1541. }
  1542. static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
  1543. struct snd_ctl_elem_value *ucontrol)
  1544. {
  1545. struct tdm_port port;
  1546. int ret = tdm_get_port_idx(kcontrol, &port);
  1547. if (ret) {
  1548. pr_err("%s: unsupported control: %s\n",
  1549. __func__, kcontrol->id.name);
  1550. } else {
  1551. tdm_rx_cfg[port.mode][port.channel].channels =
  1552. ucontrol->value.enumerated.item[0] + 1;
  1553. pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
  1554. tdm_rx_cfg[port.mode][port.channel].channels,
  1555. ucontrol->value.enumerated.item[0] + 1);
  1556. }
  1557. return ret;
  1558. }
  1559. static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
  1560. struct snd_ctl_elem_value *ucontrol)
  1561. {
  1562. struct tdm_port port;
  1563. int ret = tdm_get_port_idx(kcontrol, &port);
  1564. if (ret) {
  1565. pr_err("%s: unsupported control: %s\n",
  1566. __func__, kcontrol->id.name);
  1567. } else {
  1568. ucontrol->value.enumerated.item[0] =
  1569. tdm_tx_cfg[port.mode][port.channel].channels - 1;
  1570. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1571. tdm_tx_cfg[port.mode][port.channel].channels - 1,
  1572. ucontrol->value.enumerated.item[0]);
  1573. }
  1574. return ret;
  1575. }
  1576. static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
  1577. struct snd_ctl_elem_value *ucontrol)
  1578. {
  1579. struct tdm_port port;
  1580. int ret = tdm_get_port_idx(kcontrol, &port);
  1581. if (ret) {
  1582. pr_err("%s: unsupported control: %s\n",
  1583. __func__, kcontrol->id.name);
  1584. } else {
  1585. tdm_tx_cfg[port.mode][port.channel].channels =
  1586. ucontrol->value.enumerated.item[0] + 1;
  1587. pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
  1588. tdm_tx_cfg[port.mode][port.channel].channels,
  1589. ucontrol->value.enumerated.item[0] + 1);
  1590. }
  1591. return ret;
  1592. }
  1593. static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
  1594. {
  1595. int idx = 0;
  1596. if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
  1597. sizeof("PRIM_AUX_PCM"))) {
  1598. idx = PRIM_AUX_PCM;
  1599. } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
  1600. sizeof("SEC_AUX_PCM"))) {
  1601. idx = SEC_AUX_PCM;
  1602. } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
  1603. sizeof("TERT_AUX_PCM"))) {
  1604. idx = TERT_AUX_PCM;
  1605. } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
  1606. sizeof("QUAT_AUX_PCM"))) {
  1607. idx = QUAT_AUX_PCM;
  1608. } else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
  1609. sizeof("QUIN_AUX_PCM"))) {
  1610. idx = QUIN_AUX_PCM;
  1611. } else if (strnstr(kcontrol->id.name, "SEN_AUX_PCM",
  1612. sizeof("SEN_AUX_PCM"))) {
  1613. idx = SEN_AUX_PCM;
  1614. } else {
  1615. pr_err("%s: unsupported port: %s\n",
  1616. __func__, kcontrol->id.name);
  1617. idx = -EINVAL;
  1618. }
  1619. return idx;
  1620. }
  1621. static int aux_pcm_get_sample_rate(int value)
  1622. {
  1623. int sample_rate = 0;
  1624. switch (value) {
  1625. case 1:
  1626. sample_rate = SAMPLING_RATE_16KHZ;
  1627. break;
  1628. case 0:
  1629. default:
  1630. sample_rate = SAMPLING_RATE_8KHZ;
  1631. break;
  1632. }
  1633. return sample_rate;
  1634. }
  1635. static int aux_pcm_get_sample_rate_val(int sample_rate)
  1636. {
  1637. int sample_rate_val = 0;
  1638. switch (sample_rate) {
  1639. case SAMPLING_RATE_16KHZ:
  1640. sample_rate_val = 1;
  1641. break;
  1642. case SAMPLING_RATE_8KHZ:
  1643. default:
  1644. sample_rate_val = 0;
  1645. break;
  1646. }
  1647. return sample_rate_val;
  1648. }
  1649. static int mi2s_auxpcm_get_format(int value)
  1650. {
  1651. int format = 0;
  1652. switch (value) {
  1653. case 0:
  1654. format = SNDRV_PCM_FORMAT_S16_LE;
  1655. break;
  1656. case 1:
  1657. format = SNDRV_PCM_FORMAT_S24_LE;
  1658. break;
  1659. case 2:
  1660. format = SNDRV_PCM_FORMAT_S24_3LE;
  1661. break;
  1662. case 3:
  1663. format = SNDRV_PCM_FORMAT_S32_LE;
  1664. break;
  1665. default:
  1666. format = SNDRV_PCM_FORMAT_S16_LE;
  1667. break;
  1668. }
  1669. return format;
  1670. }
  1671. static int mi2s_auxpcm_get_format_value(int format)
  1672. {
  1673. int value = 0;
  1674. switch (format) {
  1675. case SNDRV_PCM_FORMAT_S16_LE:
  1676. value = 0;
  1677. break;
  1678. case SNDRV_PCM_FORMAT_S24_LE:
  1679. value = 1;
  1680. break;
  1681. case SNDRV_PCM_FORMAT_S24_3LE:
  1682. value = 2;
  1683. break;
  1684. case SNDRV_PCM_FORMAT_S32_LE:
  1685. value = 3;
  1686. break;
  1687. default:
  1688. value = 0;
  1689. break;
  1690. }
  1691. return value;
  1692. }
  1693. static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1694. struct snd_ctl_elem_value *ucontrol)
  1695. {
  1696. int idx = aux_pcm_get_port_idx(kcontrol);
  1697. if (idx < 0)
  1698. return idx;
  1699. ucontrol->value.enumerated.item[0] =
  1700. aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
  1701. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1702. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1703. ucontrol->value.enumerated.item[0]);
  1704. return 0;
  1705. }
  1706. static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1707. struct snd_ctl_elem_value *ucontrol)
  1708. {
  1709. int idx = aux_pcm_get_port_idx(kcontrol);
  1710. if (idx < 0)
  1711. return idx;
  1712. aux_pcm_rx_cfg[idx].sample_rate =
  1713. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1714. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1715. idx, aux_pcm_rx_cfg[idx].sample_rate,
  1716. ucontrol->value.enumerated.item[0]);
  1717. return 0;
  1718. }
  1719. static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1720. struct snd_ctl_elem_value *ucontrol)
  1721. {
  1722. int idx = aux_pcm_get_port_idx(kcontrol);
  1723. if (idx < 0)
  1724. return idx;
  1725. ucontrol->value.enumerated.item[0] =
  1726. aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
  1727. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1728. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1729. ucontrol->value.enumerated.item[0]);
  1730. return 0;
  1731. }
  1732. static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1733. struct snd_ctl_elem_value *ucontrol)
  1734. {
  1735. int idx = aux_pcm_get_port_idx(kcontrol);
  1736. if (idx < 0)
  1737. return idx;
  1738. aux_pcm_tx_cfg[idx].sample_rate =
  1739. aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1740. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1741. idx, aux_pcm_tx_cfg[idx].sample_rate,
  1742. ucontrol->value.enumerated.item[0]);
  1743. return 0;
  1744. }
  1745. static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
  1746. struct snd_ctl_elem_value *ucontrol)
  1747. {
  1748. int idx = aux_pcm_get_port_idx(kcontrol);
  1749. if (idx < 0)
  1750. return idx;
  1751. ucontrol->value.enumerated.item[0] =
  1752. mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
  1753. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1754. idx, aux_pcm_rx_cfg[idx].bit_format,
  1755. ucontrol->value.enumerated.item[0]);
  1756. return 0;
  1757. }
  1758. static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
  1759. struct snd_ctl_elem_value *ucontrol)
  1760. {
  1761. int idx = aux_pcm_get_port_idx(kcontrol);
  1762. if (idx < 0)
  1763. return idx;
  1764. aux_pcm_rx_cfg[idx].bit_format =
  1765. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1766. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1767. idx, aux_pcm_rx_cfg[idx].bit_format,
  1768. ucontrol->value.enumerated.item[0]);
  1769. return 0;
  1770. }
  1771. static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
  1772. struct snd_ctl_elem_value *ucontrol)
  1773. {
  1774. int idx = aux_pcm_get_port_idx(kcontrol);
  1775. if (idx < 0)
  1776. return idx;
  1777. ucontrol->value.enumerated.item[0] =
  1778. mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
  1779. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1780. idx, aux_pcm_tx_cfg[idx].bit_format,
  1781. ucontrol->value.enumerated.item[0]);
  1782. return 0;
  1783. }
  1784. static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
  1785. struct snd_ctl_elem_value *ucontrol)
  1786. {
  1787. int idx = aux_pcm_get_port_idx(kcontrol);
  1788. if (idx < 0)
  1789. return idx;
  1790. aux_pcm_tx_cfg[idx].bit_format =
  1791. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1792. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  1793. idx, aux_pcm_tx_cfg[idx].bit_format,
  1794. ucontrol->value.enumerated.item[0]);
  1795. return 0;
  1796. }
  1797. static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
  1798. {
  1799. int idx = 0;
  1800. if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
  1801. sizeof("PRIM_MI2S_RX"))) {
  1802. idx = PRIM_MI2S;
  1803. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
  1804. sizeof("SEC_MI2S_RX"))) {
  1805. idx = SEC_MI2S;
  1806. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
  1807. sizeof("TERT_MI2S_RX"))) {
  1808. idx = TERT_MI2S;
  1809. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
  1810. sizeof("QUAT_MI2S_RX"))) {
  1811. idx = QUAT_MI2S;
  1812. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
  1813. sizeof("QUIN_MI2S_RX"))) {
  1814. idx = QUIN_MI2S;
  1815. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_RX",
  1816. sizeof("SEN_MI2S_RX"))) {
  1817. idx = SEN_MI2S;
  1818. } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
  1819. sizeof("PRIM_MI2S_TX"))) {
  1820. idx = PRIM_MI2S;
  1821. } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
  1822. sizeof("SEC_MI2S_TX"))) {
  1823. idx = SEC_MI2S;
  1824. } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
  1825. sizeof("TERT_MI2S_TX"))) {
  1826. idx = TERT_MI2S;
  1827. } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
  1828. sizeof("QUAT_MI2S_TX"))) {
  1829. idx = QUAT_MI2S;
  1830. } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
  1831. sizeof("QUIN_MI2S_TX"))) {
  1832. idx = QUIN_MI2S;
  1833. } else if (strnstr(kcontrol->id.name, "SEN_MI2S_TX",
  1834. sizeof("SEN_MI2S_TX"))) {
  1835. idx = SEN_MI2S;
  1836. } else {
  1837. pr_err("%s: unsupported channel: %s\n",
  1838. __func__, kcontrol->id.name);
  1839. idx = -EINVAL;
  1840. }
  1841. return idx;
  1842. }
  1843. static int mi2s_get_sample_rate(int value)
  1844. {
  1845. int sample_rate = 0;
  1846. switch (value) {
  1847. case 0:
  1848. sample_rate = SAMPLING_RATE_8KHZ;
  1849. break;
  1850. case 1:
  1851. sample_rate = SAMPLING_RATE_11P025KHZ;
  1852. break;
  1853. case 2:
  1854. sample_rate = SAMPLING_RATE_16KHZ;
  1855. break;
  1856. case 3:
  1857. sample_rate = SAMPLING_RATE_22P05KHZ;
  1858. break;
  1859. case 4:
  1860. sample_rate = SAMPLING_RATE_32KHZ;
  1861. break;
  1862. case 5:
  1863. sample_rate = SAMPLING_RATE_44P1KHZ;
  1864. break;
  1865. case 6:
  1866. sample_rate = SAMPLING_RATE_48KHZ;
  1867. break;
  1868. case 7:
  1869. sample_rate = SAMPLING_RATE_96KHZ;
  1870. break;
  1871. case 8:
  1872. sample_rate = SAMPLING_RATE_192KHZ;
  1873. break;
  1874. default:
  1875. sample_rate = SAMPLING_RATE_48KHZ;
  1876. break;
  1877. }
  1878. return sample_rate;
  1879. }
  1880. static int mi2s_get_sample_rate_val(int sample_rate)
  1881. {
  1882. int sample_rate_val = 0;
  1883. switch (sample_rate) {
  1884. case SAMPLING_RATE_8KHZ:
  1885. sample_rate_val = 0;
  1886. break;
  1887. case SAMPLING_RATE_11P025KHZ:
  1888. sample_rate_val = 1;
  1889. break;
  1890. case SAMPLING_RATE_16KHZ:
  1891. sample_rate_val = 2;
  1892. break;
  1893. case SAMPLING_RATE_22P05KHZ:
  1894. sample_rate_val = 3;
  1895. break;
  1896. case SAMPLING_RATE_32KHZ:
  1897. sample_rate_val = 4;
  1898. break;
  1899. case SAMPLING_RATE_44P1KHZ:
  1900. sample_rate_val = 5;
  1901. break;
  1902. case SAMPLING_RATE_48KHZ:
  1903. sample_rate_val = 6;
  1904. break;
  1905. case SAMPLING_RATE_96KHZ:
  1906. sample_rate_val = 7;
  1907. break;
  1908. case SAMPLING_RATE_192KHZ:
  1909. sample_rate_val = 8;
  1910. break;
  1911. default:
  1912. sample_rate_val = 6;
  1913. break;
  1914. }
  1915. return sample_rate_val;
  1916. }
  1917. static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1918. struct snd_ctl_elem_value *ucontrol)
  1919. {
  1920. int idx = mi2s_get_port_idx(kcontrol);
  1921. if (idx < 0)
  1922. return idx;
  1923. ucontrol->value.enumerated.item[0] =
  1924. mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
  1925. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1926. idx, mi2s_rx_cfg[idx].sample_rate,
  1927. ucontrol->value.enumerated.item[0]);
  1928. return 0;
  1929. }
  1930. static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1931. struct snd_ctl_elem_value *ucontrol)
  1932. {
  1933. int idx = mi2s_get_port_idx(kcontrol);
  1934. if (idx < 0)
  1935. return idx;
  1936. mi2s_rx_cfg[idx].sample_rate =
  1937. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1938. pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
  1939. idx, mi2s_rx_cfg[idx].sample_rate,
  1940. ucontrol->value.enumerated.item[0]);
  1941. return 0;
  1942. }
  1943. static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  1944. struct snd_ctl_elem_value *ucontrol)
  1945. {
  1946. int idx = mi2s_get_port_idx(kcontrol);
  1947. if (idx < 0)
  1948. return idx;
  1949. ucontrol->value.enumerated.item[0] =
  1950. mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
  1951. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1952. idx, mi2s_tx_cfg[idx].sample_rate,
  1953. ucontrol->value.enumerated.item[0]);
  1954. return 0;
  1955. }
  1956. static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  1957. struct snd_ctl_elem_value *ucontrol)
  1958. {
  1959. int idx = mi2s_get_port_idx(kcontrol);
  1960. if (idx < 0)
  1961. return idx;
  1962. mi2s_tx_cfg[idx].sample_rate =
  1963. mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
  1964. pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
  1965. idx, mi2s_tx_cfg[idx].sample_rate,
  1966. ucontrol->value.enumerated.item[0]);
  1967. return 0;
  1968. }
  1969. static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
  1970. struct snd_ctl_elem_value *ucontrol)
  1971. {
  1972. int idx = mi2s_get_port_idx(kcontrol);
  1973. if (idx < 0)
  1974. return idx;
  1975. ucontrol->value.enumerated.item[0] =
  1976. mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
  1977. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1978. idx, mi2s_rx_cfg[idx].bit_format,
  1979. ucontrol->value.enumerated.item[0]);
  1980. return 0;
  1981. }
  1982. static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
  1983. struct snd_ctl_elem_value *ucontrol)
  1984. {
  1985. int idx = mi2s_get_port_idx(kcontrol);
  1986. if (idx < 0)
  1987. return idx;
  1988. mi2s_rx_cfg[idx].bit_format =
  1989. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  1990. pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
  1991. idx, mi2s_rx_cfg[idx].bit_format,
  1992. ucontrol->value.enumerated.item[0]);
  1993. return 0;
  1994. }
  1995. static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
  1996. struct snd_ctl_elem_value *ucontrol)
  1997. {
  1998. int idx = mi2s_get_port_idx(kcontrol);
  1999. if (idx < 0)
  2000. return idx;
  2001. ucontrol->value.enumerated.item[0] =
  2002. mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
  2003. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2004. idx, mi2s_tx_cfg[idx].bit_format,
  2005. ucontrol->value.enumerated.item[0]);
  2006. return 0;
  2007. }
  2008. static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
  2009. struct snd_ctl_elem_value *ucontrol)
  2010. {
  2011. int idx = mi2s_get_port_idx(kcontrol);
  2012. if (idx < 0)
  2013. return idx;
  2014. mi2s_tx_cfg[idx].bit_format =
  2015. mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
  2016. pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
  2017. idx, mi2s_tx_cfg[idx].bit_format,
  2018. ucontrol->value.enumerated.item[0]);
  2019. return 0;
  2020. }
  2021. static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
  2022. struct snd_ctl_elem_value *ucontrol)
  2023. {
  2024. int idx = mi2s_get_port_idx(kcontrol);
  2025. if (idx < 0)
  2026. return idx;
  2027. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2028. idx, mi2s_rx_cfg[idx].channels);
  2029. ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
  2030. return 0;
  2031. }
  2032. static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
  2033. struct snd_ctl_elem_value *ucontrol)
  2034. {
  2035. int idx = mi2s_get_port_idx(kcontrol);
  2036. if (idx < 0)
  2037. return idx;
  2038. mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2039. pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
  2040. idx, mi2s_rx_cfg[idx].channels);
  2041. return 1;
  2042. }
  2043. static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
  2044. struct snd_ctl_elem_value *ucontrol)
  2045. {
  2046. int idx = mi2s_get_port_idx(kcontrol);
  2047. if (idx < 0)
  2048. return idx;
  2049. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2050. idx, mi2s_tx_cfg[idx].channels);
  2051. ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
  2052. return 0;
  2053. }
  2054. static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
  2055. struct snd_ctl_elem_value *ucontrol)
  2056. {
  2057. int idx = mi2s_get_port_idx(kcontrol);
  2058. if (idx < 0)
  2059. return idx;
  2060. mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
  2061. pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
  2062. idx, mi2s_tx_cfg[idx].channels);
  2063. return 1;
  2064. }
  2065. static int msm_get_port_id(int be_id)
  2066. {
  2067. int afe_port_id = 0;
  2068. switch (be_id) {
  2069. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  2070. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
  2071. break;
  2072. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  2073. afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
  2074. break;
  2075. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  2076. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
  2077. break;
  2078. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  2079. afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
  2080. break;
  2081. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  2082. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
  2083. break;
  2084. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  2085. afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
  2086. break;
  2087. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  2088. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
  2089. break;
  2090. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  2091. afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
  2092. break;
  2093. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  2094. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
  2095. break;
  2096. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  2097. afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
  2098. break;
  2099. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  2100. afe_port_id = AFE_PORT_ID_SENARY_MI2S_RX;
  2101. break;
  2102. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  2103. afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX;
  2104. break;
  2105. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2106. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0;
  2107. break;
  2108. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2109. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_1;
  2110. break;
  2111. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2112. afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_2;
  2113. break;
  2114. default:
  2115. pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
  2116. afe_port_id = -EINVAL;
  2117. }
  2118. return afe_port_id;
  2119. }
  2120. static u32 get_mi2s_bits_per_sample(u32 bit_format)
  2121. {
  2122. u32 bit_per_sample = 0;
  2123. switch (bit_format) {
  2124. case SNDRV_PCM_FORMAT_S32_LE:
  2125. case SNDRV_PCM_FORMAT_S24_3LE:
  2126. case SNDRV_PCM_FORMAT_S24_LE:
  2127. bit_per_sample = 32;
  2128. break;
  2129. case SNDRV_PCM_FORMAT_S16_LE:
  2130. default:
  2131. bit_per_sample = 16;
  2132. break;
  2133. }
  2134. return bit_per_sample;
  2135. }
  2136. static void update_mi2s_clk_val(int dai_id, int stream)
  2137. {
  2138. u32 bit_per_sample = 0;
  2139. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  2140. bit_per_sample =
  2141. get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
  2142. mi2s_clk[dai_id].clk_freq_in_hz =
  2143. mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2144. } else {
  2145. bit_per_sample =
  2146. get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
  2147. mi2s_clk[dai_id].clk_freq_in_hz =
  2148. mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
  2149. }
  2150. }
  2151. static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
  2152. {
  2153. int ret = 0;
  2154. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  2155. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  2156. int port_id = 0;
  2157. int index = cpu_dai->id;
  2158. port_id = msm_get_port_id(rtd->dai_link->id);
  2159. if (port_id < 0) {
  2160. dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
  2161. ret = port_id;
  2162. goto err;
  2163. }
  2164. if (enable) {
  2165. update_mi2s_clk_val(index, substream->stream);
  2166. dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
  2167. mi2s_clk[index].clk_freq_in_hz);
  2168. }
  2169. mi2s_clk[index].enable = enable;
  2170. ret = afe_set_lpass_clock_v2(port_id,
  2171. &mi2s_clk[index]);
  2172. if (ret < 0) {
  2173. dev_err(rtd->card->dev,
  2174. "%s: afe lpass clock failed for port 0x%x , err:%d\n",
  2175. __func__, port_id, ret);
  2176. goto err;
  2177. }
  2178. err:
  2179. return ret;
  2180. }
  2181. static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
  2182. {
  2183. int idx = 0;
  2184. if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
  2185. sizeof("WSA_CDC_DMA_RX_0")))
  2186. idx = WSA_CDC_DMA_RX_0;
  2187. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
  2188. sizeof("WSA_CDC_DMA_RX_0")))
  2189. idx = WSA_CDC_DMA_RX_1;
  2190. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
  2191. sizeof("RX_CDC_DMA_RX_0")))
  2192. idx = RX_CDC_DMA_RX_0;
  2193. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
  2194. sizeof("RX_CDC_DMA_RX_1")))
  2195. idx = RX_CDC_DMA_RX_1;
  2196. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
  2197. sizeof("RX_CDC_DMA_RX_2")))
  2198. idx = RX_CDC_DMA_RX_2;
  2199. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
  2200. sizeof("RX_CDC_DMA_RX_3")))
  2201. idx = RX_CDC_DMA_RX_3;
  2202. else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
  2203. sizeof("RX_CDC_DMA_RX_5")))
  2204. idx = RX_CDC_DMA_RX_5;
  2205. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
  2206. sizeof("WSA_CDC_DMA_TX_0")))
  2207. idx = WSA_CDC_DMA_TX_0;
  2208. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
  2209. sizeof("WSA_CDC_DMA_TX_1")))
  2210. idx = WSA_CDC_DMA_TX_1;
  2211. else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
  2212. sizeof("WSA_CDC_DMA_TX_2")))
  2213. idx = WSA_CDC_DMA_TX_2;
  2214. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
  2215. sizeof("TX_CDC_DMA_TX_0")))
  2216. idx = TX_CDC_DMA_TX_0;
  2217. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
  2218. sizeof("TX_CDC_DMA_TX_3")))
  2219. idx = TX_CDC_DMA_TX_3;
  2220. else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
  2221. sizeof("TX_CDC_DMA_TX_4")))
  2222. idx = TX_CDC_DMA_TX_4;
  2223. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_0",
  2224. sizeof("VA_CDC_DMA_TX_0")))
  2225. idx = VA_CDC_DMA_TX_0;
  2226. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_1",
  2227. sizeof("VA_CDC_DMA_TX_1")))
  2228. idx = VA_CDC_DMA_TX_1;
  2229. else if (strnstr(kcontrol->id.name, "VA_CDC_DMA_TX_2",
  2230. sizeof("VA_CDC_DMA_TX_2")))
  2231. idx = VA_CDC_DMA_TX_2;
  2232. else {
  2233. pr_err("%s: unsupported channel: %s\n",
  2234. __func__, kcontrol->id.name);
  2235. return -EINVAL;
  2236. }
  2237. return idx;
  2238. }
  2239. static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
  2240. struct snd_ctl_elem_value *ucontrol)
  2241. {
  2242. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2243. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2244. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2245. return ch_num;
  2246. }
  2247. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2248. cdc_dma_rx_cfg[ch_num].channels - 1);
  2249. ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
  2250. return 0;
  2251. }
  2252. static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
  2253. struct snd_ctl_elem_value *ucontrol)
  2254. {
  2255. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2256. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2257. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2258. return ch_num;
  2259. }
  2260. cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2261. pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
  2262. cdc_dma_rx_cfg[ch_num].channels);
  2263. return 1;
  2264. }
  2265. static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
  2266. struct snd_ctl_elem_value *ucontrol)
  2267. {
  2268. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2269. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2270. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2271. return ch_num;
  2272. }
  2273. switch (cdc_dma_rx_cfg[ch_num].bit_format) {
  2274. case SNDRV_PCM_FORMAT_S32_LE:
  2275. ucontrol->value.integer.value[0] = 3;
  2276. break;
  2277. case SNDRV_PCM_FORMAT_S24_3LE:
  2278. ucontrol->value.integer.value[0] = 2;
  2279. break;
  2280. case SNDRV_PCM_FORMAT_S24_LE:
  2281. ucontrol->value.integer.value[0] = 1;
  2282. break;
  2283. case SNDRV_PCM_FORMAT_S16_LE:
  2284. default:
  2285. ucontrol->value.integer.value[0] = 0;
  2286. break;
  2287. }
  2288. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2289. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2290. ucontrol->value.integer.value[0]);
  2291. return 0;
  2292. }
  2293. static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
  2294. struct snd_ctl_elem_value *ucontrol)
  2295. {
  2296. int rc = 0;
  2297. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2298. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2299. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2300. return ch_num;
  2301. }
  2302. switch (ucontrol->value.integer.value[0]) {
  2303. case 3:
  2304. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2305. break;
  2306. case 2:
  2307. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2308. break;
  2309. case 1:
  2310. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2311. break;
  2312. case 0:
  2313. default:
  2314. cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2315. break;
  2316. }
  2317. pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
  2318. __func__, cdc_dma_rx_cfg[ch_num].bit_format,
  2319. ucontrol->value.integer.value[0]);
  2320. return rc;
  2321. }
  2322. static int cdc_dma_get_sample_rate_val(int sample_rate)
  2323. {
  2324. int sample_rate_val = 0;
  2325. switch (sample_rate) {
  2326. case SAMPLING_RATE_8KHZ:
  2327. sample_rate_val = 0;
  2328. break;
  2329. case SAMPLING_RATE_11P025KHZ:
  2330. sample_rate_val = 1;
  2331. break;
  2332. case SAMPLING_RATE_16KHZ:
  2333. sample_rate_val = 2;
  2334. break;
  2335. case SAMPLING_RATE_22P05KHZ:
  2336. sample_rate_val = 3;
  2337. break;
  2338. case SAMPLING_RATE_32KHZ:
  2339. sample_rate_val = 4;
  2340. break;
  2341. case SAMPLING_RATE_44P1KHZ:
  2342. sample_rate_val = 5;
  2343. break;
  2344. case SAMPLING_RATE_48KHZ:
  2345. sample_rate_val = 6;
  2346. break;
  2347. case SAMPLING_RATE_88P2KHZ:
  2348. sample_rate_val = 7;
  2349. break;
  2350. case SAMPLING_RATE_96KHZ:
  2351. sample_rate_val = 8;
  2352. break;
  2353. case SAMPLING_RATE_176P4KHZ:
  2354. sample_rate_val = 9;
  2355. break;
  2356. case SAMPLING_RATE_192KHZ:
  2357. sample_rate_val = 10;
  2358. break;
  2359. case SAMPLING_RATE_352P8KHZ:
  2360. sample_rate_val = 11;
  2361. break;
  2362. case SAMPLING_RATE_384KHZ:
  2363. sample_rate_val = 12;
  2364. break;
  2365. default:
  2366. sample_rate_val = 6;
  2367. break;
  2368. }
  2369. return sample_rate_val;
  2370. }
  2371. static int cdc_dma_get_sample_rate(int value)
  2372. {
  2373. int sample_rate = 0;
  2374. switch (value) {
  2375. case 0:
  2376. sample_rate = SAMPLING_RATE_8KHZ;
  2377. break;
  2378. case 1:
  2379. sample_rate = SAMPLING_RATE_11P025KHZ;
  2380. break;
  2381. case 2:
  2382. sample_rate = SAMPLING_RATE_16KHZ;
  2383. break;
  2384. case 3:
  2385. sample_rate = SAMPLING_RATE_22P05KHZ;
  2386. break;
  2387. case 4:
  2388. sample_rate = SAMPLING_RATE_32KHZ;
  2389. break;
  2390. case 5:
  2391. sample_rate = SAMPLING_RATE_44P1KHZ;
  2392. break;
  2393. case 6:
  2394. sample_rate = SAMPLING_RATE_48KHZ;
  2395. break;
  2396. case 7:
  2397. sample_rate = SAMPLING_RATE_88P2KHZ;
  2398. break;
  2399. case 8:
  2400. sample_rate = SAMPLING_RATE_96KHZ;
  2401. break;
  2402. case 9:
  2403. sample_rate = SAMPLING_RATE_176P4KHZ;
  2404. break;
  2405. case 10:
  2406. sample_rate = SAMPLING_RATE_192KHZ;
  2407. break;
  2408. case 11:
  2409. sample_rate = SAMPLING_RATE_352P8KHZ;
  2410. break;
  2411. case 12:
  2412. sample_rate = SAMPLING_RATE_384KHZ;
  2413. break;
  2414. default:
  2415. sample_rate = SAMPLING_RATE_48KHZ;
  2416. break;
  2417. }
  2418. return sample_rate;
  2419. }
  2420. static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2421. struct snd_ctl_elem_value *ucontrol)
  2422. {
  2423. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2424. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2425. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2426. return ch_num;
  2427. }
  2428. ucontrol->value.enumerated.item[0] =
  2429. cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
  2430. pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
  2431. cdc_dma_rx_cfg[ch_num].sample_rate);
  2432. return 0;
  2433. }
  2434. static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2435. struct snd_ctl_elem_value *ucontrol)
  2436. {
  2437. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2438. if (ch_num < 0 || ch_num >= CDC_DMA_RX_MAX) {
  2439. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2440. return ch_num;
  2441. }
  2442. cdc_dma_rx_cfg[ch_num].sample_rate =
  2443. cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
  2444. pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
  2445. __func__, ucontrol->value.enumerated.item[0],
  2446. cdc_dma_rx_cfg[ch_num].sample_rate);
  2447. return 0;
  2448. }
  2449. static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
  2450. struct snd_ctl_elem_value *ucontrol)
  2451. {
  2452. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2453. if (ch_num < 0) {
  2454. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2455. return ch_num;
  2456. }
  2457. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2458. cdc_dma_tx_cfg[ch_num].channels);
  2459. ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
  2460. return 0;
  2461. }
  2462. static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
  2463. struct snd_ctl_elem_value *ucontrol)
  2464. {
  2465. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2466. if (ch_num < 0) {
  2467. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2468. return ch_num;
  2469. }
  2470. cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
  2471. pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
  2472. cdc_dma_tx_cfg[ch_num].channels);
  2473. return 1;
  2474. }
  2475. static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
  2476. struct snd_ctl_elem_value *ucontrol)
  2477. {
  2478. int sample_rate_val;
  2479. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2480. if (ch_num < 0) {
  2481. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2482. return ch_num;
  2483. }
  2484. switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
  2485. case SAMPLING_RATE_384KHZ:
  2486. sample_rate_val = 12;
  2487. break;
  2488. case SAMPLING_RATE_352P8KHZ:
  2489. sample_rate_val = 11;
  2490. break;
  2491. case SAMPLING_RATE_192KHZ:
  2492. sample_rate_val = 10;
  2493. break;
  2494. case SAMPLING_RATE_176P4KHZ:
  2495. sample_rate_val = 9;
  2496. break;
  2497. case SAMPLING_RATE_96KHZ:
  2498. sample_rate_val = 8;
  2499. break;
  2500. case SAMPLING_RATE_88P2KHZ:
  2501. sample_rate_val = 7;
  2502. break;
  2503. case SAMPLING_RATE_48KHZ:
  2504. sample_rate_val = 6;
  2505. break;
  2506. case SAMPLING_RATE_44P1KHZ:
  2507. sample_rate_val = 5;
  2508. break;
  2509. case SAMPLING_RATE_32KHZ:
  2510. sample_rate_val = 4;
  2511. break;
  2512. case SAMPLING_RATE_22P05KHZ:
  2513. sample_rate_val = 3;
  2514. break;
  2515. case SAMPLING_RATE_16KHZ:
  2516. sample_rate_val = 2;
  2517. break;
  2518. case SAMPLING_RATE_11P025KHZ:
  2519. sample_rate_val = 1;
  2520. break;
  2521. case SAMPLING_RATE_8KHZ:
  2522. sample_rate_val = 0;
  2523. break;
  2524. default:
  2525. sample_rate_val = 6;
  2526. break;
  2527. }
  2528. ucontrol->value.integer.value[0] = sample_rate_val;
  2529. pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
  2530. cdc_dma_tx_cfg[ch_num].sample_rate);
  2531. return 0;
  2532. }
  2533. static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
  2534. struct snd_ctl_elem_value *ucontrol)
  2535. {
  2536. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2537. if (ch_num < 0) {
  2538. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2539. return ch_num;
  2540. }
  2541. switch (ucontrol->value.integer.value[0]) {
  2542. case 12:
  2543. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
  2544. break;
  2545. case 11:
  2546. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
  2547. break;
  2548. case 10:
  2549. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
  2550. break;
  2551. case 9:
  2552. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
  2553. break;
  2554. case 8:
  2555. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
  2556. break;
  2557. case 7:
  2558. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
  2559. break;
  2560. case 6:
  2561. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2562. break;
  2563. case 5:
  2564. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
  2565. break;
  2566. case 4:
  2567. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
  2568. break;
  2569. case 3:
  2570. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
  2571. break;
  2572. case 2:
  2573. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
  2574. break;
  2575. case 1:
  2576. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
  2577. break;
  2578. case 0:
  2579. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
  2580. break;
  2581. default:
  2582. cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
  2583. break;
  2584. }
  2585. pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
  2586. __func__, ucontrol->value.integer.value[0],
  2587. cdc_dma_tx_cfg[ch_num].sample_rate);
  2588. return 0;
  2589. }
  2590. static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
  2591. struct snd_ctl_elem_value *ucontrol)
  2592. {
  2593. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2594. if (ch_num < 0) {
  2595. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2596. return ch_num;
  2597. }
  2598. switch (cdc_dma_tx_cfg[ch_num].bit_format) {
  2599. case SNDRV_PCM_FORMAT_S32_LE:
  2600. ucontrol->value.integer.value[0] = 3;
  2601. break;
  2602. case SNDRV_PCM_FORMAT_S24_3LE:
  2603. ucontrol->value.integer.value[0] = 2;
  2604. break;
  2605. case SNDRV_PCM_FORMAT_S24_LE:
  2606. ucontrol->value.integer.value[0] = 1;
  2607. break;
  2608. case SNDRV_PCM_FORMAT_S16_LE:
  2609. default:
  2610. ucontrol->value.integer.value[0] = 0;
  2611. break;
  2612. }
  2613. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2614. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2615. ucontrol->value.integer.value[0]);
  2616. return 0;
  2617. }
  2618. static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
  2619. struct snd_ctl_elem_value *ucontrol)
  2620. {
  2621. int rc = 0;
  2622. int ch_num = cdc_dma_get_port_idx(kcontrol);
  2623. if (ch_num < 0) {
  2624. pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
  2625. return ch_num;
  2626. }
  2627. switch (ucontrol->value.integer.value[0]) {
  2628. case 3:
  2629. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
  2630. break;
  2631. case 2:
  2632. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
  2633. break;
  2634. case 1:
  2635. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
  2636. break;
  2637. case 0:
  2638. default:
  2639. cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
  2640. break;
  2641. }
  2642. pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
  2643. __func__, cdc_dma_tx_cfg[ch_num].bit_format,
  2644. ucontrol->value.integer.value[0]);
  2645. return rc;
  2646. }
  2647. static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
  2648. {
  2649. int idx = 0;
  2650. switch (be_id) {
  2651. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  2652. idx = WSA_CDC_DMA_RX_0;
  2653. break;
  2654. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  2655. idx = WSA_CDC_DMA_TX_0;
  2656. break;
  2657. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  2658. idx = WSA_CDC_DMA_RX_1;
  2659. break;
  2660. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  2661. idx = WSA_CDC_DMA_TX_1;
  2662. break;
  2663. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  2664. idx = WSA_CDC_DMA_TX_2;
  2665. break;
  2666. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  2667. idx = RX_CDC_DMA_RX_0;
  2668. break;
  2669. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  2670. idx = RX_CDC_DMA_RX_1;
  2671. break;
  2672. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  2673. idx = RX_CDC_DMA_RX_2;
  2674. break;
  2675. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  2676. idx = RX_CDC_DMA_RX_3;
  2677. break;
  2678. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  2679. idx = RX_CDC_DMA_RX_5;
  2680. break;
  2681. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  2682. idx = TX_CDC_DMA_TX_0;
  2683. break;
  2684. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  2685. idx = TX_CDC_DMA_TX_3;
  2686. break;
  2687. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  2688. idx = TX_CDC_DMA_TX_4;
  2689. break;
  2690. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  2691. idx = VA_CDC_DMA_TX_0;
  2692. break;
  2693. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  2694. idx = VA_CDC_DMA_TX_1;
  2695. break;
  2696. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  2697. idx = VA_CDC_DMA_TX_2;
  2698. break;
  2699. default:
  2700. idx = RX_CDC_DMA_RX_0;
  2701. break;
  2702. }
  2703. return idx;
  2704. }
  2705. static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
  2706. struct snd_ctl_elem_value *ucontrol)
  2707. {
  2708. /*
  2709. * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
  2710. * when used for BT_SCO use case. Return either Rx or Tx sample rate
  2711. * value.
  2712. */
  2713. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2714. case SAMPLING_RATE_96KHZ:
  2715. ucontrol->value.integer.value[0] = 5;
  2716. break;
  2717. case SAMPLING_RATE_88P2KHZ:
  2718. ucontrol->value.integer.value[0] = 4;
  2719. break;
  2720. case SAMPLING_RATE_48KHZ:
  2721. ucontrol->value.integer.value[0] = 3;
  2722. break;
  2723. case SAMPLING_RATE_44P1KHZ:
  2724. ucontrol->value.integer.value[0] = 2;
  2725. break;
  2726. case SAMPLING_RATE_16KHZ:
  2727. ucontrol->value.integer.value[0] = 1;
  2728. break;
  2729. case SAMPLING_RATE_8KHZ:
  2730. default:
  2731. ucontrol->value.integer.value[0] = 0;
  2732. break;
  2733. }
  2734. pr_debug("%s: sample rate = %d\n", __func__,
  2735. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2736. return 0;
  2737. }
  2738. static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
  2739. struct snd_ctl_elem_value *ucontrol)
  2740. {
  2741. switch (ucontrol->value.integer.value[0]) {
  2742. case 1:
  2743. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2744. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2745. break;
  2746. case 2:
  2747. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2748. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2749. break;
  2750. case 3:
  2751. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2752. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2753. break;
  2754. case 4:
  2755. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2756. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2757. break;
  2758. case 5:
  2759. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2760. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2761. break;
  2762. case 0:
  2763. default:
  2764. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2765. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2766. break;
  2767. }
  2768. pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
  2769. __func__,
  2770. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2771. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2772. ucontrol->value.enumerated.item[0]);
  2773. return 0;
  2774. }
  2775. static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
  2776. struct snd_ctl_elem_value *ucontrol)
  2777. {
  2778. switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
  2779. case SAMPLING_RATE_96KHZ:
  2780. ucontrol->value.integer.value[0] = 5;
  2781. break;
  2782. case SAMPLING_RATE_88P2KHZ:
  2783. ucontrol->value.integer.value[0] = 4;
  2784. break;
  2785. case SAMPLING_RATE_48KHZ:
  2786. ucontrol->value.integer.value[0] = 3;
  2787. break;
  2788. case SAMPLING_RATE_44P1KHZ:
  2789. ucontrol->value.integer.value[0] = 2;
  2790. break;
  2791. case SAMPLING_RATE_16KHZ:
  2792. ucontrol->value.integer.value[0] = 1;
  2793. break;
  2794. case SAMPLING_RATE_8KHZ:
  2795. default:
  2796. ucontrol->value.integer.value[0] = 0;
  2797. break;
  2798. }
  2799. pr_debug("%s: sample rate rx = %d\n", __func__,
  2800. slim_rx_cfg[SLIM_RX_7].sample_rate);
  2801. return 0;
  2802. }
  2803. static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
  2804. struct snd_ctl_elem_value *ucontrol)
  2805. {
  2806. switch (ucontrol->value.integer.value[0]) {
  2807. case 1:
  2808. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2809. break;
  2810. case 2:
  2811. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2812. break;
  2813. case 3:
  2814. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2815. break;
  2816. case 4:
  2817. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2818. break;
  2819. case 5:
  2820. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2821. break;
  2822. case 0:
  2823. default:
  2824. slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2825. break;
  2826. }
  2827. pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
  2828. __func__,
  2829. slim_rx_cfg[SLIM_RX_7].sample_rate,
  2830. ucontrol->value.enumerated.item[0]);
  2831. return 0;
  2832. }
  2833. static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
  2834. struct snd_ctl_elem_value *ucontrol)
  2835. {
  2836. switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
  2837. case SAMPLING_RATE_96KHZ:
  2838. ucontrol->value.integer.value[0] = 5;
  2839. break;
  2840. case SAMPLING_RATE_88P2KHZ:
  2841. ucontrol->value.integer.value[0] = 4;
  2842. break;
  2843. case SAMPLING_RATE_48KHZ:
  2844. ucontrol->value.integer.value[0] = 3;
  2845. break;
  2846. case SAMPLING_RATE_44P1KHZ:
  2847. ucontrol->value.integer.value[0] = 2;
  2848. break;
  2849. case SAMPLING_RATE_16KHZ:
  2850. ucontrol->value.integer.value[0] = 1;
  2851. break;
  2852. case SAMPLING_RATE_8KHZ:
  2853. default:
  2854. ucontrol->value.integer.value[0] = 0;
  2855. break;
  2856. }
  2857. pr_debug("%s: sample rate tx = %d\n", __func__,
  2858. slim_tx_cfg[SLIM_TX_7].sample_rate);
  2859. return 0;
  2860. }
  2861. static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
  2862. struct snd_ctl_elem_value *ucontrol)
  2863. {
  2864. switch (ucontrol->value.integer.value[0]) {
  2865. case 1:
  2866. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
  2867. break;
  2868. case 2:
  2869. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
  2870. break;
  2871. case 3:
  2872. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
  2873. break;
  2874. case 4:
  2875. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
  2876. break;
  2877. case 5:
  2878. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
  2879. break;
  2880. case 0:
  2881. default:
  2882. slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
  2883. break;
  2884. }
  2885. pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
  2886. __func__,
  2887. slim_tx_cfg[SLIM_TX_7].sample_rate,
  2888. ucontrol->value.enumerated.item[0]);
  2889. return 0;
  2890. }
  2891. static const struct snd_kcontrol_new msm_int_snd_controls[] = {
  2892. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
  2893. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2894. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
  2895. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2896. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
  2897. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2898. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
  2899. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2900. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
  2901. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2902. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
  2903. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2904. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
  2905. cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
  2906. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
  2907. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2908. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
  2909. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2910. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
  2911. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2912. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
  2913. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2914. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
  2915. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2916. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
  2917. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2918. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Channels", va_cdc_dma_tx_0_chs,
  2919. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2920. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Channels", va_cdc_dma_tx_1_chs,
  2921. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2922. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Channels", va_cdc_dma_tx_2_chs,
  2923. cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
  2924. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
  2925. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2926. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
  2927. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2928. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
  2929. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2930. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
  2931. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2932. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
  2933. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2934. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
  2935. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2936. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
  2937. cdc_dma_rx_format_get, cdc_dma_rx_format_put),
  2938. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
  2939. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2940. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
  2941. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2942. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
  2943. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2944. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
  2945. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2946. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
  2947. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2948. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 Format", va_cdc_dma_tx_0_format,
  2949. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2950. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 Format", va_cdc_dma_tx_1_format,
  2951. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2952. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 Format", va_cdc_dma_tx_2_format,
  2953. cdc_dma_tx_format_get, cdc_dma_tx_format_put),
  2954. SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
  2955. wsa_cdc_dma_rx_0_sample_rate,
  2956. cdc_dma_rx_sample_rate_get,
  2957. cdc_dma_rx_sample_rate_put),
  2958. SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
  2959. wsa_cdc_dma_rx_1_sample_rate,
  2960. cdc_dma_rx_sample_rate_get,
  2961. cdc_dma_rx_sample_rate_put),
  2962. SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
  2963. rx_cdc_dma_rx_0_sample_rate,
  2964. cdc_dma_rx_sample_rate_get,
  2965. cdc_dma_rx_sample_rate_put),
  2966. SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
  2967. rx_cdc_dma_rx_1_sample_rate,
  2968. cdc_dma_rx_sample_rate_get,
  2969. cdc_dma_rx_sample_rate_put),
  2970. SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
  2971. rx_cdc_dma_rx_2_sample_rate,
  2972. cdc_dma_rx_sample_rate_get,
  2973. cdc_dma_rx_sample_rate_put),
  2974. SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
  2975. rx_cdc_dma_rx_3_sample_rate,
  2976. cdc_dma_rx_sample_rate_get,
  2977. cdc_dma_rx_sample_rate_put),
  2978. SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
  2979. rx_cdc_dma_rx_5_sample_rate,
  2980. cdc_dma_rx_sample_rate_get,
  2981. cdc_dma_rx_sample_rate_put),
  2982. SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
  2983. wsa_cdc_dma_tx_0_sample_rate,
  2984. cdc_dma_tx_sample_rate_get,
  2985. cdc_dma_tx_sample_rate_put),
  2986. SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
  2987. wsa_cdc_dma_tx_1_sample_rate,
  2988. cdc_dma_tx_sample_rate_get,
  2989. cdc_dma_tx_sample_rate_put),
  2990. SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
  2991. wsa_cdc_dma_tx_2_sample_rate,
  2992. cdc_dma_tx_sample_rate_get,
  2993. cdc_dma_tx_sample_rate_put),
  2994. SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
  2995. tx_cdc_dma_tx_0_sample_rate,
  2996. cdc_dma_tx_sample_rate_get,
  2997. cdc_dma_tx_sample_rate_put),
  2998. SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
  2999. tx_cdc_dma_tx_3_sample_rate,
  3000. cdc_dma_tx_sample_rate_get,
  3001. cdc_dma_tx_sample_rate_put),
  3002. SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
  3003. tx_cdc_dma_tx_4_sample_rate,
  3004. cdc_dma_tx_sample_rate_get,
  3005. cdc_dma_tx_sample_rate_put),
  3006. SOC_ENUM_EXT("VA_CDC_DMA_TX_0 SampleRate",
  3007. va_cdc_dma_tx_0_sample_rate,
  3008. cdc_dma_tx_sample_rate_get,
  3009. cdc_dma_tx_sample_rate_put),
  3010. SOC_ENUM_EXT("VA_CDC_DMA_TX_1 SampleRate",
  3011. va_cdc_dma_tx_1_sample_rate,
  3012. cdc_dma_tx_sample_rate_get,
  3013. cdc_dma_tx_sample_rate_put),
  3014. SOC_ENUM_EXT("VA_CDC_DMA_TX_2 SampleRate",
  3015. va_cdc_dma_tx_2_sample_rate,
  3016. cdc_dma_tx_sample_rate_get,
  3017. cdc_dma_tx_sample_rate_put),
  3018. };
  3019. static const struct snd_kcontrol_new msm_common_snd_controls[] = {
  3020. SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
  3021. usb_audio_rx_sample_rate_get,
  3022. usb_audio_rx_sample_rate_put),
  3023. SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
  3024. usb_audio_tx_sample_rate_get,
  3025. usb_audio_tx_sample_rate_put),
  3026. SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3027. tdm_rx_sample_rate_get,
  3028. tdm_rx_sample_rate_put),
  3029. SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3030. tdm_rx_sample_rate_get,
  3031. tdm_rx_sample_rate_put),
  3032. SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3033. tdm_rx_sample_rate_get,
  3034. tdm_rx_sample_rate_put),
  3035. SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3036. tdm_rx_sample_rate_get,
  3037. tdm_rx_sample_rate_put),
  3038. SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3039. tdm_rx_sample_rate_get,
  3040. tdm_rx_sample_rate_put),
  3041. SOC_ENUM_EXT("SEN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
  3042. tdm_rx_sample_rate_get,
  3043. tdm_rx_sample_rate_put),
  3044. SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3045. tdm_tx_sample_rate_get,
  3046. tdm_tx_sample_rate_put),
  3047. SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3048. tdm_tx_sample_rate_get,
  3049. tdm_tx_sample_rate_put),
  3050. SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3051. tdm_tx_sample_rate_get,
  3052. tdm_tx_sample_rate_put),
  3053. SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3054. tdm_tx_sample_rate_get,
  3055. tdm_tx_sample_rate_put),
  3056. SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3057. tdm_tx_sample_rate_get,
  3058. tdm_tx_sample_rate_put),
  3059. SOC_ENUM_EXT("SEN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
  3060. tdm_tx_sample_rate_get,
  3061. tdm_tx_sample_rate_put),
  3062. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3063. aux_pcm_rx_sample_rate_get,
  3064. aux_pcm_rx_sample_rate_put),
  3065. SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
  3066. aux_pcm_rx_sample_rate_get,
  3067. aux_pcm_rx_sample_rate_put),
  3068. SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
  3069. aux_pcm_rx_sample_rate_get,
  3070. aux_pcm_rx_sample_rate_put),
  3071. SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
  3072. aux_pcm_rx_sample_rate_get,
  3073. aux_pcm_rx_sample_rate_put),
  3074. SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
  3075. aux_pcm_rx_sample_rate_get,
  3076. aux_pcm_rx_sample_rate_put),
  3077. SOC_ENUM_EXT("SEN_AUX_PCM_RX SampleRate", sen_aux_pcm_rx_sample_rate,
  3078. aux_pcm_rx_sample_rate_get,
  3079. aux_pcm_rx_sample_rate_put),
  3080. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3081. aux_pcm_tx_sample_rate_get,
  3082. aux_pcm_tx_sample_rate_put),
  3083. SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
  3084. aux_pcm_tx_sample_rate_get,
  3085. aux_pcm_tx_sample_rate_put),
  3086. SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
  3087. aux_pcm_tx_sample_rate_get,
  3088. aux_pcm_tx_sample_rate_put),
  3089. SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
  3090. aux_pcm_tx_sample_rate_get,
  3091. aux_pcm_tx_sample_rate_put),
  3092. SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
  3093. aux_pcm_tx_sample_rate_get,
  3094. aux_pcm_tx_sample_rate_put),
  3095. SOC_ENUM_EXT("SEN_AUX_PCM_TX SampleRate", sen_aux_pcm_tx_sample_rate,
  3096. aux_pcm_tx_sample_rate_get,
  3097. aux_pcm_tx_sample_rate_put),
  3098. SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
  3099. mi2s_rx_sample_rate_get,
  3100. mi2s_rx_sample_rate_put),
  3101. SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
  3102. mi2s_rx_sample_rate_get,
  3103. mi2s_rx_sample_rate_put),
  3104. SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
  3105. mi2s_rx_sample_rate_get,
  3106. mi2s_rx_sample_rate_put),
  3107. SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
  3108. mi2s_rx_sample_rate_get,
  3109. mi2s_rx_sample_rate_put),
  3110. SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
  3111. mi2s_rx_sample_rate_get,
  3112. mi2s_rx_sample_rate_put),
  3113. SOC_ENUM_EXT("SEN_MI2S_RX SampleRate", sen_mi2s_rx_sample_rate,
  3114. mi2s_rx_sample_rate_get,
  3115. mi2s_rx_sample_rate_put),
  3116. SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
  3117. mi2s_tx_sample_rate_get,
  3118. mi2s_tx_sample_rate_put),
  3119. SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
  3120. mi2s_tx_sample_rate_get,
  3121. mi2s_tx_sample_rate_put),
  3122. SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
  3123. mi2s_tx_sample_rate_get,
  3124. mi2s_tx_sample_rate_put),
  3125. SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
  3126. mi2s_tx_sample_rate_get,
  3127. mi2s_tx_sample_rate_put),
  3128. SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
  3129. mi2s_tx_sample_rate_get,
  3130. mi2s_tx_sample_rate_put),
  3131. SOC_ENUM_EXT("SEN_MI2S_TX SampleRate", sen_mi2s_tx_sample_rate,
  3132. mi2s_tx_sample_rate_get,
  3133. mi2s_tx_sample_rate_put),
  3134. SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
  3135. usb_audio_rx_format_get, usb_audio_rx_format_put),
  3136. SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
  3137. usb_audio_tx_format_get, usb_audio_tx_format_put),
  3138. SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
  3139. tdm_rx_format_get,
  3140. tdm_rx_format_put),
  3141. SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
  3142. tdm_rx_format_get,
  3143. tdm_rx_format_put),
  3144. SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
  3145. tdm_rx_format_get,
  3146. tdm_rx_format_put),
  3147. SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
  3148. tdm_rx_format_get,
  3149. tdm_rx_format_put),
  3150. SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
  3151. tdm_rx_format_get,
  3152. tdm_rx_format_put),
  3153. SOC_ENUM_EXT("SEN_TDM_RX_0 Format", tdm_rx_format,
  3154. tdm_rx_format_get,
  3155. tdm_rx_format_put),
  3156. SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
  3157. tdm_tx_format_get,
  3158. tdm_tx_format_put),
  3159. SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
  3160. tdm_tx_format_get,
  3161. tdm_tx_format_put),
  3162. SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
  3163. tdm_tx_format_get,
  3164. tdm_tx_format_put),
  3165. SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
  3166. tdm_tx_format_get,
  3167. tdm_tx_format_put),
  3168. SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
  3169. tdm_tx_format_get,
  3170. tdm_tx_format_put),
  3171. SOC_ENUM_EXT("SEN_TDM_TX_0 Format", tdm_tx_format,
  3172. tdm_tx_format_get,
  3173. tdm_tx_format_put),
  3174. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3175. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3176. SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
  3177. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3178. SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3179. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3180. SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
  3181. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3182. SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3183. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3184. SOC_ENUM_EXT("SEN_AUX_PCM_RX Format", aux_pcm_rx_format,
  3185. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3186. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3187. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3188. SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
  3189. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3190. SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3191. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3192. SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
  3193. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3194. SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3195. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3196. SOC_ENUM_EXT("SEN_AUX_PCM_TX Format", aux_pcm_tx_format,
  3197. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3198. SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
  3199. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3200. SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
  3201. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3202. SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
  3203. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3204. SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
  3205. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3206. SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
  3207. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3208. SOC_ENUM_EXT("SEN_MI2S_RX Format", mi2s_rx_format,
  3209. msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
  3210. SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
  3211. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3212. SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
  3213. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3214. SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
  3215. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3216. SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
  3217. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3218. SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
  3219. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3220. SOC_ENUM_EXT("SEN_MI2S_TX Format", mi2s_tx_format,
  3221. msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
  3222. SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
  3223. usb_audio_rx_ch_get, usb_audio_rx_ch_put),
  3224. SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
  3225. usb_audio_tx_ch_get, usb_audio_tx_ch_put),
  3226. SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
  3227. proxy_rx_ch_get, proxy_rx_ch_put),
  3228. SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
  3229. tdm_rx_ch_get,
  3230. tdm_rx_ch_put),
  3231. SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
  3232. tdm_rx_ch_get,
  3233. tdm_rx_ch_put),
  3234. SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
  3235. tdm_rx_ch_get,
  3236. tdm_rx_ch_put),
  3237. SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
  3238. tdm_rx_ch_get,
  3239. tdm_rx_ch_put),
  3240. SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
  3241. tdm_rx_ch_get,
  3242. tdm_rx_ch_put),
  3243. SOC_ENUM_EXT("SEN_TDM_RX_0 Channels", tdm_rx_chs,
  3244. tdm_rx_ch_get,
  3245. tdm_rx_ch_put),
  3246. SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
  3247. tdm_tx_ch_get,
  3248. tdm_tx_ch_put),
  3249. SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
  3250. tdm_tx_ch_get,
  3251. tdm_tx_ch_put),
  3252. SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
  3253. tdm_tx_ch_get,
  3254. tdm_tx_ch_put),
  3255. SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
  3256. tdm_tx_ch_get,
  3257. tdm_tx_ch_put),
  3258. SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
  3259. tdm_tx_ch_get,
  3260. tdm_tx_ch_put),
  3261. SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs,
  3262. tdm_tx_ch_get,
  3263. tdm_tx_ch_put),
  3264. SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
  3265. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3266. SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
  3267. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3268. SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
  3269. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3270. SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
  3271. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3272. SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
  3273. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3274. SOC_ENUM_EXT("SEN_MI2S_RX Channels", sen_mi2s_rx_chs,
  3275. msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
  3276. SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
  3277. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3278. SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
  3279. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3280. SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
  3281. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3282. SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
  3283. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3284. SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
  3285. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3286. SOC_ENUM_EXT("SEN_MI2S_TX Channels", sen_mi2s_tx_chs,
  3287. msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
  3288. SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
  3289. ext_disp_rx_ch_get, ext_disp_rx_ch_put),
  3290. SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
  3291. ext_disp_rx_format_get, ext_disp_rx_format_put),
  3292. SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
  3293. ext_disp_rx_sample_rate_get,
  3294. ext_disp_rx_sample_rate_put),
  3295. SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
  3296. msm_bt_sample_rate_get,
  3297. msm_bt_sample_rate_put),
  3298. SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
  3299. msm_bt_sample_rate_rx_get,
  3300. msm_bt_sample_rate_rx_put),
  3301. SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
  3302. msm_bt_sample_rate_tx_get,
  3303. msm_bt_sample_rate_tx_put),
  3304. SOC_ENUM_EXT("AFE_LOOPBACK_TX Channels", afe_loopback_tx_chs,
  3305. afe_loopback_tx_ch_get, afe_loopback_tx_ch_put),
  3306. SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
  3307. msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
  3308. };
  3309. static const struct snd_kcontrol_new msm_snd_controls[] = {
  3310. SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
  3311. msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
  3312. SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
  3313. msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
  3314. SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
  3315. aux_pcm_rx_sample_rate_get,
  3316. aux_pcm_rx_sample_rate_put),
  3317. SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
  3318. aux_pcm_tx_sample_rate_get,
  3319. aux_pcm_tx_sample_rate_put),
  3320. };
  3321. static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
  3322. {
  3323. int idx;
  3324. switch (be_id) {
  3325. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3326. idx = EXT_DISP_RX_IDX_DP;
  3327. break;
  3328. default:
  3329. pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
  3330. idx = -EINVAL;
  3331. break;
  3332. }
  3333. return idx;
  3334. }
  3335. static int kona_send_island_va_config(int32_t be_id)
  3336. {
  3337. int rc = 0;
  3338. int port_id = 0xFFFF;
  3339. port_id = msm_get_port_id(be_id);
  3340. if (port_id < 0) {
  3341. pr_err("%s: Invalid island interface, be_id: %d\n",
  3342. __func__, be_id);
  3343. rc = -EINVAL;
  3344. } else {
  3345. /*
  3346. * send island mode config
  3347. * This should be the first configuration
  3348. */
  3349. rc = afe_send_port_island_mode(port_id);
  3350. if (rc)
  3351. pr_err("%s: afe send island mode failed %d\n",
  3352. __func__, rc);
  3353. }
  3354. return rc;
  3355. }
  3356. static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
  3357. struct snd_pcm_hw_params *params)
  3358. {
  3359. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  3360. struct snd_interval *rate = hw_param_interval(params,
  3361. SNDRV_PCM_HW_PARAM_RATE);
  3362. struct snd_interval *channels = hw_param_interval(params,
  3363. SNDRV_PCM_HW_PARAM_CHANNELS);
  3364. int idx = 0, rc = 0;
  3365. pr_debug("%s: format = %d, rate = %d\n",
  3366. __func__, params_format(params), params_rate(params));
  3367. switch (dai_link->id) {
  3368. case MSM_BACKEND_DAI_USB_RX:
  3369. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3370. usb_rx_cfg.bit_format);
  3371. rate->min = rate->max = usb_rx_cfg.sample_rate;
  3372. channels->min = channels->max = usb_rx_cfg.channels;
  3373. break;
  3374. case MSM_BACKEND_DAI_USB_TX:
  3375. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3376. usb_tx_cfg.bit_format);
  3377. rate->min = rate->max = usb_tx_cfg.sample_rate;
  3378. channels->min = channels->max = usb_tx_cfg.channels;
  3379. break;
  3380. case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
  3381. idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
  3382. if (idx < 0) {
  3383. pr_err("%s: Incorrect ext disp idx %d\n",
  3384. __func__, idx);
  3385. rc = idx;
  3386. goto done;
  3387. }
  3388. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3389. ext_disp_rx_cfg[idx].bit_format);
  3390. rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
  3391. channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
  3392. break;
  3393. case MSM_BACKEND_DAI_AFE_PCM_RX:
  3394. channels->min = channels->max = proxy_rx_cfg.channels;
  3395. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3396. break;
  3397. case MSM_BACKEND_DAI_PRI_TDM_RX_0:
  3398. channels->min = channels->max =
  3399. tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3400. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3401. tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
  3402. rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
  3403. break;
  3404. case MSM_BACKEND_DAI_PRI_TDM_TX_0:
  3405. channels->min = channels->max =
  3406. tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3407. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3408. tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
  3409. rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
  3410. break;
  3411. case MSM_BACKEND_DAI_SEC_TDM_RX_0:
  3412. channels->min = channels->max =
  3413. tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3414. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3415. tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
  3416. rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
  3417. break;
  3418. case MSM_BACKEND_DAI_SEC_TDM_TX_0:
  3419. channels->min = channels->max =
  3420. tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3421. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3422. tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
  3423. rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
  3424. break;
  3425. case MSM_BACKEND_DAI_TERT_TDM_RX_0:
  3426. channels->min = channels->max =
  3427. tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3428. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3429. tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
  3430. rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
  3431. break;
  3432. case MSM_BACKEND_DAI_TERT_TDM_TX_0:
  3433. channels->min = channels->max =
  3434. tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3435. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3436. tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
  3437. rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
  3438. break;
  3439. case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
  3440. channels->min = channels->max =
  3441. tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3442. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3443. tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
  3444. rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3445. break;
  3446. case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
  3447. channels->min = channels->max =
  3448. tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3449. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3450. tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
  3451. rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
  3452. break;
  3453. case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
  3454. channels->min = channels->max =
  3455. tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3456. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3457. tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
  3458. rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3459. break;
  3460. case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
  3461. channels->min = channels->max =
  3462. tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3463. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3464. tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
  3465. rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
  3466. break;
  3467. case MSM_BACKEND_DAI_SEN_TDM_RX_0:
  3468. channels->min = channels->max =
  3469. tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3470. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3471. tdm_rx_cfg[TDM_SEN][TDM_0].bit_format);
  3472. rate->min = rate->max = tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate;
  3473. break;
  3474. case MSM_BACKEND_DAI_SEN_TDM_TX_0:
  3475. channels->min = channels->max =
  3476. tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3477. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3478. tdm_tx_cfg[TDM_SEN][TDM_0].bit_format);
  3479. rate->min = rate->max = tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate;
  3480. break;
  3481. case MSM_BACKEND_DAI_AUXPCM_RX:
  3482. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3483. aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
  3484. rate->min = rate->max =
  3485. aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
  3486. channels->min = channels->max =
  3487. aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
  3488. break;
  3489. case MSM_BACKEND_DAI_AUXPCM_TX:
  3490. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3491. aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
  3492. rate->min = rate->max =
  3493. aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
  3494. channels->min = channels->max =
  3495. aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
  3496. break;
  3497. case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
  3498. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3499. aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
  3500. rate->min = rate->max =
  3501. aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
  3502. channels->min = channels->max =
  3503. aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
  3504. break;
  3505. case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
  3506. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3507. aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
  3508. rate->min = rate->max =
  3509. aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
  3510. channels->min = channels->max =
  3511. aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
  3512. break;
  3513. case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
  3514. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3515. aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
  3516. rate->min = rate->max =
  3517. aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
  3518. channels->min = channels->max =
  3519. aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
  3520. break;
  3521. case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
  3522. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3523. aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
  3524. rate->min = rate->max =
  3525. aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
  3526. channels->min = channels->max =
  3527. aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
  3528. break;
  3529. case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
  3530. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3531. aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
  3532. rate->min = rate->max =
  3533. aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
  3534. channels->min = channels->max =
  3535. aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
  3536. break;
  3537. case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
  3538. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3539. aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
  3540. rate->min = rate->max =
  3541. aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
  3542. channels->min = channels->max =
  3543. aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
  3544. break;
  3545. case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
  3546. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3547. aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
  3548. rate->min = rate->max =
  3549. aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
  3550. channels->min = channels->max =
  3551. aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
  3552. break;
  3553. case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
  3554. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3555. aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
  3556. rate->min = rate->max =
  3557. aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
  3558. channels->min = channels->max =
  3559. aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
  3560. break;
  3561. case MSM_BACKEND_DAI_SEN_AUXPCM_RX:
  3562. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3563. aux_pcm_rx_cfg[SEN_AUX_PCM].bit_format);
  3564. rate->min = rate->max =
  3565. aux_pcm_rx_cfg[SEN_AUX_PCM].sample_rate;
  3566. channels->min = channels->max =
  3567. aux_pcm_rx_cfg[SEN_AUX_PCM].channels;
  3568. break;
  3569. case MSM_BACKEND_DAI_SEN_AUXPCM_TX:
  3570. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3571. aux_pcm_tx_cfg[SEN_AUX_PCM].bit_format);
  3572. rate->min = rate->max =
  3573. aux_pcm_tx_cfg[SEN_AUX_PCM].sample_rate;
  3574. channels->min = channels->max =
  3575. aux_pcm_tx_cfg[SEN_AUX_PCM].channels;
  3576. break;
  3577. case MSM_BACKEND_DAI_PRI_MI2S_RX:
  3578. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3579. mi2s_rx_cfg[PRIM_MI2S].bit_format);
  3580. rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
  3581. channels->min = channels->max =
  3582. mi2s_rx_cfg[PRIM_MI2S].channels;
  3583. break;
  3584. case MSM_BACKEND_DAI_PRI_MI2S_TX:
  3585. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3586. mi2s_tx_cfg[PRIM_MI2S].bit_format);
  3587. rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
  3588. channels->min = channels->max =
  3589. mi2s_tx_cfg[PRIM_MI2S].channels;
  3590. break;
  3591. case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
  3592. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3593. mi2s_rx_cfg[SEC_MI2S].bit_format);
  3594. rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
  3595. channels->min = channels->max =
  3596. mi2s_rx_cfg[SEC_MI2S].channels;
  3597. break;
  3598. case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
  3599. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3600. mi2s_tx_cfg[SEC_MI2S].bit_format);
  3601. rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
  3602. channels->min = channels->max =
  3603. mi2s_tx_cfg[SEC_MI2S].channels;
  3604. break;
  3605. case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
  3606. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3607. mi2s_rx_cfg[TERT_MI2S].bit_format);
  3608. rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
  3609. channels->min = channels->max =
  3610. mi2s_rx_cfg[TERT_MI2S].channels;
  3611. break;
  3612. case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
  3613. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3614. mi2s_tx_cfg[TERT_MI2S].bit_format);
  3615. rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
  3616. channels->min = channels->max =
  3617. mi2s_tx_cfg[TERT_MI2S].channels;
  3618. break;
  3619. case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
  3620. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3621. mi2s_rx_cfg[QUAT_MI2S].bit_format);
  3622. rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
  3623. channels->min = channels->max =
  3624. mi2s_rx_cfg[QUAT_MI2S].channels;
  3625. break;
  3626. case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
  3627. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3628. mi2s_tx_cfg[QUAT_MI2S].bit_format);
  3629. rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
  3630. channels->min = channels->max =
  3631. mi2s_tx_cfg[QUAT_MI2S].channels;
  3632. break;
  3633. case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
  3634. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3635. mi2s_rx_cfg[QUIN_MI2S].bit_format);
  3636. rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
  3637. channels->min = channels->max =
  3638. mi2s_rx_cfg[QUIN_MI2S].channels;
  3639. break;
  3640. case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
  3641. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3642. mi2s_tx_cfg[QUIN_MI2S].bit_format);
  3643. rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
  3644. channels->min = channels->max =
  3645. mi2s_tx_cfg[QUIN_MI2S].channels;
  3646. break;
  3647. case MSM_BACKEND_DAI_SENARY_MI2S_RX:
  3648. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3649. mi2s_rx_cfg[SEN_MI2S].bit_format);
  3650. rate->min = rate->max = mi2s_rx_cfg[SEN_MI2S].sample_rate;
  3651. channels->min = channels->max =
  3652. mi2s_rx_cfg[SEN_MI2S].channels;
  3653. break;
  3654. case MSM_BACKEND_DAI_SENARY_MI2S_TX:
  3655. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3656. mi2s_tx_cfg[SEN_MI2S].bit_format);
  3657. rate->min = rate->max = mi2s_tx_cfg[SEN_MI2S].sample_rate;
  3658. channels->min = channels->max =
  3659. mi2s_tx_cfg[SEN_MI2S].channels;
  3660. break;
  3661. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  3662. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  3663. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  3664. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  3665. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  3666. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  3667. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3668. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3669. cdc_dma_rx_cfg[idx].bit_format);
  3670. rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
  3671. channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
  3672. break;
  3673. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  3674. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  3675. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  3676. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  3677. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  3678. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  3679. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  3680. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  3681. idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  3682. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3683. cdc_dma_tx_cfg[idx].bit_format);
  3684. rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
  3685. channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
  3686. break;
  3687. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  3688. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3689. SNDRV_PCM_FORMAT_S32_LE);
  3690. rate->min = rate->max = SAMPLING_RATE_8KHZ;
  3691. channels->min = channels->max = msm_vi_feed_tx_ch;
  3692. break;
  3693. case MSM_BACKEND_DAI_SLIMBUS_7_RX:
  3694. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3695. slim_rx_cfg[SLIM_RX_7].bit_format);
  3696. rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
  3697. channels->min = channels->max =
  3698. slim_rx_cfg[SLIM_RX_7].channels;
  3699. break;
  3700. case MSM_BACKEND_DAI_SLIMBUS_7_TX:
  3701. rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
  3702. channels->min = channels->max =
  3703. slim_tx_cfg[SLIM_TX_7].channels;
  3704. break;
  3705. case MSM_BACKEND_DAI_SLIMBUS_8_TX:
  3706. rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
  3707. channels->min = channels->max =
  3708. slim_tx_cfg[SLIM_TX_8].channels;
  3709. break;
  3710. case MSM_BACKEND_DAI_AFE_LOOPBACK_TX:
  3711. param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
  3712. afe_loopback_tx_cfg[idx].bit_format);
  3713. rate->min = rate->max = afe_loopback_tx_cfg[idx].sample_rate;
  3714. channels->min = channels->max =
  3715. afe_loopback_tx_cfg[idx].channels;
  3716. break;
  3717. default:
  3718. rate->min = rate->max = SAMPLING_RATE_48KHZ;
  3719. break;
  3720. }
  3721. done:
  3722. return rc;
  3723. }
  3724. static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3725. {
  3726. struct snd_soc_card *card = component->card;
  3727. struct msm_asoc_mach_data *pdata =
  3728. snd_soc_card_get_drvdata(card);
  3729. if (!pdata->fsa_handle)
  3730. return false;
  3731. return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
  3732. }
  3733. static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
  3734. {
  3735. int value = 0;
  3736. bool ret = false;
  3737. struct snd_soc_card *card;
  3738. struct msm_asoc_mach_data *pdata;
  3739. if (!component) {
  3740. pr_err("%s component is NULL\n", __func__);
  3741. return false;
  3742. }
  3743. card = component->card;
  3744. pdata = snd_soc_card_get_drvdata(card);
  3745. if (!pdata)
  3746. return false;
  3747. if (wcd_mbhc_cfg.enable_usbc_analog)
  3748. return msm_usbc_swap_gnd_mic(component, active);
  3749. /* if usbc is not defined, swap using us_euro_gpio_p */
  3750. if (pdata->us_euro_gpio_p) {
  3751. value = msm_cdc_pinctrl_get_state(
  3752. pdata->us_euro_gpio_p);
  3753. if (value)
  3754. msm_cdc_pinctrl_select_sleep_state(
  3755. pdata->us_euro_gpio_p);
  3756. else
  3757. msm_cdc_pinctrl_select_active_state(
  3758. pdata->us_euro_gpio_p);
  3759. dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
  3760. __func__, value, !value);
  3761. ret = true;
  3762. }
  3763. return ret;
  3764. }
  3765. static int kona_tdm_snd_hw_params(struct snd_pcm_substream *substream,
  3766. struct snd_pcm_hw_params *params)
  3767. {
  3768. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3769. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3770. int ret = 0;
  3771. int slot_width = 32;
  3772. int channels, slots;
  3773. unsigned int slot_mask, rate, clk_freq;
  3774. unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
  3775. pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
  3776. /* currently only supporting TDM_RX_0 and TDM_TX_0 */
  3777. switch (cpu_dai->id) {
  3778. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3779. slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
  3780. break;
  3781. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3782. slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
  3783. break;
  3784. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3785. slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
  3786. break;
  3787. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3788. slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
  3789. break;
  3790. case AFE_PORT_ID_QUINARY_TDM_RX:
  3791. slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
  3792. break;
  3793. case AFE_PORT_ID_SENARY_TDM_RX:
  3794. slots = tdm_rx_cfg[TDM_SEN][TDM_0].channels;
  3795. break;
  3796. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3797. slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
  3798. break;
  3799. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3800. slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
  3801. break;
  3802. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3803. slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
  3804. break;
  3805. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3806. slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
  3807. break;
  3808. case AFE_PORT_ID_QUINARY_TDM_TX:
  3809. slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
  3810. break;
  3811. case AFE_PORT_ID_SENARY_TDM_TX:
  3812. slots = tdm_tx_cfg[TDM_SEN][TDM_0].channels;
  3813. break;
  3814. default:
  3815. pr_err("%s: dai id 0x%x not supported\n",
  3816. __func__, cpu_dai->id);
  3817. return -EINVAL;
  3818. }
  3819. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  3820. /*2 slot config - bits 0 and 1 set for the first two slots */
  3821. slot_mask = 0x0000FFFF >> (16 - slots);
  3822. channels = slots;
  3823. pr_debug("%s: tdm rx slot_width %d slots %d\n",
  3824. __func__, slot_width, slots);
  3825. ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
  3826. slots, slot_width);
  3827. if (ret < 0) {
  3828. pr_err("%s: failed to set tdm rx slot, err:%d\n",
  3829. __func__, ret);
  3830. goto end;
  3831. }
  3832. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3833. 0, NULL, channels, slot_offset);
  3834. if (ret < 0) {
  3835. pr_err("%s: failed to set tdm rx channel map, err:%d\n",
  3836. __func__, ret);
  3837. goto end;
  3838. }
  3839. } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  3840. /*2 slot config - bits 0 and 1 set for the first two slots */
  3841. slot_mask = 0x0000FFFF >> (16 - slots);
  3842. channels = slots;
  3843. pr_debug("%s: tdm tx slot_width %d slots %d\n",
  3844. __func__, slot_width, slots);
  3845. ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
  3846. slots, slot_width);
  3847. if (ret < 0) {
  3848. pr_err("%s: failed to set tdm tx slot, err:%d\n",
  3849. __func__, ret);
  3850. goto end;
  3851. }
  3852. ret = snd_soc_dai_set_channel_map(cpu_dai,
  3853. channels, slot_offset, 0, NULL);
  3854. if (ret < 0) {
  3855. pr_err("%s: failed to set tdm tx channel map, err:%d\n",
  3856. __func__, ret);
  3857. goto end;
  3858. }
  3859. } else {
  3860. ret = -EINVAL;
  3861. pr_err("%s: invalid use case, err:%d\n",
  3862. __func__, ret);
  3863. goto end;
  3864. }
  3865. rate = params_rate(params);
  3866. clk_freq = rate * slot_width * slots;
  3867. ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
  3868. if (ret < 0)
  3869. pr_err("%s: failed to set tdm clk, err:%d\n",
  3870. __func__, ret);
  3871. end:
  3872. return ret;
  3873. }
  3874. static int msm_get_tdm_mode(u32 port_id)
  3875. {
  3876. int tdm_mode;
  3877. switch (port_id) {
  3878. case AFE_PORT_ID_PRIMARY_TDM_RX:
  3879. case AFE_PORT_ID_PRIMARY_TDM_TX:
  3880. tdm_mode = TDM_PRI;
  3881. break;
  3882. case AFE_PORT_ID_SECONDARY_TDM_RX:
  3883. case AFE_PORT_ID_SECONDARY_TDM_TX:
  3884. tdm_mode = TDM_SEC;
  3885. break;
  3886. case AFE_PORT_ID_TERTIARY_TDM_RX:
  3887. case AFE_PORT_ID_TERTIARY_TDM_TX:
  3888. tdm_mode = TDM_TERT;
  3889. break;
  3890. case AFE_PORT_ID_QUATERNARY_TDM_RX:
  3891. case AFE_PORT_ID_QUATERNARY_TDM_TX:
  3892. tdm_mode = TDM_QUAT;
  3893. break;
  3894. case AFE_PORT_ID_QUINARY_TDM_RX:
  3895. case AFE_PORT_ID_QUINARY_TDM_TX:
  3896. tdm_mode = TDM_QUIN;
  3897. break;
  3898. case AFE_PORT_ID_SENARY_TDM_RX:
  3899. case AFE_PORT_ID_SENARY_TDM_TX:
  3900. tdm_mode = TDM_SEN;
  3901. break;
  3902. default:
  3903. pr_err("%s: Invalid port id: %d\n", __func__, port_id);
  3904. tdm_mode = -EINVAL;
  3905. }
  3906. return tdm_mode;
  3907. }
  3908. static int kona_tdm_snd_startup(struct snd_pcm_substream *substream)
  3909. {
  3910. int ret = 0;
  3911. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3912. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3913. struct snd_soc_card *card = rtd->card;
  3914. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3915. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3916. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3917. ret = -EINVAL;
  3918. pr_err("%s: Invalid TDM interface %d\n",
  3919. __func__, ret);
  3920. return ret;
  3921. }
  3922. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3923. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3924. == 0) {
  3925. ret = msm_cdc_pinctrl_select_active_state(
  3926. pdata->mi2s_gpio_p[tdm_mode]);
  3927. if (ret) {
  3928. pr_err("%s: TDM GPIO pinctrl set active failed with %d\n",
  3929. __func__, ret);
  3930. goto done;
  3931. }
  3932. }
  3933. atomic_inc(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3934. }
  3935. done:
  3936. return ret;
  3937. }
  3938. static void kona_tdm_snd_shutdown(struct snd_pcm_substream *substream)
  3939. {
  3940. int ret = 0;
  3941. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3942. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3943. struct snd_soc_card *card = rtd->card;
  3944. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3945. int tdm_mode = msm_get_tdm_mode(cpu_dai->id);
  3946. if (tdm_mode >= TDM_INTERFACE_MAX || tdm_mode < 0) {
  3947. ret = -EINVAL;
  3948. pr_err("%s: Invalid TDM interface %d\n",
  3949. __func__, ret);
  3950. return;
  3951. }
  3952. if (pdata->mi2s_gpio_p[tdm_mode]) {
  3953. atomic_dec(&(pdata->mi2s_gpio_ref_count[tdm_mode]));
  3954. if (atomic_read(&(pdata->mi2s_gpio_ref_count[tdm_mode]))
  3955. == 0) {
  3956. ret = msm_cdc_pinctrl_select_sleep_state(
  3957. pdata->mi2s_gpio_p[tdm_mode]);
  3958. if (ret)
  3959. pr_err("%s: TDM GPIO pinctrl set sleep failed with %d\n",
  3960. __func__, ret);
  3961. }
  3962. }
  3963. }
  3964. static int kona_aux_snd_startup(struct snd_pcm_substream *substream)
  3965. {
  3966. int ret = 0;
  3967. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3968. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3969. struct snd_soc_card *card = rtd->card;
  3970. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  3971. u32 aux_mode = cpu_dai->id - 1;
  3972. if (aux_mode >= AUX_PCM_MAX) {
  3973. ret = -EINVAL;
  3974. pr_err("%s: Invalid AUX interface %d\n",
  3975. __func__, ret);
  3976. return ret;
  3977. }
  3978. if (pdata->mi2s_gpio_p[aux_mode]) {
  3979. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  3980. == 0) {
  3981. ret = msm_cdc_pinctrl_select_active_state(
  3982. pdata->mi2s_gpio_p[aux_mode]);
  3983. if (ret) {
  3984. pr_err("%s: AUX GPIO pinctrl set active failed with %d\n",
  3985. __func__, ret);
  3986. goto done;
  3987. }
  3988. }
  3989. atomic_inc(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  3990. }
  3991. done:
  3992. return ret;
  3993. }
  3994. static void kona_aux_snd_shutdown(struct snd_pcm_substream *substream)
  3995. {
  3996. int ret = 0;
  3997. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  3998. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  3999. struct snd_soc_card *card = rtd->card;
  4000. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4001. u32 aux_mode = cpu_dai->id - 1;
  4002. if (aux_mode >= AUX_PCM_MAX) {
  4003. pr_err("%s: Invalid AUX interface %d\n",
  4004. __func__, ret);
  4005. return;
  4006. }
  4007. if (pdata->mi2s_gpio_p[aux_mode]) {
  4008. atomic_dec(&(pdata->mi2s_gpio_ref_count[aux_mode]));
  4009. if (atomic_read(&(pdata->mi2s_gpio_ref_count[aux_mode]))
  4010. == 0) {
  4011. ret = msm_cdc_pinctrl_select_sleep_state(
  4012. pdata->mi2s_gpio_p[aux_mode]);
  4013. if (ret)
  4014. pr_err("%s: AUX GPIO pinctrl set sleep failed with %d\n",
  4015. __func__, ret);
  4016. }
  4017. }
  4018. }
  4019. static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream)
  4020. {
  4021. int ret = 0;
  4022. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4023. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4024. switch (dai_link->id) {
  4025. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4026. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4027. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4028. ret = kona_send_island_va_config(dai_link->id);
  4029. if (ret)
  4030. pr_err("%s: send island va cfg failed, err: %d\n",
  4031. __func__, ret);
  4032. break;
  4033. }
  4034. return ret;
  4035. }
  4036. static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
  4037. struct snd_pcm_hw_params *params)
  4038. {
  4039. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4040. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4041. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4042. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4043. int ret = 0;
  4044. u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
  4045. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4046. u32 user_set_tx_ch = 0;
  4047. u32 user_set_rx_ch = 0;
  4048. u32 ch_id;
  4049. ret = snd_soc_dai_get_channel_map(codec_dai,
  4050. &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
  4051. &rx_ch_cdc_dma);
  4052. if (ret < 0) {
  4053. pr_err("%s: failed to get codec chan map, err:%d\n",
  4054. __func__, ret);
  4055. goto err;
  4056. }
  4057. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  4058. switch (dai_link->id) {
  4059. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
  4060. case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
  4061. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
  4062. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
  4063. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
  4064. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
  4065. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
  4066. case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
  4067. {
  4068. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4069. pr_debug("%s: id %d rx_ch=%d\n", __func__,
  4070. ch_id, cdc_dma_rx_cfg[ch_id].channels);
  4071. user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
  4072. ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
  4073. user_set_rx_ch, &rx_ch_cdc_dma);
  4074. if (ret < 0) {
  4075. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4076. __func__, ret);
  4077. goto err;
  4078. }
  4079. }
  4080. break;
  4081. }
  4082. } else {
  4083. switch (dai_link->id) {
  4084. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
  4085. {
  4086. user_set_tx_ch = msm_vi_feed_tx_ch;
  4087. }
  4088. break;
  4089. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
  4090. case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
  4091. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
  4092. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
  4093. case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
  4094. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0:
  4095. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_1:
  4096. case MSM_BACKEND_DAI_VA_CDC_DMA_TX_2:
  4097. {
  4098. ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
  4099. pr_debug("%s: id %d tx_ch=%d\n", __func__,
  4100. ch_id, cdc_dma_tx_cfg[ch_id].channels);
  4101. user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
  4102. }
  4103. break;
  4104. }
  4105. ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
  4106. &tx_ch_cdc_dma, 0, 0);
  4107. if (ret < 0) {
  4108. pr_err("%s: failed to set cpu chan map, err:%d\n",
  4109. __func__, ret);
  4110. goto err;
  4111. }
  4112. }
  4113. err:
  4114. return ret;
  4115. }
  4116. static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
  4117. {
  4118. cpumask_t mask;
  4119. if (pm_qos_request_active(&substream->latency_pm_qos_req))
  4120. pm_qos_remove_request(&substream->latency_pm_qos_req);
  4121. cpumask_clear(&mask);
  4122. cpumask_set_cpu(1, &mask); /* affine to core 1 */
  4123. cpumask_set_cpu(2, &mask); /* affine to core 2 */
  4124. cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
  4125. substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
  4126. pm_qos_add_request(&substream->latency_pm_qos_req,
  4127. PM_QOS_CPU_DMA_LATENCY,
  4128. MSM_LL_QOS_VALUE);
  4129. return 0;
  4130. }
  4131. static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
  4132. {
  4133. int ret = 0;
  4134. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4135. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4136. int index = cpu_dai->id;
  4137. unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
  4138. struct snd_soc_card *card = rtd->card;
  4139. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4140. dev_dbg(rtd->card->dev,
  4141. "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
  4142. __func__, substream->name, substream->stream,
  4143. cpu_dai->name, cpu_dai->id);
  4144. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4145. ret = -EINVAL;
  4146. dev_err(rtd->card->dev,
  4147. "%s: CPU DAI id (%d) out of range\n",
  4148. __func__, cpu_dai->id);
  4149. goto err;
  4150. }
  4151. /*
  4152. * Mutex protection in case the same MI2S
  4153. * interface using for both TX and RX so
  4154. * that the same clock won't be enable twice.
  4155. */
  4156. mutex_lock(&mi2s_intf_conf[index].lock);
  4157. if (++mi2s_intf_conf[index].ref_cnt == 1) {
  4158. /* Check if msm needs to provide the clock to the interface */
  4159. if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
  4160. mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
  4161. fmt = SND_SOC_DAIFMT_CBM_CFM;
  4162. }
  4163. ret = msm_mi2s_set_sclk(substream, true);
  4164. if (ret < 0) {
  4165. dev_err(rtd->card->dev,
  4166. "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
  4167. __func__, ret);
  4168. goto clean_up;
  4169. }
  4170. ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
  4171. if (ret < 0) {
  4172. pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
  4173. __func__, index, ret);
  4174. goto clk_off;
  4175. }
  4176. if (pdata->mi2s_gpio_p[index]) {
  4177. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4178. == 0) {
  4179. ret = msm_cdc_pinctrl_select_active_state(
  4180. pdata->mi2s_gpio_p[index]);
  4181. if (ret) {
  4182. pr_err("%s: MI2S GPIO pinctrl set active failed with %d\n",
  4183. __func__, ret);
  4184. goto clk_off;
  4185. }
  4186. }
  4187. atomic_inc(&(pdata->mi2s_gpio_ref_count[index]));
  4188. }
  4189. }
  4190. clk_off:
  4191. if (ret < 0)
  4192. msm_mi2s_set_sclk(substream, false);
  4193. clean_up:
  4194. if (ret < 0)
  4195. mi2s_intf_conf[index].ref_cnt--;
  4196. mutex_unlock(&mi2s_intf_conf[index].lock);
  4197. err:
  4198. return ret;
  4199. }
  4200. static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
  4201. {
  4202. int ret = 0;
  4203. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4204. int index = rtd->cpu_dai->id;
  4205. struct snd_soc_card *card = rtd->card;
  4206. struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
  4207. pr_debug("%s(): substream = %s stream = %d\n", __func__,
  4208. substream->name, substream->stream);
  4209. if (index < PRIM_MI2S || index >= MI2S_MAX) {
  4210. pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
  4211. return;
  4212. }
  4213. mutex_lock(&mi2s_intf_conf[index].lock);
  4214. if (--mi2s_intf_conf[index].ref_cnt == 0) {
  4215. if (pdata->mi2s_gpio_p[index]) {
  4216. atomic_dec(&(pdata->mi2s_gpio_ref_count[index]));
  4217. if (atomic_read(&(pdata->mi2s_gpio_ref_count[index]))
  4218. == 0) {
  4219. ret = msm_cdc_pinctrl_select_sleep_state(
  4220. pdata->mi2s_gpio_p[index]);
  4221. if (ret)
  4222. pr_err("%s: MI2S GPIO pinctrl set sleep failed with %d\n",
  4223. __func__, ret);
  4224. }
  4225. }
  4226. ret = msm_mi2s_set_sclk(substream, false);
  4227. if (ret < 0)
  4228. pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
  4229. __func__, index, ret);
  4230. }
  4231. mutex_unlock(&mi2s_intf_conf[index].lock);
  4232. }
  4233. static int msm_wcn_hw_params_lito(struct snd_pcm_substream *substream,
  4234. struct snd_pcm_hw_params *params)
  4235. {
  4236. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4237. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4238. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4239. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4240. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO];
  4241. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4242. int ret = 0;
  4243. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4244. codec_dai->name, codec_dai->id);
  4245. ret = snd_soc_dai_get_channel_map(codec_dai,
  4246. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4247. if (ret) {
  4248. dev_err(rtd->dev,
  4249. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4250. __func__, ret);
  4251. goto err;
  4252. }
  4253. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4254. __func__, tx_ch_cnt, dai_link->id);
  4255. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4256. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4257. if (ret)
  4258. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4259. __func__, ret);
  4260. err:
  4261. return ret;
  4262. }
  4263. static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
  4264. struct snd_pcm_hw_params *params)
  4265. {
  4266. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  4267. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4268. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  4269. struct snd_soc_dai_link *dai_link = rtd->dai_link;
  4270. u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
  4271. u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
  4272. int ret = 0;
  4273. dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
  4274. codec_dai->name, codec_dai->id);
  4275. ret = snd_soc_dai_get_channel_map(codec_dai,
  4276. &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
  4277. if (ret) {
  4278. dev_err(rtd->dev,
  4279. "%s: failed to get BTFM codec chan map\n, err:%d\n",
  4280. __func__, ret);
  4281. goto err;
  4282. }
  4283. dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
  4284. __func__, tx_ch_cnt, dai_link->id);
  4285. ret = snd_soc_dai_set_channel_map(cpu_dai,
  4286. tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
  4287. if (ret)
  4288. dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
  4289. __func__, ret);
  4290. err:
  4291. return ret;
  4292. }
  4293. static struct snd_soc_ops kona_aux_be_ops = {
  4294. .startup = kona_aux_snd_startup,
  4295. .shutdown = kona_aux_snd_shutdown
  4296. };
  4297. static struct snd_soc_ops kona_tdm_be_ops = {
  4298. .hw_params = kona_tdm_snd_hw_params,
  4299. .startup = kona_tdm_snd_startup,
  4300. .shutdown = kona_tdm_snd_shutdown
  4301. };
  4302. static struct snd_soc_ops msm_mi2s_be_ops = {
  4303. .startup = msm_mi2s_snd_startup,
  4304. .shutdown = msm_mi2s_snd_shutdown,
  4305. };
  4306. static struct snd_soc_ops msm_fe_qos_ops = {
  4307. .prepare = msm_fe_qos_prepare,
  4308. };
  4309. static struct snd_soc_ops msm_cdc_dma_be_ops = {
  4310. .startup = msm_snd_cdc_dma_startup,
  4311. .hw_params = msm_snd_cdc_dma_hw_params,
  4312. };
  4313. static struct snd_soc_ops msm_wcn_ops = {
  4314. .hw_params = msm_wcn_hw_params,
  4315. };
  4316. static struct snd_soc_ops msm_wcn_ops_lito = {
  4317. .hw_params = msm_wcn_hw_params_lito,
  4318. };
  4319. static int msm_dmic_event(struct snd_soc_dapm_widget *w,
  4320. struct snd_kcontrol *kcontrol, int event)
  4321. {
  4322. struct msm_asoc_mach_data *pdata = NULL;
  4323. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  4324. int ret = 0;
  4325. u32 dmic_idx;
  4326. int *dmic_gpio_cnt;
  4327. struct device_node *dmic_gpio;
  4328. char *wname;
  4329. wname = strpbrk(w->name, "012345");
  4330. if (!wname) {
  4331. dev_err(component->dev, "%s: widget not found\n", __func__);
  4332. return -EINVAL;
  4333. }
  4334. ret = kstrtouint(wname, 10, &dmic_idx);
  4335. if (ret < 0) {
  4336. dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
  4337. __func__);
  4338. return -EINVAL;
  4339. }
  4340. pdata = snd_soc_card_get_drvdata(component->card);
  4341. switch (dmic_idx) {
  4342. case 0:
  4343. case 1:
  4344. dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
  4345. dmic_gpio = pdata->dmic01_gpio_p;
  4346. break;
  4347. case 2:
  4348. case 3:
  4349. dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
  4350. dmic_gpio = pdata->dmic23_gpio_p;
  4351. break;
  4352. case 4:
  4353. case 5:
  4354. dmic_gpio_cnt = &dmic_4_5_gpio_cnt;
  4355. dmic_gpio = pdata->dmic45_gpio_p;
  4356. break;
  4357. default:
  4358. dev_err(component->dev, "%s: Invalid DMIC Selection\n",
  4359. __func__);
  4360. return -EINVAL;
  4361. }
  4362. dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
  4363. __func__, event, dmic_idx, *dmic_gpio_cnt);
  4364. switch (event) {
  4365. case SND_SOC_DAPM_PRE_PMU:
  4366. (*dmic_gpio_cnt)++;
  4367. if (*dmic_gpio_cnt == 1) {
  4368. ret = msm_cdc_pinctrl_select_active_state(
  4369. dmic_gpio);
  4370. if (ret < 0) {
  4371. pr_err("%s: gpio set cannot be activated %sd",
  4372. __func__, "dmic_gpio");
  4373. return ret;
  4374. }
  4375. }
  4376. break;
  4377. case SND_SOC_DAPM_POST_PMD:
  4378. (*dmic_gpio_cnt)--;
  4379. if (*dmic_gpio_cnt == 0) {
  4380. ret = msm_cdc_pinctrl_select_sleep_state(
  4381. dmic_gpio);
  4382. if (ret < 0) {
  4383. pr_err("%s: gpio set cannot be de-activated %sd",
  4384. __func__, "dmic_gpio");
  4385. return ret;
  4386. }
  4387. }
  4388. break;
  4389. default:
  4390. pr_err("%s: invalid DAPM event %d\n", __func__, event);
  4391. return -EINVAL;
  4392. }
  4393. return 0;
  4394. }
  4395. static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
  4396. SND_SOC_DAPM_MIC("Analog Mic1", NULL),
  4397. SND_SOC_DAPM_MIC("Analog Mic2", NULL),
  4398. SND_SOC_DAPM_MIC("Analog Mic3", NULL),
  4399. SND_SOC_DAPM_MIC("Analog Mic4", NULL),
  4400. SND_SOC_DAPM_MIC("Analog Mic5", NULL),
  4401. SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
  4402. SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
  4403. SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
  4404. SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
  4405. SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event),
  4406. SND_SOC_DAPM_MIC("Digital Mic5", msm_dmic_event),
  4407. };
  4408. static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
  4409. {
  4410. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4411. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160};
  4412. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4413. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4414. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4415. }
  4416. static int msm_wcn_init_lito(struct snd_soc_pcm_runtime *rtd)
  4417. {
  4418. unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
  4419. unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX_LITO] = {159, 160, 161};
  4420. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  4421. return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
  4422. tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
  4423. }
  4424. static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
  4425. {
  4426. int ret = -EINVAL;
  4427. struct snd_soc_component *component;
  4428. struct snd_soc_dapm_context *dapm;
  4429. struct snd_card *card;
  4430. struct snd_info_entry *entry;
  4431. struct snd_soc_component *aux_comp;
  4432. struct msm_asoc_mach_data *pdata =
  4433. snd_soc_card_get_drvdata(rtd->card);
  4434. component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
  4435. if (!component) {
  4436. pr_err("%s: could not find component for bolero_codec\n",
  4437. __func__);
  4438. return ret;
  4439. }
  4440. dapm = snd_soc_component_get_dapm(component);
  4441. ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
  4442. ARRAY_SIZE(msm_int_snd_controls));
  4443. if (ret < 0) {
  4444. pr_err("%s: add_component_controls failed: %d\n",
  4445. __func__, ret);
  4446. return ret;
  4447. }
  4448. ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
  4449. ARRAY_SIZE(msm_common_snd_controls));
  4450. if (ret < 0) {
  4451. pr_err("%s: add common snd controls failed: %d\n",
  4452. __func__, ret);
  4453. return ret;
  4454. }
  4455. snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
  4456. ARRAY_SIZE(msm_int_dapm_widgets));
  4457. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
  4458. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
  4459. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
  4460. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
  4461. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
  4462. snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
  4463. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
  4464. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
  4465. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
  4466. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
  4467. snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
  4468. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
  4469. snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
  4470. snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
  4471. snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
  4472. snd_soc_dapm_sync(dapm);
  4473. /*
  4474. * Send speaker configuration only for WSA8810.
  4475. * Default configuration is for WSA8815.
  4476. */
  4477. dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
  4478. __func__, rtd->card->num_aux_devs);
  4479. if (rtd->card->num_aux_devs &&
  4480. !list_empty(&rtd->card->component_dev_list)) {
  4481. aux_comp = list_first_entry(
  4482. &rtd->card->component_dev_list,
  4483. struct snd_soc_component,
  4484. card_aux_list);
  4485. if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
  4486. !strcmp(aux_comp->name, WSA8810_NAME_2)) {
  4487. wsa_macro_set_spkr_mode(component,
  4488. WSA_MACRO_SPKR_MODE_1);
  4489. wsa_macro_set_spkr_gain_offset(component,
  4490. WSA_MACRO_GAIN_OFFSET_M1P5_DB);
  4491. }
  4492. bolero_set_port_map(component, ARRAY_SIZE(sm_port_map),
  4493. sm_port_map);
  4494. }
  4495. card = rtd->card->snd_card;
  4496. if (!pdata->codec_root) {
  4497. entry = snd_info_create_subdir(card->module, "codecs",
  4498. card->proc_root);
  4499. if (!entry) {
  4500. pr_debug("%s: Cannot create codecs module entry\n",
  4501. __func__);
  4502. ret = 0;
  4503. goto err;
  4504. }
  4505. pdata->codec_root = entry;
  4506. }
  4507. bolero_info_create_codec_entry(pdata->codec_root, component);
  4508. bolero_register_wake_irq(component, false);
  4509. codec_reg_done = true;
  4510. return 0;
  4511. err:
  4512. return ret;
  4513. }
  4514. static void *def_wcd_mbhc_cal(void)
  4515. {
  4516. void *wcd_mbhc_cal;
  4517. struct wcd_mbhc_btn_detect_cfg *btn_cfg;
  4518. u16 *btn_high;
  4519. wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
  4520. WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
  4521. if (!wcd_mbhc_cal)
  4522. return NULL;
  4523. WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->v_hs_max = WCD_MBHC_HS_V_MAX;
  4524. WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->num_btn = WCD_MBHC_DEF_BUTTONS;
  4525. btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
  4526. btn_high = ((void *)&btn_cfg->_v_btn_low) +
  4527. (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
  4528. btn_high[0] = 75;
  4529. btn_high[1] = 150;
  4530. btn_high[2] = 237;
  4531. btn_high[3] = 500;
  4532. btn_high[4] = 500;
  4533. btn_high[5] = 500;
  4534. btn_high[6] = 500;
  4535. btn_high[7] = 500;
  4536. return wcd_mbhc_cal;
  4537. }
  4538. /* Digital audio interface glue - connects codec <---> CPU */
  4539. static struct snd_soc_dai_link msm_common_dai_links[] = {
  4540. /* FrontEnd DAI Links */
  4541. {/* hw:x,0 */
  4542. .name = MSM_DAILINK_NAME(Media1),
  4543. .stream_name = "MultiMedia1",
  4544. .cpu_dai_name = "MultiMedia1",
  4545. .platform_name = "msm-pcm-dsp.0",
  4546. .dynamic = 1,
  4547. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4548. .dpcm_playback = 1,
  4549. .dpcm_capture = 1,
  4550. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4551. SND_SOC_DPCM_TRIGGER_POST},
  4552. .codec_dai_name = "snd-soc-dummy-dai",
  4553. .codec_name = "snd-soc-dummy",
  4554. .ignore_suspend = 1,
  4555. /* this dainlink has playback support */
  4556. .ignore_pmdown_time = 1,
  4557. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  4558. },
  4559. {/* hw:x,1 */
  4560. .name = MSM_DAILINK_NAME(Media2),
  4561. .stream_name = "MultiMedia2",
  4562. .cpu_dai_name = "MultiMedia2",
  4563. .platform_name = "msm-pcm-dsp.0",
  4564. .dynamic = 1,
  4565. .dpcm_playback = 1,
  4566. .dpcm_capture = 1,
  4567. .codec_dai_name = "snd-soc-dummy-dai",
  4568. .codec_name = "snd-soc-dummy",
  4569. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4570. SND_SOC_DPCM_TRIGGER_POST},
  4571. .ignore_suspend = 1,
  4572. /* this dainlink has playback support */
  4573. .ignore_pmdown_time = 1,
  4574. .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
  4575. },
  4576. {/* hw:x,2 */
  4577. .name = "VoiceMMode1",
  4578. .stream_name = "VoiceMMode1",
  4579. .cpu_dai_name = "VoiceMMode1",
  4580. .platform_name = "msm-pcm-voice",
  4581. .dynamic = 1,
  4582. .dpcm_playback = 1,
  4583. .dpcm_capture = 1,
  4584. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4585. SND_SOC_DPCM_TRIGGER_POST},
  4586. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4587. .ignore_suspend = 1,
  4588. .ignore_pmdown_time = 1,
  4589. .codec_dai_name = "snd-soc-dummy-dai",
  4590. .codec_name = "snd-soc-dummy",
  4591. .id = MSM_FRONTEND_DAI_VOICEMMODE1,
  4592. },
  4593. {/* hw:x,3 */
  4594. .name = "MSM VoIP",
  4595. .stream_name = "VoIP",
  4596. .cpu_dai_name = "VoIP",
  4597. .platform_name = "msm-voip-dsp",
  4598. .dynamic = 1,
  4599. .dpcm_playback = 1,
  4600. .dpcm_capture = 1,
  4601. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4602. SND_SOC_DPCM_TRIGGER_POST},
  4603. .codec_dai_name = "snd-soc-dummy-dai",
  4604. .codec_name = "snd-soc-dummy",
  4605. .ignore_suspend = 1,
  4606. /* this dainlink has playback support */
  4607. .ignore_pmdown_time = 1,
  4608. .id = MSM_FRONTEND_DAI_VOIP,
  4609. },
  4610. {/* hw:x,4 */
  4611. .name = MSM_DAILINK_NAME(ULL),
  4612. .stream_name = "MultiMedia3",
  4613. .cpu_dai_name = "MultiMedia3",
  4614. .platform_name = "msm-pcm-dsp.2",
  4615. .dynamic = 1,
  4616. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4617. .dpcm_playback = 1,
  4618. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4619. SND_SOC_DPCM_TRIGGER_POST},
  4620. .codec_dai_name = "snd-soc-dummy-dai",
  4621. .codec_name = "snd-soc-dummy",
  4622. .ignore_suspend = 1,
  4623. /* this dainlink has playback support */
  4624. .ignore_pmdown_time = 1,
  4625. .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
  4626. },
  4627. {/* hw:x,5 */
  4628. .name = "MSM AFE-PCM RX",
  4629. .stream_name = "AFE-PROXY RX",
  4630. .cpu_dai_name = "msm-dai-q6-dev.241",
  4631. .codec_name = "msm-stub-codec.1",
  4632. .codec_dai_name = "msm-stub-rx",
  4633. .platform_name = "msm-pcm-afe",
  4634. .dpcm_playback = 1,
  4635. .ignore_suspend = 1,
  4636. /* this dainlink has playback support */
  4637. .ignore_pmdown_time = 1,
  4638. },
  4639. {/* hw:x,6 */
  4640. .name = "MSM AFE-PCM TX",
  4641. .stream_name = "AFE-PROXY TX",
  4642. .cpu_dai_name = "msm-dai-q6-dev.240",
  4643. .codec_name = "msm-stub-codec.1",
  4644. .codec_dai_name = "msm-stub-tx",
  4645. .platform_name = "msm-pcm-afe",
  4646. .dpcm_capture = 1,
  4647. .ignore_suspend = 1,
  4648. },
  4649. {/* hw:x,7 */
  4650. .name = MSM_DAILINK_NAME(Compress1),
  4651. .stream_name = "Compress1",
  4652. .cpu_dai_name = "MultiMedia4",
  4653. .platform_name = "msm-compress-dsp",
  4654. .dynamic = 1,
  4655. .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
  4656. .dpcm_playback = 1,
  4657. .dpcm_capture = 1,
  4658. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4659. SND_SOC_DPCM_TRIGGER_POST},
  4660. .codec_dai_name = "snd-soc-dummy-dai",
  4661. .codec_name = "snd-soc-dummy",
  4662. .ignore_suspend = 1,
  4663. .ignore_pmdown_time = 1,
  4664. /* this dainlink has playback support */
  4665. .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
  4666. },
  4667. /* Hostless PCM purpose */
  4668. {/* hw:x,8 */
  4669. .name = "AUXPCM Hostless",
  4670. .stream_name = "AUXPCM Hostless",
  4671. .cpu_dai_name = "AUXPCM_HOSTLESS",
  4672. .platform_name = "msm-pcm-hostless",
  4673. .dynamic = 1,
  4674. .dpcm_playback = 1,
  4675. .dpcm_capture = 1,
  4676. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4677. SND_SOC_DPCM_TRIGGER_POST},
  4678. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4679. .ignore_suspend = 1,
  4680. /* this dainlink has playback support */
  4681. .ignore_pmdown_time = 1,
  4682. .codec_dai_name = "snd-soc-dummy-dai",
  4683. .codec_name = "snd-soc-dummy",
  4684. },
  4685. {/* hw:x,9 */
  4686. .name = MSM_DAILINK_NAME(LowLatency),
  4687. .stream_name = "MultiMedia5",
  4688. .cpu_dai_name = "MultiMedia5",
  4689. .platform_name = "msm-pcm-dsp.1",
  4690. .dynamic = 1,
  4691. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  4692. .dpcm_playback = 1,
  4693. .dpcm_capture = 1,
  4694. .codec_dai_name = "snd-soc-dummy-dai",
  4695. .codec_name = "snd-soc-dummy",
  4696. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4697. SND_SOC_DPCM_TRIGGER_POST},
  4698. .ignore_suspend = 1,
  4699. /* this dainlink has playback support */
  4700. .ignore_pmdown_time = 1,
  4701. .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
  4702. .ops = &msm_fe_qos_ops,
  4703. },
  4704. {/* hw:x,10 */
  4705. .name = "Listen 1 Audio Service",
  4706. .stream_name = "Listen 1 Audio Service",
  4707. .cpu_dai_name = "LSM1",
  4708. .platform_name = "msm-lsm-client",
  4709. .dynamic = 1,
  4710. .dpcm_capture = 1,
  4711. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4712. SND_SOC_DPCM_TRIGGER_POST },
  4713. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4714. .ignore_suspend = 1,
  4715. .codec_dai_name = "snd-soc-dummy-dai",
  4716. .codec_name = "snd-soc-dummy",
  4717. .id = MSM_FRONTEND_DAI_LSM1,
  4718. },
  4719. /* Multiple Tunnel instances */
  4720. {/* hw:x,11 */
  4721. .name = MSM_DAILINK_NAME(Compress2),
  4722. .stream_name = "Compress2",
  4723. .cpu_dai_name = "MultiMedia7",
  4724. .platform_name = "msm-compress-dsp",
  4725. .dynamic = 1,
  4726. .dpcm_playback = 1,
  4727. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4728. SND_SOC_DPCM_TRIGGER_POST},
  4729. .codec_dai_name = "snd-soc-dummy-dai",
  4730. .codec_name = "snd-soc-dummy",
  4731. .ignore_suspend = 1,
  4732. .ignore_pmdown_time = 1,
  4733. /* this dainlink has playback support */
  4734. .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
  4735. },
  4736. {/* hw:x,12 */
  4737. .name = MSM_DAILINK_NAME(MultiMedia10),
  4738. .stream_name = "MultiMedia10",
  4739. .cpu_dai_name = "MultiMedia10",
  4740. .platform_name = "msm-pcm-dsp.1",
  4741. .dynamic = 1,
  4742. .dpcm_playback = 1,
  4743. .dpcm_capture = 1,
  4744. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4745. SND_SOC_DPCM_TRIGGER_POST},
  4746. .codec_dai_name = "snd-soc-dummy-dai",
  4747. .codec_name = "snd-soc-dummy",
  4748. .ignore_suspend = 1,
  4749. .ignore_pmdown_time = 1,
  4750. /* this dainlink has playback support */
  4751. .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
  4752. },
  4753. {/* hw:x,13 */
  4754. .name = MSM_DAILINK_NAME(ULL_NOIRQ),
  4755. .stream_name = "MM_NOIRQ",
  4756. .cpu_dai_name = "MultiMedia8",
  4757. .platform_name = "msm-pcm-dsp-noirq",
  4758. .dynamic = 1,
  4759. .dpcm_playback = 1,
  4760. .dpcm_capture = 1,
  4761. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4762. SND_SOC_DPCM_TRIGGER_POST},
  4763. .codec_dai_name = "snd-soc-dummy-dai",
  4764. .codec_name = "snd-soc-dummy",
  4765. .ignore_suspend = 1,
  4766. .ignore_pmdown_time = 1,
  4767. /* this dainlink has playback support */
  4768. .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
  4769. .ops = &msm_fe_qos_ops,
  4770. },
  4771. /* HDMI Hostless */
  4772. {/* hw:x,14 */
  4773. .name = "HDMI_RX_HOSTLESS",
  4774. .stream_name = "HDMI_RX_HOSTLESS",
  4775. .cpu_dai_name = "HDMI_HOSTLESS",
  4776. .platform_name = "msm-pcm-hostless",
  4777. .dynamic = 1,
  4778. .dpcm_playback = 1,
  4779. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4780. SND_SOC_DPCM_TRIGGER_POST},
  4781. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4782. .ignore_suspend = 1,
  4783. .ignore_pmdown_time = 1,
  4784. .codec_dai_name = "snd-soc-dummy-dai",
  4785. .codec_name = "snd-soc-dummy",
  4786. },
  4787. {/* hw:x,15 */
  4788. .name = "VoiceMMode2",
  4789. .stream_name = "VoiceMMode2",
  4790. .cpu_dai_name = "VoiceMMode2",
  4791. .platform_name = "msm-pcm-voice",
  4792. .dynamic = 1,
  4793. .dpcm_playback = 1,
  4794. .dpcm_capture = 1,
  4795. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4796. SND_SOC_DPCM_TRIGGER_POST},
  4797. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4798. .ignore_suspend = 1,
  4799. .ignore_pmdown_time = 1,
  4800. .codec_dai_name = "snd-soc-dummy-dai",
  4801. .codec_name = "snd-soc-dummy",
  4802. .id = MSM_FRONTEND_DAI_VOICEMMODE2,
  4803. },
  4804. /* LSM FE */
  4805. {/* hw:x,16 */
  4806. .name = "Listen 2 Audio Service",
  4807. .stream_name = "Listen 2 Audio Service",
  4808. .cpu_dai_name = "LSM2",
  4809. .platform_name = "msm-lsm-client",
  4810. .dynamic = 1,
  4811. .dpcm_capture = 1,
  4812. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4813. SND_SOC_DPCM_TRIGGER_POST },
  4814. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4815. .ignore_suspend = 1,
  4816. .codec_dai_name = "snd-soc-dummy-dai",
  4817. .codec_name = "snd-soc-dummy",
  4818. .id = MSM_FRONTEND_DAI_LSM2,
  4819. },
  4820. {/* hw:x,17 */
  4821. .name = "Listen 3 Audio Service",
  4822. .stream_name = "Listen 3 Audio Service",
  4823. .cpu_dai_name = "LSM3",
  4824. .platform_name = "msm-lsm-client",
  4825. .dynamic = 1,
  4826. .dpcm_capture = 1,
  4827. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4828. SND_SOC_DPCM_TRIGGER_POST },
  4829. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4830. .ignore_suspend = 1,
  4831. .codec_dai_name = "snd-soc-dummy-dai",
  4832. .codec_name = "snd-soc-dummy",
  4833. .id = MSM_FRONTEND_DAI_LSM3,
  4834. },
  4835. {/* hw:x,18 */
  4836. .name = "Listen 4 Audio Service",
  4837. .stream_name = "Listen 4 Audio Service",
  4838. .cpu_dai_name = "LSM4",
  4839. .platform_name = "msm-lsm-client",
  4840. .dynamic = 1,
  4841. .dpcm_capture = 1,
  4842. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4843. SND_SOC_DPCM_TRIGGER_POST },
  4844. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4845. .ignore_suspend = 1,
  4846. .codec_dai_name = "snd-soc-dummy-dai",
  4847. .codec_name = "snd-soc-dummy",
  4848. .id = MSM_FRONTEND_DAI_LSM4,
  4849. },
  4850. {/* hw:x,19 */
  4851. .name = "Listen 5 Audio Service",
  4852. .stream_name = "Listen 5 Audio Service",
  4853. .cpu_dai_name = "LSM5",
  4854. .platform_name = "msm-lsm-client",
  4855. .dynamic = 1,
  4856. .dpcm_capture = 1,
  4857. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4858. SND_SOC_DPCM_TRIGGER_POST },
  4859. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4860. .ignore_suspend = 1,
  4861. .codec_dai_name = "snd-soc-dummy-dai",
  4862. .codec_name = "snd-soc-dummy",
  4863. .id = MSM_FRONTEND_DAI_LSM5,
  4864. },
  4865. {/* hw:x,20 */
  4866. .name = "Listen 6 Audio Service",
  4867. .stream_name = "Listen 6 Audio Service",
  4868. .cpu_dai_name = "LSM6",
  4869. .platform_name = "msm-lsm-client",
  4870. .dynamic = 1,
  4871. .dpcm_capture = 1,
  4872. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4873. SND_SOC_DPCM_TRIGGER_POST },
  4874. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4875. .ignore_suspend = 1,
  4876. .codec_dai_name = "snd-soc-dummy-dai",
  4877. .codec_name = "snd-soc-dummy",
  4878. .id = MSM_FRONTEND_DAI_LSM6,
  4879. },
  4880. {/* hw:x,21 */
  4881. .name = "Listen 7 Audio Service",
  4882. .stream_name = "Listen 7 Audio Service",
  4883. .cpu_dai_name = "LSM7",
  4884. .platform_name = "msm-lsm-client",
  4885. .dynamic = 1,
  4886. .dpcm_capture = 1,
  4887. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4888. SND_SOC_DPCM_TRIGGER_POST },
  4889. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4890. .ignore_suspend = 1,
  4891. .codec_dai_name = "snd-soc-dummy-dai",
  4892. .codec_name = "snd-soc-dummy",
  4893. .id = MSM_FRONTEND_DAI_LSM7,
  4894. },
  4895. {/* hw:x,22 */
  4896. .name = "Listen 8 Audio Service",
  4897. .stream_name = "Listen 8 Audio Service",
  4898. .cpu_dai_name = "LSM8",
  4899. .platform_name = "msm-lsm-client",
  4900. .dynamic = 1,
  4901. .dpcm_capture = 1,
  4902. .trigger = { SND_SOC_DPCM_TRIGGER_POST,
  4903. SND_SOC_DPCM_TRIGGER_POST },
  4904. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  4905. .ignore_suspend = 1,
  4906. .codec_dai_name = "snd-soc-dummy-dai",
  4907. .codec_name = "snd-soc-dummy",
  4908. .id = MSM_FRONTEND_DAI_LSM8,
  4909. },
  4910. {/* hw:x,23 */
  4911. .name = MSM_DAILINK_NAME(Media9),
  4912. .stream_name = "MultiMedia9",
  4913. .cpu_dai_name = "MultiMedia9",
  4914. .platform_name = "msm-pcm-dsp.0",
  4915. .dynamic = 1,
  4916. .dpcm_playback = 1,
  4917. .dpcm_capture = 1,
  4918. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4919. SND_SOC_DPCM_TRIGGER_POST},
  4920. .codec_dai_name = "snd-soc-dummy-dai",
  4921. .codec_name = "snd-soc-dummy",
  4922. .ignore_suspend = 1,
  4923. /* this dainlink has playback support */
  4924. .ignore_pmdown_time = 1,
  4925. .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
  4926. },
  4927. {/* hw:x,24 */
  4928. .name = MSM_DAILINK_NAME(Compress4),
  4929. .stream_name = "Compress4",
  4930. .cpu_dai_name = "MultiMedia11",
  4931. .platform_name = "msm-compress-dsp",
  4932. .dynamic = 1,
  4933. .dpcm_playback = 1,
  4934. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4935. SND_SOC_DPCM_TRIGGER_POST},
  4936. .codec_dai_name = "snd-soc-dummy-dai",
  4937. .codec_name = "snd-soc-dummy",
  4938. .ignore_suspend = 1,
  4939. .ignore_pmdown_time = 1,
  4940. /* this dainlink has playback support */
  4941. .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
  4942. },
  4943. {/* hw:x,25 */
  4944. .name = MSM_DAILINK_NAME(Compress5),
  4945. .stream_name = "Compress5",
  4946. .cpu_dai_name = "MultiMedia12",
  4947. .platform_name = "msm-compress-dsp",
  4948. .dynamic = 1,
  4949. .dpcm_playback = 1,
  4950. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4951. SND_SOC_DPCM_TRIGGER_POST},
  4952. .codec_dai_name = "snd-soc-dummy-dai",
  4953. .codec_name = "snd-soc-dummy",
  4954. .ignore_suspend = 1,
  4955. .ignore_pmdown_time = 1,
  4956. /* this dainlink has playback support */
  4957. .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
  4958. },
  4959. {/* hw:x,26 */
  4960. .name = MSM_DAILINK_NAME(Compress6),
  4961. .stream_name = "Compress6",
  4962. .cpu_dai_name = "MultiMedia13",
  4963. .platform_name = "msm-compress-dsp",
  4964. .dynamic = 1,
  4965. .dpcm_playback = 1,
  4966. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4967. SND_SOC_DPCM_TRIGGER_POST},
  4968. .codec_dai_name = "snd-soc-dummy-dai",
  4969. .codec_name = "snd-soc-dummy",
  4970. .ignore_suspend = 1,
  4971. .ignore_pmdown_time = 1,
  4972. /* this dainlink has playback support */
  4973. .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
  4974. },
  4975. {/* hw:x,27 */
  4976. .name = MSM_DAILINK_NAME(Compress7),
  4977. .stream_name = "Compress7",
  4978. .cpu_dai_name = "MultiMedia14",
  4979. .platform_name = "msm-compress-dsp",
  4980. .dynamic = 1,
  4981. .dpcm_playback = 1,
  4982. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4983. SND_SOC_DPCM_TRIGGER_POST},
  4984. .codec_dai_name = "snd-soc-dummy-dai",
  4985. .codec_name = "snd-soc-dummy",
  4986. .ignore_suspend = 1,
  4987. .ignore_pmdown_time = 1,
  4988. /* this dainlink has playback support */
  4989. .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
  4990. },
  4991. {/* hw:x,28 */
  4992. .name = MSM_DAILINK_NAME(Compress8),
  4993. .stream_name = "Compress8",
  4994. .cpu_dai_name = "MultiMedia15",
  4995. .platform_name = "msm-compress-dsp",
  4996. .dynamic = 1,
  4997. .dpcm_playback = 1,
  4998. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  4999. SND_SOC_DPCM_TRIGGER_POST},
  5000. .codec_dai_name = "snd-soc-dummy-dai",
  5001. .codec_name = "snd-soc-dummy",
  5002. .ignore_suspend = 1,
  5003. .ignore_pmdown_time = 1,
  5004. /* this dainlink has playback support */
  5005. .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
  5006. },
  5007. {/* hw:x,29 */
  5008. .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
  5009. .stream_name = "MM_NOIRQ_2",
  5010. .cpu_dai_name = "MultiMedia16",
  5011. .platform_name = "msm-pcm-dsp-noirq",
  5012. .dynamic = 1,
  5013. .dpcm_playback = 1,
  5014. .dpcm_capture = 1,
  5015. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5016. SND_SOC_DPCM_TRIGGER_POST},
  5017. .codec_dai_name = "snd-soc-dummy-dai",
  5018. .codec_name = "snd-soc-dummy",
  5019. .ignore_suspend = 1,
  5020. .ignore_pmdown_time = 1,
  5021. /* this dainlink has playback support */
  5022. .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
  5023. },
  5024. {/* hw:x,30 */
  5025. .name = "CDC_DMA Hostless",
  5026. .stream_name = "CDC_DMA Hostless",
  5027. .cpu_dai_name = "CDC_DMA_HOSTLESS",
  5028. .platform_name = "msm-pcm-hostless",
  5029. .dynamic = 1,
  5030. .dpcm_playback = 1,
  5031. .dpcm_capture = 1,
  5032. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5033. SND_SOC_DPCM_TRIGGER_POST},
  5034. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5035. .ignore_suspend = 1,
  5036. /* this dailink has playback support */
  5037. .ignore_pmdown_time = 1,
  5038. .codec_dai_name = "snd-soc-dummy-dai",
  5039. .codec_name = "snd-soc-dummy",
  5040. },
  5041. {/* hw:x,31 */
  5042. .name = "TX3_CDC_DMA Hostless",
  5043. .stream_name = "TX3_CDC_DMA Hostless",
  5044. .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
  5045. .platform_name = "msm-pcm-hostless",
  5046. .dynamic = 1,
  5047. .dpcm_capture = 1,
  5048. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5049. SND_SOC_DPCM_TRIGGER_POST},
  5050. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5051. .ignore_suspend = 1,
  5052. .codec_dai_name = "snd-soc-dummy-dai",
  5053. .codec_name = "snd-soc-dummy",
  5054. },
  5055. {/* hw:x,32 */
  5056. .name = "Tertiary MI2S TX_Hostless",
  5057. .stream_name = "Tertiary MI2S_TX Hostless Capture",
  5058. .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
  5059. .platform_name = "msm-pcm-hostless",
  5060. .dynamic = 1,
  5061. .dpcm_capture = 1,
  5062. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5063. SND_SOC_DPCM_TRIGGER_POST},
  5064. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5065. .ignore_suspend = 1,
  5066. .ignore_pmdown_time = 1,
  5067. .codec_dai_name = "snd-soc-dummy-dai",
  5068. .codec_name = "snd-soc-dummy",
  5069. },
  5070. };
  5071. static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
  5072. {/* hw:x,33 */
  5073. .name = LPASS_BE_WSA_CDC_DMA_TX_0,
  5074. .stream_name = "WSA CDC DMA0 Capture",
  5075. .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
  5076. .platform_name = "msm-pcm-hostless",
  5077. .codec_name = "bolero_codec",
  5078. .codec_dai_name = "wsa_macro_vifeedback",
  5079. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
  5080. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5081. .ignore_suspend = 1,
  5082. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5083. .ops = &msm_cdc_dma_be_ops,
  5084. },
  5085. };
  5086. static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
  5087. {/* hw:x,34 */
  5088. .name = MSM_DAILINK_NAME(ASM Loopback),
  5089. .stream_name = "MultiMedia6",
  5090. .cpu_dai_name = "MultiMedia6",
  5091. .platform_name = "msm-pcm-loopback",
  5092. .dynamic = 1,
  5093. .dpcm_playback = 1,
  5094. .dpcm_capture = 1,
  5095. .codec_dai_name = "snd-soc-dummy-dai",
  5096. .codec_name = "snd-soc-dummy",
  5097. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5098. SND_SOC_DPCM_TRIGGER_POST},
  5099. .ignore_suspend = 1,
  5100. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5101. .ignore_pmdown_time = 1,
  5102. .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
  5103. },
  5104. {/* hw:x,35 */
  5105. .name = "USB Audio Hostless",
  5106. .stream_name = "USB Audio Hostless",
  5107. .cpu_dai_name = "USBAUDIO_HOSTLESS",
  5108. .platform_name = "msm-pcm-hostless",
  5109. .dynamic = 1,
  5110. .dpcm_playback = 1,
  5111. .dpcm_capture = 1,
  5112. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5113. SND_SOC_DPCM_TRIGGER_POST},
  5114. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5115. .ignore_suspend = 1,
  5116. .ignore_pmdown_time = 1,
  5117. .codec_dai_name = "snd-soc-dummy-dai",
  5118. .codec_name = "snd-soc-dummy",
  5119. },
  5120. {/* hw:x,36 */
  5121. .name = "SLIMBUS_7 Hostless",
  5122. .stream_name = "SLIMBUS_7 Hostless",
  5123. .cpu_dai_name = "SLIMBUS7_HOSTLESS",
  5124. .platform_name = "msm-pcm-hostless",
  5125. .dynamic = 1,
  5126. .dpcm_capture = 1,
  5127. .dpcm_playback = 1,
  5128. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5129. SND_SOC_DPCM_TRIGGER_POST},
  5130. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5131. .ignore_suspend = 1,
  5132. .ignore_pmdown_time = 1,
  5133. .codec_dai_name = "snd-soc-dummy-dai",
  5134. .codec_name = "snd-soc-dummy",
  5135. },
  5136. {/* hw:x,37 */
  5137. .name = "Compress Capture",
  5138. .stream_name = "Compress9",
  5139. .cpu_dai_name = "MultiMedia17",
  5140. .platform_name = "msm-compress-dsp",
  5141. .dynamic = 1,
  5142. .dpcm_capture = 1,
  5143. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5144. SND_SOC_DPCM_TRIGGER_POST},
  5145. .codec_dai_name = "snd-soc-dummy-dai",
  5146. .codec_name = "snd-soc-dummy",
  5147. .ignore_suspend = 1,
  5148. .ignore_pmdown_time = 1,
  5149. .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
  5150. },
  5151. {/* hw:x,38 */
  5152. .name = "SLIMBUS_8 Hostless",
  5153. .stream_name = "SLIMBUS_8 Hostless",
  5154. .cpu_dai_name = "SLIMBUS8_HOSTLESS",
  5155. .platform_name = "msm-pcm-hostless",
  5156. .dynamic = 1,
  5157. .dpcm_capture = 1,
  5158. .dpcm_playback = 1,
  5159. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  5160. SND_SOC_DPCM_TRIGGER_POST},
  5161. .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
  5162. .ignore_suspend = 1,
  5163. .ignore_pmdown_time = 1,
  5164. .codec_dai_name = "snd-soc-dummy-dai",
  5165. .codec_name = "snd-soc-dummy",
  5166. },
  5167. };
  5168. static struct snd_soc_dai_link msm_common_be_dai_links[] = {
  5169. /* Backend AFE DAI Links */
  5170. {
  5171. .name = LPASS_BE_AFE_PCM_RX,
  5172. .stream_name = "AFE Playback",
  5173. .cpu_dai_name = "msm-dai-q6-dev.224",
  5174. .platform_name = "msm-pcm-routing",
  5175. .codec_name = "msm-stub-codec.1",
  5176. .codec_dai_name = "msm-stub-rx",
  5177. .no_pcm = 1,
  5178. .dpcm_playback = 1,
  5179. .id = MSM_BACKEND_DAI_AFE_PCM_RX,
  5180. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5181. /* this dainlink has playback support */
  5182. .ignore_pmdown_time = 1,
  5183. .ignore_suspend = 1,
  5184. },
  5185. {
  5186. .name = LPASS_BE_AFE_PCM_TX,
  5187. .stream_name = "AFE Capture",
  5188. .cpu_dai_name = "msm-dai-q6-dev.225",
  5189. .platform_name = "msm-pcm-routing",
  5190. .codec_name = "msm-stub-codec.1",
  5191. .codec_dai_name = "msm-stub-tx",
  5192. .no_pcm = 1,
  5193. .dpcm_capture = 1,
  5194. .id = MSM_BACKEND_DAI_AFE_PCM_TX,
  5195. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5196. .ignore_suspend = 1,
  5197. },
  5198. /* Incall Record Uplink BACK END DAI Link */
  5199. {
  5200. .name = LPASS_BE_INCALL_RECORD_TX,
  5201. .stream_name = "Voice Uplink Capture",
  5202. .cpu_dai_name = "msm-dai-q6-dev.32772",
  5203. .platform_name = "msm-pcm-routing",
  5204. .codec_name = "msm-stub-codec.1",
  5205. .codec_dai_name = "msm-stub-tx",
  5206. .no_pcm = 1,
  5207. .dpcm_capture = 1,
  5208. .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
  5209. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5210. .ignore_suspend = 1,
  5211. },
  5212. /* Incall Record Downlink BACK END DAI Link */
  5213. {
  5214. .name = LPASS_BE_INCALL_RECORD_RX,
  5215. .stream_name = "Voice Downlink Capture",
  5216. .cpu_dai_name = "msm-dai-q6-dev.32771",
  5217. .platform_name = "msm-pcm-routing",
  5218. .codec_name = "msm-stub-codec.1",
  5219. .codec_dai_name = "msm-stub-tx",
  5220. .no_pcm = 1,
  5221. .dpcm_capture = 1,
  5222. .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
  5223. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5224. .ignore_suspend = 1,
  5225. },
  5226. /* Incall Music BACK END DAI Link */
  5227. {
  5228. .name = LPASS_BE_VOICE_PLAYBACK_TX,
  5229. .stream_name = "Voice Farend Playback",
  5230. .cpu_dai_name = "msm-dai-q6-dev.32773",
  5231. .platform_name = "msm-pcm-routing",
  5232. .codec_name = "msm-stub-codec.1",
  5233. .codec_dai_name = "msm-stub-rx",
  5234. .no_pcm = 1,
  5235. .dpcm_playback = 1,
  5236. .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
  5237. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5238. .ignore_suspend = 1,
  5239. .ignore_pmdown_time = 1,
  5240. },
  5241. /* Incall Music 2 BACK END DAI Link */
  5242. {
  5243. .name = LPASS_BE_VOICE2_PLAYBACK_TX,
  5244. .stream_name = "Voice2 Farend Playback",
  5245. .cpu_dai_name = "msm-dai-q6-dev.32770",
  5246. .platform_name = "msm-pcm-routing",
  5247. .codec_name = "msm-stub-codec.1",
  5248. .codec_dai_name = "msm-stub-rx",
  5249. .no_pcm = 1,
  5250. .dpcm_playback = 1,
  5251. .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
  5252. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5253. .ignore_suspend = 1,
  5254. .ignore_pmdown_time = 1,
  5255. },
  5256. {
  5257. .name = LPASS_BE_USB_AUDIO_RX,
  5258. .stream_name = "USB Audio Playback",
  5259. .cpu_dai_name = "msm-dai-q6-dev.28672",
  5260. .platform_name = "msm-pcm-routing",
  5261. .codec_name = "msm-stub-codec.1",
  5262. .codec_dai_name = "msm-stub-rx",
  5263. .no_pcm = 1,
  5264. .dpcm_playback = 1,
  5265. .id = MSM_BACKEND_DAI_USB_RX,
  5266. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5267. .ignore_pmdown_time = 1,
  5268. .ignore_suspend = 1,
  5269. },
  5270. {
  5271. .name = LPASS_BE_USB_AUDIO_TX,
  5272. .stream_name = "USB Audio Capture",
  5273. .cpu_dai_name = "msm-dai-q6-dev.28673",
  5274. .platform_name = "msm-pcm-routing",
  5275. .codec_name = "msm-stub-codec.1",
  5276. .codec_dai_name = "msm-stub-tx",
  5277. .no_pcm = 1,
  5278. .dpcm_capture = 1,
  5279. .id = MSM_BACKEND_DAI_USB_TX,
  5280. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5281. .ignore_suspend = 1,
  5282. },
  5283. {
  5284. .name = LPASS_BE_PRI_TDM_RX_0,
  5285. .stream_name = "Primary TDM0 Playback",
  5286. .cpu_dai_name = "msm-dai-q6-tdm.36864",
  5287. .platform_name = "msm-pcm-routing",
  5288. .codec_name = "msm-stub-codec.1",
  5289. .codec_dai_name = "msm-stub-rx",
  5290. .no_pcm = 1,
  5291. .dpcm_playback = 1,
  5292. .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
  5293. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5294. .ops = &kona_tdm_be_ops,
  5295. .ignore_suspend = 1,
  5296. .ignore_pmdown_time = 1,
  5297. },
  5298. {
  5299. .name = LPASS_BE_PRI_TDM_TX_0,
  5300. .stream_name = "Primary TDM0 Capture",
  5301. .cpu_dai_name = "msm-dai-q6-tdm.36865",
  5302. .platform_name = "msm-pcm-routing",
  5303. .codec_name = "msm-stub-codec.1",
  5304. .codec_dai_name = "msm-stub-tx",
  5305. .no_pcm = 1,
  5306. .dpcm_capture = 1,
  5307. .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
  5308. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5309. .ops = &kona_tdm_be_ops,
  5310. .ignore_suspend = 1,
  5311. },
  5312. {
  5313. .name = LPASS_BE_SEC_TDM_RX_0,
  5314. .stream_name = "Secondary TDM0 Playback",
  5315. .cpu_dai_name = "msm-dai-q6-tdm.36880",
  5316. .platform_name = "msm-pcm-routing",
  5317. .codec_name = "msm-stub-codec.1",
  5318. .codec_dai_name = "msm-stub-rx",
  5319. .no_pcm = 1,
  5320. .dpcm_playback = 1,
  5321. .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
  5322. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5323. .ops = &kona_tdm_be_ops,
  5324. .ignore_suspend = 1,
  5325. .ignore_pmdown_time = 1,
  5326. },
  5327. {
  5328. .name = LPASS_BE_SEC_TDM_TX_0,
  5329. .stream_name = "Secondary TDM0 Capture",
  5330. .cpu_dai_name = "msm-dai-q6-tdm.36881",
  5331. .platform_name = "msm-pcm-routing",
  5332. .codec_name = "msm-stub-codec.1",
  5333. .codec_dai_name = "msm-stub-tx",
  5334. .no_pcm = 1,
  5335. .dpcm_capture = 1,
  5336. .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
  5337. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5338. .ops = &kona_tdm_be_ops,
  5339. .ignore_suspend = 1,
  5340. },
  5341. {
  5342. .name = LPASS_BE_TERT_TDM_RX_0,
  5343. .stream_name = "Tertiary TDM0 Playback",
  5344. .cpu_dai_name = "msm-dai-q6-tdm.36896",
  5345. .platform_name = "msm-pcm-routing",
  5346. .codec_name = "msm-stub-codec.1",
  5347. .codec_dai_name = "msm-stub-rx",
  5348. .no_pcm = 1,
  5349. .dpcm_playback = 1,
  5350. .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
  5351. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5352. .ops = &kona_tdm_be_ops,
  5353. .ignore_suspend = 1,
  5354. .ignore_pmdown_time = 1,
  5355. },
  5356. {
  5357. .name = LPASS_BE_TERT_TDM_TX_0,
  5358. .stream_name = "Tertiary TDM0 Capture",
  5359. .cpu_dai_name = "msm-dai-q6-tdm.36897",
  5360. .platform_name = "msm-pcm-routing",
  5361. .codec_name = "msm-stub-codec.1",
  5362. .codec_dai_name = "msm-stub-tx",
  5363. .no_pcm = 1,
  5364. .dpcm_capture = 1,
  5365. .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
  5366. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5367. .ops = &kona_tdm_be_ops,
  5368. .ignore_suspend = 1,
  5369. },
  5370. {
  5371. .name = LPASS_BE_QUAT_TDM_RX_0,
  5372. .stream_name = "Quaternary TDM0 Playback",
  5373. .cpu_dai_name = "msm-dai-q6-tdm.36912",
  5374. .platform_name = "msm-pcm-routing",
  5375. .codec_name = "msm-stub-codec.1",
  5376. .codec_dai_name = "msm-stub-rx",
  5377. .no_pcm = 1,
  5378. .dpcm_playback = 1,
  5379. .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
  5380. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5381. .ops = &kona_tdm_be_ops,
  5382. .ignore_suspend = 1,
  5383. .ignore_pmdown_time = 1,
  5384. },
  5385. {
  5386. .name = LPASS_BE_QUAT_TDM_TX_0,
  5387. .stream_name = "Quaternary TDM0 Capture",
  5388. .cpu_dai_name = "msm-dai-q6-tdm.36913",
  5389. .platform_name = "msm-pcm-routing",
  5390. .codec_name = "msm-stub-codec.1",
  5391. .codec_dai_name = "msm-stub-tx",
  5392. .no_pcm = 1,
  5393. .dpcm_capture = 1,
  5394. .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
  5395. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5396. .ops = &kona_tdm_be_ops,
  5397. .ignore_suspend = 1,
  5398. },
  5399. {
  5400. .name = LPASS_BE_QUIN_TDM_RX_0,
  5401. .stream_name = "Quinary TDM0 Playback",
  5402. .cpu_dai_name = "msm-dai-q6-tdm.36928",
  5403. .platform_name = "msm-pcm-routing",
  5404. .codec_name = "msm-stub-codec.1",
  5405. .codec_dai_name = "msm-stub-rx",
  5406. .no_pcm = 1,
  5407. .dpcm_playback = 1,
  5408. .id = MSM_BACKEND_DAI_QUIN_TDM_RX_0,
  5409. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5410. .ops = &kona_tdm_be_ops,
  5411. .ignore_suspend = 1,
  5412. .ignore_pmdown_time = 1,
  5413. },
  5414. {
  5415. .name = LPASS_BE_QUIN_TDM_TX_0,
  5416. .stream_name = "Quinary TDM0 Capture",
  5417. .cpu_dai_name = "msm-dai-q6-tdm.36929",
  5418. .platform_name = "msm-pcm-routing",
  5419. .codec_name = "msm-stub-codec.1",
  5420. .codec_dai_name = "msm-stub-tx",
  5421. .no_pcm = 1,
  5422. .dpcm_capture = 1,
  5423. .id = MSM_BACKEND_DAI_QUIN_TDM_TX_0,
  5424. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5425. .ops = &kona_tdm_be_ops,
  5426. .ignore_suspend = 1,
  5427. },
  5428. {
  5429. .name = LPASS_BE_SEN_TDM_RX_0,
  5430. .stream_name = "Senary TDM0 Playback",
  5431. .cpu_dai_name = "msm-dai-q6-tdm.36944",
  5432. .platform_name = "msm-pcm-routing",
  5433. .codec_name = "msm-stub-codec.1",
  5434. .codec_dai_name = "msm-stub-rx",
  5435. .no_pcm = 1,
  5436. .dpcm_playback = 1,
  5437. .id = MSM_BACKEND_DAI_SEN_TDM_RX_0,
  5438. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5439. .ops = &kona_tdm_be_ops,
  5440. .ignore_suspend = 1,
  5441. .ignore_pmdown_time = 1,
  5442. },
  5443. {
  5444. .name = LPASS_BE_SEN_TDM_TX_0,
  5445. .stream_name = "Senary TDM0 Capture",
  5446. .cpu_dai_name = "msm-dai-q6-tdm.36945",
  5447. .platform_name = "msm-pcm-routing",
  5448. .codec_name = "msm-stub-codec.1",
  5449. .codec_dai_name = "msm-stub-tx",
  5450. .no_pcm = 1,
  5451. .dpcm_capture = 1,
  5452. .id = MSM_BACKEND_DAI_SEN_TDM_TX_0,
  5453. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5454. .ops = &kona_tdm_be_ops,
  5455. .ignore_suspend = 1,
  5456. },
  5457. };
  5458. static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
  5459. {
  5460. .name = LPASS_BE_SLIMBUS_7_RX,
  5461. .stream_name = "Slimbus7 Playback",
  5462. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5463. .platform_name = "msm-pcm-routing",
  5464. .codec_name = "btfmslim_slave",
  5465. /* BT codec driver determines capabilities based on
  5466. * dai name, bt codecdai name should always contains
  5467. * supported usecase information
  5468. */
  5469. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5470. .no_pcm = 1,
  5471. .dpcm_playback = 1,
  5472. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5473. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5474. .init = &msm_wcn_init,
  5475. .ops = &msm_wcn_ops,
  5476. /* dai link has playback support */
  5477. .ignore_pmdown_time = 1,
  5478. .ignore_suspend = 1,
  5479. },
  5480. {
  5481. .name = LPASS_BE_SLIMBUS_7_TX,
  5482. .stream_name = "Slimbus7 Capture",
  5483. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5484. .platform_name = "msm-pcm-routing",
  5485. .codec_name = "btfmslim_slave",
  5486. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5487. .no_pcm = 1,
  5488. .dpcm_capture = 1,
  5489. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5490. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5491. .ops = &msm_wcn_ops,
  5492. .ignore_suspend = 1,
  5493. },
  5494. };
  5495. static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
  5496. {
  5497. .name = LPASS_BE_SLIMBUS_7_RX,
  5498. .stream_name = "Slimbus7 Playback",
  5499. .cpu_dai_name = "msm-dai-q6-dev.16398",
  5500. .platform_name = "msm-pcm-routing",
  5501. .codec_name = "btfmslim_slave",
  5502. /* BT codec driver determines capabilities based on
  5503. * dai name, bt codecdai name should always contains
  5504. * supported usecase information
  5505. */
  5506. .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
  5507. .no_pcm = 1,
  5508. .dpcm_playback = 1,
  5509. .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
  5510. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5511. .init = &msm_wcn_init_lito,
  5512. .ops = &msm_wcn_ops_lito,
  5513. /* dai link has playback support */
  5514. .ignore_pmdown_time = 1,
  5515. .ignore_suspend = 1,
  5516. },
  5517. {
  5518. .name = LPASS_BE_SLIMBUS_7_TX,
  5519. .stream_name = "Slimbus7 Capture",
  5520. .cpu_dai_name = "msm-dai-q6-dev.16399",
  5521. .platform_name = "msm-pcm-routing",
  5522. .codec_name = "btfmslim_slave",
  5523. .codec_dai_name = "btfm_bt_sco_slim_tx",
  5524. .no_pcm = 1,
  5525. .dpcm_capture = 1,
  5526. .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
  5527. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5528. .ops = &msm_wcn_ops_lito,
  5529. .ignore_suspend = 1,
  5530. },
  5531. {
  5532. .name = LPASS_BE_SLIMBUS_8_TX,
  5533. .stream_name = "Slimbus8 Capture",
  5534. .cpu_dai_name = "msm-dai-q6-dev.16401",
  5535. .platform_name = "msm-pcm-routing",
  5536. .codec_name = "btfmslim_slave",
  5537. .codec_dai_name = "btfm_fm_slim_tx",
  5538. .no_pcm = 1,
  5539. .dpcm_capture = 1,
  5540. .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
  5541. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5542. .ops = &msm_wcn_ops_lito,
  5543. .ignore_suspend = 1,
  5544. },
  5545. };
  5546. static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
  5547. /* DISP PORT BACK END DAI Link */
  5548. {
  5549. .name = LPASS_BE_DISPLAY_PORT,
  5550. .stream_name = "Display Port Playback",
  5551. .cpu_dai_name = "msm-dai-q6-dp.24608",
  5552. .platform_name = "msm-pcm-routing",
  5553. .codec_name = "msm-ext-disp-audio-codec-rx",
  5554. .codec_dai_name = "msm_dp_audio_codec_rx_dai",
  5555. .no_pcm = 1,
  5556. .dpcm_playback = 1,
  5557. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
  5558. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5559. .ignore_pmdown_time = 1,
  5560. .ignore_suspend = 1,
  5561. },
  5562. /* DISP PORT 1 BACK END DAI Link */
  5563. {
  5564. .name = LPASS_BE_DISPLAY_PORT1,
  5565. .stream_name = "Display Port1 Playback",
  5566. .cpu_dai_name = "msm-dai-q6-dp.24608",
  5567. .platform_name = "msm-pcm-routing",
  5568. .codec_name = "msm-ext-disp-audio-codec-rx",
  5569. .codec_dai_name = "msm_dp_audio_codec_rx1_dai",
  5570. .no_pcm = 1,
  5571. .dpcm_playback = 1,
  5572. .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX_1,
  5573. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5574. .ignore_pmdown_time = 1,
  5575. .ignore_suspend = 1,
  5576. },
  5577. };
  5578. static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
  5579. {
  5580. .name = LPASS_BE_PRI_MI2S_RX,
  5581. .stream_name = "Primary MI2S Playback",
  5582. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5583. .platform_name = "msm-pcm-routing",
  5584. .codec_name = "msm-stub-codec.1",
  5585. .codec_dai_name = "msm-stub-rx",
  5586. .no_pcm = 1,
  5587. .dpcm_playback = 1,
  5588. .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
  5589. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5590. .ops = &msm_mi2s_be_ops,
  5591. .ignore_suspend = 1,
  5592. .ignore_pmdown_time = 1,
  5593. },
  5594. {
  5595. .name = LPASS_BE_PRI_MI2S_TX,
  5596. .stream_name = "Primary MI2S Capture",
  5597. .cpu_dai_name = "msm-dai-q6-mi2s.0",
  5598. .platform_name = "msm-pcm-routing",
  5599. .codec_name = "msm-stub-codec.1",
  5600. .codec_dai_name = "msm-stub-tx",
  5601. .no_pcm = 1,
  5602. .dpcm_capture = 1,
  5603. .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
  5604. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5605. .ops = &msm_mi2s_be_ops,
  5606. .ignore_suspend = 1,
  5607. },
  5608. {
  5609. .name = LPASS_BE_SEC_MI2S_RX,
  5610. .stream_name = "Secondary MI2S Playback",
  5611. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5612. .platform_name = "msm-pcm-routing",
  5613. .codec_name = "msm-stub-codec.1",
  5614. .codec_dai_name = "msm-stub-rx",
  5615. .no_pcm = 1,
  5616. .dpcm_playback = 1,
  5617. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
  5618. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5619. .ops = &msm_mi2s_be_ops,
  5620. .ignore_suspend = 1,
  5621. .ignore_pmdown_time = 1,
  5622. },
  5623. {
  5624. .name = LPASS_BE_SEC_MI2S_TX,
  5625. .stream_name = "Secondary MI2S Capture",
  5626. .cpu_dai_name = "msm-dai-q6-mi2s.1",
  5627. .platform_name = "msm-pcm-routing",
  5628. .codec_name = "msm-stub-codec.1",
  5629. .codec_dai_name = "msm-stub-tx",
  5630. .no_pcm = 1,
  5631. .dpcm_capture = 1,
  5632. .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
  5633. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5634. .ops = &msm_mi2s_be_ops,
  5635. .ignore_suspend = 1,
  5636. },
  5637. {
  5638. .name = LPASS_BE_TERT_MI2S_RX,
  5639. .stream_name = "Tertiary MI2S Playback",
  5640. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5641. .platform_name = "msm-pcm-routing",
  5642. .codec_name = "msm-stub-codec.1",
  5643. .codec_dai_name = "msm-stub-rx",
  5644. .no_pcm = 1,
  5645. .dpcm_playback = 1,
  5646. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
  5647. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5648. .ops = &msm_mi2s_be_ops,
  5649. .ignore_suspend = 1,
  5650. .ignore_pmdown_time = 1,
  5651. },
  5652. {
  5653. .name = LPASS_BE_TERT_MI2S_TX,
  5654. .stream_name = "Tertiary MI2S Capture",
  5655. .cpu_dai_name = "msm-dai-q6-mi2s.2",
  5656. .platform_name = "msm-pcm-routing",
  5657. .codec_name = "msm-stub-codec.1",
  5658. .codec_dai_name = "msm-stub-tx",
  5659. .no_pcm = 1,
  5660. .dpcm_capture = 1,
  5661. .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
  5662. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5663. .ops = &msm_mi2s_be_ops,
  5664. .ignore_suspend = 1,
  5665. },
  5666. {
  5667. .name = LPASS_BE_QUAT_MI2S_RX,
  5668. .stream_name = "Quaternary MI2S Playback",
  5669. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5670. .platform_name = "msm-pcm-routing",
  5671. .codec_name = "msm-stub-codec.1",
  5672. .codec_dai_name = "msm-stub-rx",
  5673. .no_pcm = 1,
  5674. .dpcm_playback = 1,
  5675. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
  5676. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5677. .ops = &msm_mi2s_be_ops,
  5678. .ignore_suspend = 1,
  5679. .ignore_pmdown_time = 1,
  5680. },
  5681. {
  5682. .name = LPASS_BE_QUAT_MI2S_TX,
  5683. .stream_name = "Quaternary MI2S Capture",
  5684. .cpu_dai_name = "msm-dai-q6-mi2s.3",
  5685. .platform_name = "msm-pcm-routing",
  5686. .codec_name = "msm-stub-codec.1",
  5687. .codec_dai_name = "msm-stub-tx",
  5688. .no_pcm = 1,
  5689. .dpcm_capture = 1,
  5690. .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
  5691. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5692. .ops = &msm_mi2s_be_ops,
  5693. .ignore_suspend = 1,
  5694. },
  5695. {
  5696. .name = LPASS_BE_QUIN_MI2S_RX,
  5697. .stream_name = "Quinary MI2S Playback",
  5698. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5699. .platform_name = "msm-pcm-routing",
  5700. .codec_name = "msm-stub-codec.1",
  5701. .codec_dai_name = "msm-stub-rx",
  5702. .no_pcm = 1,
  5703. .dpcm_playback = 1,
  5704. .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
  5705. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5706. .ops = &msm_mi2s_be_ops,
  5707. .ignore_suspend = 1,
  5708. .ignore_pmdown_time = 1,
  5709. },
  5710. {
  5711. .name = LPASS_BE_QUIN_MI2S_TX,
  5712. .stream_name = "Quinary MI2S Capture",
  5713. .cpu_dai_name = "msm-dai-q6-mi2s.4",
  5714. .platform_name = "msm-pcm-routing",
  5715. .codec_name = "msm-stub-codec.1",
  5716. .codec_dai_name = "msm-stub-tx",
  5717. .no_pcm = 1,
  5718. .dpcm_capture = 1,
  5719. .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
  5720. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5721. .ops = &msm_mi2s_be_ops,
  5722. .ignore_suspend = 1,
  5723. },
  5724. {
  5725. .name = LPASS_BE_SENARY_MI2S_RX,
  5726. .stream_name = "Senary MI2S Playback",
  5727. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  5728. .platform_name = "msm-pcm-routing",
  5729. .codec_name = "msm-stub-codec.1",
  5730. .codec_dai_name = "msm-stub-rx",
  5731. .no_pcm = 1,
  5732. .dpcm_playback = 1,
  5733. .id = MSM_BACKEND_DAI_SENARY_MI2S_RX,
  5734. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5735. .ops = &msm_mi2s_be_ops,
  5736. .ignore_suspend = 1,
  5737. .ignore_pmdown_time = 1,
  5738. },
  5739. {
  5740. .name = LPASS_BE_SENARY_MI2S_TX,
  5741. .stream_name = "Senary MI2S Capture",
  5742. .cpu_dai_name = "msm-dai-q6-mi2s.5",
  5743. .platform_name = "msm-pcm-routing",
  5744. .codec_name = "msm-stub-codec.1",
  5745. .codec_dai_name = "msm-stub-tx",
  5746. .no_pcm = 1,
  5747. .dpcm_capture = 1,
  5748. .id = MSM_BACKEND_DAI_SENARY_MI2S_TX,
  5749. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5750. .ops = &msm_mi2s_be_ops,
  5751. .ignore_suspend = 1,
  5752. },
  5753. };
  5754. static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
  5755. /* Primary AUX PCM Backend DAI Links */
  5756. {
  5757. .name = LPASS_BE_AUXPCM_RX,
  5758. .stream_name = "AUX PCM Playback",
  5759. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5760. .platform_name = "msm-pcm-routing",
  5761. .codec_name = "msm-stub-codec.1",
  5762. .codec_dai_name = "msm-stub-rx",
  5763. .no_pcm = 1,
  5764. .dpcm_playback = 1,
  5765. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  5766. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5767. .ops = &kona_aux_be_ops,
  5768. .ignore_pmdown_time = 1,
  5769. .ignore_suspend = 1,
  5770. },
  5771. {
  5772. .name = LPASS_BE_AUXPCM_TX,
  5773. .stream_name = "AUX PCM Capture",
  5774. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  5775. .platform_name = "msm-pcm-routing",
  5776. .codec_name = "msm-stub-codec.1",
  5777. .codec_dai_name = "msm-stub-tx",
  5778. .no_pcm = 1,
  5779. .dpcm_capture = 1,
  5780. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  5781. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5782. .ops = &kona_aux_be_ops,
  5783. .ignore_suspend = 1,
  5784. },
  5785. /* Secondary AUX PCM Backend DAI Links */
  5786. {
  5787. .name = LPASS_BE_SEC_AUXPCM_RX,
  5788. .stream_name = "Sec AUX PCM Playback",
  5789. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5790. .platform_name = "msm-pcm-routing",
  5791. .codec_name = "msm-stub-codec.1",
  5792. .codec_dai_name = "msm-stub-rx",
  5793. .no_pcm = 1,
  5794. .dpcm_playback = 1,
  5795. .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
  5796. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5797. .ops = &kona_aux_be_ops,
  5798. .ignore_pmdown_time = 1,
  5799. .ignore_suspend = 1,
  5800. },
  5801. {
  5802. .name = LPASS_BE_SEC_AUXPCM_TX,
  5803. .stream_name = "Sec AUX PCM Capture",
  5804. .cpu_dai_name = "msm-dai-q6-auxpcm.2",
  5805. .platform_name = "msm-pcm-routing",
  5806. .codec_name = "msm-stub-codec.1",
  5807. .codec_dai_name = "msm-stub-tx",
  5808. .no_pcm = 1,
  5809. .dpcm_capture = 1,
  5810. .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
  5811. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5812. .ops = &kona_aux_be_ops,
  5813. .ignore_suspend = 1,
  5814. },
  5815. /* Tertiary AUX PCM Backend DAI Links */
  5816. {
  5817. .name = LPASS_BE_TERT_AUXPCM_RX,
  5818. .stream_name = "Tert AUX PCM Playback",
  5819. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5820. .platform_name = "msm-pcm-routing",
  5821. .codec_name = "msm-stub-codec.1",
  5822. .codec_dai_name = "msm-stub-rx",
  5823. .no_pcm = 1,
  5824. .dpcm_playback = 1,
  5825. .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
  5826. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5827. .ops = &kona_aux_be_ops,
  5828. .ignore_suspend = 1,
  5829. },
  5830. {
  5831. .name = LPASS_BE_TERT_AUXPCM_TX,
  5832. .stream_name = "Tert AUX PCM Capture",
  5833. .cpu_dai_name = "msm-dai-q6-auxpcm.3",
  5834. .platform_name = "msm-pcm-routing",
  5835. .codec_name = "msm-stub-codec.1",
  5836. .codec_dai_name = "msm-stub-tx",
  5837. .no_pcm = 1,
  5838. .dpcm_capture = 1,
  5839. .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
  5840. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5841. .ops = &kona_aux_be_ops,
  5842. .ignore_suspend = 1,
  5843. },
  5844. /* Quaternary AUX PCM Backend DAI Links */
  5845. {
  5846. .name = LPASS_BE_QUAT_AUXPCM_RX,
  5847. .stream_name = "Quat AUX PCM Playback",
  5848. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5849. .platform_name = "msm-pcm-routing",
  5850. .codec_name = "msm-stub-codec.1",
  5851. .codec_dai_name = "msm-stub-rx",
  5852. .no_pcm = 1,
  5853. .dpcm_playback = 1,
  5854. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
  5855. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5856. .ops = &kona_aux_be_ops,
  5857. .ignore_suspend = 1,
  5858. },
  5859. {
  5860. .name = LPASS_BE_QUAT_AUXPCM_TX,
  5861. .stream_name = "Quat AUX PCM Capture",
  5862. .cpu_dai_name = "msm-dai-q6-auxpcm.4",
  5863. .platform_name = "msm-pcm-routing",
  5864. .codec_name = "msm-stub-codec.1",
  5865. .codec_dai_name = "msm-stub-tx",
  5866. .no_pcm = 1,
  5867. .dpcm_capture = 1,
  5868. .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
  5869. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5870. .ops = &kona_aux_be_ops,
  5871. .ignore_suspend = 1,
  5872. },
  5873. /* Quinary AUX PCM Backend DAI Links */
  5874. {
  5875. .name = LPASS_BE_QUIN_AUXPCM_RX,
  5876. .stream_name = "Quin AUX PCM Playback",
  5877. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5878. .platform_name = "msm-pcm-routing",
  5879. .codec_name = "msm-stub-codec.1",
  5880. .codec_dai_name = "msm-stub-rx",
  5881. .no_pcm = 1,
  5882. .dpcm_playback = 1,
  5883. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
  5884. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5885. .ops = &kona_aux_be_ops,
  5886. .ignore_suspend = 1,
  5887. },
  5888. {
  5889. .name = LPASS_BE_QUIN_AUXPCM_TX,
  5890. .stream_name = "Quin AUX PCM Capture",
  5891. .cpu_dai_name = "msm-dai-q6-auxpcm.5",
  5892. .platform_name = "msm-pcm-routing",
  5893. .codec_name = "msm-stub-codec.1",
  5894. .codec_dai_name = "msm-stub-tx",
  5895. .no_pcm = 1,
  5896. .dpcm_capture = 1,
  5897. .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
  5898. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5899. .ops = &kona_aux_be_ops,
  5900. .ignore_suspend = 1,
  5901. },
  5902. /* Senary AUX PCM Backend DAI Links */
  5903. {
  5904. .name = LPASS_BE_SEN_AUXPCM_RX,
  5905. .stream_name = "Sen AUX PCM Playback",
  5906. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  5907. .platform_name = "msm-pcm-routing",
  5908. .codec_name = "msm-stub-codec.1",
  5909. .codec_dai_name = "msm-stub-rx",
  5910. .no_pcm = 1,
  5911. .dpcm_playback = 1,
  5912. .id = MSM_BACKEND_DAI_SEN_AUXPCM_RX,
  5913. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5914. .ops = &kona_aux_be_ops,
  5915. .ignore_suspend = 1,
  5916. },
  5917. {
  5918. .name = LPASS_BE_SEN_AUXPCM_TX,
  5919. .stream_name = "Sen AUX PCM Capture",
  5920. .cpu_dai_name = "msm-dai-q6-auxpcm.6",
  5921. .platform_name = "msm-pcm-routing",
  5922. .codec_name = "msm-stub-codec.1",
  5923. .codec_dai_name = "msm-stub-tx",
  5924. .no_pcm = 1,
  5925. .dpcm_capture = 1,
  5926. .id = MSM_BACKEND_DAI_SEN_AUXPCM_TX,
  5927. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5928. .ops = &kona_aux_be_ops,
  5929. .ignore_suspend = 1,
  5930. },
  5931. };
  5932. static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
  5933. /* WSA CDC DMA Backend DAI Links */
  5934. {
  5935. .name = LPASS_BE_WSA_CDC_DMA_RX_0,
  5936. .stream_name = "WSA CDC DMA0 Playback",
  5937. .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
  5938. .platform_name = "msm-pcm-routing",
  5939. .codec_name = "bolero_codec",
  5940. .codec_dai_name = "wsa_macro_rx1",
  5941. .no_pcm = 1,
  5942. .dpcm_playback = 1,
  5943. .init = &msm_int_audrx_init,
  5944. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
  5945. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5946. .ignore_pmdown_time = 1,
  5947. .ignore_suspend = 1,
  5948. .ops = &msm_cdc_dma_be_ops,
  5949. },
  5950. {
  5951. .name = LPASS_BE_WSA_CDC_DMA_RX_1,
  5952. .stream_name = "WSA CDC DMA1 Playback",
  5953. .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
  5954. .platform_name = "msm-pcm-routing",
  5955. .codec_name = "bolero_codec",
  5956. .codec_dai_name = "wsa_macro_rx_mix",
  5957. .no_pcm = 1,
  5958. .dpcm_playback = 1,
  5959. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
  5960. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5961. .ignore_pmdown_time = 1,
  5962. .ignore_suspend = 1,
  5963. .ops = &msm_cdc_dma_be_ops,
  5964. },
  5965. {
  5966. .name = LPASS_BE_WSA_CDC_DMA_TX_1,
  5967. .stream_name = "WSA CDC DMA1 Capture",
  5968. .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
  5969. .platform_name = "msm-pcm-routing",
  5970. .codec_name = "bolero_codec",
  5971. .codec_dai_name = "wsa_macro_echo",
  5972. .no_pcm = 1,
  5973. .dpcm_capture = 1,
  5974. .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
  5975. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5976. .ignore_suspend = 1,
  5977. .ops = &msm_cdc_dma_be_ops,
  5978. },
  5979. };
  5980. static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
  5981. /* RX CDC DMA Backend DAI Links */
  5982. {
  5983. .name = LPASS_BE_RX_CDC_DMA_RX_0,
  5984. .stream_name = "RX CDC DMA0 Playback",
  5985. .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
  5986. .platform_name = "msm-pcm-routing",
  5987. .codec_name = "bolero_codec",
  5988. .codec_dai_name = "rx_macro_rx1",
  5989. .no_pcm = 1,
  5990. .dpcm_playback = 1,
  5991. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
  5992. .be_hw_params_fixup = msm_be_hw_params_fixup,
  5993. .ignore_pmdown_time = 1,
  5994. .ignore_suspend = 1,
  5995. .ops = &msm_cdc_dma_be_ops,
  5996. },
  5997. {
  5998. .name = LPASS_BE_RX_CDC_DMA_RX_1,
  5999. .stream_name = "RX CDC DMA1 Playback",
  6000. .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
  6001. .platform_name = "msm-pcm-routing",
  6002. .codec_name = "bolero_codec",
  6003. .codec_dai_name = "rx_macro_rx2",
  6004. .no_pcm = 1,
  6005. .dpcm_playback = 1,
  6006. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
  6007. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6008. .ignore_pmdown_time = 1,
  6009. .ignore_suspend = 1,
  6010. .ops = &msm_cdc_dma_be_ops,
  6011. },
  6012. {
  6013. .name = LPASS_BE_RX_CDC_DMA_RX_2,
  6014. .stream_name = "RX CDC DMA2 Playback",
  6015. .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
  6016. .platform_name = "msm-pcm-routing",
  6017. .codec_name = "bolero_codec",
  6018. .codec_dai_name = "rx_macro_rx3",
  6019. .no_pcm = 1,
  6020. .dpcm_playback = 1,
  6021. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
  6022. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6023. .ignore_pmdown_time = 1,
  6024. .ignore_suspend = 1,
  6025. .ops = &msm_cdc_dma_be_ops,
  6026. },
  6027. {
  6028. .name = LPASS_BE_RX_CDC_DMA_RX_3,
  6029. .stream_name = "RX CDC DMA3 Playback",
  6030. .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
  6031. .platform_name = "msm-pcm-routing",
  6032. .codec_name = "bolero_codec",
  6033. .codec_dai_name = "rx_macro_rx4",
  6034. .no_pcm = 1,
  6035. .dpcm_playback = 1,
  6036. .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
  6037. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6038. .ignore_pmdown_time = 1,
  6039. .ignore_suspend = 1,
  6040. .ops = &msm_cdc_dma_be_ops,
  6041. },
  6042. /* TX CDC DMA Backend DAI Links */
  6043. {
  6044. .name = LPASS_BE_TX_CDC_DMA_TX_3,
  6045. .stream_name = "TX CDC DMA3 Capture",
  6046. .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
  6047. .platform_name = "msm-pcm-routing",
  6048. .codec_name = "bolero_codec",
  6049. .codec_dai_name = "tx_macro_tx1",
  6050. .no_pcm = 1,
  6051. .dpcm_capture = 1,
  6052. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
  6053. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6054. .ignore_suspend = 1,
  6055. .ops = &msm_cdc_dma_be_ops,
  6056. },
  6057. {
  6058. .name = LPASS_BE_TX_CDC_DMA_TX_4,
  6059. .stream_name = "TX CDC DMA4 Capture",
  6060. .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
  6061. .platform_name = "msm-pcm-routing",
  6062. .codec_name = "bolero_codec",
  6063. .codec_dai_name = "tx_macro_tx2",
  6064. .no_pcm = 1,
  6065. .dpcm_capture = 1,
  6066. .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
  6067. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6068. .ignore_suspend = 1,
  6069. .ops = &msm_cdc_dma_be_ops,
  6070. },
  6071. };
  6072. static struct snd_soc_dai_link msm_va_cdc_dma_be_dai_links[] = {
  6073. {
  6074. .name = LPASS_BE_VA_CDC_DMA_TX_0,
  6075. .stream_name = "VA CDC DMA0 Capture",
  6076. .cpu_dai_name = "msm-dai-cdc-dma-dev.45089",
  6077. .platform_name = "msm-pcm-routing",
  6078. .codec_name = "bolero_codec",
  6079. .codec_dai_name = "va_macro_tx1",
  6080. .no_pcm = 1,
  6081. .dpcm_capture = 1,
  6082. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_0,
  6083. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6084. .ignore_suspend = 1,
  6085. .ops = &msm_cdc_dma_be_ops,
  6086. },
  6087. {
  6088. .name = LPASS_BE_VA_CDC_DMA_TX_1,
  6089. .stream_name = "VA CDC DMA1 Capture",
  6090. .cpu_dai_name = "msm-dai-cdc-dma-dev.45091",
  6091. .platform_name = "msm-pcm-routing",
  6092. .codec_name = "bolero_codec",
  6093. .codec_dai_name = "va_macro_tx2",
  6094. .no_pcm = 1,
  6095. .dpcm_capture = 1,
  6096. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_1,
  6097. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6098. .ignore_suspend = 1,
  6099. .ops = &msm_cdc_dma_be_ops,
  6100. },
  6101. {
  6102. .name = LPASS_BE_VA_CDC_DMA_TX_2,
  6103. .stream_name = "VA CDC DMA2 Capture",
  6104. .cpu_dai_name = "msm-dai-cdc-dma-dev.45093",
  6105. .platform_name = "msm-pcm-routing",
  6106. .codec_name = "bolero_codec",
  6107. .codec_dai_name = "va_macro_tx3",
  6108. .no_pcm = 1,
  6109. .dpcm_capture = 1,
  6110. .id = MSM_BACKEND_DAI_VA_CDC_DMA_TX_2,
  6111. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6112. .ignore_suspend = 1,
  6113. .ops = &msm_cdc_dma_be_ops,
  6114. },
  6115. };
  6116. static struct snd_soc_dai_link msm_afe_rxtx_lb_be_dai_link[] = {
  6117. {
  6118. .name = LPASS_BE_AFE_LOOPBACK_TX,
  6119. .stream_name = "AFE Loopback Capture",
  6120. .cpu_dai_name = "msm-dai-q6-dev.24577",
  6121. .platform_name = "msm-pcm-routing",
  6122. .codec_name = "msm-stub-codec.1",
  6123. .codec_dai_name = "msm-stub-tx",
  6124. .no_pcm = 1,
  6125. .dpcm_capture = 1,
  6126. .id = MSM_BACKEND_DAI_AFE_LOOPBACK_TX,
  6127. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6128. .ignore_pmdown_time = 1,
  6129. .ignore_suspend = 1,
  6130. },
  6131. };
  6132. static struct snd_soc_dai_link msm_kona_dai_links[
  6133. ARRAY_SIZE(msm_common_dai_links) +
  6134. ARRAY_SIZE(msm_bolero_fe_dai_links) +
  6135. ARRAY_SIZE(msm_common_misc_fe_dai_links) +
  6136. ARRAY_SIZE(msm_common_be_dai_links) +
  6137. ARRAY_SIZE(msm_mi2s_be_dai_links) +
  6138. ARRAY_SIZE(msm_auxpcm_be_dai_links) +
  6139. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
  6140. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links) +
  6141. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
  6142. ARRAY_SIZE(ext_disp_be_dai_link) +
  6143. ARRAY_SIZE(msm_wcn_be_dai_links) +
  6144. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link) +
  6145. ARRAY_SIZE(msm_wcn_btfm_be_dai_links)];
  6146. static int msm_populate_dai_link_component_of_node(
  6147. struct snd_soc_card *card)
  6148. {
  6149. int i, index, ret = 0;
  6150. struct device *cdev = card->dev;
  6151. struct snd_soc_dai_link *dai_link = card->dai_link;
  6152. struct device_node *np;
  6153. if (!cdev) {
  6154. dev_err(cdev, "%s: Sound card device memory NULL\n", __func__);
  6155. return -ENODEV;
  6156. }
  6157. for (i = 0; i < card->num_links; i++) {
  6158. if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
  6159. continue;
  6160. /* populate platform_of_node for snd card dai links */
  6161. if (dai_link[i].platform_name &&
  6162. !dai_link[i].platform_of_node) {
  6163. index = of_property_match_string(cdev->of_node,
  6164. "asoc-platform-names",
  6165. dai_link[i].platform_name);
  6166. if (index < 0) {
  6167. dev_err(cdev, "%s: No match found for platform name: %s\n",
  6168. __func__, dai_link[i].platform_name);
  6169. ret = index;
  6170. goto err;
  6171. }
  6172. np = of_parse_phandle(cdev->of_node, "asoc-platform",
  6173. index);
  6174. if (!np) {
  6175. dev_err(cdev, "%s: retrieving phandle for platform %s, index %d failed\n",
  6176. __func__, dai_link[i].platform_name,
  6177. index);
  6178. ret = -ENODEV;
  6179. goto err;
  6180. }
  6181. dai_link[i].platform_of_node = np;
  6182. dai_link[i].platform_name = NULL;
  6183. }
  6184. /* populate cpu_of_node for snd card dai links */
  6185. if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
  6186. index = of_property_match_string(cdev->of_node,
  6187. "asoc-cpu-names",
  6188. dai_link[i].cpu_dai_name);
  6189. if (index >= 0) {
  6190. np = of_parse_phandle(cdev->of_node, "asoc-cpu",
  6191. index);
  6192. if (!np) {
  6193. dev_err(cdev, "%s: retrieving phandle for cpu dai %s failed\n",
  6194. __func__,
  6195. dai_link[i].cpu_dai_name);
  6196. ret = -ENODEV;
  6197. goto err;
  6198. }
  6199. dai_link[i].cpu_of_node = np;
  6200. dai_link[i].cpu_dai_name = NULL;
  6201. }
  6202. }
  6203. /* populate codec_of_node for snd card dai links */
  6204. if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
  6205. index = of_property_match_string(cdev->of_node,
  6206. "asoc-codec-names",
  6207. dai_link[i].codec_name);
  6208. if (index < 0)
  6209. continue;
  6210. np = of_parse_phandle(cdev->of_node, "asoc-codec",
  6211. index);
  6212. if (!np) {
  6213. dev_err(cdev, "%s: retrieving phandle for codec %s failed\n",
  6214. __func__, dai_link[i].codec_name);
  6215. ret = -ENODEV;
  6216. goto err;
  6217. }
  6218. dai_link[i].codec_of_node = np;
  6219. dai_link[i].codec_name = NULL;
  6220. }
  6221. }
  6222. err:
  6223. return ret;
  6224. }
  6225. static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
  6226. {
  6227. int ret = -EINVAL;
  6228. struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
  6229. if (!component) {
  6230. pr_err("* %s: No match for msm-stub-codec component\n", __func__);
  6231. return ret;
  6232. }
  6233. ret = snd_soc_add_component_controls(component, msm_snd_controls,
  6234. ARRAY_SIZE(msm_snd_controls));
  6235. if (ret < 0) {
  6236. dev_err(component->dev,
  6237. "%s: add_codec_controls failed, err = %d\n",
  6238. __func__, ret);
  6239. return ret;
  6240. }
  6241. return ret;
  6242. }
  6243. static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
  6244. struct snd_pcm_hw_params *params)
  6245. {
  6246. return 0;
  6247. }
  6248. static struct snd_soc_ops msm_stub_be_ops = {
  6249. .hw_params = msm_snd_stub_hw_params,
  6250. };
  6251. struct snd_soc_card snd_soc_card_stub_msm = {
  6252. .name = "kona-stub-snd-card",
  6253. };
  6254. static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
  6255. /* FrontEnd DAI Links */
  6256. {
  6257. .name = "MSMSTUB Media1",
  6258. .stream_name = "MultiMedia1",
  6259. .cpu_dai_name = "MultiMedia1",
  6260. .platform_name = "msm-pcm-dsp.0",
  6261. .dynamic = 1,
  6262. .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
  6263. .dpcm_playback = 1,
  6264. .dpcm_capture = 1,
  6265. .trigger = {SND_SOC_DPCM_TRIGGER_POST,
  6266. SND_SOC_DPCM_TRIGGER_POST},
  6267. .codec_dai_name = "snd-soc-dummy-dai",
  6268. .codec_name = "snd-soc-dummy",
  6269. .ignore_suspend = 1,
  6270. /* this dainlink has playback support */
  6271. .ignore_pmdown_time = 1,
  6272. .id = MSM_FRONTEND_DAI_MULTIMEDIA1
  6273. },
  6274. };
  6275. static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
  6276. /* Backend DAI Links */
  6277. {
  6278. .name = LPASS_BE_AUXPCM_RX,
  6279. .stream_name = "AUX PCM Playback",
  6280. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6281. .platform_name = "msm-pcm-routing",
  6282. .codec_name = "msm-stub-codec.1",
  6283. .codec_dai_name = "msm-stub-rx",
  6284. .no_pcm = 1,
  6285. .dpcm_playback = 1,
  6286. .id = MSM_BACKEND_DAI_AUXPCM_RX,
  6287. .init = &msm_audrx_stub_init,
  6288. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6289. .ignore_pmdown_time = 1,
  6290. .ignore_suspend = 1,
  6291. .ops = &msm_stub_be_ops,
  6292. },
  6293. {
  6294. .name = LPASS_BE_AUXPCM_TX,
  6295. .stream_name = "AUX PCM Capture",
  6296. .cpu_dai_name = "msm-dai-q6-auxpcm.1",
  6297. .platform_name = "msm-pcm-routing",
  6298. .codec_name = "msm-stub-codec.1",
  6299. .codec_dai_name = "msm-stub-tx",
  6300. .no_pcm = 1,
  6301. .dpcm_capture = 1,
  6302. .id = MSM_BACKEND_DAI_AUXPCM_TX,
  6303. .be_hw_params_fixup = msm_be_hw_params_fixup,
  6304. .ignore_suspend = 1,
  6305. .ops = &msm_stub_be_ops,
  6306. },
  6307. };
  6308. static struct snd_soc_dai_link msm_stub_dai_links[
  6309. ARRAY_SIZE(msm_stub_fe_dai_links) +
  6310. ARRAY_SIZE(msm_stub_be_dai_links)];
  6311. static const struct of_device_id kona_asoc_machine_of_match[] = {
  6312. { .compatible = "qcom,kona-asoc-snd",
  6313. .data = "codec"},
  6314. { .compatible = "qcom,kona-asoc-snd-stub",
  6315. .data = "stub_codec"},
  6316. {},
  6317. };
  6318. static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
  6319. {
  6320. struct snd_soc_card *card = NULL;
  6321. struct snd_soc_dai_link *dailink = NULL;
  6322. int len_1 = 0;
  6323. int len_2 = 0;
  6324. int total_links = 0;
  6325. int rc = 0;
  6326. u32 mi2s_audio_intf = 0;
  6327. u32 auxpcm_audio_intf = 0;
  6328. u32 val = 0;
  6329. u32 wcn_btfm_intf = 0;
  6330. const struct of_device_id *match;
  6331. match = of_match_node(kona_asoc_machine_of_match, dev->of_node);
  6332. if (!match) {
  6333. dev_err(dev, "%s: No DT match found for sound card\n",
  6334. __func__);
  6335. return NULL;
  6336. }
  6337. if (!strcmp(match->data, "codec")) {
  6338. card = &snd_soc_card_kona_msm;
  6339. memcpy(msm_kona_dai_links + total_links,
  6340. msm_common_dai_links,
  6341. sizeof(msm_common_dai_links));
  6342. total_links += ARRAY_SIZE(msm_common_dai_links);
  6343. memcpy(msm_kona_dai_links + total_links,
  6344. msm_bolero_fe_dai_links,
  6345. sizeof(msm_bolero_fe_dai_links));
  6346. total_links +=
  6347. ARRAY_SIZE(msm_bolero_fe_dai_links);
  6348. memcpy(msm_kona_dai_links + total_links,
  6349. msm_common_misc_fe_dai_links,
  6350. sizeof(msm_common_misc_fe_dai_links));
  6351. total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
  6352. memcpy(msm_kona_dai_links + total_links,
  6353. msm_common_be_dai_links,
  6354. sizeof(msm_common_be_dai_links));
  6355. total_links += ARRAY_SIZE(msm_common_be_dai_links);
  6356. memcpy(msm_kona_dai_links + total_links,
  6357. msm_wsa_cdc_dma_be_dai_links,
  6358. sizeof(msm_wsa_cdc_dma_be_dai_links));
  6359. total_links +=
  6360. ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
  6361. memcpy(msm_kona_dai_links + total_links,
  6362. msm_rx_tx_cdc_dma_be_dai_links,
  6363. sizeof(msm_rx_tx_cdc_dma_be_dai_links));
  6364. total_links +=
  6365. ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
  6366. memcpy(msm_kona_dai_links + total_links,
  6367. msm_va_cdc_dma_be_dai_links,
  6368. sizeof(msm_va_cdc_dma_be_dai_links));
  6369. total_links +=
  6370. ARRAY_SIZE(msm_va_cdc_dma_be_dai_links);
  6371. rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
  6372. &mi2s_audio_intf);
  6373. if (rc) {
  6374. dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
  6375. __func__);
  6376. } else {
  6377. if (mi2s_audio_intf) {
  6378. memcpy(msm_kona_dai_links + total_links,
  6379. msm_mi2s_be_dai_links,
  6380. sizeof(msm_mi2s_be_dai_links));
  6381. total_links +=
  6382. ARRAY_SIZE(msm_mi2s_be_dai_links);
  6383. }
  6384. }
  6385. rc = of_property_read_u32(dev->of_node,
  6386. "qcom,auxpcm-audio-intf",
  6387. &auxpcm_audio_intf);
  6388. if (rc) {
  6389. dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
  6390. __func__);
  6391. } else {
  6392. if (auxpcm_audio_intf) {
  6393. memcpy(msm_kona_dai_links + total_links,
  6394. msm_auxpcm_be_dai_links,
  6395. sizeof(msm_auxpcm_be_dai_links));
  6396. total_links +=
  6397. ARRAY_SIZE(msm_auxpcm_be_dai_links);
  6398. }
  6399. }
  6400. rc = of_property_read_u32(dev->of_node,
  6401. "qcom,ext-disp-audio-rx", &val);
  6402. if (!rc && val) {
  6403. dev_dbg(dev, "%s(): ext disp audio support present\n",
  6404. __func__);
  6405. memcpy(msm_kona_dai_links + total_links,
  6406. ext_disp_be_dai_link,
  6407. sizeof(ext_disp_be_dai_link));
  6408. total_links += ARRAY_SIZE(ext_disp_be_dai_link);
  6409. }
  6410. rc = of_property_read_u32(dev->of_node, "qcom,wcn-bt", &val);
  6411. if (!rc && val) {
  6412. dev_dbg(dev, "%s(): WCN BT support present\n",
  6413. __func__);
  6414. memcpy(msm_kona_dai_links + total_links,
  6415. msm_wcn_be_dai_links,
  6416. sizeof(msm_wcn_be_dai_links));
  6417. total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
  6418. }
  6419. rc = of_property_read_u32(dev->of_node, "qcom,afe-rxtx-lb",
  6420. &val);
  6421. if (!rc && val) {
  6422. memcpy(msm_kona_dai_links + total_links,
  6423. msm_afe_rxtx_lb_be_dai_link,
  6424. sizeof(msm_afe_rxtx_lb_be_dai_link));
  6425. total_links +=
  6426. ARRAY_SIZE(msm_afe_rxtx_lb_be_dai_link);
  6427. }
  6428. rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
  6429. &wcn_btfm_intf);
  6430. if (rc) {
  6431. dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
  6432. __func__);
  6433. } else {
  6434. if (wcn_btfm_intf) {
  6435. memcpy(msm_kona_dai_links + total_links,
  6436. msm_wcn_btfm_be_dai_links,
  6437. sizeof(msm_wcn_btfm_be_dai_links));
  6438. total_links +=
  6439. ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
  6440. }
  6441. }
  6442. dailink = msm_kona_dai_links;
  6443. } else if(!strcmp(match->data, "stub_codec")) {
  6444. card = &snd_soc_card_stub_msm;
  6445. len_1 = ARRAY_SIZE(msm_stub_fe_dai_links);
  6446. len_2 = len_1 + ARRAY_SIZE(msm_stub_be_dai_links);
  6447. memcpy(msm_stub_dai_links,
  6448. msm_stub_fe_dai_links,
  6449. sizeof(msm_stub_fe_dai_links));
  6450. memcpy(msm_stub_dai_links + len_1,
  6451. msm_stub_be_dai_links,
  6452. sizeof(msm_stub_be_dai_links));
  6453. dailink = msm_stub_dai_links;
  6454. total_links = len_2;
  6455. }
  6456. if (card) {
  6457. card->dai_link = dailink;
  6458. card->num_links = total_links;
  6459. }
  6460. return card;
  6461. }
  6462. static int msm_wsa881x_init(struct snd_soc_component *component)
  6463. {
  6464. u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6465. u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
  6466. u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
  6467. SPKR_L_BOOST, SPKR_L_VI};
  6468. u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
  6469. SPKR_R_BOOST, SPKR_R_VI};
  6470. unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
  6471. unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
  6472. struct msm_asoc_mach_data *pdata;
  6473. struct snd_soc_dapm_context *dapm;
  6474. struct snd_card *card;
  6475. struct snd_info_entry *entry;
  6476. int ret = 0;
  6477. if (!component) {
  6478. pr_err("%s component is NULL\n", __func__);
  6479. return -EINVAL;
  6480. }
  6481. card = component->card->snd_card;
  6482. dapm = snd_soc_component_get_dapm(component);
  6483. if (!strcmp(component->name_prefix, "SpkrLeft")) {
  6484. dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
  6485. __func__, component->name);
  6486. wsa881x_set_channel_map(component, &spkleft_ports[0],
  6487. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6488. &ch_rate[0], &spkleft_port_types[0]);
  6489. if (dapm->component) {
  6490. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
  6491. snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
  6492. }
  6493. } else if (!strcmp(component->name_prefix, "SpkrRight")) {
  6494. dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
  6495. __func__, component->name);
  6496. wsa881x_set_channel_map(component, &spkright_ports[0],
  6497. WSA881X_MAX_SWR_PORTS, &ch_mask[0],
  6498. &ch_rate[0], &spkright_port_types[0]);
  6499. if (dapm->component) {
  6500. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
  6501. snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
  6502. }
  6503. } else {
  6504. dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
  6505. component->name);
  6506. ret = -EINVAL;
  6507. goto err;
  6508. }
  6509. pdata = snd_soc_card_get_drvdata(component->card);
  6510. if (!pdata->codec_root) {
  6511. entry = snd_info_create_subdir(card->module, "codecs",
  6512. card->proc_root);
  6513. if (!entry) {
  6514. pr_err("%s: Cannot create codecs module entry\n",
  6515. __func__);
  6516. ret = 0;
  6517. goto err;
  6518. }
  6519. pdata->codec_root = entry;
  6520. }
  6521. wsa881x_codec_info_create_codec_entry(pdata->codec_root,
  6522. component);
  6523. err:
  6524. return ret;
  6525. }
  6526. static int msm_aux_codec_init(struct snd_soc_component *component)
  6527. {
  6528. struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
  6529. int ret = 0;
  6530. void *mbhc_calibration;
  6531. struct snd_info_entry *entry;
  6532. struct snd_card *card = component->card->snd_card;
  6533. struct msm_asoc_mach_data *pdata;
  6534. snd_soc_dapm_ignore_suspend(dapm, "EAR");
  6535. snd_soc_dapm_ignore_suspend(dapm, "AUX");
  6536. snd_soc_dapm_ignore_suspend(dapm, "HPHL");
  6537. snd_soc_dapm_ignore_suspend(dapm, "HPHR");
  6538. snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
  6539. snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
  6540. snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
  6541. snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
  6542. snd_soc_dapm_sync(dapm);
  6543. pdata = snd_soc_card_get_drvdata(component->card);
  6544. if (!pdata->codec_root) {
  6545. entry = snd_info_create_subdir(card->module, "codecs",
  6546. card->proc_root);
  6547. if (!entry) {
  6548. dev_dbg(component->dev, "%s: Cannot create codecs module entry\n",
  6549. __func__);
  6550. ret = 0;
  6551. goto mbhc_cfg_cal;
  6552. }
  6553. pdata->codec_root = entry;
  6554. }
  6555. wcd938x_info_create_codec_entry(pdata->codec_root, component);
  6556. mbhc_cfg_cal:
  6557. mbhc_calibration = def_wcd_mbhc_cal();
  6558. if (!mbhc_calibration)
  6559. return -ENOMEM;
  6560. wcd_mbhc_cfg.calibration = mbhc_calibration;
  6561. ret = wcd938x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
  6562. if (ret) {
  6563. dev_err(component->dev, "%s: mbhc hs detect failed, err:%d\n",
  6564. __func__, ret);
  6565. goto err_hs_detect;
  6566. }
  6567. return 0;
  6568. err_hs_detect:
  6569. kfree(mbhc_calibration);
  6570. return ret;
  6571. }
  6572. static int msm_init_aux_dev(struct platform_device *pdev,
  6573. struct snd_soc_card *card)
  6574. {
  6575. struct device_node *wsa_of_node;
  6576. struct device_node *aux_codec_of_node;
  6577. u32 wsa_max_devs;
  6578. u32 wsa_dev_cnt;
  6579. u32 codec_aux_dev_cnt = 0;
  6580. int i;
  6581. struct msm_wsa881x_dev_info *wsa881x_dev_info;
  6582. struct aux_codec_dev_info *aux_cdc_dev_info;
  6583. const char *auxdev_name_prefix[1];
  6584. char *dev_name_str = NULL;
  6585. int found = 0;
  6586. int codecs_found = 0;
  6587. int ret = 0;
  6588. /* Get maximum WSA device count for this platform */
  6589. ret = of_property_read_u32(pdev->dev.of_node,
  6590. "qcom,wsa-max-devs", &wsa_max_devs);
  6591. if (ret) {
  6592. dev_info(&pdev->dev,
  6593. "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
  6594. __func__, pdev->dev.of_node->full_name, ret);
  6595. wsa_max_devs = 0;
  6596. goto codec_aux_dev;
  6597. }
  6598. if (wsa_max_devs == 0) {
  6599. dev_warn(&pdev->dev,
  6600. "%s: Max WSA devices is 0 for this target?\n",
  6601. __func__);
  6602. goto codec_aux_dev;
  6603. }
  6604. /* Get count of WSA device phandles for this platform */
  6605. wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
  6606. "qcom,wsa-devs", NULL);
  6607. if (wsa_dev_cnt == -ENOENT) {
  6608. dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
  6609. __func__);
  6610. goto err;
  6611. } else if (wsa_dev_cnt <= 0) {
  6612. dev_err(&pdev->dev,
  6613. "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
  6614. __func__, wsa_dev_cnt);
  6615. ret = -EINVAL;
  6616. goto err;
  6617. }
  6618. /*
  6619. * Expect total phandles count to be NOT less than maximum possible
  6620. * WSA count. However, if it is less, then assign same value to
  6621. * max count as well.
  6622. */
  6623. if (wsa_dev_cnt < wsa_max_devs) {
  6624. dev_dbg(&pdev->dev,
  6625. "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
  6626. __func__, wsa_max_devs, wsa_dev_cnt);
  6627. wsa_max_devs = wsa_dev_cnt;
  6628. }
  6629. /* Make sure prefix string passed for each WSA device */
  6630. ret = of_property_count_strings(pdev->dev.of_node,
  6631. "qcom,wsa-aux-dev-prefix");
  6632. if (ret != wsa_dev_cnt) {
  6633. dev_err(&pdev->dev,
  6634. "%s: expecting %d wsa prefix. Defined only %d in DT\n",
  6635. __func__, wsa_dev_cnt, ret);
  6636. ret = -EINVAL;
  6637. goto err;
  6638. }
  6639. /*
  6640. * Alloc mem to store phandle and index info of WSA device, if already
  6641. * registered with ALSA core
  6642. */
  6643. wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
  6644. sizeof(struct msm_wsa881x_dev_info),
  6645. GFP_KERNEL);
  6646. if (!wsa881x_dev_info) {
  6647. ret = -ENOMEM;
  6648. goto err;
  6649. }
  6650. /*
  6651. * search and check whether all WSA devices are already
  6652. * registered with ALSA core or not. If found a node, store
  6653. * the node and the index in a local array of struct for later
  6654. * use.
  6655. */
  6656. for (i = 0; i < wsa_dev_cnt; i++) {
  6657. wsa_of_node = of_parse_phandle(pdev->dev.of_node,
  6658. "qcom,wsa-devs", i);
  6659. if (unlikely(!wsa_of_node)) {
  6660. /* we should not be here */
  6661. dev_err(&pdev->dev,
  6662. "%s: wsa dev node is not present\n",
  6663. __func__);
  6664. ret = -EINVAL;
  6665. goto err;
  6666. }
  6667. if (soc_find_component(wsa_of_node, NULL)) {
  6668. /* WSA device registered with ALSA core */
  6669. wsa881x_dev_info[found].of_node = wsa_of_node;
  6670. wsa881x_dev_info[found].index = i;
  6671. found++;
  6672. if (found == wsa_max_devs)
  6673. break;
  6674. }
  6675. }
  6676. if (found < wsa_max_devs) {
  6677. dev_dbg(&pdev->dev,
  6678. "%s: failed to find %d components. Found only %d\n",
  6679. __func__, wsa_max_devs, found);
  6680. return -EPROBE_DEFER;
  6681. }
  6682. dev_info(&pdev->dev,
  6683. "%s: found %d wsa881x devices registered with ALSA core\n",
  6684. __func__, found);
  6685. codec_aux_dev:
  6686. /* Get count of aux codec device phandles for this platform */
  6687. codec_aux_dev_cnt = of_count_phandle_with_args(
  6688. pdev->dev.of_node,
  6689. "qcom,codec-aux-devs", NULL);
  6690. if (codec_aux_dev_cnt == -ENOENT) {
  6691. dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
  6692. __func__);
  6693. goto err;
  6694. } else if (codec_aux_dev_cnt <= 0) {
  6695. dev_err(&pdev->dev,
  6696. "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
  6697. __func__, codec_aux_dev_cnt);
  6698. ret = -EINVAL;
  6699. goto err;
  6700. }
  6701. /*
  6702. * Alloc mem to store phandle and index info of aux codec
  6703. * if already registered with ALSA core
  6704. */
  6705. aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_aux_dev_cnt,
  6706. sizeof(struct aux_codec_dev_info),
  6707. GFP_KERNEL);
  6708. if (!aux_cdc_dev_info) {
  6709. ret = -ENOMEM;
  6710. goto err;
  6711. }
  6712. /*
  6713. * search and check whether all aux codecs are already
  6714. * registered with ALSA core or not. If found a node, store
  6715. * the node and the index in a local array of struct for later
  6716. * use.
  6717. */
  6718. for (i = 0; i < codec_aux_dev_cnt; i++) {
  6719. aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
  6720. "qcom,codec-aux-devs", i);
  6721. if (unlikely(!aux_codec_of_node)) {
  6722. /* we should not be here */
  6723. dev_err(&pdev->dev,
  6724. "%s: aux codec dev node is not present\n",
  6725. __func__);
  6726. ret = -EINVAL;
  6727. goto err;
  6728. }
  6729. if (soc_find_component(aux_codec_of_node, NULL)) {
  6730. /* AUX codec registered with ALSA core */
  6731. aux_cdc_dev_info[codecs_found].of_node =
  6732. aux_codec_of_node;
  6733. aux_cdc_dev_info[codecs_found].index = i;
  6734. codecs_found++;
  6735. }
  6736. }
  6737. if (codecs_found < codec_aux_dev_cnt) {
  6738. dev_dbg(&pdev->dev,
  6739. "%s: failed to find %d components. Found only %d\n",
  6740. __func__, codec_aux_dev_cnt, codecs_found);
  6741. return -EPROBE_DEFER;
  6742. }
  6743. dev_info(&pdev->dev,
  6744. "%s: found %d AUX codecs registered with ALSA core\n",
  6745. __func__, codecs_found);
  6746. card->num_aux_devs = wsa_max_devs + codec_aux_dev_cnt;
  6747. card->num_configs = wsa_max_devs + codec_aux_dev_cnt;
  6748. /* Alloc array of AUX devs struct */
  6749. msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
  6750. sizeof(struct snd_soc_aux_dev),
  6751. GFP_KERNEL);
  6752. if (!msm_aux_dev) {
  6753. ret = -ENOMEM;
  6754. goto err;
  6755. }
  6756. /* Alloc array of codec conf struct */
  6757. msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
  6758. sizeof(struct snd_soc_codec_conf),
  6759. GFP_KERNEL);
  6760. if (!msm_codec_conf) {
  6761. ret = -ENOMEM;
  6762. goto err;
  6763. }
  6764. for (i = 0; i < wsa_max_devs; i++) {
  6765. dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
  6766. GFP_KERNEL);
  6767. if (!dev_name_str) {
  6768. ret = -ENOMEM;
  6769. goto err;
  6770. }
  6771. ret = of_property_read_string_index(pdev->dev.of_node,
  6772. "qcom,wsa-aux-dev-prefix",
  6773. wsa881x_dev_info[i].index,
  6774. auxdev_name_prefix);
  6775. if (ret) {
  6776. dev_err(&pdev->dev,
  6777. "%s: failed to read wsa aux dev prefix, ret = %d\n",
  6778. __func__, ret);
  6779. ret = -EINVAL;
  6780. goto err;
  6781. }
  6782. snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
  6783. msm_aux_dev[i].name = dev_name_str;
  6784. msm_aux_dev[i].codec_name = NULL;
  6785. msm_aux_dev[i].codec_of_node =
  6786. wsa881x_dev_info[i].of_node;
  6787. msm_aux_dev[i].init = msm_wsa881x_init;
  6788. msm_codec_conf[i].dev_name = NULL;
  6789. msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
  6790. msm_codec_conf[i].of_node =
  6791. wsa881x_dev_info[i].of_node;
  6792. }
  6793. for (i = 0; i < codec_aux_dev_cnt; i++) {
  6794. msm_aux_dev[wsa_max_devs + i].name = NULL;
  6795. msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
  6796. msm_aux_dev[wsa_max_devs + i].codec_of_node =
  6797. aux_cdc_dev_info[i].of_node;
  6798. msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
  6799. msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
  6800. msm_codec_conf[wsa_max_devs + i].name_prefix =
  6801. NULL;
  6802. msm_codec_conf[wsa_max_devs + i].of_node =
  6803. aux_cdc_dev_info[i].of_node;
  6804. }
  6805. card->codec_conf = msm_codec_conf;
  6806. card->aux_dev = msm_aux_dev;
  6807. err:
  6808. return ret;
  6809. }
  6810. static void msm_i2s_auxpcm_init(struct platform_device *pdev)
  6811. {
  6812. int count = 0;
  6813. u32 mi2s_master_slave[MI2S_MAX];
  6814. int ret = 0;
  6815. for (count = 0; count < MI2S_MAX; count++) {
  6816. mutex_init(&mi2s_intf_conf[count].lock);
  6817. mi2s_intf_conf[count].ref_cnt = 0;
  6818. }
  6819. ret = of_property_read_u32_array(pdev->dev.of_node,
  6820. "qcom,msm-mi2s-master",
  6821. mi2s_master_slave, MI2S_MAX);
  6822. if (ret) {
  6823. dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
  6824. __func__);
  6825. } else {
  6826. for (count = 0; count < MI2S_MAX; count++) {
  6827. mi2s_intf_conf[count].msm_is_mi2s_master =
  6828. mi2s_master_slave[count];
  6829. }
  6830. }
  6831. }
  6832. static void msm_i2s_auxpcm_deinit(void)
  6833. {
  6834. int count = 0;
  6835. for (count = 0; count < MI2S_MAX; count++) {
  6836. mutex_destroy(&mi2s_intf_conf[count].lock);
  6837. mi2s_intf_conf[count].ref_cnt = 0;
  6838. mi2s_intf_conf[count].msm_is_mi2s_master = 0;
  6839. }
  6840. }
  6841. static int kona_ssr_enable(struct device *dev, void *data)
  6842. {
  6843. struct platform_device *pdev = to_platform_device(dev);
  6844. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6845. int ret = 0;
  6846. if (!card) {
  6847. dev_err(dev, "%s: card is NULL\n", __func__);
  6848. ret = -EINVAL;
  6849. goto err;
  6850. }
  6851. if (!strcmp(card->name, "kona-stub-snd-card")) {
  6852. /* TODO */
  6853. dev_dbg(dev, "%s: TODO \n", __func__);
  6854. }
  6855. snd_soc_card_change_online_state(card, 1);
  6856. dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
  6857. err:
  6858. return ret;
  6859. }
  6860. static void kona_ssr_disable(struct device *dev, void *data)
  6861. {
  6862. struct platform_device *pdev = to_platform_device(dev);
  6863. struct snd_soc_card *card = platform_get_drvdata(pdev);
  6864. if (!card) {
  6865. dev_err(dev, "%s: card is NULL\n", __func__);
  6866. return;
  6867. }
  6868. dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
  6869. snd_soc_card_change_online_state(card, 0);
  6870. if (!strcmp(card->name, "kona-stub-snd-card")) {
  6871. /* TODO */
  6872. dev_dbg(dev, "%s: TODO \n", __func__);
  6873. }
  6874. }
  6875. static const struct snd_event_ops kona_ssr_ops = {
  6876. .enable = kona_ssr_enable,
  6877. .disable = kona_ssr_disable,
  6878. };
  6879. static int msm_audio_ssr_compare(struct device *dev, void *data)
  6880. {
  6881. struct device_node *node = data;
  6882. dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
  6883. __func__, dev->of_node, node);
  6884. return (dev->of_node && dev->of_node == node);
  6885. }
  6886. static int msm_audio_ssr_register(struct device *dev)
  6887. {
  6888. struct device_node *np = dev->of_node;
  6889. struct snd_event_clients *ssr_clients = NULL;
  6890. struct device_node *node = NULL;
  6891. int ret = 0;
  6892. int i = 0;
  6893. for (i = 0; ; i++) {
  6894. node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
  6895. if (!node)
  6896. break;
  6897. snd_event_mstr_add_client(&ssr_clients,
  6898. msm_audio_ssr_compare, node);
  6899. }
  6900. ret = snd_event_master_register(dev, &kona_ssr_ops,
  6901. ssr_clients, NULL);
  6902. if (!ret)
  6903. snd_event_notify(dev, SND_EVENT_UP);
  6904. return ret;
  6905. }
  6906. static int msm_asoc_machine_probe(struct platform_device *pdev)
  6907. {
  6908. struct snd_soc_card *card = NULL;
  6909. struct msm_asoc_mach_data *pdata = NULL;
  6910. const char *mbhc_audio_jack_type = NULL;
  6911. int ret = 0;
  6912. uint index = 0;
  6913. if (!pdev->dev.of_node) {
  6914. dev_err(&pdev->dev, "%s: No platform supplied from device tree\n", __func__);
  6915. return -EINVAL;
  6916. }
  6917. pdata = devm_kzalloc(&pdev->dev,
  6918. sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
  6919. if (!pdata)
  6920. return -ENOMEM;
  6921. card = populate_snd_card_dailinks(&pdev->dev);
  6922. if (!card) {
  6923. dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
  6924. ret = -EINVAL;
  6925. goto err;
  6926. }
  6927. card->dev = &pdev->dev;
  6928. platform_set_drvdata(pdev, card);
  6929. snd_soc_card_set_drvdata(card, pdata);
  6930. ret = snd_soc_of_parse_card_name(card, "qcom,model");
  6931. if (ret) {
  6932. dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
  6933. __func__, ret);
  6934. goto err;
  6935. }
  6936. ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
  6937. if (ret) {
  6938. dev_err(&pdev->dev, "%s: parse audio routing failed, err:%d\n",
  6939. __func__, ret);
  6940. goto err;
  6941. }
  6942. ret = msm_populate_dai_link_component_of_node(card);
  6943. if (ret) {
  6944. ret = -EPROBE_DEFER;
  6945. goto err;
  6946. }
  6947. ret = msm_init_aux_dev(pdev, card);
  6948. if (ret)
  6949. goto err;
  6950. ret = devm_snd_soc_register_card(&pdev->dev, card);
  6951. if (ret == -EPROBE_DEFER) {
  6952. if (codec_reg_done)
  6953. ret = -EINVAL;
  6954. goto err;
  6955. } else if (ret) {
  6956. dev_err(&pdev->dev, "%s: snd_soc_register_card failed (%d)\n",
  6957. __func__, ret);
  6958. goto err;
  6959. }
  6960. dev_info(&pdev->dev, "%s: Sound card %s registered\n",
  6961. __func__, card->name);
  6962. pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6963. "qcom,hph-en1-gpio", 0);
  6964. if (!pdata->hph_en1_gpio_p) {
  6965. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6966. __func__, "qcom,hph-en1-gpio",
  6967. pdev->dev.of_node->full_name);
  6968. }
  6969. pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
  6970. "qcom,hph-en0-gpio", 0);
  6971. if (!pdata->hph_en0_gpio_p) {
  6972. dev_dbg(&pdev->dev, "%s: property %s not detected in node %s\n",
  6973. __func__, "qcom,hph-en0-gpio",
  6974. pdev->dev.of_node->full_name);
  6975. }
  6976. ret = of_property_read_string(pdev->dev.of_node,
  6977. "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
  6978. if (ret) {
  6979. dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
  6980. __func__, "qcom,mbhc-audio-jack-type",
  6981. pdev->dev.of_node->full_name);
  6982. dev_dbg(&pdev->dev, "Jack type properties set to default\n");
  6983. } else {
  6984. if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
  6985. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6986. dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
  6987. } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
  6988. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6989. dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
  6990. } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
  6991. wcd_mbhc_cfg.enable_anc_mic_detect = true;
  6992. dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
  6993. } else {
  6994. wcd_mbhc_cfg.enable_anc_mic_detect = false;
  6995. dev_dbg(&pdev->dev, "Unknown value, set to default\n");
  6996. }
  6997. }
  6998. /*
  6999. * Parse US-Euro gpio info from DT. Report no error if us-euro
  7000. * entry is not found in DT file as some targets do not support
  7001. * US-Euro detection
  7002. */
  7003. pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7004. "qcom,us-euro-gpios", 0);
  7005. if (!pdata->us_euro_gpio_p) {
  7006. dev_dbg(&pdev->dev, "property %s not detected in node %s",
  7007. "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
  7008. } else {
  7009. dev_dbg(&pdev->dev, "%s detected\n",
  7010. "qcom,us-euro-gpios");
  7011. wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
  7012. }
  7013. if (wcd_mbhc_cfg.enable_usbc_analog)
  7014. wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
  7015. pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
  7016. "fsa4480-i2c-handle", 0);
  7017. if (!pdata->fsa_handle)
  7018. dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
  7019. "fsa4480-i2c-handle", pdev->dev.of_node->full_name);
  7020. msm_i2s_auxpcm_init(pdev);
  7021. pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7022. "qcom,cdc-dmic01-gpios",
  7023. 0);
  7024. pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7025. "qcom,cdc-dmic23-gpios",
  7026. 0);
  7027. pdata->dmic45_gpio_p = of_parse_phandle(pdev->dev.of_node,
  7028. "qcom,cdc-dmic45-gpios",
  7029. 0);
  7030. pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7031. "qcom,pri-mi2s-gpios", 0);
  7032. pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7033. "qcom,sec-mi2s-gpios", 0);
  7034. pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7035. "qcom,tert-mi2s-gpios", 0);
  7036. pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7037. "qcom,quat-mi2s-gpios", 0);
  7038. pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7039. "qcom,quin-mi2s-gpios", 0);
  7040. pdata->mi2s_gpio_p[SEN_MI2S] = of_parse_phandle(pdev->dev.of_node,
  7041. "qcom,sen-mi2s-gpios", 0);
  7042. for (index = PRIM_MI2S; index < MI2S_MAX; index++)
  7043. atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0);
  7044. ret = msm_audio_ssr_register(&pdev->dev);
  7045. if (ret)
  7046. pr_err("%s: Registration with SND event FWK failed ret = %d\n",
  7047. __func__, ret);
  7048. is_initial_boot = true;
  7049. return 0;
  7050. err:
  7051. devm_kfree(&pdev->dev, pdata);
  7052. return ret;
  7053. }
  7054. static int msm_asoc_machine_remove(struct platform_device *pdev)
  7055. {
  7056. struct snd_soc_card *card = platform_get_drvdata(pdev);
  7057. snd_event_master_deregister(&pdev->dev);
  7058. snd_soc_unregister_card(card);
  7059. msm_i2s_auxpcm_deinit();
  7060. return 0;
  7061. }
  7062. static struct platform_driver kona_asoc_machine_driver = {
  7063. .driver = {
  7064. .name = DRV_NAME,
  7065. .owner = THIS_MODULE,
  7066. .pm = &snd_soc_pm_ops,
  7067. .of_match_table = kona_asoc_machine_of_match,
  7068. .suppress_bind_attrs = true,
  7069. },
  7070. .probe = msm_asoc_machine_probe,
  7071. .remove = msm_asoc_machine_remove,
  7072. };
  7073. module_platform_driver(kona_asoc_machine_driver);
  7074. MODULE_DESCRIPTION("ALSA SoC msm");
  7075. MODULE_LICENSE("GPL v2");
  7076. MODULE_ALIAS("platform:" DRV_NAME);
  7077. MODULE_DEVICE_TABLE(of, kona_asoc_machine_of_match);